1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 #include "tcam.h" 47 #include "tcflower.h" 48 49 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 50 { 51 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 52 dev_err(chip->dev, "Switch registers lock not held!\n"); 53 dump_stack(); 54 } 55 } 56 57 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 58 { 59 int err; 60 61 assert_reg_lock(chip); 62 63 err = mv88e6xxx_smi_read(chip, addr, reg, val); 64 if (err) 65 return err; 66 67 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 68 addr, reg, *val); 69 70 return 0; 71 } 72 73 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 74 { 75 int err; 76 77 assert_reg_lock(chip); 78 79 err = mv88e6xxx_smi_write(chip, addr, reg, val); 80 if (err) 81 return err; 82 83 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 84 addr, reg, val); 85 86 return 0; 87 } 88 89 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 90 u16 mask, u16 val) 91 { 92 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 93 u16 data; 94 int err; 95 int i; 96 97 /* There's no bus specific operation to wait for a mask. Even 98 * if the initial poll takes longer than 50ms, always do at 99 * least one more attempt. 100 */ 101 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 102 err = mv88e6xxx_read(chip, addr, reg, &data); 103 if (err) 104 return err; 105 106 if ((data & mask) == val) 107 return 0; 108 109 if (i < 2) 110 cpu_relax(); 111 else 112 usleep_range(1000, 2000); 113 } 114 115 err = mv88e6xxx_read(chip, addr, reg, &data); 116 if (err) 117 return err; 118 119 if ((data & mask) == val) 120 return 0; 121 122 dev_err(chip->dev, "Timeout while waiting for switch\n"); 123 return -ETIMEDOUT; 124 } 125 126 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 127 int bit, int val) 128 { 129 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 130 val ? BIT(bit) : 0x0000); 131 } 132 133 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 134 { 135 struct mv88e6xxx_mdio_bus *mdio_bus; 136 137 mdio_bus = list_first_entry_or_null(&chip->mdios, 138 struct mv88e6xxx_mdio_bus, list); 139 if (!mdio_bus) 140 return NULL; 141 142 return mdio_bus->bus; 143 } 144 145 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 146 { 147 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 148 unsigned int n = d->hwirq; 149 150 chip->g1_irq.masked |= (1 << n); 151 } 152 153 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 154 { 155 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 156 unsigned int n = d->hwirq; 157 158 chip->g1_irq.masked &= ~(1 << n); 159 } 160 161 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 162 { 163 unsigned int nhandled = 0; 164 unsigned int sub_irq; 165 unsigned int n; 166 u16 reg; 167 u16 ctl1; 168 int err; 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 172 mv88e6xxx_reg_unlock(chip); 173 174 if (err) 175 goto out; 176 177 do { 178 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 179 if (reg & (1 << n)) { 180 sub_irq = irq_find_mapping(chip->g1_irq.domain, 181 n); 182 handle_nested_irq(sub_irq); 183 ++nhandled; 184 } 185 } 186 187 mv88e6xxx_reg_lock(chip); 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 189 if (err) 190 goto unlock; 191 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 192 unlock: 193 mv88e6xxx_reg_unlock(chip); 194 if (err) 195 goto out; 196 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 197 } while (reg & ctl1); 198 199 out: 200 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 201 } 202 203 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 204 { 205 struct mv88e6xxx_chip *chip = dev_id; 206 207 return mv88e6xxx_g1_irq_thread_work(chip); 208 } 209 210 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 211 { 212 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 213 214 mv88e6xxx_reg_lock(chip); 215 } 216 217 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 218 { 219 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 220 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 221 u16 reg; 222 int err; 223 224 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 225 if (err) 226 goto out; 227 228 reg &= ~mask; 229 reg |= (~chip->g1_irq.masked & mask); 230 231 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 232 if (err) 233 goto out; 234 235 out: 236 mv88e6xxx_reg_unlock(chip); 237 } 238 239 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 240 .name = "mv88e6xxx-g1", 241 .irq_mask = mv88e6xxx_g1_irq_mask, 242 .irq_unmask = mv88e6xxx_g1_irq_unmask, 243 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 244 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 245 }; 246 247 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 248 unsigned int irq, 249 irq_hw_number_t hwirq) 250 { 251 struct mv88e6xxx_chip *chip = d->host_data; 252 253 irq_set_chip_data(irq, d->host_data); 254 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 255 irq_set_noprobe(irq); 256 257 return 0; 258 } 259 260 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 261 .map = mv88e6xxx_g1_irq_domain_map, 262 .xlate = irq_domain_xlate_twocell, 263 }; 264 265 /* To be called with reg_lock held */ 266 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 267 { 268 int irq, virq; 269 u16 mask; 270 271 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 272 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 273 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 274 275 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 276 virq = irq_find_mapping(chip->g1_irq.domain, irq); 277 irq_dispose_mapping(virq); 278 } 279 280 irq_domain_remove(chip->g1_irq.domain); 281 } 282 283 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 284 { 285 /* 286 * free_irq must be called without reg_lock taken because the irq 287 * handler takes this lock, too. 288 */ 289 free_irq(chip->irq, chip); 290 291 mv88e6xxx_reg_lock(chip); 292 mv88e6xxx_g1_irq_free_common(chip); 293 mv88e6xxx_reg_unlock(chip); 294 } 295 296 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 297 { 298 int err, irq, virq; 299 u16 reg, mask; 300 301 chip->g1_irq.nirqs = chip->info->g1_irqs; 302 chip->g1_irq.domain = irq_domain_create_simple( 303 NULL, chip->g1_irq.nirqs, 0, 304 &mv88e6xxx_g1_irq_domain_ops, chip); 305 if (!chip->g1_irq.domain) 306 return -ENOMEM; 307 308 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 309 irq_create_mapping(chip->g1_irq.domain, irq); 310 311 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 312 chip->g1_irq.masked = ~0; 313 314 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 315 if (err) 316 goto out_mapping; 317 318 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 319 320 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 321 if (err) 322 goto out_disable; 323 324 /* Reading the interrupt status clears (most of) them */ 325 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 326 if (err) 327 goto out_disable; 328 329 return 0; 330 331 out_disable: 332 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 333 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 334 335 out_mapping: 336 for (irq = 0; irq < 16; irq++) { 337 virq = irq_find_mapping(chip->g1_irq.domain, irq); 338 irq_dispose_mapping(virq); 339 } 340 341 irq_domain_remove(chip->g1_irq.domain); 342 343 return err; 344 } 345 346 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 347 { 348 static struct lock_class_key lock_key; 349 static struct lock_class_key request_key; 350 int err; 351 352 err = mv88e6xxx_g1_irq_setup_common(chip); 353 if (err) 354 return err; 355 356 /* These lock classes tells lockdep that global 1 irqs are in 357 * a different category than their parent GPIO, so it won't 358 * report false recursion. 359 */ 360 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 361 362 snprintf(chip->irq_name, sizeof(chip->irq_name), 363 "mv88e6xxx-%s", dev_name(chip->dev)); 364 365 mv88e6xxx_reg_unlock(chip); 366 err = request_threaded_irq(chip->irq, NULL, 367 mv88e6xxx_g1_irq_thread_fn, 368 IRQF_ONESHOT | IRQF_SHARED, 369 chip->irq_name, chip); 370 mv88e6xxx_reg_lock(chip); 371 if (err) 372 mv88e6xxx_g1_irq_free_common(chip); 373 374 return err; 375 } 376 377 static void mv88e6xxx_irq_poll(struct kthread_work *work) 378 { 379 struct mv88e6xxx_chip *chip = container_of(work, 380 struct mv88e6xxx_chip, 381 irq_poll_work.work); 382 mv88e6xxx_g1_irq_thread_work(chip); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 } 387 388 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 389 { 390 int err; 391 392 err = mv88e6xxx_g1_irq_setup_common(chip); 393 if (err) 394 return err; 395 396 kthread_init_delayed_work(&chip->irq_poll_work, 397 mv88e6xxx_irq_poll); 398 399 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev)); 400 if (IS_ERR(chip->kworker)) 401 return PTR_ERR(chip->kworker); 402 403 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 404 msecs_to_jiffies(100)); 405 406 return 0; 407 } 408 409 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 410 { 411 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 412 kthread_destroy_worker(chip->kworker); 413 414 mv88e6xxx_reg_lock(chip); 415 mv88e6xxx_g1_irq_free_common(chip); 416 mv88e6xxx_reg_unlock(chip); 417 } 418 419 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 420 int port, phy_interface_t interface) 421 { 422 int err; 423 424 if (chip->info->ops->port_set_rgmii_delay) { 425 err = chip->info->ops->port_set_rgmii_delay(chip, port, 426 interface); 427 if (err && err != -EOPNOTSUPP) 428 return err; 429 } 430 431 if (chip->info->ops->port_set_cmode) { 432 err = chip->info->ops->port_set_cmode(chip, port, 433 interface); 434 if (err && err != -EOPNOTSUPP) 435 return err; 436 } 437 438 return 0; 439 } 440 441 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 442 int link, int speed, int duplex, int pause, 443 phy_interface_t mode) 444 { 445 int err; 446 447 if (!chip->info->ops->port_set_link) 448 return 0; 449 450 /* Port's MAC control must not be changed unless the link is down */ 451 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 452 if (err) 453 return err; 454 455 if (chip->info->ops->port_set_speed_duplex) { 456 err = chip->info->ops->port_set_speed_duplex(chip, port, 457 speed, duplex); 458 if (err && err != -EOPNOTSUPP) 459 goto restore_link; 460 } 461 462 if (chip->info->ops->port_set_pause) { 463 err = chip->info->ops->port_set_pause(chip, port, pause); 464 if (err) 465 goto restore_link; 466 } 467 468 err = mv88e6xxx_port_config_interface(chip, port, mode); 469 restore_link: 470 if (chip->info->ops->port_set_link(chip, port, link)) 471 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 472 473 return err; 474 } 475 476 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 477 { 478 return port >= chip->info->internal_phys_offset && 479 port < chip->info->num_internal_phys + 480 chip->info->internal_phys_offset; 481 } 482 483 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 484 { 485 u16 reg; 486 int err; 487 488 /* The 88e6250 family does not have the PHY detect bit. Instead, 489 * report whether the port is internal. 490 */ 491 if (chip->info->family == MV88E6XXX_FAMILY_6250) 492 return mv88e6xxx_phy_is_internal(chip, port); 493 494 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 495 if (err) { 496 dev_err(chip->dev, 497 "p%d: %s: failed to read port status\n", 498 port, __func__); 499 return err; 500 } 501 502 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 503 } 504 505 static const u8 mv88e6185_phy_interface_modes[] = { 506 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 507 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 509 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 510 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 511 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 512 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 513 }; 514 515 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 516 struct phylink_config *config) 517 { 518 u8 cmode = chip->ports[port].cmode; 519 520 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 521 522 if (mv88e6xxx_phy_is_internal(chip, port)) { 523 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 524 } else { 525 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 526 mv88e6185_phy_interface_modes[cmode]) 527 __set_bit(mv88e6185_phy_interface_modes[cmode], 528 config->supported_interfaces); 529 530 config->mac_capabilities |= MAC_1000FD; 531 } 532 } 533 534 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 535 struct phylink_config *config) 536 { 537 u8 cmode = chip->ports[port].cmode; 538 539 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 540 mv88e6185_phy_interface_modes[cmode]) 541 __set_bit(mv88e6185_phy_interface_modes[cmode], 542 config->supported_interfaces); 543 544 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 545 MAC_1000FD; 546 } 547 548 static const u8 mv88e6xxx_phy_interface_modes[] = { 549 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 550 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 551 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 552 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 553 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 554 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 555 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 556 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 557 /* higher interface modes are not needed here, since ports supporting 558 * them are writable, and so the supported interfaces are filled in the 559 * corresponding .phylink_set_interfaces() implementation below 560 */ 561 }; 562 563 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 564 { 565 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 566 mv88e6xxx_phy_interface_modes[cmode]) 567 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 568 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 569 phy_interface_set_rgmii(supported); 570 } 571 572 static void 573 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 574 struct phylink_config *config) 575 { 576 unsigned long *supported = config->supported_interfaces; 577 int err; 578 u16 reg; 579 580 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 581 if (err) { 582 dev_err(chip->dev, "p%d: failed to read port status\n", port); 583 return; 584 } 585 586 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 589 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 590 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 591 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 592 break; 593 594 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 595 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 596 __set_bit(PHY_INTERFACE_MODE_MII, supported); 597 break; 598 599 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 601 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 602 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 603 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 604 break; 605 606 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 607 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 608 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 609 break; 610 611 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 612 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 613 break; 614 615 default: 616 dev_err(chip->dev, 617 "p%d: invalid port mode in status register: %04x\n", 618 port, reg); 619 } 620 } 621 622 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 623 struct phylink_config *config) 624 { 625 if (!mv88e6xxx_phy_is_internal(chip, port)) 626 mv88e6250_setup_supported_interfaces(chip, port, config); 627 628 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 629 } 630 631 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 632 struct phylink_config *config) 633 { 634 unsigned long *supported = config->supported_interfaces; 635 636 /* Translate the default cmode */ 637 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 638 639 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 640 MAC_1000FD; 641 } 642 643 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 644 { 645 u16 reg, val; 646 int err; 647 648 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 649 if (err) 650 return err; 651 652 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 653 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 654 return 0xf; 655 656 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 657 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 658 if (err) 659 return err; 660 661 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 662 if (err) 663 return err; 664 665 /* Restore PHY_DETECT value */ 666 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 667 if (err) 668 return err; 669 670 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 671 } 672 673 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 674 struct phylink_config *config) 675 { 676 unsigned long *supported = config->supported_interfaces; 677 int err, cmode; 678 679 /* Translate the default cmode */ 680 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 681 682 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 683 MAC_1000FD; 684 685 /* Port 4 supports automedia if the serdes is associated with it. */ 686 if (port == 4) { 687 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 688 if (err <= 0) 689 return; 690 691 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 692 if (cmode < 0) 693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 694 port); 695 else 696 mv88e6xxx_translate_cmode(cmode, supported); 697 } 698 } 699 700 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 701 struct phylink_config *config) 702 { 703 unsigned long *supported = config->supported_interfaces; 704 int cmode; 705 706 /* Translate the default cmode */ 707 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 708 709 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 710 MAC_1000FD; 711 712 /* Port 0/1 are serdes only ports */ 713 if (port == 0 || port == 1) { 714 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 715 if (cmode < 0) 716 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 717 port); 718 else 719 mv88e6xxx_translate_cmode(cmode, supported); 720 } 721 } 722 723 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 724 struct phylink_config *config) 725 { 726 unsigned long *supported = config->supported_interfaces; 727 728 /* Translate the default cmode */ 729 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 730 731 /* No ethtool bits for 200Mbps */ 732 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 733 MAC_1000FD; 734 735 /* The C_Mode field is programmable on port 5 */ 736 if (port == 5) { 737 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 738 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 739 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 740 741 config->mac_capabilities |= MAC_2500FD; 742 } 743 } 744 745 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 746 struct phylink_config *config) 747 { 748 unsigned long *supported = config->supported_interfaces; 749 750 /* Translate the default cmode */ 751 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 752 753 /* No ethtool bits for 200Mbps */ 754 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 755 MAC_1000FD; 756 757 /* The C_Mode field is programmable on ports 9 and 10 */ 758 if (port == 9 || port == 10) { 759 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 760 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 761 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 762 763 config->mac_capabilities |= MAC_2500FD; 764 } 765 } 766 767 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 768 struct phylink_config *config) 769 { 770 unsigned long *supported = config->supported_interfaces; 771 772 mv88e6390_phylink_get_caps(chip, port, config); 773 774 /* For the 6x90X, ports 2-7 can be in automedia mode. 775 * (Note that 6x90 doesn't support RXAUI nor XAUI). 776 * 777 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 778 * configured for 1000BASE-X, SGMII or 2500BASE-X. 779 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 780 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 781 * 782 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 783 * configured for 1000BASE-X, SGMII or 2500BASE-X. 784 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 785 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 786 * 787 * For now, be permissive (as the old code was) and allow 1000BASE-X 788 * on ports 2..7. 789 */ 790 if (port >= 2 && port <= 7) 791 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 792 793 /* The C_Mode field can also be programmed for 10G speeds */ 794 if (port == 9 || port == 10) { 795 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 796 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 797 798 config->mac_capabilities |= MAC_10000FD; 799 } 800 } 801 802 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 803 struct phylink_config *config) 804 { 805 unsigned long *supported = config->supported_interfaces; 806 bool is_6191x = 807 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 808 bool is_6361 = 809 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 810 811 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 812 813 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 814 MAC_1000FD; 815 816 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 817 if (port == 0 || port == 9 || port == 10) { 818 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 819 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 820 821 /* 6191X supports >1G modes only on port 10 */ 822 if (!is_6191x || port == 10) { 823 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 824 config->mac_capabilities |= MAC_2500FD; 825 826 /* 6361 only supports up to 2500BaseX */ 827 if (!is_6361) { 828 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 829 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 831 config->mac_capabilities |= MAC_5000FD | 832 MAC_10000FD; 833 } 834 } 835 } 836 837 if (port == 0) { 838 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 839 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 843 } 844 } 845 846 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 847 struct phylink_config *config) 848 { 849 struct mv88e6xxx_chip *chip = ds->priv; 850 851 mv88e6xxx_reg_lock(chip); 852 chip->info->ops->phylink_get_caps(chip, port, config); 853 mv88e6xxx_reg_unlock(chip); 854 855 if (mv88e6xxx_phy_is_internal(chip, port)) { 856 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 857 config->supported_interfaces); 858 /* Internal ports with no phy-mode need GMII for PHYLIB */ 859 __set_bit(PHY_INTERFACE_MODE_GMII, 860 config->supported_interfaces); 861 } 862 } 863 864 static struct phylink_pcs * 865 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 866 phy_interface_t interface) 867 { 868 struct dsa_port *dp = dsa_phylink_to_port(config); 869 struct mv88e6xxx_chip *chip = dp->ds->priv; 870 struct phylink_pcs *pcs = NULL; 871 872 if (chip->info->ops->pcs_ops) 873 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 874 interface); 875 876 return pcs; 877 } 878 879 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 880 unsigned int mode, phy_interface_t interface) 881 { 882 struct dsa_port *dp = dsa_phylink_to_port(config); 883 struct mv88e6xxx_chip *chip = dp->ds->priv; 884 int port = dp->index; 885 int err = 0; 886 887 /* In inband mode, the link may come up at any time while the link 888 * is not forced down. Force the link down while we reconfigure the 889 * interface mode. 890 */ 891 if (mode == MLO_AN_INBAND && 892 chip->ports[port].interface != interface && 893 chip->info->ops->port_set_link) { 894 mv88e6xxx_reg_lock(chip); 895 err = chip->info->ops->port_set_link(chip, port, 896 LINK_FORCED_DOWN); 897 mv88e6xxx_reg_unlock(chip); 898 } 899 900 return err; 901 } 902 903 static void mv88e6xxx_mac_config(struct phylink_config *config, 904 unsigned int mode, 905 const struct phylink_link_state *state) 906 { 907 struct dsa_port *dp = dsa_phylink_to_port(config); 908 struct mv88e6xxx_chip *chip = dp->ds->priv; 909 int port = dp->index; 910 int err = 0; 911 912 mv88e6xxx_reg_lock(chip); 913 914 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 915 err = mv88e6xxx_port_config_interface(chip, port, 916 state->interface); 917 if (err && err != -EOPNOTSUPP) 918 goto err_unlock; 919 } 920 921 err_unlock: 922 mv88e6xxx_reg_unlock(chip); 923 924 if (err && err != -EOPNOTSUPP) 925 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 926 } 927 928 static int mv88e6xxx_mac_finish(struct phylink_config *config, 929 unsigned int mode, phy_interface_t interface) 930 { 931 struct dsa_port *dp = dsa_phylink_to_port(config); 932 struct mv88e6xxx_chip *chip = dp->ds->priv; 933 int port = dp->index; 934 int err = 0; 935 936 /* Undo the forced down state above after completing configuration 937 * irrespective of its state on entry, which allows the link to come 938 * up in the in-band case where there is no separate SERDES. Also 939 * ensure that the link can come up if the PPU is in use and we are 940 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 941 */ 942 mv88e6xxx_reg_lock(chip); 943 944 if (chip->info->ops->port_set_link && 945 ((mode == MLO_AN_INBAND && 946 chip->ports[port].interface != interface) || 947 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 948 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 949 950 mv88e6xxx_reg_unlock(chip); 951 952 chip->ports[port].interface = interface; 953 954 return err; 955 } 956 957 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 958 unsigned int mode, 959 phy_interface_t interface) 960 { 961 struct dsa_port *dp = dsa_phylink_to_port(config); 962 struct mv88e6xxx_chip *chip = dp->ds->priv; 963 const struct mv88e6xxx_ops *ops; 964 int port = dp->index; 965 int err = 0; 966 967 ops = chip->info->ops; 968 969 mv88e6xxx_reg_lock(chip); 970 /* Force the link down if we know the port may not be automatically 971 * updated by the switch or if we are using fixed-link mode. 972 */ 973 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 974 mode == MLO_AN_FIXED) && ops->port_sync_link) 975 err = ops->port_sync_link(chip, port, mode, false); 976 977 if (!err && ops->port_set_speed_duplex) 978 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 979 DUPLEX_UNFORCED); 980 mv88e6xxx_reg_unlock(chip); 981 982 if (err) 983 dev_err(chip->dev, 984 "p%d: failed to force MAC link down\n", port); 985 } 986 987 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 988 struct phy_device *phydev, 989 unsigned int mode, phy_interface_t interface, 990 int speed, int duplex, 991 bool tx_pause, bool rx_pause) 992 { 993 struct dsa_port *dp = dsa_phylink_to_port(config); 994 struct mv88e6xxx_chip *chip = dp->ds->priv; 995 const struct mv88e6xxx_ops *ops; 996 int port = dp->index; 997 int err = 0; 998 999 ops = chip->info->ops; 1000 1001 mv88e6xxx_reg_lock(chip); 1002 /* Configure and force the link up if we know that the port may not 1003 * automatically updated by the switch or if we are using fixed-link 1004 * mode. 1005 */ 1006 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1007 mode == MLO_AN_FIXED) { 1008 if (ops->port_set_speed_duplex) { 1009 err = ops->port_set_speed_duplex(chip, port, 1010 speed, duplex); 1011 if (err && err != -EOPNOTSUPP) 1012 goto error; 1013 } 1014 1015 if (ops->port_sync_link) 1016 err = ops->port_sync_link(chip, port, mode, true); 1017 } 1018 error: 1019 mv88e6xxx_reg_unlock(chip); 1020 1021 if (err && err != -EOPNOTSUPP) 1022 dev_err(chip->dev, 1023 "p%d: failed to configure MAC link up\n", port); 1024 } 1025 1026 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1027 { 1028 int err; 1029 1030 if (!chip->info->ops->stats_snapshot) 1031 return -EOPNOTSUPP; 1032 1033 mv88e6xxx_reg_lock(chip); 1034 err = chip->info->ops->stats_snapshot(chip, port); 1035 mv88e6xxx_reg_unlock(chip); 1036 1037 return err; 1038 } 1039 1040 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1041 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1042 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1043 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1044 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1045 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1046 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1047 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1048 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1049 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1050 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1051 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1052 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1053 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1054 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1055 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1056 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1057 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1058 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1059 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1060 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1061 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1062 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1063 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1064 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1065 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1066 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1067 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1068 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1069 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1070 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1071 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1072 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1073 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1074 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1075 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1076 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1077 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1078 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1079 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1080 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1081 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1082 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1083 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1084 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1086 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1087 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1088 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1089 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1090 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1096 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1097 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1098 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1099 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1100 /* */ 1101 1102 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1103 { #_string, _size, _reg, _type } 1104 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1105 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1106 }; 1107 1108 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1109 MV88E6XXX_HW_STAT_ID_ ## _string 1110 enum mv88e6xxx_hw_stat_id { 1111 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1112 }; 1113 1114 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1115 const struct mv88e6xxx_hw_stat *s, 1116 int port, u16 bank1_select, 1117 u16 histogram) 1118 { 1119 u32 low; 1120 u32 high = 0; 1121 u16 reg = 0; 1122 int err; 1123 u64 value; 1124 1125 switch (s->type) { 1126 case STATS_TYPE_PORT: 1127 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1128 if (err) 1129 return U64_MAX; 1130 1131 low = reg; 1132 if (s->size == 4) { 1133 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1134 if (err) 1135 return U64_MAX; 1136 low |= ((u32)reg) << 16; 1137 } 1138 break; 1139 case STATS_TYPE_BANK1: 1140 reg = bank1_select; 1141 fallthrough; 1142 case STATS_TYPE_BANK0: 1143 reg |= s->reg | histogram; 1144 mv88e6xxx_g1_stats_read(chip, reg, &low); 1145 if (s->size == 8) 1146 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1147 break; 1148 default: 1149 return U64_MAX; 1150 } 1151 value = (((u64)high) << 32) | low; 1152 return value; 1153 } 1154 1155 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1156 uint8_t **data, int types) 1157 { 1158 const struct mv88e6xxx_hw_stat *stat; 1159 int i; 1160 1161 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1162 stat = &mv88e6xxx_hw_stats[i]; 1163 if (stat->type & types) 1164 ethtool_puts(data, stat->string); 1165 } 1166 } 1167 1168 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1169 uint8_t **data) 1170 { 1171 mv88e6xxx_stats_get_strings(chip, data, 1172 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1173 } 1174 1175 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1176 uint8_t **data) 1177 { 1178 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1179 } 1180 1181 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1182 uint8_t **data) 1183 { 1184 mv88e6xxx_stats_get_strings(chip, data, 1185 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1186 } 1187 1188 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1189 "atu_member_violation", 1190 "atu_miss_violation", 1191 "atu_full_violation", 1192 "vtu_member_violation", 1193 "vtu_miss_violation", 1194 }; 1195 1196 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data) 1197 { 1198 unsigned int i; 1199 1200 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1201 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]); 1202 } 1203 1204 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1205 u32 stringset, uint8_t *data) 1206 { 1207 struct mv88e6xxx_chip *chip = ds->priv; 1208 1209 if (stringset != ETH_SS_STATS) 1210 return; 1211 1212 mv88e6xxx_reg_lock(chip); 1213 1214 if (chip->info->ops->stats_get_strings) 1215 chip->info->ops->stats_get_strings(chip, &data); 1216 1217 if (chip->info->ops->serdes_get_strings) 1218 chip->info->ops->serdes_get_strings(chip, port, &data); 1219 1220 mv88e6xxx_atu_vtu_get_strings(&data); 1221 1222 mv88e6xxx_reg_unlock(chip); 1223 } 1224 1225 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1226 int types) 1227 { 1228 const struct mv88e6xxx_hw_stat *stat; 1229 int i, j; 1230 1231 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1232 stat = &mv88e6xxx_hw_stats[i]; 1233 if (stat->type & types) 1234 j++; 1235 } 1236 return j; 1237 } 1238 1239 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1240 { 1241 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1242 STATS_TYPE_PORT); 1243 } 1244 1245 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1246 { 1247 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1248 } 1249 1250 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1251 { 1252 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1253 STATS_TYPE_BANK1); 1254 } 1255 1256 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1257 { 1258 struct mv88e6xxx_chip *chip = ds->priv; 1259 int serdes_count = 0; 1260 int count = 0; 1261 1262 if (sset != ETH_SS_STATS) 1263 return 0; 1264 1265 mv88e6xxx_reg_lock(chip); 1266 if (chip->info->ops->stats_get_sset_count) 1267 count = chip->info->ops->stats_get_sset_count(chip); 1268 if (count < 0) 1269 goto out; 1270 1271 if (chip->info->ops->serdes_get_sset_count) 1272 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1273 port); 1274 if (serdes_count < 0) { 1275 count = serdes_count; 1276 goto out; 1277 } 1278 count += serdes_count; 1279 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1280 1281 out: 1282 mv88e6xxx_reg_unlock(chip); 1283 1284 return count; 1285 } 1286 1287 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1288 const struct mv88e6xxx_hw_stat *stat, 1289 uint64_t *data) 1290 { 1291 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1292 MV88E6XXX_G1_STATS_OP_HIST_RX); 1293 return 1; 1294 } 1295 1296 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1297 const struct mv88e6xxx_hw_stat *stat, 1298 uint64_t *data) 1299 { 1300 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1301 MV88E6XXX_G1_STATS_OP_HIST_RX); 1302 return 1; 1303 } 1304 1305 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1306 const struct mv88e6xxx_hw_stat *stat, 1307 uint64_t *data) 1308 { 1309 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1310 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1311 MV88E6XXX_G1_STATS_OP_HIST_RX); 1312 return 1; 1313 } 1314 1315 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1316 const struct mv88e6xxx_hw_stat *stat, 1317 uint64_t *data) 1318 { 1319 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1320 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1321 0); 1322 return 1; 1323 } 1324 1325 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1326 const struct mv88e6xxx_hw_stat *stat, 1327 uint64_t *data) 1328 { 1329 int ret = 0; 1330 1331 if (!(stat->type & chip->info->stats_type)) 1332 return 0; 1333 1334 if (chip->info->ops->stats_get_stat) { 1335 mv88e6xxx_reg_lock(chip); 1336 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1337 mv88e6xxx_reg_unlock(chip); 1338 } 1339 1340 return ret; 1341 } 1342 1343 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1344 uint64_t *data) 1345 { 1346 const struct mv88e6xxx_hw_stat *stat; 1347 size_t i, j; 1348 1349 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1350 stat = &mv88e6xxx_hw_stats[i]; 1351 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1352 } 1353 return j; 1354 } 1355 1356 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1357 uint64_t *data) 1358 { 1359 *data++ = chip->ports[port].atu_member_violation; 1360 *data++ = chip->ports[port].atu_miss_violation; 1361 *data++ = chip->ports[port].atu_full_violation; 1362 *data++ = chip->ports[port].vtu_member_violation; 1363 *data++ = chip->ports[port].vtu_miss_violation; 1364 } 1365 1366 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1367 uint64_t *data) 1368 { 1369 size_t count; 1370 1371 count = mv88e6xxx_stats_get_stats(chip, port, data); 1372 1373 mv88e6xxx_reg_lock(chip); 1374 if (chip->info->ops->serdes_get_stats) { 1375 data += count; 1376 count = chip->info->ops->serdes_get_stats(chip, port, data); 1377 } 1378 data += count; 1379 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1380 mv88e6xxx_reg_unlock(chip); 1381 } 1382 1383 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1384 uint64_t *data) 1385 { 1386 struct mv88e6xxx_chip *chip = ds->priv; 1387 int ret; 1388 1389 ret = mv88e6xxx_stats_snapshot(chip, port); 1390 if (ret < 0) 1391 return; 1392 1393 mv88e6xxx_get_stats(chip, port, data); 1394 } 1395 1396 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1397 struct ethtool_eth_mac_stats *mac_stats) 1398 { 1399 struct mv88e6xxx_chip *chip = ds->priv; 1400 int ret; 1401 1402 ret = mv88e6xxx_stats_snapshot(chip, port); 1403 if (ret < 0) 1404 return; 1405 1406 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1407 mv88e6xxx_stats_get_stat(chip, port, \ 1408 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1409 &mac_stats->stats._member) 1410 1411 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1412 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1413 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1414 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1425 1426 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1427 1428 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1429 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1430 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1431 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1432 } 1433 1434 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1435 struct ethtool_rmon_stats *rmon_stats, 1436 const struct ethtool_rmon_hist_range **ranges) 1437 { 1438 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1439 { 64, 64 }, 1440 { 65, 127 }, 1441 { 128, 255 }, 1442 { 256, 511 }, 1443 { 512, 1023 }, 1444 { 1024, 65535 }, 1445 {} 1446 }; 1447 struct mv88e6xxx_chip *chip = ds->priv; 1448 int ret; 1449 1450 ret = mv88e6xxx_stats_snapshot(chip, port); 1451 if (ret < 0) 1452 return; 1453 1454 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1455 mv88e6xxx_stats_get_stat(chip, port, \ 1456 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1457 &rmon_stats->stats._member) 1458 1459 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1460 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1461 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1462 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1463 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1464 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1465 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1466 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1467 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1468 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1469 1470 #undef MV88E6XXX_RMON_STAT_MAP 1471 1472 *ranges = rmon_ranges; 1473 } 1474 1475 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1476 { 1477 struct mv88e6xxx_chip *chip = ds->priv; 1478 int len; 1479 1480 len = 32 * sizeof(u16); 1481 if (chip->info->ops->serdes_get_regs_len) 1482 len += chip->info->ops->serdes_get_regs_len(chip, port); 1483 1484 return len; 1485 } 1486 1487 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1488 struct ethtool_regs *regs, void *_p) 1489 { 1490 struct mv88e6xxx_chip *chip = ds->priv; 1491 int err; 1492 u16 reg; 1493 u16 *p = _p; 1494 int i; 1495 1496 regs->version = chip->info->prod_num; 1497 1498 memset(p, 0xff, 32 * sizeof(u16)); 1499 1500 mv88e6xxx_reg_lock(chip); 1501 1502 for (i = 0; i < 32; i++) { 1503 1504 err = mv88e6xxx_port_read(chip, port, i, ®); 1505 if (!err) 1506 p[i] = reg; 1507 } 1508 1509 if (chip->info->ops->serdes_get_regs) 1510 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1511 1512 mv88e6xxx_reg_unlock(chip); 1513 } 1514 1515 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1516 struct ethtool_keee *e) 1517 { 1518 /* Nothing to do on the port's MAC */ 1519 return 0; 1520 } 1521 1522 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1523 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1524 { 1525 struct dsa_switch *ds = chip->ds; 1526 struct dsa_switch_tree *dst = ds->dst; 1527 struct dsa_port *dp, *other_dp; 1528 bool found = false; 1529 u16 pvlan; 1530 1531 /* dev is a physical switch */ 1532 if (dev <= dst->last_switch) { 1533 list_for_each_entry(dp, &dst->ports, list) { 1534 if (dp->ds->index == dev && dp->index == port) { 1535 /* dp might be a DSA link or a user port, so it 1536 * might or might not have a bridge. 1537 * Use the "found" variable for both cases. 1538 */ 1539 found = true; 1540 break; 1541 } 1542 } 1543 /* dev is a virtual bridge */ 1544 } else { 1545 list_for_each_entry(dp, &dst->ports, list) { 1546 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1547 1548 if (!bridge_num) 1549 continue; 1550 1551 if (bridge_num + dst->last_switch != dev) 1552 continue; 1553 1554 found = true; 1555 break; 1556 } 1557 } 1558 1559 /* Prevent frames from unknown switch or virtual bridge */ 1560 if (!found) 1561 return 0; 1562 1563 /* Frames from DSA links and CPU ports can egress any local port */ 1564 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1565 return mv88e6xxx_port_mask(chip); 1566 1567 pvlan = 0; 1568 1569 /* Frames from standalone user ports can only egress on the 1570 * upstream port. 1571 */ 1572 if (!dsa_port_bridge_dev_get(dp)) 1573 return BIT(dsa_switch_upstream_port(ds)); 1574 1575 /* Frames from bridged user ports can egress any local DSA 1576 * links and CPU ports, as well as any local member of their 1577 * bridge group. 1578 */ 1579 dsa_switch_for_each_port(other_dp, ds) 1580 if (other_dp->type == DSA_PORT_TYPE_CPU || 1581 other_dp->type == DSA_PORT_TYPE_DSA || 1582 dsa_port_bridge_same(dp, other_dp)) 1583 pvlan |= BIT(other_dp->index); 1584 1585 return pvlan; 1586 } 1587 1588 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1589 { 1590 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1591 1592 /* prevent frames from going back out of the port they came in on */ 1593 output_ports &= ~BIT(port); 1594 1595 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1596 } 1597 1598 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1599 u8 state) 1600 { 1601 struct mv88e6xxx_chip *chip = ds->priv; 1602 int err; 1603 1604 mv88e6xxx_reg_lock(chip); 1605 err = mv88e6xxx_port_set_state(chip, port, state); 1606 mv88e6xxx_reg_unlock(chip); 1607 1608 if (err) 1609 dev_err(ds->dev, "p%d: failed to update state\n", port); 1610 } 1611 1612 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1613 { 1614 int err; 1615 1616 if (chip->info->ops->ieee_pri_map) { 1617 err = chip->info->ops->ieee_pri_map(chip); 1618 if (err) 1619 return err; 1620 } 1621 1622 if (chip->info->ops->ip_pri_map) { 1623 err = chip->info->ops->ip_pri_map(chip); 1624 if (err) 1625 return err; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1632 { 1633 struct dsa_switch *ds = chip->ds; 1634 int target, port; 1635 int err; 1636 1637 if (!chip->info->global2_addr) 1638 return 0; 1639 1640 /* Initialize the routing port to the 32 possible target devices */ 1641 for (target = 0; target < 32; target++) { 1642 port = dsa_routing_port(ds, target); 1643 if (port == ds->num_ports) 1644 port = 0x1f; 1645 1646 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1647 if (err) 1648 return err; 1649 } 1650 1651 if (chip->info->ops->set_cascade_port) { 1652 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1653 err = chip->info->ops->set_cascade_port(chip, port); 1654 if (err) 1655 return err; 1656 } 1657 1658 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1659 if (err) 1660 return err; 1661 1662 return 0; 1663 } 1664 1665 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1666 { 1667 /* Clear all trunk masks and mapping */ 1668 if (chip->info->global2_addr) 1669 return mv88e6xxx_g2_trunk_clear(chip); 1670 1671 return 0; 1672 } 1673 1674 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1675 { 1676 if (chip->info->ops->rmu_disable) 1677 return chip->info->ops->rmu_disable(chip); 1678 1679 return 0; 1680 } 1681 1682 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1683 { 1684 if (chip->info->ops->pot_clear) 1685 return chip->info->ops->pot_clear(chip); 1686 1687 return 0; 1688 } 1689 1690 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1691 { 1692 if (chip->info->ops->mgmt_rsvd2cpu) 1693 return chip->info->ops->mgmt_rsvd2cpu(chip); 1694 1695 return 0; 1696 } 1697 1698 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1699 { 1700 int err; 1701 1702 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1703 if (err) 1704 return err; 1705 1706 /* The chips that have a "learn2all" bit in Global1, ATU 1707 * Control are precisely those whose port registers have a 1708 * Message Port bit in Port Control 1 and hence implement 1709 * ->port_setup_message_port. 1710 */ 1711 if (chip->info->ops->port_setup_message_port) { 1712 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1713 if (err) 1714 return err; 1715 } 1716 1717 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1718 } 1719 1720 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1721 { 1722 int port; 1723 int err; 1724 1725 if (!chip->info->ops->irl_init_all) 1726 return 0; 1727 1728 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1729 /* Disable ingress rate limiting by resetting all per port 1730 * ingress rate limit resources to their initial state. 1731 */ 1732 err = chip->info->ops->irl_init_all(chip, port); 1733 if (err) 1734 return err; 1735 } 1736 1737 return 0; 1738 } 1739 1740 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1741 { 1742 if (chip->info->ops->set_switch_mac) { 1743 u8 addr[ETH_ALEN]; 1744 1745 eth_random_addr(addr); 1746 1747 return chip->info->ops->set_switch_mac(chip, addr); 1748 } 1749 1750 return 0; 1751 } 1752 1753 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1754 { 1755 struct dsa_switch_tree *dst = chip->ds->dst; 1756 struct dsa_switch *ds; 1757 struct dsa_port *dp; 1758 u16 pvlan = 0; 1759 1760 if (!mv88e6xxx_has_pvt(chip)) 1761 return 0; 1762 1763 /* Skip the local source device, which uses in-chip port VLAN */ 1764 if (dev != chip->ds->index) { 1765 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1766 1767 ds = dsa_switch_find(dst->index, dev); 1768 dp = ds ? dsa_to_port(ds, port) : NULL; 1769 if (dp && dp->lag) { 1770 /* As the PVT is used to limit flooding of 1771 * FORWARD frames, which use the LAG ID as the 1772 * source port, we must translate dev/port to 1773 * the special "LAG device" in the PVT, using 1774 * the LAG ID (one-based) as the port number 1775 * (zero-based). 1776 */ 1777 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1778 port = dsa_port_lag_id_get(dp) - 1; 1779 } 1780 } 1781 1782 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1783 } 1784 1785 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1786 { 1787 int dev, port; 1788 int err; 1789 1790 if (!mv88e6xxx_has_pvt(chip)) 1791 return 0; 1792 1793 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1794 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1795 */ 1796 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1797 if (err) 1798 return err; 1799 1800 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1801 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1802 err = mv88e6xxx_pvt_map(chip, dev, port); 1803 if (err) 1804 return err; 1805 } 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1812 u16 fid) 1813 { 1814 if (dsa_to_port(chip->ds, port)->lag) 1815 /* Hardware is incapable of fast-aging a LAG through a 1816 * regular ATU move operation. Until we have something 1817 * more fancy in place this is a no-op. 1818 */ 1819 return -EOPNOTSUPP; 1820 1821 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1822 } 1823 1824 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1825 { 1826 struct mv88e6xxx_chip *chip = ds->priv; 1827 int err; 1828 1829 mv88e6xxx_reg_lock(chip); 1830 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1831 mv88e6xxx_reg_unlock(chip); 1832 1833 if (err) 1834 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1835 port, err); 1836 } 1837 1838 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1839 { 1840 if (!mv88e6xxx_max_vid(chip)) 1841 return 0; 1842 1843 return mv88e6xxx_g1_vtu_flush(chip); 1844 } 1845 1846 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1847 struct mv88e6xxx_vtu_entry *entry) 1848 { 1849 int err; 1850 1851 if (!chip->info->ops->vtu_getnext) 1852 return -EOPNOTSUPP; 1853 1854 memset(entry, 0, sizeof(*entry)); 1855 1856 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1857 entry->valid = false; 1858 1859 err = chip->info->ops->vtu_getnext(chip, entry); 1860 1861 if (entry->vid != vid) 1862 entry->valid = false; 1863 1864 return err; 1865 } 1866 1867 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1868 int (*cb)(struct mv88e6xxx_chip *chip, 1869 const struct mv88e6xxx_vtu_entry *entry, 1870 void *priv), 1871 void *priv) 1872 { 1873 struct mv88e6xxx_vtu_entry entry = { 1874 .vid = mv88e6xxx_max_vid(chip), 1875 .valid = false, 1876 }; 1877 int err; 1878 1879 if (!chip->info->ops->vtu_getnext) 1880 return -EOPNOTSUPP; 1881 1882 do { 1883 err = chip->info->ops->vtu_getnext(chip, &entry); 1884 if (err) 1885 return err; 1886 1887 if (!entry.valid) 1888 break; 1889 1890 err = cb(chip, &entry, priv); 1891 if (err) 1892 return err; 1893 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1894 1895 return 0; 1896 } 1897 1898 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1899 struct mv88e6xxx_vtu_entry *entry) 1900 { 1901 if (!chip->info->ops->vtu_loadpurge) 1902 return -EOPNOTSUPP; 1903 1904 return chip->info->ops->vtu_loadpurge(chip, entry); 1905 } 1906 1907 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1908 { 1909 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1910 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1911 return -ENOSPC; 1912 1913 /* Clear the database */ 1914 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1915 } 1916 1917 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1918 struct mv88e6xxx_stu_entry *entry) 1919 { 1920 if (!chip->info->ops->stu_loadpurge) 1921 return -EOPNOTSUPP; 1922 1923 return chip->info->ops->stu_loadpurge(chip, entry); 1924 } 1925 1926 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1927 { 1928 struct mv88e6xxx_stu_entry stu = { 1929 .valid = true, 1930 .sid = 0 1931 }; 1932 1933 if (!mv88e6xxx_has_stu(chip)) 1934 return 0; 1935 1936 /* Make sure that SID 0 is always valid. This is used by VTU 1937 * entries that do not make use of the STU, e.g. when creating 1938 * a VLAN upper on a port that is also part of a VLAN 1939 * filtering bridge. 1940 */ 1941 return mv88e6xxx_stu_loadpurge(chip, &stu); 1942 } 1943 1944 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1945 { 1946 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1947 struct mv88e6xxx_mst *mst; 1948 1949 __set_bit(0, busy); 1950 1951 list_for_each_entry(mst, &chip->msts, node) 1952 __set_bit(mst->stu.sid, busy); 1953 1954 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1955 1956 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1957 } 1958 1959 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1960 { 1961 struct mv88e6xxx_mst *mst, *tmp; 1962 int err; 1963 1964 /* If the SID is zero, it is for a VLAN mapped to the default MSTI, 1965 * and mv88e6xxx_stu_setup() made sure it is always present, and thus, 1966 * should not be removed here. 1967 * 1968 * If the chip lacks STU support, numerically the "sid" variable will 1969 * happen to also be zero, but we don't want to rely on that fact, so 1970 * we explicitly test that first. In that case, there is also nothing 1971 * to do here. 1972 */ 1973 if (!mv88e6xxx_has_stu(chip) || !sid) 1974 return 0; 1975 1976 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1977 if (mst->stu.sid != sid) 1978 continue; 1979 1980 if (!refcount_dec_and_test(&mst->refcnt)) 1981 return 0; 1982 1983 mst->stu.valid = false; 1984 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1985 if (err) { 1986 refcount_set(&mst->refcnt, 1); 1987 return err; 1988 } 1989 1990 list_del(&mst->node); 1991 kfree(mst); 1992 return 0; 1993 } 1994 1995 return -ENOENT; 1996 } 1997 1998 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1999 u16 msti, u8 *sid) 2000 { 2001 struct mv88e6xxx_mst *mst; 2002 int err, i; 2003 2004 if (!mv88e6xxx_has_stu(chip)) { 2005 err = -EOPNOTSUPP; 2006 goto err; 2007 } 2008 2009 if (!msti) { 2010 *sid = 0; 2011 return 0; 2012 } 2013 2014 list_for_each_entry(mst, &chip->msts, node) { 2015 if (mst->br == br && mst->msti == msti) { 2016 refcount_inc(&mst->refcnt); 2017 *sid = mst->stu.sid; 2018 return 0; 2019 } 2020 } 2021 2022 err = mv88e6xxx_sid_get(chip, sid); 2023 if (err) 2024 goto err; 2025 2026 mst = kzalloc_obj(*mst); 2027 if (!mst) { 2028 err = -ENOMEM; 2029 goto err; 2030 } 2031 2032 INIT_LIST_HEAD(&mst->node); 2033 refcount_set(&mst->refcnt, 1); 2034 mst->br = br; 2035 mst->msti = msti; 2036 mst->stu.valid = true; 2037 mst->stu.sid = *sid; 2038 2039 /* The bridge starts out all ports in the disabled state. But 2040 * a STU state of disabled means to go by the port-global 2041 * state. So we set all user port's initial state to blocking, 2042 * to match the bridge's behavior. 2043 */ 2044 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2045 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2046 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2047 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2048 2049 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2050 if (err) 2051 goto err_free; 2052 2053 list_add_tail(&mst->node, &chip->msts); 2054 return 0; 2055 2056 err_free: 2057 kfree(mst); 2058 err: 2059 return err; 2060 } 2061 2062 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2063 const struct switchdev_mst_state *st) 2064 { 2065 struct dsa_port *dp = dsa_to_port(ds, port); 2066 struct mv88e6xxx_chip *chip = ds->priv; 2067 struct mv88e6xxx_mst *mst; 2068 u8 state; 2069 int err; 2070 2071 if (!mv88e6xxx_has_stu(chip)) 2072 return -EOPNOTSUPP; 2073 2074 switch (st->state) { 2075 case BR_STATE_DISABLED: 2076 case BR_STATE_BLOCKING: 2077 case BR_STATE_LISTENING: 2078 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2079 break; 2080 case BR_STATE_LEARNING: 2081 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2082 break; 2083 case BR_STATE_FORWARDING: 2084 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2085 break; 2086 default: 2087 return -EINVAL; 2088 } 2089 2090 list_for_each_entry(mst, &chip->msts, node) { 2091 if (mst->br == dsa_port_bridge_dev_get(dp) && 2092 mst->msti == st->msti) { 2093 if (mst->stu.state[port] == state) 2094 return 0; 2095 2096 mst->stu.state[port] = state; 2097 mv88e6xxx_reg_lock(chip); 2098 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2099 mv88e6xxx_reg_unlock(chip); 2100 return err; 2101 } 2102 } 2103 2104 return -ENOENT; 2105 } 2106 2107 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2108 u16 vid) 2109 { 2110 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2111 struct mv88e6xxx_chip *chip = ds->priv; 2112 struct mv88e6xxx_vtu_entry vlan; 2113 int err; 2114 2115 /* DSA and CPU ports have to be members of multiple vlans */ 2116 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2117 return 0; 2118 2119 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2120 if (err) 2121 return err; 2122 2123 if (!vlan.valid) 2124 return 0; 2125 2126 dsa_switch_for_each_user_port(other_dp, ds) { 2127 struct net_device *other_br; 2128 2129 if (vlan.member[other_dp->index] == 2130 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2131 continue; 2132 2133 if (dsa_port_bridge_same(dp, other_dp)) 2134 break; /* same bridge, check next VLAN */ 2135 2136 other_br = dsa_port_bridge_dev_get(other_dp); 2137 if (!other_br) 2138 continue; 2139 2140 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2141 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2142 return -EOPNOTSUPP; 2143 } 2144 2145 return 0; 2146 } 2147 2148 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2149 { 2150 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2151 struct net_device *br = dsa_port_bridge_dev_get(dp); 2152 struct mv88e6xxx_port *p = &chip->ports[port]; 2153 u16 pvid = MV88E6XXX_VID_STANDALONE; 2154 bool drop_untagged = false; 2155 int err; 2156 2157 if (br) { 2158 if (br_vlan_enabled(br)) { 2159 pvid = p->bridge_pvid.vid; 2160 drop_untagged = !p->bridge_pvid.valid; 2161 } else { 2162 pvid = MV88E6XXX_VID_BRIDGED; 2163 } 2164 } 2165 2166 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2167 if (err) 2168 return err; 2169 2170 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2171 } 2172 2173 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2174 bool vlan_filtering, 2175 struct netlink_ext_ack *extack) 2176 { 2177 struct mv88e6xxx_chip *chip = ds->priv; 2178 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2179 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2180 int err; 2181 2182 if (!mv88e6xxx_max_vid(chip)) 2183 return -EOPNOTSUPP; 2184 2185 mv88e6xxx_reg_lock(chip); 2186 2187 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2188 if (err) 2189 goto unlock; 2190 2191 err = mv88e6xxx_port_commit_pvid(chip, port); 2192 if (err) 2193 goto unlock; 2194 2195 unlock: 2196 mv88e6xxx_reg_unlock(chip); 2197 2198 return err; 2199 } 2200 2201 static int 2202 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2203 const struct switchdev_obj_port_vlan *vlan) 2204 { 2205 struct mv88e6xxx_chip *chip = ds->priv; 2206 int err; 2207 2208 if (!mv88e6xxx_max_vid(chip)) 2209 return -EOPNOTSUPP; 2210 2211 /* If the requested port doesn't belong to the same bridge as the VLAN 2212 * members, do not support it (yet) and fallback to software VLAN. 2213 */ 2214 mv88e6xxx_reg_lock(chip); 2215 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2216 mv88e6xxx_reg_unlock(chip); 2217 2218 return err; 2219 } 2220 2221 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip, 2222 const unsigned char *addr, u16 vid, 2223 u16 *fid, struct mv88e6xxx_atu_entry *entry) 2224 { 2225 struct mv88e6xxx_vtu_entry vlan; 2226 int err; 2227 2228 /* Ports have two private address databases: one for when the port is 2229 * standalone and one for when the port is under a bridge and the 2230 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2231 * address database to remain 100% empty, so we never load an ATU entry 2232 * into a standalone port's database. Therefore, translate the null 2233 * VLAN ID into the port's database used for VLAN-unaware bridging. 2234 */ 2235 if (vid == 0) { 2236 *fid = MV88E6XXX_FID_BRIDGED; 2237 } else { 2238 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2239 if (err) 2240 return err; 2241 2242 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2243 if (!vlan.valid) 2244 return -EOPNOTSUPP; 2245 2246 *fid = vlan.fid; 2247 } 2248 2249 entry->state = 0; 2250 ether_addr_copy(entry->mac, addr); 2251 eth_addr_dec(entry->mac); 2252 2253 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry); 2254 } 2255 2256 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip, 2257 const unsigned char *addr, u16 vid) 2258 { 2259 struct mv88e6xxx_atu_entry entry; 2260 u16 fid; 2261 int err; 2262 2263 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2264 if (err) 2265 return false; 2266 2267 return entry.state && ether_addr_equal(entry.mac, addr); 2268 } 2269 2270 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2271 const unsigned char *addr, u16 vid, 2272 u8 state) 2273 { 2274 struct mv88e6xxx_atu_entry entry; 2275 u16 fid; 2276 int err; 2277 2278 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2279 if (err) 2280 return err; 2281 2282 /* Initialize a fresh ATU entry if it isn't found */ 2283 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2284 memset(&entry, 0, sizeof(entry)); 2285 ether_addr_copy(entry.mac, addr); 2286 } 2287 2288 /* Purge the ATU entry only if no port is using it anymore */ 2289 if (!state) { 2290 entry.portvec &= ~BIT(port); 2291 if (!entry.portvec) 2292 entry.state = 0; 2293 } else { 2294 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2295 entry.portvec = BIT(port); 2296 else 2297 entry.portvec |= BIT(port); 2298 2299 entry.state = state; 2300 } 2301 2302 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2303 } 2304 2305 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2306 const struct mv88e6xxx_policy *policy) 2307 { 2308 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2309 enum mv88e6xxx_policy_action action = policy->action; 2310 const u8 *addr = policy->addr; 2311 u16 vid = policy->vid; 2312 u8 state; 2313 int err; 2314 int id; 2315 2316 if (!chip->info->ops->port_set_policy) 2317 return -EOPNOTSUPP; 2318 2319 switch (mapping) { 2320 case MV88E6XXX_POLICY_MAPPING_DA: 2321 case MV88E6XXX_POLICY_MAPPING_SA: 2322 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2323 state = 0; /* Dissociate the port and address */ 2324 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2325 is_multicast_ether_addr(addr)) 2326 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2327 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2328 is_unicast_ether_addr(addr)) 2329 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2330 else 2331 return -EOPNOTSUPP; 2332 2333 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2334 state); 2335 if (err) 2336 return err; 2337 break; 2338 default: 2339 return -EOPNOTSUPP; 2340 } 2341 2342 /* Skip the port's policy clearing if the mapping is still in use */ 2343 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2344 idr_for_each_entry(&chip->policies, policy, id) 2345 if (policy->port == port && 2346 policy->mapping == mapping && 2347 policy->action != action) 2348 return 0; 2349 2350 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2351 } 2352 2353 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2354 struct ethtool_rx_flow_spec *fs) 2355 { 2356 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2357 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2358 enum mv88e6xxx_policy_mapping mapping; 2359 enum mv88e6xxx_policy_action action; 2360 struct mv88e6xxx_policy *policy; 2361 u16 vid = 0; 2362 u8 *addr; 2363 int err; 2364 int id; 2365 2366 if (fs->location != RX_CLS_LOC_ANY) 2367 return -EINVAL; 2368 2369 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2370 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2371 else 2372 return -EOPNOTSUPP; 2373 2374 switch (fs->flow_type & ~FLOW_EXT) { 2375 case ETHER_FLOW: 2376 if (!is_zero_ether_addr(mac_mask->h_dest) && 2377 is_zero_ether_addr(mac_mask->h_source)) { 2378 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2379 addr = mac_entry->h_dest; 2380 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2381 !is_zero_ether_addr(mac_mask->h_source)) { 2382 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2383 addr = mac_entry->h_source; 2384 } else { 2385 /* Cannot support DA and SA mapping in the same rule */ 2386 return -EOPNOTSUPP; 2387 } 2388 break; 2389 default: 2390 return -EOPNOTSUPP; 2391 } 2392 2393 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2394 if (fs->m_ext.vlan_tci != htons(0xffff)) 2395 return -EOPNOTSUPP; 2396 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2397 } 2398 2399 idr_for_each_entry(&chip->policies, policy, id) { 2400 if (policy->port == port && policy->mapping == mapping && 2401 policy->action == action && policy->vid == vid && 2402 ether_addr_equal(policy->addr, addr)) 2403 return -EEXIST; 2404 } 2405 2406 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2407 if (!policy) 2408 return -ENOMEM; 2409 2410 fs->location = 0; 2411 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2412 GFP_KERNEL); 2413 if (err) { 2414 devm_kfree(chip->dev, policy); 2415 return err; 2416 } 2417 2418 memcpy(&policy->fs, fs, sizeof(*fs)); 2419 ether_addr_copy(policy->addr, addr); 2420 policy->mapping = mapping; 2421 policy->action = action; 2422 policy->port = port; 2423 policy->vid = vid; 2424 2425 err = mv88e6xxx_policy_apply(chip, port, policy); 2426 if (err) { 2427 idr_remove(&chip->policies, fs->location); 2428 devm_kfree(chip->dev, policy); 2429 return err; 2430 } 2431 2432 return 0; 2433 } 2434 2435 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2436 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2437 { 2438 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2439 struct mv88e6xxx_chip *chip = ds->priv; 2440 struct mv88e6xxx_policy *policy; 2441 u32 cnt = 0; 2442 int err; 2443 int id; 2444 2445 mv88e6xxx_reg_lock(chip); 2446 2447 switch (rxnfc->cmd) { 2448 case ETHTOOL_GRXCLSRLCNT: 2449 rxnfc->data = 0; 2450 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2451 rxnfc->rule_cnt = 0; 2452 idr_for_each_entry(&chip->policies, policy, id) 2453 if (policy->port == port) 2454 rxnfc->rule_cnt++; 2455 err = 0; 2456 break; 2457 case ETHTOOL_GRXCLSRULE: 2458 err = -ENOENT; 2459 policy = idr_find(&chip->policies, fs->location); 2460 if (policy && policy->port == port) { 2461 memcpy(fs, &policy->fs, sizeof(*fs)); 2462 err = 0; 2463 } 2464 break; 2465 case ETHTOOL_GRXCLSRLALL: 2466 rxnfc->data = 0; 2467 err = 0; 2468 idr_for_each_entry(&chip->policies, policy, id) { 2469 if (policy->port != port) 2470 continue; 2471 if (cnt == rxnfc->rule_cnt) { 2472 err = -EMSGSIZE; 2473 break; 2474 } 2475 rule_locs[cnt++] = id; 2476 } 2477 if (!err) 2478 rxnfc->rule_cnt = cnt; 2479 break; 2480 default: 2481 err = -EOPNOTSUPP; 2482 break; 2483 } 2484 2485 mv88e6xxx_reg_unlock(chip); 2486 2487 return err; 2488 } 2489 2490 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2491 struct ethtool_rxnfc *rxnfc) 2492 { 2493 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2494 struct mv88e6xxx_chip *chip = ds->priv; 2495 struct mv88e6xxx_policy *policy; 2496 int err; 2497 2498 mv88e6xxx_reg_lock(chip); 2499 2500 switch (rxnfc->cmd) { 2501 case ETHTOOL_SRXCLSRLINS: 2502 err = mv88e6xxx_policy_insert(chip, port, fs); 2503 break; 2504 case ETHTOOL_SRXCLSRLDEL: 2505 err = -ENOENT; 2506 policy = idr_find(&chip->policies, fs->location); 2507 if (policy && policy->port == port) { 2508 idr_remove(&chip->policies, fs->location); 2509 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2510 err = mv88e6xxx_policy_apply(chip, port, policy); 2511 devm_kfree(chip->dev, policy); 2512 } 2513 break; 2514 default: 2515 err = -EOPNOTSUPP; 2516 break; 2517 } 2518 2519 mv88e6xxx_reg_unlock(chip); 2520 2521 return err; 2522 } 2523 2524 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2525 u16 vid) 2526 { 2527 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2528 u8 broadcast[ETH_ALEN]; 2529 2530 eth_broadcast_addr(broadcast); 2531 2532 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2533 } 2534 2535 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2536 { 2537 int port; 2538 int err; 2539 2540 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2541 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2542 struct net_device *brport; 2543 2544 if (dsa_is_unused_port(chip->ds, port)) 2545 continue; 2546 2547 brport = dsa_port_to_bridge_port(dp); 2548 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2549 /* Skip bridged user ports where broadcast 2550 * flooding is disabled. 2551 */ 2552 continue; 2553 2554 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2555 if (err) 2556 return err; 2557 } 2558 2559 return 0; 2560 } 2561 2562 struct mv88e6xxx_port_broadcast_sync_ctx { 2563 int port; 2564 bool flood; 2565 }; 2566 2567 static int 2568 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2569 const struct mv88e6xxx_vtu_entry *vlan, 2570 void *_ctx) 2571 { 2572 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2573 u8 broadcast[ETH_ALEN]; 2574 u8 state; 2575 2576 if (ctx->flood) 2577 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2578 else 2579 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2580 2581 eth_broadcast_addr(broadcast); 2582 2583 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2584 vlan->vid, state); 2585 } 2586 2587 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2588 bool flood) 2589 { 2590 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2591 .port = port, 2592 .flood = flood, 2593 }; 2594 struct mv88e6xxx_vtu_entry vid0 = { 2595 .vid = 0, 2596 }; 2597 int err; 2598 2599 /* Update the port's private database... */ 2600 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2601 if (err) 2602 return err; 2603 2604 /* ...and the database for all VLANs. */ 2605 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2606 &ctx); 2607 } 2608 2609 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2610 u16 vid, u8 member, bool warn) 2611 { 2612 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2613 struct mv88e6xxx_vtu_entry vlan; 2614 int i, err; 2615 2616 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2617 if (err) 2618 return err; 2619 2620 if (!vlan.valid) { 2621 memset(&vlan, 0, sizeof(vlan)); 2622 2623 if (vid == MV88E6XXX_VID_STANDALONE) 2624 vlan.policy = true; 2625 2626 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2627 if (err) 2628 return err; 2629 2630 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2631 if (i == port) 2632 vlan.member[i] = member; 2633 else 2634 vlan.member[i] = non_member; 2635 2636 vlan.vid = vid; 2637 vlan.valid = true; 2638 2639 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2640 if (err) 2641 return err; 2642 2643 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2644 if (err) 2645 return err; 2646 } else if (vlan.member[port] != member) { 2647 vlan.member[port] = member; 2648 2649 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2650 if (err) 2651 return err; 2652 } else if (warn) { 2653 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2654 port, vid); 2655 } 2656 2657 /* Record FID used in SW FID map */ 2658 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2659 2660 return 0; 2661 } 2662 2663 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2664 const struct switchdev_obj_port_vlan *vlan, 2665 struct netlink_ext_ack *extack) 2666 { 2667 struct mv88e6xxx_chip *chip = ds->priv; 2668 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2669 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2670 struct mv88e6xxx_port *p = &chip->ports[port]; 2671 bool warn; 2672 u8 member; 2673 int err; 2674 2675 if (!vlan->vid) 2676 return 0; 2677 2678 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2679 if (err) 2680 return err; 2681 2682 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2683 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2684 else if (untagged) 2685 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2686 else 2687 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2688 2689 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2690 * and then the CPU port. Do not warn for duplicates for the CPU port. 2691 */ 2692 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2693 2694 mv88e6xxx_reg_lock(chip); 2695 2696 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2697 if (err) { 2698 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2699 vlan->vid, untagged ? 'u' : 't'); 2700 goto out; 2701 } 2702 2703 if (pvid) { 2704 p->bridge_pvid.vid = vlan->vid; 2705 p->bridge_pvid.valid = true; 2706 2707 err = mv88e6xxx_port_commit_pvid(chip, port); 2708 if (err) 2709 goto out; 2710 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2711 /* The old pvid was reinstalled as a non-pvid VLAN */ 2712 p->bridge_pvid.valid = false; 2713 2714 err = mv88e6xxx_port_commit_pvid(chip, port); 2715 if (err) 2716 goto out; 2717 } 2718 2719 out: 2720 mv88e6xxx_reg_unlock(chip); 2721 2722 return err; 2723 } 2724 2725 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2726 int port, u16 vid) 2727 { 2728 struct mv88e6xxx_vtu_entry vlan; 2729 int i, err; 2730 2731 if (!vid) 2732 return 0; 2733 2734 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2735 if (err) 2736 return err; 2737 2738 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2739 * tell switchdev that this VLAN is likely handled in software. 2740 */ 2741 if (!vlan.valid || 2742 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2743 return -EOPNOTSUPP; 2744 2745 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2746 2747 /* keep the VLAN unless all ports are excluded */ 2748 vlan.valid = false; 2749 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2750 if (vlan.member[i] != 2751 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2752 vlan.valid = true; 2753 break; 2754 } 2755 } 2756 2757 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2758 if (err) 2759 return err; 2760 2761 if (!vlan.valid) { 2762 err = mv88e6xxx_mst_put(chip, vlan.sid); 2763 if (err) 2764 return err; 2765 2766 /* Record FID freed in SW FID map */ 2767 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2768 } 2769 2770 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2771 } 2772 2773 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2774 const struct switchdev_obj_port_vlan *vlan) 2775 { 2776 struct mv88e6xxx_chip *chip = ds->priv; 2777 struct mv88e6xxx_port *p = &chip->ports[port]; 2778 int err = 0; 2779 u16 pvid; 2780 2781 if (!mv88e6xxx_max_vid(chip)) 2782 return -EOPNOTSUPP; 2783 2784 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2785 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2786 * switchdev workqueue to ensure that all FDB entries are deleted 2787 * before we remove the VLAN. 2788 */ 2789 dsa_flush_workqueue(); 2790 2791 mv88e6xxx_reg_lock(chip); 2792 2793 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2794 if (err) 2795 goto unlock; 2796 2797 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2798 if (err) 2799 goto unlock; 2800 2801 if (vlan->vid == pvid) { 2802 p->bridge_pvid.valid = false; 2803 2804 err = mv88e6xxx_port_commit_pvid(chip, port); 2805 if (err) 2806 goto unlock; 2807 } 2808 2809 unlock: 2810 mv88e6xxx_reg_unlock(chip); 2811 2812 return err; 2813 } 2814 2815 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2816 { 2817 struct mv88e6xxx_chip *chip = ds->priv; 2818 struct mv88e6xxx_vtu_entry vlan; 2819 int err; 2820 2821 mv88e6xxx_reg_lock(chip); 2822 2823 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2824 if (err) 2825 goto unlock; 2826 2827 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2828 2829 unlock: 2830 mv88e6xxx_reg_unlock(chip); 2831 2832 return err; 2833 } 2834 2835 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2836 struct dsa_bridge bridge, 2837 const struct switchdev_vlan_msti *msti) 2838 { 2839 struct mv88e6xxx_chip *chip = ds->priv; 2840 struct mv88e6xxx_vtu_entry vlan; 2841 u8 old_sid, new_sid; 2842 int err; 2843 2844 if (!mv88e6xxx_has_stu(chip)) 2845 return -EOPNOTSUPP; 2846 2847 mv88e6xxx_reg_lock(chip); 2848 2849 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2850 if (err) 2851 goto unlock; 2852 2853 if (!vlan.valid) { 2854 err = -EINVAL; 2855 goto unlock; 2856 } 2857 2858 old_sid = vlan.sid; 2859 2860 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2861 if (err) 2862 goto unlock; 2863 2864 if (new_sid != old_sid) { 2865 vlan.sid = new_sid; 2866 2867 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2868 if (err) { 2869 mv88e6xxx_mst_put(chip, new_sid); 2870 goto unlock; 2871 } 2872 } 2873 2874 err = mv88e6xxx_mst_put(chip, old_sid); 2875 2876 unlock: 2877 mv88e6xxx_reg_unlock(chip); 2878 return err; 2879 } 2880 2881 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2882 const unsigned char *addr, u16 vid, 2883 struct dsa_db db) 2884 { 2885 struct mv88e6xxx_chip *chip = ds->priv; 2886 int err; 2887 2888 mv88e6xxx_reg_lock(chip); 2889 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2890 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2891 if (err) 2892 goto out; 2893 2894 if (!mv88e6xxx_port_db_find(chip, addr, vid)) 2895 err = -ENOSPC; 2896 2897 out: 2898 mv88e6xxx_reg_unlock(chip); 2899 2900 return err; 2901 } 2902 2903 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2904 const unsigned char *addr, u16 vid, 2905 struct dsa_db db) 2906 { 2907 struct mv88e6xxx_chip *chip = ds->priv; 2908 int err; 2909 2910 mv88e6xxx_reg_lock(chip); 2911 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2912 mv88e6xxx_reg_unlock(chip); 2913 2914 return err; 2915 } 2916 2917 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2918 u16 fid, u16 vid, int port, 2919 dsa_fdb_dump_cb_t *cb, void *data) 2920 { 2921 struct mv88e6xxx_atu_entry addr; 2922 bool is_static; 2923 int err; 2924 2925 addr.state = 0; 2926 eth_broadcast_addr(addr.mac); 2927 2928 do { 2929 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2930 if (err) 2931 return err; 2932 2933 if (!addr.state) 2934 break; 2935 2936 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2937 continue; 2938 2939 if (!is_unicast_ether_addr(addr.mac)) 2940 continue; 2941 2942 is_static = (addr.state == 2943 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2944 err = cb(addr.mac, vid, is_static, data); 2945 if (err) 2946 return err; 2947 } while (!is_broadcast_ether_addr(addr.mac)); 2948 2949 return err; 2950 } 2951 2952 struct mv88e6xxx_port_db_dump_vlan_ctx { 2953 int port; 2954 dsa_fdb_dump_cb_t *cb; 2955 void *data; 2956 }; 2957 2958 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2959 const struct mv88e6xxx_vtu_entry *entry, 2960 void *_data) 2961 { 2962 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2963 2964 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2965 ctx->port, ctx->cb, ctx->data); 2966 } 2967 2968 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2969 dsa_fdb_dump_cb_t *cb, void *data) 2970 { 2971 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2972 .port = port, 2973 .cb = cb, 2974 .data = data, 2975 }; 2976 u16 fid; 2977 int err; 2978 2979 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2980 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2981 if (err) 2982 return err; 2983 2984 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2985 if (err) 2986 return err; 2987 2988 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2989 } 2990 2991 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2992 dsa_fdb_dump_cb_t *cb, void *data) 2993 { 2994 struct mv88e6xxx_chip *chip = ds->priv; 2995 int err; 2996 2997 mv88e6xxx_reg_lock(chip); 2998 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2999 mv88e6xxx_reg_unlock(chip); 3000 3001 return err; 3002 } 3003 3004 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 3005 struct dsa_bridge bridge) 3006 { 3007 struct dsa_switch *ds = chip->ds; 3008 struct dsa_switch_tree *dst = ds->dst; 3009 struct dsa_port *dp; 3010 int err; 3011 3012 list_for_each_entry(dp, &dst->ports, list) { 3013 if (dsa_port_offloads_bridge(dp, &bridge)) { 3014 if (dp->ds == ds) { 3015 /* This is a local bridge group member, 3016 * remap its Port VLAN Map. 3017 */ 3018 err = mv88e6xxx_port_vlan_map(chip, dp->index); 3019 if (err) 3020 return err; 3021 } else { 3022 /* This is an external bridge group member, 3023 * remap its cross-chip Port VLAN Table entry. 3024 */ 3025 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3026 dp->index); 3027 if (err) 3028 return err; 3029 } 3030 } 3031 } 3032 3033 return 0; 3034 } 3035 3036 /* Treat the software bridge as a virtual single-port switch behind the 3037 * CPU and map in the PVT. First dst->last_switch elements are taken by 3038 * physical switches, so start from beyond that range. 3039 */ 3040 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3041 unsigned int bridge_num) 3042 { 3043 u8 dev = bridge_num + ds->dst->last_switch; 3044 struct mv88e6xxx_chip *chip = ds->priv; 3045 3046 return mv88e6xxx_pvt_map(chip, dev, 0); 3047 } 3048 3049 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3050 struct dsa_bridge bridge, 3051 bool *tx_fwd_offload, 3052 struct netlink_ext_ack *extack) 3053 { 3054 struct mv88e6xxx_chip *chip = ds->priv; 3055 int err; 3056 3057 mv88e6xxx_reg_lock(chip); 3058 3059 err = mv88e6xxx_bridge_map(chip, bridge); 3060 if (err) 3061 goto unlock; 3062 3063 err = mv88e6xxx_port_set_map_da(chip, port, true); 3064 if (err) 3065 goto unlock; 3066 3067 err = mv88e6xxx_port_commit_pvid(chip, port); 3068 if (err) 3069 goto unlock; 3070 3071 if (mv88e6xxx_has_pvt(chip)) { 3072 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3073 if (err) 3074 goto unlock; 3075 3076 *tx_fwd_offload = true; 3077 } 3078 3079 unlock: 3080 mv88e6xxx_reg_unlock(chip); 3081 3082 return err; 3083 } 3084 3085 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3086 struct dsa_bridge bridge) 3087 { 3088 struct mv88e6xxx_chip *chip = ds->priv; 3089 int err; 3090 3091 mv88e6xxx_reg_lock(chip); 3092 3093 if (bridge.tx_fwd_offload && 3094 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3095 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3096 3097 if (mv88e6xxx_bridge_map(chip, bridge) || 3098 mv88e6xxx_port_vlan_map(chip, port)) 3099 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3100 3101 err = mv88e6xxx_port_set_map_da(chip, port, false); 3102 if (err) 3103 dev_err(ds->dev, 3104 "port %d failed to restore map-DA: %pe\n", 3105 port, ERR_PTR(err)); 3106 3107 err = mv88e6xxx_port_commit_pvid(chip, port); 3108 if (err) 3109 dev_err(ds->dev, 3110 "port %d failed to restore standalone pvid: %pe\n", 3111 port, ERR_PTR(err)); 3112 3113 mv88e6xxx_reg_unlock(chip); 3114 } 3115 3116 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3117 int tree_index, int sw_index, 3118 int port, struct dsa_bridge bridge, 3119 struct netlink_ext_ack *extack) 3120 { 3121 struct mv88e6xxx_chip *chip = ds->priv; 3122 int err; 3123 3124 if (tree_index != ds->dst->index) 3125 return 0; 3126 3127 mv88e6xxx_reg_lock(chip); 3128 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3129 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3130 mv88e6xxx_reg_unlock(chip); 3131 3132 return err; 3133 } 3134 3135 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3136 int tree_index, int sw_index, 3137 int port, struct dsa_bridge bridge) 3138 { 3139 struct mv88e6xxx_chip *chip = ds->priv; 3140 3141 if (tree_index != ds->dst->index) 3142 return; 3143 3144 mv88e6xxx_reg_lock(chip); 3145 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3146 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3147 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3148 mv88e6xxx_reg_unlock(chip); 3149 } 3150 3151 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3152 { 3153 if (chip->info->ops->reset) 3154 return chip->info->ops->reset(chip); 3155 3156 return 0; 3157 } 3158 3159 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3160 { 3161 struct gpio_desc *gpiod = chip->reset; 3162 int err; 3163 3164 /* If there is a GPIO connected to the reset pin, toggle it */ 3165 if (gpiod) { 3166 /* If the switch has just been reset and not yet completed 3167 * loading EEPROM, the reset may interrupt the I2C transaction 3168 * mid-byte, causing the first EEPROM read after the reset 3169 * from the wrong location resulting in the switch booting 3170 * to wrong mode and inoperable. 3171 * For this reason, switch families with EEPROM support 3172 * generally wait for EEPROM loads to complete as their pre- 3173 * and post-reset handlers. 3174 */ 3175 if (chip->info->ops->hardware_reset_pre) { 3176 err = chip->info->ops->hardware_reset_pre(chip); 3177 if (err) 3178 dev_err(chip->dev, "pre-reset error: %d\n", err); 3179 } 3180 3181 gpiod_set_value_cansleep(gpiod, 1); 3182 usleep_range(10000, 20000); 3183 gpiod_set_value_cansleep(gpiod, 0); 3184 usleep_range(10000, 20000); 3185 3186 if (chip->info->ops->hardware_reset_post) { 3187 err = chip->info->ops->hardware_reset_post(chip); 3188 if (err) 3189 dev_err(chip->dev, "post-reset error: %d\n", err); 3190 } 3191 } 3192 } 3193 3194 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3195 { 3196 int i, err; 3197 3198 /* Set all ports to the Disabled state */ 3199 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3200 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3201 if (err) 3202 return err; 3203 } 3204 3205 /* Wait for transmit queues to drain, 3206 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3207 */ 3208 usleep_range(2000, 4000); 3209 3210 return 0; 3211 } 3212 3213 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3214 { 3215 int err; 3216 3217 err = mv88e6xxx_disable_ports(chip); 3218 if (err) 3219 return err; 3220 3221 mv88e6xxx_hardware_reset(chip); 3222 3223 return mv88e6xxx_software_reset(chip); 3224 } 3225 3226 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3227 enum mv88e6xxx_frame_mode frame, 3228 enum mv88e6xxx_egress_mode egress, u16 etype) 3229 { 3230 int err; 3231 3232 if (!chip->info->ops->port_set_frame_mode) 3233 return -EOPNOTSUPP; 3234 3235 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3236 if (err) 3237 return err; 3238 3239 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3240 if (err) 3241 return err; 3242 3243 if (chip->info->ops->port_set_ether_type) 3244 return chip->info->ops->port_set_ether_type(chip, port, etype); 3245 3246 return 0; 3247 } 3248 3249 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3250 { 3251 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3252 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3253 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3254 } 3255 3256 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3257 { 3258 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3259 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3260 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3261 } 3262 3263 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3264 { 3265 return mv88e6xxx_set_port_mode(chip, port, 3266 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3267 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3268 ETH_P_EDSA); 3269 } 3270 3271 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3272 { 3273 if (dsa_is_dsa_port(chip->ds, port)) 3274 return mv88e6xxx_set_port_mode_dsa(chip, port); 3275 3276 if (dsa_is_user_port(chip->ds, port)) 3277 return mv88e6xxx_set_port_mode_normal(chip, port); 3278 3279 /* Setup CPU port mode depending on its supported tag format */ 3280 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3281 return mv88e6xxx_set_port_mode_dsa(chip, port); 3282 3283 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3284 return mv88e6xxx_set_port_mode_edsa(chip, port); 3285 3286 return -EINVAL; 3287 } 3288 3289 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3290 { 3291 bool message = dsa_is_dsa_port(chip->ds, port); 3292 3293 return mv88e6xxx_port_set_message_port(chip, port, message); 3294 } 3295 3296 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3297 { 3298 int err; 3299 3300 if (chip->info->ops->port_set_ucast_flood) { 3301 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3302 if (err) 3303 return err; 3304 } 3305 if (chip->info->ops->port_set_mcast_flood) { 3306 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3307 if (err) 3308 return err; 3309 } 3310 3311 return 0; 3312 } 3313 3314 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3315 enum mv88e6xxx_egress_direction direction, 3316 int port) 3317 { 3318 int err; 3319 3320 if (!chip->info->ops->set_egress_port) 3321 return -EOPNOTSUPP; 3322 3323 err = chip->info->ops->set_egress_port(chip, direction, port); 3324 if (err) 3325 return err; 3326 3327 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3328 chip->ingress_dest_port = port; 3329 else 3330 chip->egress_dest_port = port; 3331 3332 return 0; 3333 } 3334 3335 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3336 { 3337 struct dsa_switch *ds = chip->ds; 3338 int upstream_port; 3339 int err; 3340 3341 upstream_port = dsa_upstream_port(ds, port); 3342 if (chip->info->ops->port_set_upstream_port) { 3343 err = chip->info->ops->port_set_upstream_port(chip, port, 3344 upstream_port); 3345 if (err) 3346 return err; 3347 } 3348 3349 if (port == upstream_port) { 3350 if (chip->info->ops->set_cpu_port) { 3351 err = chip->info->ops->set_cpu_port(chip, 3352 upstream_port); 3353 if (err) 3354 return err; 3355 } 3356 3357 err = mv88e6xxx_set_egress_port(chip, 3358 MV88E6XXX_EGRESS_DIR_INGRESS, 3359 upstream_port); 3360 if (err && err != -EOPNOTSUPP) 3361 return err; 3362 3363 err = mv88e6xxx_set_egress_port(chip, 3364 MV88E6XXX_EGRESS_DIR_EGRESS, 3365 upstream_port); 3366 if (err && err != -EOPNOTSUPP) 3367 return err; 3368 } 3369 3370 return 0; 3371 } 3372 3373 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3374 { 3375 struct fwnode_handle *ports_fwnode; 3376 struct fwnode_handle *port_fwnode; 3377 struct dsa_switch *ds = chip->ds; 3378 struct mv88e6xxx_port *p; 3379 int err; 3380 u16 reg; 3381 u32 val; 3382 3383 p = &chip->ports[port]; 3384 p->chip = chip; 3385 p->port = port; 3386 3387 /* Look up corresponding fwnode if any */ 3388 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3389 if (!ports_fwnode) 3390 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3391 if (ports_fwnode) { 3392 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3393 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3394 continue; 3395 if (val == port) { 3396 p->fwnode = port_fwnode; 3397 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3398 break; 3399 } 3400 } 3401 fwnode_handle_put(ports_fwnode); 3402 } else { 3403 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3404 } 3405 3406 if (chip->info->ops->port_setup_leds) { 3407 err = chip->info->ops->port_setup_leds(chip, port); 3408 if (err && err != -EOPNOTSUPP) 3409 return err; 3410 } 3411 3412 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3413 SPEED_UNFORCED, DUPLEX_UNFORCED, 3414 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3415 if (err) 3416 return err; 3417 3418 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3419 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3420 * tunneling, determine priority by looking at 802.1p and IP 3421 * priority fields (IP prio has precedence), and set STP state 3422 * to Forwarding. 3423 * 3424 * If this is the CPU link, use DSA or EDSA tagging depending 3425 * on which tagging mode was configured. 3426 * 3427 * If this is a link to another switch, use DSA tagging mode. 3428 * 3429 * If this is the upstream port for this switch, enable 3430 * forwarding of unknown unicasts and multicasts. 3431 */ 3432 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3433 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3434 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3435 * by a USER port to the CPU port to allow snooping. 3436 */ 3437 if (dsa_is_user_port(ds, port)) 3438 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3439 3440 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3441 if (err) 3442 return err; 3443 3444 err = mv88e6xxx_setup_port_mode(chip, port); 3445 if (err) 3446 return err; 3447 3448 err = mv88e6xxx_setup_egress_floods(chip, port); 3449 if (err) 3450 return err; 3451 3452 /* Port Control 2: don't force a good FCS, set the MTU size to 3453 * 10222 bytes, disable 802.1q tags checking, don't discard 3454 * tagged or untagged frames on this port, skip destination 3455 * address lookup on user ports, disable ARP mirroring and don't 3456 * send a copy of all transmitted/received frames on this port 3457 * to the CPU. 3458 */ 3459 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3460 if (err) 3461 return err; 3462 3463 err = mv88e6xxx_setup_upstream_port(chip, port); 3464 if (err) 3465 return err; 3466 3467 /* On chips that support it, set all downstream DSA ports' 3468 * VLAN policy to TRAP. In combination with loading 3469 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3470 * provides a better isolation barrier between standalone 3471 * ports, as the ATU is bypassed on any intermediate switches 3472 * between the incoming port and the CPU. 3473 */ 3474 if (dsa_is_downstream_port(ds, port) && 3475 chip->info->ops->port_set_policy) { 3476 err = chip->info->ops->port_set_policy(chip, port, 3477 MV88E6XXX_POLICY_MAPPING_VTU, 3478 MV88E6XXX_POLICY_ACTION_TRAP); 3479 if (err) 3480 return err; 3481 } 3482 3483 /* User ports start out in standalone mode and 802.1Q is 3484 * therefore disabled. On DSA ports, all valid VIDs are always 3485 * loaded in the VTU - therefore, enable 802.1Q in order to take 3486 * advantage of VLAN policy on chips that supports it. 3487 */ 3488 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3489 dsa_is_user_port(ds, port) ? 3490 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3491 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3492 if (err) 3493 return err; 3494 3495 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3496 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3497 * the first free FID. This will be used as the private PVID for 3498 * unbridged ports. Shared (DSA and CPU) ports must also be 3499 * members of this VID, in order to trap all frames assigned to 3500 * it to the CPU. 3501 */ 3502 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3503 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3504 false); 3505 if (err) 3506 return err; 3507 3508 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3509 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3510 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3511 * as the private PVID on ports under a VLAN-unaware bridge. 3512 * Shared (DSA and CPU) ports must also be members of it, to translate 3513 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3514 * relying on their port default FID. 3515 */ 3516 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3517 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3518 false); 3519 if (err) 3520 return err; 3521 3522 if (chip->info->ops->port_set_jumbo_size) { 3523 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3524 if (err) 3525 return err; 3526 } 3527 3528 /* Port Association Vector: disable automatic address learning 3529 * on all user ports since they start out in standalone 3530 * mode. When joining a bridge, learning will be configured to 3531 * match the bridge port settings. Enable learning on all 3532 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3533 * learning process. 3534 * 3535 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3536 * and RefreshLocked. I.e. setup standard automatic learning. 3537 */ 3538 if (dsa_is_user_port(ds, port)) 3539 reg = 0; 3540 else 3541 reg = 1 << port; 3542 3543 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3544 reg); 3545 if (err) 3546 return err; 3547 3548 /* Egress rate control 2: disable egress rate control. */ 3549 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3550 0x0000); 3551 if (err) 3552 return err; 3553 3554 if (chip->info->ops->port_pause_limit) { 3555 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3556 if (err) 3557 return err; 3558 } 3559 3560 if (chip->info->ops->port_disable_learn_limit) { 3561 err = chip->info->ops->port_disable_learn_limit(chip, port); 3562 if (err) 3563 return err; 3564 } 3565 3566 if (chip->info->ops->port_disable_pri_override) { 3567 err = chip->info->ops->port_disable_pri_override(chip, port); 3568 if (err) 3569 return err; 3570 } 3571 if (chip->info->ops->port_enable_tcam) { 3572 err = chip->info->ops->port_enable_tcam(chip, port); 3573 if (err) 3574 return err; 3575 } 3576 3577 if (chip->info->ops->port_tag_remap) { 3578 err = chip->info->ops->port_tag_remap(chip, port); 3579 if (err) 3580 return err; 3581 } 3582 3583 if (chip->info->ops->port_egress_rate_limiting) { 3584 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3585 if (err) 3586 return err; 3587 } 3588 3589 if (chip->info->ops->port_setup_message_port) { 3590 err = chip->info->ops->port_setup_message_port(chip, port); 3591 if (err) 3592 return err; 3593 } 3594 3595 /* Port based VLAN map: give each port the same default address 3596 * database, and allow bidirectional communication between the 3597 * CPU and DSA port(s), and the other ports. 3598 */ 3599 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3600 if (err) 3601 return err; 3602 3603 err = mv88e6xxx_port_vlan_map(chip, port); 3604 if (err) 3605 return err; 3606 3607 /* Default VLAN ID and priority: don't set a default VLAN 3608 * ID, and set the default packet priority to zero. 3609 */ 3610 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3611 } 3612 3613 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3614 { 3615 struct mv88e6xxx_chip *chip = ds->priv; 3616 3617 if (chip->info->ops->port_set_jumbo_size) 3618 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3619 else if (chip->info->ops->set_max_frame_size) 3620 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3621 return ETH_DATA_LEN; 3622 } 3623 3624 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3625 { 3626 struct mv88e6xxx_chip *chip = ds->priv; 3627 int ret = 0; 3628 3629 /* For families where we don't know how to alter the MTU, 3630 * just accept any value up to ETH_DATA_LEN 3631 */ 3632 if (!chip->info->ops->port_set_jumbo_size && 3633 !chip->info->ops->set_max_frame_size) { 3634 if (new_mtu > ETH_DATA_LEN) 3635 return -EINVAL; 3636 3637 return 0; 3638 } 3639 3640 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3641 new_mtu += EDSA_HLEN; 3642 3643 mv88e6xxx_reg_lock(chip); 3644 if (chip->info->ops->port_set_jumbo_size) 3645 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3646 else if (chip->info->ops->set_max_frame_size && 3647 dsa_is_cpu_port(ds, port)) 3648 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3649 mv88e6xxx_reg_unlock(chip); 3650 3651 return ret; 3652 } 3653 3654 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3655 unsigned int ageing_time) 3656 { 3657 struct mv88e6xxx_chip *chip = ds->priv; 3658 int err; 3659 3660 mv88e6xxx_reg_lock(chip); 3661 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3662 mv88e6xxx_reg_unlock(chip); 3663 3664 return err; 3665 } 3666 3667 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3668 { 3669 int err; 3670 3671 /* Initialize the statistics unit */ 3672 if (chip->info->ops->stats_set_histogram) { 3673 err = chip->info->ops->stats_set_histogram(chip); 3674 if (err) 3675 return err; 3676 } 3677 3678 return mv88e6xxx_g1_stats_clear(chip); 3679 } 3680 3681 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip) 3682 { 3683 u16 dummy; 3684 int err; 3685 3686 /* Workaround for erratum 3687 * 3.3 RGMII timing may be out of spec when transmit delay is enabled 3688 */ 3689 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000); 3690 if (err) 3691 return err; 3692 3693 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy); 3694 } 3695 3696 /* Check if the errata has already been applied. */ 3697 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3698 { 3699 int port; 3700 int err; 3701 u16 val; 3702 3703 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3704 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3705 if (err) { 3706 dev_err(chip->dev, 3707 "Error reading hidden register: %d\n", err); 3708 return false; 3709 } 3710 if (val != 0x01c0) 3711 return false; 3712 } 3713 3714 return true; 3715 } 3716 3717 /* The 6390 copper ports have an errata which require poking magic 3718 * values into undocumented hidden registers and then performing a 3719 * software reset. 3720 */ 3721 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3722 { 3723 int port; 3724 int err; 3725 3726 if (mv88e6390_setup_errata_applied(chip)) 3727 return 0; 3728 3729 /* Set the ports into blocking mode */ 3730 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3731 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3732 if (err) 3733 return err; 3734 } 3735 3736 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3737 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3738 if (err) 3739 return err; 3740 } 3741 3742 return mv88e6xxx_software_reset(chip); 3743 } 3744 3745 /* For MV88E6XXX_FAMILY_6352, perform reset on G1 control. 3746 * Also, read and cache G2 scratch register. 3747 */ 3748 static int mv88e6352_reset(struct mv88e6xxx_chip *chip) 3749 { 3750 int err; 3751 3752 err = mv88e6352_g1_reset(chip); 3753 if (err) 3754 return err; 3755 3756 return mv88e6352_g2_cache_global_scratch_config3(chip); 3757 } 3758 3759 /* prod_id for switch families which do not have a PHY model number */ 3760 static const u16 family_prod_id_table[] = { 3761 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3762 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3763 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3764 }; 3765 3766 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3767 { 3768 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3769 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3770 u16 prod_id; 3771 u16 val; 3772 int err; 3773 3774 if (!chip->info->ops->phy_read) 3775 return -EOPNOTSUPP; 3776 3777 mv88e6xxx_reg_lock(chip); 3778 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3779 mv88e6xxx_reg_unlock(chip); 3780 3781 /* Some internal PHYs don't have a model number. */ 3782 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3783 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3784 prod_id = family_prod_id_table[chip->info->family]; 3785 if (prod_id) 3786 val |= prod_id >> 4; 3787 } 3788 3789 return err ? err : val; 3790 } 3791 3792 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3793 int reg) 3794 { 3795 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3796 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3797 u16 val; 3798 int err; 3799 3800 if (!chip->info->ops->phy_read_c45) 3801 return -ENODEV; 3802 3803 mv88e6xxx_reg_lock(chip); 3804 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3805 mv88e6xxx_reg_unlock(chip); 3806 3807 return err ? err : val; 3808 } 3809 3810 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3811 { 3812 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3813 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3814 int err; 3815 3816 if (!chip->info->ops->phy_write) 3817 return -EOPNOTSUPP; 3818 3819 mv88e6xxx_reg_lock(chip); 3820 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3821 mv88e6xxx_reg_unlock(chip); 3822 3823 return err; 3824 } 3825 3826 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3827 int reg, u16 val) 3828 { 3829 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3830 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3831 int err; 3832 3833 if (!chip->info->ops->phy_write_c45) 3834 return -EOPNOTSUPP; 3835 3836 mv88e6xxx_reg_lock(chip); 3837 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3838 mv88e6xxx_reg_unlock(chip); 3839 3840 return err; 3841 } 3842 3843 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3844 struct device_node *np, 3845 bool external) 3846 { 3847 static int index; 3848 struct mv88e6xxx_mdio_bus *mdio_bus; 3849 struct mii_bus *bus; 3850 int err; 3851 3852 if (external) { 3853 mv88e6xxx_reg_lock(chip); 3854 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3855 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3856 else 3857 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3858 mv88e6xxx_reg_unlock(chip); 3859 3860 if (err) 3861 return err; 3862 } 3863 3864 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3865 if (!bus) 3866 return -ENOMEM; 3867 3868 mdio_bus = bus->priv; 3869 mdio_bus->bus = bus; 3870 mdio_bus->chip = chip; 3871 INIT_LIST_HEAD(&mdio_bus->list); 3872 mdio_bus->external = external; 3873 3874 if (np) { 3875 bus->name = np->full_name; 3876 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3877 } else { 3878 bus->name = "mv88e6xxx SMI"; 3879 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3880 } 3881 3882 bus->read = mv88e6xxx_mdio_read; 3883 bus->write = mv88e6xxx_mdio_write; 3884 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3885 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3886 bus->parent = chip->dev; 3887 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3888 mv88e6xxx_num_ports(chip) - 1, 3889 chip->info->phy_base_addr); 3890 3891 if (!external) { 3892 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3893 if (err) 3894 goto out; 3895 } 3896 3897 err = of_mdiobus_register(bus, np); 3898 if (err) { 3899 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3900 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3901 goto out; 3902 } 3903 3904 if (external) 3905 list_add_tail(&mdio_bus->list, &chip->mdios); 3906 else 3907 list_add(&mdio_bus->list, &chip->mdios); 3908 3909 return 0; 3910 3911 out: 3912 mdiobus_free(bus); 3913 return err; 3914 } 3915 3916 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3917 3918 { 3919 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3920 struct mii_bus *bus; 3921 3922 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3923 bus = mdio_bus->bus; 3924 3925 if (!mdio_bus->external) 3926 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3927 3928 mdiobus_unregister(bus); 3929 mdiobus_free(bus); 3930 } 3931 } 3932 3933 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3934 { 3935 struct device_node *np = chip->dev->of_node; 3936 struct device_node *child; 3937 int err; 3938 3939 /* Always register one mdio bus for the internal/default mdio 3940 * bus. This maybe represented in the device tree, but is 3941 * optional. 3942 */ 3943 child = of_get_child_by_name(np, "mdio"); 3944 err = mv88e6xxx_mdio_register(chip, child, false); 3945 of_node_put(child); 3946 if (err) 3947 return err; 3948 3949 /* Walk the device tree, and see if there are any other nodes 3950 * which say they are compatible with the external mdio 3951 * bus. 3952 */ 3953 for_each_available_child_of_node(np, child) { 3954 if (of_device_is_compatible( 3955 child, "marvell,mv88e6xxx-mdio-external")) { 3956 err = mv88e6xxx_mdio_register(chip, child, true); 3957 if (err) { 3958 mv88e6xxx_mdios_unregister(chip); 3959 of_node_put(child); 3960 return err; 3961 } 3962 } 3963 } 3964 3965 return 0; 3966 } 3967 3968 static int mv88e6xxx_tcam_setup(struct mv88e6xxx_chip *chip) 3969 { 3970 if (!mv88e6xxx_has_tcam(chip)) 3971 return 0; 3972 3973 return chip->info->ops->tcam_ops->flush_tcam(chip); 3974 } 3975 3976 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3977 { 3978 struct mv88e6xxx_chip *chip = ds->priv; 3979 3980 mv88e6xxx_teardown_devlink_params(ds); 3981 dsa_devlink_resources_unregister(ds); 3982 mv88e6xxx_teardown_devlink_regions_global(ds); 3983 mv88e6xxx_hwtstamp_free(chip); 3984 mv88e6xxx_ptp_free(chip); 3985 mv88e6xxx_flower_teardown(chip); 3986 mv88e6xxx_mdios_unregister(chip); 3987 } 3988 3989 static int mv88e6xxx_setup(struct dsa_switch *ds) 3990 { 3991 struct mv88e6xxx_chip *chip = ds->priv; 3992 u8 cmode; 3993 int err; 3994 int i; 3995 3996 err = mv88e6xxx_mdios_register(chip); 3997 if (err) 3998 return err; 3999 4000 chip->ds = ds; 4001 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 4002 4003 /* Since virtual bridges are mapped in the PVT, the number we support 4004 * depends on the physical switch topology. We need to let DSA figure 4005 * that out and therefore we cannot set this at dsa_register_switch() 4006 * time. 4007 */ 4008 if (mv88e6xxx_has_pvt(chip)) 4009 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 4010 ds->dst->last_switch - 1; 4011 4012 mv88e6xxx_reg_lock(chip); 4013 4014 if (chip->info->ops->setup_errata) { 4015 err = chip->info->ops->setup_errata(chip); 4016 if (err) 4017 goto unlock; 4018 } 4019 4020 /* Cache the cmode of each port. */ 4021 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4022 if (chip->info->ops->port_get_cmode) { 4023 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 4024 if (err) 4025 goto unlock; 4026 4027 chip->ports[i].cmode = cmode; 4028 } 4029 } 4030 4031 err = mv88e6xxx_vtu_setup(chip); 4032 if (err) 4033 goto unlock; 4034 4035 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 4036 * VTU, thereby also flushing the STU). 4037 */ 4038 err = mv88e6xxx_stu_setup(chip); 4039 if (err) 4040 goto unlock; 4041 4042 /* Setup Switch Port Registers */ 4043 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4044 if (dsa_is_unused_port(ds, i)) 4045 continue; 4046 4047 /* Prevent the use of an invalid port. */ 4048 if (mv88e6xxx_is_invalid_port(chip, i)) { 4049 dev_err(chip->dev, "port %d is invalid\n", i); 4050 err = -EINVAL; 4051 goto unlock; 4052 } 4053 4054 err = mv88e6xxx_setup_port(chip, i); 4055 if (err) 4056 goto unlock; 4057 } 4058 4059 err = mv88e6xxx_irl_setup(chip); 4060 if (err) 4061 goto unlock; 4062 4063 err = mv88e6xxx_mac_setup(chip); 4064 if (err) 4065 goto unlock; 4066 4067 err = mv88e6xxx_phy_setup(chip); 4068 if (err) 4069 goto unlock; 4070 4071 err = mv88e6xxx_pvt_setup(chip); 4072 if (err) 4073 goto unlock; 4074 4075 err = mv88e6xxx_atu_setup(chip); 4076 if (err) 4077 goto unlock; 4078 4079 err = mv88e6xxx_broadcast_setup(chip, 0); 4080 if (err) 4081 goto unlock; 4082 4083 err = mv88e6xxx_pot_setup(chip); 4084 if (err) 4085 goto unlock; 4086 4087 err = mv88e6xxx_rmu_setup(chip); 4088 if (err) 4089 goto unlock; 4090 4091 err = mv88e6xxx_rsvd2cpu_setup(chip); 4092 if (err) 4093 goto unlock; 4094 4095 err = mv88e6xxx_trunk_setup(chip); 4096 if (err) 4097 goto unlock; 4098 4099 err = mv88e6xxx_devmap_setup(chip); 4100 if (err) 4101 goto unlock; 4102 4103 err = mv88e6xxx_pri_setup(chip); 4104 if (err) 4105 goto unlock; 4106 4107 /* Setup PTP Hardware Clock and timestamping */ 4108 if (chip->info->ptp_support) { 4109 err = mv88e6xxx_ptp_setup(chip); 4110 if (err) 4111 goto unlock; 4112 4113 err = mv88e6xxx_hwtstamp_setup(chip); 4114 if (err) 4115 goto unlock; 4116 } 4117 4118 err = mv88e6xxx_stats_setup(chip); 4119 if (err) 4120 goto unlock; 4121 4122 err = mv88e6xxx_tcam_setup(chip); 4123 if (err) 4124 goto unlock; 4125 4126 unlock: 4127 mv88e6xxx_reg_unlock(chip); 4128 4129 if (err) 4130 goto out_hwtstamp; 4131 4132 /* Have to be called without holding the register lock, since 4133 * they take the devlink lock, and we later take the locks in 4134 * the reverse order when getting/setting parameters or 4135 * resource occupancy. 4136 */ 4137 err = mv88e6xxx_setup_devlink_resources(ds); 4138 if (err) 4139 goto out_hwtstamp; 4140 4141 err = mv88e6xxx_setup_devlink_params(ds); 4142 if (err) 4143 goto out_resources; 4144 4145 err = mv88e6xxx_setup_devlink_regions_global(ds); 4146 if (err) 4147 goto out_params; 4148 4149 return 0; 4150 4151 out_params: 4152 mv88e6xxx_teardown_devlink_params(ds); 4153 out_resources: 4154 dsa_devlink_resources_unregister(ds); 4155 out_hwtstamp: 4156 mv88e6xxx_hwtstamp_free(chip); 4157 mv88e6xxx_ptp_free(chip); 4158 mv88e6xxx_mdios_unregister(chip); 4159 4160 return err; 4161 } 4162 4163 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4164 { 4165 struct mv88e6xxx_chip *chip = ds->priv; 4166 int err; 4167 4168 if (chip->info->ops->pcs_ops && 4169 chip->info->ops->pcs_ops->pcs_init) { 4170 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4171 if (err) 4172 return err; 4173 } 4174 4175 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4176 } 4177 4178 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4179 { 4180 struct mv88e6xxx_chip *chip = ds->priv; 4181 4182 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4183 4184 if (chip->info->ops->pcs_ops && 4185 chip->info->ops->pcs_ops->pcs_teardown) 4186 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4187 } 4188 4189 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4190 { 4191 struct mv88e6xxx_chip *chip = ds->priv; 4192 4193 return chip->eeprom_len; 4194 } 4195 4196 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4197 struct ethtool_eeprom *eeprom, u8 *data) 4198 { 4199 struct mv88e6xxx_chip *chip = ds->priv; 4200 int err; 4201 4202 if (!chip->info->ops->get_eeprom) 4203 return -EOPNOTSUPP; 4204 4205 mv88e6xxx_reg_lock(chip); 4206 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4207 mv88e6xxx_reg_unlock(chip); 4208 4209 if (err) 4210 return err; 4211 4212 eeprom->magic = 0xc3ec4951; 4213 4214 return 0; 4215 } 4216 4217 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4218 struct ethtool_eeprom *eeprom, u8 *data) 4219 { 4220 struct mv88e6xxx_chip *chip = ds->priv; 4221 int err; 4222 4223 if (!chip->info->ops->set_eeprom) 4224 return -EOPNOTSUPP; 4225 4226 if (eeprom->magic != 0xc3ec4951) 4227 return -EINVAL; 4228 4229 mv88e6xxx_reg_lock(chip); 4230 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4231 mv88e6xxx_reg_unlock(chip); 4232 4233 return err; 4234 } 4235 4236 static const struct mv88e6xxx_ops mv88e6085_ops = { 4237 /* MV88E6XXX_FAMILY_6097 */ 4238 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4239 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4240 .irl_init_all = mv88e6352_g2_irl_init_all, 4241 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4242 .phy_read = mv88e6185_phy_ppu_read, 4243 .phy_write = mv88e6185_phy_ppu_write, 4244 .port_set_link = mv88e6xxx_port_set_link, 4245 .port_sync_link = mv88e6xxx_port_sync_link, 4246 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4247 .port_tag_remap = mv88e6095_port_tag_remap, 4248 .port_set_policy = mv88e6352_port_set_policy, 4249 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4250 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4251 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4252 .port_set_ether_type = mv88e6351_port_set_ether_type, 4253 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4254 .port_pause_limit = mv88e6097_port_pause_limit, 4255 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4256 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4257 .port_get_cmode = mv88e6185_port_get_cmode, 4258 .port_setup_message_port = mv88e6xxx_setup_message_port, 4259 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4260 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4261 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4262 .stats_get_strings = mv88e6095_stats_get_strings, 4263 .stats_get_stat = mv88e6095_stats_get_stat, 4264 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4265 .set_egress_port = mv88e6095_g1_set_egress_port, 4266 .watchdog_ops = &mv88e6097_watchdog_ops, 4267 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4268 .pot_clear = mv88e6xxx_g2_pot_clear, 4269 .ppu_enable = mv88e6185_g1_ppu_enable, 4270 .ppu_disable = mv88e6185_g1_ppu_disable, 4271 .reset = mv88e6185_g1_reset, 4272 .rmu_disable = mv88e6085_g1_rmu_disable, 4273 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4274 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4275 .stu_getnext = mv88e6352_g1_stu_getnext, 4276 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4277 .phylink_get_caps = mv88e6185_phylink_get_caps, 4278 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4279 }; 4280 4281 static const struct mv88e6xxx_ops mv88e6095_ops = { 4282 /* MV88E6XXX_FAMILY_6095 */ 4283 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4284 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4285 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4286 .phy_read = mv88e6185_phy_ppu_read, 4287 .phy_write = mv88e6185_phy_ppu_write, 4288 .port_set_link = mv88e6xxx_port_set_link, 4289 .port_sync_link = mv88e6185_port_sync_link, 4290 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4291 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4292 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4293 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4294 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4295 .port_get_cmode = mv88e6185_port_get_cmode, 4296 .port_setup_message_port = mv88e6xxx_setup_message_port, 4297 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4298 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4299 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4300 .stats_get_strings = mv88e6095_stats_get_strings, 4301 .stats_get_stat = mv88e6095_stats_get_stat, 4302 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4303 .ppu_enable = mv88e6185_g1_ppu_enable, 4304 .ppu_disable = mv88e6185_g1_ppu_disable, 4305 .reset = mv88e6185_g1_reset, 4306 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4307 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4308 .phylink_get_caps = mv88e6095_phylink_get_caps, 4309 .pcs_ops = &mv88e6185_pcs_ops, 4310 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4311 }; 4312 4313 static const struct mv88e6xxx_ops mv88e6097_ops = { 4314 /* MV88E6XXX_FAMILY_6097 */ 4315 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4316 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4317 .irl_init_all = mv88e6352_g2_irl_init_all, 4318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4319 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4320 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4321 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4322 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4323 .port_set_link = mv88e6xxx_port_set_link, 4324 .port_sync_link = mv88e6185_port_sync_link, 4325 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4326 .port_tag_remap = mv88e6095_port_tag_remap, 4327 .port_set_policy = mv88e6352_port_set_policy, 4328 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4329 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4330 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4331 .port_set_ether_type = mv88e6351_port_set_ether_type, 4332 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4333 .port_pause_limit = mv88e6097_port_pause_limit, 4334 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4335 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4336 .port_get_cmode = mv88e6185_port_get_cmode, 4337 .port_setup_message_port = mv88e6xxx_setup_message_port, 4338 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4339 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4340 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4341 .stats_get_strings = mv88e6095_stats_get_strings, 4342 .stats_get_stat = mv88e6095_stats_get_stat, 4343 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4344 .set_egress_port = mv88e6095_g1_set_egress_port, 4345 .watchdog_ops = &mv88e6097_watchdog_ops, 4346 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4347 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4348 .pot_clear = mv88e6xxx_g2_pot_clear, 4349 .reset = mv88e6352_g1_reset, 4350 .rmu_disable = mv88e6085_g1_rmu_disable, 4351 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4352 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4353 .phylink_get_caps = mv88e6095_phylink_get_caps, 4354 .pcs_ops = &mv88e6185_pcs_ops, 4355 .stu_getnext = mv88e6352_g1_stu_getnext, 4356 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4357 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4358 }; 4359 4360 static const struct mv88e6xxx_ops mv88e6123_ops = { 4361 /* MV88E6XXX_FAMILY_6165 */ 4362 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4363 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4364 .irl_init_all = mv88e6352_g2_irl_init_all, 4365 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4366 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4367 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4368 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4369 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4370 .port_set_link = mv88e6xxx_port_set_link, 4371 .port_sync_link = mv88e6xxx_port_sync_link, 4372 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4373 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4374 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4375 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4376 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4377 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4378 .port_get_cmode = mv88e6185_port_get_cmode, 4379 .port_setup_message_port = mv88e6xxx_setup_message_port, 4380 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4381 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4382 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4383 .stats_get_strings = mv88e6095_stats_get_strings, 4384 .stats_get_stat = mv88e6095_stats_get_stat, 4385 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4386 .set_egress_port = mv88e6095_g1_set_egress_port, 4387 .watchdog_ops = &mv88e6097_watchdog_ops, 4388 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4389 .pot_clear = mv88e6xxx_g2_pot_clear, 4390 .reset = mv88e6352_g1_reset, 4391 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4392 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4393 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4394 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4395 .stu_getnext = mv88e6352_g1_stu_getnext, 4396 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4397 .phylink_get_caps = mv88e6185_phylink_get_caps, 4398 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4399 }; 4400 4401 static const struct mv88e6xxx_ops mv88e6131_ops = { 4402 /* MV88E6XXX_FAMILY_6185 */ 4403 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4404 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4405 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4406 .phy_read = mv88e6185_phy_ppu_read, 4407 .phy_write = mv88e6185_phy_ppu_write, 4408 .port_set_link = mv88e6xxx_port_set_link, 4409 .port_sync_link = mv88e6xxx_port_sync_link, 4410 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4411 .port_tag_remap = mv88e6095_port_tag_remap, 4412 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4413 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4414 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4415 .port_set_ether_type = mv88e6351_port_set_ether_type, 4416 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4417 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4418 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4419 .port_pause_limit = mv88e6097_port_pause_limit, 4420 .port_set_pause = mv88e6185_port_set_pause, 4421 .port_get_cmode = mv88e6185_port_get_cmode, 4422 .port_setup_message_port = mv88e6xxx_setup_message_port, 4423 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4424 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4425 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4426 .stats_get_strings = mv88e6095_stats_get_strings, 4427 .stats_get_stat = mv88e6095_stats_get_stat, 4428 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4429 .set_egress_port = mv88e6095_g1_set_egress_port, 4430 .watchdog_ops = &mv88e6097_watchdog_ops, 4431 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4432 .ppu_enable = mv88e6185_g1_ppu_enable, 4433 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4434 .ppu_disable = mv88e6185_g1_ppu_disable, 4435 .reset = mv88e6185_g1_reset, 4436 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4437 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4438 .phylink_get_caps = mv88e6185_phylink_get_caps, 4439 }; 4440 4441 static const struct mv88e6xxx_ops mv88e6141_ops = { 4442 /* MV88E6XXX_FAMILY_6341 */ 4443 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4444 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4445 .irl_init_all = mv88e6352_g2_irl_init_all, 4446 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4447 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4448 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4449 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4450 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4451 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4452 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4453 .port_set_link = mv88e6xxx_port_set_link, 4454 .port_sync_link = mv88e6xxx_port_sync_link, 4455 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4456 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4457 .port_tag_remap = mv88e6095_port_tag_remap, 4458 .port_set_policy = mv88e6352_port_set_policy, 4459 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4460 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4461 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4462 .port_set_ether_type = mv88e6351_port_set_ether_type, 4463 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4464 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4465 .port_pause_limit = mv88e6097_port_pause_limit, 4466 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4467 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4468 .port_get_cmode = mv88e6352_port_get_cmode, 4469 .port_set_cmode = mv88e6341_port_set_cmode, 4470 .port_setup_message_port = mv88e6xxx_setup_message_port, 4471 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4472 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4473 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4474 .stats_get_strings = mv88e6320_stats_get_strings, 4475 .stats_get_stat = mv88e6390_stats_get_stat, 4476 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4477 .set_egress_port = mv88e6390_g1_set_egress_port, 4478 .watchdog_ops = &mv88e6390_watchdog_ops, 4479 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4480 .pot_clear = mv88e6xxx_g2_pot_clear, 4481 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4482 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4483 .reset = mv88e6352_g1_reset, 4484 .rmu_disable = mv88e6390_g1_rmu_disable, 4485 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4486 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4487 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4488 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4489 .stu_getnext = mv88e6352_g1_stu_getnext, 4490 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4491 .serdes_get_lane = mv88e6341_serdes_get_lane, 4492 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4493 .gpio_ops = &mv88e6352_gpio_ops, 4494 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4495 .serdes_get_strings = mv88e6390_serdes_get_strings, 4496 .serdes_get_stats = mv88e6390_serdes_get_stats, 4497 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4498 .serdes_get_regs = mv88e6390_serdes_get_regs, 4499 .phylink_get_caps = mv88e6341_phylink_get_caps, 4500 .pcs_ops = &mv88e6390_pcs_ops, 4501 }; 4502 4503 static const struct mv88e6xxx_ops mv88e6161_ops = { 4504 /* MV88E6XXX_FAMILY_6165 */ 4505 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4506 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4507 .irl_init_all = mv88e6352_g2_irl_init_all, 4508 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4509 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4510 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4511 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4512 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4513 .port_set_link = mv88e6xxx_port_set_link, 4514 .port_sync_link = mv88e6xxx_port_sync_link, 4515 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4516 .port_tag_remap = mv88e6095_port_tag_remap, 4517 .port_set_policy = mv88e6352_port_set_policy, 4518 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4519 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4520 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4521 .port_set_ether_type = mv88e6351_port_set_ether_type, 4522 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4523 .port_pause_limit = mv88e6097_port_pause_limit, 4524 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4525 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4526 .port_get_cmode = mv88e6185_port_get_cmode, 4527 .port_setup_message_port = mv88e6xxx_setup_message_port, 4528 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4529 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4530 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4531 .stats_get_strings = mv88e6095_stats_get_strings, 4532 .stats_get_stat = mv88e6095_stats_get_stat, 4533 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4534 .set_egress_port = mv88e6095_g1_set_egress_port, 4535 .watchdog_ops = &mv88e6097_watchdog_ops, 4536 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4537 .pot_clear = mv88e6xxx_g2_pot_clear, 4538 .reset = mv88e6352_g1_reset, 4539 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4540 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4541 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4542 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4543 .stu_getnext = mv88e6352_g1_stu_getnext, 4544 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4545 .avb_ops = &mv88e6165_avb_ops, 4546 .ptp_ops = &mv88e6165_ptp_ops, 4547 .phylink_get_caps = mv88e6185_phylink_get_caps, 4548 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4549 }; 4550 4551 static const struct mv88e6xxx_ops mv88e6165_ops = { 4552 /* MV88E6XXX_FAMILY_6165 */ 4553 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4554 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4555 .irl_init_all = mv88e6352_g2_irl_init_all, 4556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4557 .phy_read = mv88e6165_phy_read, 4558 .phy_write = mv88e6165_phy_write, 4559 .port_set_link = mv88e6xxx_port_set_link, 4560 .port_sync_link = mv88e6xxx_port_sync_link, 4561 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4562 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4563 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4564 .port_get_cmode = mv88e6185_port_get_cmode, 4565 .port_setup_message_port = mv88e6xxx_setup_message_port, 4566 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4567 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4568 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4569 .stats_get_strings = mv88e6095_stats_get_strings, 4570 .stats_get_stat = mv88e6095_stats_get_stat, 4571 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4572 .set_egress_port = mv88e6095_g1_set_egress_port, 4573 .watchdog_ops = &mv88e6097_watchdog_ops, 4574 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4575 .pot_clear = mv88e6xxx_g2_pot_clear, 4576 .reset = mv88e6352_g1_reset, 4577 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4578 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4579 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4580 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4581 .stu_getnext = mv88e6352_g1_stu_getnext, 4582 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4583 .avb_ops = &mv88e6165_avb_ops, 4584 .ptp_ops = &mv88e6165_ptp_ops, 4585 .phylink_get_caps = mv88e6185_phylink_get_caps, 4586 }; 4587 4588 static const struct mv88e6xxx_ops mv88e6171_ops = { 4589 /* MV88E6XXX_FAMILY_6351 */ 4590 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4591 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4592 .irl_init_all = mv88e6352_g2_irl_init_all, 4593 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4594 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4595 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4596 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4597 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4598 .port_set_link = mv88e6xxx_port_set_link, 4599 .port_sync_link = mv88e6xxx_port_sync_link, 4600 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4601 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4602 .port_tag_remap = mv88e6095_port_tag_remap, 4603 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4604 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4605 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4606 .port_set_ether_type = mv88e6351_port_set_ether_type, 4607 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4608 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4609 .port_pause_limit = mv88e6097_port_pause_limit, 4610 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4611 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4612 .port_get_cmode = mv88e6352_port_get_cmode, 4613 .port_setup_message_port = mv88e6xxx_setup_message_port, 4614 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4615 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4616 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4617 .stats_get_strings = mv88e6095_stats_get_strings, 4618 .stats_get_stat = mv88e6095_stats_get_stat, 4619 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4620 .set_egress_port = mv88e6095_g1_set_egress_port, 4621 .watchdog_ops = &mv88e6097_watchdog_ops, 4622 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4623 .pot_clear = mv88e6xxx_g2_pot_clear, 4624 .reset = mv88e6352_g1_reset, 4625 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4626 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4627 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4628 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4629 .stu_getnext = mv88e6352_g1_stu_getnext, 4630 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4631 .phylink_get_caps = mv88e6351_phylink_get_caps, 4632 }; 4633 4634 static const struct mv88e6xxx_ops mv88e6172_ops = { 4635 /* MV88E6XXX_FAMILY_6352 */ 4636 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4637 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4638 .irl_init_all = mv88e6352_g2_irl_init_all, 4639 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4640 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4641 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4642 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4643 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4644 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4645 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4646 .port_set_link = mv88e6xxx_port_set_link, 4647 .port_sync_link = mv88e6xxx_port_sync_link, 4648 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4649 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4650 .port_tag_remap = mv88e6095_port_tag_remap, 4651 .port_set_policy = mv88e6352_port_set_policy, 4652 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4653 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4654 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4655 .port_set_ether_type = mv88e6351_port_set_ether_type, 4656 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4657 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4658 .port_pause_limit = mv88e6097_port_pause_limit, 4659 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4660 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4661 .port_get_cmode = mv88e6352_port_get_cmode, 4662 .port_setup_leds = mv88e6xxx_port_setup_leds, 4663 .port_setup_message_port = mv88e6xxx_setup_message_port, 4664 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4665 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4666 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4667 .stats_get_strings = mv88e6095_stats_get_strings, 4668 .stats_get_stat = mv88e6095_stats_get_stat, 4669 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4670 .set_egress_port = mv88e6095_g1_set_egress_port, 4671 .watchdog_ops = &mv88e6097_watchdog_ops, 4672 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4673 .pot_clear = mv88e6xxx_g2_pot_clear, 4674 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4675 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4676 .reset = mv88e6352_reset, 4677 .rmu_disable = mv88e6352_g1_rmu_disable, 4678 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4679 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4680 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4681 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4682 .stu_getnext = mv88e6352_g1_stu_getnext, 4683 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4684 .serdes_get_lane = mv88e6352_serdes_get_lane, 4685 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4686 .serdes_get_regs = mv88e6352_serdes_get_regs, 4687 .gpio_ops = &mv88e6352_gpio_ops, 4688 .phylink_get_caps = mv88e6352_phylink_get_caps, 4689 .pcs_ops = &mv88e6352_pcs_ops, 4690 }; 4691 4692 static const struct mv88e6xxx_ops mv88e6175_ops = { 4693 /* MV88E6XXX_FAMILY_6351 */ 4694 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4695 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4696 .irl_init_all = mv88e6352_g2_irl_init_all, 4697 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4698 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4699 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4700 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4701 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4702 .port_set_link = mv88e6xxx_port_set_link, 4703 .port_sync_link = mv88e6xxx_port_sync_link, 4704 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4705 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4706 .port_tag_remap = mv88e6095_port_tag_remap, 4707 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4708 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4709 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4710 .port_set_ether_type = mv88e6351_port_set_ether_type, 4711 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4712 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4713 .port_pause_limit = mv88e6097_port_pause_limit, 4714 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4715 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4716 .port_get_cmode = mv88e6352_port_get_cmode, 4717 .port_setup_message_port = mv88e6xxx_setup_message_port, 4718 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4719 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4720 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4721 .stats_get_strings = mv88e6095_stats_get_strings, 4722 .stats_get_stat = mv88e6095_stats_get_stat, 4723 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4724 .set_egress_port = mv88e6095_g1_set_egress_port, 4725 .watchdog_ops = &mv88e6097_watchdog_ops, 4726 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4727 .pot_clear = mv88e6xxx_g2_pot_clear, 4728 .reset = mv88e6352_g1_reset, 4729 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4730 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4731 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4732 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4733 .stu_getnext = mv88e6352_g1_stu_getnext, 4734 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4735 .phylink_get_caps = mv88e6351_phylink_get_caps, 4736 }; 4737 4738 static const struct mv88e6xxx_ops mv88e6176_ops = { 4739 /* MV88E6XXX_FAMILY_6352 */ 4740 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4741 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4742 .irl_init_all = mv88e6352_g2_irl_init_all, 4743 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4744 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4745 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4746 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4747 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4748 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4749 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4750 .port_set_link = mv88e6xxx_port_set_link, 4751 .port_sync_link = mv88e6xxx_port_sync_link, 4752 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4753 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4754 .port_tag_remap = mv88e6095_port_tag_remap, 4755 .port_set_policy = mv88e6352_port_set_policy, 4756 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4757 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4758 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4759 .port_set_ether_type = mv88e6351_port_set_ether_type, 4760 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4761 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4762 .port_pause_limit = mv88e6097_port_pause_limit, 4763 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4764 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4765 .port_get_cmode = mv88e6352_port_get_cmode, 4766 .port_setup_leds = mv88e6xxx_port_setup_leds, 4767 .port_setup_message_port = mv88e6xxx_setup_message_port, 4768 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4769 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4770 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4771 .stats_get_strings = mv88e6095_stats_get_strings, 4772 .stats_get_stat = mv88e6095_stats_get_stat, 4773 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4774 .set_egress_port = mv88e6095_g1_set_egress_port, 4775 .watchdog_ops = &mv88e6097_watchdog_ops, 4776 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4777 .pot_clear = mv88e6xxx_g2_pot_clear, 4778 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4779 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4780 .reset = mv88e6352_reset, 4781 .rmu_disable = mv88e6352_g1_rmu_disable, 4782 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4783 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4784 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4785 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4786 .stu_getnext = mv88e6352_g1_stu_getnext, 4787 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4788 .serdes_get_lane = mv88e6352_serdes_get_lane, 4789 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4790 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4791 .serdes_get_regs = mv88e6352_serdes_get_regs, 4792 .gpio_ops = &mv88e6352_gpio_ops, 4793 .phylink_get_caps = mv88e6352_phylink_get_caps, 4794 .pcs_ops = &mv88e6352_pcs_ops, 4795 }; 4796 4797 static const struct mv88e6xxx_ops mv88e6185_ops = { 4798 /* MV88E6XXX_FAMILY_6185 */ 4799 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4800 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4801 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4802 .phy_read = mv88e6185_phy_ppu_read, 4803 .phy_write = mv88e6185_phy_ppu_write, 4804 .port_set_link = mv88e6xxx_port_set_link, 4805 .port_sync_link = mv88e6185_port_sync_link, 4806 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4807 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4808 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4809 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4810 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4811 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4812 .port_set_pause = mv88e6185_port_set_pause, 4813 .port_get_cmode = mv88e6185_port_get_cmode, 4814 .port_setup_message_port = mv88e6xxx_setup_message_port, 4815 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4816 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4817 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4818 .stats_get_strings = mv88e6095_stats_get_strings, 4819 .stats_get_stat = mv88e6095_stats_get_stat, 4820 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4821 .set_egress_port = mv88e6095_g1_set_egress_port, 4822 .watchdog_ops = &mv88e6097_watchdog_ops, 4823 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4824 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4825 .ppu_enable = mv88e6185_g1_ppu_enable, 4826 .ppu_disable = mv88e6185_g1_ppu_disable, 4827 .reset = mv88e6185_g1_reset, 4828 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4829 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4830 .phylink_get_caps = mv88e6185_phylink_get_caps, 4831 .pcs_ops = &mv88e6185_pcs_ops, 4832 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4833 }; 4834 4835 static const struct mv88e6xxx_ops mv88e6190_ops = { 4836 /* MV88E6XXX_FAMILY_6390 */ 4837 .setup_errata = mv88e6390_setup_errata, 4838 .irl_init_all = mv88e6390_g2_irl_init_all, 4839 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4840 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4841 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4842 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4843 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4844 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4845 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4846 .port_set_link = mv88e6xxx_port_set_link, 4847 .port_sync_link = mv88e6xxx_port_sync_link, 4848 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4849 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4850 .port_tag_remap = mv88e6390_port_tag_remap, 4851 .port_set_policy = mv88e6352_port_set_policy, 4852 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4853 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4854 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4855 .port_set_ether_type = mv88e6351_port_set_ether_type, 4856 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4857 .port_pause_limit = mv88e6390_port_pause_limit, 4858 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4859 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4860 .port_get_cmode = mv88e6352_port_get_cmode, 4861 .port_set_cmode = mv88e6390_port_set_cmode, 4862 .port_setup_message_port = mv88e6xxx_setup_message_port, 4863 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4864 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4865 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4866 .stats_get_strings = mv88e6320_stats_get_strings, 4867 .stats_get_stat = mv88e6390_stats_get_stat, 4868 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4869 .set_egress_port = mv88e6390_g1_set_egress_port, 4870 .watchdog_ops = &mv88e6390_watchdog_ops, 4871 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4872 .pot_clear = mv88e6xxx_g2_pot_clear, 4873 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4874 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4875 .reset = mv88e6352_g1_reset, 4876 .rmu_disable = mv88e6390_g1_rmu_disable, 4877 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4878 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4879 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4880 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4881 .stu_getnext = mv88e6390_g1_stu_getnext, 4882 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4883 .serdes_get_lane = mv88e6390_serdes_get_lane, 4884 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4885 .serdes_get_strings = mv88e6390_serdes_get_strings, 4886 .serdes_get_stats = mv88e6390_serdes_get_stats, 4887 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4888 .serdes_get_regs = mv88e6390_serdes_get_regs, 4889 .gpio_ops = &mv88e6352_gpio_ops, 4890 .phylink_get_caps = mv88e6390_phylink_get_caps, 4891 .pcs_ops = &mv88e6390_pcs_ops, 4892 }; 4893 4894 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4895 /* MV88E6XXX_FAMILY_6390 */ 4896 .setup_errata = mv88e6390_setup_errata, 4897 .irl_init_all = mv88e6390_g2_irl_init_all, 4898 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4899 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4900 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4901 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4902 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4903 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4904 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4905 .port_set_link = mv88e6xxx_port_set_link, 4906 .port_sync_link = mv88e6xxx_port_sync_link, 4907 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4908 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4909 .port_tag_remap = mv88e6390_port_tag_remap, 4910 .port_set_policy = mv88e6352_port_set_policy, 4911 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4912 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4913 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4914 .port_set_ether_type = mv88e6351_port_set_ether_type, 4915 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4916 .port_pause_limit = mv88e6390_port_pause_limit, 4917 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4918 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4919 .port_get_cmode = mv88e6352_port_get_cmode, 4920 .port_set_cmode = mv88e6390x_port_set_cmode, 4921 .port_setup_message_port = mv88e6xxx_setup_message_port, 4922 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4923 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4924 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4925 .stats_get_strings = mv88e6320_stats_get_strings, 4926 .stats_get_stat = mv88e6390_stats_get_stat, 4927 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4928 .set_egress_port = mv88e6390_g1_set_egress_port, 4929 .watchdog_ops = &mv88e6390_watchdog_ops, 4930 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4931 .pot_clear = mv88e6xxx_g2_pot_clear, 4932 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4933 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4934 .reset = mv88e6352_g1_reset, 4935 .rmu_disable = mv88e6390_g1_rmu_disable, 4936 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4937 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4938 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4939 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4940 .stu_getnext = mv88e6390_g1_stu_getnext, 4941 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4942 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4943 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4944 .serdes_get_strings = mv88e6390_serdes_get_strings, 4945 .serdes_get_stats = mv88e6390_serdes_get_stats, 4946 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4947 .serdes_get_regs = mv88e6390_serdes_get_regs, 4948 .gpio_ops = &mv88e6352_gpio_ops, 4949 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4950 .pcs_ops = &mv88e6390_pcs_ops, 4951 }; 4952 4953 static const struct mv88e6xxx_ops mv88e6191_ops = { 4954 /* MV88E6XXX_FAMILY_6390 */ 4955 .setup_errata = mv88e6390_setup_errata, 4956 .irl_init_all = mv88e6390_g2_irl_init_all, 4957 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4958 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4959 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4960 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4961 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4962 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4963 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4964 .port_set_link = mv88e6xxx_port_set_link, 4965 .port_sync_link = mv88e6xxx_port_sync_link, 4966 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4967 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4968 .port_tag_remap = mv88e6390_port_tag_remap, 4969 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4970 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4971 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4972 .port_set_ether_type = mv88e6351_port_set_ether_type, 4973 .port_pause_limit = mv88e6390_port_pause_limit, 4974 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4975 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4976 .port_get_cmode = mv88e6352_port_get_cmode, 4977 .port_set_cmode = mv88e6390_port_set_cmode, 4978 .port_setup_message_port = mv88e6xxx_setup_message_port, 4979 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4980 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4981 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4982 .stats_get_strings = mv88e6320_stats_get_strings, 4983 .stats_get_stat = mv88e6390_stats_get_stat, 4984 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4985 .set_egress_port = mv88e6390_g1_set_egress_port, 4986 .watchdog_ops = &mv88e6390_watchdog_ops, 4987 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4988 .pot_clear = mv88e6xxx_g2_pot_clear, 4989 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4990 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4991 .reset = mv88e6352_g1_reset, 4992 .rmu_disable = mv88e6390_g1_rmu_disable, 4993 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4994 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4995 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4996 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4997 .stu_getnext = mv88e6390_g1_stu_getnext, 4998 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4999 .serdes_get_lane = mv88e6390_serdes_get_lane, 5000 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5001 .serdes_get_strings = mv88e6390_serdes_get_strings, 5002 .serdes_get_stats = mv88e6390_serdes_get_stats, 5003 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5004 .serdes_get_regs = mv88e6390_serdes_get_regs, 5005 .avb_ops = &mv88e6390_avb_ops, 5006 .ptp_ops = &mv88e6352_ptp_ops, 5007 .phylink_get_caps = mv88e6390_phylink_get_caps, 5008 .pcs_ops = &mv88e6390_pcs_ops, 5009 }; 5010 5011 static const struct mv88e6xxx_ops mv88e6240_ops = { 5012 /* MV88E6XXX_FAMILY_6352 */ 5013 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5014 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5015 .irl_init_all = mv88e6352_g2_irl_init_all, 5016 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5017 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5018 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5019 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5020 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5021 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5022 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5023 .port_set_link = mv88e6xxx_port_set_link, 5024 .port_sync_link = mv88e6xxx_port_sync_link, 5025 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5026 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5027 .port_tag_remap = mv88e6095_port_tag_remap, 5028 .port_set_policy = mv88e6352_port_set_policy, 5029 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5030 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5031 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5032 .port_set_ether_type = mv88e6351_port_set_ether_type, 5033 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5034 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5035 .port_pause_limit = mv88e6097_port_pause_limit, 5036 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5037 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5038 .port_get_cmode = mv88e6352_port_get_cmode, 5039 .port_setup_leds = mv88e6xxx_port_setup_leds, 5040 .port_setup_message_port = mv88e6xxx_setup_message_port, 5041 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5042 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5043 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5044 .stats_get_strings = mv88e6095_stats_get_strings, 5045 .stats_get_stat = mv88e6095_stats_get_stat, 5046 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5047 .set_egress_port = mv88e6095_g1_set_egress_port, 5048 .watchdog_ops = &mv88e6097_watchdog_ops, 5049 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5050 .pot_clear = mv88e6xxx_g2_pot_clear, 5051 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5052 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5053 .reset = mv88e6352_reset, 5054 .rmu_disable = mv88e6352_g1_rmu_disable, 5055 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5056 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5057 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5058 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5059 .stu_getnext = mv88e6352_g1_stu_getnext, 5060 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5061 .serdes_get_lane = mv88e6352_serdes_get_lane, 5062 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5063 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5064 .serdes_get_regs = mv88e6352_serdes_get_regs, 5065 .gpio_ops = &mv88e6352_gpio_ops, 5066 .avb_ops = &mv88e6352_avb_ops, 5067 .ptp_ops = &mv88e6352_ptp_ops, 5068 .phylink_get_caps = mv88e6352_phylink_get_caps, 5069 .pcs_ops = &mv88e6352_pcs_ops, 5070 }; 5071 5072 static const struct mv88e6xxx_ops mv88e6250_ops = { 5073 /* MV88E6XXX_FAMILY_6250 */ 5074 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5075 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5076 .irl_init_all = mv88e6352_g2_irl_init_all, 5077 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5078 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5079 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5080 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5081 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5082 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5083 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5084 .port_set_link = mv88e6xxx_port_set_link, 5085 .port_sync_link = mv88e6xxx_port_sync_link, 5086 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5087 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5088 .port_tag_remap = mv88e6095_port_tag_remap, 5089 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5090 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5091 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5092 .port_set_ether_type = mv88e6351_port_set_ether_type, 5093 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5094 .port_pause_limit = mv88e6097_port_pause_limit, 5095 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5096 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5097 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5098 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5099 .stats_get_strings = mv88e6250_stats_get_strings, 5100 .stats_get_stat = mv88e6250_stats_get_stat, 5101 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5102 .set_egress_port = mv88e6095_g1_set_egress_port, 5103 .watchdog_ops = &mv88e6250_watchdog_ops, 5104 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5105 .pot_clear = mv88e6xxx_g2_pot_clear, 5106 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5107 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5108 .reset = mv88e6250_g1_reset, 5109 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5110 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5111 .avb_ops = &mv88e6352_avb_ops, 5112 .ptp_ops = &mv88e6352_ptp_ops, 5113 .phylink_get_caps = mv88e6250_phylink_get_caps, 5114 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5115 }; 5116 5117 static const struct mv88e6xxx_ops mv88e6290_ops = { 5118 /* MV88E6XXX_FAMILY_6390 */ 5119 .setup_errata = mv88e6390_setup_errata, 5120 .irl_init_all = mv88e6390_g2_irl_init_all, 5121 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5122 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5123 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5124 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5125 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5126 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5127 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5128 .port_set_link = mv88e6xxx_port_set_link, 5129 .port_sync_link = mv88e6xxx_port_sync_link, 5130 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5131 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5132 .port_tag_remap = mv88e6390_port_tag_remap, 5133 .port_set_policy = mv88e6352_port_set_policy, 5134 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5135 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5136 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5137 .port_set_ether_type = mv88e6351_port_set_ether_type, 5138 .port_pause_limit = mv88e6390_port_pause_limit, 5139 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5140 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5141 .port_get_cmode = mv88e6352_port_get_cmode, 5142 .port_set_cmode = mv88e6390_port_set_cmode, 5143 .port_setup_message_port = mv88e6xxx_setup_message_port, 5144 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5145 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5146 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5147 .stats_get_strings = mv88e6320_stats_get_strings, 5148 .stats_get_stat = mv88e6390_stats_get_stat, 5149 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5150 .set_egress_port = mv88e6390_g1_set_egress_port, 5151 .watchdog_ops = &mv88e6390_watchdog_ops, 5152 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5153 .pot_clear = mv88e6xxx_g2_pot_clear, 5154 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5155 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5156 .reset = mv88e6352_g1_reset, 5157 .rmu_disable = mv88e6390_g1_rmu_disable, 5158 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5159 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5160 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5161 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5162 .stu_getnext = mv88e6390_g1_stu_getnext, 5163 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5164 .serdes_get_lane = mv88e6390_serdes_get_lane, 5165 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5166 .serdes_get_strings = mv88e6390_serdes_get_strings, 5167 .serdes_get_stats = mv88e6390_serdes_get_stats, 5168 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5169 .serdes_get_regs = mv88e6390_serdes_get_regs, 5170 .gpio_ops = &mv88e6352_gpio_ops, 5171 .avb_ops = &mv88e6390_avb_ops, 5172 .ptp_ops = &mv88e6390_ptp_ops, 5173 .phylink_get_caps = mv88e6390_phylink_get_caps, 5174 .pcs_ops = &mv88e6390_pcs_ops, 5175 .tcam_ops = &mv88e6390_tcam_ops, 5176 }; 5177 5178 static const struct mv88e6xxx_ops mv88e6320_ops = { 5179 /* MV88E6XXX_FAMILY_6320 */ 5180 .setup_errata = mv88e6320_setup_errata, 5181 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5182 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5183 .irl_init_all = mv88e6352_g2_irl_init_all, 5184 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5185 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5186 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5187 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5188 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5189 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5190 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5191 .port_set_link = mv88e6xxx_port_set_link, 5192 .port_sync_link = mv88e6xxx_port_sync_link, 5193 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5194 .port_set_speed_duplex = mv88e6320_port_set_speed_duplex, 5195 .port_tag_remap = mv88e6095_port_tag_remap, 5196 .port_set_policy = mv88e6352_port_set_policy, 5197 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5198 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5199 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5200 .port_set_ether_type = mv88e6351_port_set_ether_type, 5201 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5202 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5203 .port_pause_limit = mv88e6097_port_pause_limit, 5204 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5205 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5206 .port_get_cmode = mv88e6352_port_get_cmode, 5207 .port_setup_message_port = mv88e6xxx_setup_message_port, 5208 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5209 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5210 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5211 .stats_get_strings = mv88e6320_stats_get_strings, 5212 .stats_get_stat = mv88e6320_stats_get_stat, 5213 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5214 .set_egress_port = mv88e6095_g1_set_egress_port, 5215 .watchdog_ops = &mv88e6390_watchdog_ops, 5216 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5217 .pot_clear = mv88e6xxx_g2_pot_clear, 5218 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5219 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5220 .reset = mv88e6352_g1_reset, 5221 .rmu_disable = mv88e6352_g1_rmu_disable, 5222 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5223 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5224 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5225 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5226 .stu_getnext = mv88e6352_g1_stu_getnext, 5227 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5228 .gpio_ops = &mv88e6352_gpio_ops, 5229 .avb_ops = &mv88e6352_avb_ops, 5230 .ptp_ops = &mv88e6352_ptp_ops, 5231 .phylink_get_caps = mv88e632x_phylink_get_caps, 5232 }; 5233 5234 static const struct mv88e6xxx_ops mv88e6321_ops = { 5235 /* MV88E6XXX_FAMILY_6320 */ 5236 .setup_errata = mv88e6320_setup_errata, 5237 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5238 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5239 .irl_init_all = mv88e6352_g2_irl_init_all, 5240 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5241 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5243 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5244 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5245 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5246 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5247 .port_set_link = mv88e6xxx_port_set_link, 5248 .port_sync_link = mv88e6xxx_port_sync_link, 5249 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5250 .port_set_speed_duplex = mv88e6320_port_set_speed_duplex, 5251 .port_tag_remap = mv88e6095_port_tag_remap, 5252 .port_set_policy = mv88e6352_port_set_policy, 5253 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5254 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5255 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5256 .port_set_ether_type = mv88e6351_port_set_ether_type, 5257 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5258 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5259 .port_pause_limit = mv88e6097_port_pause_limit, 5260 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5261 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5262 .port_get_cmode = mv88e6352_port_get_cmode, 5263 .port_setup_message_port = mv88e6xxx_setup_message_port, 5264 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5265 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5266 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5267 .stats_get_strings = mv88e6320_stats_get_strings, 5268 .stats_get_stat = mv88e6320_stats_get_stat, 5269 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5270 .set_egress_port = mv88e6095_g1_set_egress_port, 5271 .watchdog_ops = &mv88e6390_watchdog_ops, 5272 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5273 .pot_clear = mv88e6xxx_g2_pot_clear, 5274 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5275 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5276 .reset = mv88e6352_g1_reset, 5277 .rmu_disable = mv88e6352_g1_rmu_disable, 5278 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5279 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5280 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5281 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5282 .stu_getnext = mv88e6352_g1_stu_getnext, 5283 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5284 .serdes_get_lane = mv88e6321_serdes_get_lane, 5285 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5286 .serdes_get_regs = mv88e6352_serdes_get_regs, 5287 .gpio_ops = &mv88e6352_gpio_ops, 5288 .avb_ops = &mv88e6352_avb_ops, 5289 .ptp_ops = &mv88e6352_ptp_ops, 5290 .phylink_get_caps = mv88e632x_phylink_get_caps, 5291 .pcs_ops = &mv88e6352_pcs_ops, 5292 }; 5293 5294 static const struct mv88e6xxx_ops mv88e6341_ops = { 5295 /* MV88E6XXX_FAMILY_6341 */ 5296 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5297 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5298 .irl_init_all = mv88e6352_g2_irl_init_all, 5299 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5300 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5302 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5303 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5304 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5305 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5306 .port_set_link = mv88e6xxx_port_set_link, 5307 .port_sync_link = mv88e6xxx_port_sync_link, 5308 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5309 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5310 .port_tag_remap = mv88e6095_port_tag_remap, 5311 .port_set_policy = mv88e6352_port_set_policy, 5312 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5313 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5314 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5315 .port_set_ether_type = mv88e6351_port_set_ether_type, 5316 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5317 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5318 .port_pause_limit = mv88e6097_port_pause_limit, 5319 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5320 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5321 .port_get_cmode = mv88e6352_port_get_cmode, 5322 .port_set_cmode = mv88e6341_port_set_cmode, 5323 .port_setup_message_port = mv88e6xxx_setup_message_port, 5324 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5325 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5326 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5327 .stats_get_strings = mv88e6320_stats_get_strings, 5328 .stats_get_stat = mv88e6390_stats_get_stat, 5329 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5330 .set_egress_port = mv88e6390_g1_set_egress_port, 5331 .watchdog_ops = &mv88e6390_watchdog_ops, 5332 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5333 .pot_clear = mv88e6xxx_g2_pot_clear, 5334 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5335 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5336 .reset = mv88e6352_g1_reset, 5337 .rmu_disable = mv88e6390_g1_rmu_disable, 5338 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5339 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5340 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5341 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5342 .stu_getnext = mv88e6352_g1_stu_getnext, 5343 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5344 .serdes_get_lane = mv88e6341_serdes_get_lane, 5345 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5346 .gpio_ops = &mv88e6352_gpio_ops, 5347 .avb_ops = &mv88e6390_avb_ops, 5348 .ptp_ops = &mv88e6352_ptp_ops, 5349 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5350 .serdes_get_strings = mv88e6390_serdes_get_strings, 5351 .serdes_get_stats = mv88e6390_serdes_get_stats, 5352 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5353 .serdes_get_regs = mv88e6390_serdes_get_regs, 5354 .phylink_get_caps = mv88e6341_phylink_get_caps, 5355 .pcs_ops = &mv88e6390_pcs_ops, 5356 }; 5357 5358 static const struct mv88e6xxx_ops mv88e6350_ops = { 5359 /* MV88E6XXX_FAMILY_6351 */ 5360 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5361 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5362 .irl_init_all = mv88e6352_g2_irl_init_all, 5363 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5364 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5365 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5366 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5367 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5368 .port_set_link = mv88e6xxx_port_set_link, 5369 .port_sync_link = mv88e6xxx_port_sync_link, 5370 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5371 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5372 .port_tag_remap = mv88e6095_port_tag_remap, 5373 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5374 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5375 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5376 .port_set_ether_type = mv88e6351_port_set_ether_type, 5377 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5378 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5379 .port_pause_limit = mv88e6097_port_pause_limit, 5380 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5381 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5382 .port_get_cmode = mv88e6352_port_get_cmode, 5383 .port_setup_message_port = mv88e6xxx_setup_message_port, 5384 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5385 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5386 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5387 .stats_get_strings = mv88e6095_stats_get_strings, 5388 .stats_get_stat = mv88e6095_stats_get_stat, 5389 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5390 .set_egress_port = mv88e6095_g1_set_egress_port, 5391 .watchdog_ops = &mv88e6097_watchdog_ops, 5392 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5393 .pot_clear = mv88e6xxx_g2_pot_clear, 5394 .reset = mv88e6352_g1_reset, 5395 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5396 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5397 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5398 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5399 .stu_getnext = mv88e6352_g1_stu_getnext, 5400 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5401 .phylink_get_caps = mv88e6351_phylink_get_caps, 5402 }; 5403 5404 static const struct mv88e6xxx_ops mv88e6351_ops = { 5405 /* MV88E6XXX_FAMILY_6351 */ 5406 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5407 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5408 .irl_init_all = mv88e6352_g2_irl_init_all, 5409 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5410 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5411 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5412 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5413 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5414 .port_set_link = mv88e6xxx_port_set_link, 5415 .port_sync_link = mv88e6xxx_port_sync_link, 5416 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5417 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5418 .port_tag_remap = mv88e6095_port_tag_remap, 5419 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5420 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5421 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5422 .port_set_ether_type = mv88e6351_port_set_ether_type, 5423 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5424 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5425 .port_pause_limit = mv88e6097_port_pause_limit, 5426 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5427 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5428 .port_get_cmode = mv88e6352_port_get_cmode, 5429 .port_setup_message_port = mv88e6xxx_setup_message_port, 5430 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5431 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5432 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5433 .stats_get_strings = mv88e6095_stats_get_strings, 5434 .stats_get_stat = mv88e6095_stats_get_stat, 5435 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5436 .set_egress_port = mv88e6095_g1_set_egress_port, 5437 .watchdog_ops = &mv88e6097_watchdog_ops, 5438 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5439 .pot_clear = mv88e6xxx_g2_pot_clear, 5440 .reset = mv88e6352_g1_reset, 5441 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5442 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5443 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5444 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5445 .stu_getnext = mv88e6352_g1_stu_getnext, 5446 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5447 .avb_ops = &mv88e6352_avb_ops, 5448 .ptp_ops = &mv88e6352_ptp_ops, 5449 .phylink_get_caps = mv88e6351_phylink_get_caps, 5450 }; 5451 5452 static const struct mv88e6xxx_ops mv88e6352_ops = { 5453 /* MV88E6XXX_FAMILY_6352 */ 5454 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5455 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5456 .irl_init_all = mv88e6352_g2_irl_init_all, 5457 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5458 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5459 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5460 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5461 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5462 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5463 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5464 .port_set_link = mv88e6xxx_port_set_link, 5465 .port_sync_link = mv88e6xxx_port_sync_link, 5466 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5467 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5468 .port_tag_remap = mv88e6095_port_tag_remap, 5469 .port_set_policy = mv88e6352_port_set_policy, 5470 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5471 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5472 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5473 .port_set_ether_type = mv88e6351_port_set_ether_type, 5474 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5475 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5476 .port_pause_limit = mv88e6097_port_pause_limit, 5477 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5478 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5479 .port_get_cmode = mv88e6352_port_get_cmode, 5480 .port_setup_leds = mv88e6xxx_port_setup_leds, 5481 .port_setup_message_port = mv88e6xxx_setup_message_port, 5482 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5483 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5484 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5485 .stats_get_strings = mv88e6095_stats_get_strings, 5486 .stats_get_stat = mv88e6095_stats_get_stat, 5487 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5488 .set_egress_port = mv88e6095_g1_set_egress_port, 5489 .watchdog_ops = &mv88e6097_watchdog_ops, 5490 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5491 .pot_clear = mv88e6xxx_g2_pot_clear, 5492 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5493 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5494 .reset = mv88e6352_reset, 5495 .rmu_disable = mv88e6352_g1_rmu_disable, 5496 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5497 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5498 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5499 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5500 .stu_getnext = mv88e6352_g1_stu_getnext, 5501 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5502 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5503 .gpio_ops = &mv88e6352_gpio_ops, 5504 .avb_ops = &mv88e6352_avb_ops, 5505 .ptp_ops = &mv88e6352_ptp_ops, 5506 .serdes_get_lane = mv88e6352_serdes_get_lane, 5507 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5508 .serdes_get_strings = mv88e6352_serdes_get_strings, 5509 .serdes_get_stats = mv88e6352_serdes_get_stats, 5510 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5511 .serdes_get_regs = mv88e6352_serdes_get_regs, 5512 .phylink_get_caps = mv88e6352_phylink_get_caps, 5513 .pcs_ops = &mv88e6352_pcs_ops, 5514 }; 5515 5516 static const struct mv88e6xxx_ops mv88e6390_ops = { 5517 /* MV88E6XXX_FAMILY_6390 */ 5518 .setup_errata = mv88e6390_setup_errata, 5519 .irl_init_all = mv88e6390_g2_irl_init_all, 5520 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5521 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5522 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5523 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5524 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5525 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5526 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5527 .port_set_link = mv88e6xxx_port_set_link, 5528 .port_sync_link = mv88e6xxx_port_sync_link, 5529 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5530 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5531 .port_tag_remap = mv88e6390_port_tag_remap, 5532 .port_set_policy = mv88e6352_port_set_policy, 5533 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5534 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5535 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5536 .port_set_ether_type = mv88e6351_port_set_ether_type, 5537 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5538 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5539 .port_pause_limit = mv88e6390_port_pause_limit, 5540 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5541 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5542 .port_get_cmode = mv88e6352_port_get_cmode, 5543 .port_set_cmode = mv88e6390_port_set_cmode, 5544 .port_setup_message_port = mv88e6xxx_setup_message_port, 5545 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5546 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5547 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5548 .stats_get_strings = mv88e6320_stats_get_strings, 5549 .stats_get_stat = mv88e6390_stats_get_stat, 5550 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5551 .set_egress_port = mv88e6390_g1_set_egress_port, 5552 .watchdog_ops = &mv88e6390_watchdog_ops, 5553 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5554 .pot_clear = mv88e6xxx_g2_pot_clear, 5555 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5556 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5557 .reset = mv88e6352_g1_reset, 5558 .rmu_disable = mv88e6390_g1_rmu_disable, 5559 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5560 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5561 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5562 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5563 .stu_getnext = mv88e6390_g1_stu_getnext, 5564 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5565 .serdes_get_lane = mv88e6390_serdes_get_lane, 5566 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5567 .gpio_ops = &mv88e6352_gpio_ops, 5568 .avb_ops = &mv88e6390_avb_ops, 5569 .ptp_ops = &mv88e6390_ptp_ops, 5570 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5571 .serdes_get_strings = mv88e6390_serdes_get_strings, 5572 .serdes_get_stats = mv88e6390_serdes_get_stats, 5573 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5574 .serdes_get_regs = mv88e6390_serdes_get_regs, 5575 .phylink_get_caps = mv88e6390_phylink_get_caps, 5576 .pcs_ops = &mv88e6390_pcs_ops, 5577 .tcam_ops = &mv88e6390_tcam_ops, 5578 }; 5579 5580 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5581 /* MV88E6XXX_FAMILY_6390 */ 5582 .setup_errata = mv88e6390_setup_errata, 5583 .irl_init_all = mv88e6390_g2_irl_init_all, 5584 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5585 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5586 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5587 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5588 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5589 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5590 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5591 .port_set_link = mv88e6xxx_port_set_link, 5592 .port_sync_link = mv88e6xxx_port_sync_link, 5593 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5594 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5595 .port_tag_remap = mv88e6390_port_tag_remap, 5596 .port_set_policy = mv88e6352_port_set_policy, 5597 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5598 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5599 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5600 .port_set_ether_type = mv88e6351_port_set_ether_type, 5601 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5602 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5603 .port_pause_limit = mv88e6390_port_pause_limit, 5604 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5605 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5606 .port_get_cmode = mv88e6352_port_get_cmode, 5607 .port_set_cmode = mv88e6390x_port_set_cmode, 5608 .port_setup_message_port = mv88e6xxx_setup_message_port, 5609 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5610 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5611 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5612 .stats_get_strings = mv88e6320_stats_get_strings, 5613 .stats_get_stat = mv88e6390_stats_get_stat, 5614 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5615 .set_egress_port = mv88e6390_g1_set_egress_port, 5616 .watchdog_ops = &mv88e6390_watchdog_ops, 5617 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5618 .pot_clear = mv88e6xxx_g2_pot_clear, 5619 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5620 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5621 .reset = mv88e6352_g1_reset, 5622 .rmu_disable = mv88e6390_g1_rmu_disable, 5623 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5624 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5625 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5626 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5627 .stu_getnext = mv88e6390_g1_stu_getnext, 5628 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5629 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5630 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5631 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5632 .serdes_get_strings = mv88e6390_serdes_get_strings, 5633 .serdes_get_stats = mv88e6390_serdes_get_stats, 5634 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5635 .serdes_get_regs = mv88e6390_serdes_get_regs, 5636 .gpio_ops = &mv88e6352_gpio_ops, 5637 .avb_ops = &mv88e6390_avb_ops, 5638 .ptp_ops = &mv88e6390_ptp_ops, 5639 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5640 .pcs_ops = &mv88e6390_pcs_ops, 5641 }; 5642 5643 static const struct mv88e6xxx_ops mv88e6191x_ops = { 5644 /* MV88E6XXX_FAMILY_6393 without AVB and PTP: 6191X and 6193X */ 5645 .irl_init_all = mv88e6390_g2_irl_init_all, 5646 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5647 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5648 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5649 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5650 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5651 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5652 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5653 .port_set_link = mv88e6xxx_port_set_link, 5654 .port_sync_link = mv88e6xxx_port_sync_link, 5655 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5656 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5657 .port_tag_remap = mv88e6390_port_tag_remap, 5658 .port_set_policy = mv88e6393x_port_set_policy, 5659 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5660 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5661 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5662 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5663 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5664 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5665 .port_pause_limit = mv88e6390_port_pause_limit, 5666 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5667 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5668 .port_get_cmode = mv88e6352_port_get_cmode, 5669 .port_set_cmode = mv88e6393x_port_set_cmode, 5670 .port_setup_message_port = mv88e6xxx_setup_message_port, 5671 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5672 .port_enable_tcam = mv88e6xxx_port_enable_tcam, 5673 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5674 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5675 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5676 .stats_get_strings = mv88e6320_stats_get_strings, 5677 .stats_get_stat = mv88e6390_stats_get_stat, 5678 /* .set_cpu_port is missing because this family does not support a global 5679 * CPU port, only per port CPU port which is set via 5680 * .port_set_upstream_port method. 5681 */ 5682 .set_egress_port = mv88e6393x_set_egress_port, 5683 .watchdog_ops = &mv88e6393x_watchdog_ops, 5684 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5685 .pot_clear = mv88e6xxx_g2_pot_clear, 5686 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5687 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5688 .reset = mv88e6352_g1_reset, 5689 .rmu_disable = mv88e6390_g1_rmu_disable, 5690 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5691 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5692 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5693 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5694 .stu_getnext = mv88e6390_g1_stu_getnext, 5695 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5696 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5697 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5698 /* TODO: serdes stats */ 5699 .gpio_ops = &mv88e6352_gpio_ops, 5700 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5701 .pcs_ops = &mv88e6393x_pcs_ops, 5702 .tcam_ops = &mv88e6393_tcam_ops, 5703 }; 5704 5705 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5706 /* MV88E6XXX_FAMILY_6393 */ 5707 .irl_init_all = mv88e6390_g2_irl_init_all, 5708 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5709 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5710 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5711 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5712 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5713 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5714 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5715 .port_set_link = mv88e6xxx_port_set_link, 5716 .port_sync_link = mv88e6xxx_port_sync_link, 5717 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5718 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5719 .port_tag_remap = mv88e6390_port_tag_remap, 5720 .port_set_policy = mv88e6393x_port_set_policy, 5721 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5722 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5723 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5724 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5725 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5726 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5727 .port_pause_limit = mv88e6390_port_pause_limit, 5728 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5729 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5730 .port_get_cmode = mv88e6352_port_get_cmode, 5731 .port_set_cmode = mv88e6393x_port_set_cmode, 5732 .port_setup_message_port = mv88e6xxx_setup_message_port, 5733 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5734 .port_enable_tcam = mv88e6xxx_port_enable_tcam, 5735 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5736 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5737 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5738 .stats_get_strings = mv88e6320_stats_get_strings, 5739 .stats_get_stat = mv88e6390_stats_get_stat, 5740 /* .set_cpu_port is missing because this family does not support a global 5741 * CPU port, only per port CPU port which is set via 5742 * .port_set_upstream_port method. 5743 */ 5744 .set_egress_port = mv88e6393x_set_egress_port, 5745 .watchdog_ops = &mv88e6393x_watchdog_ops, 5746 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5747 .pot_clear = mv88e6xxx_g2_pot_clear, 5748 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5749 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5750 .reset = mv88e6352_g1_reset, 5751 .rmu_disable = mv88e6390_g1_rmu_disable, 5752 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5753 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5754 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5755 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5756 .stu_getnext = mv88e6390_g1_stu_getnext, 5757 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5758 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5759 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5760 /* TODO: serdes stats */ 5761 .gpio_ops = &mv88e6352_gpio_ops, 5762 .avb_ops = &mv88e6390_avb_ops, 5763 .ptp_ops = &mv88e6352_ptp_ops, 5764 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5765 .pcs_ops = &mv88e6393x_pcs_ops, 5766 .tcam_ops = &mv88e6393_tcam_ops, 5767 }; 5768 5769 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5770 [MV88E6020] = { 5771 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5772 .family = MV88E6XXX_FAMILY_6250, 5773 .name = "Marvell 88E6020", 5774 .num_databases = 64, 5775 /* Ports 2-4 are not routed to pins 5776 * => usable ports 0, 1, 5, 6 5777 */ 5778 .num_ports = 7, 5779 .num_internal_phys = 2, 5780 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5781 .max_vid = 4095, 5782 .port_base_addr = 0x8, 5783 .phy_base_addr = 0x0, 5784 .global1_addr = 0xf, 5785 .global2_addr = 0x7, 5786 .age_time_coeff = 15000, 5787 .g1_irqs = 9, 5788 .g2_irqs = 5, 5789 .stats_type = STATS_TYPE_BANK0, 5790 .atu_move_port_mask = 0xf, 5791 .dual_chip = true, 5792 .ops = &mv88e6250_ops, 5793 }, 5794 5795 [MV88E6071] = { 5796 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5797 .family = MV88E6XXX_FAMILY_6250, 5798 .name = "Marvell 88E6071", 5799 .num_databases = 64, 5800 .num_ports = 7, 5801 .num_internal_phys = 5, 5802 .max_vid = 4095, 5803 .port_base_addr = 0x08, 5804 .phy_base_addr = 0x00, 5805 .global1_addr = 0x0f, 5806 .global2_addr = 0x07, 5807 .age_time_coeff = 15000, 5808 .g1_irqs = 9, 5809 .g2_irqs = 5, 5810 .stats_type = STATS_TYPE_BANK0, 5811 .atu_move_port_mask = 0xf, 5812 .dual_chip = true, 5813 .ops = &mv88e6250_ops, 5814 }, 5815 5816 [MV88E6085] = { 5817 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5818 .family = MV88E6XXX_FAMILY_6097, 5819 .name = "Marvell 88E6085", 5820 .num_databases = 4096, 5821 .num_macs = 8192, 5822 .num_ports = 10, 5823 .num_internal_phys = 5, 5824 .max_vid = 4095, 5825 .max_sid = 63, 5826 .port_base_addr = 0x10, 5827 .phy_base_addr = 0x0, 5828 .global1_addr = 0x1b, 5829 .global2_addr = 0x1c, 5830 .age_time_coeff = 15000, 5831 .g1_irqs = 8, 5832 .g2_irqs = 10, 5833 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5834 .atu_move_port_mask = 0xf, 5835 .pvt = true, 5836 .multi_chip = true, 5837 .ops = &mv88e6085_ops, 5838 }, 5839 5840 [MV88E6095] = { 5841 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5842 .family = MV88E6XXX_FAMILY_6095, 5843 .name = "Marvell 88E6095/88E6095F", 5844 .num_databases = 256, 5845 .num_macs = 8192, 5846 .num_ports = 11, 5847 .num_internal_phys = 0, 5848 .max_vid = 4095, 5849 .port_base_addr = 0x10, 5850 .phy_base_addr = 0x0, 5851 .global1_addr = 0x1b, 5852 .global2_addr = 0x1c, 5853 .age_time_coeff = 15000, 5854 .g1_irqs = 8, 5855 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5856 .atu_move_port_mask = 0xf, 5857 .multi_chip = true, 5858 .ops = &mv88e6095_ops, 5859 }, 5860 5861 [MV88E6097] = { 5862 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5863 .family = MV88E6XXX_FAMILY_6097, 5864 .name = "Marvell 88E6097/88E6097F", 5865 .num_databases = 4096, 5866 .num_macs = 8192, 5867 .num_ports = 11, 5868 .num_internal_phys = 8, 5869 .max_vid = 4095, 5870 .max_sid = 63, 5871 .port_base_addr = 0x10, 5872 .phy_base_addr = 0x0, 5873 .global1_addr = 0x1b, 5874 .global2_addr = 0x1c, 5875 .age_time_coeff = 15000, 5876 .g1_irqs = 8, 5877 .g2_irqs = 10, 5878 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5879 .atu_move_port_mask = 0xf, 5880 .pvt = true, 5881 .multi_chip = true, 5882 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5883 .ops = &mv88e6097_ops, 5884 }, 5885 5886 [MV88E6123] = { 5887 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5888 .family = MV88E6XXX_FAMILY_6165, 5889 .name = "Marvell 88E6123", 5890 .num_databases = 4096, 5891 .num_macs = 1024, 5892 .num_ports = 3, 5893 .num_internal_phys = 5, 5894 .max_vid = 4095, 5895 .max_sid = 63, 5896 .port_base_addr = 0x10, 5897 .phy_base_addr = 0x0, 5898 .global1_addr = 0x1b, 5899 .global2_addr = 0x1c, 5900 .age_time_coeff = 15000, 5901 .g1_irqs = 9, 5902 .g2_irqs = 10, 5903 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5904 .atu_move_port_mask = 0xf, 5905 .pvt = true, 5906 .multi_chip = true, 5907 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5908 .ops = &mv88e6123_ops, 5909 }, 5910 5911 [MV88E6131] = { 5912 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5913 .family = MV88E6XXX_FAMILY_6185, 5914 .name = "Marvell 88E6131", 5915 .num_databases = 256, 5916 .num_macs = 8192, 5917 .num_ports = 8, 5918 .num_internal_phys = 0, 5919 .max_vid = 4095, 5920 .port_base_addr = 0x10, 5921 .phy_base_addr = 0x0, 5922 .global1_addr = 0x1b, 5923 .global2_addr = 0x1c, 5924 .age_time_coeff = 15000, 5925 .g1_irqs = 9, 5926 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5927 .atu_move_port_mask = 0xf, 5928 .multi_chip = true, 5929 .ops = &mv88e6131_ops, 5930 }, 5931 5932 [MV88E6141] = { 5933 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5934 .family = MV88E6XXX_FAMILY_6341, 5935 .name = "Marvell 88E6141", 5936 .num_databases = 256, 5937 .num_macs = 2048, 5938 .num_ports = 6, 5939 .num_internal_phys = 5, 5940 .num_gpio = 11, 5941 .max_vid = 4095, 5942 .max_sid = 63, 5943 .port_base_addr = 0x10, 5944 .phy_base_addr = 0x10, 5945 .global1_addr = 0x1b, 5946 .global2_addr = 0x1c, 5947 .age_time_coeff = 3750, 5948 .atu_move_port_mask = 0xf, 5949 .g1_irqs = 9, 5950 .g2_irqs = 10, 5951 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5952 .pvt = true, 5953 .multi_chip = true, 5954 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5955 .ops = &mv88e6141_ops, 5956 }, 5957 5958 [MV88E6161] = { 5959 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5960 .family = MV88E6XXX_FAMILY_6165, 5961 .name = "Marvell 88E6161", 5962 .num_databases = 4096, 5963 .num_macs = 1024, 5964 .num_ports = 6, 5965 .num_internal_phys = 5, 5966 .max_vid = 4095, 5967 .max_sid = 63, 5968 .port_base_addr = 0x10, 5969 .phy_base_addr = 0x0, 5970 .global1_addr = 0x1b, 5971 .global2_addr = 0x1c, 5972 .age_time_coeff = 15000, 5973 .g1_irqs = 9, 5974 .g2_irqs = 10, 5975 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5976 .atu_move_port_mask = 0xf, 5977 .pvt = true, 5978 .multi_chip = true, 5979 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5980 .ptp_support = true, 5981 .ops = &mv88e6161_ops, 5982 }, 5983 5984 [MV88E6165] = { 5985 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5986 .family = MV88E6XXX_FAMILY_6165, 5987 .name = "Marvell 88E6165", 5988 .num_databases = 4096, 5989 .num_macs = 8192, 5990 .num_ports = 6, 5991 .num_internal_phys = 0, 5992 .max_vid = 4095, 5993 .max_sid = 63, 5994 .port_base_addr = 0x10, 5995 .phy_base_addr = 0x0, 5996 .global1_addr = 0x1b, 5997 .global2_addr = 0x1c, 5998 .age_time_coeff = 15000, 5999 .g1_irqs = 9, 6000 .g2_irqs = 10, 6001 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6002 .atu_move_port_mask = 0xf, 6003 .pvt = true, 6004 .multi_chip = true, 6005 .ptp_support = true, 6006 .ops = &mv88e6165_ops, 6007 }, 6008 6009 [MV88E6171] = { 6010 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 6011 .family = MV88E6XXX_FAMILY_6351, 6012 .name = "Marvell 88E6171", 6013 .num_databases = 4096, 6014 .num_macs = 8192, 6015 .num_ports = 7, 6016 .num_internal_phys = 5, 6017 .max_vid = 4095, 6018 .max_sid = 63, 6019 .port_base_addr = 0x10, 6020 .phy_base_addr = 0x0, 6021 .global1_addr = 0x1b, 6022 .global2_addr = 0x1c, 6023 .age_time_coeff = 15000, 6024 .g1_irqs = 9, 6025 .g2_irqs = 10, 6026 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6027 .atu_move_port_mask = 0xf, 6028 .pvt = true, 6029 .multi_chip = true, 6030 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6031 .ops = &mv88e6171_ops, 6032 }, 6033 6034 [MV88E6172] = { 6035 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 6036 .family = MV88E6XXX_FAMILY_6352, 6037 .name = "Marvell 88E6172", 6038 .num_databases = 4096, 6039 .num_macs = 8192, 6040 .num_ports = 7, 6041 .num_internal_phys = 5, 6042 .num_gpio = 15, 6043 .max_vid = 4095, 6044 .max_sid = 63, 6045 .port_base_addr = 0x10, 6046 .phy_base_addr = 0x0, 6047 .global1_addr = 0x1b, 6048 .global2_addr = 0x1c, 6049 .age_time_coeff = 15000, 6050 .g1_irqs = 9, 6051 .g2_irqs = 10, 6052 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6053 .atu_move_port_mask = 0xf, 6054 .pvt = true, 6055 .multi_chip = true, 6056 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6057 .ops = &mv88e6172_ops, 6058 }, 6059 6060 [MV88E6175] = { 6061 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 6062 .family = MV88E6XXX_FAMILY_6351, 6063 .name = "Marvell 88E6175", 6064 .num_databases = 4096, 6065 .num_macs = 8192, 6066 .num_ports = 7, 6067 .num_internal_phys = 5, 6068 .max_vid = 4095, 6069 .max_sid = 63, 6070 .port_base_addr = 0x10, 6071 .phy_base_addr = 0x0, 6072 .global1_addr = 0x1b, 6073 .global2_addr = 0x1c, 6074 .age_time_coeff = 15000, 6075 .g1_irqs = 9, 6076 .g2_irqs = 10, 6077 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6078 .atu_move_port_mask = 0xf, 6079 .pvt = true, 6080 .multi_chip = true, 6081 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6082 .ops = &mv88e6175_ops, 6083 }, 6084 6085 [MV88E6176] = { 6086 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 6087 .family = MV88E6XXX_FAMILY_6352, 6088 .name = "Marvell 88E6176", 6089 .num_databases = 4096, 6090 .num_macs = 8192, 6091 .num_ports = 7, 6092 .num_internal_phys = 5, 6093 .num_gpio = 15, 6094 .max_vid = 4095, 6095 .max_sid = 63, 6096 .port_base_addr = 0x10, 6097 .phy_base_addr = 0x0, 6098 .global1_addr = 0x1b, 6099 .global2_addr = 0x1c, 6100 .age_time_coeff = 15000, 6101 .g1_irqs = 9, 6102 .g2_irqs = 10, 6103 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6104 .atu_move_port_mask = 0xf, 6105 .pvt = true, 6106 .multi_chip = true, 6107 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6108 .ops = &mv88e6176_ops, 6109 }, 6110 6111 [MV88E6185] = { 6112 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 6113 .family = MV88E6XXX_FAMILY_6185, 6114 .name = "Marvell 88E6185", 6115 .num_databases = 256, 6116 .num_macs = 8192, 6117 .num_ports = 10, 6118 .num_internal_phys = 0, 6119 .max_vid = 4095, 6120 .port_base_addr = 0x10, 6121 .phy_base_addr = 0x0, 6122 .global1_addr = 0x1b, 6123 .global2_addr = 0x1c, 6124 .age_time_coeff = 15000, 6125 .g1_irqs = 8, 6126 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6127 .atu_move_port_mask = 0xf, 6128 .multi_chip = true, 6129 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6130 .ops = &mv88e6185_ops, 6131 }, 6132 6133 [MV88E6190] = { 6134 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 6135 .family = MV88E6XXX_FAMILY_6390, 6136 .name = "Marvell 88E6190", 6137 .num_databases = 4096, 6138 .num_macs = 16384, 6139 .num_ports = 11, /* 10 + Z80 */ 6140 .num_internal_phys = 9, 6141 .num_gpio = 16, 6142 .max_vid = 8191, 6143 .max_sid = 63, 6144 .port_base_addr = 0x0, 6145 .phy_base_addr = 0x0, 6146 .global1_addr = 0x1b, 6147 .global2_addr = 0x1c, 6148 .age_time_coeff = 3750, 6149 .g1_irqs = 9, 6150 .g2_irqs = 14, 6151 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6152 .pvt = true, 6153 .multi_chip = true, 6154 .atu_move_port_mask = 0x1f, 6155 .ops = &mv88e6190_ops, 6156 }, 6157 6158 [MV88E6190X] = { 6159 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6160 .family = MV88E6XXX_FAMILY_6390, 6161 .name = "Marvell 88E6190X", 6162 .num_databases = 4096, 6163 .num_macs = 16384, 6164 .num_ports = 11, /* 10 + Z80 */ 6165 .num_internal_phys = 9, 6166 .num_gpio = 16, 6167 .max_vid = 8191, 6168 .max_sid = 63, 6169 .port_base_addr = 0x0, 6170 .phy_base_addr = 0x0, 6171 .global1_addr = 0x1b, 6172 .global2_addr = 0x1c, 6173 .age_time_coeff = 3750, 6174 .g1_irqs = 9, 6175 .g2_irqs = 14, 6176 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6177 .atu_move_port_mask = 0x1f, 6178 .pvt = true, 6179 .multi_chip = true, 6180 .ops = &mv88e6190x_ops, 6181 }, 6182 6183 [MV88E6191] = { 6184 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6185 .family = MV88E6XXX_FAMILY_6390, 6186 .name = "Marvell 88E6191", 6187 .num_databases = 4096, 6188 .num_macs = 16384, 6189 .num_ports = 11, /* 10 + Z80 */ 6190 .num_internal_phys = 9, 6191 .max_vid = 8191, 6192 .max_sid = 63, 6193 .port_base_addr = 0x0, 6194 .phy_base_addr = 0x0, 6195 .global1_addr = 0x1b, 6196 .global2_addr = 0x1c, 6197 .age_time_coeff = 3750, 6198 .g1_irqs = 9, 6199 .g2_irqs = 14, 6200 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6201 .atu_move_port_mask = 0x1f, 6202 .pvt = true, 6203 .multi_chip = true, 6204 .ptp_support = true, 6205 .ops = &mv88e6191_ops, 6206 }, 6207 6208 [MV88E6191X] = { 6209 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6210 .family = MV88E6XXX_FAMILY_6393, 6211 .name = "Marvell 88E6191X", 6212 .num_databases = 4096, 6213 .num_ports = 11, /* 10 + Z80 */ 6214 .num_internal_phys = 8, 6215 .internal_phys_offset = 1, 6216 .max_vid = 8191, 6217 .max_sid = 63, 6218 .port_base_addr = 0x0, 6219 .phy_base_addr = 0x0, 6220 .global1_addr = 0x1b, 6221 .global2_addr = 0x1c, 6222 .age_time_coeff = 3750, 6223 .g1_irqs = 10, 6224 .g2_irqs = 14, 6225 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6226 .atu_move_port_mask = 0x1f, 6227 .pvt = true, 6228 .multi_chip = true, 6229 .ops = &mv88e6191x_ops, 6230 }, 6231 6232 [MV88E6193X] = { 6233 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6234 .family = MV88E6XXX_FAMILY_6393, 6235 .name = "Marvell 88E6193X", 6236 .num_databases = 4096, 6237 .num_ports = 11, /* 10 + Z80 */ 6238 .num_internal_phys = 8, 6239 .num_tcam_entries = 256, 6240 .internal_phys_offset = 1, 6241 .max_vid = 8191, 6242 .max_sid = 63, 6243 .port_base_addr = 0x0, 6244 .phy_base_addr = 0x0, 6245 .global1_addr = 0x1b, 6246 .global2_addr = 0x1c, 6247 .tcam_addr = 0x1f, 6248 .age_time_coeff = 3750, 6249 .g1_irqs = 10, 6250 .g2_irqs = 14, 6251 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6252 .atu_move_port_mask = 0x1f, 6253 .pvt = true, 6254 .multi_chip = true, 6255 .ops = &mv88e6191x_ops, 6256 }, 6257 6258 [MV88E6220] = { 6259 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6260 .family = MV88E6XXX_FAMILY_6250, 6261 .name = "Marvell 88E6220", 6262 .num_databases = 64, 6263 6264 /* Ports 2-4 are not routed to pins 6265 * => usable ports 0, 1, 5, 6 6266 */ 6267 .num_ports = 7, 6268 .num_internal_phys = 2, 6269 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6270 .max_vid = 4095, 6271 .port_base_addr = 0x08, 6272 .phy_base_addr = 0x00, 6273 .global1_addr = 0x0f, 6274 .global2_addr = 0x07, 6275 .age_time_coeff = 15000, 6276 .g1_irqs = 9, 6277 .g2_irqs = 10, 6278 .stats_type = STATS_TYPE_BANK0, 6279 .atu_move_port_mask = 0xf, 6280 .dual_chip = true, 6281 .ptp_support = true, 6282 .ops = &mv88e6250_ops, 6283 }, 6284 6285 [MV88E6240] = { 6286 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6287 .family = MV88E6XXX_FAMILY_6352, 6288 .name = "Marvell 88E6240", 6289 .num_databases = 4096, 6290 .num_macs = 8192, 6291 .num_ports = 7, 6292 .num_internal_phys = 5, 6293 .num_gpio = 15, 6294 .max_vid = 4095, 6295 .max_sid = 63, 6296 .port_base_addr = 0x10, 6297 .phy_base_addr = 0x0, 6298 .global1_addr = 0x1b, 6299 .global2_addr = 0x1c, 6300 .age_time_coeff = 15000, 6301 .g1_irqs = 9, 6302 .g2_irqs = 10, 6303 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6304 .atu_move_port_mask = 0xf, 6305 .pvt = true, 6306 .multi_chip = true, 6307 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6308 .ptp_support = true, 6309 .ops = &mv88e6240_ops, 6310 }, 6311 6312 [MV88E6250] = { 6313 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6314 .family = MV88E6XXX_FAMILY_6250, 6315 .name = "Marvell 88E6250", 6316 .num_databases = 64, 6317 .num_ports = 7, 6318 .num_internal_phys = 5, 6319 .max_vid = 4095, 6320 .port_base_addr = 0x08, 6321 .phy_base_addr = 0x00, 6322 .global1_addr = 0x0f, 6323 .global2_addr = 0x07, 6324 .age_time_coeff = 15000, 6325 .g1_irqs = 9, 6326 .g2_irqs = 10, 6327 .stats_type = STATS_TYPE_BANK0, 6328 .atu_move_port_mask = 0xf, 6329 .dual_chip = true, 6330 .ptp_support = true, 6331 .ops = &mv88e6250_ops, 6332 }, 6333 6334 [MV88E6290] = { 6335 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6336 .family = MV88E6XXX_FAMILY_6390, 6337 .name = "Marvell 88E6290", 6338 .num_databases = 4096, 6339 .num_ports = 11, /* 10 + Z80 */ 6340 .num_internal_phys = 9, 6341 .num_gpio = 16, 6342 .num_tcam_entries = 256, 6343 .max_vid = 8191, 6344 .max_sid = 63, 6345 .port_base_addr = 0x0, 6346 .phy_base_addr = 0x0, 6347 .global1_addr = 0x1b, 6348 .global2_addr = 0x1c, 6349 .tcam_addr = 0x1f, 6350 .age_time_coeff = 3750, 6351 .g1_irqs = 9, 6352 .g2_irqs = 14, 6353 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6354 .atu_move_port_mask = 0x1f, 6355 .pvt = true, 6356 .multi_chip = true, 6357 .ptp_support = true, 6358 .ops = &mv88e6290_ops, 6359 }, 6360 6361 [MV88E6320] = { 6362 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6363 .family = MV88E6XXX_FAMILY_6320, 6364 .name = "Marvell 88E6320", 6365 .num_databases = 4096, 6366 .num_macs = 8192, 6367 .num_ports = 7, 6368 .num_internal_phys = 2, 6369 .internal_phys_offset = 3, 6370 .num_gpio = 15, 6371 .max_vid = 4095, 6372 .max_sid = 63, 6373 .port_base_addr = 0x10, 6374 .phy_base_addr = 0x0, 6375 .global1_addr = 0x1b, 6376 .global2_addr = 0x1c, 6377 .age_time_coeff = 15000, 6378 .g1_irqs = 9, 6379 .g2_irqs = 10, 6380 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6381 .atu_move_port_mask = 0xf, 6382 .pvt = true, 6383 .multi_chip = true, 6384 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6385 .ptp_support = true, 6386 .ops = &mv88e6320_ops, 6387 }, 6388 6389 [MV88E6321] = { 6390 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6391 .family = MV88E6XXX_FAMILY_6320, 6392 .name = "Marvell 88E6321", 6393 .num_databases = 4096, 6394 .num_macs = 8192, 6395 .num_ports = 7, 6396 .num_internal_phys = 2, 6397 .internal_phys_offset = 3, 6398 .num_gpio = 15, 6399 .max_vid = 4095, 6400 .max_sid = 63, 6401 .port_base_addr = 0x10, 6402 .phy_base_addr = 0x0, 6403 .global1_addr = 0x1b, 6404 .global2_addr = 0x1c, 6405 .age_time_coeff = 15000, 6406 .g1_irqs = 9, 6407 .g2_irqs = 10, 6408 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6409 .atu_move_port_mask = 0xf, 6410 .pvt = true, 6411 .multi_chip = true, 6412 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6413 .ptp_support = true, 6414 .ops = &mv88e6321_ops, 6415 }, 6416 6417 [MV88E6341] = { 6418 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6419 .family = MV88E6XXX_FAMILY_6341, 6420 .name = "Marvell 88E6341", 6421 .num_databases = 256, 6422 .num_macs = 2048, 6423 .num_internal_phys = 5, 6424 .num_ports = 6, 6425 .num_gpio = 11, 6426 .max_vid = 4095, 6427 .max_sid = 63, 6428 .port_base_addr = 0x10, 6429 .phy_base_addr = 0x10, 6430 .global1_addr = 0x1b, 6431 .global2_addr = 0x1c, 6432 .age_time_coeff = 3750, 6433 .atu_move_port_mask = 0xf, 6434 .g1_irqs = 9, 6435 .g2_irqs = 10, 6436 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6437 .pvt = true, 6438 .multi_chip = true, 6439 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6440 .ptp_support = true, 6441 .ops = &mv88e6341_ops, 6442 }, 6443 6444 [MV88E6350] = { 6445 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6446 .family = MV88E6XXX_FAMILY_6351, 6447 .name = "Marvell 88E6350", 6448 .num_databases = 4096, 6449 .num_macs = 8192, 6450 .num_ports = 7, 6451 .num_internal_phys = 5, 6452 .max_vid = 4095, 6453 .max_sid = 63, 6454 .port_base_addr = 0x10, 6455 .phy_base_addr = 0x0, 6456 .global1_addr = 0x1b, 6457 .global2_addr = 0x1c, 6458 .age_time_coeff = 15000, 6459 .g1_irqs = 9, 6460 .g2_irqs = 10, 6461 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6462 .atu_move_port_mask = 0xf, 6463 .pvt = true, 6464 .multi_chip = true, 6465 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6466 .ops = &mv88e6350_ops, 6467 }, 6468 6469 [MV88E6351] = { 6470 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6471 .family = MV88E6XXX_FAMILY_6351, 6472 .name = "Marvell 88E6351", 6473 .num_databases = 4096, 6474 .num_macs = 8192, 6475 .num_ports = 7, 6476 .num_internal_phys = 5, 6477 .max_vid = 4095, 6478 .max_sid = 63, 6479 .port_base_addr = 0x10, 6480 .phy_base_addr = 0x0, 6481 .global1_addr = 0x1b, 6482 .global2_addr = 0x1c, 6483 .age_time_coeff = 15000, 6484 .g1_irqs = 9, 6485 .g2_irqs = 10, 6486 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6487 .atu_move_port_mask = 0xf, 6488 .pvt = true, 6489 .multi_chip = true, 6490 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6491 .ops = &mv88e6351_ops, 6492 }, 6493 6494 [MV88E6352] = { 6495 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6496 .family = MV88E6XXX_FAMILY_6352, 6497 .name = "Marvell 88E6352", 6498 .num_databases = 4096, 6499 .num_macs = 8192, 6500 .num_ports = 7, 6501 .num_internal_phys = 5, 6502 .num_gpio = 15, 6503 .max_vid = 4095, 6504 .max_sid = 63, 6505 .port_base_addr = 0x10, 6506 .phy_base_addr = 0x0, 6507 .global1_addr = 0x1b, 6508 .global2_addr = 0x1c, 6509 .age_time_coeff = 15000, 6510 .g1_irqs = 9, 6511 .g2_irqs = 10, 6512 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6513 .atu_move_port_mask = 0xf, 6514 .pvt = true, 6515 .multi_chip = true, 6516 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6517 .ptp_support = true, 6518 .ops = &mv88e6352_ops, 6519 }, 6520 [MV88E6361] = { 6521 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6522 .family = MV88E6XXX_FAMILY_6393, 6523 .name = "Marvell 88E6361", 6524 .num_databases = 4096, 6525 .num_macs = 16384, 6526 .num_ports = 11, 6527 /* Ports 1, 2 and 8 are not routed */ 6528 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6529 .num_internal_phys = 5, 6530 .internal_phys_offset = 3, 6531 .max_vid = 8191, 6532 .max_sid = 63, 6533 .port_base_addr = 0x0, 6534 .phy_base_addr = 0x0, 6535 .global1_addr = 0x1b, 6536 .global2_addr = 0x1c, 6537 .age_time_coeff = 3750, 6538 .g1_irqs = 10, 6539 .g2_irqs = 14, 6540 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6541 .atu_move_port_mask = 0x1f, 6542 .pvt = true, 6543 .multi_chip = true, 6544 .ptp_support = true, 6545 .ops = &mv88e6393x_ops, 6546 }, 6547 [MV88E6390] = { 6548 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6549 .family = MV88E6XXX_FAMILY_6390, 6550 .name = "Marvell 88E6390", 6551 .num_databases = 4096, 6552 .num_macs = 16384, 6553 .num_ports = 11, /* 10 + Z80 */ 6554 .num_internal_phys = 9, 6555 .num_gpio = 16, 6556 .num_tcam_entries = 256, 6557 .max_vid = 8191, 6558 .max_sid = 63, 6559 .port_base_addr = 0x0, 6560 .phy_base_addr = 0x0, 6561 .global1_addr = 0x1b, 6562 .global2_addr = 0x1c, 6563 .tcam_addr = 0x1f, 6564 .age_time_coeff = 3750, 6565 .g1_irqs = 9, 6566 .g2_irqs = 14, 6567 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6568 .atu_move_port_mask = 0x1f, 6569 .pvt = true, 6570 .multi_chip = true, 6571 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6572 .ptp_support = true, 6573 .ops = &mv88e6390_ops, 6574 }, 6575 [MV88E6390X] = { 6576 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6577 .family = MV88E6XXX_FAMILY_6390, 6578 .name = "Marvell 88E6390X", 6579 .num_databases = 4096, 6580 .num_macs = 16384, 6581 .num_ports = 11, /* 10 + Z80 */ 6582 .num_internal_phys = 9, 6583 .num_gpio = 16, 6584 .max_vid = 8191, 6585 .max_sid = 63, 6586 .port_base_addr = 0x0, 6587 .phy_base_addr = 0x0, 6588 .global1_addr = 0x1b, 6589 .global2_addr = 0x1c, 6590 .age_time_coeff = 3750, 6591 .g1_irqs = 9, 6592 .g2_irqs = 14, 6593 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6594 .atu_move_port_mask = 0x1f, 6595 .pvt = true, 6596 .multi_chip = true, 6597 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6598 .ptp_support = true, 6599 .ops = &mv88e6390x_ops, 6600 }, 6601 6602 [MV88E6393X] = { 6603 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6604 .family = MV88E6XXX_FAMILY_6393, 6605 .name = "Marvell 88E6393X", 6606 .num_databases = 4096, 6607 .num_ports = 11, /* 10 + Z80 */ 6608 .num_internal_phys = 8, 6609 .num_tcam_entries = 256, 6610 .internal_phys_offset = 1, 6611 .max_vid = 8191, 6612 .max_sid = 63, 6613 .port_base_addr = 0x0, 6614 .phy_base_addr = 0x0, 6615 .global1_addr = 0x1b, 6616 .global2_addr = 0x1c, 6617 .tcam_addr = 0x1f, 6618 .age_time_coeff = 3750, 6619 .g1_irqs = 10, 6620 .g2_irqs = 14, 6621 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6622 .atu_move_port_mask = 0x1f, 6623 .pvt = true, 6624 .multi_chip = true, 6625 .ptp_support = true, 6626 .ops = &mv88e6393x_ops, 6627 }, 6628 }; 6629 6630 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6631 { 6632 int i; 6633 6634 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6635 if (mv88e6xxx_table[i].prod_num == prod_num) 6636 return &mv88e6xxx_table[i]; 6637 6638 return NULL; 6639 } 6640 6641 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6642 { 6643 const struct mv88e6xxx_info *info; 6644 unsigned int prod_num, rev; 6645 u16 id; 6646 int err; 6647 6648 mv88e6xxx_reg_lock(chip); 6649 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6650 mv88e6xxx_reg_unlock(chip); 6651 if (err) 6652 return err; 6653 6654 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6655 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6656 6657 info = mv88e6xxx_lookup_info(prod_num); 6658 if (!info) 6659 return -ENODEV; 6660 6661 /* Update the compatible info with the probed one */ 6662 chip->info = info; 6663 6664 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6665 chip->info->prod_num, chip->info->name, rev); 6666 6667 return 0; 6668 } 6669 6670 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6671 struct mdio_device *mdiodev) 6672 { 6673 int err; 6674 6675 /* dual_chip takes precedence over single/multi-chip modes */ 6676 if (chip->info->dual_chip) 6677 return -EINVAL; 6678 6679 /* If the mdio addr is 16 indicating the first port address of a switch 6680 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6681 * configured in single chip addressing mode. Setup the smi access as 6682 * single chip addressing mode and attempt to detect the model of the 6683 * switch, if this fails the device is not configured in single chip 6684 * addressing mode. 6685 */ 6686 if (mdiodev->addr != 16) 6687 return -EINVAL; 6688 6689 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6690 if (err) 6691 return err; 6692 6693 return mv88e6xxx_detect(chip); 6694 } 6695 6696 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6697 { 6698 struct mv88e6xxx_chip *chip; 6699 6700 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6701 if (!chip) 6702 return NULL; 6703 6704 chip->dev = dev; 6705 6706 mutex_init(&chip->reg_lock); 6707 INIT_LIST_HEAD(&chip->mdios); 6708 idr_init(&chip->policies); 6709 INIT_LIST_HEAD(&chip->msts); 6710 INIT_LIST_HEAD(&chip->tcam.entries); 6711 6712 return chip; 6713 } 6714 6715 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6716 int port, 6717 enum dsa_tag_protocol m) 6718 { 6719 struct mv88e6xxx_chip *chip = ds->priv; 6720 6721 return chip->tag_protocol; 6722 } 6723 6724 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6725 enum dsa_tag_protocol proto) 6726 { 6727 struct mv88e6xxx_chip *chip = ds->priv; 6728 enum dsa_tag_protocol old_protocol; 6729 struct dsa_port *cpu_dp; 6730 int err; 6731 6732 switch (proto) { 6733 case DSA_TAG_PROTO_EDSA: 6734 switch (chip->info->edsa_support) { 6735 case MV88E6XXX_EDSA_UNSUPPORTED: 6736 return -EPROTONOSUPPORT; 6737 case MV88E6XXX_EDSA_UNDOCUMENTED: 6738 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6739 fallthrough; 6740 case MV88E6XXX_EDSA_SUPPORTED: 6741 break; 6742 } 6743 break; 6744 case DSA_TAG_PROTO_DSA: 6745 break; 6746 default: 6747 return -EPROTONOSUPPORT; 6748 } 6749 6750 old_protocol = chip->tag_protocol; 6751 chip->tag_protocol = proto; 6752 6753 mv88e6xxx_reg_lock(chip); 6754 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6755 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6756 if (err) { 6757 mv88e6xxx_reg_unlock(chip); 6758 goto unwind; 6759 } 6760 } 6761 mv88e6xxx_reg_unlock(chip); 6762 6763 return 0; 6764 6765 unwind: 6766 chip->tag_protocol = old_protocol; 6767 6768 mv88e6xxx_reg_lock(chip); 6769 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6770 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6771 mv88e6xxx_reg_unlock(chip); 6772 6773 return err; 6774 } 6775 6776 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6777 const struct switchdev_obj_port_mdb *mdb, 6778 struct dsa_db db) 6779 { 6780 struct mv88e6xxx_chip *chip = ds->priv; 6781 int err; 6782 6783 mv88e6xxx_reg_lock(chip); 6784 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6785 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6786 if (err) 6787 goto out; 6788 6789 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid)) 6790 err = -ENOSPC; 6791 6792 out: 6793 mv88e6xxx_reg_unlock(chip); 6794 6795 return err; 6796 } 6797 6798 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6799 const struct switchdev_obj_port_mdb *mdb, 6800 struct dsa_db db) 6801 { 6802 struct mv88e6xxx_chip *chip = ds->priv; 6803 int err; 6804 6805 mv88e6xxx_reg_lock(chip); 6806 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6807 mv88e6xxx_reg_unlock(chip); 6808 6809 return err; 6810 } 6811 6812 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6813 struct dsa_mall_mirror_tc_entry *mirror, 6814 bool ingress, 6815 struct netlink_ext_ack *extack) 6816 { 6817 enum mv88e6xxx_egress_direction direction = ingress ? 6818 MV88E6XXX_EGRESS_DIR_INGRESS : 6819 MV88E6XXX_EGRESS_DIR_EGRESS; 6820 struct mv88e6xxx_chip *chip = ds->priv; 6821 bool other_mirrors = false; 6822 int i; 6823 int err; 6824 6825 mutex_lock(&chip->reg_lock); 6826 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6827 mirror->to_local_port) { 6828 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6829 other_mirrors |= ingress ? 6830 chip->ports[i].mirror_ingress : 6831 chip->ports[i].mirror_egress; 6832 6833 /* Can't change egress port when other mirror is active */ 6834 if (other_mirrors) { 6835 err = -EBUSY; 6836 goto out; 6837 } 6838 6839 err = mv88e6xxx_set_egress_port(chip, direction, 6840 mirror->to_local_port); 6841 if (err) 6842 goto out; 6843 } 6844 6845 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6846 out: 6847 mutex_unlock(&chip->reg_lock); 6848 6849 return err; 6850 } 6851 6852 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6853 struct dsa_mall_mirror_tc_entry *mirror) 6854 { 6855 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6856 MV88E6XXX_EGRESS_DIR_INGRESS : 6857 MV88E6XXX_EGRESS_DIR_EGRESS; 6858 struct mv88e6xxx_chip *chip = ds->priv; 6859 bool other_mirrors = false; 6860 int i; 6861 6862 mutex_lock(&chip->reg_lock); 6863 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6864 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6865 6866 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6867 other_mirrors |= mirror->ingress ? 6868 chip->ports[i].mirror_ingress : 6869 chip->ports[i].mirror_egress; 6870 6871 /* Reset egress port when no other mirror is active */ 6872 if (!other_mirrors) { 6873 if (mv88e6xxx_set_egress_port(chip, direction, 6874 dsa_upstream_port(ds, port))) 6875 dev_err(ds->dev, "failed to set egress port\n"); 6876 } 6877 6878 mutex_unlock(&chip->reg_lock); 6879 } 6880 6881 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6882 struct switchdev_brport_flags flags, 6883 struct netlink_ext_ack *extack) 6884 { 6885 struct mv88e6xxx_chip *chip = ds->priv; 6886 const struct mv88e6xxx_ops *ops; 6887 6888 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6889 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6890 return -EINVAL; 6891 6892 ops = chip->info->ops; 6893 6894 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6895 return -EINVAL; 6896 6897 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6898 return -EINVAL; 6899 6900 return 0; 6901 } 6902 6903 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6904 struct switchdev_brport_flags flags, 6905 struct netlink_ext_ack *extack) 6906 { 6907 struct mv88e6xxx_chip *chip = ds->priv; 6908 int err = 0; 6909 6910 mv88e6xxx_reg_lock(chip); 6911 6912 if (flags.mask & BR_LEARNING) { 6913 bool learning = !!(flags.val & BR_LEARNING); 6914 u16 pav = learning ? (1 << port) : 0; 6915 6916 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6917 if (err) 6918 goto out; 6919 } 6920 6921 if (flags.mask & BR_FLOOD) { 6922 bool unicast = !!(flags.val & BR_FLOOD); 6923 6924 err = chip->info->ops->port_set_ucast_flood(chip, port, 6925 unicast); 6926 if (err) 6927 goto out; 6928 } 6929 6930 if (flags.mask & BR_MCAST_FLOOD) { 6931 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6932 6933 err = chip->info->ops->port_set_mcast_flood(chip, port, 6934 multicast); 6935 if (err) 6936 goto out; 6937 } 6938 6939 if (flags.mask & BR_BCAST_FLOOD) { 6940 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6941 6942 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6943 if (err) 6944 goto out; 6945 } 6946 6947 if (flags.mask & BR_PORT_MAB) { 6948 bool mab = !!(flags.val & BR_PORT_MAB); 6949 6950 mv88e6xxx_port_set_mab(chip, port, mab); 6951 } 6952 6953 if (flags.mask & BR_PORT_LOCKED) { 6954 bool locked = !!(flags.val & BR_PORT_LOCKED); 6955 6956 err = mv88e6xxx_port_set_lock(chip, port, locked); 6957 if (err) 6958 goto out; 6959 } 6960 out: 6961 mv88e6xxx_reg_unlock(chip); 6962 6963 return err; 6964 } 6965 6966 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6967 struct dsa_lag lag, 6968 struct netdev_lag_upper_info *info, 6969 struct netlink_ext_ack *extack) 6970 { 6971 struct mv88e6xxx_chip *chip = ds->priv; 6972 struct dsa_port *dp; 6973 int members = 0; 6974 6975 if (!mv88e6xxx_has_lag(chip)) { 6976 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6977 return false; 6978 } 6979 6980 if (!lag.id) 6981 return false; 6982 6983 dsa_lag_foreach_port(dp, ds->dst, &lag) 6984 /* Includes the port joining the LAG */ 6985 members++; 6986 6987 if (members > 8) { 6988 NL_SET_ERR_MSG_MOD(extack, 6989 "Cannot offload more than 8 LAG ports"); 6990 return false; 6991 } 6992 6993 /* We could potentially relax this to include active 6994 * backup in the future. 6995 */ 6996 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6997 NL_SET_ERR_MSG_MOD(extack, 6998 "Can only offload LAG using hash TX type"); 6999 return false; 7000 } 7001 7002 /* Ideally we would also validate that the hash type matches 7003 * the hardware. Alas, this is always set to unknown on team 7004 * interfaces. 7005 */ 7006 return true; 7007 } 7008 7009 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 7010 { 7011 struct mv88e6xxx_chip *chip = ds->priv; 7012 struct dsa_port *dp; 7013 u16 map = 0; 7014 int id; 7015 7016 /* DSA LAG IDs are one-based, hardware is zero-based */ 7017 id = lag.id - 1; 7018 7019 /* Build the map of all ports to distribute flows destined for 7020 * this LAG. This can be either a local user port, or a DSA 7021 * port if the LAG port is on a remote chip. 7022 */ 7023 dsa_lag_foreach_port(dp, ds->dst, &lag) 7024 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 7025 7026 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 7027 } 7028 7029 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 7030 /* Row number corresponds to the number of active members in a 7031 * LAG. Each column states which of the eight hash buckets are 7032 * mapped to the column:th port in the LAG. 7033 * 7034 * Example: In a LAG with three active ports, the second port 7035 * ([2][1]) would be selected for traffic mapped to buckets 7036 * 3,4,5 (0x38). 7037 */ 7038 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 7039 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 7040 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 7041 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 7042 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 7043 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 7044 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 7045 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 7046 }; 7047 7048 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 7049 int num_tx, int nth) 7050 { 7051 u8 active = 0; 7052 int i; 7053 7054 num_tx = num_tx <= 8 ? num_tx : 8; 7055 if (nth < num_tx) 7056 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 7057 7058 for (i = 0; i < 8; i++) { 7059 if (BIT(i) & active) 7060 mask[i] |= BIT(port); 7061 } 7062 } 7063 7064 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 7065 { 7066 struct mv88e6xxx_chip *chip = ds->priv; 7067 unsigned int id, num_tx; 7068 struct dsa_port *dp; 7069 struct dsa_lag *lag; 7070 int i, err, nth; 7071 u16 mask[8]; 7072 u16 ivec; 7073 7074 /* Assume no port is a member of any LAG. */ 7075 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 7076 7077 /* Disable all masks for ports that _are_ members of a LAG. */ 7078 dsa_switch_for_each_port(dp, ds) { 7079 if (!dp->lag) 7080 continue; 7081 7082 ivec &= ~BIT(dp->index); 7083 } 7084 7085 for (i = 0; i < 8; i++) 7086 mask[i] = ivec; 7087 7088 /* Enable the correct subset of masks for all LAG ports that 7089 * are in the Tx set. 7090 */ 7091 dsa_lags_foreach_id(id, ds->dst) { 7092 lag = dsa_lag_by_id(ds->dst, id); 7093 if (!lag) 7094 continue; 7095 7096 num_tx = 0; 7097 dsa_lag_foreach_port(dp, ds->dst, lag) { 7098 if (dp->lag_tx_enabled) 7099 num_tx++; 7100 } 7101 7102 if (!num_tx) 7103 continue; 7104 7105 nth = 0; 7106 dsa_lag_foreach_port(dp, ds->dst, lag) { 7107 if (!dp->lag_tx_enabled) 7108 continue; 7109 7110 if (dp->ds == ds) 7111 mv88e6xxx_lag_set_port_mask(mask, dp->index, 7112 num_tx, nth); 7113 7114 nth++; 7115 } 7116 } 7117 7118 for (i = 0; i < 8; i++) { 7119 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 7120 if (err) 7121 return err; 7122 } 7123 7124 return 0; 7125 } 7126 7127 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 7128 struct dsa_lag lag) 7129 { 7130 int err; 7131 7132 err = mv88e6xxx_lag_sync_masks(ds); 7133 7134 if (!err) 7135 err = mv88e6xxx_lag_sync_map(ds, lag); 7136 7137 return err; 7138 } 7139 7140 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 7141 { 7142 struct mv88e6xxx_chip *chip = ds->priv; 7143 int err; 7144 7145 mv88e6xxx_reg_lock(chip); 7146 err = mv88e6xxx_lag_sync_masks(ds); 7147 mv88e6xxx_reg_unlock(chip); 7148 return err; 7149 } 7150 7151 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 7152 struct dsa_lag lag, 7153 struct netdev_lag_upper_info *info, 7154 struct netlink_ext_ack *extack) 7155 { 7156 struct mv88e6xxx_chip *chip = ds->priv; 7157 int err, id; 7158 7159 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7160 return -EOPNOTSUPP; 7161 7162 /* DSA LAG IDs are one-based */ 7163 id = lag.id - 1; 7164 7165 mv88e6xxx_reg_lock(chip); 7166 7167 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 7168 if (err) 7169 goto err_unlock; 7170 7171 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7172 if (err) 7173 goto err_clear_trunk; 7174 7175 mv88e6xxx_reg_unlock(chip); 7176 return 0; 7177 7178 err_clear_trunk: 7179 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7180 err_unlock: 7181 mv88e6xxx_reg_unlock(chip); 7182 return err; 7183 } 7184 7185 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7186 struct dsa_lag lag) 7187 { 7188 struct mv88e6xxx_chip *chip = ds->priv; 7189 int err_sync, err_trunk; 7190 7191 mv88e6xxx_reg_lock(chip); 7192 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7193 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7194 mv88e6xxx_reg_unlock(chip); 7195 return err_sync ? : err_trunk; 7196 } 7197 7198 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7199 int port) 7200 { 7201 struct mv88e6xxx_chip *chip = ds->priv; 7202 int err; 7203 7204 mv88e6xxx_reg_lock(chip); 7205 err = mv88e6xxx_lag_sync_masks(ds); 7206 mv88e6xxx_reg_unlock(chip); 7207 return err; 7208 } 7209 7210 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7211 int port, struct dsa_lag lag, 7212 struct netdev_lag_upper_info *info, 7213 struct netlink_ext_ack *extack) 7214 { 7215 struct mv88e6xxx_chip *chip = ds->priv; 7216 int err; 7217 7218 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7219 return -EOPNOTSUPP; 7220 7221 mv88e6xxx_reg_lock(chip); 7222 7223 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7224 if (err) 7225 goto unlock; 7226 7227 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7228 7229 unlock: 7230 mv88e6xxx_reg_unlock(chip); 7231 return err; 7232 } 7233 7234 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7235 int port, struct dsa_lag lag) 7236 { 7237 struct mv88e6xxx_chip *chip = ds->priv; 7238 int err_sync, err_pvt; 7239 7240 mv88e6xxx_reg_lock(chip); 7241 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7242 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7243 mv88e6xxx_reg_unlock(chip); 7244 return err_sync ? : err_pvt; 7245 } 7246 7247 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7248 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7249 .mac_prepare = mv88e6xxx_mac_prepare, 7250 .mac_config = mv88e6xxx_mac_config, 7251 .mac_finish = mv88e6xxx_mac_finish, 7252 .mac_link_down = mv88e6xxx_mac_link_down, 7253 .mac_link_up = mv88e6xxx_mac_link_up, 7254 }; 7255 7256 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7257 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7258 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7259 .setup = mv88e6xxx_setup, 7260 .teardown = mv88e6xxx_teardown, 7261 .port_setup = mv88e6xxx_port_setup, 7262 .port_teardown = mv88e6xxx_port_teardown, 7263 .phylink_get_caps = mv88e6xxx_get_caps, 7264 .get_strings = mv88e6xxx_get_strings, 7265 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7266 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7267 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7268 .get_sset_count = mv88e6xxx_get_sset_count, 7269 .port_max_mtu = mv88e6xxx_get_max_mtu, 7270 .port_change_mtu = mv88e6xxx_change_mtu, 7271 .support_eee = dsa_supports_eee, 7272 .set_mac_eee = mv88e6xxx_set_mac_eee, 7273 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7274 .get_eeprom = mv88e6xxx_get_eeprom, 7275 .set_eeprom = mv88e6xxx_set_eeprom, 7276 .get_regs_len = mv88e6xxx_get_regs_len, 7277 .get_regs = mv88e6xxx_get_regs, 7278 .get_rxnfc = mv88e6xxx_get_rxnfc, 7279 .set_rxnfc = mv88e6xxx_set_rxnfc, 7280 .set_ageing_time = mv88e6xxx_set_ageing_time, 7281 .port_bridge_join = mv88e6xxx_port_bridge_join, 7282 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7283 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7284 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7285 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7286 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7287 .port_fast_age = mv88e6xxx_port_fast_age, 7288 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7289 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7290 .port_vlan_add = mv88e6xxx_port_vlan_add, 7291 .port_vlan_del = mv88e6xxx_port_vlan_del, 7292 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7293 .port_fdb_add = mv88e6xxx_port_fdb_add, 7294 .port_fdb_del = mv88e6xxx_port_fdb_del, 7295 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7296 .port_mdb_add = mv88e6xxx_port_mdb_add, 7297 .port_mdb_del = mv88e6xxx_port_mdb_del, 7298 .port_mirror_add = mv88e6xxx_port_mirror_add, 7299 .port_mirror_del = mv88e6xxx_port_mirror_del, 7300 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7301 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7302 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7303 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7304 .port_txtstamp = mv88e6xxx_port_txtstamp, 7305 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7306 .cls_flower_add = mv88e6xxx_cls_flower_add, 7307 .cls_flower_del = mv88e6xxx_cls_flower_del, 7308 .get_ts_info = mv88e6xxx_get_ts_info, 7309 .devlink_param_get = mv88e6xxx_devlink_param_get, 7310 .devlink_param_set = mv88e6xxx_devlink_param_set, 7311 .devlink_info_get = mv88e6xxx_devlink_info_get, 7312 .port_lag_change = mv88e6xxx_port_lag_change, 7313 .port_lag_join = mv88e6xxx_port_lag_join, 7314 .port_lag_leave = mv88e6xxx_port_lag_leave, 7315 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7316 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7317 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7318 }; 7319 7320 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7321 { 7322 struct device *dev = chip->dev; 7323 struct dsa_switch *ds; 7324 7325 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7326 if (!ds) 7327 return -ENOMEM; 7328 7329 ds->dev = dev; 7330 ds->num_ports = mv88e6xxx_num_ports(chip); 7331 ds->priv = chip; 7332 ds->dev = dev; 7333 ds->ops = &mv88e6xxx_switch_ops; 7334 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7335 ds->ageing_time_min = chip->info->age_time_coeff; 7336 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7337 7338 /* Some chips support up to 32, but that requires enabling the 7339 * 5-bit port mode, which we do not support. 640k^W16 ought to 7340 * be enough for anyone. 7341 */ 7342 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7343 7344 dev_set_drvdata(dev, ds); 7345 7346 return dsa_register_switch(ds); 7347 } 7348 7349 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7350 { 7351 dsa_unregister_switch(chip->ds); 7352 } 7353 7354 static const void *pdata_device_get_match_data(struct device *dev) 7355 { 7356 const struct of_device_id *matches = dev->driver->of_match_table; 7357 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7358 7359 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7360 matches++) { 7361 if (!strcmp(pdata->compatible, matches->compatible)) 7362 return matches->data; 7363 } 7364 return NULL; 7365 } 7366 7367 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7368 * would be lost after a power cycle so prevent it to be suspended. 7369 */ 7370 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7371 { 7372 return -EOPNOTSUPP; 7373 } 7374 7375 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7376 { 7377 return 0; 7378 } 7379 7380 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7381 7382 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7383 { 7384 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7385 const struct mv88e6xxx_info *compat_info = NULL; 7386 struct device *dev = &mdiodev->dev; 7387 struct device_node *np = dev->of_node; 7388 struct mv88e6xxx_chip *chip; 7389 int port; 7390 int err; 7391 7392 if (!np && !pdata) 7393 return -EINVAL; 7394 7395 if (np) 7396 compat_info = of_device_get_match_data(dev); 7397 7398 if (pdata) { 7399 compat_info = pdata_device_get_match_data(dev); 7400 7401 if (!pdata->netdev) 7402 return -EINVAL; 7403 7404 for (port = 0; port < DSA_MAX_PORTS; port++) { 7405 if (!(pdata->enabled_ports & (1 << port))) 7406 continue; 7407 if (strcmp(pdata->cd.port_names[port], "cpu")) 7408 continue; 7409 pdata->cd.netdev[port] = &pdata->netdev->dev; 7410 break; 7411 } 7412 } 7413 7414 if (!compat_info) 7415 return -EINVAL; 7416 7417 chip = mv88e6xxx_alloc_chip(dev); 7418 if (!chip) { 7419 err = -ENOMEM; 7420 goto out; 7421 } 7422 7423 chip->info = compat_info; 7424 7425 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7426 if (IS_ERR(chip->reset)) { 7427 err = PTR_ERR(chip->reset); 7428 goto out; 7429 } 7430 if (chip->reset) 7431 usleep_range(10000, 20000); 7432 7433 /* Detect if the device is configured in single chip addressing mode, 7434 * otherwise continue with address specific smi init/detection. 7435 */ 7436 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7437 if (err) { 7438 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7439 if (err) 7440 goto out; 7441 7442 err = mv88e6xxx_detect(chip); 7443 if (err) 7444 goto out; 7445 } 7446 7447 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7448 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7449 else 7450 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7451 7452 mv88e6xxx_phy_init(chip); 7453 7454 if (chip->info->ops->get_eeprom) { 7455 if (np) 7456 of_property_read_u32(np, "eeprom-length", 7457 &chip->eeprom_len); 7458 else 7459 chip->eeprom_len = pdata->eeprom_len; 7460 } 7461 7462 mv88e6xxx_reg_lock(chip); 7463 err = mv88e6xxx_switch_reset(chip); 7464 mv88e6xxx_reg_unlock(chip); 7465 if (err) 7466 goto out_phy; 7467 7468 if (np) { 7469 chip->irq = of_irq_get(np, 0); 7470 if (chip->irq == -EPROBE_DEFER) { 7471 err = chip->irq; 7472 goto out_phy; 7473 } 7474 } 7475 7476 if (pdata) 7477 chip->irq = pdata->irq; 7478 7479 /* Has to be performed before the MDIO bus is created, because 7480 * the PHYs will link their interrupts to these interrupt 7481 * controllers 7482 */ 7483 mv88e6xxx_reg_lock(chip); 7484 if (chip->irq > 0) 7485 err = mv88e6xxx_g1_irq_setup(chip); 7486 else 7487 err = mv88e6xxx_irq_poll_setup(chip); 7488 mv88e6xxx_reg_unlock(chip); 7489 7490 if (err) 7491 goto out_phy; 7492 7493 if (chip->info->g2_irqs > 0) { 7494 err = mv88e6xxx_g2_irq_setup(chip); 7495 if (err) 7496 goto out_g1_irq; 7497 } 7498 7499 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7500 if (err) 7501 goto out_g2_irq; 7502 7503 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7504 if (err) 7505 goto out_g1_atu_prob_irq; 7506 7507 err = mv88e6xxx_register_switch(chip); 7508 if (err) 7509 goto out_g1_vtu_prob_irq; 7510 7511 return 0; 7512 7513 out_g1_vtu_prob_irq: 7514 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7515 out_g1_atu_prob_irq: 7516 mv88e6xxx_g1_atu_prob_irq_free(chip); 7517 out_g2_irq: 7518 if (chip->info->g2_irqs > 0) 7519 mv88e6xxx_g2_irq_free(chip); 7520 out_g1_irq: 7521 if (chip->irq > 0) 7522 mv88e6xxx_g1_irq_free(chip); 7523 else 7524 mv88e6xxx_irq_poll_free(chip); 7525 out_phy: 7526 mv88e6xxx_phy_destroy(chip); 7527 out: 7528 if (pdata) 7529 dev_put(pdata->netdev); 7530 7531 return err; 7532 } 7533 7534 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7535 { 7536 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7537 struct mv88e6xxx_chip *chip; 7538 7539 if (!ds) 7540 return; 7541 7542 chip = ds->priv; 7543 7544 mv88e6xxx_unregister_switch(chip); 7545 7546 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7547 mv88e6xxx_g1_atu_prob_irq_free(chip); 7548 7549 if (chip->info->g2_irqs > 0) 7550 mv88e6xxx_g2_irq_free(chip); 7551 7552 if (chip->irq > 0) 7553 mv88e6xxx_g1_irq_free(chip); 7554 else 7555 mv88e6xxx_irq_poll_free(chip); 7556 7557 mv88e6xxx_phy_destroy(chip); 7558 } 7559 7560 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7561 { 7562 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7563 7564 if (!ds) 7565 return; 7566 7567 dsa_switch_shutdown(ds); 7568 7569 dev_set_drvdata(&mdiodev->dev, NULL); 7570 } 7571 7572 static const struct of_device_id mv88e6xxx_of_match[] = { 7573 { 7574 .compatible = "marvell,mv88e6085", 7575 .data = &mv88e6xxx_table[MV88E6085], 7576 }, 7577 { 7578 .compatible = "marvell,mv88e6190", 7579 .data = &mv88e6xxx_table[MV88E6190], 7580 }, 7581 { 7582 .compatible = "marvell,mv88e6250", 7583 .data = &mv88e6xxx_table[MV88E6250], 7584 }, 7585 { /* sentinel */ } 7586 }; 7587 7588 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7589 7590 static struct mdio_driver mv88e6xxx_driver = { 7591 .probe = mv88e6xxx_probe, 7592 .remove = mv88e6xxx_remove, 7593 .shutdown = mv88e6xxx_shutdown, 7594 .mdiodrv.driver = { 7595 .name = "mv88e6085", 7596 .of_match_table = mv88e6xxx_of_match, 7597 .pm = &mv88e6xxx_pm_ops, 7598 }, 7599 }; 7600 7601 mdio_module_driver(mv88e6xxx_driver); 7602 7603 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7604 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7605 MODULE_LICENSE("GPL"); 7606