1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP 4 * platforms. 5 * 6 * Copyright (C) 2012 Marvell 7 * 8 * Yehuda Yitschak <yehuday@marvell.com> 9 * Gregory Clement <gregory.clement@free-electrons.com> 10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 11 * 12 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is 13 * responsible for ensuring hardware coherency between all CPUs and between 14 * CPUs and I/O masters. This file initializes the coherency fabric and 15 * supplies basic routines for configuring and controlling hardware coherency 16 */ 17 18 #define pr_fmt(fmt) "mvebu-coherency: " fmt 19 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/of_address.h> 23 #include <linux/io.h> 24 #include <linux/smp.h> 25 #include <linux/dma-map-ops.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 #include <linux/mbus.h> 29 #include <linux/pci.h> 30 #include <asm/smp_plat.h> 31 #include <asm/cacheflush.h> 32 #include <asm/mach/map.h> 33 #include <asm/dma-mapping.h> 34 #include "coherency.h" 35 #include "mvebu-soc-id.h" 36 37 unsigned long coherency_phys_base; 38 void __iomem *coherency_base; 39 static void __iomem *coherency_cpu_base; 40 static void __iomem *cpu_config_base; 41 42 /* Coherency fabric registers */ 43 #define IO_SYNC_BARRIER_CTL_OFFSET 0x0 44 45 enum { 46 COHERENCY_FABRIC_TYPE_NONE, 47 COHERENCY_FABRIC_TYPE_ARMADA_370_XP, 48 COHERENCY_FABRIC_TYPE_ARMADA_375, 49 COHERENCY_FABRIC_TYPE_ARMADA_380, 50 }; 51 52 static const struct of_device_id of_coherency_table[] = { 53 {.compatible = "marvell,coherency-fabric", 54 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP }, 55 {.compatible = "marvell,armada-375-coherency-fabric", 56 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 }, 57 {.compatible = "marvell,armada-380-coherency-fabric", 58 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 }, 59 { /* end of list */ }, 60 }; 61 62 /* Functions defined in coherency_ll.S */ 63 int ll_enable_coherency(void); 64 void ll_add_cpu_to_smp_group(void); 65 66 #define CPU_CONFIG_SHARED_L2 BIT(16) 67 68 /* 69 * Disable the "Shared L2 Present" bit in CPU Configuration register 70 * on Armada XP. 71 * 72 * The "Shared L2 Present" bit affects the "level of coherence" value 73 * in the clidr CP15 register. Cache operation functions such as 74 * "flush all" and "invalidate all" operate on all the cache levels 75 * that included in the defined level of coherence. When HW I/O 76 * coherency is used, this bit causes unnecessary flushes of the L2 77 * cache. 78 */ 79 static void armada_xp_clear_shared_l2(void) 80 { 81 u32 reg; 82 83 if (!cpu_config_base) 84 return; 85 86 reg = readl(cpu_config_base); 87 reg &= ~CPU_CONFIG_SHARED_L2; 88 writel(reg, cpu_config_base); 89 } 90 91 static int mvebu_hwcc_notifier(struct notifier_block *nb, 92 unsigned long event, void *__dev) 93 { 94 struct device *dev = __dev; 95 96 if (event != BUS_NOTIFY_ADD_DEVICE) 97 return NOTIFY_DONE; 98 dev_set_dma_coherent(dev); 99 100 return NOTIFY_OK; 101 } 102 103 static struct notifier_block mvebu_hwcc_nb = { 104 .notifier_call = mvebu_hwcc_notifier, 105 }; 106 107 static struct notifier_block mvebu_hwcc_pci_nb __maybe_unused = { 108 .notifier_call = mvebu_hwcc_notifier, 109 }; 110 111 static int armada_xp_clear_l2_starting(unsigned int cpu) 112 { 113 armada_xp_clear_shared_l2(); 114 return 0; 115 } 116 117 static void __init armada_370_coherency_init(struct device_node *np) 118 { 119 struct resource res; 120 struct device_node *cpu_config_np; 121 122 of_address_to_resource(np, 0, &res); 123 coherency_phys_base = res.start; 124 /* 125 * Ensure secondary CPUs will see the updated value, 126 * which they read before they join the coherency 127 * fabric, and therefore before they are coherent with 128 * the boot CPU cache. 129 */ 130 sync_cache_w(&coherency_phys_base); 131 coherency_base = of_iomap(np, 0); 132 coherency_cpu_base = of_iomap(np, 1); 133 134 cpu_config_np = of_find_compatible_node(NULL, NULL, 135 "marvell,armada-xp-cpu-config"); 136 137 cpu_config_base = of_iomap(cpu_config_np, 0); 138 of_node_put(cpu_config_np); 139 if (!cpu_config_base) 140 goto exit; 141 142 cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_COHERENCY, 143 "arm/mvebu/coherency:starting", 144 armada_xp_clear_l2_starting, NULL); 145 exit: 146 set_cpu_coherent(); 147 } 148 149 /* 150 * This ioremap hook is used on Armada 375/38x to ensure that all MMIO 151 * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is 152 * needed for the HW I/O coherency mechanism to work properly without 153 * deadlock. 154 */ 155 static void __iomem * 156 armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size, 157 unsigned int mtype, void *caller) 158 { 159 mtype = MT_UNCACHED; 160 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 161 } 162 163 static void __init armada_375_380_coherency_init(struct device_node *np) 164 { 165 struct device_node *cache_dn; 166 167 coherency_cpu_base = of_iomap(np, 0); 168 arch_ioremap_caller = armada_wa_ioremap_caller; 169 pci_ioremap_set_mem_type(MT_UNCACHED); 170 171 /* 172 * We should switch the PL310 to I/O coherency mode only if 173 * I/O coherency is actually enabled. 174 */ 175 if (!coherency_available()) 176 return; 177 178 /* 179 * Add the PL310 property "arm,io-coherent". This makes sure the 180 * outer sync operation is not used, which allows to 181 * workaround the system erratum that causes deadlocks when 182 * doing PCIe in an SMP situation on Armada 375 and Armada 183 * 38x. 184 */ 185 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") { 186 struct property *p; 187 188 p = kzalloc_obj(*p); 189 p->name = kstrdup("arm,io-coherent", GFP_KERNEL); 190 of_add_property(cache_dn, p); 191 } 192 } 193 194 static int coherency_type(void) 195 { 196 struct device_node *np; 197 const struct of_device_id *match; 198 int type; 199 200 /* 201 * The coherency fabric is needed: 202 * - For coherency between processors on Armada XP, so only 203 * when SMP is enabled. 204 * - For coherency between the processor and I/O devices, but 205 * this coherency requires many pre-requisites (write 206 * allocate cache policy, shareable pages, SMP bit set) that 207 * are only meant in SMP situations. 208 * 209 * Note that this means that on Armada 370, there is currently 210 * no way to use hardware I/O coherency, because even when 211 * CONFIG_SMP is enabled, is_smp() returns false due to the 212 * Armada 370 being a single-core processor. To lift this 213 * limitation, we would have to find a way to make the cache 214 * policy set to write-allocate (on all Armada SoCs), and to 215 * set the shareable attribute in page tables (on all Armada 216 * SoCs except the Armada 370). Unfortunately, such decisions 217 * are taken very early in the kernel boot process, at a point 218 * where we don't know yet on which SoC we are running. 219 220 */ 221 if (!is_smp()) 222 return COHERENCY_FABRIC_TYPE_NONE; 223 224 np = of_find_matching_node_and_match(NULL, of_coherency_table, &match); 225 if (!np) 226 return COHERENCY_FABRIC_TYPE_NONE; 227 228 type = (int) match->data; 229 230 of_node_put(np); 231 232 return type; 233 } 234 235 int set_cpu_coherent(void) 236 { 237 int type = coherency_type(); 238 239 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) { 240 if (!coherency_base) { 241 pr_warn("Can't make current CPU cache coherent.\n"); 242 pr_warn("Coherency fabric is not initialized\n"); 243 return 1; 244 } 245 246 armada_xp_clear_shared_l2(); 247 ll_add_cpu_to_smp_group(); 248 return ll_enable_coherency(); 249 } 250 251 return 0; 252 } 253 254 int coherency_available(void) 255 { 256 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; 257 } 258 259 int __init coherency_init(void) 260 { 261 int type = coherency_type(); 262 struct device_node *np; 263 264 np = of_find_matching_node(NULL, of_coherency_table); 265 266 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) 267 armada_370_coherency_init(np); 268 else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 || 269 type == COHERENCY_FABRIC_TYPE_ARMADA_380) 270 armada_375_380_coherency_init(np); 271 272 of_node_put(np); 273 274 return 0; 275 } 276 277 static int __init coherency_late_init(void) 278 { 279 if (coherency_available()) 280 bus_register_notifier(&platform_bus_type, 281 &mvebu_hwcc_nb); 282 return 0; 283 } 284 285 postcore_initcall(coherency_late_init); 286 287 #if IS_ENABLED(CONFIG_PCI) 288 static int __init coherency_pci_init(void) 289 { 290 if (coherency_available()) 291 bus_register_notifier(&pci_bus_type, 292 &mvebu_hwcc_pci_nb); 293 return 0; 294 } 295 296 arch_initcall(coherency_pci_init); 297 #endif 298