1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/notifier.h>
49 #include <linux/refcount.h>
50 #include <linux/auxiliary_bus.h>
51 #include <linux/mutex.h>
52
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59
60 #define MLX5_ADEV_NAME "mlx5_core"
61
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64 enum {
65 MLX5_BOARD_ID_LEN = 64,
66 };
67
68 enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70 };
71
72 enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76 };
77
78 enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84 };
85
86 enum {
87 MLX5_MAX_PORTS = 8,
88 };
89
90 enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100 };
101
102 enum {
103 MLX5_REG_SBPR = 0xb001,
104 MLX5_REG_SBCM = 0xb002,
105 MLX5_REG_QPTS = 0x4002,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_QPDPM = 0x4013,
109 MLX5_REG_QCAM = 0x4019,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_CORE_DUMP = 0x402e,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PPTB = 0x500b,
123 MLX5_REG_PBMC = 0x500c,
124 MLX5_REG_PMAOS = 0x5012,
125 MLX5_REG_PUDE = 0x5009,
126 MLX5_REG_PMPE = 0x5010,
127 MLX5_REG_PELC = 0x500e,
128 MLX5_REG_PVLC = 0x500f,
129 MLX5_REG_PCMR = 0x5041,
130 MLX5_REG_PDDR = 0x5031,
131 MLX5_REG_PMLP = 0x5002,
132 MLX5_REG_PPLM = 0x5023,
133 MLX5_REG_PCAM = 0x507f,
134 MLX5_REG_NODE_DESC = 0x6001,
135 MLX5_REG_HOST_ENDIANNESS = 0x7004,
136 MLX5_REG_MTCAP = 0x9009,
137 MLX5_REG_MTMP = 0x900A,
138 MLX5_REG_MCIA = 0x9014,
139 MLX5_REG_MFRL = 0x9028,
140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MRTC = 0x902d,
142 MLX5_REG_MTRC_CAP = 0x9040,
143 MLX5_REG_MTRC_CONF = 0x9041,
144 MLX5_REG_MTRC_STDB = 0x9042,
145 MLX5_REG_MTRC_CTRL = 0x9043,
146 MLX5_REG_MPEIN = 0x9050,
147 MLX5_REG_MPCNT = 0x9051,
148 MLX5_REG_MTPPS = 0x9053,
149 MLX5_REG_MTPPSE = 0x9054,
150 MLX5_REG_MTUTC = 0x9055,
151 MLX5_REG_MPEGC = 0x9056,
152 MLX5_REG_MPIR = 0x9059,
153 MLX5_REG_MCQS = 0x9060,
154 MLX5_REG_MCQI = 0x9061,
155 MLX5_REG_MCC = 0x9062,
156 MLX5_REG_MCDA = 0x9063,
157 MLX5_REG_MCAM = 0x907f,
158 MLX5_REG_MSECQ = 0x9155,
159 MLX5_REG_MSEES = 0x9156,
160 MLX5_REG_MIRC = 0x9162,
161 MLX5_REG_MTPTM = 0x9180,
162 MLX5_REG_MTCTR = 0x9181,
163 MLX5_REG_SBCAM = 0xB01F,
164 MLX5_REG_RESOURCE_DUMP = 0xC000,
165 MLX5_REG_DTOR = 0xC00E,
166 };
167
168 enum mlx5_qpts_trust_state {
169 MLX5_QPTS_TRUST_PCP = 1,
170 MLX5_QPTS_TRUST_DSCP = 2,
171 };
172
173 enum mlx5_dcbx_oper_mode {
174 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
175 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
176 };
177
178 enum {
179 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
180 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
181 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
182 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
183 };
184
185 enum mlx5_page_fault_resume_flags {
186 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
187 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
188 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
189 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
190 };
191
192 enum dbg_rsc_type {
193 MLX5_DBG_RSC_QP,
194 MLX5_DBG_RSC_EQ,
195 MLX5_DBG_RSC_CQ,
196 };
197
198 enum port_state_policy {
199 MLX5_POLICY_DOWN = 0,
200 MLX5_POLICY_UP = 1,
201 MLX5_POLICY_FOLLOW = 2,
202 MLX5_POLICY_INVALID = 0xffffffff
203 };
204
205 enum mlx5_coredev_type {
206 MLX5_COREDEV_PF,
207 MLX5_COREDEV_VF,
208 MLX5_COREDEV_SF,
209 };
210
211 struct mlx5_field_desc {
212 int i;
213 };
214
215 struct mlx5_rsc_debug {
216 struct mlx5_core_dev *dev;
217 void *object;
218 enum dbg_rsc_type type;
219 struct dentry *root;
220 struct mlx5_field_desc fields[];
221 };
222
223 enum mlx5_dev_event {
224 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
225 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
226 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
227 };
228
229 enum mlx5_port_status {
230 MLX5_PORT_UP = 1,
231 MLX5_PORT_DOWN = 2,
232 };
233
234 enum mlx5_cmdif_state {
235 MLX5_CMDIF_STATE_UNINITIALIZED,
236 MLX5_CMDIF_STATE_UP,
237 MLX5_CMDIF_STATE_DOWN,
238 };
239
240 struct mlx5_cmd_first {
241 __be32 data[4];
242 };
243
244 struct mlx5_cmd_msg {
245 struct list_head list;
246 struct cmd_msg_cache *parent;
247 u32 len;
248 struct mlx5_cmd_first first;
249 struct mlx5_cmd_mailbox *next;
250 };
251
252 struct mlx5_cmd_debug {
253 struct dentry *dbg_root;
254 void *in_msg;
255 void *out_msg;
256 u8 status;
257 u16 inlen;
258 u16 outlen;
259 };
260
261 struct cmd_msg_cache {
262 /* protect block chain allocations
263 */
264 spinlock_t lock;
265 struct list_head head;
266 unsigned int max_inbox_size;
267 unsigned int num_ent;
268 };
269
270 enum {
271 MLX5_NUM_COMMAND_CACHES = 5,
272 };
273
274 struct mlx5_cmd_stats {
275 u64 sum;
276 u64 n;
277 /* number of times command failed */
278 u64 failed;
279 /* number of times command failed on bad status returned by FW */
280 u64 failed_mbox_status;
281 /* last command failed returned errno */
282 u32 last_failed_errno;
283 /* last bad status returned by FW */
284 u8 last_failed_mbox_status;
285 /* last command failed syndrome returned by FW */
286 u32 last_failed_syndrome;
287 struct dentry *root;
288 /* protect command average calculations */
289 spinlock_t lock;
290 };
291
292 struct mlx5_cmd {
293 struct mlx5_nb nb;
294
295 /* members which needs to be queried or reinitialized each reload */
296 struct {
297 u16 cmdif_rev;
298 u8 log_sz;
299 u8 log_stride;
300 int max_reg_cmds;
301 unsigned long bitmask;
302 struct semaphore sem;
303 struct semaphore pages_sem;
304 struct semaphore throttle_sem;
305 } vars;
306 enum mlx5_cmdif_state state;
307 void *cmd_alloc_buf;
308 dma_addr_t alloc_dma;
309 int alloc_size;
310 void *cmd_buf;
311 dma_addr_t dma;
312
313 /* protect command queue allocations
314 */
315 spinlock_t alloc_lock;
316
317 /* protect token allocations
318 */
319 spinlock_t token_lock;
320 u8 token;
321 char wq_name[MLX5_CMD_WQ_MAX_NAME];
322 struct workqueue_struct *wq;
323 int mode;
324 u16 allowed_opcode;
325 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
326 struct dma_pool *pool;
327 struct mlx5_cmd_debug dbg;
328 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
329 int checksum_disabled;
330 struct xarray stats;
331 };
332
333 struct mlx5_cmd_mailbox {
334 void *buf;
335 dma_addr_t dma;
336 struct mlx5_cmd_mailbox *next;
337 };
338
339 struct mlx5_buf_list {
340 void *buf;
341 dma_addr_t map;
342 };
343
344 struct mlx5_frag_buf {
345 struct mlx5_buf_list *frags;
346 int npages;
347 int size;
348 u8 page_shift;
349 };
350
351 struct mlx5_frag_buf_ctrl {
352 struct mlx5_buf_list *frags;
353 u32 sz_m1;
354 u16 frag_sz_m1;
355 u16 strides_offset;
356 u8 log_sz;
357 u8 log_stride;
358 u8 log_frag_strides;
359 };
360
361 struct mlx5_core_psv {
362 u32 psv_idx;
363 struct psv_layout {
364 u32 pd;
365 u16 syndrome;
366 u16 reserved;
367 u16 bg;
368 u16 app_tag;
369 u32 ref_tag;
370 } psv;
371 };
372
373 struct mlx5_core_sig_ctx {
374 struct mlx5_core_psv psv_memory;
375 struct mlx5_core_psv psv_wire;
376 struct ib_sig_err err_item;
377 bool sig_status_checked;
378 bool sig_err_exists;
379 u32 sigerr_count;
380 };
381
382 #define MLX5_24BIT_MASK ((1 << 24) - 1)
383
384 enum mlx5_res_type {
385 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
386 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
387 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
388 MLX5_RES_SRQ = 3,
389 MLX5_RES_XSRQ = 4,
390 MLX5_RES_XRQ = 5,
391 };
392
393 struct mlx5_core_rsc_common {
394 enum mlx5_res_type res;
395 refcount_t refcount;
396 struct completion free;
397 };
398
399 struct mlx5_uars_page {
400 void __iomem *map;
401 bool wc;
402 u32 index;
403 struct list_head list;
404 unsigned int bfregs;
405 unsigned long *reg_bitmap; /* for non fast path bf regs */
406 unsigned long *fp_bitmap;
407 unsigned int reg_avail;
408 unsigned int fp_avail;
409 struct kref ref_count;
410 struct mlx5_core_dev *mdev;
411 };
412
413 struct mlx5_bfreg_head {
414 /* protect blue flame registers allocations */
415 struct mutex lock;
416 struct list_head list;
417 };
418
419 struct mlx5_bfreg_data {
420 struct mlx5_bfreg_head reg_head;
421 struct mlx5_bfreg_head wc_head;
422 };
423
424 struct mlx5_sq_bfreg {
425 void __iomem *map;
426 struct mlx5_uars_page *up;
427 bool wc;
428 u32 index;
429 unsigned int offset;
430 };
431
432 struct mlx5_core_health {
433 struct health_buffer __iomem *health;
434 __be32 __iomem *health_counter;
435 struct timer_list timer;
436 u32 prev;
437 int miss_counter;
438 u8 synd;
439 u32 fatal_error;
440 u32 crdump_size;
441 struct workqueue_struct *wq;
442 unsigned long flags;
443 struct work_struct fatal_report_work;
444 struct work_struct report_work;
445 struct devlink_health_reporter *fw_reporter;
446 struct devlink_health_reporter *fw_fatal_reporter;
447 struct devlink_health_reporter *vnic_reporter;
448 struct delayed_work update_fw_log_ts_work;
449 };
450
451 enum {
452 MLX5_PF_NOTIFY_DISABLE_VF,
453 MLX5_PF_NOTIFY_ENABLE_VF,
454 };
455
456 struct mlx5_vf_context {
457 int enabled;
458 u64 port_guid;
459 u64 node_guid;
460 /* Valid bits are used to validate administrative guid only.
461 * Enabled after ndo_set_vf_guid
462 */
463 u8 port_guid_valid:1;
464 u8 node_guid_valid:1;
465 enum port_state_policy policy;
466 struct blocking_notifier_head notifier;
467 };
468
469 struct mlx5_core_sriov {
470 struct mlx5_vf_context *vfs_ctx;
471 int num_vfs;
472 u16 max_vfs;
473 u16 max_ec_vfs;
474 };
475
476 struct mlx5_events;
477 struct mlx5_mpfs;
478 struct mlx5_eswitch;
479 struct mlx5_lag;
480 struct mlx5_devcom_dev;
481 struct mlx5_fw_reset;
482 struct mlx5_eq_table;
483 struct mlx5_irq_table;
484 struct mlx5_vhca_state_notifier;
485 struct mlx5_sf_dev_table;
486 struct mlx5_sf_hw_table;
487 struct mlx5_sf_table;
488 struct mlx5_crypto_dek_priv;
489
490 struct mlx5_rate_limit {
491 u32 rate;
492 u32 max_burst_sz;
493 u16 typical_pkt_sz;
494 };
495
496 struct mlx5_rl_entry {
497 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
498 u64 refcount;
499 u16 index;
500 u16 uid;
501 u8 dedicated : 1;
502 };
503
504 struct mlx5_rl_table {
505 /* protect rate limit table */
506 struct mutex rl_lock;
507 u16 max_size;
508 u32 max_rate;
509 u32 min_rate;
510 struct mlx5_rl_entry *rl_entry;
511 u64 refcount;
512 };
513
514 struct mlx5_core_roce {
515 struct mlx5_flow_table *ft;
516 struct mlx5_flow_group *fg;
517 struct mlx5_flow_handle *allow_rule;
518 };
519
520 enum {
521 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
522 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
523 /* Set during device detach to block any further devices
524 * creation/deletion on drivers rescan. Unset during device attach.
525 */
526 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
527 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
528 };
529
530 struct mlx5_adev {
531 struct auxiliary_device adev;
532 struct mlx5_core_dev *mdev;
533 int idx;
534 };
535
536 struct mlx5_debugfs_entries {
537 struct dentry *dbg_root;
538 struct dentry *qp_debugfs;
539 struct dentry *eq_debugfs;
540 struct dentry *cq_debugfs;
541 struct dentry *cmdif_debugfs;
542 struct dentry *pages_debugfs;
543 struct dentry *lag_debugfs;
544 };
545
546 enum mlx5_func_type {
547 MLX5_PF,
548 MLX5_VF,
549 MLX5_SF,
550 MLX5_HOST_PF,
551 MLX5_EC_VF,
552 MLX5_FUNC_TYPE_NUM,
553 };
554
555 struct mlx5_ft_pool;
556 struct mlx5_priv {
557 /* IRQ table valid only for real pci devices PF or VF */
558 struct mlx5_irq_table *irq_table;
559 struct mlx5_eq_table *eq_table;
560
561 /* pages stuff */
562 struct mlx5_nb pg_nb;
563 struct workqueue_struct *pg_wq;
564 struct xarray page_root_xa;
565 atomic_t reg_pages;
566 struct list_head free_list;
567 u32 fw_pages;
568 u32 page_counters[MLX5_FUNC_TYPE_NUM];
569 u32 fw_pages_alloc_failed;
570 u32 give_pages_dropped;
571 u32 reclaim_pages_discard;
572
573 struct mlx5_core_health health;
574 struct list_head traps;
575
576 struct mlx5_debugfs_entries dbg;
577
578 /* start: alloc staff */
579 /* protect buffer allocation according to numa node */
580 struct mutex alloc_mutex;
581 int numa_node;
582
583 struct mutex pgdir_mutex;
584 struct list_head pgdir_list;
585 /* end: alloc staff */
586
587 struct mlx5_adev **adev;
588 int adev_idx;
589 int sw_vhca_id;
590 struct mlx5_events *events;
591 struct mlx5_vhca_events *vhca_events;
592
593 struct mlx5_flow_steering *steering;
594 struct mlx5_mpfs *mpfs;
595 struct mlx5_eswitch *eswitch;
596 struct mlx5_core_sriov sriov;
597 struct mlx5_lag *lag;
598 u32 flags;
599 struct mlx5_devcom_dev *devc;
600 struct mlx5_devcom_comp_dev *hca_devcom_comp;
601 struct mlx5_fw_reset *fw_reset;
602 struct mlx5_core_roce roce;
603 struct mlx5_fc_stats *fc_stats;
604 struct mlx5_rl_table rl_table;
605 struct mlx5_ft_pool *ft_pool;
606
607 struct mlx5_bfreg_data bfregs;
608 struct mlx5_uars_page *uar;
609 #ifdef CONFIG_MLX5_SF
610 struct mlx5_vhca_state_notifier *vhca_state_notifier;
611 struct mlx5_sf_dev_table *sf_dev_table;
612 struct mlx5_core_dev *parent_mdev;
613 #endif
614 #ifdef CONFIG_MLX5_SF_MANAGER
615 struct mlx5_sf_hw_table *sf_hw_table;
616 struct mlx5_sf_table *sf_table;
617 #endif
618 struct blocking_notifier_head lag_nh;
619 };
620
621 enum mlx5_device_state {
622 MLX5_DEVICE_STATE_UP = 1,
623 MLX5_DEVICE_STATE_INTERNAL_ERROR,
624 };
625
626 enum mlx5_interface_state {
627 MLX5_INTERFACE_STATE_UP = BIT(0),
628 MLX5_BREAK_FW_WAIT = BIT(1),
629 };
630
631 enum mlx5_pci_status {
632 MLX5_PCI_STATUS_DISABLED,
633 MLX5_PCI_STATUS_ENABLED,
634 };
635
636 enum mlx5_pagefault_type_flags {
637 MLX5_PFAULT_REQUESTOR = 1 << 0,
638 MLX5_PFAULT_WRITE = 1 << 1,
639 MLX5_PFAULT_RDMA = 1 << 2,
640 };
641
642 struct mlx5_td {
643 /* protects tirs list changes while tirs refresh */
644 struct mutex list_lock;
645 struct list_head tirs_list;
646 u32 tdn;
647 };
648
649 struct mlx5e_resources {
650 struct mlx5e_hw_objs {
651 u32 pdn;
652 struct mlx5_td td;
653 u32 mkey;
654 struct mlx5_sq_bfreg bfreg;
655 #define MLX5_MAX_NUM_TC 8
656 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
657 bool tisn_valid;
658 } hw_objs;
659 struct net_device *uplink_netdev;
660 struct mutex uplink_netdev_lock;
661 struct mlx5_crypto_dek_priv *dek_priv;
662 };
663
664 enum mlx5_sw_icm_type {
665 MLX5_SW_ICM_TYPE_STEERING,
666 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
667 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
668 MLX5_SW_ICM_TYPE_SW_ENCAP,
669 };
670
671 #define MLX5_MAX_RESERVED_GIDS 8
672
673 struct mlx5_rsvd_gids {
674 unsigned int start;
675 unsigned int count;
676 struct ida ida;
677 };
678
679 #define MAX_PIN_NUM 8
680 struct mlx5_pps {
681 u8 pin_caps[MAX_PIN_NUM];
682 struct work_struct out_work;
683 u64 start[MAX_PIN_NUM];
684 u8 enabled;
685 u64 min_npps_period;
686 u64 min_out_pulse_duration_ns;
687 };
688
689 struct mlx5_timer {
690 struct cyclecounter cycles;
691 struct timecounter tc;
692 u32 nominal_c_mult;
693 unsigned long overflow_period;
694 struct delayed_work overflow_work;
695 };
696
697 struct mlx5_clock {
698 struct mlx5_nb pps_nb;
699 seqlock_t lock;
700 struct hwtstamp_config hwtstamp_config;
701 struct ptp_clock *ptp;
702 struct ptp_clock_info ptp_info;
703 struct mlx5_pps pps_info;
704 struct mlx5_timer timer;
705 };
706
707 struct mlx5_dm;
708 struct mlx5_fw_tracer;
709 struct mlx5_vxlan;
710 struct mlx5_geneve;
711 struct mlx5_hv_vhca;
712
713 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
714 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
715
716 enum {
717 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
718 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
719 };
720
721 enum {
722 MKEY_CACHE_LAST_STD_ENTRY = 20,
723 MLX5_IMR_KSM_CACHE_ENTRY,
724 MAX_MKEY_CACHE_ENTRIES
725 };
726
727 struct mlx5_profile {
728 u64 mask;
729 u8 log_max_qp;
730 u8 num_cmd_caches;
731 struct {
732 int size;
733 int limit;
734 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
735 };
736
737 struct mlx5_hca_cap {
738 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
739 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
740 };
741
742 enum mlx5_wc_state {
743 MLX5_WC_STATE_UNINITIALIZED,
744 MLX5_WC_STATE_UNSUPPORTED,
745 MLX5_WC_STATE_SUPPORTED,
746 };
747
748 struct mlx5_core_dev {
749 struct device *device;
750 enum mlx5_coredev_type coredev_type;
751 struct pci_dev *pdev;
752 /* sync pci state */
753 struct mutex pci_status_mutex;
754 enum mlx5_pci_status pci_status;
755 u8 rev_id;
756 char board_id[MLX5_BOARD_ID_LEN];
757 struct mlx5_cmd cmd;
758 struct {
759 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
760 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
761 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
762 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
763 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
764 u8 embedded_cpu;
765 } caps;
766 struct mlx5_timeouts *timeouts;
767 u64 sys_image_guid;
768 phys_addr_t iseg_base;
769 struct mlx5_init_seg __iomem *iseg;
770 phys_addr_t bar_addr;
771 enum mlx5_device_state state;
772 /* sync interface state */
773 struct mutex intf_state_mutex;
774 struct lock_class_key lock_key;
775 unsigned long intf_state;
776 struct mlx5_priv priv;
777 struct mlx5_profile profile;
778 u32 issi;
779 struct mlx5e_resources mlx5e_res;
780 struct mlx5_dm *dm;
781 struct mlx5_vxlan *vxlan;
782 struct mlx5_geneve *geneve;
783 struct {
784 struct mlx5_rsvd_gids reserved_gids;
785 u32 roce_en;
786 } roce;
787 #ifdef CONFIG_MLX5_FPGA
788 struct mlx5_fpga_device *fpga;
789 #endif
790 struct mlx5_clock clock;
791 struct mlx5_ib_clock_info *clock_info;
792 struct mlx5_fw_tracer *tracer;
793 struct mlx5_rsc_dump *rsc_dump;
794 u32 vsc_addr;
795 struct mlx5_hv_vhca *hv_vhca;
796 struct mlx5_hwmon *hwmon;
797 u64 num_block_tc;
798 u64 num_block_ipsec;
799 #ifdef CONFIG_MLX5_MACSEC
800 struct mlx5_macsec_fs *macsec_fs;
801 /* MACsec notifier chain to sync MACsec core and IB database */
802 struct blocking_notifier_head macsec_nh;
803 #endif
804 u64 num_ipsec_offloads;
805 struct mlx5_sd *sd;
806 enum mlx5_wc_state wc_state;
807 /* sync write combining state */
808 struct mutex wc_state_lock;
809 };
810
811 struct mlx5_db {
812 __be32 *db;
813 union {
814 struct mlx5_db_pgdir *pgdir;
815 struct mlx5_ib_user_db_page *user_page;
816 } u;
817 dma_addr_t dma;
818 int index;
819 };
820
821 enum {
822 MLX5_COMP_EQ_SIZE = 1024,
823 };
824
825 enum {
826 MLX5_PTYS_IB = 1 << 0,
827 MLX5_PTYS_EN = 1 << 2,
828 };
829
830 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
831
832 enum {
833 MLX5_CMD_ENT_STATE_PENDING_COMP,
834 };
835
836 struct mlx5_cmd_work_ent {
837 unsigned long state;
838 struct mlx5_cmd_msg *in;
839 struct mlx5_cmd_msg *out;
840 void *uout;
841 int uout_size;
842 mlx5_cmd_cbk_t callback;
843 struct delayed_work cb_timeout_work;
844 void *context;
845 int idx;
846 struct completion handling;
847 struct completion slotted;
848 struct completion done;
849 struct mlx5_cmd *cmd;
850 struct work_struct work;
851 struct mlx5_cmd_layout *lay;
852 int ret;
853 int page_queue;
854 u8 status;
855 u8 token;
856 u64 ts1;
857 u64 ts2;
858 u16 op;
859 bool polling;
860 /* Track the max comp handlers */
861 refcount_t refcnt;
862 };
863
864 enum phy_port_state {
865 MLX5_AAA_111
866 };
867
868 struct mlx5_hca_vport_context {
869 u32 field_select;
870 bool sm_virt_aware;
871 bool has_smi;
872 bool has_raw;
873 enum port_state_policy policy;
874 enum phy_port_state phys_state;
875 enum ib_port_state vport_state;
876 u8 port_physical_state;
877 u64 sys_image_guid;
878 u64 port_guid;
879 u64 node_guid;
880 u32 cap_mask1;
881 u32 cap_mask1_perm;
882 u16 cap_mask2;
883 u16 cap_mask2_perm;
884 u16 lid;
885 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
886 u8 lmc;
887 u8 subnet_timeout;
888 u16 sm_lid;
889 u8 sm_sl;
890 u16 qkey_violation_counter;
891 u16 pkey_violation_counter;
892 bool grh_required;
893 u8 num_plane;
894 };
895
896 #define STRUCT_FIELD(header, field) \
897 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
898 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
899
900 extern struct dentry *mlx5_debugfs_root;
901
fw_rev_maj(struct mlx5_core_dev * dev)902 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
903 {
904 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
905 }
906
fw_rev_min(struct mlx5_core_dev * dev)907 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
908 {
909 return ioread32be(&dev->iseg->fw_rev) >> 16;
910 }
911
fw_rev_sub(struct mlx5_core_dev * dev)912 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
913 {
914 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
915 }
916
mlx5_base_mkey(const u32 key)917 static inline u32 mlx5_base_mkey(const u32 key)
918 {
919 return key & 0xffffff00u;
920 }
921
wq_get_byte_sz(u8 log_sz,u8 log_stride)922 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
923 {
924 return ((u32)1 << log_sz) << log_stride;
925 }
926
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)927 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
928 u8 log_stride, u8 log_sz,
929 u16 strides_offset,
930 struct mlx5_frag_buf_ctrl *fbc)
931 {
932 fbc->frags = frags;
933 fbc->log_stride = log_stride;
934 fbc->log_sz = log_sz;
935 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
936 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
937 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
938 fbc->strides_offset = strides_offset;
939 }
940
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)941 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
942 u8 log_stride, u8 log_sz,
943 struct mlx5_frag_buf_ctrl *fbc)
944 {
945 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
946 }
947
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)948 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
949 u32 ix)
950 {
951 unsigned int frag;
952
953 ix += fbc->strides_offset;
954 frag = ix >> fbc->log_frag_strides;
955
956 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
957 }
958
959 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)960 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
961 {
962 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
963
964 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
965 }
966
967 enum {
968 CMD_ALLOWED_OPCODE_ALL,
969 };
970
971 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
972 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
973 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
974
975 struct mlx5_async_ctx {
976 struct mlx5_core_dev *dev;
977 atomic_t num_inflight;
978 struct completion inflight_done;
979 };
980
981 struct mlx5_async_work;
982
983 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
984
985 struct mlx5_async_work {
986 struct mlx5_async_ctx *ctx;
987 mlx5_async_cbk_t user_callback;
988 u16 opcode; /* cmd opcode */
989 u16 op_mod; /* cmd op_mod */
990 void *out; /* pointer to the cmd output buffer */
991 };
992
993 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
994 struct mlx5_async_ctx *ctx);
995 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
996 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
997 void *out, int out_size, mlx5_async_cbk_t callback,
998 struct mlx5_async_work *work);
999 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1000 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1001 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1002 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1003 int out_size);
1004
1005 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1006 ({ \
1007 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1008 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1009 })
1010
1011 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1012 ({ \
1013 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1014 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1015 })
1016
1017 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1018 void *out, int out_size);
1019 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1020
1021 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1022 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1023
1024 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1025
1026 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1027 int mlx5_health_init(struct mlx5_core_dev *dev);
1028 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1029 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1030 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1031 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1032 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1033 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1034 struct mlx5_frag_buf *buf, int node);
1035 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1036 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1037 int inlen);
1038 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1039 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1040 int outlen);
1041 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1042 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1043 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1044 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1045 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1046 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1047 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1048 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1049 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1050 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1051 void mlx5_register_debugfs(void);
1052 void mlx5_unregister_debugfs(void);
1053
1054 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1055 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1056 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1057 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1058 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1059
1060 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1061 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1062 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1063 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1064 void *data_out, int size_out, u16 reg_id, int arg,
1065 int write, bool verbose);
1066 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1067 int size_in, void *data_out, int size_out,
1068 u16 reg_num, int arg, int write);
1069
1070 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1071 int node);
1072
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1073 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1074 {
1075 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1076 }
1077
1078 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1079
1080 const char *mlx5_command_str(int command);
1081 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1082 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1083 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1084 int npsvs, u32 *sig_index);
1085 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1086 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1087 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1088
1089 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1090 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1091 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1092 struct mlx5_rate_limit *rl);
1093 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1094 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1095 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1096 bool dedicated_entry, u16 *index);
1097 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1098 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1099 struct mlx5_rate_limit *rl_1);
1100 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1101 bool map_wc, bool fast_path);
1102 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1103
1104 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1105 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1106 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1107 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1108 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1109 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1110
mlx5_mkey_to_idx(u32 mkey)1111 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1112 {
1113 return mkey >> 8;
1114 }
1115
mlx5_idx_to_mkey(u32 mkey_idx)1116 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1117 {
1118 return mkey_idx << 8;
1119 }
1120
mlx5_mkey_variant(u32 mkey)1121 static inline u8 mlx5_mkey_variant(u32 mkey)
1122 {
1123 return mkey & 0xff;
1124 }
1125
1126 /* Async-atomic event notifier used by mlx5 core to forward FW
1127 * evetns received from event queue to mlx5 consumers.
1128 * Optimise event queue dipatching.
1129 */
1130 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1131 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1132
1133 /* Async-atomic event notifier used for forwarding
1134 * evetns from the event queue into the to mlx5 events dispatcher,
1135 * eswitch, clock and others.
1136 */
1137 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1138 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1139
1140 /* Blocking event notifier used to forward SW events, used for slow path */
1141 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1142 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1143 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1144 void *data);
1145
1146 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1147
1148 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1149 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1150 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1151 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1152 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1153 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1154 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1155 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1156 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1157 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1158 struct net_device *slave);
1159 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1160 u64 *values,
1161 int num_counters,
1162 size_t *offsets);
1163 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1164
1165 #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1166 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1167 peer; \
1168 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1169
1170 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1171 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1172 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1173 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1174 u64 length, u32 log_alignment, u16 uid,
1175 phys_addr_t *addr, u32 *obj_id);
1176 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1177 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1178
1179 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1180 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1181
1182 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1183 int vf_id,
1184 struct notifier_block *nb);
1185 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1186 int vf_id,
1187 struct notifier_block *nb);
1188 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1189 struct ib_device *device,
1190 struct rdma_netdev_alloc_params *params);
1191
1192 enum {
1193 MLX5_PCI_DEV_IS_VF = 1 << 0,
1194 };
1195
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1196 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1197 {
1198 return dev->coredev_type == MLX5_COREDEV_PF;
1199 }
1200
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1201 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1202 {
1203 return dev->coredev_type == MLX5_COREDEV_VF;
1204 }
1205
mlx5_core_same_coredev_type(const struct mlx5_core_dev * dev1,const struct mlx5_core_dev * dev2)1206 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1207 const struct mlx5_core_dev *dev2)
1208 {
1209 return dev1->coredev_type == dev2->coredev_type;
1210 }
1211
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1212 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1213 {
1214 return dev->caps.embedded_cpu;
1215 }
1216
1217 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1218 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1219 {
1220 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1221 }
1222
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1223 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1224 {
1225 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1226 }
1227
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1228 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1229 {
1230 return dev->priv.sriov.max_vfs;
1231 }
1232
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1233 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1234 {
1235 /* LACP owner conditions:
1236 * 1) Function is physical.
1237 * 2) LAG is supported by FW.
1238 * 3) LAG is managed by driver (currently the only option).
1239 */
1240 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1241 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1242 MLX5_CAP_GEN(dev, lag_master);
1243 }
1244
mlx5_core_max_ec_vfs(const struct mlx5_core_dev * dev)1245 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1246 {
1247 return dev->priv.sriov.max_ec_vfs;
1248 }
1249
mlx5_get_gid_table_len(u16 param)1250 static inline int mlx5_get_gid_table_len(u16 param)
1251 {
1252 if (param > 4) {
1253 pr_warn("gid table length is zero\n");
1254 return 0;
1255 }
1256
1257 return 8 * (1 << param);
1258 }
1259
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1260 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1261 {
1262 return !!(dev->priv.rl_table.max_size);
1263 }
1264
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1265 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1266 {
1267 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1268 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1269 }
1270
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1271 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1272 {
1273 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1274 }
1275
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1276 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1277 {
1278 return mlx5_core_is_mp_slave(dev) ||
1279 mlx5_core_is_mp_master(dev);
1280 }
1281
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1282 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1283 {
1284 if (!mlx5_core_mp_enabled(dev))
1285 return 1;
1286
1287 return MLX5_CAP_GEN(dev, native_port_num);
1288 }
1289
mlx5_get_dev_index(struct mlx5_core_dev * dev)1290 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1291 {
1292 int idx = MLX5_CAP_GEN(dev, native_port_num);
1293
1294 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1295 return idx - 1;
1296 else
1297 return PCI_FUNC(dev->pdev->devfn);
1298 }
1299
1300 enum {
1301 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1302 };
1303
1304 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1305
mlx5_get_roce_state(struct mlx5_core_dev * dev)1306 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1307 {
1308 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1309 return MLX5_CAP_GEN(dev, roce);
1310
1311 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1312 * in order to support RoCE enable/disable feature
1313 */
1314 return mlx5_is_roce_on(dev);
1315 }
1316
1317 #ifdef CONFIG_MLX5_MACSEC
mlx5e_is_macsec_device(const struct mlx5_core_dev * mdev)1318 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1319 {
1320 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1321 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1322 return false;
1323
1324 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1325 return false;
1326
1327 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1328 return false;
1329
1330 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1331 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1332 return false;
1333
1334 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1335 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1336 return false;
1337
1338 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1339 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1340 return false;
1341
1342 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1343 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1344 return false;
1345
1346 return true;
1347 }
1348
1349 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1350
mlx5_is_macsec_roce_supported(struct mlx5_core_dev * mdev)1351 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1352 {
1353 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1354 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1355 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1356 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1357 return false;
1358
1359 return true;
1360 }
1361 #endif
1362
1363 enum {
1364 MLX5_OCTWORD = 16,
1365 };
1366
1367 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1368 #endif /* MLX5_DRIVER_H */
1369