1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __AUDIOREACH_H__ 4 #define __AUDIOREACH_H__ 5 #include <linux/types.h> 6 #include <linux/soc/qcom/apr.h> 7 #include <uapi/sound/snd_ar_tokens.h> 8 #include <sound/soc.h> 9 struct q6apm; 10 struct q6apm_graph; 11 12 /* Module IDs */ 13 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 14 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 15 #define MODULE_ID_GAIN 0x07001002 16 #define MODULE_ID_PCM_CNV 0x07001003 17 #define MODULE_ID_PCM_ENC 0x07001004 18 #define MODULE_ID_PCM_DEC 0x07001005 19 #define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008 20 #define MODULE_ID_PLACEHOLDER_DECODER 0x07001009 21 #define MODULE_ID_I2S_SINK 0x0700100A 22 #define MODULE_ID_I2S_SOURCE 0x0700100B 23 #define MODULE_ID_SAL 0x07001010 24 #define MODULE_ID_MFC 0x07001015 25 #define MODULE_ID_DATA_LOGGING 0x0700101A 26 #define MODULE_ID_AAC_DEC 0x0700101F 27 #define MODULE_ID_CODEC_DMA_SINK 0x07001023 28 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 29 #define MODULE_ID_FLAC_DEC 0x0700102F 30 #define MODULE_ID_SMECNS_V2 0x07001031 31 #define MODULE_ID_MP3_DECODE 0x0700103B 32 #define MODULE_ID_GAPLESS 0x0700104D 33 #define MODULE_ID_DISPLAY_PORT_SINK 0x07001069 34 #define MODULE_ID_OPUS_DEC 0x07001174 35 36 #define APM_CMD_GET_SPF_STATE 0x01001021 37 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007 38 39 #define APM_MODULE_INSTANCE_ID 0x00000001 40 #define PRM_MODULE_INSTANCE_ID 0x00000002 41 #define AMDB_MODULE_INSTANCE_ID 0x00000003 42 #define VCPM_MODULE_INSTANCE_ID 0x00000004 43 #define AR_MODULE_INSTANCE_ID_START 0x00006000 44 #define AR_MODULE_INSTANCE_ID_END 0x00007000 45 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 46 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 47 #define AR_CONT_INSTANCE_ID_START 0x00005000 48 #define AR_CONT_INSTANCE_ID_END 0x00006000 49 #define AR_SG_INSTANCE_ID_START 0x00004000 50 51 #define APM_CMD_GRAPH_OPEN 0x01001000 52 #define APM_CMD_GRAPH_PREPARE 0x01001001 53 #define APM_CMD_GRAPH_START 0x01001002 54 #define APM_CMD_GRAPH_STOP 0x01001003 55 #define APM_CMD_GRAPH_CLOSE 0x01001004 56 #define APM_CMD_GRAPH_FLUSH 0x01001005 57 #define APM_CMD_SET_CFG 0x01001006 58 #define APM_CMD_GET_CFG 0x01001007 59 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C 60 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D 61 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 62 #define APM_CMD_RSP_GET_CFG 0x02001000 63 #define APM_CMD_CLOSE_ALL 0x01001013 64 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A 65 66 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 67 68 struct apm_cmd_shared_mem_map_regions { 69 uint16_t mem_pool_id; 70 uint16_t num_regions; 71 uint32_t property_flag; 72 } __packed; 73 74 struct apm_shared_map_region_payload { 75 uint32_t shm_addr_lsw; 76 uint32_t shm_addr_msw; 77 uint32_t mem_size_bytes; 78 } __packed; 79 80 struct apm_cmd_shared_mem_unmap_regions { 81 uint32_t mem_map_handle; 82 } __packed; 83 84 struct apm_cmd_rsp_shared_mem_map_regions { 85 uint32_t mem_map_handle; 86 } __packed; 87 88 /* APM module */ 89 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 90 91 #define APM_PARAM_ID_MODULE_LIST 0x08001002 92 93 struct apm_param_id_modules_list { 94 uint32_t num_modules_list; 95 } __packed; 96 97 #define APM_PARAM_ID_MODULE_PROP 0x08001003 98 99 struct apm_param_id_module_prop { 100 uint32_t num_modules_prop_cfg; 101 } __packed; 102 103 struct apm_module_prop_cfg { 104 uint32_t instance_id; 105 uint32_t num_props; 106 } __packed; 107 108 #define APM_PARAM_ID_MODULE_CONN 0x08001004 109 110 struct apm_param_id_module_conn { 111 uint32_t num_connections; 112 } __packed; 113 114 struct apm_module_conn_obj { 115 uint32_t src_mod_inst_id; 116 uint32_t src_mod_op_port_id; 117 uint32_t dst_mod_inst_id; 118 uint32_t dst_mod_ip_port_id; 119 } __packed; 120 121 #define APM_PARAM_ID_GAIN 0x08001006 122 123 struct param_id_gain_cfg { 124 uint16_t gain; 125 uint16_t reserved; 126 } __packed; 127 128 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 129 130 struct param_id_pcm_output_format_cfg { 131 uint32_t data_format; 132 uint32_t fmt_id; 133 uint32_t payload_size; 134 } __packed; 135 136 struct payload_pcm_output_format_cfg { 137 uint16_t bit_width; 138 uint16_t alignment; 139 uint16_t bits_per_sample; 140 uint16_t q_factor; 141 uint16_t endianness; 142 uint16_t interleaved; 143 uint16_t reserved; 144 uint16_t num_channels; 145 uint8_t channel_mapping[]; 146 } __packed; 147 148 #define PARAM_ID_ENC_BITRATE 0x08001052 149 150 struct param_id_enc_bitrate_param { 151 uint32_t bitrate; 152 } __packed; 153 154 #define DATA_FORMAT_FIXED_POINT 1 155 #define DATA_FORMAT_GENERIC_COMPRESSED 5 156 #define DATA_FORMAT_RAW_COMPRESSED 6 157 #define PCM_LSB_ALIGNED 1 158 #define PCM_MSB_ALIGNED 2 159 #define PCM_LITTLE_ENDIAN 1 160 #define PCM_BIT_ENDIAN 2 161 162 #define MEDIA_FMT_ID_PCM 0x09001000 163 #define MEDIA_FMT_ID_MP3 0x09001009 164 #define SAMPLE_RATE_48K 48000 165 #define BIT_WIDTH_16 16 166 167 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 168 169 struct apm_modules_prop_info { 170 uint32_t max_ip_port; 171 uint32_t max_op_port; 172 } __packed; 173 174 /* Shared memory module */ 175 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 176 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) 177 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) 178 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) 179 #define WR_SH_MEM_EP_EOF_FLAG BIT(4) 180 181 struct apm_data_cmd_wr_sh_mem_ep_data_buffer { 182 uint32_t buf_addr_lsw; 183 uint32_t buf_addr_msw; 184 uint32_t mem_map_handle; 185 uint32_t buf_size; 186 uint32_t timestamp_lsw; 187 uint32_t timestamp_msw; 188 uint32_t flags; 189 } __packed; 190 191 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A 192 193 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { 194 uint32_t buf_addr_lsw; 195 uint32_t buf_addr_msw; 196 uint32_t mem_map_handle; 197 uint32_t buf_size; 198 uint32_t timestamp_lsw; 199 uint32_t timestamp_msw; 200 uint32_t flags; 201 uint32_t md_addr_lsw; 202 uint32_t md_addr_msw; 203 uint32_t md_map_handle; 204 uint32_t md_buf_size; 205 } __packed; 206 207 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 208 209 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { 210 uint32_t buf_addr_lsw; 211 uint32_t buf_addr_msw; 212 uint32_t mem_map_handle; 213 uint32_t status; 214 215 } __packed; 216 217 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 218 219 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { 220 uint32_t buf_addr_lsw; 221 uint32_t buf_addr_msw; 222 uint32_t mem_map_handle; 223 uint32_t status; 224 uint32_t md_buf_addr_lsw; 225 uint32_t md_buf_addr_msw; 226 uint32_t md_mem_map_handle; 227 uint32_t md_status; 228 } __packed; 229 230 #define PARAM_ID_MEDIA_FORMAT 0x0800100C 231 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 232 233 struct apm_media_format { 234 uint32_t data_format; 235 uint32_t fmt_id; 236 uint32_t payload_size; 237 } __packed; 238 239 #define MEDIA_FMT_ID_FLAC 0x09001004 240 241 struct payload_media_fmt_flac_t { 242 uint16_t num_channels; 243 uint16_t sample_size; 244 uint16_t min_blk_size; 245 uint16_t max_blk_size; 246 uint32_t sample_rate; 247 uint32_t min_frame_size; 248 uint32_t max_frame_size; 249 } __packed; 250 251 #define MEDIA_FMT_ID_AAC 0x09001001 252 253 struct payload_media_fmt_aac_t { 254 uint16_t aac_fmt_flag; 255 uint16_t audio_obj_type; 256 uint16_t num_channels; 257 uint16_t total_size_of_PCE_bits; 258 uint32_t sample_rate; 259 } __packed; 260 261 #define MEDIA_FMT_ID_OPUS 0x09001039 262 struct payload_media_fmt_opus_t { 263 uint16_t bitstream_format; 264 uint16_t payload_type; 265 uint8_t version; 266 uint8_t num_channels; 267 uint16_t pre_skip; 268 uint32_t sample_rate; 269 uint16_t output_gain; 270 uint8_t mapping_family; 271 uint8_t stream_count; 272 uint8_t coupled_count; 273 uint8_t channel_mapping[8]; 274 uint8_t reserved[3]; 275 } __packed; 276 277 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 278 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1 279 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2 280 281 struct data_cmd_wr_sh_mem_ep_eos { 282 uint32_t policy; 283 284 } __packed; 285 286 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 287 288 struct data_cmd_rd_sh_mem_ep_data_buffer { 289 uint32_t buf_addr_lsw; 290 uint32_t buf_addr_msw; 291 uint32_t mem_map_handle; 292 uint32_t buf_size; 293 } __packed; 294 295 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 296 297 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { 298 uint32_t status; 299 uint32_t buf_addr_lsw; 300 uint32_t buf_addr_msw; 301 uint32_t mem_map_handle; 302 uint32_t data_size; 303 uint32_t offset; 304 uint32_t timestamp_lsw; 305 uint32_t timestamp_msw; 306 uint32_t flags; 307 uint32_t num_frames; 308 } __packed; 309 310 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B 311 312 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { 313 uint32_t buf_addr_lsw; 314 uint32_t buf_addr_msw; 315 uint32_t mem_map_handle; 316 uint32_t buf_size; 317 uint32_t md_buf_addr_lsw; 318 uint32_t md_buf_addr_msw; 319 uint32_t md_mem_map_handle; 320 uint32_t md_buf_size; 321 } __packed; 322 323 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 324 325 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { 326 uint32_t status; 327 uint32_t buf_addr_lsw; 328 uint32_t buf_addr_msw; 329 uint32_t mem_map_handle; 330 uint32_t data_size; 331 uint32_t offset; 332 uint32_t timestamp_lsw; 333 uint32_t timestamp_msw; 334 uint32_t flags; 335 uint32_t num_frames; 336 uint32_t md_status; 337 uint32_t md_buf_addr_lsw; 338 uint32_t md_buf_addr_msw; 339 uint32_t md_mem_map_handle; 340 uint32_t md_size; 341 } __packed; 342 343 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007 344 345 struct param_id_rd_sh_mem_cfg { 346 uint32_t num_frames_per_buffer; 347 uint32_t metadata_control_flags; 348 349 } __packed; 350 351 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 352 353 struct data_cmd_wr_sh_mem_ep_eos_rendered { 354 uint32_t module_instance_id; 355 uint32_t render_status; 356 } __packed; 357 358 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 359 360 struct apm_cmd_header { 361 uint32_t payload_address_lsw; 362 uint32_t payload_address_msw; 363 uint32_t mem_map_handle; 364 uint32_t payload_size; 365 } __packed; 366 367 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) 368 369 struct apm_module_param_data { 370 uint32_t module_instance_id; 371 uint32_t param_id; 372 uint32_t param_size; 373 uint32_t error_code; 374 } __packed; 375 376 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) 377 378 struct apm_module_param_shared_data { 379 uint32_t param_id; 380 uint32_t param_size; 381 } __packed; 382 383 struct apm_prop_data { 384 uint32_t prop_id; 385 uint32_t prop_size; 386 } __packed; 387 388 /* Sub-Graph Properties */ 389 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 390 391 struct apm_param_id_sub_graph_cfg { 392 uint32_t num_sub_graphs; 393 } __packed; 394 395 struct apm_sub_graph_cfg { 396 uint32_t sub_graph_id; 397 uint32_t num_sub_graph_prop; 398 } __packed; 399 400 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E 401 402 struct apm_sg_prop_id_perf_mode { 403 uint32_t perf_mode; 404 } __packed; 405 406 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4 407 408 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F 409 410 struct apm_sg_prop_id_direction { 411 uint32_t direction; 412 } __packed; 413 414 #define APM_SG_PROP_ID_DIR_SIZE 4 415 416 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 417 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 418 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 419 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 420 421 struct apm_sg_prop_id_scenario_id { 422 uint32_t scenario_id; 423 } __packed; 424 425 #define APM_SG_PROP_ID_SID_SIZE 4 426 /* container api */ 427 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 428 429 struct apm_param_id_container_cfg { 430 uint32_t num_containers; 431 } __packed; 432 433 struct apm_container_cfg { 434 uint32_t container_id; 435 uint32_t num_prop; 436 } __packed; 437 438 struct apm_cont_capability { 439 uint32_t capability_id; 440 } __packed; 441 442 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 443 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 444 445 #define APM_PROP_ID_INVALID 0x0 446 #define APM_CONTAINER_CAP_ID_PP 0x1 447 #define APM_CONTAINER_CAP_ID_PP 0x1 448 449 struct apm_cont_prop_id_cap_list { 450 uint32_t num_capability_id; 451 } __packed; 452 453 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 454 455 struct apm_cont_prop_id_graph_pos { 456 uint32_t graph_pos; 457 } __packed; 458 459 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 460 461 struct apm_cont_prop_id_stack_size { 462 uint32_t stack_size; 463 } __packed; 464 465 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 466 467 struct apm_cont_prop_id_domain { 468 uint32_t proc_domain; 469 } __packed; 470 471 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 472 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1 473 474 #define PARAM_ID_I2S_INTF_CFG 0x08001019 475 struct param_id_i2s_intf_cfg { 476 uint32_t lpaif_type; 477 uint32_t intf_idx; 478 uint16_t sd_line_idx; 479 uint16_t ws_src; 480 } __packed; 481 482 #define I2S_INTF_TYPE_PRIMARY 0 483 #define I2S_INTF_TYPE_SECONDARY 1 484 #define I2S_INTF_TYPE_TERTIARY 2 485 #define I2S_INTF_TYPE_QUATERNARY 3 486 #define I2S_INTF_TYPE_QUINARY 4 487 #define I2S_SD0 1 488 #define I2S_SD1 2 489 #define I2S_SD2 3 490 #define I2S_SD3 4 491 492 #define PORT_ID_I2S_INPUT 2 493 #define PORT_ID_I2S_OUPUT 1 494 #define I2S_STACK_SIZE 2048 495 496 #define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154 497 498 struct param_id_display_port_intf_cfg { 499 uint32_t channel_allocation; 500 /* Multi-Steam Transport index */ 501 uint32_t mst_idx; 502 uint32_t dptx_idx; 503 } __packed; 504 505 #define PARAM_ID_HW_EP_MF_CFG 0x08001017 506 struct param_id_hw_ep_mf { 507 uint32_t sample_rate; 508 uint16_t bit_width; 509 uint16_t num_channels; 510 uint32_t data_format; 511 } __packed; 512 513 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 514 515 struct param_id_fram_size_factor { 516 uint32_t frame_size_factor; 517 } __packed; 518 519 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB 520 521 struct apm_cont_prop_id_parent_container { 522 uint32_t parent_container_id; 523 } __packed; 524 525 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 526 #define APM_CONT_HEAP_DEFAULT 0x1 527 #define APM_CONT_HEAP_LOW_POWER 0x2 528 529 struct apm_cont_prop_id_headp_id { 530 uint32_t heap_id; 531 } __packed; 532 533 struct apm_modules_list { 534 uint32_t sub_graph_id; 535 uint32_t container_id; 536 uint32_t num_modules; 537 } __packed; 538 539 struct apm_module_obj { 540 uint32_t module_id; 541 uint32_t instance_id; 542 } __packed; 543 544 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 545 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 546 struct apm_module_prop_id_port_info { 547 uint32_t max_ip_port; 548 uint32_t max_op_port; 549 } __packed; 550 551 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1 552 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 553 #define DATA_LOGGING_STACK_SIZE 2048 554 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 555 556 struct data_logging_config { 557 uint32_t log_code; 558 uint32_t log_tap_point_id; 559 uint32_t mode; 560 } __packed; 561 562 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016 563 struct param_id_sal_output_config { 564 uint32_t bits_per_sample; 565 } __packed; 566 567 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E 568 struct param_id_sal_limiter_enable { 569 uint32_t enable_lim; 570 } __packed; 571 572 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 573 #define PARAM_ID_EARLY_EOS_DELAY 0x0800114C 574 #define EARLY_EOS_DELAY_MS 150 575 576 struct param_id_mfc_media_format { 577 uint32_t sample_rate; 578 uint16_t bit_width; 579 uint16_t num_channels; 580 uint16_t channel_mapping[]; 581 } __packed; 582 583 struct param_id_gapless_early_eos_delay_t { 584 uint32_t early_eos_delay_ms; 585 } __packed; 586 587 struct media_format { 588 uint32_t data_format; 589 uint32_t fmt_id; 590 uint32_t payload_size; 591 } __packed; 592 593 struct payload_media_fmt_pcm { 594 uint32_t sample_rate; 595 uint16_t bit_width; 596 uint16_t alignment; 597 uint16_t bits_per_sample; 598 uint16_t q_factor; 599 uint16_t endianness; 600 uint16_t num_channels; 601 uint8_t channel_mapping[]; 602 } __packed; 603 604 #define PARAM_ID_MODULE_ENABLE 0x08001026 605 struct param_id_module_enable { 606 uint32_t enable; 607 } __packed; 608 609 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 610 611 struct param_id_codec_dma_intf_cfg { 612 /* 1 - RXTX 613 * 2 - WSA 614 * 3 - VA 615 * 4 - AXI 616 */ 617 uint32_t lpaif_type; 618 /* 619 * RX0 | TX0 = 1 620 * RX1 | TX1 = 2 621 * RX2 | TX2 = 3... so on 622 */ 623 uint32_t intf_index; 624 uint32_t active_channels_mask; 625 } __packed; 626 627 struct audio_hw_clk_cfg { 628 uint32_t clock_id; 629 uint32_t clock_freq; 630 uint32_t clock_attri; 631 uint32_t clock_root; 632 } __packed; 633 634 struct audio_hw_clk_rel_cfg { 635 uint32_t clock_id; 636 } __packed; 637 638 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 639 #define AR_HW_EP_POWER_MODE_0 0 /* default */ 640 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */ 641 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */ 642 643 struct param_id_hw_ep_power_mode_cfg { 644 uint32_t power_mode; 645 } __packed; 646 647 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 648 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0 649 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1 650 #define AR_PCM_MAX_NUM_CHANNEL 8 651 652 struct param_id_hw_ep_dma_data_align { 653 uint32_t dma_data_align; 654 } __packed; 655 656 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 657 #define VOL_CTRL_DEFAULT_GAIN 0x2000 658 659 struct param_id_vol_ctrl_master_gain { 660 uint16_t master_gain; 661 uint16_t reserved; 662 } __packed; 663 664 665 #define PARAM_ID_REMOVE_INITIAL_SILENCE 0x0800114B 666 #define PARAM_ID_REMOVE_TRAILING_SILENCE 0x0800115D 667 668 #define PARAM_ID_REAL_MODULE_ID 0x0800100B 669 670 struct param_id_placeholder_real_module_id { 671 uint32_t real_module_id; 672 } __packed; 673 674 /* Graph */ 675 struct audioreach_connection { 676 /* Connections */ 677 uint32_t src_mod_inst_id; 678 uint32_t src_mod_op_port_id; 679 uint32_t dst_mod_inst_id; 680 uint32_t dst_mod_ip_port_id; 681 struct list_head node; 682 }; 683 684 struct audioreach_graph_info { 685 int id; 686 uint32_t num_sub_graphs; 687 struct list_head sg_list; 688 /* DPCM connection from FE Graph to BE graph */ 689 uint32_t src_mod_inst_id; 690 uint32_t src_mod_op_port_id; 691 uint32_t dst_mod_inst_id; 692 uint32_t dst_mod_ip_port_id; 693 }; 694 695 struct audioreach_sub_graph { 696 uint32_t sub_graph_id; 697 uint32_t perf_mode; 698 uint32_t direction; 699 uint32_t scenario_id; 700 struct list_head node; 701 702 struct audioreach_graph_info *info; 703 uint32_t num_containers; 704 struct list_head container_list; 705 }; 706 707 struct audioreach_container { 708 uint32_t container_id; 709 uint32_t capability_id; 710 uint32_t graph_pos; 711 uint32_t stack_size; 712 uint32_t proc_domain; 713 struct list_head node; 714 715 uint32_t num_modules; 716 struct list_head modules_list; 717 struct audioreach_sub_graph *sub_graph; 718 }; 719 720 #define AR_MAX_MOD_LINKS 8 721 722 struct audioreach_module { 723 uint32_t module_id; 724 uint32_t instance_id; 725 726 uint32_t max_ip_port; 727 uint32_t max_op_port; 728 729 uint32_t num_connections; 730 /* Connections */ 731 uint32_t src_mod_inst_id; 732 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS]; 733 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS]; 734 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS]; 735 736 /* Format specifics */ 737 uint32_t ch_fmt; 738 uint32_t rate; 739 uint32_t bit_depth; 740 741 /* I2S module */ 742 uint32_t hw_interface_idx; 743 uint32_t sd_line_idx; 744 uint32_t ws_src; 745 uint32_t frame_size_factor; 746 uint32_t data_format; 747 uint32_t hw_interface_type; 748 749 /* PCM module specific */ 750 uint32_t interleave_type; 751 752 /* GAIN/Vol Control Module */ 753 uint16_t gain; 754 755 /* Logging */ 756 uint32_t log_code; 757 uint32_t log_tap_point_id; 758 uint32_t log_mode; 759 760 /* bookkeeping */ 761 struct list_head node; 762 struct audioreach_container *container; 763 struct snd_soc_dapm_widget *widget; 764 struct audioreach_module_priv_data *data; 765 }; 766 767 struct audioreach_module_config { 768 int direction; 769 u32 sample_rate; 770 u16 bit_width; 771 u16 bits_per_sample; 772 773 u16 data_format; 774 u16 num_channels; 775 u16 dp_idx; 776 u32 channel_allocation; 777 u32 sd_line_mask; 778 int fmt; 779 struct snd_codec codec; 780 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL]; 781 }; 782 783 /* Packet Allocation routines */ 784 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t 785 token); 786 void audioreach_set_default_channel_mapping(u8 *ch_map, int num_channels); 787 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, 788 uint32_t token, uint32_t src_port, 789 uint32_t dest_port); 790 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, 791 uint32_t src_port); 792 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, 793 uint32_t token, uint32_t src_port, 794 uint32_t dest_port); 795 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info 796 *info); 797 /* Topology specific */ 798 int audioreach_tplg_init(struct snd_soc_component *component); 799 800 /* Module specific */ 801 void audioreach_graph_free_buf(struct q6apm_graph *graph); 802 int audioreach_map_memory_regions(struct q6apm_graph *graph, 803 unsigned int dir, size_t period_sz, 804 unsigned int periods, 805 bool is_contiguous); 806 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result, 807 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait, 808 struct gpr_pkt *pkt, uint32_t rsp_opcode); 809 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt, 810 uint32_t rsp_opcode); 811 int audioreach_set_media_format(struct q6apm_graph *graph, 812 struct audioreach_module *module, 813 struct audioreach_module_config *cfg); 814 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); 815 int audioreach_gain_set_vol_ctrl(struct q6apm *apm, 816 struct audioreach_module *module, int vol); 817 int audioreach_send_u32_param(struct q6apm_graph *graph, struct audioreach_module *module, 818 uint32_t param_id, uint32_t param_val); 819 int audioreach_compr_set_param(struct q6apm_graph *graph, struct audioreach_module_config *mcfg); 820 821 #endif /* __AUDIOREACH_H__ */ 822