xref: /linux/drivers/clk/stm32/clk-stm32-core.c (revision 522ba450b56fff29f868b1552bdc2965f55de7ed)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 
17 #include "clk-stm32-core.h"
18 #include "reset-stm32.h"
19 
20 static DEFINE_SPINLOCK(rlock);
21 
stm32_rcc_clock_init(struct device * dev,const struct of_device_id * match,void __iomem * base)22 static int stm32_rcc_clock_init(struct device *dev,
23 				const struct of_device_id *match,
24 				void __iomem *base)
25 {
26 	const struct stm32_rcc_match_data *data = match->data;
27 	struct clk_hw_onecell_data *clk_data = data->hw_clks;
28 	struct clk_hw **hws;
29 	int n, max_binding;
30 
31 	max_binding =  data->maxbinding;
32 
33 	clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);
34 	if (!clk_data)
35 		return -ENOMEM;
36 
37 	clk_data->num = max_binding;
38 
39 	hws = clk_data->hws;
40 
41 	for (n = 0; n < max_binding; n++)
42 		hws[n] = ERR_PTR(-ENOENT);
43 
44 	for (n = 0; n < data->num_clocks; n++) {
45 		const struct clock_config *cfg_clock = &data->tab_clocks[n];
46 		struct clk_hw *hw = ERR_PTR(-ENOENT);
47 
48 		if (data->check_security &&
49 		    data->check_security(dev->of_node, base, cfg_clock))
50 			continue;
51 
52 		if (cfg_clock->func)
53 			hw = (*cfg_clock->func)(dev, data, base, &rlock,
54 						cfg_clock);
55 
56 		if (IS_ERR(hw)) {
57 			dev_err(dev, "Can't register clk %d: %ld\n", n,
58 				PTR_ERR(hw));
59 			return PTR_ERR(hw);
60 		}
61 
62 		if (cfg_clock->id != NO_ID)
63 			hws[cfg_clock->id] = hw;
64 	}
65 
66 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
67 }
68 
stm32_rcc_init(struct device * dev,const struct of_device_id * match_data,void __iomem * base)69 int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
70 		   void __iomem *base)
71 {
72 	const struct stm32_rcc_match_data *rcc_match_data;
73 	const struct of_device_id *match;
74 	int err;
75 
76 	match = of_match_node(match_data, dev_of_node(dev));
77 	if (!match) {
78 		dev_err(dev, "match data not found\n");
79 		return -ENODEV;
80 	}
81 
82 	rcc_match_data = match->data;
83 
84 	/* RCC Reset Configuration */
85 	err = stm32_rcc_reset_init(dev, rcc_match_data->reset_data, base);
86 	if (err) {
87 		pr_err("stm32 reset failed to initialize\n");
88 		return err;
89 	}
90 
91 	/* RCC Clock Configuration */
92 	err = stm32_rcc_clock_init(dev, match, base);
93 	if (err) {
94 		pr_err("stm32 clock failed to initialize\n");
95 		return err;
96 	}
97 
98 	return 0;
99 }
100 
stm32_mux_get_parent(void __iomem * base,struct clk_stm32_clock_data * data,u16 mux_id)101 static u8 stm32_mux_get_parent(void __iomem *base,
102 			       struct clk_stm32_clock_data *data,
103 			       u16 mux_id)
104 {
105 	const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
106 	u32 mask = BIT(mux->width) - 1;
107 	u32 val;
108 
109 	val = readl(base + mux->offset) >> mux->shift;
110 	val &= mask;
111 
112 	return val;
113 }
114 
stm32_mux_set_parent(void __iomem * base,struct clk_stm32_clock_data * data,u16 mux_id,u8 index)115 static int stm32_mux_set_parent(void __iomem *base,
116 				struct clk_stm32_clock_data *data,
117 				u16 mux_id, u8 index)
118 {
119 	const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
120 
121 	u32 mask = BIT(mux->width) - 1;
122 	u32 reg = readl(base + mux->offset);
123 	u32 val = index << mux->shift;
124 
125 	reg &= ~(mask << mux->shift);
126 	reg |= val;
127 
128 	writel(reg, base + mux->offset);
129 
130 	return 0;
131 }
132 
stm32_gate_endisable(void __iomem * base,struct clk_stm32_clock_data * data,u16 gate_id,int enable)133 static void stm32_gate_endisable(void __iomem *base,
134 				 struct clk_stm32_clock_data *data,
135 				 u16 gate_id, int enable)
136 {
137 	const struct stm32_gate_cfg *gate = &data->gates[gate_id];
138 	void __iomem *addr = base + gate->offset;
139 
140 	if (enable) {
141 		if (data->gate_cpt[gate_id]++ > 0)
142 			return;
143 
144 		if (gate->set_clr != 0)
145 			writel(BIT(gate->bit_idx), addr);
146 		else
147 			writel(readl(addr) | BIT(gate->bit_idx), addr);
148 	} else {
149 		if (--data->gate_cpt[gate_id] > 0)
150 			return;
151 
152 		if (gate->set_clr != 0)
153 			writel(BIT(gate->bit_idx), addr + gate->set_clr);
154 		else
155 			writel(readl(addr) & ~BIT(gate->bit_idx), addr);
156 	}
157 }
158 
stm32_gate_disable_unused(void __iomem * base,struct clk_stm32_clock_data * data,u16 gate_id)159 static void stm32_gate_disable_unused(void __iomem *base,
160 				      struct clk_stm32_clock_data *data,
161 				      u16 gate_id)
162 {
163 	const struct stm32_gate_cfg *gate = &data->gates[gate_id];
164 	void __iomem *addr = base + gate->offset;
165 
166 	if (data->gate_cpt[gate_id] > 0)
167 		return;
168 
169 	if (gate->set_clr != 0)
170 		writel(BIT(gate->bit_idx), addr + gate->set_clr);
171 	else
172 		writel(readl(addr) & ~BIT(gate->bit_idx), addr);
173 }
174 
stm32_gate_is_enabled(void __iomem * base,struct clk_stm32_clock_data * data,u16 gate_id)175 static int stm32_gate_is_enabled(void __iomem *base,
176 				 struct clk_stm32_clock_data *data,
177 				 u16 gate_id)
178 {
179 	const struct stm32_gate_cfg *gate = &data->gates[gate_id];
180 
181 	return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
182 }
183 
_get_table_div(const struct clk_div_table * table,unsigned int val)184 static unsigned int _get_table_div(const struct clk_div_table *table,
185 				   unsigned int val)
186 {
187 	const struct clk_div_table *clkt;
188 
189 	for (clkt = table; clkt->div; clkt++)
190 		if (clkt->val == val)
191 			return clkt->div;
192 	return 0;
193 }
194 
_get_div(const struct clk_div_table * table,unsigned int val,unsigned long flags,u8 width)195 static unsigned int _get_div(const struct clk_div_table *table,
196 			     unsigned int val, unsigned long flags, u8 width)
197 {
198 	if (flags & CLK_DIVIDER_ONE_BASED)
199 		return val;
200 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
201 		return 1 << val;
202 	if (table)
203 		return _get_table_div(table, val);
204 	return val + 1;
205 }
206 
stm32_divider_get_rate(void __iomem * base,struct clk_stm32_clock_data * data,u16 div_id,unsigned long parent_rate)207 static unsigned long stm32_divider_get_rate(void __iomem *base,
208 					    struct clk_stm32_clock_data *data,
209 					    u16 div_id,
210 					    unsigned long parent_rate)
211 {
212 	const struct stm32_div_cfg *divider = &data->dividers[div_id];
213 	unsigned int val;
214 	unsigned int div;
215 
216 	val =  readl(base + divider->offset) >> divider->shift;
217 	val &= clk_div_mask(divider->width);
218 	div = _get_div(divider->table, val, divider->flags, divider->width);
219 
220 	if (!div) {
221 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
222 		     "%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
223 		     div_id);
224 		return parent_rate;
225 	}
226 
227 	return DIV_ROUND_UP_ULL((u64)parent_rate, div);
228 }
229 
stm32_divider_set_rate(void __iomem * base,struct clk_stm32_clock_data * data,u16 div_id,unsigned long rate,unsigned long parent_rate)230 static int stm32_divider_set_rate(void __iomem *base,
231 				  struct clk_stm32_clock_data *data,
232 				  u16 div_id, unsigned long rate,
233 				  unsigned long parent_rate)
234 {
235 	const struct stm32_div_cfg *divider = &data->dividers[div_id];
236 	int value;
237 	u32 val;
238 
239 	value = divider_get_val(rate, parent_rate, divider->table,
240 				divider->width, divider->flags);
241 	if (value < 0)
242 		return value;
243 
244 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
245 		val = clk_div_mask(divider->width) << (divider->shift + 16);
246 	} else {
247 		val = readl(base + divider->offset);
248 		val &= ~(clk_div_mask(divider->width) << divider->shift);
249 	}
250 
251 	val |= (u32)value << divider->shift;
252 
253 	writel(val, base + divider->offset);
254 
255 	return 0;
256 }
257 
clk_stm32_mux_get_parent(struct clk_hw * hw)258 static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
259 {
260 	struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
261 
262 	return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);
263 }
264 
clk_stm32_mux_set_parent(struct clk_hw * hw,u8 index)265 static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)
266 {
267 	struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
268 	unsigned long flags = 0;
269 
270 	spin_lock_irqsave(mux->lock, flags);
271 
272 	stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);
273 
274 	spin_unlock_irqrestore(mux->lock, flags);
275 
276 	return 0;
277 }
278 
279 const struct clk_ops clk_stm32_mux_ops = {
280 	.determine_rate	= __clk_mux_determine_rate,
281 	.get_parent	= clk_stm32_mux_get_parent,
282 	.set_parent	= clk_stm32_mux_set_parent,
283 };
284 
clk_stm32_gate_endisable(struct clk_hw * hw,int enable)285 static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)
286 {
287 	struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
288 	unsigned long flags = 0;
289 
290 	spin_lock_irqsave(gate->lock, flags);
291 
292 	stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);
293 
294 	spin_unlock_irqrestore(gate->lock, flags);
295 }
296 
clk_stm32_gate_enable(struct clk_hw * hw)297 static int clk_stm32_gate_enable(struct clk_hw *hw)
298 {
299 	clk_stm32_gate_endisable(hw, 1);
300 
301 	return 0;
302 }
303 
clk_stm32_gate_disable(struct clk_hw * hw)304 static void clk_stm32_gate_disable(struct clk_hw *hw)
305 {
306 	clk_stm32_gate_endisable(hw, 0);
307 }
308 
clk_stm32_gate_is_enabled(struct clk_hw * hw)309 static int clk_stm32_gate_is_enabled(struct clk_hw *hw)
310 {
311 	struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
312 
313 	return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);
314 }
315 
clk_stm32_gate_disable_unused(struct clk_hw * hw)316 static void clk_stm32_gate_disable_unused(struct clk_hw *hw)
317 {
318 	struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
319 	unsigned long flags = 0;
320 
321 	spin_lock_irqsave(gate->lock, flags);
322 
323 	stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);
324 
325 	spin_unlock_irqrestore(gate->lock, flags);
326 }
327 
328 const struct clk_ops clk_stm32_gate_ops = {
329 	.enable		= clk_stm32_gate_enable,
330 	.disable	= clk_stm32_gate_disable,
331 	.is_enabled	= clk_stm32_gate_is_enabled,
332 	.disable_unused	= clk_stm32_gate_disable_unused,
333 };
334 
clk_stm32_divider_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)335 static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
336 				      unsigned long parent_rate)
337 {
338 	struct clk_stm32_div *div = to_clk_stm32_divider(hw);
339 	unsigned long flags = 0;
340 	int ret;
341 
342 	if (div->div_id == NO_STM32_DIV)
343 		return rate;
344 
345 	spin_lock_irqsave(div->lock, flags);
346 
347 	ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);
348 
349 	spin_unlock_irqrestore(div->lock, flags);
350 
351 	return ret;
352 }
353 
clk_stm32_divider_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)354 static int clk_stm32_divider_determine_rate(struct clk_hw *hw,
355 					    struct clk_rate_request *req)
356 {
357 	struct clk_stm32_div *div = to_clk_stm32_divider(hw);
358 	const struct stm32_div_cfg *divider;
359 
360 	if (div->div_id == NO_STM32_DIV)
361 		return 0;
362 
363 	divider = &div->clock_data->dividers[div->div_id];
364 
365 	/* if read only, just return current value */
366 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
367 		u32 val;
368 
369 		val =  readl(div->base + divider->offset) >> divider->shift;
370 		val &= clk_div_mask(divider->width);
371 
372 		req->rate = divider_ro_round_rate(hw, req->rate,
373 						  &req->best_parent_rate,
374 						  divider->table,
375 						  divider->width,
376 						  divider->flags, val);
377 
378 		return 0;
379 	}
380 
381 	req->rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw),
382 					      req->rate,
383 					      &req->best_parent_rate,
384 					      divider->table,
385 					      divider->width, divider->flags);
386 
387 	return 0;
388 }
389 
clk_stm32_divider_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)390 static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
391 						   unsigned long parent_rate)
392 {
393 	struct clk_stm32_div *div = to_clk_stm32_divider(hw);
394 
395 	if (div->div_id == NO_STM32_DIV)
396 		return parent_rate;
397 
398 	return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);
399 }
400 
401 const struct clk_ops clk_stm32_divider_ops = {
402 	.recalc_rate	= clk_stm32_divider_recalc_rate,
403 	.determine_rate = clk_stm32_divider_determine_rate,
404 	.set_rate	= clk_stm32_divider_set_rate,
405 };
406 
clk_stm32_composite_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)407 static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
408 					unsigned long parent_rate)
409 {
410 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
411 	unsigned long flags = 0;
412 	int ret;
413 
414 	if (composite->div_id == NO_STM32_DIV)
415 		return rate;
416 
417 	spin_lock_irqsave(composite->lock, flags);
418 
419 	ret = stm32_divider_set_rate(composite->base, composite->clock_data,
420 				     composite->div_id, rate, parent_rate);
421 
422 	spin_unlock_irqrestore(composite->lock, flags);
423 
424 	return ret;
425 }
426 
clk_stm32_composite_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)427 static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
428 						     unsigned long parent_rate)
429 {
430 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
431 
432 	if (composite->div_id == NO_STM32_DIV)
433 		return parent_rate;
434 
435 	return stm32_divider_get_rate(composite->base, composite->clock_data,
436 				      composite->div_id, parent_rate);
437 }
438 
clk_stm32_composite_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)439 static int clk_stm32_composite_determine_rate(struct clk_hw *hw,
440 					      struct clk_rate_request *req)
441 {
442 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
443 	const struct stm32_div_cfg *divider;
444 	long rate;
445 
446 	if (composite->div_id == NO_STM32_DIV)
447 		return 0;
448 
449 	divider = &composite->clock_data->dividers[composite->div_id];
450 
451 	/* if read only, just return current value */
452 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
453 		u32 val;
454 
455 		val =  readl(composite->base + divider->offset) >> divider->shift;
456 		val &= clk_div_mask(divider->width);
457 
458 		rate = divider_ro_round_rate(hw, req->rate, &req->best_parent_rate,
459 					     divider->table, divider->width, divider->flags,
460 					     val);
461 		if (rate < 0)
462 			return rate;
463 
464 		req->rate = rate;
465 		return 0;
466 	}
467 
468 	rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw),
469 					 req->rate, &req->best_parent_rate,
470 					 divider->table, divider->width, divider->flags);
471 	if (rate < 0)
472 		return rate;
473 
474 	req->rate = rate;
475 	return 0;
476 }
477 
clk_stm32_composite_get_parent(struct clk_hw * hw)478 static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
479 {
480 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
481 
482 	return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
483 }
484 
clk_stm32_composite_set_parent(struct clk_hw * hw,u8 index)485 static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
486 {
487 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
488 	unsigned long flags = 0;
489 
490 	spin_lock_irqsave(composite->lock, flags);
491 
492 	stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
493 
494 	spin_unlock_irqrestore(composite->lock, flags);
495 
496 	if (composite->clock_data->is_multi_mux) {
497 		struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);
498 
499 		if (other_mux_hw) {
500 			struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);
501 
502 			clk_hw_reparent(other_mux_hw, hwp);
503 		}
504 	}
505 
506 	return 0;
507 }
508 
clk_stm32_composite_is_enabled(struct clk_hw * hw)509 static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
510 {
511 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
512 
513 	if (composite->gate_id == NO_STM32_GATE)
514 		return (__clk_get_enable_count(hw->clk) > 0);
515 
516 	return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
517 }
518 
519 #define MUX_SAFE_POSITION 0
520 
clk_stm32_has_safe_mux(struct clk_hw * hw)521 static int clk_stm32_has_safe_mux(struct clk_hw *hw)
522 {
523 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
524 	const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];
525 
526 	return !!(mux->flags & MUX_SAFE);
527 }
528 
clk_stm32_set_safe_position_mux(struct clk_hw * hw)529 static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)
530 {
531 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
532 
533 	if (!clk_stm32_composite_is_enabled(hw)) {
534 		unsigned long flags = 0;
535 
536 		if (composite->clock_data->is_multi_mux) {
537 			struct clk_hw *other_mux_hw = NULL;
538 
539 			other_mux_hw = composite->clock_data->is_multi_mux(hw);
540 
541 			if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))
542 				return;
543 		}
544 
545 		spin_lock_irqsave(composite->lock, flags);
546 
547 		stm32_mux_set_parent(composite->base, composite->clock_data,
548 				     composite->mux_id, MUX_SAFE_POSITION);
549 
550 		spin_unlock_irqrestore(composite->lock, flags);
551 	}
552 }
553 
clk_stm32_safe_restore_position_mux(struct clk_hw * hw)554 static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)
555 {
556 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
557 	int sel = clk_hw_get_parent_index(hw);
558 	unsigned long flags = 0;
559 
560 	spin_lock_irqsave(composite->lock, flags);
561 
562 	stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);
563 
564 	spin_unlock_irqrestore(composite->lock, flags);
565 }
566 
clk_stm32_composite_gate_endisable(struct clk_hw * hw,int enable)567 static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
568 {
569 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
570 	unsigned long flags = 0;
571 
572 	spin_lock_irqsave(composite->lock, flags);
573 
574 	stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
575 
576 	spin_unlock_irqrestore(composite->lock, flags);
577 }
578 
clk_stm32_composite_gate_enable(struct clk_hw * hw)579 static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
580 {
581 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
582 
583 	if (composite->gate_id == NO_STM32_GATE)
584 		return 0;
585 
586 	clk_stm32_composite_gate_endisable(hw, 1);
587 
588 	if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
589 		clk_stm32_safe_restore_position_mux(hw);
590 
591 	return 0;
592 }
593 
clk_stm32_composite_gate_disable(struct clk_hw * hw)594 static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
595 {
596 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
597 
598 	if (composite->gate_id == NO_STM32_GATE)
599 		return;
600 
601 	clk_stm32_composite_gate_endisable(hw, 0);
602 
603 	if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
604 		clk_stm32_set_safe_position_mux(hw);
605 }
606 
clk_stm32_composite_disable_unused(struct clk_hw * hw)607 static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
608 {
609 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
610 	unsigned long flags = 0;
611 
612 	if (composite->gate_id == NO_STM32_GATE)
613 		return;
614 
615 	spin_lock_irqsave(composite->lock, flags);
616 
617 	stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
618 
619 	spin_unlock_irqrestore(composite->lock, flags);
620 }
621 
622 const struct clk_ops clk_stm32_composite_ops = {
623 	.set_rate	= clk_stm32_composite_set_rate,
624 	.recalc_rate	= clk_stm32_composite_recalc_rate,
625 	.determine_rate	= clk_stm32_composite_determine_rate,
626 	.get_parent	= clk_stm32_composite_get_parent,
627 	.set_parent	= clk_stm32_composite_set_parent,
628 	.enable		= clk_stm32_composite_gate_enable,
629 	.disable	= clk_stm32_composite_gate_disable,
630 	.is_enabled	= clk_stm32_composite_is_enabled,
631 	.disable_unused	= clk_stm32_composite_disable_unused,
632 };
633 
clk_stm32_mux_register(struct device * dev,const struct stm32_rcc_match_data * data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)634 struct clk_hw *clk_stm32_mux_register(struct device *dev,
635 				      const struct stm32_rcc_match_data *data,
636 				      void __iomem *base,
637 				      spinlock_t *lock,
638 				      const struct clock_config *cfg)
639 {
640 	struct clk_stm32_mux *mux = cfg->clock_cfg;
641 	struct clk_hw *hw = &mux->hw;
642 	int err;
643 
644 	mux->base = base;
645 	mux->lock = lock;
646 	mux->clock_data = data->clock_data;
647 
648 	err = devm_clk_hw_register(dev, hw);
649 	if (err)
650 		return ERR_PTR(err);
651 
652 	return hw;
653 }
654 
clk_stm32_gate_register(struct device * dev,const struct stm32_rcc_match_data * data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)655 struct clk_hw *clk_stm32_gate_register(struct device *dev,
656 				       const struct stm32_rcc_match_data *data,
657 				       void __iomem *base,
658 				       spinlock_t *lock,
659 				       const struct clock_config *cfg)
660 {
661 	struct clk_stm32_gate *gate = cfg->clock_cfg;
662 	struct clk_hw *hw = &gate->hw;
663 	int err;
664 
665 	gate->base = base;
666 	gate->lock = lock;
667 	gate->clock_data = data->clock_data;
668 
669 	err = devm_clk_hw_register(dev, hw);
670 	if (err)
671 		return ERR_PTR(err);
672 
673 	return hw;
674 }
675 
clk_stm32_div_register(struct device * dev,const struct stm32_rcc_match_data * data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)676 struct clk_hw *clk_stm32_div_register(struct device *dev,
677 				      const struct stm32_rcc_match_data *data,
678 				      void __iomem *base,
679 				      spinlock_t *lock,
680 				      const struct clock_config *cfg)
681 {
682 	struct clk_stm32_div *div = cfg->clock_cfg;
683 	struct clk_hw *hw = &div->hw;
684 	int err;
685 
686 	div->base = base;
687 	div->lock = lock;
688 	div->clock_data = data->clock_data;
689 
690 	err = devm_clk_hw_register(dev, hw);
691 	if (err)
692 		return ERR_PTR(err);
693 
694 	return hw;
695 }
696 
clk_stm32_composite_register(struct device * dev,const struct stm32_rcc_match_data * data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)697 struct clk_hw *clk_stm32_composite_register(struct device *dev,
698 					    const struct stm32_rcc_match_data *data,
699 					    void __iomem *base,
700 					    spinlock_t *lock,
701 					    const struct clock_config *cfg)
702 {
703 	struct clk_stm32_composite *composite = cfg->clock_cfg;
704 	struct clk_hw *hw = &composite->hw;
705 	int err;
706 
707 	composite->base = base;
708 	composite->lock = lock;
709 	composite->clock_data = data->clock_data;
710 
711 	err = devm_clk_hw_register(dev, hw);
712 	if (err)
713 		return ERR_PTR(err);
714 
715 	return hw;
716 }
717