1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2004
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 /*
37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/bus.h>
46
47 #include <net/if.h>
48 #include <net/if_arp.h>
49 #include <net/if_media.h>
50
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include "miidevs.h"
54
55 #include <dev/mii/ciphyreg.h>
56
57 #include "miibus_if.h"
58
59 #include <machine/bus.h>
60
61 static int ciphy_probe(device_t);
62 static int ciphy_attach(device_t);
63
64 static device_method_t ciphy_methods[] = {
65 /* device interface */
66 DEVMETHOD(device_probe, ciphy_probe),
67 DEVMETHOD(device_attach, ciphy_attach),
68 DEVMETHOD(device_detach, mii_phy_detach),
69 DEVMETHOD(device_shutdown, bus_generic_shutdown),
70 DEVMETHOD_END
71 };
72
73 static driver_t ciphy_driver = {
74 "ciphy",
75 ciphy_methods,
76 sizeof(struct mii_softc)
77 };
78
79 DRIVER_MODULE(ciphy, miibus, ciphy_driver, 0, 0);
80
81 static int ciphy_service(struct mii_softc *, struct mii_data *, int);
82 static void ciphy_status(struct mii_softc *);
83 static void ciphy_reset(struct mii_softc *);
84 static void ciphy_fixup(struct mii_softc *);
85
86 static const struct mii_phydesc ciphys[] = {
87 MII_PHY_DESC(xxCICADA, CS8201),
88 MII_PHY_DESC(xxCICADA, CS8201A),
89 MII_PHY_DESC(xxCICADA, CS8201B),
90 MII_PHY_DESC(xxCICADA, CS8204),
91 MII_PHY_DESC(xxCICADA, VSC8211),
92 MII_PHY_DESC(xxCICADA, VSC8221),
93 MII_PHY_DESC(xxCICADA, CS8244),
94 MII_PHY_DESC(xxVITESSE, VSC8601),
95 MII_PHY_DESC(xxVITESSE, VSC8641),
96 MII_PHY_END
97 };
98
99 static const struct mii_phy_funcs ciphy_funcs = {
100 ciphy_service,
101 ciphy_status,
102 ciphy_reset
103 };
104
105 static int
ciphy_probe(device_t dev)106 ciphy_probe(device_t dev)
107 {
108
109 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
110 }
111
112 static int
ciphy_attach(device_t dev)113 ciphy_attach(device_t dev)
114 {
115
116 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
117 &ciphy_funcs, 1);
118 return (0);
119 }
120
121 static int
ciphy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)122 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
123 {
124 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
125 int reg, speed, gig;
126
127 switch (cmd) {
128 case MII_POLLSTAT:
129 break;
130
131 case MII_MEDIACHG:
132 ciphy_fixup(sc); /* XXX hardware bug work-around */
133
134 switch (IFM_SUBTYPE(ife->ifm_media)) {
135 case IFM_AUTO:
136 #ifdef foo
137 /*
138 * If we're already in auto mode, just return.
139 */
140 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
141 return (0);
142 #endif
143 (void)mii_phy_auto(sc);
144 break;
145 case IFM_1000_T:
146 speed = CIPHY_S1000;
147 goto setit;
148 case IFM_100_TX:
149 speed = CIPHY_S100;
150 goto setit;
151 case IFM_10_T:
152 speed = CIPHY_S10;
153 setit:
154 if ((ife->ifm_media & IFM_FDX) != 0) {
155 speed |= CIPHY_BMCR_FDX;
156 gig = CIPHY_1000CTL_AFD;
157 } else
158 gig = CIPHY_1000CTL_AHD;
159
160 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
161 gig |= CIPHY_1000CTL_MSE;
162 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
163 gig |= CIPHY_1000CTL_MSC;
164 speed |=
165 CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG;
166 } else
167 gig = 0;
168 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
169 PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
170 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
171 break;
172 case IFM_NONE:
173 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
174 break;
175 default:
176 return (EINVAL);
177 }
178 break;
179
180 case MII_TICK:
181 /*
182 * Only used for autonegotiation.
183 */
184 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
185 break;
186
187 /*
188 * Check to see if we have link. If we do, we don't
189 * need to restart the autonegotiation process. Read
190 * the BMSR twice in case it's latched.
191 */
192 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
193 if (reg & BMSR_LINK)
194 break;
195
196 /* Announce link loss right after it happens. */
197 if (++sc->mii_ticks == 0)
198 break;
199 /*
200 * Only retry autonegotiation every mii_anegticks seconds.
201 */
202 if (sc->mii_ticks <= sc->mii_anegticks)
203 break;
204
205 sc->mii_ticks = 0;
206 mii_phy_auto(sc);
207 break;
208 }
209
210 /* Update the media status. */
211 PHY_STATUS(sc);
212
213 /*
214 * Callback if something changed. Note that we need to poke
215 * apply fixups for certain PHY revs.
216 */
217 if (sc->mii_media_active != mii->mii_media_active ||
218 sc->mii_media_status != mii->mii_media_status ||
219 cmd == MII_MEDIACHG) {
220 ciphy_fixup(sc);
221 }
222 mii_phy_update(sc, cmd);
223 return (0);
224 }
225
226 static void
ciphy_status(struct mii_softc * sc)227 ciphy_status(struct mii_softc *sc)
228 {
229 struct mii_data *mii = sc->mii_pdata;
230 int bmsr, bmcr;
231
232 mii->mii_media_status = IFM_AVALID;
233 mii->mii_media_active = IFM_ETHER;
234
235 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
236
237 if (bmsr & BMSR_LINK)
238 mii->mii_media_status |= IFM_ACTIVE;
239
240 bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
241
242 if (bmcr & CIPHY_BMCR_LOOP)
243 mii->mii_media_active |= IFM_LOOP;
244
245 if (bmcr & CIPHY_BMCR_AUTOEN) {
246 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
247 /* Erg, still trying, I guess... */
248 mii->mii_media_active |= IFM_NONE;
249 return;
250 }
251 }
252
253 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
254 switch (bmsr & CIPHY_AUXCSR_SPEED) {
255 case CIPHY_SPEED10:
256 mii->mii_media_active |= IFM_10_T;
257 break;
258 case CIPHY_SPEED100:
259 mii->mii_media_active |= IFM_100_TX;
260 break;
261 case CIPHY_SPEED1000:
262 mii->mii_media_active |= IFM_1000_T;
263 break;
264 default:
265 device_printf(sc->mii_dev, "unknown PHY speed %x\n",
266 bmsr & CIPHY_AUXCSR_SPEED);
267 break;
268 }
269
270 if (bmsr & CIPHY_AUXCSR_FDX)
271 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
272 else
273 mii->mii_media_active |= IFM_HDX;
274
275 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
276 (PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0)
277 mii->mii_media_active |= IFM_ETH_MASTER;
278 }
279
280 static void
ciphy_reset(struct mii_softc * sc)281 ciphy_reset(struct mii_softc *sc)
282 {
283
284 mii_phy_reset(sc);
285 DELAY(1000);
286 }
287
288 #define PHY_SETBIT(x, y, z) \
289 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
290 #define PHY_CLRBIT(x, y, z) \
291 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
292
293 static void
ciphy_fixup(struct mii_softc * sc)294 ciphy_fixup(struct mii_softc *sc)
295 {
296 uint16_t model;
297 uint16_t status, speed;
298 uint16_t val;
299
300 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
301 status = PHY_READ(sc, CIPHY_MII_AUXCSR);
302 speed = status & CIPHY_AUXCSR_SPEED;
303
304 if (mii_phy_mac_match(sc, "nfe")) {
305 /* need to set for 2.5V RGMII for NVIDIA adapters */
306 val = PHY_READ(sc, CIPHY_MII_ECTL1);
307 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
308 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
309 PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
310 /* From Linux. */
311 val = PHY_READ(sc, CIPHY_MII_AUXCSR);
312 val |= CIPHY_AUXCSR_MDPPS;
313 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
314 val = PHY_READ(sc, CIPHY_MII_10BTCSR);
315 val |= CIPHY_10BTCSR_ECHO;
316 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
317 }
318
319 switch (model) {
320 case MII_MODEL_xxCICADA_CS8204:
321 case MII_MODEL_xxCICADA_CS8201:
322
323 /* Turn off "aux mode" (whatever that means) */
324 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
325
326 /*
327 * Work around speed polling bug in VT3119/VT3216
328 * when using MII in full duplex mode.
329 */
330 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
331 (status & CIPHY_AUXCSR_FDX)) {
332 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
333 } else {
334 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
335 }
336
337 /* Enable link/activity LED blink. */
338 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
339
340 break;
341
342 case MII_MODEL_xxCICADA_CS8201A:
343 case MII_MODEL_xxCICADA_CS8201B:
344
345 /*
346 * Work around speed polling bug in VT3119/VT3216
347 * when using MII in full duplex mode.
348 */
349 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
350 (status & CIPHY_AUXCSR_FDX)) {
351 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
352 } else {
353 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
354 }
355
356 break;
357 case MII_MODEL_xxCICADA_VSC8211:
358 case MII_MODEL_xxCICADA_VSC8221:
359 case MII_MODEL_xxCICADA_CS8244:
360 case MII_MODEL_xxVITESSE_VSC8601:
361 case MII_MODEL_xxVITESSE_VSC8641:
362 break;
363 default:
364 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
365 model);
366 break;
367 }
368 }
369