1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
6 * Copyright (c) 2017 The FreeBSD Foundation
7 * All rights reserved.
8 *
9 * Portions of this software were developed by Landon Fuller
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
20 * redistribution must be conditioned upon including a substantially
21 * similar Disclaimer requirement for further binary redistribution.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 */
36
37 #include <sys/cdefs.h>
38 /*
39 * Broadcom ChipCommon driver.
40 *
41 * With the exception of some very early chipsets, the ChipCommon core
42 * has been included in all HND SoCs and chipsets based on the siba(4)
43 * and bcma(4) interconnects, providing a common interface to chipset
44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts,
45 * GPIO, flash, etc.
46 */
47
48 #include <sys/param.h>
49 #include <sys/kernel.h>
50 #include <sys/lock.h>
51 #include <sys/bus.h>
52 #include <sys/rman.h>
53 #include <sys/malloc.h>
54 #include <sys/module.h>
55 #include <sys/mutex.h>
56 #include <sys/systm.h>
57
58 #include <machine/bus.h>
59 #include <machine/resource.h>
60
61 #include <dev/bhnd/bhnd.h>
62 #include <dev/bhnd/bhndvar.h>
63
64 #include "chipcreg.h"
65 #include "chipcvar.h"
66
67 #include "chipc_private.h"
68
69 static struct bhnd_device_quirk chipc_quirks[];
70
71 /* Supported device identifiers */
72 static const struct bhnd_device chipc_devices[] = {
73 BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
74 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
75 BHND_DEVICE_END
76 };
77
78 /* Device quirks table */
79 static struct bhnd_device_quirk chipc_quirks[] = {
80 /* HND OTP controller revisions */
81 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
82 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
83 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
84
85 /* IPX OTP controller revisions */
86 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
87 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
88
89 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
90 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
91 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
92
93 /* 4706 variant quirks */
94 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
95 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH),
96
97 /* 4331 quirks*/
98 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
99 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
100 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
101 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
102
103 /* 4360 quirks */
104 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
105 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
106 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
107 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
108
109 BHND_DEVICE_QUIRK_END
110 };
111
112 static int chipc_add_children(struct chipc_softc *sc);
113
114 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
115 struct chipc_caps *caps);
116 static int chipc_read_caps(struct chipc_softc *sc,
117 struct chipc_caps *caps);
118
119 static bool chipc_should_enable_muxed_sprom(
120 struct chipc_softc *sc);
121 static int chipc_enable_otp_power(struct chipc_softc *sc);
122 static void chipc_disable_otp_power(struct chipc_softc *sc);
123 static int chipc_enable_sprom_pins(struct chipc_softc *sc);
124 static void chipc_disable_sprom_pins(struct chipc_softc *sc);
125
126 static int chipc_try_activate_resource(device_t dev,
127 device_t child, struct resource *r,
128 bool req_direct);
129
130 static int chipc_init_rman(struct chipc_softc *sc);
131 static void chipc_free_rman(struct chipc_softc *sc);
132 static struct rman *chipc_get_rman(device_t dev, int type, u_int flags);
133
134 /* quirk and capability flag convenience macros */
135 #define CHIPC_QUIRK(_sc, _name) \
136 ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
137
138 #define CHIPC_CAP(_sc, _name) \
139 ((_sc)->caps._name)
140
141 #define CHIPC_ASSERT_QUIRK(_sc, name) \
142 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
143
144 #define CHIPC_ASSERT_CAP(_sc, name) \
145 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
146
147 static int
chipc_probe(device_t dev)148 chipc_probe(device_t dev)
149 {
150 const struct bhnd_device *id;
151
152 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
153 if (id == NULL)
154 return (ENXIO);
155
156 bhnd_set_default_core_desc(dev);
157 return (BUS_PROBE_DEFAULT);
158 }
159
160 static int
chipc_attach(device_t dev)161 chipc_attach(device_t dev)
162 {
163 struct chipc_softc *sc;
164 int error;
165
166 sc = device_get_softc(dev);
167 sc->dev = dev;
168 sc->quirks = bhnd_device_quirks(dev, chipc_devices,
169 sizeof(chipc_devices[0]));
170 sc->sprom_refcnt = 0;
171
172 CHIPC_LOCK_INIT(sc);
173 STAILQ_INIT(&sc->mem_regions);
174
175 /* Set up resource management */
176 if ((error = chipc_init_rman(sc))) {
177 device_printf(sc->dev,
178 "failed to initialize chipc resource state: %d\n", error);
179 goto failed;
180 }
181
182 /* Allocate the region containing the chipc register block */
183 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
184 error = ENXIO;
185 goto failed;
186 }
187
188 error = chipc_retain_region(sc, sc->core_region,
189 RF_ALLOCATED|RF_ACTIVE);
190 if (error) {
191 sc->core_region = NULL;
192 goto failed;
193 }
194
195 /* Save a direct reference to our chipc registers */
196 sc->core = sc->core_region->cr_res;
197
198 /* Fetch and parse capability register(s) */
199 if ((error = chipc_read_caps(sc, &sc->caps)))
200 goto failed;
201
202 if (bootverbose)
203 chipc_print_caps(sc->dev, &sc->caps);
204
205 /* Attach all supported child devices */
206 if ((error = chipc_add_children(sc)))
207 goto failed;
208
209 /*
210 * Register ourselves with the bus; we're fully initialized and can
211 * response to ChipCommin API requests.
212 *
213 * Since our children may need access to ChipCommon, this must be done
214 * before attaching our children below (via bus_attach_children).
215 */
216 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC)))
217 goto failed;
218
219 bus_attach_children(dev);
220
221 return (0);
222
223 failed:
224 device_delete_children(sc->dev);
225
226 if (sc->core_region != NULL) {
227 chipc_release_region(sc, sc->core_region,
228 RF_ALLOCATED|RF_ACTIVE);
229 }
230
231 chipc_free_rman(sc);
232 CHIPC_LOCK_DESTROY(sc);
233 return (error);
234 }
235
236 static int
chipc_detach(device_t dev)237 chipc_detach(device_t dev)
238 {
239 struct chipc_softc *sc;
240 int error;
241
242 sc = device_get_softc(dev);
243
244 if ((error = bus_generic_detach(dev)))
245 return (error);
246
247 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
248 return (error);
249
250 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
251 chipc_free_rman(sc);
252
253 CHIPC_LOCK_DESTROY(sc);
254
255 return (0);
256 }
257
258 static int
chipc_add_children(struct chipc_softc * sc)259 chipc_add_children(struct chipc_softc *sc)
260 {
261 device_t child;
262 const char *flash_bus;
263 int error;
264
265 /* SPROM/OTP */
266 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
267 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
268 {
269 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", DEVICE_UNIT_ANY);
270 if (child == NULL) {
271 device_printf(sc->dev, "failed to add nvram device\n");
272 return (ENXIO);
273 }
274
275 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
276 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP,
277 CHIPC_SPROM_OTP_SIZE, 0, 0);
278 if (error) {
279 device_printf(sc->dev, "failed to set OTP memory "
280 "resource: %d\n", error);
281 return (error);
282 }
283 }
284
285 /*
286 * PMU/PWR_CTRL
287 *
288 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is
289 * attached directly to the bhnd(4) bus -- not chipc.
290 */
291 if (sc->caps.pmu && !sc->caps.aob) {
292 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", DEVICE_UNIT_ANY);
293 if (child == NULL) {
294 device_printf(sc->dev, "failed to add pmu\n");
295 return (ENXIO);
296 }
297 } else if (sc->caps.pwr_ctrl) {
298 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", DEVICE_UNIT_ANY);
299 if (child == NULL) {
300 device_printf(sc->dev, "failed to add pwrctl\n");
301 return (ENXIO);
302 }
303 }
304
305 /* GPIO */
306 child = BUS_ADD_CHILD(sc->dev, 0, "gpio", DEVICE_UNIT_ANY);
307 if (child == NULL) {
308 device_printf(sc->dev, "failed to add gpio\n");
309 return (ENXIO);
310 }
311
312 error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0);
313 if (error) {
314 device_printf(sc->dev, "failed to set gpio memory resource: "
315 "%d\n", error);
316 return (error);
317 }
318
319 /* All remaining devices are SoC-only */
320 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
321 return (0);
322
323 /* UARTs */
324 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
325 int irq_rid, mem_rid;
326
327 irq_rid = 0;
328 mem_rid = 0;
329
330 child = BUS_ADD_CHILD(sc->dev, 0, "uart", DEVICE_UNIT_ANY);
331 if (child == NULL) {
332 device_printf(sc->dev, "failed to add uart%u\n", i);
333 return (ENXIO);
334 }
335
336 /* Shared IRQ */
337 error = chipc_set_irq_resource(sc, child, irq_rid, 0);
338 if (error) {
339 device_printf(sc->dev, "failed to set uart%u irq %u\n",
340 i, 0);
341 return (error);
342 }
343
344 /* UART registers are mapped sequentially */
345 error = chipc_set_mem_resource(sc, child, mem_rid,
346 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
347 if (error) {
348 device_printf(sc->dev, "failed to set uart%u memory "
349 "resource: %d\n", i, error);
350 return (error);
351 }
352 }
353
354 /* Flash */
355 flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
356 if (flash_bus != NULL) {
357 int rid;
358
359 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, DEVICE_UNIT_ANY);
360 if (child == NULL) {
361 device_printf(sc->dev, "failed to add %s device\n",
362 flash_bus);
363 return (ENXIO);
364 }
365
366 /* flash memory mapping */
367 rid = 0;
368 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1,
369 1);
370 if (error) {
371 device_printf(sc->dev, "failed to set flash memory "
372 "resource %d: %d\n", rid, error);
373 return (error);
374 }
375
376 /* flashctrl registers */
377 rid++;
378 error = chipc_set_mem_resource(sc, child, rid,
379 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
380 if (error) {
381 device_printf(sc->dev, "failed to set flash memory "
382 "resource %d: %d\n", rid, error);
383 return (error);
384 }
385 }
386
387 return (0);
388 }
389
390 /**
391 * Determine the NVRAM data source for this device.
392 *
393 * The SPROM, OTP, and flash capability flags must be fully populated in
394 * @p caps.
395 *
396 * @param sc chipc driver state.
397 * @param caps capability flags to be used to derive NVRAM configuration.
398 */
399 static bhnd_nvram_src
chipc_find_nvram_src(struct chipc_softc * sc,struct chipc_caps * caps)400 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
401 {
402 uint32_t otp_st, srom_ctrl;
403
404 /*
405 * We check for hardware presence in order of precedence. For example,
406 * SPROM is always used in preference to internal OTP if found.
407 */
408 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
409 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
410 if (srom_ctrl & CHIPC_SRC_PRESENT)
411 return (BHND_NVRAM_SRC_SPROM);
412 }
413
414 /* Check for programmed OTP H/W subregion (contains SROM data) */
415 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
416 /* TODO: need access to HND-OTP device */
417 if (!CHIPC_QUIRK(sc, OTP_HND)) {
418 device_printf(sc->dev,
419 "NVRAM unavailable: unsupported OTP controller.\n");
420 return (BHND_NVRAM_SRC_UNKNOWN);
421 }
422
423 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
424 if (otp_st & CHIPC_OTPS_GUP_HW)
425 return (BHND_NVRAM_SRC_OTP);
426 }
427
428 /* Check for flash */
429 if (caps->flash_type != CHIPC_FLASH_NONE)
430 return (BHND_NVRAM_SRC_FLASH);
431
432 /* No NVRAM hardware capability declared */
433 return (BHND_NVRAM_SRC_UNKNOWN);
434 }
435
436 /* Read and parse chipc capabilities */
437 static int
chipc_read_caps(struct chipc_softc * sc,struct chipc_caps * caps)438 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
439 {
440 uint32_t cap_reg;
441 uint32_t cap_ext_reg;
442 uint32_t regval;
443
444 /* Fetch cap registers */
445 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
446 cap_ext_reg = 0;
447 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
448 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
449
450 /* Extract values */
451 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
452 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
453 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
454 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
455
456 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
457 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
458 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
459
460 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
461 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
462 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
463 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
464 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
465 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
466 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
467
468 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
469 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
470 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
471
472 /* Fetch OTP size for later IPX controller revisions */
473 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
474 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
475 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
476 }
477
478 /* Determine flash type and parameters */
479 caps->cfi_width = 0;
480 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
481 case CHIPC_CAP_SFLASH_ST:
482 caps->flash_type = CHIPC_SFLASH_ST;
483 break;
484 case CHIPC_CAP_SFLASH_AT:
485 caps->flash_type = CHIPC_SFLASH_AT;
486 break;
487 case CHIPC_CAP_NFLASH:
488 /* unimplemented */
489 caps->flash_type = CHIPC_NFLASH;
490 break;
491 case CHIPC_CAP_PFLASH:
492 caps->flash_type = CHIPC_PFLASH_CFI;
493
494 /* determine cfi width */
495 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
496 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
497 caps->cfi_width = 2;
498 else
499 caps->cfi_width = 1;
500
501 break;
502 case CHIPC_CAP_FLASH_NONE:
503 caps->flash_type = CHIPC_FLASH_NONE;
504 break;
505
506 }
507
508 /* Handle 4706_NFLASH fallback */
509 if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
510 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
511 {
512 caps->flash_type = CHIPC_NFLASH_4706;
513 }
514
515 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash
516 * capability flags have been populated. */
517 caps->nvram_src = chipc_find_nvram_src(sc, caps);
518
519 /* Determine the SPROM offset within OTP (if any). SPROM-formatted
520 * data is placed within the OTP general use region. */
521 caps->sprom_offset = 0;
522 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
523 CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
524
525 /* Bit offset to GUP HW subregion containing SPROM data */
526 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
527 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
528
529 /* Convert to bytes */
530 caps->sprom_offset /= 8;
531 }
532
533 return (0);
534 }
535
536 static int
chipc_suspend(device_t dev)537 chipc_suspend(device_t dev)
538 {
539 return (bus_generic_suspend(dev));
540 }
541
542 static int
chipc_resume(device_t dev)543 chipc_resume(device_t dev)
544 {
545 return (bus_generic_resume(dev));
546 }
547
548 static void
chipc_probe_nomatch(device_t dev,device_t child)549 chipc_probe_nomatch(device_t dev, device_t child)
550 {
551 struct resource_list *rl;
552 const char *name;
553
554 name = device_get_name(child);
555 if (name == NULL)
556 name = "unknown device";
557
558 device_printf(dev, "<%s> at", name);
559
560 rl = BUS_GET_RESOURCE_LIST(dev, child);
561 if (rl != NULL) {
562 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
563 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
564 }
565
566 printf(" (no driver attached)\n");
567 }
568
569 static int
chipc_print_child(device_t dev,device_t child)570 chipc_print_child(device_t dev, device_t child)
571 {
572 struct resource_list *rl;
573 int retval = 0;
574
575 retval += bus_print_child_header(dev, child);
576
577 rl = BUS_GET_RESOURCE_LIST(dev, child);
578 if (rl != NULL) {
579 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
580 "%#jx");
581 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
582 "%jd");
583 }
584
585 retval += bus_print_child_domain(dev, child);
586 retval += bus_print_child_footer(dev, child);
587
588 return (retval);
589 }
590
591 static device_t
chipc_add_child(device_t dev,u_int order,const char * name,int unit)592 chipc_add_child(device_t dev, u_int order, const char *name, int unit)
593 {
594 struct chipc_devinfo *dinfo;
595 device_t child;
596
597 child = device_add_child_ordered(dev, order, name, unit);
598 if (child == NULL)
599 return (NULL);
600
601 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
602 if (dinfo == NULL) {
603 device_delete_child(dev, child);
604 return (NULL);
605 }
606
607 resource_list_init(&dinfo->resources);
608 dinfo->irq_mapped = false;
609 device_set_ivars(child, dinfo);
610
611 return (child);
612 }
613
614 static void
chipc_child_deleted(device_t dev,device_t child)615 chipc_child_deleted(device_t dev, device_t child)
616 {
617 struct chipc_devinfo *dinfo = device_get_ivars(child);
618
619 if (dinfo != NULL) {
620 /* Free the child's resource list */
621 resource_list_free(&dinfo->resources);
622
623 /* Unmap the child's IRQ */
624 if (dinfo->irq_mapped) {
625 bhnd_unmap_intr(dev, dinfo->irq);
626 dinfo->irq_mapped = false;
627 }
628
629 free(dinfo, M_BHND);
630 }
631
632 device_set_ivars(child, NULL);
633 }
634
635 static struct resource_list *
chipc_get_resource_list(device_t dev,device_t child)636 chipc_get_resource_list(device_t dev, device_t child)
637 {
638 struct chipc_devinfo *dinfo = device_get_ivars(child);
639 return (&dinfo->resources);
640 }
641
642 /* Allocate region records for the given port, and add the port's memory
643 * range to the mem_rman */
644 static int
chipc_rman_init_regions(struct chipc_softc * sc,bhnd_port_type type,u_int port)645 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
646 u_int port)
647 {
648 struct chipc_region *cr;
649 rman_res_t start, end;
650 u_int num_regions;
651 int error;
652
653 num_regions = bhnd_get_region_count(sc->dev, type, port);
654 for (u_int region = 0; region < num_regions; region++) {
655 /* Allocate new region record */
656 cr = chipc_alloc_region(sc, type, port, region);
657 if (cr == NULL)
658 return (ENODEV);
659
660 /* Can't manage regions that cannot be allocated */
661 if (cr->cr_rid < 0) {
662 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
663 "%s%u.%u", bhnd_port_type_name(type), port, region);
664 chipc_free_region(sc, cr);
665 continue;
666 }
667
668 /* Add to rman's managed range */
669 start = cr->cr_addr;
670 end = cr->cr_end;
671 if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
672 chipc_free_region(sc, cr);
673 return (error);
674 }
675
676 /* Add to region list */
677 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
678 }
679
680 return (0);
681 }
682
683 /* Initialize memory state for all chipc port regions */
684 static int
chipc_init_rman(struct chipc_softc * sc)685 chipc_init_rman(struct chipc_softc *sc)
686 {
687 u_int num_ports;
688 int error;
689
690 /* Port types for which we'll register chipc_region mappings */
691 bhnd_port_type types[] = {
692 BHND_PORT_DEVICE
693 };
694
695 /* Initialize resource manager */
696 sc->mem_rman.rm_start = 0;
697 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
698 sc->mem_rman.rm_type = RMAN_ARRAY;
699 sc->mem_rman.rm_descr = "ChipCommon Device Memory";
700 if ((error = rman_init(&sc->mem_rman))) {
701 device_printf(sc->dev, "could not initialize mem_rman: %d\n",
702 error);
703 return (error);
704 }
705
706 /* Populate per-port-region state */
707 for (u_int i = 0; i < nitems(types); i++) {
708 num_ports = bhnd_get_port_count(sc->dev, types[i]);
709 for (u_int port = 0; port < num_ports; port++) {
710 error = chipc_rman_init_regions(sc, types[i], port);
711 if (error) {
712 device_printf(sc->dev,
713 "region init failed for %s%u: %d\n",
714 bhnd_port_type_name(types[i]), port,
715 error);
716
717 goto failed;
718 }
719 }
720 }
721
722 return (0);
723
724 failed:
725 chipc_free_rman(sc);
726 return (error);
727 }
728
729 /* Free memory management state */
730 static void
chipc_free_rman(struct chipc_softc * sc)731 chipc_free_rman(struct chipc_softc *sc)
732 {
733 struct chipc_region *cr, *cr_next;
734
735 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
736 chipc_free_region(sc, cr);
737
738 rman_fini(&sc->mem_rman);
739 }
740
741 /**
742 * Return the rman instance for a given resource @p type, if any.
743 *
744 * @param sc The chipc device state.
745 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
746 * @param flags Resource flags (e.g. RF_PREFETCHABLE)
747 */
748 static struct rman *
chipc_get_rman(device_t dev,int type,u_int flags)749 chipc_get_rman(device_t dev, int type, u_int flags)
750 {
751 struct chipc_softc *sc = device_get_softc(dev);
752
753 switch (type) {
754 case SYS_RES_MEMORY:
755 return (&sc->mem_rman);
756
757 case SYS_RES_IRQ:
758 /* We delegate IRQ resource management to the parent bus */
759 return (NULL);
760
761 default:
762 return (NULL);
763 };
764 }
765
766 static struct resource *
chipc_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)767 chipc_alloc_resource(device_t dev, device_t child, int type,
768 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
769 {
770 struct chipc_softc *sc;
771 struct chipc_region *cr;
772 struct resource_list_entry *rle;
773 struct resource *rv;
774 struct rman *rm;
775 int error;
776 bool passthrough, isdefault;
777
778 sc = device_get_softc(dev);
779 passthrough = (device_get_parent(child) != dev);
780 isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
781 rle = NULL;
782
783 /* Fetch the resource manager, delegate request if necessary */
784 rm = chipc_get_rman(dev, type, flags);
785 if (rm == NULL) {
786 /* Requested resource type is delegated to our parent */
787 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
788 start, end, count, flags);
789 return (rv);
790 }
791
792 /* Populate defaults */
793 if (!passthrough && isdefault) {
794 /* Fetch the resource list entry. */
795 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
796 type, *rid);
797 if (rle == NULL) {
798 device_printf(dev,
799 "default resource %#x type %d for child %s "
800 "not found\n", *rid, type,
801 device_get_nameunit(child));
802 return (NULL);
803 }
804
805 if (rle->res != NULL) {
806 device_printf(dev,
807 "resource entry %#x type %d for child %s is busy "
808 "[%d]\n",
809 *rid, type, device_get_nameunit(child),
810 rman_get_flags(rle->res));
811
812 return (NULL);
813 }
814
815 start = rle->start;
816 end = rle->end;
817 count = ulmax(count, rle->count);
818 }
819
820 /* Locate a mapping region */
821 if ((cr = chipc_find_region(sc, start, end)) == NULL) {
822 /* Resource requests outside our shared port regions can be
823 * delegated to our parent. */
824 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
825 start, end, count, flags);
826 return (rv);
827 }
828
829 /*
830 * As a special case, children that map the complete ChipCommon register
831 * block are delegated to our parent.
832 *
833 * The rman API does not support sharing resources that are not
834 * identical in size; since we allocate subregions to various children,
835 * any children that need to map the entire register block (e.g. because
836 * they require access to discontiguous register ranges) must make the
837 * allocation through our parent, where we hold a compatible
838 * RF_SHAREABLE allocation.
839 */
840 if (cr == sc->core_region && cr->cr_addr == start &&
841 cr->cr_end == end && cr->cr_count == count)
842 {
843 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
844 start, end, count, flags);
845 return (rv);
846 }
847
848 /* Try to retain a region reference */
849 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
850 return (NULL);
851
852 /* Make our rman reservation */
853 rv = bus_generic_rman_alloc_resource(dev, child, type, rid, start, end,
854 count, flags);
855 if (rv == NULL) {
856 chipc_release_region(sc, cr, RF_ALLOCATED);
857 return (NULL);
858 }
859
860 /* Update child's resource list entry */
861 if (rle != NULL) {
862 rle->res = rv;
863 rle->start = rman_get_start(rv);
864 rle->end = rman_get_end(rv);
865 rle->count = rman_get_size(rv);
866 }
867
868 return (rv);
869 }
870
871 static int
chipc_release_resource(device_t dev,device_t child,struct resource * r)872 chipc_release_resource(device_t dev, device_t child, struct resource *r)
873 {
874 struct chipc_softc *sc;
875 struct chipc_region *cr;
876 struct rman *rm;
877 struct resource_list_entry *rle;
878 int error;
879
880 sc = device_get_softc(dev);
881
882 /* Handled by parent bus? */
883 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
884 if (rm == NULL || !rman_is_region_manager(r, rm)) {
885 return (bus_generic_rl_release_resource(dev, child, r));
886 }
887
888 /* Locate the mapping region */
889 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
890 if (cr == NULL)
891 return (EINVAL);
892
893 /* Cache rle */
894 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
895 rman_get_type(r), rman_get_rid(r));
896
897 /* Deactivate resources */
898 error = bus_generic_rman_release_resource(dev, child, r);
899 if (error != 0)
900 return (error);
901
902 /* Drop allocation reference */
903 chipc_release_region(sc, cr, RF_ALLOCATED);
904
905 /* Clear reference from the resource list entry if exists */
906 if (rle != NULL)
907 rle->res = NULL;
908
909 return (0);
910 }
911
912 static int
chipc_adjust_resource(device_t dev,device_t child,struct resource * r,rman_res_t start,rman_res_t end)913 chipc_adjust_resource(device_t dev, device_t child,
914 struct resource *r, rman_res_t start, rman_res_t end)
915 {
916 struct chipc_softc *sc;
917 struct chipc_region *cr;
918 struct rman *rm;
919
920 sc = device_get_softc(dev);
921
922 /* Handled by parent bus? */
923 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
924 if (rm == NULL || !rman_is_region_manager(r, rm)) {
925 return (bus_generic_adjust_resource(dev, child, r, start, end));
926 }
927
928 /* The range is limited to the existing region mapping */
929 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
930 if (cr == NULL)
931 return (EINVAL);
932
933 if (end <= start)
934 return (EINVAL);
935
936 if (start < cr->cr_addr || end > cr->cr_end)
937 return (EINVAL);
938
939 /* Range falls within the existing region */
940 return (rman_adjust_resource(r, start, end));
941 }
942
943 /**
944 * Retain an RF_ACTIVE reference to the region mapping @p r, and
945 * configure @p r with its subregion values.
946 *
947 * @param sc Driver instance state.
948 * @param child Requesting child device.
949 * @param r resource to be activated.
950 * @param req_direct If true, failure to allocate a direct bhnd resource
951 * will be treated as an error. If false, the resource will not be marked
952 * as RF_ACTIVE if bhnd direct resource allocation fails.
953 */
954 static int
chipc_try_activate_resource(device_t dev,device_t child,struct resource * r,bool req_direct)955 chipc_try_activate_resource(device_t dev, device_t child,
956 struct resource *r, bool req_direct)
957 {
958 struct chipc_softc *sc = device_get_softc(dev);
959 struct rman *rm;
960 struct chipc_region *cr;
961 bhnd_size_t cr_offset;
962 rman_res_t r_start, r_end, r_size;
963 int error;
964
965 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
966 if (rm == NULL || !rman_is_region_manager(r, rm))
967 return (EINVAL);
968
969 r_start = rman_get_start(r);
970 r_end = rman_get_end(r);
971 r_size = rman_get_size(r);
972
973 /* Find the corresponding chipc region */
974 cr = chipc_find_region(sc, r_start, r_end);
975 if (cr == NULL)
976 return (EINVAL);
977
978 /* Calculate subregion offset within the chipc region */
979 cr_offset = r_start - cr->cr_addr;
980
981 /* Retain (and activate, if necessary) the chipc region */
982 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
983 return (error);
984
985 /* Configure child resource with its subregion values. */
986 if (cr->cr_res->direct) {
987 error = chipc_init_child_resource(r, cr->cr_res->res,
988 cr_offset, r_size);
989 if (error)
990 goto cleanup;
991
992 /* Mark active */
993 if ((error = rman_activate_resource(r)))
994 goto cleanup;
995 } else if (req_direct) {
996 error = ENOMEM;
997 goto cleanup;
998 }
999
1000 return (0);
1001
1002 cleanup:
1003 chipc_release_region(sc, cr, RF_ACTIVE);
1004 return (error);
1005 }
1006
1007 static int
chipc_activate_bhnd_resource(device_t dev,device_t child,int type,int rid,struct bhnd_resource * r)1008 chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
1009 int rid, struct bhnd_resource *r)
1010 {
1011 struct rman *rm;
1012 int error;
1013
1014 /* Delegate non-locally managed resources to parent */
1015 rm = chipc_get_rman(dev, type, rman_get_flags(r->res));
1016 if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
1017 return (bhnd_bus_generic_activate_resource(dev, child, type,
1018 rid, r));
1019 }
1020
1021 /* Try activating the chipc region resource */
1022 error = chipc_try_activate_resource(dev, child, r->res, false);
1023 if (error)
1024 return (error);
1025
1026 /* Mark the child resource as direct according to the returned resource
1027 * state */
1028 if (rman_get_flags(r->res) & RF_ACTIVE)
1029 r->direct = true;
1030
1031 return (0);
1032 }
1033
1034 static int
chipc_activate_resource(device_t dev,device_t child,struct resource * r)1035 chipc_activate_resource(device_t dev, device_t child, struct resource *r)
1036 {
1037 struct rman *rm;
1038
1039 /* Delegate non-locally managed resources to parent */
1040 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
1041 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1042 return (bus_generic_activate_resource(dev, child, r));
1043 }
1044
1045 /* Try activating the chipc region-based resource */
1046 return (chipc_try_activate_resource(dev, child, r, true));
1047 }
1048
1049 /**
1050 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
1051 */
1052 static int
chipc_deactivate_resource(device_t dev,device_t child,struct resource * r)1053 chipc_deactivate_resource(device_t dev, device_t child,
1054 struct resource *r)
1055 {
1056 struct chipc_softc *sc;
1057 struct chipc_region *cr;
1058 struct rman *rm;
1059 int error;
1060
1061 sc = device_get_softc(dev);
1062
1063 /* Handled by parent bus? */
1064 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r));
1065 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1066 return (bus_generic_deactivate_resource(dev, child, r));
1067 }
1068
1069 /* Find the corresponding chipc region */
1070 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
1071 if (cr == NULL)
1072 return (EINVAL);
1073
1074 /* Mark inactive */
1075 if ((error = rman_deactivate_resource(r)))
1076 return (error);
1077
1078 /* Drop associated RF_ACTIVE reference */
1079 chipc_release_region(sc, cr, RF_ACTIVE);
1080
1081 return (0);
1082 }
1083
1084 /**
1085 * Examine bus state and make a best effort determination of whether it's
1086 * likely safe to enable the muxed SPROM pins.
1087 *
1088 * On devices that do not use SPROM pin muxing, always returns true.
1089 *
1090 * @param sc chipc driver state.
1091 */
1092 static bool
chipc_should_enable_muxed_sprom(struct chipc_softc * sc)1093 chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
1094 {
1095 device_t *devs;
1096 device_t hostb;
1097 device_t parent;
1098 int devcount;
1099 int error;
1100 bool result;
1101
1102 /* Nothing to do? */
1103 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1104 return (true);
1105
1106 bus_topo_lock();
1107
1108 parent = device_get_parent(sc->dev);
1109 hostb = bhnd_bus_find_hostb_device(parent);
1110
1111 if ((error = device_get_children(parent, &devs, &devcount))) {
1112 bus_topo_unlock();
1113 return (false);
1114 }
1115
1116 /* Reject any active devices other than ChipCommon, or the
1117 * host bridge (if any). */
1118 result = true;
1119 for (int i = 0; i < devcount; i++) {
1120 if (devs[i] == hostb || devs[i] == sc->dev)
1121 continue;
1122
1123 if (!device_is_attached(devs[i]))
1124 continue;
1125
1126 if (device_is_suspended(devs[i]))
1127 continue;
1128
1129 /* Active device; assume SPROM is busy */
1130 result = false;
1131 break;
1132 }
1133
1134 free(devs, M_TEMP);
1135 bus_topo_unlock();
1136 return (result);
1137 }
1138
1139 static int
chipc_enable_sprom(device_t dev)1140 chipc_enable_sprom(device_t dev)
1141 {
1142 struct chipc_softc *sc;
1143 int error;
1144
1145 sc = device_get_softc(dev);
1146 CHIPC_LOCK(sc);
1147
1148 /* Already enabled? */
1149 if (sc->sprom_refcnt >= 1) {
1150 sc->sprom_refcnt++;
1151 CHIPC_UNLOCK(sc);
1152
1153 return (0);
1154 }
1155
1156 switch (sc->caps.nvram_src) {
1157 case BHND_NVRAM_SRC_SPROM:
1158 error = chipc_enable_sprom_pins(sc);
1159 break;
1160 case BHND_NVRAM_SRC_OTP:
1161 error = chipc_enable_otp_power(sc);
1162 break;
1163 default:
1164 error = 0;
1165 break;
1166 }
1167
1168 /* Bump the reference count */
1169 if (error == 0)
1170 sc->sprom_refcnt++;
1171
1172 CHIPC_UNLOCK(sc);
1173 return (error);
1174 }
1175
1176 static void
chipc_disable_sprom(device_t dev)1177 chipc_disable_sprom(device_t dev)
1178 {
1179 struct chipc_softc *sc;
1180
1181 sc = device_get_softc(dev);
1182 CHIPC_LOCK(sc);
1183
1184 /* Check reference count, skip disable if in-use. */
1185 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
1186 sc->sprom_refcnt--;
1187 if (sc->sprom_refcnt > 0) {
1188 CHIPC_UNLOCK(sc);
1189 return;
1190 }
1191
1192 switch (sc->caps.nvram_src) {
1193 case BHND_NVRAM_SRC_SPROM:
1194 chipc_disable_sprom_pins(sc);
1195 break;
1196 case BHND_NVRAM_SRC_OTP:
1197 chipc_disable_otp_power(sc);
1198 break;
1199 default:
1200 break;
1201 }
1202
1203 CHIPC_UNLOCK(sc);
1204 }
1205
1206 static int
chipc_enable_otp_power(struct chipc_softc * sc)1207 chipc_enable_otp_power(struct chipc_softc *sc)
1208 {
1209 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for
1210 // OTPS_READY to be set in `optstatus`.
1211 return (0);
1212 }
1213
1214 static void
chipc_disable_otp_power(struct chipc_softc * sc)1215 chipc_disable_otp_power(struct chipc_softc *sc)
1216 {
1217 // TODO: Disable OTP resource via PMU
1218 }
1219
1220 /**
1221 * If required by this device, enable access to the SPROM.
1222 *
1223 * @param sc chipc driver state.
1224 */
1225 static int
chipc_enable_sprom_pins(struct chipc_softc * sc)1226 chipc_enable_sprom_pins(struct chipc_softc *sc)
1227 {
1228 uint32_t cctrl;
1229
1230 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1231 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
1232
1233 /* Nothing to do? */
1234 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1235 return (0);
1236
1237 /* Check whether bus is busy */
1238 if (!chipc_should_enable_muxed_sprom(sc))
1239 return (EBUSY);
1240
1241 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1242
1243 /* 4331 devices */
1244 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1245 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
1246
1247 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1248 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1249
1250 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1251 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
1252
1253 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1254 return (0);
1255 }
1256
1257 /* 4360 devices */
1258 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1259 /* Unimplemented */
1260 }
1261
1262 /* Refuse to proceed on unsupported devices with muxed SPROM pins */
1263 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
1264 return (ENXIO);
1265 }
1266
1267 /**
1268 * If required by this device, revert any GPIO/pin configuration applied
1269 * to allow SPROM access.
1270 *
1271 * @param sc chipc driver state.
1272 */
1273 static void
chipc_disable_sprom_pins(struct chipc_softc * sc)1274 chipc_disable_sprom_pins(struct chipc_softc *sc)
1275 {
1276 uint32_t cctrl;
1277
1278 /* Nothing to do? */
1279 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1280 return;
1281
1282 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1283 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
1284
1285 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1286
1287 /* 4331 devices */
1288 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1289 cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
1290
1291 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1292 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1293
1294 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1295 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
1296
1297 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1298 return;
1299 }
1300
1301 /* 4360 devices */
1302 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1303 /* Unimplemented */
1304 }
1305 }
1306
1307 static uint32_t
chipc_read_chipst(device_t dev)1308 chipc_read_chipst(device_t dev)
1309 {
1310 struct chipc_softc *sc = device_get_softc(dev);
1311 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
1312 }
1313
1314 static void
chipc_write_chipctrl(device_t dev,uint32_t value,uint32_t mask)1315 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
1316 {
1317 struct chipc_softc *sc;
1318 uint32_t cctrl;
1319
1320 sc = device_get_softc(dev);
1321
1322 CHIPC_LOCK(sc);
1323
1324 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1325 cctrl = (cctrl & ~mask) | (value | mask);
1326 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1327
1328 CHIPC_UNLOCK(sc);
1329 }
1330
1331 static struct chipc_caps *
chipc_get_caps(device_t dev)1332 chipc_get_caps(device_t dev)
1333 {
1334 struct chipc_softc *sc;
1335
1336 sc = device_get_softc(dev);
1337 return (&sc->caps);
1338 }
1339
1340 static device_method_t chipc_methods[] = {
1341 /* Device interface */
1342 DEVMETHOD(device_probe, chipc_probe),
1343 DEVMETHOD(device_attach, chipc_attach),
1344 DEVMETHOD(device_detach, chipc_detach),
1345 DEVMETHOD(device_suspend, chipc_suspend),
1346 DEVMETHOD(device_resume, chipc_resume),
1347
1348 /* Bus interface */
1349 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch),
1350 DEVMETHOD(bus_print_child, chipc_print_child),
1351
1352 DEVMETHOD(bus_add_child, chipc_add_child),
1353 DEVMETHOD(bus_child_deleted, chipc_child_deleted),
1354
1355 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
1356 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
1357 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
1358 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource),
1359 DEVMETHOD(bus_release_resource, chipc_release_resource),
1360 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource),
1361 DEVMETHOD(bus_activate_resource, chipc_activate_resource),
1362 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource),
1363 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list),
1364 DEVMETHOD(bus_get_rman, chipc_get_rman),
1365
1366 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1367 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1368 DEVMETHOD(bus_config_intr, bus_generic_config_intr),
1369 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
1370 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
1371
1372 /* BHND bus inteface */
1373 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
1374
1375 /* ChipCommon interface */
1376 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
1377 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
1378 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
1379 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
1380 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
1381
1382 DEVMETHOD_END
1383 };
1384
1385 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
1386 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, 0, 0,
1387 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1388 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
1389 MODULE_VERSION(bhnd_chipc, 1);
1390