1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifdef HAVE_KERNEL_OPTION_HEADERS
30 #include "opt_snd.h"
31 #endif
32
33 #include <dev/sound/pcm/sound.h>
34 #include <dev/sound/pcm/ac97.h>
35 #include <dev/sound/pci/t4dwave.h>
36
37 #include <dev/pci/pcireg.h>
38 #include <dev/pci/pcivar.h>
39
40 /* -------------------------------------------------------------------- */
41
42 #define TDX_PCI_ID 0x20001023
43 #define TNX_PCI_ID 0x20011023
44 #define ALI_PCI_ID 0x545110b9
45 #define SPA_PCI_ID 0x70181039
46
47 #define TR_DEFAULT_BUFSZ 0x1000
48 /* For ALi M5451 the DMA transfer size appears to be fixed to 64k. */
49 #define ALI_BUFSZ 0x10000
50 #define TR_BUFALGN 0x8
51 #define TR_TIMEOUT_CDC 0xffff
52 #define TR_MAXHWCH 64
53 #define ALI_MAXHWCH 32
54 #define TR_MAXPLAYCH 4
55 #define ALI_MAXPLAYCH 1
56 /*
57 * Though, it's not clearly documented in the 4DWAVE datasheet, the
58 * DX and NX chips can't handle DMA addresses located above 1GB as the
59 * LBA (loop begin address) register which holds the DMA base address
60 * is 32-bit, but the two MSBs are used for other purposes.
61 */
62 #define TR_MAXADDR ((1U << 30) - 1)
63 #define ALI_MAXADDR ((1U << 31) - 1)
64
65 struct tr_info;
66
67 /* channel registers */
68 struct tr_chinfo {
69 u_int32_t cso, alpha, fms, fmc, ec;
70 u_int32_t lba;
71 u_int32_t eso, delta;
72 u_int32_t rvol, cvol;
73 u_int32_t gvsel, pan, vol, ctrl;
74 u_int32_t active:1, was_active:1;
75 int index, bufhalf;
76 struct snd_dbuf *buffer;
77 struct pcm_channel *channel;
78 struct tr_info *parent;
79 };
80
81 struct tr_rchinfo {
82 u_int32_t delta;
83 u_int32_t active:1, was_active:1;
84 struct snd_dbuf *buffer;
85 struct pcm_channel *channel;
86 struct tr_info *parent;
87 };
88
89 /* device private data */
90 struct tr_info {
91 u_int32_t type;
92 u_int32_t rev;
93
94 bus_space_tag_t st;
95 bus_space_handle_t sh;
96 bus_dma_tag_t parent_dmat;
97
98 struct resource *reg, *irq;
99 int regtype, regid, irqid;
100 void *ih;
101
102 struct mtx *lock;
103
104 u_int32_t hwchns;
105 u_int32_t playchns;
106 unsigned int bufsz;
107
108 struct tr_chinfo chinfo[TR_MAXPLAYCH];
109 struct tr_rchinfo recchinfo;
110 };
111
112 /* -------------------------------------------------------------------- */
113
114 static u_int32_t tr_recfmt[] = {
115 SND_FORMAT(AFMT_U8, 1, 0),
116 SND_FORMAT(AFMT_U8, 2, 0),
117 SND_FORMAT(AFMT_S8, 1, 0),
118 SND_FORMAT(AFMT_S8, 2, 0),
119 SND_FORMAT(AFMT_S16_LE, 1, 0),
120 SND_FORMAT(AFMT_S16_LE, 2, 0),
121 SND_FORMAT(AFMT_U16_LE, 1, 0),
122 SND_FORMAT(AFMT_U16_LE, 2, 0),
123 0
124 };
125 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0};
126
127 static u_int32_t tr_playfmt[] = {
128 SND_FORMAT(AFMT_U8, 1, 0),
129 SND_FORMAT(AFMT_U8, 2, 0),
130 SND_FORMAT(AFMT_S8, 1, 0),
131 SND_FORMAT(AFMT_S8, 2, 0),
132 SND_FORMAT(AFMT_S16_LE, 1, 0),
133 SND_FORMAT(AFMT_S16_LE, 2, 0),
134 SND_FORMAT(AFMT_U16_LE, 1, 0),
135 SND_FORMAT(AFMT_U16_LE, 2, 0),
136 0
137 };
138 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0};
139
140 /* -------------------------------------------------------------------- */
141
142 /* Hardware */
143
144 static u_int32_t
tr_rd(struct tr_info * tr,int regno,int size)145 tr_rd(struct tr_info *tr, int regno, int size)
146 {
147 switch(size) {
148 case 1:
149 return bus_space_read_1(tr->st, tr->sh, regno);
150 case 2:
151 return bus_space_read_2(tr->st, tr->sh, regno);
152 case 4:
153 return bus_space_read_4(tr->st, tr->sh, regno);
154 default:
155 return 0xffffffff;
156 }
157 }
158
159 static void
tr_wr(struct tr_info * tr,int regno,u_int32_t data,int size)160 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size)
161 {
162 switch(size) {
163 case 1:
164 bus_space_write_1(tr->st, tr->sh, regno, data);
165 break;
166 case 2:
167 bus_space_write_2(tr->st, tr->sh, regno, data);
168 break;
169 case 4:
170 bus_space_write_4(tr->st, tr->sh, regno, data);
171 break;
172 }
173 }
174
175 /* -------------------------------------------------------------------- */
176 /* ac97 codec */
177
178 static int
tr_rdcd(kobj_t obj,void * devinfo,int regno)179 tr_rdcd(kobj_t obj, void *devinfo, int regno)
180 {
181 struct tr_info *tr = (struct tr_info *)devinfo;
182 int i, j, treg, trw;
183
184 switch (tr->type) {
185 case SPA_PCI_ID:
186 treg=SPA_REG_CODECRD;
187 trw=SPA_CDC_RWSTAT;
188 break;
189 case ALI_PCI_ID:
190 if (tr->rev > 0x01)
191 treg=TDX_REG_CODECWR;
192 else
193 treg=TDX_REG_CODECRD;
194 trw=TDX_CDC_RWSTAT;
195 break;
196 case TDX_PCI_ID:
197 treg=TDX_REG_CODECRD;
198 trw=TDX_CDC_RWSTAT;
199 break;
200 case TNX_PCI_ID:
201 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD;
202 trw=TNX_CDC_RWSTAT;
203 break;
204 default:
205 printf("!!! tr_rdcd defaulted !!!\n");
206 return -1;
207 }
208
209 i = j = 0;
210
211 regno &= 0x7f;
212 snd_mtxlock(tr->lock);
213 if (tr->type == ALI_PCI_ID) {
214 u_int32_t chk1, chk2;
215 j = trw;
216 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
217 j = tr_rd(tr, treg, 4);
218 if (i > 0) {
219 chk1 = tr_rd(tr, 0xc8, 4);
220 chk2 = tr_rd(tr, 0xc8, 4);
221 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
222 i--)
223 chk2 = tr_rd(tr, 0xc8, 4);
224 }
225 }
226 if (tr->type != ALI_PCI_ID || i > 0) {
227 tr_wr(tr, treg, regno | trw, 4);
228 j=trw;
229 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
230 j=tr_rd(tr, treg, 4);
231 }
232 snd_mtxunlock(tr->lock);
233 if (i == 0) printf("codec timeout during read of register %x\n", regno);
234 return (j >> TR_CDC_DATA) & 0xffff;
235 }
236
237 static int
tr_wrcd(kobj_t obj,void * devinfo,int regno,u_int32_t data)238 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
239 {
240 struct tr_info *tr = (struct tr_info *)devinfo;
241 int i, j, treg, trw;
242
243 switch (tr->type) {
244 case SPA_PCI_ID:
245 treg=SPA_REG_CODECWR;
246 trw=SPA_CDC_RWSTAT;
247 break;
248 case ALI_PCI_ID:
249 case TDX_PCI_ID:
250 treg=TDX_REG_CODECWR;
251 trw=TDX_CDC_RWSTAT;
252 break;
253 case TNX_PCI_ID:
254 treg=TNX_REG_CODECWR;
255 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0);
256 break;
257 default:
258 printf("!!! tr_wrcd defaulted !!!");
259 return -1;
260 }
261
262 i = 0;
263
264 regno &= 0x7f;
265 #if 0
266 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno));
267 #endif
268 j=trw;
269 snd_mtxlock(tr->lock);
270 if (tr->type == ALI_PCI_ID) {
271 j = trw;
272 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
273 j = tr_rd(tr, treg, 4);
274 if (i > 0) {
275 u_int32_t chk1, chk2;
276 chk1 = tr_rd(tr, 0xc8, 4);
277 chk2 = tr_rd(tr, 0xc8, 4);
278 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
279 i--)
280 chk2 = tr_rd(tr, 0xc8, 4);
281 }
282 }
283 if (tr->type != ALI_PCI_ID || i > 0) {
284 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--)
285 j=tr_rd(tr, treg, 4);
286 if (tr->type == ALI_PCI_ID && tr->rev > 0x01)
287 trw |= 0x0100;
288 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4);
289 }
290 #if 0
291 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno));
292 #endif
293 snd_mtxunlock(tr->lock);
294 if (i==0) printf("codec timeout writing %x, data %x\n", regno, data);
295 return (i > 0)? 0 : -1;
296 }
297
298 static kobj_method_t tr_ac97_methods[] = {
299 KOBJMETHOD(ac97_read, tr_rdcd),
300 KOBJMETHOD(ac97_write, tr_wrcd),
301 KOBJMETHOD_END
302 };
303 AC97_DECLARE(tr_ac97);
304
305 /* -------------------------------------------------------------------- */
306 /* playback channel interrupts */
307
308 #if 0
309 static u_int32_t
310 tr_testint(struct tr_chinfo *ch)
311 {
312 struct tr_info *tr = ch->parent;
313 int bank, chan;
314
315 bank = (ch->index & 0x20) ? 1 : 0;
316 chan = ch->index & 0x1f;
317 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan);
318 }
319 #endif
320
321 static void
tr_clrint(struct tr_chinfo * ch)322 tr_clrint(struct tr_chinfo *ch)
323 {
324 struct tr_info *tr = ch->parent;
325 int bank, chan;
326
327 bank = (ch->index & 0x20) ? 1 : 0;
328 chan = ch->index & 0x1f;
329 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4);
330 }
331
332 static void
tr_enaint(struct tr_chinfo * ch,int enable)333 tr_enaint(struct tr_chinfo *ch, int enable)
334 {
335 struct tr_info *tr = ch->parent;
336 u_int32_t i, reg;
337 int bank, chan;
338
339 snd_mtxlock(tr->lock);
340 bank = (ch->index & 0x20) ? 1 : 0;
341 chan = ch->index & 0x1f;
342 reg = bank? TR_REG_INTENB : TR_REG_INTENA;
343
344 i = tr_rd(tr, reg, 4);
345 i &= ~(1 << chan);
346 i |= (enable? 1 : 0) << chan;
347
348 tr_clrint(ch);
349 tr_wr(tr, reg, i, 4);
350 snd_mtxunlock(tr->lock);
351 }
352
353 /* playback channels */
354
355 static void
tr_selch(struct tr_chinfo * ch)356 tr_selch(struct tr_chinfo *ch)
357 {
358 struct tr_info *tr = ch->parent;
359 int i;
360
361 i = tr_rd(tr, TR_REG_CIR, 4);
362 i &= ~TR_CIR_MASK;
363 i |= ch->index & 0x3f;
364 tr_wr(tr, TR_REG_CIR, i, 4);
365 }
366
367 static void
tr_startch(struct tr_chinfo * ch)368 tr_startch(struct tr_chinfo *ch)
369 {
370 struct tr_info *tr = ch->parent;
371 int bank, chan;
372
373 bank = (ch->index & 0x20) ? 1 : 0;
374 chan = ch->index & 0x1f;
375 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4);
376 }
377
378 static void
tr_stopch(struct tr_chinfo * ch)379 tr_stopch(struct tr_chinfo *ch)
380 {
381 struct tr_info *tr = ch->parent;
382 int bank, chan;
383
384 bank = (ch->index & 0x20) ? 1 : 0;
385 chan = ch->index & 0x1f;
386 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4);
387 }
388
389 static void
tr_wrch(struct tr_chinfo * ch)390 tr_wrch(struct tr_chinfo *ch)
391 {
392 struct tr_info *tr = ch->parent;
393 u_int32_t cr[TR_CHN_REGS], i;
394
395 ch->gvsel &= 0x00000001;
396 ch->fmc &= 0x00000003;
397 ch->fms &= 0x0000000f;
398 ch->ctrl &= 0x0000000f;
399 ch->pan &= 0x0000007f;
400 ch->rvol &= 0x0000007f;
401 ch->cvol &= 0x0000007f;
402 ch->vol &= 0x000000ff;
403 ch->ec &= 0x00000fff;
404 ch->alpha &= 0x00000fff;
405 ch->delta &= 0x0000ffff;
406 if (tr->type == ALI_PCI_ID)
407 ch->lba &= ALI_MAXADDR;
408 else
409 ch->lba &= TR_MAXADDR;
410
411 cr[1]=ch->lba;
412 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol);
413 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec);
414
415 switch (tr->type) {
416 case SPA_PCI_ID:
417 case ALI_PCI_ID:
418 case TDX_PCI_ID:
419 ch->cso &= 0x0000ffff;
420 ch->eso &= 0x0000ffff;
421 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms);
422 cr[2]=(ch->eso<<16) | (ch->delta);
423 break;
424 case TNX_PCI_ID:
425 ch->cso &= 0x00ffffff;
426 ch->eso &= 0x00ffffff;
427 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso);
428 cr[2]=((ch->delta>>8)<<24) | (ch->eso);
429 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14);
430 break;
431 }
432 snd_mtxlock(tr->lock);
433 tr_selch(ch);
434 for (i=0; i<TR_CHN_REGS; i++)
435 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4);
436 snd_mtxunlock(tr->lock);
437 }
438
439 static void
tr_rdch(struct tr_chinfo * ch)440 tr_rdch(struct tr_chinfo *ch)
441 {
442 struct tr_info *tr = ch->parent;
443 u_int32_t cr[5], i;
444
445 snd_mtxlock(tr->lock);
446 tr_selch(ch);
447 for (i=0; i<5; i++)
448 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4);
449 snd_mtxunlock(tr->lock);
450
451 if (tr->type == ALI_PCI_ID)
452 ch->lba=(cr[1] & ALI_MAXADDR);
453 else
454 ch->lba=(cr[1] & TR_MAXADDR);
455 ch->fmc= (cr[3] & 0x0000c000) >> 14;
456 ch->rvol= (cr[3] & 0x00003f80) >> 7;
457 ch->cvol= (cr[3] & 0x0000007f);
458 ch->gvsel= (cr[4] & 0x80000000) >> 31;
459 ch->pan= (cr[4] & 0x7f000000) >> 24;
460 ch->vol= (cr[4] & 0x00ff0000) >> 16;
461 ch->ctrl= (cr[4] & 0x0000f000) >> 12;
462 ch->ec= (cr[4] & 0x00000fff);
463 switch(tr->type) {
464 case SPA_PCI_ID:
465 case ALI_PCI_ID:
466 case TDX_PCI_ID:
467 ch->cso= (cr[0] & 0xffff0000) >> 16;
468 ch->alpha= (cr[0] & 0x0000fff0) >> 4;
469 ch->fms= (cr[0] & 0x0000000f);
470 ch->eso= (cr[2] & 0xffff0000) >> 16;
471 ch->delta= (cr[2] & 0x0000ffff);
472 break;
473 case TNX_PCI_ID:
474 ch->cso= (cr[0] & 0x00ffffff);
475 ch->eso= (cr[2] & 0x00ffffff);
476 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24);
477 ch->alpha= (cr[3] & 0xfff00000) >> 20;
478 ch->fms= (cr[3] & 0x000f0000) >> 16;
479 break;
480 }
481 }
482
483 static u_int32_t
tr_fmttobits(u_int32_t fmt)484 tr_fmttobits(u_int32_t fmt)
485 {
486 u_int32_t bits;
487
488 bits = 0;
489 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0;
490 bits |= (AFMT_CHANNEL(fmt) > 1)? 0x4 : 0;
491 bits |= (fmt & AFMT_16BIT)? 0x8 : 0;
492
493 return bits;
494 }
495
496 /* -------------------------------------------------------------------- */
497 /* channel interface */
498
499 static void *
trpchan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)500 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
501 {
502 struct tr_info *tr = devinfo;
503 struct tr_chinfo *ch;
504
505 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction"));
506 ch = &tr->chinfo[tr->playchns];
507 ch->index = tr->playchns++;
508 ch->buffer = b;
509 ch->parent = tr;
510 ch->channel = c;
511 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
512 return NULL;
513
514 return ch;
515 }
516
517 static int
trpchan_setformat(kobj_t obj,void * data,u_int32_t format)518 trpchan_setformat(kobj_t obj, void *data, u_int32_t format)
519 {
520 struct tr_chinfo *ch = data;
521
522 ch->ctrl = tr_fmttobits(format) | 0x01;
523
524 return 0;
525 }
526
527 static u_int32_t
trpchan_setspeed(kobj_t obj,void * data,u_int32_t speed)528 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
529 {
530 struct tr_chinfo *ch = data;
531
532 ch->delta = (speed << 12) / 48000;
533 return (ch->delta * 48000) >> 12;
534 }
535
536 static u_int32_t
trpchan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)537 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
538 {
539 struct tr_chinfo *ch = data;
540
541 sndbuf_resize(ch->buffer, 2, blocksize);
542 return blocksize;
543 }
544
545 static int
trpchan_trigger(kobj_t obj,void * data,int go)546 trpchan_trigger(kobj_t obj, void *data, int go)
547 {
548 struct tr_chinfo *ch = data;
549
550 if (!PCMTRIG_COMMON(go))
551 return 0;
552
553 if (go == PCMTRIG_START) {
554 ch->fmc = 3;
555 ch->fms = 0;
556 ch->ec = 0;
557 ch->alpha = 0;
558 ch->lba = sndbuf_getbufaddr(ch->buffer);
559 ch->cso = 0;
560 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getalign(ch->buffer)) - 1;
561 ch->rvol = ch->cvol = 0x7f;
562 ch->gvsel = 0;
563 ch->pan = 0;
564 ch->vol = 0;
565 ch->bufhalf = 0;
566 tr_wrch(ch);
567 tr_enaint(ch, 1);
568 tr_startch(ch);
569 ch->active = 1;
570 } else {
571 tr_stopch(ch);
572 ch->active = 0;
573 }
574
575 return 0;
576 }
577
578 static u_int32_t
trpchan_getptr(kobj_t obj,void * data)579 trpchan_getptr(kobj_t obj, void *data)
580 {
581 struct tr_chinfo *ch = data;
582
583 tr_rdch(ch);
584 return ch->cso * sndbuf_getalign(ch->buffer);
585 }
586
587 static struct pcmchan_caps *
trpchan_getcaps(kobj_t obj,void * data)588 trpchan_getcaps(kobj_t obj, void *data)
589 {
590 return &tr_playcaps;
591 }
592
593 static kobj_method_t trpchan_methods[] = {
594 KOBJMETHOD(channel_init, trpchan_init),
595 KOBJMETHOD(channel_setformat, trpchan_setformat),
596 KOBJMETHOD(channel_setspeed, trpchan_setspeed),
597 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize),
598 KOBJMETHOD(channel_trigger, trpchan_trigger),
599 KOBJMETHOD(channel_getptr, trpchan_getptr),
600 KOBJMETHOD(channel_getcaps, trpchan_getcaps),
601 KOBJMETHOD_END
602 };
603 CHANNEL_DECLARE(trpchan);
604
605 /* -------------------------------------------------------------------- */
606 /* rec channel interface */
607
608 static void *
trrchan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)609 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
610 {
611 struct tr_info *tr = devinfo;
612 struct tr_rchinfo *ch;
613
614 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction"));
615 ch = &tr->recchinfo;
616 ch->buffer = b;
617 ch->parent = tr;
618 ch->channel = c;
619 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
620 return NULL;
621
622 return ch;
623 }
624
625 static int
trrchan_setformat(kobj_t obj,void * data,u_int32_t format)626 trrchan_setformat(kobj_t obj, void *data, u_int32_t format)
627 {
628 struct tr_rchinfo *ch = data;
629 struct tr_info *tr = ch->parent;
630 u_int32_t i, bits;
631
632 bits = tr_fmttobits(format);
633 /* set # of samples between interrupts */
634 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1;
635 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4);
636 /* set sample format */
637 i = 0x18 | (bits << 4);
638 tr_wr(tr, TR_REG_SBCTRL, i, 1);
639
640 return 0;
641 }
642
643 static u_int32_t
trrchan_setspeed(kobj_t obj,void * data,u_int32_t speed)644 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
645 {
646 struct tr_rchinfo *ch = data;
647 struct tr_info *tr = ch->parent;
648
649 /* setup speed */
650 ch->delta = (48000 << 12) / speed;
651 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2);
652
653 /* return closest possible speed */
654 return (48000 << 12) / ch->delta;
655 }
656
657 static u_int32_t
trrchan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)658 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
659 {
660 struct tr_rchinfo *ch = data;
661
662 sndbuf_resize(ch->buffer, 2, blocksize);
663
664 return blocksize;
665 }
666
667 static int
trrchan_trigger(kobj_t obj,void * data,int go)668 trrchan_trigger(kobj_t obj, void *data, int go)
669 {
670 struct tr_rchinfo *ch = data;
671 struct tr_info *tr = ch->parent;
672 u_int32_t i;
673
674 if (!PCMTRIG_COMMON(go))
675 return 0;
676
677 if (go == PCMTRIG_START) {
678 /* set up dma mode regs */
679 tr_wr(tr, TR_REG_DMAR15, 0, 1);
680 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03;
681 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1);
682 /* set up base address */
683 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4);
684 /* set up buffer size */
685 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff;
686 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4);
687 /* start */
688 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1);
689 ch->active = 1;
690 } else {
691 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1);
692 ch->active = 0;
693 }
694
695 /* return 0 if ok */
696 return 0;
697 }
698
699 static u_int32_t
trrchan_getptr(kobj_t obj,void * data)700 trrchan_getptr(kobj_t obj, void *data)
701 {
702 struct tr_rchinfo *ch = data;
703 struct tr_info *tr = ch->parent;
704
705 /* return current byte offset of channel */
706 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer);
707 }
708
709 static struct pcmchan_caps *
trrchan_getcaps(kobj_t obj,void * data)710 trrchan_getcaps(kobj_t obj, void *data)
711 {
712 return &tr_reccaps;
713 }
714
715 static kobj_method_t trrchan_methods[] = {
716 KOBJMETHOD(channel_init, trrchan_init),
717 KOBJMETHOD(channel_setformat, trrchan_setformat),
718 KOBJMETHOD(channel_setspeed, trrchan_setspeed),
719 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize),
720 KOBJMETHOD(channel_trigger, trrchan_trigger),
721 KOBJMETHOD(channel_getptr, trrchan_getptr),
722 KOBJMETHOD(channel_getcaps, trrchan_getcaps),
723 KOBJMETHOD_END
724 };
725 CHANNEL_DECLARE(trrchan);
726
727 /* -------------------------------------------------------------------- */
728 /* The interrupt handler */
729
730 static void
tr_intr(void * p)731 tr_intr(void *p)
732 {
733 struct tr_info *tr = (struct tr_info *)p;
734 struct tr_chinfo *ch;
735 u_int32_t active, mask, bufhalf, chnum, intsrc;
736 int tmp;
737
738 intsrc = tr_rd(tr, TR_REG_MISCINT, 4);
739 if (intsrc & TR_INT_ADDR) {
740 chnum = 0;
741 while (chnum < tr->hwchns) {
742 mask = 0x00000001;
743 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4);
744 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4);
745 if (active) {
746 do {
747 if (active & mask) {
748 tmp = (bufhalf & mask)? 1 : 0;
749 if (chnum < tr->playchns) {
750 ch = &tr->chinfo[chnum];
751 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */
752 if (ch->bufhalf != tmp) {
753 chn_intr(ch->channel);
754 ch->bufhalf = tmp;
755 }
756 }
757 }
758 chnum++;
759 mask <<= 1;
760 } while (chnum & 31);
761 } else
762 chnum += 32;
763
764 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4);
765 }
766 }
767 if (intsrc & TR_INT_SB) {
768 chn_intr(tr->recchinfo.channel);
769 tr_rd(tr, TR_REG_SBR9, 1);
770 tr_rd(tr, TR_REG_SBR10, 1);
771 }
772 }
773
774 /* -------------------------------------------------------------------- */
775
776 /*
777 * Probe and attach the card
778 */
779
780 static int
tr_init(struct tr_info * tr)781 tr_init(struct tr_info *tr)
782 {
783 switch (tr->type) {
784 case SPA_PCI_ID:
785 tr_wr(tr, SPA_REG_GPIO, 0, 4);
786 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4);
787 break;
788 case TDX_PCI_ID:
789 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4);
790 break;
791 case TNX_PCI_ID:
792 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4);
793 break;
794 }
795
796 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4);
797 return 0;
798 }
799
800 static int
tr_pci_probe(device_t dev)801 tr_pci_probe(device_t dev)
802 {
803 switch (pci_get_devid(dev)) {
804 case SPA_PCI_ID:
805 device_set_desc(dev, "SiS 7018");
806 return BUS_PROBE_DEFAULT;
807 case ALI_PCI_ID:
808 device_set_desc(dev, "Acer Labs M5451");
809 return BUS_PROBE_DEFAULT;
810 case TDX_PCI_ID:
811 device_set_desc(dev, "Trident 4DWave DX");
812 return BUS_PROBE_DEFAULT;
813 case TNX_PCI_ID:
814 device_set_desc(dev, "Trident 4DWave NX");
815 return BUS_PROBE_DEFAULT;
816 }
817
818 return ENXIO;
819 }
820
821 static int
tr_pci_attach(device_t dev)822 tr_pci_attach(device_t dev)
823 {
824 struct tr_info *tr;
825 struct ac97_info *codec = NULL;
826 bus_addr_t lowaddr;
827 int i, dacn;
828 char status[SND_STATUSLEN];
829
830 tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO);
831 tr->type = pci_get_devid(dev);
832 tr->rev = pci_get_revid(dev);
833 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc");
834
835 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
836 "dac", &i) == 0) {
837 if (i < 1)
838 dacn = 1;
839 else if (i > TR_MAXPLAYCH)
840 dacn = TR_MAXPLAYCH;
841 else
842 dacn = i;
843 } else {
844 switch (tr->type) {
845 case ALI_PCI_ID:
846 dacn = ALI_MAXPLAYCH;
847 break;
848 default:
849 dacn = TR_MAXPLAYCH;
850 break;
851 }
852 }
853
854 pci_enable_busmaster(dev);
855
856 tr->regid = PCIR_BAR(0);
857 tr->regtype = SYS_RES_IOPORT;
858 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid,
859 RF_ACTIVE);
860 if (tr->reg) {
861 tr->st = rman_get_bustag(tr->reg);
862 tr->sh = rman_get_bushandle(tr->reg);
863 } else {
864 device_printf(dev, "unable to map register space\n");
865 goto bad;
866 }
867
868 if (tr_init(tr) == -1) {
869 device_printf(dev, "unable to initialize the card\n");
870 goto bad;
871 }
872 tr->playchns = 0;
873
874 codec = AC97_CREATE(dev, tr, tr_ac97);
875 if (codec == NULL) goto bad;
876 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
877
878 tr->irqid = 0;
879 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid,
880 RF_ACTIVE | RF_SHAREABLE);
881 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) {
882 device_printf(dev, "unable to map interrupt\n");
883 goto bad;
884 }
885
886 if (tr->type == ALI_PCI_ID) {
887 /*
888 * The M5451 generates 31 bit of DMA and in order to do
889 * 32-bit DMA, the 31st bit can be set via its accompanying
890 * ISA bridge. Note that we can't predict whether bus_dma(9)
891 * will actually supply us with a 32-bit buffer and even when
892 * using a low address of BUS_SPACE_MAXADDR_32BIT for both
893 * we might end up with the play buffer being in the 32-bit
894 * range while the record buffer isn't or vice versa. So we
895 * don't enabling the 31st bit.
896 */
897 lowaddr = ALI_MAXADDR;
898 tr->hwchns = ALI_MAXHWCH;
899 tr->bufsz = ALI_BUFSZ;
900 } else {
901 lowaddr = TR_MAXADDR;
902 tr->hwchns = TR_MAXHWCH;
903 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ,
904 65536);
905 }
906
907 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
908 /*alignment*/TR_BUFALGN,
909 /*boundary*/0,
910 /*lowaddr*/lowaddr,
911 /*highaddr*/BUS_SPACE_MAXADDR,
912 /*filter*/NULL, /*filterarg*/NULL,
913 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/tr->bufsz,
914 /*flags*/0, /*lockfunc*/NULL, /*lockarg*/NULL,
915 &tr->parent_dmat) != 0) {
916 device_printf(dev, "unable to create dma tag\n");
917 goto bad;
918 }
919
920 snprintf(status, SND_STATUSLEN, "port 0x%jx irq %jd on %s",
921 rman_get_start(tr->reg), rman_get_start(tr->irq),
922 device_get_nameunit(device_get_parent(dev)));
923
924 pcm_init(dev, tr);
925 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr);
926 for (i = 0; i < dacn; i++)
927 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr);
928 if (pcm_register(dev, status))
929 goto bad;
930
931 return 0;
932
933 bad:
934 if (codec) ac97_destroy(codec);
935 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
936 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih);
937 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
938 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat);
939 if (tr->lock) snd_mtxfree(tr->lock);
940 free(tr, M_DEVBUF);
941 return ENXIO;
942 }
943
944 static int
tr_pci_detach(device_t dev)945 tr_pci_detach(device_t dev)
946 {
947 int r;
948 struct tr_info *tr;
949
950 r = pcm_unregister(dev);
951 if (r)
952 return r;
953
954 tr = pcm_getdevinfo(dev);
955 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
956 bus_teardown_intr(dev, tr->irq, tr->ih);
957 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
958 bus_dma_tag_destroy(tr->parent_dmat);
959 snd_mtxfree(tr->lock);
960 free(tr, M_DEVBUF);
961
962 return 0;
963 }
964
965 static int
tr_pci_suspend(device_t dev)966 tr_pci_suspend(device_t dev)
967 {
968 int i;
969 struct tr_info *tr;
970
971 tr = pcm_getdevinfo(dev);
972
973 for (i = 0; i < tr->playchns; i++) {
974 tr->chinfo[i].was_active = tr->chinfo[i].active;
975 if (tr->chinfo[i].active) {
976 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP);
977 }
978 }
979
980 tr->recchinfo.was_active = tr->recchinfo.active;
981 if (tr->recchinfo.active) {
982 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP);
983 }
984
985 return 0;
986 }
987
988 static int
tr_pci_resume(device_t dev)989 tr_pci_resume(device_t dev)
990 {
991 int i;
992 struct tr_info *tr;
993
994 tr = pcm_getdevinfo(dev);
995
996 if (tr_init(tr) == -1) {
997 device_printf(dev, "unable to initialize the card\n");
998 return ENXIO;
999 }
1000
1001 if (mixer_reinit(dev) == -1) {
1002 device_printf(dev, "unable to initialize the mixer\n");
1003 return ENXIO;
1004 }
1005
1006 for (i = 0; i < tr->playchns; i++) {
1007 if (tr->chinfo[i].was_active) {
1008 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START);
1009 }
1010 }
1011
1012 if (tr->recchinfo.was_active) {
1013 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START);
1014 }
1015
1016 return 0;
1017 }
1018
1019 static device_method_t tr_methods[] = {
1020 /* Device interface */
1021 DEVMETHOD(device_probe, tr_pci_probe),
1022 DEVMETHOD(device_attach, tr_pci_attach),
1023 DEVMETHOD(device_detach, tr_pci_detach),
1024 DEVMETHOD(device_suspend, tr_pci_suspend),
1025 DEVMETHOD(device_resume, tr_pci_resume),
1026 { 0, 0 }
1027 };
1028
1029 static driver_t tr_driver = {
1030 "pcm",
1031 tr_methods,
1032 PCM_SOFTC_SIZE,
1033 };
1034
1035 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, 0, 0);
1036 MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1037 MODULE_VERSION(snd_t4dwave, 1);
1038