1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2024 NanjingTianyihexin Electronics Ltd.
4 * http://www.tianyihexin.com
5 *
6 * Driver for NanjingTianyihexin HX9023S Cap Sensor.
7 * Datasheet available at:
8 * http://www.tianyihexin.com/ueditor/php/upload/file/20240614/1718336303992081.pdf
9 */
10
11 #include <linux/array_size.h>
12 #include <linux/bitfield.h>
13 #include <linux/bitops.h>
14 #include <linux/cleanup.h>
15 #include <linux/device.h>
16 #include <linux/errno.h>
17 #include <linux/firmware.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
20 #include <linux/irqreturn.h>
21 #include <linux/math64.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
24 #include <linux/mutex.h>
25 #include <linux/pm.h>
26 #include <linux/property.h>
27 #include <linux/regmap.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/types.h>
30 #include <linux/units.h>
31
32 #include <asm/byteorder.h>
33 #include <linux/unaligned.h>
34
35 #include <linux/iio/buffer.h>
36 #include <linux/iio/events.h>
37 #include <linux/iio/iio.h>
38 #include <linux/iio/trigger.h>
39 #include <linux/iio/triggered_buffer.h>
40 #include <linux/iio/trigger_consumer.h>
41 #include <linux/iio/types.h>
42
43 #define HX9023S_CHIP_ID 0x1D
44 #define HX9023S_CH_NUM 5
45 #define HX9023S_POS 0x03
46 #define HX9023S_NEG 0x02
47 #define HX9023S_NOT_CONNECTED 16
48
49 #define HX9023S_GLOBAL_CTRL0 0x00
50 #define HX9023S_PRF_CFG 0x02
51 #define HX9023S_CH0_CFG_7_0 0x03
52 #define HX9023S_CH4_CFG_9_8 0x0C
53 #define HX9023S_RANGE_7_0 0x0D
54 #define HX9023S_RANGE_9_8 0x0E
55 #define HX9023S_RANGE_18_16 0x0F
56 #define HX9023S_AVG0_NOSR0_CFG 0x10
57 #define HX9023S_NOSR12_CFG 0x11
58 #define HX9023S_NOSR34_CFG 0x12
59 #define HX9023S_AVG12_CFG 0x13
60 #define HX9023S_AVG34_CFG 0x14
61 #define HX9023S_OFFSET_DAC0_7_0 0x15
62 #define HX9023S_OFFSET_DAC4_9_8 0x1E
63 #define HX9023S_SAMPLE_NUM_7_0 0x1F
64 #define HX9023S_INTEGRATION_NUM_7_0 0x21
65 #define HX9023S_CH_NUM_CFG 0x24
66 #define HX9023S_LP_ALP_4_CFG 0x29
67 #define HX9023S_LP_ALP_1_0_CFG 0x2A
68 #define HX9023S_LP_ALP_3_2_CFG 0x2B
69 #define HX9023S_UP_ALP_1_0_CFG 0x2C
70 #define HX9023S_UP_ALP_3_2_CFG 0x2D
71 #define HX9023S_DN_UP_ALP_0_4_CFG 0x2E
72 #define HX9023S_DN_ALP_2_1_CFG 0x2F
73 #define HX9023S_DN_ALP_4_3_CFG 0x30
74 #define HX9023S_RAW_BL_RD_CFG 0x38
75 #define HX9023S_INTERRUPT_CFG 0x39
76 #define HX9023S_INTERRUPT_CFG1 0x3A
77 #define HX9023S_CALI_DIFF_CFG 0x3B
78 #define HX9023S_DITHER_CFG 0x3C
79 #define HX9023S_DEVICE_ID 0x60
80 #define HX9023S_PROX_STATUS 0x6B
81 #define HX9023S_PROX_INT_HIGH_CFG 0x6C
82 #define HX9023S_PROX_INT_LOW_CFG 0x6D
83 #define HX9023S_PROX_HIGH_DIFF_CFG_CH0_0 0x80
84 #define HX9023S_PROX_LOW_DIFF_CFG_CH0_0 0x88
85 #define HX9023S_PROX_LOW_DIFF_CFG_CH3_1 0x8F
86 #define HX9023S_PROX_HIGH_DIFF_CFG_CH4_0 0x9E
87 #define HX9023S_PROX_HIGH_DIFF_CFG_CH4_1 0x9F
88 #define HX9023S_PROX_LOW_DIFF_CFG_CH4_0 0xA2
89 #define HX9023S_PROX_LOW_DIFF_CFG_CH4_1 0xA3
90 #define HX9023S_CAP_INI_CH4_0 0xB3
91 #define HX9023S_LP_DIFF_CH4_2 0xBA
92 #define HX9023S_RAW_BL_CH4_0 0xB5
93 #define HX9023S_LP_DIFF_CH4_0 0xB8
94 #define HX9023S_DSP_CONFIG_CTRL1 0xC8
95 #define HX9023S_CAP_INI_CH0_0 0xE0
96 #define HX9023S_RAW_BL_CH0_0 0xE8
97 #define HX9023S_LP_DIFF_CH0_0 0xF4
98 #define HX9023S_LP_DIFF_CH3_2 0xFF
99
100 #define HX9023S_DATA_LOCK_MASK BIT(4)
101 #define HX9023S_INTERRUPT_MASK GENMASK(9, 0)
102 #define HX9023S_PROX_DEBOUNCE_MASK GENMASK(3, 0)
103
104 #define FW_VER_OFFSET 2
105 #define FW_REG_CNT_OFFSET 3
106 #define FW_DATA_OFFSET 16
107
108 struct hx9023s_bin {
109 u16 reg_count;
110 u16 fw_size;
111 u8 fw_ver;
112 u8 data[] __counted_by(fw_size);
113 };
114
115 struct hx9023s_ch_data {
116 s16 raw; /* Raw Data*/
117 s16 lp; /* Low Pass Filter Data*/
118 s16 bl; /* Base Line Data */
119 s16 diff; /* Difference of Low Pass Data and Base Line Data */
120
121 struct {
122 unsigned int near;
123 unsigned int far;
124 } thres;
125
126 u16 dac;
127 u8 channel_positive;
128 u8 channel_negative;
129 bool sel_bl;
130 bool sel_raw;
131 bool sel_diff;
132 bool sel_lp;
133 bool enable;
134 };
135
136 struct hx9023s_data {
137 struct iio_trigger *trig;
138 struct regmap *regmap;
139 unsigned long chan_prox_stat;
140 unsigned long chan_read;
141 unsigned long chan_event;
142 unsigned long ch_en_stat;
143 unsigned long chan_in_use;
144 unsigned int prox_state_reg;
145 bool trigger_enabled;
146
147 struct {
148 __le16 channels[HX9023S_CH_NUM];
149 aligned_s64 ts;
150 } buffer;
151
152 /*
153 * Serialize access to registers below:
154 * HX9023S_PROX_INT_LOW_CFG,
155 * HX9023S_PROX_INT_HIGH_CFG,
156 * HX9023S_INTERRUPT_CFG,
157 * HX9023S_CH_NUM_CFG
158 * Serialize access to channel configuration in
159 * hx9023s_push_events and hx9023s_trigger_handler.
160 */
161 struct mutex mutex;
162 struct hx9023s_ch_data ch_data[HX9023S_CH_NUM];
163 };
164
165 static const struct reg_sequence hx9023s_reg_init_list[] = {
166 /* scan period */
167 REG_SEQ0(HX9023S_PRF_CFG, 0x17),
168
169 /* full scale of conversion phase of each channel */
170 REG_SEQ0(HX9023S_RANGE_7_0, 0x11),
171 REG_SEQ0(HX9023S_RANGE_9_8, 0x02),
172 REG_SEQ0(HX9023S_RANGE_18_16, 0x00),
173
174 /* ADC average number and OSR number of each channel */
175 REG_SEQ0(HX9023S_AVG0_NOSR0_CFG, 0x71),
176 REG_SEQ0(HX9023S_NOSR12_CFG, 0x44),
177 REG_SEQ0(HX9023S_NOSR34_CFG, 0x00),
178 REG_SEQ0(HX9023S_AVG12_CFG, 0x33),
179 REG_SEQ0(HX9023S_AVG34_CFG, 0x00),
180
181 /* sample & integration frequency of the ADC */
182 REG_SEQ0(HX9023S_SAMPLE_NUM_7_0, 0x65),
183 REG_SEQ0(HX9023S_INTEGRATION_NUM_7_0, 0x65),
184
185 /* coefficient of the first order low pass filter during each channel */
186 REG_SEQ0(HX9023S_LP_ALP_1_0_CFG, 0x22),
187 REG_SEQ0(HX9023S_LP_ALP_3_2_CFG, 0x22),
188 REG_SEQ0(HX9023S_LP_ALP_4_CFG, 0x02),
189
190 /* up coefficient of the first order low pass filter during each channel */
191 REG_SEQ0(HX9023S_UP_ALP_1_0_CFG, 0x88),
192 REG_SEQ0(HX9023S_UP_ALP_3_2_CFG, 0x88),
193 REG_SEQ0(HX9023S_DN_UP_ALP_0_4_CFG, 0x18),
194
195 /* down coefficient of the first order low pass filter during each channel */
196 REG_SEQ0(HX9023S_DN_ALP_2_1_CFG, 0x11),
197 REG_SEQ0(HX9023S_DN_ALP_4_3_CFG, 0x11),
198
199 /* selection of data for the Data Mux Register to output data */
200 REG_SEQ0(HX9023S_RAW_BL_RD_CFG, 0xF0),
201
202 /* enable the interrupt function */
203 REG_SEQ0(HX9023S_INTERRUPT_CFG, 0xFF),
204 REG_SEQ0(HX9023S_INTERRUPT_CFG1, 0x3B),
205 REG_SEQ0(HX9023S_DITHER_CFG, 0x21),
206
207 /* threshold of the offset compensation */
208 REG_SEQ0(HX9023S_CALI_DIFF_CFG, 0x07),
209
210 /* proximity persistency number(near & far) */
211 REG_SEQ0(HX9023S_PROX_INT_HIGH_CFG, 0x01),
212 REG_SEQ0(HX9023S_PROX_INT_LOW_CFG, 0x01),
213
214 /* disable the data lock */
215 REG_SEQ0(HX9023S_DSP_CONFIG_CTRL1, 0x00),
216 };
217
218 static const struct iio_event_spec hx9023s_events[] = {
219 {
220 .type = IIO_EV_TYPE_THRESH,
221 .dir = IIO_EV_DIR_RISING,
222 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
223 .mask_separate = BIT(IIO_EV_INFO_VALUE),
224 },
225 {
226 .type = IIO_EV_TYPE_THRESH,
227 .dir = IIO_EV_DIR_FALLING,
228 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
229 .mask_separate = BIT(IIO_EV_INFO_VALUE),
230
231 },
232 {
233 .type = IIO_EV_TYPE_THRESH,
234 .dir = IIO_EV_DIR_EITHER,
235 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
236 },
237 };
238
239 #define HX9023S_CHANNEL(idx) \
240 { \
241 .type = IIO_PROXIMITY, \
242 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
243 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
244 .indexed = 1, \
245 .channel = idx, \
246 .address = 0, \
247 .event_spec = hx9023s_events, \
248 .num_event_specs = ARRAY_SIZE(hx9023s_events), \
249 .scan_index = idx, \
250 .scan_type = { \
251 .sign = 's', \
252 .realbits = 16, \
253 .storagebits = 16, \
254 .endianness = IIO_BE, \
255 }, \
256 }
257
258 static const struct iio_chan_spec hx9023s_channels[] = {
259 HX9023S_CHANNEL(0),
260 HX9023S_CHANNEL(1),
261 HX9023S_CHANNEL(2),
262 HX9023S_CHANNEL(3),
263 HX9023S_CHANNEL(4),
264 IIO_CHAN_SOFT_TIMESTAMP(5),
265 };
266
267 static const unsigned int hx9023s_samp_freq_table[] = {
268 2, 2, 4, 6, 8, 10, 14, 18, 22, 26,
269 30, 34, 38, 42, 46, 50, 56, 62, 68, 74,
270 80, 90, 100, 200, 300, 400, 600, 800, 1000, 2000,
271 3000, 4000,
272 };
273
274 static const struct regmap_range hx9023s_rd_reg_ranges[] = {
275 regmap_reg_range(HX9023S_GLOBAL_CTRL0, HX9023S_LP_DIFF_CH3_2),
276 };
277
278 static const struct regmap_range hx9023s_wr_reg_ranges[] = {
279 regmap_reg_range(HX9023S_GLOBAL_CTRL0, HX9023S_LP_DIFF_CH3_2),
280 };
281
282 static const struct regmap_range hx9023s_volatile_reg_ranges[] = {
283 regmap_reg_range(HX9023S_CAP_INI_CH4_0, HX9023S_LP_DIFF_CH4_2),
284 regmap_reg_range(HX9023S_CAP_INI_CH0_0, HX9023S_LP_DIFF_CH3_2),
285 regmap_reg_range(HX9023S_PROX_STATUS, HX9023S_PROX_STATUS),
286 };
287
288 static const struct regmap_access_table hx9023s_rd_regs = {
289 .yes_ranges = hx9023s_rd_reg_ranges,
290 .n_yes_ranges = ARRAY_SIZE(hx9023s_rd_reg_ranges),
291 };
292
293 static const struct regmap_access_table hx9023s_wr_regs = {
294 .yes_ranges = hx9023s_wr_reg_ranges,
295 .n_yes_ranges = ARRAY_SIZE(hx9023s_wr_reg_ranges),
296 };
297
298 static const struct regmap_access_table hx9023s_volatile_regs = {
299 .yes_ranges = hx9023s_volatile_reg_ranges,
300 .n_yes_ranges = ARRAY_SIZE(hx9023s_volatile_reg_ranges),
301 };
302
303 static const struct regmap_config hx9023s_regmap_config = {
304 .reg_bits = 8,
305 .val_bits = 8,
306 .cache_type = REGCACHE_MAPLE,
307 .rd_table = &hx9023s_rd_regs,
308 .wr_table = &hx9023s_wr_regs,
309 .volatile_table = &hx9023s_volatile_regs,
310 };
311
hx9023s_interrupt_enable(struct hx9023s_data * data)312 static int hx9023s_interrupt_enable(struct hx9023s_data *data)
313 {
314 return regmap_update_bits(data->regmap, HX9023S_INTERRUPT_CFG,
315 HX9023S_INTERRUPT_MASK, HX9023S_INTERRUPT_MASK);
316 }
317
hx9023s_interrupt_disable(struct hx9023s_data * data)318 static int hx9023s_interrupt_disable(struct hx9023s_data *data)
319 {
320 return regmap_update_bits(data->regmap, HX9023S_INTERRUPT_CFG,
321 HX9023S_INTERRUPT_MASK, 0x00);
322 }
323
hx9023s_data_lock(struct hx9023s_data * data,bool locked)324 static int hx9023s_data_lock(struct hx9023s_data *data, bool locked)
325 {
326 if (locked)
327 return regmap_update_bits(data->regmap,
328 HX9023S_DSP_CONFIG_CTRL1,
329 HX9023S_DATA_LOCK_MASK,
330 HX9023S_DATA_LOCK_MASK);
331 else
332 return regmap_update_bits(data->regmap,
333 HX9023S_DSP_CONFIG_CTRL1,
334 HX9023S_DATA_LOCK_MASK, 0);
335 }
336
hx9023s_ch_cfg(struct hx9023s_data * data)337 static int hx9023s_ch_cfg(struct hx9023s_data *data)
338 {
339 __le16 reg_list[HX9023S_CH_NUM];
340 u8 ch_pos[HX9023S_CH_NUM];
341 u8 ch_neg[HX9023S_CH_NUM];
342 /* Bit positions corresponding to input pin connections */
343 u8 conn_cs[HX9023S_CH_NUM] = { 0, 2, 4, 6, 8 };
344 unsigned int i;
345 u16 reg;
346
347 for (i = 0; i < HX9023S_CH_NUM; i++) {
348 ch_pos[i] = data->ch_data[i].channel_positive == HX9023S_NOT_CONNECTED ?
349 HX9023S_NOT_CONNECTED : conn_cs[data->ch_data[i].channel_positive];
350 ch_neg[i] = data->ch_data[i].channel_negative == HX9023S_NOT_CONNECTED ?
351 HX9023S_NOT_CONNECTED : conn_cs[data->ch_data[i].channel_negative];
352
353 reg = (HX9023S_POS << ch_pos[i]) | (HX9023S_NEG << ch_neg[i]);
354 reg_list[i] = cpu_to_le16(reg);
355 }
356
357 return regmap_bulk_write(data->regmap, HX9023S_CH0_CFG_7_0, reg_list,
358 sizeof(reg_list));
359 }
360
hx9023s_write_far_debounce(struct hx9023s_data * data,int val)361 static int hx9023s_write_far_debounce(struct hx9023s_data *data, int val)
362 {
363 guard(mutex)(&data->mutex);
364 return regmap_update_bits(data->regmap, HX9023S_PROX_INT_LOW_CFG,
365 HX9023S_PROX_DEBOUNCE_MASK,
366 FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, val));
367 }
368
hx9023s_write_near_debounce(struct hx9023s_data * data,int val)369 static int hx9023s_write_near_debounce(struct hx9023s_data *data, int val)
370 {
371 guard(mutex)(&data->mutex);
372 return regmap_update_bits(data->regmap, HX9023S_PROX_INT_HIGH_CFG,
373 HX9023S_PROX_DEBOUNCE_MASK,
374 FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, val));
375 }
376
hx9023s_read_far_debounce(struct hx9023s_data * data,int * val)377 static int hx9023s_read_far_debounce(struct hx9023s_data *data, int *val)
378 {
379 int ret;
380
381 ret = regmap_read(data->regmap, HX9023S_PROX_INT_LOW_CFG, val);
382 if (ret)
383 return ret;
384
385 *val = FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, *val);
386
387 return IIO_VAL_INT;
388 }
389
hx9023s_read_near_debounce(struct hx9023s_data * data,int * val)390 static int hx9023s_read_near_debounce(struct hx9023s_data *data, int *val)
391 {
392 int ret;
393
394 ret = regmap_read(data->regmap, HX9023S_PROX_INT_HIGH_CFG, val);
395 if (ret)
396 return ret;
397
398 *val = FIELD_GET(HX9023S_PROX_DEBOUNCE_MASK, *val);
399
400 return IIO_VAL_INT;
401 }
402
hx9023s_get_thres_near(struct hx9023s_data * data,u8 ch,int * val)403 static int hx9023s_get_thres_near(struct hx9023s_data *data, u8 ch, int *val)
404 {
405 int ret;
406 __le16 buf;
407 unsigned int reg, tmp;
408
409 reg = (ch == 4) ? HX9023S_PROX_HIGH_DIFF_CFG_CH4_0 :
410 HX9023S_PROX_HIGH_DIFF_CFG_CH0_0 + (ch * 2);
411
412 ret = regmap_bulk_read(data->regmap, reg, &buf, sizeof(buf));
413 if (ret)
414 return ret;
415
416 tmp = (le16_to_cpu(buf) & GENMASK(9, 0)) * 32;
417 data->ch_data[ch].thres.near = tmp;
418 *val = tmp;
419
420 return IIO_VAL_INT;
421 }
422
hx9023s_get_thres_far(struct hx9023s_data * data,u8 ch,int * val)423 static int hx9023s_get_thres_far(struct hx9023s_data *data, u8 ch, int *val)
424 {
425 int ret;
426 __le16 buf;
427 unsigned int reg, tmp;
428
429 reg = (ch == 4) ? HX9023S_PROX_LOW_DIFF_CFG_CH4_0 :
430 HX9023S_PROX_LOW_DIFF_CFG_CH0_0 + (ch * 2);
431
432 ret = regmap_bulk_read(data->regmap, reg, &buf, sizeof(buf));
433 if (ret)
434 return ret;
435
436 tmp = (le16_to_cpu(buf) & GENMASK(9, 0)) * 32;
437 data->ch_data[ch].thres.far = tmp;
438 *val = tmp;
439
440 return IIO_VAL_INT;
441 }
442
hx9023s_set_thres_near(struct hx9023s_data * data,u8 ch,int val)443 static int hx9023s_set_thres_near(struct hx9023s_data *data, u8 ch, int val)
444 {
445 __le16 val_le16 = cpu_to_le16((val / 32) & GENMASK(9, 0));
446 unsigned int reg;
447
448 data->ch_data[ch].thres.near = ((val / 32) & GENMASK(9, 0)) * 32;
449 reg = (ch == 4) ? HX9023S_PROX_HIGH_DIFF_CFG_CH4_0 :
450 HX9023S_PROX_HIGH_DIFF_CFG_CH0_0 + (ch * 2);
451
452 return regmap_bulk_write(data->regmap, reg, &val_le16, sizeof(val_le16));
453 }
454
hx9023s_set_thres_far(struct hx9023s_data * data,u8 ch,int val)455 static int hx9023s_set_thres_far(struct hx9023s_data *data, u8 ch, int val)
456 {
457 __le16 val_le16 = cpu_to_le16((val / 32) & GENMASK(9, 0));
458 unsigned int reg;
459
460 data->ch_data[ch].thres.far = ((val / 32) & GENMASK(9, 0)) * 32;
461 reg = (ch == 4) ? HX9023S_PROX_LOW_DIFF_CFG_CH4_0 :
462 HX9023S_PROX_LOW_DIFF_CFG_CH0_0 + (ch * 2);
463
464 return regmap_bulk_write(data->regmap, reg, &val_le16, sizeof(val_le16));
465 }
466
hx9023s_get_prox_state(struct hx9023s_data * data)467 static int hx9023s_get_prox_state(struct hx9023s_data *data)
468 {
469 return regmap_read(data->regmap, HX9023S_PROX_STATUS, &data->prox_state_reg);
470 }
471
hx9023s_data_select(struct hx9023s_data * data)472 static int hx9023s_data_select(struct hx9023s_data *data)
473 {
474 int ret;
475 unsigned int i, buf;
476 unsigned long tmp;
477
478 ret = regmap_read(data->regmap, HX9023S_RAW_BL_RD_CFG, &buf);
479 if (ret)
480 return ret;
481
482 tmp = buf;
483 for (i = 0; i < 4; i++) {
484 data->ch_data[i].sel_diff = test_bit(i, &tmp);
485 data->ch_data[i].sel_lp = !data->ch_data[i].sel_diff;
486 data->ch_data[i].sel_bl = test_bit(i + 4, &tmp);
487 data->ch_data[i].sel_raw = !data->ch_data[i].sel_bl;
488 }
489
490 ret = regmap_read(data->regmap, HX9023S_INTERRUPT_CFG1, &buf);
491 if (ret)
492 return ret;
493
494 tmp = buf;
495 data->ch_data[4].sel_diff = test_bit(2, &tmp);
496 data->ch_data[4].sel_lp = !data->ch_data[4].sel_diff;
497 data->ch_data[4].sel_bl = test_bit(3, &tmp);
498 data->ch_data[4].sel_raw = !data->ch_data[4].sel_bl;
499
500 return 0;
501 }
502
hx9023s_sample(struct hx9023s_data * data)503 static int hx9023s_sample(struct hx9023s_data *data)
504 {
505 int ret;
506 unsigned int i;
507 u8 buf[HX9023S_CH_NUM * 3];
508 u16 value;
509
510 ret = hx9023s_data_lock(data, true);
511 if (ret)
512 return ret;
513
514 ret = hx9023s_data_select(data);
515 if (ret)
516 goto err;
517
518 /* 3 bytes for each of channels 0 to 3 which have contiguous registers */
519 ret = regmap_bulk_read(data->regmap, HX9023S_RAW_BL_CH0_0, buf, 12);
520 if (ret)
521 goto err;
522
523 /* 3 bytes for channel 4 */
524 ret = regmap_bulk_read(data->regmap, HX9023S_RAW_BL_CH4_0, buf + 12, 3);
525 if (ret)
526 goto err;
527
528 for (i = 0; i < HX9023S_CH_NUM; i++) {
529 value = get_unaligned_le16(&buf[i * 3 + 1]);
530 data->ch_data[i].raw = 0;
531 data->ch_data[i].bl = 0;
532 if (data->ch_data[i].sel_raw)
533 data->ch_data[i].raw = value;
534 if (data->ch_data[i].sel_bl)
535 data->ch_data[i].bl = value;
536 }
537
538 /* 3 bytes for each of channels 0 to 3 which have contiguous registers */
539 ret = regmap_bulk_read(data->regmap, HX9023S_LP_DIFF_CH0_0, buf, 12);
540 if (ret)
541 goto err;
542
543 /* 3 bytes for channel 4 */
544 ret = regmap_bulk_read(data->regmap, HX9023S_LP_DIFF_CH4_0, buf + 12, 3);
545 if (ret)
546 goto err;
547
548 for (i = 0; i < HX9023S_CH_NUM; i++) {
549 value = get_unaligned_le16(&buf[i * 3 + 1]);
550 data->ch_data[i].lp = 0;
551 data->ch_data[i].diff = 0;
552 if (data->ch_data[i].sel_lp)
553 data->ch_data[i].lp = value;
554 if (data->ch_data[i].sel_diff)
555 data->ch_data[i].diff = value;
556 }
557
558 for (i = 0; i < HX9023S_CH_NUM; i++) {
559 if (data->ch_data[i].sel_lp && data->ch_data[i].sel_bl)
560 data->ch_data[i].diff = data->ch_data[i].lp - data->ch_data[i].bl;
561 }
562
563 /* 2 bytes for each of channels 0 to 4 which have contiguous registers */
564 ret = regmap_bulk_read(data->regmap, HX9023S_OFFSET_DAC0_7_0, buf, 10);
565 if (ret)
566 goto err;
567
568 for (i = 0; i < HX9023S_CH_NUM; i++) {
569 value = get_unaligned_le16(&buf[i * 2]);
570 value = FIELD_GET(GENMASK(11, 0), value);
571 data->ch_data[i].dac = value;
572 }
573
574 err:
575 return hx9023s_data_lock(data, false);
576 }
577
hx9023s_ch_en(struct hx9023s_data * data,u8 ch_id,bool en)578 static int hx9023s_ch_en(struct hx9023s_data *data, u8 ch_id, bool en)
579 {
580 int ret;
581 unsigned int buf;
582
583 ret = regmap_read(data->regmap, HX9023S_CH_NUM_CFG, &buf);
584 if (ret)
585 return ret;
586
587 data->ch_en_stat = buf;
588 if (en && data->ch_en_stat == 0)
589 data->prox_state_reg = 0;
590
591 data->ch_data[ch_id].enable = en;
592 __assign_bit(ch_id, &data->ch_en_stat, en);
593
594 return regmap_write(data->regmap, HX9023S_CH_NUM_CFG, data->ch_en_stat);
595 }
596
hx9023s_property_get(struct hx9023s_data * data)597 static int hx9023s_property_get(struct hx9023s_data *data)
598 {
599 struct device *dev = regmap_get_device(data->regmap);
600 u32 array[2];
601 u32 i, reg, temp;
602 int ret;
603
604 data->chan_in_use = 0;
605 for (i = 0; i < HX9023S_CH_NUM; i++) {
606 data->ch_data[i].channel_positive = HX9023S_NOT_CONNECTED;
607 data->ch_data[i].channel_negative = HX9023S_NOT_CONNECTED;
608 }
609
610 device_for_each_child_node_scoped(dev, child) {
611 ret = fwnode_property_read_u32(child, "reg", ®);
612 if (ret || reg >= HX9023S_CH_NUM)
613 return dev_err_probe(dev, ret < 0 ? ret : -EINVAL,
614 "Failed to read reg\n");
615 __set_bit(reg, &data->chan_in_use);
616
617 ret = fwnode_property_read_u32(child, "single-channel", &temp);
618 if (ret == 0) {
619 data->ch_data[reg].channel_positive = temp;
620 data->ch_data[reg].channel_negative = HX9023S_NOT_CONNECTED;
621 } else {
622 ret = fwnode_property_read_u32_array(child, "diff-channels",
623 array, ARRAY_SIZE(array));
624 if (ret == 0) {
625 data->ch_data[reg].channel_positive = array[0];
626 data->ch_data[reg].channel_negative = array[1];
627 } else {
628 return dev_err_probe(dev, ret,
629 "Property read failed: %d\n",
630 reg);
631 }
632 }
633 }
634
635 return 0;
636 }
637
hx9023s_update_chan_en(struct hx9023s_data * data,unsigned long chan_read,unsigned long chan_event)638 static int hx9023s_update_chan_en(struct hx9023s_data *data,
639 unsigned long chan_read,
640 unsigned long chan_event)
641 {
642 unsigned int i;
643 unsigned long channels = chan_read | chan_event;
644
645 if ((data->chan_read | data->chan_event) != channels) {
646 for_each_set_bit(i, &channels, HX9023S_CH_NUM)
647 hx9023s_ch_en(data, i, test_bit(i, &data->chan_in_use));
648 for_each_clear_bit(i, &channels, HX9023S_CH_NUM)
649 hx9023s_ch_en(data, i, false);
650 }
651
652 data->chan_read = chan_read;
653 data->chan_event = chan_event;
654
655 return 0;
656 }
657
hx9023s_get_proximity(struct hx9023s_data * data,const struct iio_chan_spec * chan,int * val)658 static int hx9023s_get_proximity(struct hx9023s_data *data,
659 const struct iio_chan_spec *chan,
660 int *val)
661 {
662 int ret;
663
664 ret = hx9023s_sample(data);
665 if (ret)
666 return ret;
667
668 ret = hx9023s_get_prox_state(data);
669 if (ret)
670 return ret;
671
672 *val = data->ch_data[chan->channel].diff;
673 return IIO_VAL_INT;
674 }
675
hx9023s_get_samp_freq(struct hx9023s_data * data,int * val,int * val2)676 static int hx9023s_get_samp_freq(struct hx9023s_data *data, int *val, int *val2)
677 {
678 int ret;
679 unsigned int odr, index;
680
681 ret = regmap_read(data->regmap, HX9023S_PRF_CFG, &index);
682 if (ret)
683 return ret;
684
685 odr = hx9023s_samp_freq_table[index];
686 *val = KILO / odr;
687 *val2 = div_u64((KILO % odr) * MICRO, odr);
688
689 return IIO_VAL_INT_PLUS_MICRO;
690 }
691
hx9023s_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)692 static int hx9023s_read_raw(struct iio_dev *indio_dev,
693 const struct iio_chan_spec *chan,
694 int *val, int *val2, long mask)
695 {
696 struct hx9023s_data *data = iio_priv(indio_dev);
697 int ret;
698
699 if (chan->type != IIO_PROXIMITY)
700 return -EINVAL;
701
702 switch (mask) {
703 case IIO_CHAN_INFO_RAW:
704 if (!iio_device_claim_direct(indio_dev))
705 return -EBUSY;
706
707 ret = hx9023s_get_proximity(data, chan, val);
708 iio_device_release_direct(indio_dev);
709 return ret;
710 case IIO_CHAN_INFO_SAMP_FREQ:
711 return hx9023s_get_samp_freq(data, val, val2);
712 default:
713 return -EINVAL;
714 }
715 }
716
hx9023s_set_samp_freq(struct hx9023s_data * data,int val,int val2)717 static int hx9023s_set_samp_freq(struct hx9023s_data *data, int val, int val2)
718 {
719 struct device *dev = regmap_get_device(data->regmap);
720 unsigned int i, period_ms;
721
722 period_ms = div_u64(NANO, (val * MEGA + val2));
723
724 for (i = 0; i < ARRAY_SIZE(hx9023s_samp_freq_table); i++) {
725 if (period_ms == hx9023s_samp_freq_table[i])
726 break;
727 }
728 if (i == ARRAY_SIZE(hx9023s_samp_freq_table)) {
729 dev_err(dev, "Period:%dms NOT found!\n", period_ms);
730 return -EINVAL;
731 }
732
733 return regmap_write(data->regmap, HX9023S_PRF_CFG, i);
734 }
735
hx9023s_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long mask)736 static int hx9023s_write_raw(struct iio_dev *indio_dev,
737 const struct iio_chan_spec *chan,
738 int val, int val2, long mask)
739 {
740 struct hx9023s_data *data = iio_priv(indio_dev);
741
742 if (chan->type != IIO_PROXIMITY)
743 return -EINVAL;
744
745 if (mask != IIO_CHAN_INFO_SAMP_FREQ)
746 return -EINVAL;
747
748 return hx9023s_set_samp_freq(data, val, val2);
749 }
750
hx9023s_irq_handler(int irq,void * private)751 static irqreturn_t hx9023s_irq_handler(int irq, void *private)
752 {
753 struct iio_dev *indio_dev = private;
754 struct hx9023s_data *data = iio_priv(indio_dev);
755
756 if (data->trigger_enabled)
757 iio_trigger_poll(data->trig);
758
759 return IRQ_WAKE_THREAD;
760 }
761
hx9023s_push_events(struct iio_dev * indio_dev)762 static void hx9023s_push_events(struct iio_dev *indio_dev)
763 {
764 struct hx9023s_data *data = iio_priv(indio_dev);
765 s64 timestamp = iio_get_time_ns(indio_dev);
766 unsigned long prox_changed;
767 unsigned int chan;
768 int ret;
769
770 ret = hx9023s_sample(data);
771 if (ret)
772 return;
773
774 ret = hx9023s_get_prox_state(data);
775 if (ret)
776 return;
777
778 prox_changed = (data->chan_prox_stat ^ data->prox_state_reg) & data->chan_event;
779 for_each_set_bit(chan, &prox_changed, HX9023S_CH_NUM) {
780 unsigned int dir;
781
782 dir = (data->prox_state_reg & BIT(chan)) ?
783 IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
784
785 iio_push_event(indio_dev,
786 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan,
787 IIO_EV_TYPE_THRESH, dir),
788 timestamp);
789 }
790 data->chan_prox_stat = data->prox_state_reg;
791 }
792
hx9023s_irq_thread_handler(int irq,void * private)793 static irqreturn_t hx9023s_irq_thread_handler(int irq, void *private)
794 {
795 struct iio_dev *indio_dev = private;
796 struct hx9023s_data *data = iio_priv(indio_dev);
797
798 guard(mutex)(&data->mutex);
799 hx9023s_push_events(indio_dev);
800
801 return IRQ_HANDLED;
802 }
803
hx9023s_read_event_val(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)804 static int hx9023s_read_event_val(struct iio_dev *indio_dev,
805 const struct iio_chan_spec *chan,
806 enum iio_event_type type,
807 enum iio_event_direction dir,
808 enum iio_event_info info, int *val, int *val2)
809 {
810 struct hx9023s_data *data = iio_priv(indio_dev);
811
812 if (chan->type != IIO_PROXIMITY)
813 return -EINVAL;
814
815 switch (info) {
816 case IIO_EV_INFO_VALUE:
817 switch (dir) {
818 case IIO_EV_DIR_RISING:
819 return hx9023s_get_thres_far(data, chan->channel, val);
820 case IIO_EV_DIR_FALLING:
821 return hx9023s_get_thres_near(data, chan->channel, val);
822 default:
823 return -EINVAL;
824 }
825 case IIO_EV_INFO_PERIOD:
826 switch (dir) {
827 case IIO_EV_DIR_RISING:
828 return hx9023s_read_far_debounce(data, val);
829 case IIO_EV_DIR_FALLING:
830 return hx9023s_read_near_debounce(data, val);
831 default:
832 return -EINVAL;
833 }
834 default:
835 return -EINVAL;
836 }
837 }
838
hx9023s_write_event_val(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)839 static int hx9023s_write_event_val(struct iio_dev *indio_dev,
840 const struct iio_chan_spec *chan,
841 enum iio_event_type type,
842 enum iio_event_direction dir,
843 enum iio_event_info info, int val, int val2)
844 {
845 struct hx9023s_data *data = iio_priv(indio_dev);
846
847 if (chan->type != IIO_PROXIMITY)
848 return -EINVAL;
849
850 switch (info) {
851 case IIO_EV_INFO_VALUE:
852 switch (dir) {
853 case IIO_EV_DIR_RISING:
854 return hx9023s_set_thres_far(data, chan->channel, val);
855 case IIO_EV_DIR_FALLING:
856 return hx9023s_set_thres_near(data, chan->channel, val);
857 default:
858 return -EINVAL;
859 }
860 case IIO_EV_INFO_PERIOD:
861 switch (dir) {
862 case IIO_EV_DIR_RISING:
863 return hx9023s_write_far_debounce(data, val);
864 case IIO_EV_DIR_FALLING:
865 return hx9023s_write_near_debounce(data, val);
866 default:
867 return -EINVAL;
868 }
869 default:
870 return -EINVAL;
871 }
872 }
873
hx9023s_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)874 static int hx9023s_read_event_config(struct iio_dev *indio_dev,
875 const struct iio_chan_spec *chan,
876 enum iio_event_type type,
877 enum iio_event_direction dir)
878 {
879 struct hx9023s_data *data = iio_priv(indio_dev);
880
881 return test_bit(chan->channel, &data->chan_event);
882 }
883
hx9023s_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)884 static int hx9023s_write_event_config(struct iio_dev *indio_dev,
885 const struct iio_chan_spec *chan,
886 enum iio_event_type type,
887 enum iio_event_direction dir,
888 bool state)
889 {
890 struct hx9023s_data *data = iio_priv(indio_dev);
891
892 if (test_bit(chan->channel, &data->chan_in_use)) {
893 hx9023s_ch_en(data, chan->channel, state);
894 __assign_bit(chan->channel, &data->chan_event,
895 data->ch_data[chan->channel].enable);
896 }
897
898 return 0;
899 }
900
901 static const struct iio_info hx9023s_info = {
902 .read_raw = hx9023s_read_raw,
903 .write_raw = hx9023s_write_raw,
904 .read_event_value = hx9023s_read_event_val,
905 .write_event_value = hx9023s_write_event_val,
906 .read_event_config = hx9023s_read_event_config,
907 .write_event_config = hx9023s_write_event_config,
908 };
909
hx9023s_set_trigger_state(struct iio_trigger * trig,bool state)910 static int hx9023s_set_trigger_state(struct iio_trigger *trig, bool state)
911 {
912 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
913 struct hx9023s_data *data = iio_priv(indio_dev);
914
915 guard(mutex)(&data->mutex);
916 if (state)
917 hx9023s_interrupt_enable(data);
918 else if (!data->chan_read)
919 hx9023s_interrupt_disable(data);
920 data->trigger_enabled = state;
921
922 return 0;
923 }
924
925 static const struct iio_trigger_ops hx9023s_trigger_ops = {
926 .set_trigger_state = hx9023s_set_trigger_state,
927 };
928
hx9023s_trigger_handler(int irq,void * private)929 static irqreturn_t hx9023s_trigger_handler(int irq, void *private)
930 {
931 struct iio_poll_func *pf = private;
932 struct iio_dev *indio_dev = pf->indio_dev;
933 struct hx9023s_data *data = iio_priv(indio_dev);
934 struct device *dev = regmap_get_device(data->regmap);
935 unsigned int bit, index, i = 0;
936 int ret;
937
938 guard(mutex)(&data->mutex);
939 ret = hx9023s_sample(data);
940 if (ret) {
941 dev_warn(dev, "sampling failed\n");
942 goto out;
943 }
944
945 ret = hx9023s_get_prox_state(data);
946 if (ret) {
947 dev_warn(dev, "get prox failed\n");
948 goto out;
949 }
950
951 iio_for_each_active_channel(indio_dev, bit) {
952 index = indio_dev->channels[bit].channel;
953 data->buffer.channels[i++] = cpu_to_le16(data->ch_data[index].diff);
954 }
955
956 iio_push_to_buffers_with_ts(indio_dev, &data->buffer,
957 sizeof(data->buffer), pf->timestamp);
958
959 out:
960 iio_trigger_notify_done(indio_dev->trig);
961
962 return IRQ_HANDLED;
963 }
964
hx9023s_buffer_preenable(struct iio_dev * indio_dev)965 static int hx9023s_buffer_preenable(struct iio_dev *indio_dev)
966 {
967 struct hx9023s_data *data = iio_priv(indio_dev);
968 unsigned long channels = 0;
969 unsigned int bit;
970
971 guard(mutex)(&data->mutex);
972 iio_for_each_active_channel(indio_dev, bit)
973 __set_bit(indio_dev->channels[bit].channel, &channels);
974
975 hx9023s_update_chan_en(data, channels, data->chan_event);
976
977 return 0;
978 }
979
hx9023s_buffer_postdisable(struct iio_dev * indio_dev)980 static int hx9023s_buffer_postdisable(struct iio_dev *indio_dev)
981 {
982 struct hx9023s_data *data = iio_priv(indio_dev);
983
984 guard(mutex)(&data->mutex);
985 hx9023s_update_chan_en(data, 0, data->chan_event);
986
987 return 0;
988 }
989
990 static const struct iio_buffer_setup_ops hx9023s_buffer_setup_ops = {
991 .preenable = hx9023s_buffer_preenable,
992 .postdisable = hx9023s_buffer_postdisable,
993 };
994
hx9023s_id_check(struct iio_dev * indio_dev)995 static int hx9023s_id_check(struct iio_dev *indio_dev)
996 {
997 struct hx9023s_data *data = iio_priv(indio_dev);
998 struct device *dev = regmap_get_device(data->regmap);
999 unsigned int id;
1000 int ret;
1001
1002 ret = regmap_read(data->regmap, HX9023S_DEVICE_ID, &id);
1003 if (ret)
1004 return ret;
1005
1006 if (id != HX9023S_CHIP_ID)
1007 dev_warn(dev, "Unexpected chip ID, assuming compatible\n");
1008
1009 return 0;
1010 }
1011
hx9023s_bin_load(struct hx9023s_data * data,struct hx9023s_bin * bin)1012 static int hx9023s_bin_load(struct hx9023s_data *data, struct hx9023s_bin *bin)
1013 {
1014 u8 *cfg_start = bin->data + FW_DATA_OFFSET;
1015 u8 addr, val;
1016 u16 i;
1017 int ret;
1018
1019 for (i = 0; i < bin->reg_count; i++) {
1020 addr = cfg_start[i * 2];
1021 val = cfg_start[i * 2 + 1];
1022 ret = regmap_write(data->regmap, addr, val);
1023 if (ret < 0)
1024 return ret;
1025 }
1026
1027 return 0;
1028 }
1029
hx9023s_send_cfg(const struct firmware * fw,struct hx9023s_data * data)1030 static int hx9023s_send_cfg(const struct firmware *fw, struct hx9023s_data *data)
1031 {
1032 struct hx9023s_bin *bin __free(kfree) =
1033 kzalloc(fw->size + sizeof(*bin), GFP_KERNEL);
1034 if (!bin)
1035 return -ENOMEM;
1036
1037 memcpy(bin->data, fw->data, fw->size);
1038
1039 bin->fw_size = fw->size;
1040 bin->fw_ver = bin->data[FW_VER_OFFSET];
1041 bin->reg_count = get_unaligned_le16(bin->data + FW_REG_CNT_OFFSET);
1042
1043 release_firmware(fw);
1044
1045 return hx9023s_bin_load(data, bin);
1046 }
1047
hx9023s_cfg_update(const struct firmware * fw,void * context)1048 static void hx9023s_cfg_update(const struct firmware *fw, void *context)
1049 {
1050 struct hx9023s_data *data = context;
1051 struct device *dev = regmap_get_device(data->regmap);
1052 int ret;
1053
1054 if (!fw || !fw->data) {
1055 dev_warn(dev, "No firmware\n");
1056 goto no_fw;
1057 }
1058
1059 ret = hx9023s_send_cfg(fw, data);
1060 if (ret) {
1061 dev_warn(dev, "Firmware update failed: %d\n", ret);
1062 goto no_fw;
1063 }
1064
1065 ret = regcache_sync(data->regmap);
1066 if (ret)
1067 dev_err(dev, "regcache sync failed\n");
1068
1069 return;
1070
1071 no_fw:
1072 ret = regmap_multi_reg_write(data->regmap, hx9023s_reg_init_list,
1073 ARRAY_SIZE(hx9023s_reg_init_list));
1074 if (ret) {
1075 dev_err(dev, "Error loading default configuration\n");
1076 return;
1077 }
1078
1079 ret = regcache_sync(data->regmap);
1080 if (ret)
1081 dev_err(dev, "regcache sync failed\n");
1082 }
1083
hx9023s_probe(struct i2c_client * client)1084 static int hx9023s_probe(struct i2c_client *client)
1085 {
1086 struct device *dev = &client->dev;
1087 struct iio_dev *indio_dev;
1088 struct hx9023s_data *data;
1089 int ret;
1090
1091 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1092 if (!indio_dev)
1093 return -ENOMEM;
1094
1095 data = iio_priv(indio_dev);
1096 mutex_init(&data->mutex);
1097
1098 data->regmap = devm_regmap_init_i2c(client, &hx9023s_regmap_config);
1099 if (IS_ERR(data->regmap))
1100 return dev_err_probe(dev, PTR_ERR(data->regmap),
1101 "regmap init failed\n");
1102
1103 ret = hx9023s_property_get(data);
1104 if (ret)
1105 return dev_err_probe(dev, ret, "dts phase failed\n");
1106
1107 ret = devm_regulator_get_enable(dev, "vdd");
1108 if (ret)
1109 return dev_err_probe(dev, ret, "regulator get failed\n");
1110
1111 ret = hx9023s_id_check(indio_dev);
1112 if (ret)
1113 return dev_err_probe(dev, ret, "id check failed\n");
1114
1115 indio_dev->name = "hx9023s";
1116 indio_dev->channels = hx9023s_channels;
1117 indio_dev->num_channels = ARRAY_SIZE(hx9023s_channels);
1118 indio_dev->info = &hx9023s_info;
1119 indio_dev->modes = INDIO_DIRECT_MODE;
1120 i2c_set_clientdata(client, indio_dev);
1121
1122 ret = hx9023s_ch_cfg(data);
1123 if (ret)
1124 return dev_err_probe(dev, ret, "channel config failed\n");
1125
1126 ret = request_firmware_nowait(THIS_MODULE, true, "hx9023s.bin", dev,
1127 GFP_KERNEL, data, hx9023s_cfg_update);
1128 if (ret)
1129 return dev_err_probe(dev, ret, "reg config failed\n");
1130
1131 if (client->irq) {
1132 ret = devm_request_threaded_irq(dev, client->irq,
1133 hx9023s_irq_handler,
1134 hx9023s_irq_thread_handler,
1135 IRQF_ONESHOT,
1136 "hx9023s_event", indio_dev);
1137 if (ret)
1138 return dev_err_probe(dev, ret, "irq request failed\n");
1139
1140 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1141 indio_dev->name,
1142 iio_device_id(indio_dev));
1143 if (!data->trig)
1144 return dev_err_probe(dev, -ENOMEM,
1145 "iio trigger alloc failed\n");
1146
1147 data->trig->ops = &hx9023s_trigger_ops;
1148 iio_trigger_set_drvdata(data->trig, indio_dev);
1149
1150 ret = devm_iio_trigger_register(dev, data->trig);
1151 if (ret)
1152 return dev_err_probe(dev, ret,
1153 "iio trigger register failed\n");
1154 }
1155
1156 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1157 iio_pollfunc_store_time,
1158 hx9023s_trigger_handler,
1159 &hx9023s_buffer_setup_ops);
1160 if (ret)
1161 return dev_err_probe(dev, ret,
1162 "iio triggered buffer setup failed\n");
1163
1164 return devm_iio_device_register(dev, indio_dev);
1165 }
1166
hx9023s_suspend(struct device * dev)1167 static int hx9023s_suspend(struct device *dev)
1168 {
1169 struct hx9023s_data *data = iio_priv(dev_get_drvdata(dev));
1170
1171 guard(mutex)(&data->mutex);
1172 hx9023s_interrupt_disable(data);
1173
1174 return 0;
1175 }
1176
hx9023s_resume(struct device * dev)1177 static int hx9023s_resume(struct device *dev)
1178 {
1179 struct hx9023s_data *data = iio_priv(dev_get_drvdata(dev));
1180
1181 guard(mutex)(&data->mutex);
1182 if (data->trigger_enabled)
1183 hx9023s_interrupt_enable(data);
1184
1185 return 0;
1186 }
1187
1188 static DEFINE_SIMPLE_DEV_PM_OPS(hx9023s_pm_ops, hx9023s_suspend,
1189 hx9023s_resume);
1190
1191 static const struct of_device_id hx9023s_of_match[] = {
1192 { .compatible = "tyhx,hx9023s" },
1193 { }
1194 };
1195 MODULE_DEVICE_TABLE(of, hx9023s_of_match);
1196
1197 static const struct i2c_device_id hx9023s_id[] = {
1198 { "hx9023s" },
1199 { }
1200 };
1201 MODULE_DEVICE_TABLE(i2c, hx9023s_id);
1202
1203 static struct i2c_driver hx9023s_driver = {
1204 .driver = {
1205 .name = "hx9023s",
1206 .of_match_table = hx9023s_of_match,
1207 .pm = &hx9023s_pm_ops,
1208
1209 /*
1210 * The I2C operations in hx9023s_reg_init() and hx9023s_ch_cfg()
1211 * are time-consuming. Prefer async so we don't delay boot
1212 * if we're builtin to the kernel.
1213 */
1214 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1215 },
1216 .probe = hx9023s_probe,
1217 .id_table = hx9023s_id,
1218 };
1219 module_i2c_driver(hx9023s_driver);
1220
1221 MODULE_AUTHOR("Yasin Lee <yasin.lee.x@gmail.com>");
1222 MODULE_DESCRIPTION("Driver for TYHX HX9023S SAR sensor");
1223 MODULE_LICENSE("GPL");
1224