1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 14 ** 15 ** Redistribution and use in source and binary forms,with or without 16 ** modification,are permitted provided that the following conditions 17 ** are met: 18 ** 1. Redistributions of source code must retain the above copyright 19 ** notice,this list of conditions and the following disclaimer. 20 ** 2. Redistributions in binary form must reproduce the above copyright 21 ** notice,this list of conditions and the following disclaimer in the 22 ** documentation and/or other materials provided with the distribution. 23 ** 3. The name of the author may not be used to endorse or promote products 24 ** derived from this software without specific prior written permission. 25 ** 26 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 28 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 30 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 31 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 33 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 34 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 35 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 ************************************************************************** 37 */ 38 #define ARCMSR_SCSI_INITIATOR_ID 255 39 #define ARCMSR_DEV_SECTOR_SIZE 512 40 #define ARCMSR_MAX_XFER_SECTORS 4096 41 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 42 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 43 #define ARCMSR_VIRTUAL_DEVICE_ID (ARCMSR_MAX_TARGETID - 1) 44 #define ARCMSR_MAX_CHIPTYPE_NUM 4 45 #define ARCMSR_MAX_OUTSTANDING_CMD 256 46 #define ARCMSR_MAX_START_JOB 256 47 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 48 #define ARCMSR_MAX_FREESRB_NUM 384 49 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 50 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 51 #define ARCMSR_MAX_ADAPTER 4 52 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 53 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 54 #define ARCMSR_MAX_HBD_POSTQUEUE 256 55 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 56 #define ARCMSR_NUM_MSIX_VECTORS 4 57 /* 58 ********************************************************************* 59 */ 60 #ifndef TRUE 61 #define TRUE 1 62 #endif 63 #ifndef FALSE 64 #define FALSE 0 65 #endif 66 #ifndef INTR_ENTROPY 67 # define INTR_ENTROPY 0 68 #endif 69 70 #ifndef offsetof 71 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 72 #endif 73 74 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 75 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 76 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 77 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 78 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 79 #define arcmsr_htole32(x) htole32(x) 80 typedef struct mtx arcmsr_lock_t; 81 82 /* 83 ********************************************************************************** 84 ** 85 ********************************************************************************** 86 */ 87 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 88 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 91 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 92 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 93 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 94 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 95 #define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 97 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 98 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 99 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 100 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 101 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 102 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 103 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 104 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 105 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 106 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 107 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 108 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 109 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 110 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 111 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 112 #define PCI_DEVICE_ID_ARECA_1883 0x1883 /* Device ID */ 113 #define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */ 114 115 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 116 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 117 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */ 118 #define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */ 119 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 120 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 121 #define ARECA_SUB_DEV_ID_1214 0x1214 /* Subsystem Device ID */ 122 #define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */ 123 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 124 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 125 #define ARECA_SUB_DEV_ID_1224 0x1224 /* Subsystem Device ID */ 126 #define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */ 127 128 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 129 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 130 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 131 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 132 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 133 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 134 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 135 #define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */ 136 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 137 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 138 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 139 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 140 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 141 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 142 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 143 #define PCIDevVenIDARC1224 0x122417D3 /* Vendor Device ID */ 144 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 145 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 146 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 147 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 148 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 149 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 150 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 151 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 152 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 153 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 154 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 155 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 156 #define PCIDevVenIDARC1883 0x188317D3 /* Vendor Device ID */ 157 #define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */ 158 #define PCIDevVenIDARC1886_0 0x188617D3 /* Vendor Device ID */ 159 #define PCIDevVenIDARC1886_ 0x188917D3 /* Vendor Device ID */ 160 #define PCIDevVenIDARC1886 0x188A17D3 /* Vendor Device ID */ 161 162 #ifndef PCIR_BARS 163 #define PCIR_BARS 0x10 164 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 165 #endif 166 167 #define PCI_BASE_ADDR0 0x10 168 #define PCI_BASE_ADDR1 0x14 169 #define PCI_BASE_ADDR2 0x18 170 #define PCI_BASE_ADDR3 0x1C 171 #define PCI_BASE_ADDR4 0x20 172 #define PCI_BASE_ADDR5 0x24 173 /* 174 ********************************************************************************** 175 ** 176 ********************************************************************************** 177 */ 178 #define ARCMSR_SCSICMD_IOCTL 0x77 179 #define ARCMSR_CDEVSW_IOCTL 0x88 180 #define ARCMSR_MESSAGE_FAIL 0x0001 181 #define ARCMSR_MESSAGE_SUCCESS 0x0000 182 /* 183 ********************************************************************************** 184 ** 185 ********************************************************************************** 186 */ 187 #define arcmsr_ccbsrb_ptr spriv_ptr0 188 #define arcmsr_ccbacb_ptr spriv_ptr1 189 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 190 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 191 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 192 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 193 /* 194 ************************************************************************** 195 ************************************************************************** 196 */ 197 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 198 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 199 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r) 200 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d) 201 /* 202 ********************************************************************************** 203 ** IOCTL CONTROL Mail Box 204 ********************************************************************************** 205 */ 206 struct CMD_MESSAGE { 207 u_int32_t HeaderLength; 208 u_int8_t Signature[8]; 209 u_int32_t Timeout; 210 u_int32_t ControlCode; 211 u_int32_t ReturnCode; 212 u_int32_t Length; 213 }; 214 215 struct CMD_MESSAGE_FIELD { 216 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 217 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 218 }; 219 220 /************************************************************************/ 221 /************************************************************************/ 222 223 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 224 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 225 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 226 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 227 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 228 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 229 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 230 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 231 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 232 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 233 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 234 235 /*DeviceType*/ 236 #define ARECA_SATA_RAID 0x90000000 237 238 /*FunctionCode*/ 239 #define FUNCTION_READ_RQBUFFER 0x0801 240 #define FUNCTION_WRITE_WQBUFFER 0x0802 241 #define FUNCTION_CLEAR_RQBUFFER 0x0803 242 #define FUNCTION_CLEAR_WQBUFFER 0x0804 243 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 244 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 245 #define FUNCTION_SAY_HELLO 0x0807 246 #define FUNCTION_SAY_GOODBYE 0x0808 247 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 248 /* 249 ************************************************************************ 250 ** IOCTL CONTROL CODE 251 ************************************************************************ 252 */ 253 /* ARECA IO CONTROL CODE*/ 254 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 255 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 256 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 257 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 258 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 259 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 260 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 261 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 262 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 263 264 /* ARECA IOCTL ReturnCode */ 265 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 266 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 267 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 268 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 269 /* 270 ************************************************************************ 271 ** SPEC. for Areca HBA adapter 272 ************************************************************************ 273 */ 274 /* signature of set and get firmware config */ 275 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 276 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 277 /* message code of inbound message register */ 278 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 279 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 280 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 281 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 282 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 283 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 284 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 285 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 286 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 287 /* doorbell interrupt generator */ 288 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 289 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 290 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 291 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 292 /* srb areca cdb flag */ 293 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 294 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 295 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 296 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 297 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 298 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 299 /* outbound firmware ok */ 300 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 301 302 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 303 /* 304 ************************************************************************ 305 ** SPEC. for Areca HBB adapter 306 ************************************************************************ 307 */ 308 /* ARECA HBB COMMAND for its FIRMWARE */ 309 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 310 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 311 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 312 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 313 314 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */ 315 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 316 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */ 317 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 318 319 /* ARECA FLAG LANGUAGE */ 320 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 321 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 322 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 323 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 324 325 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 326 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 327 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 328 329 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 330 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 331 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 332 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 333 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 334 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 335 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 336 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 337 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 338 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 339 340 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 341 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 342 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 343 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 344 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 345 346 /* data tunnel buffer between user space program and its firmware */ 347 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 348 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 349 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 350 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 351 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 352 #define ARCMSR_HBB_BASE0_LEN 0x00021000 353 #define ARCMSR_HBB_BASE1_LEN 0x00010000 354 /* 355 ************************************************************************ 356 ** SPEC. for Areca HBC adapter 357 ************************************************************************ 358 */ 359 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 360 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 361 /* Host Interrupt Mask */ 362 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 363 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 364 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 365 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 366 /* Host Interrupt Status */ 367 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 368 /* 369 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 370 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 371 */ 372 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 373 /* 374 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 375 ** value. This bit clears only when Outbound Doorbell bits 376 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 377 ** Clear register clears bits in the Outbound Doorbell register. 378 */ 379 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 380 /* 381 ** Set whenever the Outbound Post List Producer/Consumer 382 ** Register (FIFO) is not empty. It clears when the Outbound 383 ** Post List FIFO is empty. 384 */ 385 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 386 /* 387 ** This bit indicates a SAS interrupt from a source external to 388 ** the PCIe core. This bit is not maskable. 389 */ 390 /* DoorBell*/ 391 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 392 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 393 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 394 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 395 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 396 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 397 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 398 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 399 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 400 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 401 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 402 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 403 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 404 405 /* 406 ************************************************************************ 407 ** SPEC. for Areca HBD adapter 408 ************************************************************************ 409 */ 410 #define ARCMSR_HBDMU_CHIP_ID 0x00004 411 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 412 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 413 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 414 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 415 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 416 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 417 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 418 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 419 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 420 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 421 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 422 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 423 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 424 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 425 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 426 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 427 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 428 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 429 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 430 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 431 432 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 433 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 434 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 435 436 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 437 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 438 439 /* Host Interrupt Mask */ 440 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 441 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 442 443 /* Host Interrupt Status */ 444 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 445 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 446 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 447 448 /* DoorBell*/ 449 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 450 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 451 452 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 453 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 454 455 /*outbound message 0 ready*/ 456 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 457 458 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 459 460 /*outbound message cmd isr door bell clear*/ 461 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 462 463 /*outbound list */ 464 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 465 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 466 467 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 468 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 469 /* 470 ******************************************************************************* 471 ** SPEC. for Areca HBE adapter 472 ******************************************************************************* 473 */ 474 #define ARCMSR_SIGNATURE_1884 0x188417D3 475 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001 476 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 477 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */ 478 479 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002 480 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004 481 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */ 482 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002 483 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004 484 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */ 485 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */ 486 /* ARC-1884 doorbell sync */ 487 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100 488 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004 489 /* 490 ******************************************************************************* 491 ** SPEC. for Areca HBF adapter 492 ******************************************************************************* 493 */ 494 #define ARCMSR_SIGNATURE_1886 0x188617D3 495 // Doorbell and interrupt definition are same as Type E adapter 496 /* ARC-1886 doorbell sync */ 497 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100 498 //set host rw buffer physical address at inbound message 0, 1 (low,high) 499 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300 500 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000 501 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000 502 503 /* 504 ********************************************************************* 505 ** Messaging Unit (MU) of Type A processor 506 ********************************************************************* 507 */ 508 struct HBA_MessageUnit 509 { 510 u_int32_t resrved0[4]; /*0000 000F*/ 511 u_int32_t inbound_msgaddr0; /*0010 0013*/ 512 u_int32_t inbound_msgaddr1; /*0014 0017*/ 513 u_int32_t outbound_msgaddr0; /*0018 001B*/ 514 u_int32_t outbound_msgaddr1; /*001C 001F*/ 515 u_int32_t inbound_doorbell; /*0020 0023*/ 516 u_int32_t inbound_intstatus; /*0024 0027*/ 517 u_int32_t inbound_intmask; /*0028 002B*/ 518 u_int32_t outbound_doorbell; /*002C 002F*/ 519 u_int32_t outbound_intstatus; /*0030 0033*/ 520 u_int32_t outbound_intmask; /*0034 0037*/ 521 u_int32_t reserved1[2]; /*0038 003F*/ 522 u_int32_t inbound_queueport; /*0040 0043*/ 523 u_int32_t outbound_queueport; /*0044 0047*/ 524 u_int32_t reserved2[2]; /*0048 004F*/ 525 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 526 u_int32_t reserved4[128]; /*0800 09FF 128*/ 527 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 528 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 529 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 530 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 531 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 532 }; 533 /* 534 ********************************************************************* 535 ** 536 ********************************************************************* 537 */ 538 struct HBB_DOORBELL_1203 539 { 540 u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */ 541 u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */ 542 u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */ 543 u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */ 544 u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */ 545 }; 546 struct HBB_DOORBELL 547 { 548 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 549 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 550 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 551 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 552 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 553 }; 554 /* 555 ********************************************************************* 556 ** 557 ********************************************************************* 558 */ 559 struct HBB_RWBUFFER 560 { 561 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 562 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 563 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 564 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 565 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 566 }; 567 /* 568 ********************************************************************* 569 ** Messaging Unit (MU) of Type B processor(MARVEL) 570 ********************************************************************* 571 */ 572 struct HBB_MessageUnit 573 { 574 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 575 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 576 int32_t postq_index; /* post queue index */ 577 int32_t doneq_index; /* done queue index */ 578 struct HBB_DOORBELL *hbb_doorbell; 579 struct HBB_RWBUFFER *hbb_rwbuffer; 580 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */ 581 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */ 582 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */ 583 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */ 584 }; 585 586 /* 587 ********************************************************************* 588 ** Messaging Unit (MU) of Type C processor(LSI) 589 ********************************************************************* 590 */ 591 struct HBC_MessageUnit { 592 u_int32_t message_unit_status; /*0000 0003*/ 593 u_int32_t slave_error_attribute; /*0004 0007*/ 594 u_int32_t slave_error_address; /*0008 000B*/ 595 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 596 u_int32_t master_error_attribute; /*0010 0013*/ 597 u_int32_t master_error_address_low; /*0014 0017*/ 598 u_int32_t master_error_address_high; /*0018 001B*/ 599 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 600 u_int32_t inbound_doorbell; /*0020 0023*/ 601 u_int32_t diagnostic_rw_data; /*0024 0027*/ 602 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 603 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 604 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 605 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 606 u_int32_t dcr_data; /*0038 003B*/ 607 u_int32_t dcr_address; /*003C 003F*/ 608 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 609 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 610 u_int32_t hcb_pci_address_low; /*0048 004B*/ 611 u_int32_t hcb_pci_address_high; /*004C 004F*/ 612 u_int32_t iop_int_status; /*0050 0053*/ 613 u_int32_t iop_int_mask; /*0054 0057*/ 614 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 615 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 616 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 617 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 618 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 619 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 620 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 621 u_int32_t i2o_message_unit_control; /*0074 0077*/ 622 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 623 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 624 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 625 u_int32_t message_dest_address_index; /*0090 0093*/ 626 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 627 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 628 u_int32_t outbound_doorbell; /*009C 009F*/ 629 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 630 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 631 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 632 u_int32_t reserved0; /*00AC 00AF*/ 633 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 634 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 635 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 636 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 637 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 638 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 639 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 640 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 641 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 642 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 643 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 644 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 645 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 646 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 647 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 648 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 649 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 650 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 651 u_int32_t host_diagnostic; /*00F8 00FB*/ 652 u_int32_t write_sequence; /*00FC 00FF*/ 653 u_int32_t reserved1[34]; /*0100 0187*/ 654 u_int32_t reserved2[1950]; /*0188 1FFF*/ 655 u_int32_t message_wbuffer[32]; /*2000 207F*/ 656 u_int32_t reserved3[32]; /*2080 20FF*/ 657 u_int32_t message_rbuffer[32]; /*2100 217F*/ 658 u_int32_t reserved4[32]; /*2180 21FF*/ 659 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 660 }; 661 /* 662 ********************************************************************* 663 ** Messaging Unit (MU) of Type D processor 664 ********************************************************************* 665 */ 666 struct InBound_SRB { 667 uint32_t addressLow; //pointer to SRB block 668 uint32_t addressHigh; 669 uint32_t length; // in DWORDs 670 uint32_t reserved0; 671 }; 672 673 struct OutBound_SRB { 674 uint32_t addressLow; //pointer to SRB block 675 uint32_t addressHigh; 676 }; 677 678 struct HBD_MessageUnit { 679 uint32_t reserved0; 680 uint32_t chip_id; //0x0004 681 uint32_t cpu_mem_config; //0x0008 682 uint32_t reserved1[10]; //0x000C 683 uint32_t i2o_host_interrupt_mask; //0x0034 684 uint32_t reserved2[114]; //0x0038 685 uint32_t host_int_status; //0x0200 686 uint32_t host_int_enable; //0x0204 687 uint32_t reserved3[1]; //0x0208 688 uint32_t pcief0_int_enable; //0x020C 689 uint32_t reserved4[124]; //0x0210 690 uint32_t inbound_msgaddr0; //0x0400 691 uint32_t inbound_msgaddr1; //0x0404 692 uint32_t reserved5[6]; //0x0408 693 uint32_t outbound_msgaddr0; //0x0420 694 uint32_t outbound_msgaddr1; //0x0424 695 uint32_t reserved6[14]; //0x0428 696 uint32_t inbound_doorbell; //0x0460 697 uint32_t reserved7[7]; //0x0464 698 uint32_t outbound_doorbell; //0x0480 699 uint32_t outbound_doorbell_enable; //0x0484 700 uint32_t reserved8[734]; //0x0488 701 uint32_t inboundlist_base_low; //0x1000 702 uint32_t inboundlist_base_high; //0x1004 703 uint32_t reserved9[4]; //0x1008 704 uint32_t inboundlist_write_pointer; //0x1018 705 uint32_t inboundlist_read_pointer; //0x101C 706 uint32_t reserved10[16]; //0x1020 707 uint32_t outboundlist_base_low; //0x1060 708 uint32_t outboundlist_base_high; //0x1064 709 uint32_t reserved11; //0x1068 710 uint32_t outboundlist_copy_pointer; //0x106C 711 uint32_t outboundlist_read_pointer; //0x1070 0x1072 712 uint32_t reserved12[5]; //0x1074 713 uint32_t outboundlist_interrupt_cause; //0x1088 714 uint32_t outboundlist_interrupt_enable; //0x108C 715 uint32_t reserved13[988]; //0x1090 716 uint32_t message_wbuffer[32]; //0x2000 717 uint32_t reserved14[32]; //0x2080 718 uint32_t message_rbuffer[32]; //0x2100 719 uint32_t reserved15[32]; //0x2180 720 uint32_t msgcode_rwbuffer[256]; //0x2200 721 }; 722 723 struct HBD_MessageUnit0 { 724 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 725 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 726 uint16_t postq_index; 727 uint16_t doneq_index; 728 struct HBD_MessageUnit *phbdmu; 729 }; 730 /* 731 ********************************************************************* 732 ** Messaging Unit (MU) of Type E processor(LSI) 733 ********************************************************************* 734 */ 735 struct HBE_MessageUnit { 736 u_int32_t iobound_doorbell; /*0000 0003*/ 737 u_int32_t write_sequence_3xxx; /*0004 0007*/ 738 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 739 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 740 u_int32_t master_error_attribute; /*0010 0013*/ 741 u_int32_t master_error_address_low; /*0014 0017*/ 742 u_int32_t master_error_address_high; /*0018 001B*/ 743 u_int32_t hcb_size; /*001C 001F*/ 744 u_int32_t inbound_doorbell; /*0020 0023*/ 745 u_int32_t diagnostic_rw_data; /*0024 0027*/ 746 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 747 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 748 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 749 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 750 u_int32_t dcr_data; /*0038 003B*/ 751 u_int32_t dcr_address; /*003C 003F*/ 752 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 753 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 754 u_int32_t hcb_pci_address_low; /*0048 004B*/ 755 u_int32_t hcb_pci_address_high; /*004C 004F*/ 756 u_int32_t iop_int_status; /*0050 0053*/ 757 u_int32_t iop_int_mask; /*0054 0057*/ 758 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 759 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 760 u_int32_t inbound_free_list_index; /*0060 0063*/ 761 u_int32_t inbound_post_list_index; /*0064 0067*/ 762 u_int32_t outbound_free_list_index; /*0068 006B*/ 763 u_int32_t outbound_post_list_index; /*006C 006F*/ 764 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 765 u_int32_t i2o_message_unit_control; /*0074 0077*/ 766 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 767 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 768 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 769 u_int32_t message_dest_address_index; /*0090 0093*/ 770 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 771 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 772 u_int32_t outbound_doorbell; /*009C 009F*/ 773 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 774 u_int32_t message_source_address_index; /*00A4 00A7*/ 775 u_int32_t message_done_queue_index; /*00A8 00AB*/ 776 u_int32_t reserved0; /*00AC 00AF*/ 777 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 778 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 779 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 780 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 781 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 782 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 783 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 784 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 785 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 786 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 787 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 788 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 789 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 790 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 791 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 792 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 793 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 794 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 795 u_int32_t host_diagnostic; /*00F8 00FB*/ 796 u_int32_t write_sequence; /*00FC 00FF*/ 797 u_int32_t reserved1[46]; /*0100 01B7*/ 798 u_int32_t reply_post_producer_index; /*01B8 01BB*/ 799 u_int32_t reply_post_consumer_index; /*01BC 01BF*/ 800 u_int32_t reserved2[1936]; /*01C0 1FFF*/ 801 u_int32_t message_wbuffer[32]; /*2000 207F*/ 802 u_int32_t reserved3[32]; /*2080 20FF*/ 803 u_int32_t message_rbuffer[32]; /*2100 217F*/ 804 u_int32_t reserved4[32]; /*2180 21FF*/ 805 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 806 }; 807 808 /* 809 ********************************************************************* 810 ** Messaging Unit (MU) of Type F processor(LSI) 811 ********************************************************************* 812 */ 813 struct HBF_MessageUnit { 814 u_int32_t iobound_doorbell; /*0000 0003*/ 815 u_int32_t write_sequence_3xxx; /*0004 0007*/ 816 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 817 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 818 u_int32_t master_error_attribute; /*0010 0013*/ 819 u_int32_t master_error_address_low; /*0014 0017*/ 820 u_int32_t master_error_address_high; /*0018 001B*/ 821 u_int32_t hcb_size; /*001C 001F*/ 822 u_int32_t inbound_doorbell; /*0020 0023*/ 823 u_int32_t diagnostic_rw_data; /*0024 0027*/ 824 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 825 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 826 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 827 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 828 u_int32_t dcr_data; /*0038 003B*/ 829 u_int32_t dcr_address; /*003C 003F*/ 830 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 831 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 832 u_int32_t hcb_pci_address_low; /*0048 004B*/ 833 u_int32_t hcb_pci_address_high; /*004C 004F*/ 834 u_int32_t iop_int_status; /*0050 0053*/ 835 u_int32_t iop_int_mask; /*0054 0057*/ 836 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 837 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 838 u_int32_t inbound_free_list_index; /*0060 0063*/ 839 u_int32_t inbound_post_list_index; /*0064 0067*/ 840 u_int32_t reply_post_producer_index; /*0068 006B*/ 841 u_int32_t reply_post_consumer_index; /*006C 006F*/ 842 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 843 u_int32_t i2o_message_unit_control; /*0074 0077*/ 844 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 845 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 846 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 847 u_int32_t message_dest_address_index; /*0090 0093*/ 848 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 849 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 850 u_int32_t outbound_doorbell; /*009C 009F*/ 851 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 852 u_int32_t message_source_address_index; /*00A4 00A7*/ 853 u_int32_t message_done_queue_index; /*00A8 00AB*/ 854 u_int32_t reserved0; /*00AC 00AF*/ 855 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 856 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 857 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 858 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 859 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 860 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 861 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 862 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 863 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 864 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 865 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 866 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 867 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 868 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 869 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 870 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 871 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 872 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 873 u_int32_t host_diagnostic; /*00F8 00FB*/ 874 u_int32_t write_sequence; /*00FC 00FF*/ 875 u_int32_t reserved1[46]; /*0100 01B7*/ 876 u_int32_t reply_post_producer_index1; /*01B8 01BB*/ 877 u_int32_t reply_post_consumer_index1; /*01BC 01BF*/ 878 }; 879 880 #define MESG_RW_BUFFER_SIZE (256 * 3) 881 882 typedef struct deliver_completeQ { 883 u_int16_t cmdFlag; 884 u_int16_t cmdSMID; 885 u_int16_t cmdLMID; // reserved (0) 886 u_int16_t cmdFlag2; // reserved (0) 887 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q; 888 889 #define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128) 890 891 /* 892 ********************************************************************* 893 ** 894 ********************************************************************* 895 */ 896 struct MessageUnit_UNION 897 { 898 union { 899 struct HBA_MessageUnit hbamu; 900 struct HBB_MessageUnit hbbmu; 901 struct HBC_MessageUnit hbcmu; 902 struct HBD_MessageUnit0 hbdmu; 903 struct HBE_MessageUnit hbemu; 904 struct HBF_MessageUnit hbfmu; 905 } muu; 906 }; 907 /* 908 ************************************************************* 909 ** structure for holding DMA address data 910 ************************************************************* 911 */ 912 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 913 /* 914 ************************************************************************************************ 915 ** ARECA FIRMWARE SPEC 916 ************************************************************************************************ 917 ** Usage of IOP331 adapter 918 ** (All In/Out is in IOP331's view) 919 ** 1. Message 0 --> InitThread message and retrun code 920 ** 2. Doorbell is used for RS-232 emulation 921 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 922 ** bit1 -- data out has been read (DRIVER DATA READ OK) 923 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 924 ** bit1 -- data in has been read (IOP331 DATA READ OK) 925 ** 3. Index Memory Usage 926 ** offset 0xf00 : for RS232 out (request buffer) 927 ** offset 0xe00 : for RS232 in (scratch buffer) 928 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 929 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 930 ** 4. RS-232 emulation 931 ** Currently 128 byte buffer is used 932 ** 1st u_int32_t : Data length (1--124) 933 ** Byte 4--127 : Max 124 bytes of data 934 ** 5. PostQ 935 ** All SCSI Command must be sent through postQ: 936 ** (inbound queue port) Request frame must be 32 bytes aligned 937 ** # bit27--bit31 => flag for post ccb 938 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 939 ** bit31 : 0 : 256 bytes frame 940 ** 1 : 512 bytes frame 941 ** bit30 : 0 : normal request 942 ** 1 : BIOS request 943 ** bit29 : reserved 944 ** bit28 : reserved 945 ** bit27 : reserved 946 ** ------------------------------------------------------------------------------- 947 ** (outbount queue port) Request reply 948 ** # bit27--bit31 => flag for reply 949 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 950 ** bit31 : must be 0 (for this type of reply) 951 ** bit30 : reserved for BIOS handshake 952 ** bit29 : reserved 953 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 954 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 955 ** bit27 : reserved 956 ** 6. BIOS request 957 ** All BIOS request is the same with request from PostQ 958 ** Except : 959 ** Request frame is sent from configuration space 960 ** offset: 0x78 : Request Frame (bit30 == 1) 961 ** offset: 0x18 : writeonly to generate IRQ to IOP331 962 ** Completion of request: 963 ** (bit30 == 0, bit28==err flag) 964 ** 7. Definition of SGL entry (structure) 965 ** 8. Message1 Out - Diag Status Code (????) 966 ** 9. Message0 message code : 967 ** 0x00 : NOP 968 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 969 ** Signature 0x87974060(4) 970 ** Request len 0x00000200(4) 971 ** numbers of queue 0x00000100(4) 972 ** SDRAM Size 0x00000100(4)-->256 MB 973 ** IDE Channels 0x00000008(4) 974 ** vendor 40 bytes char 975 ** model 8 bytes char 976 ** FirmVer 16 bytes char 977 ** Device Map 16 bytes char 978 ** 979 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 980 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 981 ** Signature 0x87974063(4) 982 ** UPPER32 of Request Frame (4)-->Driver Only 983 ** 0x03 : Reset (Abort all queued Command) 984 ** 0x04 : Stop Background Activity 985 ** 0x05 : Flush Cache 986 ** 0x06 : Start Background Activity (re-start if background is halted) 987 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 988 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 989 ** byte 0 : 0xaa <-- signature 990 ** byte 1 : 0x55 <-- signature 991 ** byte 2 : year (04) 992 ** byte 3 : month (1..12) 993 ** byte 4 : date (1..31) 994 ** byte 5 : hour (0..23) 995 ** byte 6 : minute (0..59) 996 ** byte 7 : second (0..59) 997 ** ********************************************************************************* 998 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 999 ** ==> Difference from IOP348 1000 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 1001 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 1002 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 1003 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 1004 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 1005 ** <A> use doorbell to generate interrupt 1006 ** 1007 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 1008 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 1009 ** 1010 ** a. Message1: Out - Diag Status Code (????) 1011 ** 1012 ** b. Message0: message code 1013 ** 0x00 : NOP 1014 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 1015 ** Signature 0x87974060(4) 1016 ** Request len 0x00000200(4) 1017 ** numbers of queue 0x00000100(4) 1018 ** SDRAM Size 0x00000100(4)-->256 MB 1019 ** IDE Channels 0x00000008(4) 1020 ** vendor 40 bytes char 1021 ** model 8 bytes char 1022 ** FirmVer 16 bytes char 1023 ** Device Map 16 bytes char 1024 ** cfgVersion ULONG <== Added for checking of new firmware capability 1025 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 1026 ** Signature 0x87974063(4) 1027 ** UPPER32 of Request Frame (4)-->Driver Only 1028 ** 0x03 : Reset (Abort all queued Command) 1029 ** 0x04 : Stop Background Activity 1030 ** 0x05 : Flush Cache 1031 ** 0x06 : Start Background Activity (re-start if background is halted) 1032 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 1033 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 1034 ** byte 0 : 0xaa <-- signature 1035 ** byte 1 : 0x55 <-- signature 1036 ** byte 2 : year (04) 1037 ** byte 3 : month (1..12) 1038 ** byte 4 : date (1..31) 1039 ** byte 5 : hour (0..23) 1040 ** byte 6 : minute (0..59) 1041 ** byte 7 : second (0..59) 1042 ** 1043 ** <2> Doorbell Register is used for RS-232 emulation 1044 ** <A> different clear register 1045 ** <B> different bit0 definition (bit0 is reserved) 1046 ** 1047 ** inbound doorbell : at offset 0x20 1048 ** inbound doorbell clear : at offset 0x70 1049 ** 1050 ** inbound doorbell : bit0 -- reserved 1051 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 1052 ** bit2 -- data out has been read (DRIVER DATA READ OK) 1053 ** bit3 -- inbound message 0 ready 1054 ** bit4 -- more than 12 request completed in a time 1055 ** 1056 ** outbound doorbell : at offset 0x9C 1057 ** outbound doorbell clear : at offset 0xA0 1058 ** 1059 ** outbound doorbell : bit0 -- reserved 1060 ** bit1 -- data out ready (IOP DATA WRITE OK) 1061 ** bit2 -- data in has been read (IOP DATA READ OK) 1062 ** bit3 -- outbound message 0 ready 1063 ** 1064 ** <3> Index Memory Usage (Buffer Area) 1065 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 1066 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 1067 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 1068 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 1069 ** 1070 ** <4> PostQ (Command Post Address) 1071 ** All SCSI Command must be sent through postQ: 1072 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 1073 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 1074 ** outbound queue port32 at offset 0x44 1075 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 1076 ** <A> For 32bit queue, access low part is enough to send/receive request 1077 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 1078 ** same for outbound queue port 1079 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 1080 ** to post inbound request in a single instruction, and use 64bit instruction 1081 ** to retrieve outbound request in a single instruction. 1082 ** If in 32bit environment, when sending inbound queue, write high part first 1083 ** then write low part. For receiving outbound request, read high part first 1084 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 1085 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 1086 ** consistency of the FIFO. Another way to check empty is to check status flag 1087 ** at 0x30 bit3. 1088 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 1089 ** For BIOS, 16bytes aligned is OK 1090 ** For Driver, 32bytes alignment is recommended. 1091 ** POST Command bit0 to bit3 is defined differently 1092 ** ---------------------------- 1093 ** bit0:1 for PULL mode (must be 1) 1094 ** ---------------------------- 1095 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 1096 ** 000: <= 0x0080 (128) 1097 ** 001: <= 0x0100 (256) 1098 ** 010: <= 0x0180 (384) 1099 ** 011: <= 0x0200 (512) 1100 ** 100: <= 0x0280 (640) 1101 ** 101: <= 0x0300 (768) 1102 ** 110: <= 0x0300 (reserved) 1103 ** 111: <= 0x0300 (reserved) 1104 ** ----------------------------- 1105 ** if len > 0x300 the len always set as 0x300 1106 ** ----------------------------- 1107 ** post addr = addr | ((len-1) >> 6) | 1 1108 ** ----------------------------- 1109 ** page length in command buffer still required, 1110 ** 1111 ** if page length > 3, 1112 ** firmware will assume more request data need to be retrieved 1113 ** 1114 ** <D> Outbound Posting 1115 ** bit0:0 , no error, 1 with error, refer to status buffer 1116 ** bit1:0 , reserved (will be 0) 1117 ** bit2:0 , reserved (will be 0) 1118 ** bit3:0 , reserved (will be 0) 1119 ** bit63-4: Completed command address 1120 ** 1121 ** <E> BIOS support, no special support is required. 1122 ** LSI2108 support I/O register 1123 ** All driver functionality is supported through I/O address 1124 ** 1125 ************************************************************************************************ 1126 */ 1127 /* 1128 ********************************** 1129 ** 1130 ********************************** 1131 */ 1132 /* size 8 bytes */ 1133 /* 32bit Scatter-Gather list */ 1134 struct SG32ENTRY { /* length bit 24 == 0 */ 1135 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1136 u_int32_t address; 1137 }; 1138 /* size 12 bytes */ 1139 /* 64bit Scatter-Gather list */ 1140 struct SG64ENTRY { /* length bit 24 == 1 */ 1141 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1142 u_int32_t address; 1143 u_int32_t addresshigh; 1144 }; 1145 struct SGENTRY_UNION { 1146 union { 1147 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 1148 struct SG64ENTRY sg64entry; /* 30h */ 1149 }u; 1150 }; 1151 /* 1152 ********************************** 1153 ** 1154 ********************************** 1155 */ 1156 struct QBUFFER { 1157 u_int32_t data_len; 1158 u_int8_t data[124]; 1159 }; 1160 /* 1161 ********************************** 1162 */ 1163 typedef struct PHYS_ADDR64 { 1164 u_int32_t phyadd_low; 1165 u_int32_t phyadd_high; 1166 }PHYSADDR64; 1167 /* 1168 ************************************************************************************************ 1169 ** FIRMWARE INFO 1170 ************************************************************************************************ 1171 */ 1172 #define ARCMSR_FW_MODEL_OFFSET 15 1173 #define ARCMSR_FW_VERS_OFFSET 17 1174 #define ARCMSR_FW_DEVMAP_OFFSET 21 1175 #define ARCMSR_FW_CFGVER_OFFSET 25 1176 #define ARCMSR_FW_PICSTATUS 30 1177 1178 struct FIRMWARE_INFO { 1179 u_int32_t signature; /*0,00-03*/ 1180 u_int32_t request_len; /*1,04-07*/ 1181 u_int32_t numbers_queue; /*2,08-11*/ 1182 u_int32_t sdram_size; /*3,12-15*/ 1183 u_int32_t ide_channels; /*4,16-19*/ 1184 char vendor[40]; /*5,20-59*/ 1185 char model[8]; /*15,60-67*/ 1186 char firmware_ver[16]; /*17,68-83*/ 1187 char device_map[16]; /*21,84-99*/ 1188 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 1189 char cfgSerial[16]; /*26,104-119*/ 1190 u_int32_t cfgPicStatus; /*30,120-123*/ 1191 }; 1192 /* (A) For cfgVersion in FIRMWARE_INFO 1193 ** if low BYTE (byte#0) >= 3 (version 3) 1194 ** then byte#1 report the capability of the firmware can xfer in a single request 1195 ** 1196 ** byte#1 1197 ** 0 256K 1198 ** 1 512K 1199 ** 2 1M 1200 ** 3 2M 1201 ** 4 4M 1202 ** 5 8M 1203 ** 6 16M 1204 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 1205 ** Driver support new xfer method need to set this field to indicate 1206 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 1207 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 1208 ** driver need to set the msgPages to 0x16 1209 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 1210 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 1211 ** <= 0x100 1 0 1212 ** <= 0x200 2 1 1213 ** <= 0x300 3 1 1214 ** <= 0x400 4 1 1215 ** . 1216 ** . 1217 */ 1218 1219 /* 1220 ************************************************************************************************ 1221 ** size 0x1F8 (504) 1222 ************************************************************************************************ 1223 */ 1224 struct ARCMSR_CDB { 1225 u_int8_t Bus; /* 00h should be 0 */ 1226 u_int8_t TargetID; /* 01h should be 0--15 */ 1227 u_int8_t LUN; /* 02h should be 0--7 */ 1228 u_int8_t Function; /* 03h should be 1 */ 1229 1230 u_int8_t CdbLength; /* 04h not used now */ 1231 u_int8_t sgcount; /* 05h */ 1232 u_int8_t Flags; /* 06h */ 1233 u_int8_t msgPages; /* 07h */ 1234 1235 u_int32_t Context; /* 08h Address of this request */ 1236 u_int32_t DataLength; /* 0ch not used now */ 1237 1238 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1239 /* 1240 ******************************************************** 1241 ** Device Status : the same from SCSI bus if error occur 1242 ** SCSI bus status codes. 1243 ******************************************************** 1244 */ 1245 u_int8_t DeviceStatus; /* 20h if error */ 1246 1247 u_int8_t SenseData[15]; /* 21h output */ 1248 1249 union { 1250 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1251 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1252 } u; 1253 }; 1254 /* CDB flag */ 1255 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1256 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1257 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1258 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1259 #define ARCMSR_CDB_FLAG_HEADQ 0x08 1260 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1261 /* scsi status */ 1262 #define SCSISTAT_GOOD 0x00 1263 #define SCSISTAT_CHECK_CONDITION 0x02 1264 #define SCSISTAT_CONDITION_MET 0x04 1265 #define SCSISTAT_BUSY 0x08 1266 #define SCSISTAT_INTERMEDIATE 0x10 1267 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1268 #define SCSISTAT_RESERVATION_CONFLICT 0x18 1269 #define SCSISTAT_COMMAND_TERMINATED 0x22 1270 #define SCSISTAT_QUEUE_FULL 0x28 1271 /* DeviceStatus */ 1272 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1273 #define ARCMSR_DEV_ABORTED 0xF1 1274 #define ARCMSR_DEV_INIT_FAIL 0xF2 1275 /* 1276 ********************************************************************* 1277 ** Command Control Block (SrbExtension) 1278 ** SRB must be not cross page boundary,and the order from offset 0 1279 ** structure describing an ATA disk request 1280 ** this SRB length must be 32 bytes boundary 1281 ********************************************************************* 1282 */ 1283 struct CommandControlBlock { 1284 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1285 unsigned long cdb_phyaddr; /* 504-507 */ 1286 /* ======================512+32 bytes============================ */ 1287 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1288 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1289 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1290 u_int16_t srb_flags; /* 536-537 */ 1291 u_int16_t srb_state; /* 538-539 */ 1292 u_int32_t arc_cdb_size; /* 508-511 */ 1293 struct callout ccb_callout; 1294 u_int32_t smid; 1295 /* ========================================================== */ 1296 }; 1297 /* srb_flags */ 1298 #define SRB_FLAG_READ 0x0000 1299 #define SRB_FLAG_WRITE 0x0001 1300 #define SRB_FLAG_ERROR 0x0002 1301 #define SRB_FLAG_FLUSHCACHE 0x0004 1302 #define SRB_FLAG_MASTER_ABORTED 0x0008 1303 #define SRB_FLAG_DMAVALID 0x0010 1304 #define SRB_FLAG_DMACONSISTENT 0x0020 1305 #define SRB_FLAG_DMAWRITE 0x0040 1306 #define SRB_FLAG_PKTBIND 0x0080 1307 #define SRB_FLAG_TIMER_START 0x0080 1308 #define SRB_FLAG_DIRECT_IO 0x0100 1309 #define SRB_FLAG_USE_SG 0x0200 1310 /* srb_state */ 1311 #define ARCMSR_SRB_DONE 0x0000 1312 #define ARCMSR_SRB_UNBUILD 0x0000 1313 #define ARCMSR_SRB_TIMEOUT 0x1111 1314 #define ARCMSR_SRB_RETRY 0x2222 1315 #define ARCMSR_SRB_START 0x55AA 1316 #define ARCMSR_SRB_PENDING 0xAA55 1317 #define ARCMSR_SRB_RESET 0xA5A5 1318 #define ARCMSR_SRB_ABORTED 0x5A5A 1319 #define ARCMSR_SRB_ILLEGAL 0xFFFF 1320 1321 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1322 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1323 1324 /* 1325 ********************************************************************* 1326 ** Adapter Control Block 1327 ********************************************************************* 1328 */ 1329 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */ 1330 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */ 1331 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */ 1332 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */ 1333 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */ 1334 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hbd L IOP */ 1335 1336 struct AdapterControlBlock { 1337 u_int32_t adapter_type; /* adapter A,B..... */ 1338 1339 bus_space_tag_t btag[2]; 1340 bus_space_handle_t bhandle[2]; 1341 bus_dma_tag_t parent_dmat; 1342 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1343 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1344 bus_dmamap_t srb_dmamap; 1345 device_t pci_dev; 1346 struct cdev *ioctl_dev; 1347 int pci_unit; 1348 1349 struct resource *sys_res_arcmsr[2]; 1350 struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS]; 1351 void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */ 1352 int irq_id[ARCMSR_NUM_MSIX_VECTORS]; 1353 1354 /* Hooks into the CAM XPT */ 1355 struct cam_sim *psim; 1356 struct cam_path *ppath; 1357 u_int8_t *uncacheptr; 1358 unsigned long vir2phy_offset; 1359 union { 1360 unsigned long phyaddr; 1361 struct { 1362 u_int32_t phyadd_low; 1363 u_int32_t phyadd_high; 1364 }B; 1365 }srb_phyaddr; 1366 // unsigned long srb_phyaddr; 1367 /* Offset is used in making arc cdb physical to virtual calculations */ 1368 u_int32_t outbound_int_enable; 1369 1370 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1371 vm_offset_t mem_base0; 1372 vm_offset_t mem_base1; 1373 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC) 1374 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host) 1375 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA 1376 1377 u_int8_t adapter_index; 1378 u_int8_t irq; 1379 u_int16_t acb_flags; 1380 1381 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1382 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1383 int32_t workingsrb_doneindex; /* done srb array index */ 1384 int32_t workingsrb_startindex; /* start srb array index */ 1385 int32_t srboutstandingcount; 1386 1387 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1388 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1389 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1390 1391 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1392 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1393 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1394 1395 arcmsr_lock_t isr_lock; 1396 arcmsr_lock_t srb_lock; 1397 arcmsr_lock_t postDone_lock; 1398 arcmsr_lock_t qbuffer_lock; 1399 1400 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1401 u_int32_t num_resets; 1402 u_int32_t num_aborts; 1403 u_int32_t firm_request_len; /*1,04-07*/ 1404 u_int32_t firm_numbers_queue; /*2,08-11*/ 1405 u_int32_t firm_sdram_size; /*3,12-15*/ 1406 u_int32_t firm_ide_channels; /*4,16-19*/ 1407 u_int32_t firm_cfg_version; 1408 char firm_model[12]; /*15,60-67*/ 1409 char firm_version[20]; /*17,68-83*/ 1410 char device_map[20]; /*21,84-99 */ 1411 u_int32_t firm_PicStatus; 1412 struct callout devmap_callout; 1413 u_int32_t pktRequestCount; 1414 u_int32_t pktReturnCount; 1415 u_int32_t vendor_device_id; 1416 u_int32_t adapter_bus_speed; 1417 u_int32_t maxOutstanding; 1418 u_int16_t sub_device_id; 1419 u_int32_t doneq_index; 1420 u_int32_t in_doorbell; 1421 u_int32_t out_doorbell; 1422 u_int32_t completionQ_entry; 1423 pCompletion_Q pCompletionQ; 1424 int xor_mega; 1425 int msix_vectors; 1426 int rid[2]; 1427 unsigned long completeQ_phys; 1428 u_int32_t max_coherent_size; 1429 u_int8_t *xortable; 1430 unsigned long xor_sgtable_phy; 1431 bus_dma_tag_t xortable_dmat; /* dmat for xor table */ 1432 bus_dmamap_t xortable_dmamap; 1433 u_int8_t *xorptr; 1434 bus_dma_tag_t xor_dmat; /* dmat for xor */ 1435 bus_dmamap_t xor_dmamap; 1436 unsigned int init2cfg_size; 1437 unsigned int xorVirtOffset; 1438 };/* HW_DEVICE_EXTENSION */ 1439 1440 struct HostRamBuf { 1441 u_int32_t hrbSignature; // must be "HRBS" 1442 u_int32_t hrbSize; // total buffer size(must be multiples of MB, this version should be 128+3 MB, i.e. 0x8300000) 1443 u_int32_t hrbRes[2]; // reserved, must be set to 0 1444 }; 1445 struct XorSg { 1446 u_int64_t xorPhys; 1447 u_int64_t xorBufLen; 1448 }; 1449 #define ARCMSR_XOR_SEG_SIZE (1024 * 1024) 1450 #define ARCMSR_MAX_XOR_SEG 128 + 3 1451 #define ARCMSR_DMA_ALLOC_FLAG (BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO | BUS_DMA_NOCACHE) 1452 1453 /* acb_flags */ 1454 #define ACB_F_SCSISTOPADAPTER 0x0001 1455 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1456 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1457 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1458 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1459 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1460 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1461 #define ACB_F_BUS_RESET 0x0080 1462 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 1463 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb failed */ 1464 #define ACB_F_CAM_DEV_QFRZN 0x0400 1465 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1466 #define ACB_F_SRB_FUNCTION_POWER 0x1000 1467 #define ACB_F_MSIX_ENABLED 0x2000 1468 #define ACB_F_MSG_GET_CONFIG 0x4000 1469 #define ACB_F_DIRECT_IO 0x8000 1470 #define ACB_F_DMAMAP_SRB 0x10000 1471 #define ACB_F_DMAMAP_SGTABLE 0x20000 1472 #define ACB_F_DMAMAP_SG 0x40000 1473 #define ACB_F_MAPXOR_FAILD 0x80000 1474 /* devstate */ 1475 #define ARECA_RAID_GONE 0x55 1476 #define ARECA_RAID_GOOD 0xaa 1477 /* adapter_bus_speed */ 1478 #define ACB_BUS_SPEED_3G 0 1479 #define ACB_BUS_SPEED_6G 1 1480 #define ACB_BUS_SPEED_12G 2 1481 /* 1482 ************************************************************* 1483 ************************************************************* 1484 */ 1485 struct SENSE_DATA { 1486 u_int8_t ErrorCode:7; 1487 u_int8_t Valid:1; 1488 u_int8_t SegmentNumber; 1489 u_int8_t SenseKey:4; 1490 u_int8_t Reserved:1; 1491 u_int8_t IncorrectLength:1; 1492 u_int8_t EndOfMedia:1; 1493 u_int8_t FileMark:1; 1494 u_int8_t Information[4]; 1495 u_int8_t AdditionalSenseLength; 1496 u_int8_t CommandSpecificInformation[4]; 1497 u_int8_t AdditionalSenseCode; 1498 u_int8_t AdditionalSenseCodeQualifier; 1499 u_int8_t FieldReplaceableUnitCode; 1500 u_int8_t SenseKeySpecific[3]; 1501 }; 1502 /* 1503 ********************************** 1504 ** Peripheral Device Type definitions 1505 ********************************** 1506 */ 1507 #define SCSI_DASD 0x00 /* Direct-access Device */ 1508 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1509 #define SCSI_PRINTER 0x02 /* Printer device */ 1510 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1511 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1512 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1513 #define SCSI_SCANNER 0x06 /* Scanner device */ 1514 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1515 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1516 #define SCSI_COMM 0x09 /* Communications device */ 1517 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1518 /* 1519 ************************************************************************************************************ 1520 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1521 ** 80331 PCI-to-PCI Bridge 1522 ** PCI Configuration Space 1523 ** 1524 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1525 ** Programming Interface 1526 ** ======================== 1527 ** Configuration Register Address Space Groupings and Ranges 1528 ** ============================================================= 1529 ** Register Group Configuration Offset 1530 ** ------------------------------------------------------------- 1531 ** Standard PCI Configuration 00-3Fh 1532 ** ------------------------------------------------------------- 1533 ** Device Specific Registers 40-A7h 1534 ** ------------------------------------------------------------- 1535 ** Reserved A8-CBh 1536 ** ------------------------------------------------------------- 1537 ** Enhanced Capability List CC-FFh 1538 ** ========================================================================================================== 1539 ** Standard PCI [Type 1] Configuration Space Address Map 1540 ** ********************************************************************************************************** 1541 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1542 ** ---------------------------------------------------------------------------------------------------------- 1543 ** | Device ID | Vendor ID | 00h 1544 ** ---------------------------------------------------------------------------------------------------------- 1545 ** | Primary Status | Primary Command | 04h 1546 ** ---------------------------------------------------------------------------------------------------------- 1547 ** | Class Code | RevID | 08h 1548 ** ---------------------------------------------------------------------------------------------------------- 1549 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1550 ** ---------------------------------------------------------------------------------------------------------- 1551 ** | Reserved | 10h 1552 ** ---------------------------------------------------------------------------------------------------------- 1553 ** | Reserved | 14h 1554 ** ---------------------------------------------------------------------------------------------------------- 1555 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1556 ** ---------------------------------------------------------------------------------------------------------- 1557 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1558 ** ---------------------------------------------------------------------------------------------------------- 1559 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1560 ** ---------------------------------------------------------------------------------------------------------- 1561 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1562 ** ---------------------------------------------------------------------------------------------------------- 1563 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1564 ** ---------------------------------------------------------------------------------------------------------- 1565 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1566 ** ---------------------------------------------------------------------------------------------------------- 1567 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1568 ** ---------------------------------------------------------------------------------------------------------- 1569 ** | Reserved | Capabilities Pointer | 34h 1570 ** ---------------------------------------------------------------------------------------------------------- 1571 ** | Reserved | 38h 1572 ** ---------------------------------------------------------------------------------------------------------- 1573 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1574 **============================================================================================================= 1575 */ 1576 /* 1577 **============================================================================================================= 1578 ** 0x03-0x00 : 1579 ** Bit Default Description 1580 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1581 ** ID is unique per product speed as indicated. 1582 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1583 **============================================================================================================= 1584 */ 1585 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1586 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1587 /* 1588 **============================================================================== 1589 ** 0x05-0x04 : command register 1590 ** Bit Default Description 1591 **15:11 00h Reserved 1592 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1593 ** The bridge does not support interrupts. 1594 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1595 ** transactions on the primary bus. 1596 ** The bridge does not generate fast back to back 1597 ** transactions on the primary bus. 1598 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1599 ** 0=The bridge does not assert P_SERR#. 1600 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1601 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1602 ** that bridge does not perform address or data stepping, 1603 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1604 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1605 ** Also bridge does not assert P_SERR# in response to 1606 ** a detected address or attribute parity error. 1607 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1608 ** The bridge also asserts P_SERR# 1609 ** (when enabled globally via bit(8) of this register) 1610 ** in response to a detected address or attribute parity error. 1611 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1612 ** VGA palette write transactions are I/O transactions 1613 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1614 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1615 ** or are fully decoding 1616 ** (i.e., must be all 0's depending upon the VGA 1617 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1618 ** P_AD[31:16] equal to 0000h 1619 ** 0=The bridge ignores VGA palette write transactions, 1620 ** unless decoded by the standard I/O address range window. 1621 ** 1=The bridge responds to VGA palette write transactions 1622 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1623 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1624 ** MWI transactions targeting resources on the opposite side of the bridge, 1625 ** however, are forwarded as MWI transactions. 1626 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1627 ** This bit is read only and always returns 0 when read 1628 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1629 ** Initiation of configuration transactions is not affected by the state of this bit. 1630 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1631 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1632 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1633 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1634 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1635 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1636 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1637 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1638 **============================================================================== 1639 */ 1640 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1641 #define PCI_DISABLE_INTERRUPT 0x0400 1642 /* 1643 **============================================================================== 1644 ** 0x07-0x06 : status register 1645 ** Bit Default Description 1646 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1647 ** attribute or data parity error. 1648 ** This bit is set regardless of the state of the PER bit in the command register. 1649 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1650 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1651 ** acting as the initiator on the primary bus, 1652 ** its transaction (with the exception of special cycles) 1653 ** has been terminated with a Master Abort. 1654 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1655 ** acting as the initiator on the primary bus, 1656 ** its transaction has been terminated with a Target Abort. 1657 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1658 ** as the target of a transaction, terminates it with a Target Abort. 1659 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1660 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1661 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1662 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1663 ** The bridge is the current master on the primary bus 1664 ** S_PERR# is detected asserted or is asserted by bridge 1665 ** The Parity Error Response bit is set in the Command register 1666 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1667 ** is able to respond to fast back to back transactions on its primary interface. 1668 ** 06 0 Reserved 1669 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1670 ** 1 = 1671 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1672 ** Offset 34h (Capability Pointer register) 1673 ** provides the offset for the first entry 1674 ** in the linked list of enhanced capabilities. 1675 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1676 ** The bridge does not support interrupts. 1677 ** 02:00 000 Reserved 1678 **============================================================================== 1679 */ 1680 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1681 #define ARCMSR_ADAP_66MHZ 0x20 1682 /* 1683 **============================================================================== 1684 ** 0x08 : revision ID 1685 ** Bit Default Description 1686 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1687 **============================================================================== 1688 */ 1689 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1690 /* 1691 **============================================================================== 1692 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1693 ** Bit Default Description 1694 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1695 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1696 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1697 **============================================================================== 1698 */ 1699 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1700 /* 1701 **============================================================================== 1702 ** 0x0c : cache line size 1703 ** Bit Default Description 1704 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1705 ** The contents of this register are factored into 1706 ** internal policy decisions associated with memory read prefetching, 1707 ** and the promotion of Memory Write transactions to MWI transactions. 1708 ** Valid cache line sizes are 8 and 16 dwords. 1709 ** When the cache line size is set to an invalid value, 1710 ** bridge behaves as though the cache line size was set to 00h. 1711 **============================================================================== 1712 */ 1713 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1714 /* 1715 **============================================================================== 1716 ** 0x0d : latency timer (number of pci clock 00-ff ) 1717 ** Bit Default Description 1718 ** Primary Latency Timer (PTV): 1719 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1720 ** referenced from the assertion of FRAME# to the expiration of the timer, 1721 ** when bridge may continue as master of the current transaction. All bits are writable, 1722 ** resulting in a granularity of 1 PCI clock cycle. 1723 ** When the timer expires (i.e., equals 00h) 1724 ** bridge relinquishes the bus after the first data transfer 1725 ** when its PCI bus grant has been deasserted. 1726 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1727 ** Indicates the number of PCI clock cycles, 1728 ** referenced from the assertion of FRAME# to the expiration of the timer, 1729 ** when bridge may continue as master of the current transaction. 1730 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1731 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1732 ** (Except in the case where MLT expires within 3 data phases 1733 ** of an ADB.In this case bridge continues on 1734 ** until it reaches the next ADB before relinquishing the bus.) 1735 **============================================================================== 1736 */ 1737 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1738 /* 1739 **============================================================================== 1740 ** 0x0e : (header type,single function ) 1741 ** Bit Default Description 1742 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1743 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1744 ** Returns ��01h�� when read indicating 1745 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1746 **============================================================================== 1747 */ 1748 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1749 /* 1750 **============================================================================== 1751 ** 0x0f : 1752 **============================================================================== 1753 */ 1754 /* 1755 **============================================================================== 1756 ** 0x13-0x10 : 1757 ** PCI CFG Base Address #0 (0x10) 1758 **============================================================================== 1759 */ 1760 /* 1761 **============================================================================== 1762 ** 0x17-0x14 : 1763 ** PCI CFG Base Address #1 (0x14) 1764 **============================================================================== 1765 */ 1766 /* 1767 **============================================================================== 1768 ** 0x1b-0x18 : 1769 ** PCI CFG Base Address #2 (0x18) 1770 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1771 ** Bit Default Description 1772 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1773 ** Any Type 1 configuration cycle 1774 ** on the primary bus whose bus number is greater than the secondary bus number, 1775 ** and less than or equal to the subordinate bus number 1776 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1777 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1778 ** Any Type 1 configuration cycle matching this bus number 1779 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1780 ** before being executed on bridge's secondary PCI bus. 1781 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1782 ** Any Type 1 configuration cycle on the primary interface 1783 ** with a bus number that is less than the contents 1784 ** of this register field does not be claimed by bridge. 1785 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1786 ** Bit Default Description 1787 ** Secondary Latency Timer (STV): 1788 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1789 ** Indicates the number of PCI clock cycles, 1790 ** referenced from the assertion of FRAME# to the expiration of the timer, 1791 ** when bridge may continue as master of the current transaction. All bits are writable, 1792 ** resulting in a granularity of 1 PCI clock cycle. 1793 ** When the timer expires (i.e., equals 00h) 1794 ** bridge relinquishes the bus after the first data transfer 1795 ** when its PCI bus grant has been deasserted. 1796 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1797 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1798 ** to the expiration of the timer, 1799 ** when bridge may continue as master of the current transaction. All bits are writable, 1800 ** resulting in a granularity of 1 PCI clock cycle. 1801 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1802 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1803 ** In this case bridge continues on until it reaches the next ADB 1804 ** before relinquishing the bus) 1805 **============================================================================== 1806 */ 1807 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1808 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1809 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1810 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1811 /* 1812 **============================================================================== 1813 ** 0x1f-0x1c : 1814 ** PCI CFG Base Address #3 (0x1C) 1815 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1816 ** Bit Default Description 1817 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1818 ** determine when to forward I/O transactions from one interface to the other. 1819 ** These bits correspond to address lines 15:12 for 4KB alignment. 1820 ** Bits 11:0 are assumed to be FFFh. 1821 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1822 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1823 ** an address range to determine when to forward I/O transactions 1824 ** from one interface to the other. 1825 ** These bits correspond to address lines 15:12 for 4KB alignment. 1826 ** Bits 11:0 are assumed to be 000h. 1827 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1828 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1829 ** Bit Default Description 1830 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1831 ** attribute or data parity error on its secondary interface. 1832 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1833 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1834 ** acting as the initiator on the secondary bus, 1835 ** it's transaction (with the exception of special cycles) 1836 ** has been terminated with a Master Abort. 1837 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1838 ** acting as the initiator on the secondary bus, 1839 ** it's transaction has been terminated with a Target Abort. 1840 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1841 ** as the target of a transaction, terminates it with a Target Abort. 1842 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1843 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1844 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1845 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1846 ** The bridge is the current master on the secondary bus 1847 ** S_PERR# is detected asserted or is asserted by bridge 1848 ** The Parity Error Response bit is set in the Command register 1849 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1850 ** 06 0b Reserved 1851 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1852 ** 1 = 1853 ** 04:00 00h Reserved 1854 **============================================================================== 1855 */ 1856 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1857 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1858 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1859 /* 1860 **============================================================================== 1861 ** 0x23-0x20 : 1862 ** PCI CFG Base Address #4 (0x20) 1863 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1864 ** Bit Default Description 1865 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1866 ** the upper 1MB aligned value (exclusive) of the range. 1867 ** The incoming address must be less than or equal to this value. 1868 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1869 ** are assumed to be F FFFFh. 1870 ** 19:16 0h Reserved. 1871 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1872 ** of the incoming address to determine the lower 1MB 1873 ** aligned value (inclusive) of the range. 1874 ** The incoming address must be greater than or equal to this value. 1875 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1876 ** are assumed to be 0 0000h. 1877 ** 03:00 0h Reserved. 1878 **============================================================================== 1879 */ 1880 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1881 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1882 /* 1883 **============================================================================== 1884 ** 0x27-0x24 : 1885 ** PCI CFG Base Address #5 (0x24) 1886 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1887 ** Bit Default Description 1888 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1889 ** the upper 1MB aligned value (exclusive) of the range. 1890 ** The incoming address must be less than or equal to this value. 1891 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1892 ** are assumed to be F FFFFh. 1893 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1894 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1895 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1896 ** of the range. 1897 ** The incoming address must be greater than or equal to this value. 1898 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1899 ** are assumed to be 0 0000h. 1900 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1901 **============================================================================== 1902 */ 1903 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1904 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1905 /* 1906 **============================================================================== 1907 ** 0x2b-0x28 : 1908 ** Bit Default Description 1909 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1910 ** bridge supports full 64-bit addressing. 1911 **============================================================================== 1912 */ 1913 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1914 /* 1915 **============================================================================== 1916 ** 0x2f-0x2c : 1917 ** Bit Default Description 1918 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1919 ** bridge supports full 64-bit addressing. 1920 **============================================================================== 1921 */ 1922 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1923 /* 1924 **============================================================================== 1925 ** 0x33-0x30 : 1926 ** Bit Default Description 1927 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1928 ** space. (Power Management Capability Registers) 1929 **============================================================================== 1930 */ 1931 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1932 /* 1933 **============================================================================== 1934 ** 0x3b-0x35 : reserved 1935 **============================================================================== 1936 */ 1937 /* 1938 **============================================================================== 1939 ** 0x3d-0x3c : 1940 ** 1941 ** Bit Default Description 1942 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1943 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1944 **============================================================================== 1945 */ 1946 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1947 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1948 /* 1949 **============================================================================== 1950 ** 0x3f-0x3e : 1951 ** Bit Default Description 1952 ** 15:12 0h Reserved 1953 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1954 ** to a timer discard on either the primary or secondary interface. 1955 ** 0b=SERR# is not asserted. 1956 ** 1b=SERR# is asserted. 1957 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1958 ** The delayed completion is then discarded. 1959 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1960 ** that bridge waits for an initiator on the secondary bus 1961 ** to repeat a delayed transaction request. 1962 ** The counter starts when the delayed transaction completion is ready 1963 ** to be returned to the initiator. 1964 ** When the initiator has not repeated the transaction 1965 ** at least once before the counter expires,bridge 1966 ** discards the delayed transaction from its queues. 1967 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1968 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1969 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1970 ** that bridge waits for an initiator on the primary bus 1971 ** to repeat a delayed transaction request. 1972 ** The counter starts when the delayed transaction completion 1973 ** is ready to be returned to the initiator. 1974 ** When the initiator has not repeated the transaction 1975 ** at least once before the counter expires, 1976 ** bridge discards the delayed transaction from its queues. 1977 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1978 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1979 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1980 ** 06 0b Secondary Bus Reset (SBR): 1981 ** When cleared to 0b: The bridge deasserts S_RST#, 1982 ** when it had been asserted by writing this bit to a 1b. 1983 ** When set to 1b: The bridge asserts S_RST#. 1984 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1985 ** when a master abort termination occurs in response to 1986 ** a delayed transaction initiated by bridge on the target bus. 1987 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1988 ** and returns FFFF FFFFh when a read. 1989 ** 1b=When the transaction had not yet been completed on the initiator bus 1990 ** (e.g.,delayed reads, or non-posted writes), 1991 ** then bridge returns a Target Abort in response to the original requester 1992 ** when it returns looking for its delayed completion on the initiator bus. 1993 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1994 ** then bridge asserts P_SERR# (when enabled). 1995 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1996 ** while attempting to deliver a posted memory write on the destination bus. 1997 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1998 ** (also of this register), 1999 ** and the VGA Palette Snoop Enable bit (Command Register). 2000 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 2001 ** the VGA Aliasing bit for the corresponding enabled functionality,: 2002 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 2003 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 2004 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 2005 ** then this bit has no impact on bridge behavior. 2006 ** 03 0b VGA Enable: Setting this bit enables address decoding 2007 ** and transaction forwarding of the following VGA transactions from the primary bus 2008 ** to the secondary bus: 2009 ** frame buffer memory addresses 000A0000h:000BFFFFh, 2010 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 2011 ** or must be ��000000b�� 2012 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 2013 ** I/O and Memory Enable bits must be set in the Command register 2014 ** to enable forwarding of VGA cycles. 2015 ** 02 0b ISA Enable: Setting this bit enables special handling 2016 ** for the forwarding of ISA I/O transactions that fall within the address range 2017 ** specified by the I/O Base and Limit registers, 2018 ** and are within the lowest 64Kbyte of the I/O address map 2019 ** (i.e., 0000 0000h - 0000 FFFFh). 2020 ** 0b=All I/O transactions that fall within the I/O Base 2021 ** and Limit registers' specified range are forwarded 2022 ** from primary to secondary unfiltered. 2023 ** 1b=Blocks the forwarding from primary to secondary 2024 ** of the top 768 bytes of each 1Kbyte alias. 2025 ** On the secondary the top 768 bytes of each 1K alias 2026 ** are inversely decoded and forwarded 2027 ** from secondary to primary. 2028 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 2029 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 2030 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 2031 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 2032 ** that is detected on its secondary interface. 2033 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 2034 ** Also bridge does not assert P_SERR# in response to a detected address 2035 ** or attribute parity error. 2036 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 2037 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 2038 ** of the Command register) 2039 ** in response to a detected address or attribute parity error. 2040 **============================================================================== 2041 */ 2042 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 2043 /* 2044 ************************************************************************** 2045 ** Device Specific Registers 40-A7h 2046 ************************************************************************** 2047 ** ---------------------------------------------------------------------------------------------------------- 2048 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2049 ** ---------------------------------------------------------------------------------------------------------- 2050 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 2051 ** ---------------------------------------------------------------------------------------------------------- 2052 ** | Bridge Control 2 | Bridge Control 1 | 44h 2053 ** ---------------------------------------------------------------------------------------------------------- 2054 ** | Reserved | Bridge Status | 48h 2055 ** ---------------------------------------------------------------------------------------------------------- 2056 ** | Reserved | 4Ch 2057 ** ---------------------------------------------------------------------------------------------------------- 2058 ** | Prefetch Policy | Multi-Transaction Timer | 50h 2059 ** ---------------------------------------------------------------------------------------------------------- 2060 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 2061 ** ---------------------------------------------------------------------------------------------------------- 2062 ** | Reserved | Reserved | Secondary Decode Enable | 58h 2063 ** ---------------------------------------------------------------------------------------------------------- 2064 ** | Reserved | Secondary IDSEL | 5Ch 2065 ** ---------------------------------------------------------------------------------------------------------- 2066 ** | Reserved | 5Ch 2067 ** ---------------------------------------------------------------------------------------------------------- 2068 ** | Reserved | 68h:CBh 2069 ** ---------------------------------------------------------------------------------------------------------- 2070 ************************************************************************** 2071 **============================================================================== 2072 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 2073 ** Bit Default Description 2074 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 2075 ** (PCI=16 clocks,PCI-X=6 clocks). 2076 ** Note that this field is only meaningful when: 2077 ** # Bit[11] of this register is set to 1b, 2078 ** indicating that a Grant Time-out violation had occurred. 2079 ** # bridge internal arbiter is enabled. 2080 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 2081 ** 0000b REQ#/GNT#[0] 2082 ** 0001b REQ#/GNT#[1] 2083 ** 0010b REQ#/GNT#[2] 2084 ** 0011b REQ#/GNT#[3] 2085 ** 1111b Default Value (no violation detected) 2086 ** When bit[11] is cleared by software, this field reverts back to its default value. 2087 ** All other values are Reserved 2088 ** 11 0b Grant Time-out Occurred: When set to 1b, 2089 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 2090 ** Software clears this bit by writing a 1b to it. 2091 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 2092 ** 1=During bus idle, bridge parks the bus on itself. 2093 ** The bus grant is removed from the last master and internally asserted to bridge. 2094 ** 09:08 00b Reserved 2095 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 2096 ** Each bit of this field assigns its corresponding secondary 2097 ** bus master to either the high priority arbiter ring (1b) 2098 ** or to the low priority arbiter ring (0b). 2099 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 2100 ** Bit [6] corresponds to the bridge internal secondary bus request 2101 ** while Bit [7] corresponds to the SATU secondary bus request. 2102 ** Bits [5:4] are unused. 2103 ** 0b=Indicates that the master belongs to the low priority group. 2104 ** 1b=Indicates that the master belongs to the high priority group 2105 **================================================================================= 2106 ** 0x43: Bridge Control Register 0 - BCR0 2107 ** Bit Default Description 2108 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 2109 ** and the Posted Write data is limited to 4KB. 2110 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 2111 ** 14 Posted Memory Write transactions and 8KB of posted write data. 2112 ** 06:03 0H Reserved. 2113 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 2114 ** to perform upstream prefetch operations for Memory 2115 ** Read requests received on its secondary interface. 2116 ** This bit also controls the bridge's ability to generate advanced read commands 2117 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 2118 ** to a Conventional PCI bus. 2119 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 2120 ** The use of Memory Read Line and Memory Read 2121 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 2122 ** to an upstream bus operating in Conventional PCI mode. 2123 ** 1b=bridge treats upstream PCI Memory Read requests as though 2124 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 2125 ** Read Block commands as Memory Read 2126 ** when the primary bus is operating 2127 ** in Conventional PCI mode. 2128 ** NOTE: This bit does not affect bridge ability to perform read prefetching 2129 ** when the received command is Memory Read Line or Memory Read Multiple. 2130 **================================================================================= 2131 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 2132 ** Bit Default Description 2133 ** 15:08 0000000b Reserved 2134 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 2135 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 2136 ** The three options for handling these alias commands are to either pass it as is, 2137 ** re-map to the actual block memory read/write command encoding, or ignore 2138 ** the transaction forcing a Master Abort to occur on the Origination Bus. 2139 ** Bit (7:6) Handling of command 2140 ** 0 0 Re-map to Memory Read/Write Block before forwarding 2141 ** 0 1 Enqueue and forward the alias command code unaltered 2142 ** 1 0 Ignore the transaction, forcing Master Abort 2143 ** 1 1 Reserved 2144 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 2145 ** The watchdog timers are used to detect prohibitively long latencies in the system. 2146 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 2147 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 2148 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 2149 ** and as the number of times being retried when operating in Conventional PCI mode) 2150 ** 0b=All 2 24 watchdog timers are enabled. 2151 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 2152 ** the number of attempts bridge makes when initiating a PMW, 2153 ** transacting a Delayed Transaction, or how long it waits for 2154 ** a split completion corresponding to one of its requests. 2155 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 2156 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 2157 ** 0b=The Secondary bus arbiter times out an agent 2158 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 2159 ** once the bus has gone idle. 2160 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 2161 ** An infringing agent does not receive a subsequent GNT# 2162 ** until it de-asserts its REQ# for at least one clock cycle. 2163 ** 1b=GNT# time-out mechanism is disabled. 2164 ** 03 00b Reserved. 2165 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 2166 ** The time out mechanism is used to ensure that initiators 2167 ** of delayed transactions return for their delayed completion data/status 2168 ** within a reasonable amount of time after it is available from bridge. 2169 ** 0b=The secondary master time-out counter is enabled 2170 ** and uses the value specified by the Secondary Discard Timer bit 2171 ** (see Bridge Control Register). 2172 ** 1b=The secondary master time-out counter is disabled. 2173 ** The bridge waits indefinitely for a secondary bus master 2174 ** to repeat a delayed transaction. 2175 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 2176 ** The time out mechanism is used to ensure that initiators 2177 ** of delayed transactions return for their delayed completion data/status 2178 ** within a reasonable amount of time after it is available from bridge. 2179 ** 0b=The primary master time-out counter is enabled and uses the value specified 2180 ** by the Primary Discard Timer bit (see Bridge Control Register). 2181 ** 1b=The secondary master time-out counter is disabled. 2182 ** The bridge waits indefinitely for a secondary bus master 2183 ** to repeat a delayed transaction. 2184 ** 00 0b Reserved 2185 **================================================================================= 2186 ** 0x47-0x46: Bridge Control Register 2 - BCR2 2187 ** Bit Default Description 2188 ** 15:07 0000b Reserved. 2189 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 2190 ** This bit disables all of the secondary PCI clock outputs including 2191 ** the feedback clock S_CLKOUT. 2192 ** This means that the user is required to provide an S_CLKIN input source. 2193 ** 05:04 11 (66 MHz) Preserved. 2194 ** 01 (100 MHz) 2195 ** 00 (133 MHz) 2196 ** 03:00 Fh (100 MHz & 66 MHz) 2197 ** 7h (133 MHz) 2198 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 2199 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 2200 ** default to being enabled following the rising edge of P_RST#, depending on the 2201 ** frequency of the secondary bus clock: 2202 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 2203 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 2204 ** �E Designs with 133 MHz Secondary PCI clock power up 2205 ** with the lower order 3 S_CLKOs enabled by default. 2206 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 2207 ** to downstream device clock inputs. 2208 **================================================================================= 2209 ** 0x49-0x48: Bridge Status Register - BSR 2210 ** Bit Default Description 2211 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2212 ** is conditionally asserted when the secondary discard timer expires. 2213 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 2214 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2215 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 2216 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2217 ** when bridge discards an upstream split read request 2218 ** after waiting in excess of 2 24 clocks for the corresponding 2219 ** Split Completion to arrive. 2220 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 2221 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2222 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 2223 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2224 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 2225 ** Split Completion to arrive. 2226 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2227 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2228 ** by bridge, to retire a PMW upstream. 2229 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2230 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 2231 ** by bridge, to retire a PMW upstream. 2232 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2233 ** is conditionally asserted when bridge discards an upstream PMW transaction 2234 ** after receiving 2 24 target retries from the primary bus target 2235 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2236 ** is conditionally asserted when a data parity error is detected by bridge 2237 ** while attempting to retire a PMW upstream 2238 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 2239 ** is conditionally asserted when bridge detects an address parity error on 2240 ** the secondary bus. 2241 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2242 ** is conditionally asserted when the primary bus discard timer expires. 2243 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 2244 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2245 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 2246 ** from the secondary bus target. 2247 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2248 ** when bridge discards a downstream split read request 2249 ** after waiting in excess of 2 24 clocks for the corresponding 2250 ** Split Completion to arrive. 2251 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 2252 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2253 ** when bridge discards a downstream delayed write transaction request 2254 ** after receiving 2 24 target retries from the secondary bus target. 2255 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2256 ** is conditionally asserted when bridge discards a downstream 2257 ** split write request after waiting in excess of 2 24 clocks 2258 ** for the corresponding Split Completion to arrive. 2259 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 2260 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2261 ** by bridge, to retire a PMW downstream. 2262 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 2263 ** when a Target Abort occurs as a result of an attempt, by bridge, 2264 ** to retire a PMW downstream. 2265 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2266 ** is conditionally asserted when bridge discards a downstream PMW transaction 2267 ** after receiving 2 24 target retries from the secondary bus target 2268 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2269 ** is conditionally asserted when a data parity error is detected by bridge 2270 ** while attempting to retire a PMW downstream. 2271 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 2272 ** when bridge detects an address parity error on the primary bus. 2273 **================================================================================== 2274 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2275 ** Bit Default Description 2276 ** 15:13 000b Reserved 2277 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2278 ** that a secondary bus master has its grant maintained in order to enable 2279 ** multiple transactions to execute within the same arbitration cycle. 2280 ** Bit[02:00] GNT# Extended Duration 2281 ** 000 MTT Disabled (Default=no GNT# extension) 2282 ** 001 16 clocks 2283 ** 010 32 clocks 2284 ** 011 64 clocks 2285 ** 100 128 clocks 2286 ** 101 256 clocks 2287 ** 110 Invalid (treated as 000) 2288 ** 111 Invalid (treated as 000) 2289 ** 09:08 00b Reserved 2290 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2291 ** pair supported by bridge secondary arbiter. 2292 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2293 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2294 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2295 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 2296 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2297 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2298 **================================================================================== 2299 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 2300 ** Bit Default Description 2301 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2302 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2303 ** using the FirstRead parameter. 2304 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2305 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2306 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2307 ** the number of bytes to prefetch from the secondary bus interface 2308 ** on the initial PreFetch operation. 2309 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2310 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2311 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2312 ** in calculating the number of bytes to prefetch from the primary 2313 ** bus interface on subsequent PreFetch operations given 2314 ** that the read demands were not satisfied using 2315 ** the FirstRead parameter. 2316 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2317 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2318 ** Memory Read Multiple 6 cache lines 2319 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2320 ** in calculating the number of bytes to prefetch from 2321 ** the primary bus interface on the initial PreFetch operation. 2322 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2323 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2324 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2325 ** algorithm for the secondary and the primary bus interfaces. 2326 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2327 ** enable bits for REQ#/GNT#[2:0]. 2328 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2329 ** 1b: enables the staged pre-fetch feature 2330 ** 0b: disables staged pre-fetch, 2331 ** and hardwires read pre-fetch policy to the following for 2332 ** Memory Read, 2333 ** Memory Read Line, 2334 ** and Memory Read Multiple commands: 2335 ** Command Type Hardwired Pre-Fetch Amount... 2336 ** Memory Read 4 DWORDs 2337 ** Memory Read Line 1 cache line 2338 ** Memory Read Multiple 2 cache lines 2339 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2340 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2341 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2342 **================================================================================== 2343 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2344 ** Bit Default Description 2345 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2346 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2347 ** 0b=bridge asserts P_SERR#. 2348 ** 1b=bridge does not assert P_SERR# 2349 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2350 ** 0b=bridge asserts P_SERR#. 2351 ** 1b=bridge does not assert P_SERR# 2352 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2353 ** 0b=bridge asserts P_SERR#. 2354 ** 1b=bridge does not assert P_SERR# 2355 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2356 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2357 ** 0b=bridge asserts P_SERR#. 2358 ** 1b=bridge does not assert P_SERR# 2359 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2360 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2361 ** 0b=bridge asserts P_SERR#. 2362 ** 1b=bridge does not assert P_SERR# 2363 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2364 ** it discards an upstream posted write transaction. 2365 ** 0b=bridge asserts P_SERR#. 2366 ** 1b=bridge does not assert P_SERR# 2367 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2368 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2369 ** 0b=bridge asserts P_SERR#. 2370 ** 1b=bridge does not assert P_SERR# 2371 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2372 ** when it detects an address parity error on the secondary bus. 2373 ** 0b=bridge asserts P_SERR#. 2374 ** 1b=bridge does not assert P_SERR# 2375 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2376 ** its discarding of a delayed transaction that was initiated on the secondary bus. 2377 ** 0b=bridge asserts P_SERR#. 2378 ** 1b=bridge does not assert P_SERR# 2379 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2380 ** 0b=bridge asserts P_SERR#. 2381 ** 1b=bridge does not assert P_SERR# 2382 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2383 ** 0b=bridge asserts P_SERR#. 2384 ** 1b=bridge does not assert P_SERR# 2385 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2386 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2387 ** 0b=bridge asserts P_SERR#. 2388 ** 1b=bridge does not assert P_SERR# 2389 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2390 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2391 ** 0b=bridge asserts P_SERR#. 2392 ** 1b=bridge does not assert P_SERR# 2393 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2394 ** that it discards a downstream posted write transaction. 2395 ** 0b=bridge asserts P_SERR#. 2396 ** 1b=bridge does not assert P_SERR# 2397 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2398 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2399 ** 0b=bridge asserts P_SERR#. 2400 ** 1b=bridge does not assert P_SERR# 2401 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2402 ** when it detects an address parity error on the primary bus. 2403 ** 0b=bridge asserts P_SERR#. 2404 ** 1b=bridge does not assert P_SERR# 2405 **=============================================================================== 2406 ** 0x56: Pre-Boot Status Register - PBSR 2407 ** Bit Default Description 2408 ** 07 1 Reserved 2409 ** 06 - Reserved - value indeterminate 2410 ** 05:02 0 Reserved 2411 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2412 ** This bit reflect captured S_133EN strap, 2413 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2414 ** Max Allowable Secondary Bus Frequency 2415 ** ** S_133EN PCI-X Mode 2416 ** ** 0 100 MHz 2417 ** ** 1 133 MH 2418 ** 00 0b Reserved 2419 **=============================================================================== 2420 ** 0x59-0x58: Secondary Decode Enable Register - SDER 2421 ** Bit Default Description 2422 ** 15:03 FFF1h Preserved. 2423 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2424 ** bridge overrides its secondary inverse decode logic and not 2425 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2426 ** This creates a private memory space on the Secondary PCI bus 2427 ** that allows peer-to-peer transactions. 2428 ** 01:00 10 2 Preserved. 2429 **=============================================================================== 2430 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2431 ** Bit Default Description 2432 ** 15:10 000000 2 Reserved. 2433 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2434 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2435 ** When this bit is clear, 2436 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2437 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2438 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2439 ** When this bit is clear, 2440 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2441 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2442 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2443 ** When this bit is clear, 2444 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2445 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2446 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2447 ** When this bit is clear, 2448 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2449 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2450 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2451 ** When this bit is clear, 2452 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2453 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2454 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2455 ** When this bit is clear, 2456 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2457 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2458 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2459 ** When this bit is clear, 2460 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2461 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2462 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2463 ** When this bit is clear, 2464 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2465 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2466 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2467 ** When this bit is clear, 2468 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2469 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2470 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2471 ** When this bit is clear, 2472 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2473 ************************************************************************** 2474 */ 2475 /* 2476 ************************************************************************** 2477 ** Reserved A8-CBh 2478 ************************************************************************** 2479 */ 2480 /* 2481 ************************************************************************** 2482 ** PCI Extended Enhanced Capabilities List CC-FFh 2483 ************************************************************************** 2484 ** ---------------------------------------------------------------------------------------------------------- 2485 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2486 ** ---------------------------------------------------------------------------------------------------------- 2487 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2488 ** ---------------------------------------------------------------------------------------------------------- 2489 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2490 ** ---------------------------------------------------------------------------------------------------------- 2491 ** | Reserved | Reserved | Reserved | E4h 2492 ** ---------------------------------------------------------------------------------------------------------- 2493 ** | Reserved | E8h 2494 ** ---------------------------------------------------------------------------------------------------------- 2495 ** | Reserved | Reserved | Reserved | Reserved | ECh 2496 ** ---------------------------------------------------------------------------------------------------------- 2497 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2498 ** ---------------------------------------------------------------------------------------------------------- 2499 ** | PCI-X Bridge Status | F4h 2500 ** ---------------------------------------------------------------------------------------------------------- 2501 ** | PCI-X Upstream Split Transaction Control | F8h 2502 ** ---------------------------------------------------------------------------------------------------------- 2503 ** | PCI-X Downstream Split Transaction Control | FCh 2504 ** ---------------------------------------------------------------------------------------------------------- 2505 **=============================================================================== 2506 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2507 ** Bit Default Description 2508 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2509 **=============================================================================== 2510 ** 0xDD: Next Item Pointer - PM_NXTP 2511 ** Bit Default Description 2512 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2513 **=============================================================================== 2514 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2515 ** Bit Default Description 2516 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2517 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2518 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2519 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2520 ** This returns 000b as PME# wake-up for bridge is not implemented. 2521 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2522 ** 04:03 00 Reserved 2523 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2524 **=============================================================================== 2525 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2526 ** Bit Default Description 2527 ** 15:09 00h Reserved 2528 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2529 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2530 ** 07:02 00h Reserved 2531 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2532 ** a function and to set the Function into a new power state. 2533 ** 00 - D0 state 2534 ** 01 - D1 state 2535 ** 10 - D2 state 2536 ** 11 - D3 hot state 2537 **=============================================================================== 2538 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2539 ** Bit Default Description 2540 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2541 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2542 ** is to occur as a direct result of programming the function to D3 hot. 2543 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2544 ** 05:00 00h Reserved 2545 **=============================================================================== 2546 ** 0xE3: Power Management Data Register - PMDR 2547 ** Bit Default Description 2548 ** 07:00 00h Reserved 2549 **=============================================================================== 2550 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2551 ** Bit Default Description 2552 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2553 **=============================================================================== 2554 ** 0xF1: Next Item Pointer - PX_NXTP 2555 ** Bit Default Description 2556 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2557 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2558 **=============================================================================== 2559 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2560 ** Bit Default Description 2561 ** 15:09 00h Reserved 2562 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2563 ** The values are: 2564 ** ** BitsMax FrequencyClock Period 2565 ** ** 000PCI ModeN/A 2566 ** ** 00166 15 2567 ** ** 01010010 2568 ** ** 0111337.5 2569 ** ** 1xxreservedreserved 2570 ** ** The default value for this register is the operating frequency of the secondary bus 2571 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2572 ** secondary bus to the primary bus because there is not enough room within the limit 2573 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2574 ** Transaction Control register. The bridge does not set this bit. 2575 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2576 ** The bridge does not set this bit. 2577 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2578 ** equal to bridge secondary bus number, device number 00h, 2579 ** and function number 0 is received on the secondary interface. 2580 ** This bit is cleared by software writing a '1'. 2581 ** 02 0b Split Completion Discarded (SCD): This bit is set 2582 ** when bridge discards a split completion moving toward the secondary bus 2583 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2584 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2585 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2586 **=============================================================================== 2587 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2588 ** Bit Default Description 2589 ** 31:22 0 Reserved 2590 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2591 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2592 ** because bridge throttles traffic on the completion side. 2593 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2594 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2595 ** this bit by writing a 1b to it. 2596 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2597 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2598 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2599 ** 0=The maximum operating frequency is 66 MHz. 2600 ** 1=The maximum operating frequency is 133 MHz. 2601 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2602 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2603 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2604 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2605 ** of the BNUM register at offset 18h. 2606 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2607 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2608 ** May be updated whenever a PCI-X 2609 ** configuration write cycle that targets bridge scores a hit. 2610 ** 02:00 0h Function Number (FNUM): The bridge Function # 2611 **=============================================================================== 2612 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2613 ** Bit Default Description 2614 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2615 ** Software is permitted to program this register to any value greater than or equal to 2616 ** the contents of the Split Transaction Capacity register. A value less than the contents 2617 ** of the Split Transaction Capacity register causes unspecified results. 2618 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2619 ** size regardless of the amount of buffer space available. 2620 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2621 ** split completions. This register controls behavior of the bridge buffers for forwarding 2622 ** Split Transactions from a primary bus requester to a secondary bus completer. 2623 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2624 **=============================================================================== 2625 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2626 ** Bit Default Description 2627 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2628 ** Software is permitted to program this register to any value greater than or equal to 2629 ** the contents of the Split Transaction Capacity register. A value less than the contents 2630 ** of the Split Transaction Capacity register causes unspecified results. 2631 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2632 ** size regardless of the amount of buffer space available. 2633 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2634 ** split completions. This register controls behavior of the bridge buffers for forwarding 2635 ** Split Transactions from a primary bus requester to a secondary bus completer. 2636 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2637 ** (7936 bytes). 2638 ************************************************************************** 2639 */ 2640 2641 /* 2642 ************************************************************************************************************************************* 2643 ** 80331 Address Translation Unit Register Definitions 2644 ** ATU Interface Configuration Header Format 2645 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2646 ************************************************************************************************************************************* 2647 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2648 **=================================================================================================================================== 2649 ** | ATU Device ID | Vendor ID | 00h 2650 ** ---------------------------------------------------------------------------------------------------------- 2651 ** | Status | Command | 04H 2652 ** ---------------------------------------------------------------------------------------------------------- 2653 ** | ATU Class Code | Revision ID | 08H 2654 ** ---------------------------------------------------------------------------------------------------------- 2655 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2656 ** ---------------------------------------------------------------------------------------------------------- 2657 ** | Inbound ATU Base Address 0 | 10H 2658 ** ---------------------------------------------------------------------------------------------------------- 2659 ** | Inbound ATU Upper Base Address 0 | 14H 2660 ** ---------------------------------------------------------------------------------------------------------- 2661 ** | Inbound ATU Base Address 1 | 18H 2662 ** ---------------------------------------------------------------------------------------------------------- 2663 ** | Inbound ATU Upper Base Address 1 | 1CH 2664 ** ---------------------------------------------------------------------------------------------------------- 2665 ** | Inbound ATU Base Address 2 | 20H 2666 ** ---------------------------------------------------------------------------------------------------------- 2667 ** | Inbound ATU Upper Base Address 2 | 24H 2668 ** ---------------------------------------------------------------------------------------------------------- 2669 ** | Reserved | 28H 2670 ** ---------------------------------------------------------------------------------------------------------- 2671 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2672 ** ---------------------------------------------------------------------------------------------------------- 2673 ** | Expansion ROM Base Address | 30H 2674 ** ---------------------------------------------------------------------------------------------------------- 2675 ** | Reserved Capabilities Pointer | 34H 2676 ** ---------------------------------------------------------------------------------------------------------- 2677 ** | Reserved | 38H 2678 ** ---------------------------------------------------------------------------------------------------------- 2679 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2680 ** ---------------------------------------------------------------------------------------------------------- 2681 ********************************************************************************************************************* 2682 */ 2683 /* 2684 *********************************************************************************** 2685 ** ATU Vendor ID Register - ATUVID 2686 ** ----------------------------------------------------------------- 2687 ** Bit Default Description 2688 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2689 ** This register, combined with the DID, uniquely identify the PCI device. 2690 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2691 ** to simulate the interface of a standard mechanism currently used by existing application software. 2692 *********************************************************************************** 2693 */ 2694 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2695 /* 2696 *********************************************************************************** 2697 ** ATU Device ID Register - ATUDID 2698 ** ----------------------------------------------------------------- 2699 ** Bit Default Description 2700 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2701 ** This ID, combined with the VID, uniquely identify any PCI device. 2702 *********************************************************************************** 2703 */ 2704 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2705 /* 2706 *********************************************************************************** 2707 ** ATU Command Register - ATUCMD 2708 ** ----------------------------------------------------------------- 2709 ** Bit Default Description 2710 ** 15:11 000000 2 Reserved 2711 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2712 ** 0=enables the assertion of interrupt signal. 2713 ** 1=disables the assertion of its interrupt signal. 2714 ** 09 0 2 Fast Back to Back Enable - When cleared, 2715 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2716 ** Ignored when operating in the PCI-X mode. 2717 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2718 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2719 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2720 ** of address stepping for PCI-X mode. 2721 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2722 ** is detected. When cleared, parity checking is disabled. 2723 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2724 ** does not perform VGA palette snooping. 2725 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2726 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2727 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2728 ** Not implemented and a reserved bit field. 2729 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2730 ** When cleared, disables the device from generating PCI accesses. 2731 ** When set, allows the device to behave as a PCI bus master. 2732 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2733 ** of the state of this bit. 2734 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2735 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2736 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2737 ** Not implemented and a reserved bit field. 2738 *********************************************************************************** 2739 */ 2740 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2741 /* 2742 *********************************************************************************** 2743 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2744 ** ----------------------------------------------------------------- 2745 ** Bit Default Description 2746 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2747 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2748 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2749 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2750 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2751 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2752 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2753 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2754 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2755 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2756 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2757 ** terminates the transaction on the PCI bus with a target abort. 2758 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2759 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2760 ** (except configuration accesses). 2761 ** 00 2=Fast 2762 ** 01 2=Medium 2763 ** 10 2=Slow 2764 ** 11 2=Reserved 2765 ** The ATU interface uses Medium timing. 2766 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2767 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2768 ** �E And the ATU acted as the requester 2769 ** for the operation in which the error occurred. 2770 ** �E And the ATUCMD register��s Parity Error Response bit is set 2771 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2772 ** �E And the ATUCMD register��s Parity Error Response bit is set 2773 ** 07 1 2 (Conventional mode) 2774 ** 0 2 (PCI-X mode) 2775 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2776 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2777 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2778 ** 06 0 2 UDF Supported - User Definable Features are not supported 2779 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2780 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2781 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2782 ** when the Interrupt Disable bit in the command register is a 0. 2783 ** 0=ATU interrupt signal deasserted. 2784 ** 1=ATU interrupt signal asserted. 2785 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2786 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2787 ** interrupt signal. 2788 ** 02:00 00000 2 Reserved. 2789 *********************************************************************************** 2790 */ 2791 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2792 /* 2793 *********************************************************************************** 2794 ** ATU Revision ID Register - ATURID 2795 ** ----------------------------------------------------------------- 2796 ** Bit Default Description 2797 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2798 *********************************************************************************** 2799 */ 2800 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2801 /* 2802 *********************************************************************************** 2803 ** ATU Class Code Register - ATUCCR 2804 ** ----------------------------------------------------------------- 2805 ** Bit Default Description 2806 ** 23:16 05H Base Class - Memory Controller 2807 ** 15:08 80H Sub Class - Other Memory Controller 2808 ** 07:00 00H Programming Interface - None defined 2809 *********************************************************************************** 2810 */ 2811 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2812 /* 2813 *********************************************************************************** 2814 ** ATU Cacheline Size Register - ATUCLSR 2815 ** ----------------------------------------------------------------- 2816 ** Bit Default Description 2817 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2818 *********************************************************************************** 2819 */ 2820 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2821 /* 2822 *********************************************************************************** 2823 ** ATU Latency Timer Register - ATULT 2824 ** ----------------------------------------------------------------- 2825 ** Bit Default Description 2826 ** 07:03 00000 2 (for Conventional mode) 2827 ** 01000 2 (for PCI-X mode) 2828 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2829 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2830 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2831 *********************************************************************************** 2832 */ 2833 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2834 /* 2835 *********************************************************************************** 2836 ** ATU Header Type Register - ATUHTR 2837 ** ----------------------------------------------------------------- 2838 ** Bit Default Description 2839 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2840 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2841 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2842 *********************************************************************************** 2843 */ 2844 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2845 /* 2846 *********************************************************************************** 2847 ** ATU BIST Register - ATUBISTR 2848 ** 2849 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2850 ** initiated. This register is the interface between the host processor requesting BIST functions and 2851 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2852 ** ----------------------------------------------------------------- 2853 ** Bit Default Description 2854 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2855 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2856 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2857 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2858 ** found in ATUBISTR register bits [3:0]. 2859 ** When the ATUCR BIST Interrupt Enable bit is clear: 2860 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2861 ** The Intel XScale core does not clear this bit. 2862 ** 05:04 00 2 Reserved 2863 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2864 ** The Intel XScale core places the results of the software BIST in these bits. 2865 ** A nonzero value indicates a device-specific error. 2866 *********************************************************************************** 2867 */ 2868 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2869 2870 /* 2871 *************************************************************************************** 2872 ** ATU Base Registers and Associated Limit Registers 2873 *************************************************************************************** 2874 ** Base Address Register Limit Register Description 2875 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2876 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2877 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2878 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2879 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2880 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2881 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2882 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2883 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2884 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2885 **-------------------------------------------------------------------------------------- 2886 ** ATU Inbound Window 1 is not a translate window. 2887 ** The ATU does not claim any PCI accesses that fall within this range. 2888 ** This window is used to allocate host memory for use by Private Devices. 2889 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2890 *********************************************************************************** 2891 */ 2892 2893 /* 2894 *********************************************************************************** 2895 ** Inbound ATU Base Address Register 0 - IABAR0 2896 ** 2897 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2898 ** defines the block of memory addresses where the inbound translation window 0 begins. 2899 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2900 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2901 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2902 ** depending on the value located within the IALR0. 2903 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2904 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2905 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2906 ** Warning: 2907 ** When IALR0 is cleared prior to host configuration: 2908 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2909 ** Assuming IALR0 is not cleared: 2910 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2911 ** when the Prefetchable Indicator is cleared prior to host configuration, 2912 ** the user should also set the Type Indicator for 32 bit addressability. 2913 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2914 ** when the Prefetchable Indicator is set prior to host configuration, the user 2915 ** should also set the Type Indicator for 64 bit addressability. 2916 ** This is the default for IABAR0. 2917 ** ----------------------------------------------------------------- 2918 ** Bit Default Description 2919 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2920 ** the translation function is to respond to when addressed from the PCI bus. 2921 ** 11:04 00H Reserved. 2922 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2923 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2924 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2925 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2926 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2927 ** The ATU does not occupy I/O space, 2928 ** thus this bit must be zero. 2929 *********************************************************************************** 2930 */ 2931 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2932 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2933 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2934 /* 2935 *********************************************************************************** 2936 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2937 ** 2938 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2939 ** Together with the Translation Base Address this register defines the actual location the translation 2940 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2941 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2942 ** Note: 2943 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2944 ** the IAUBAR0 register attributes are read-only. 2945 ** ----------------------------------------------------------------- 2946 ** Bit Default Description 2947 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2948 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2949 *********************************************************************************** 2950 */ 2951 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2952 /* 2953 *********************************************************************************** 2954 ** Inbound ATU Base Address Register 1 - IABAR1 2955 ** 2956 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2957 ** defines the block of memory addresses where the inbound translation window 1 begins. 2958 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2959 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2960 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2961 ** Warning: 2962 ** When a non-zero value is not written to IALR1 prior to host configuration, 2963 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2964 ** This is the default for IABAR1. 2965 ** Assuming a non-zero value is written to IALR1, 2966 ** the user may set the Prefetchable Indicator 2967 ** or the Type Indicator: 2968 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2969 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2970 ** the user should also leave the Type Indicator set for 32 bit addressability. 2971 ** This is the default for IABAR1. 2972 ** b. when the Prefetchable Indicator is set prior to host configuration, 2973 ** the user should also set the Type Indicator for 64 bit addressability. 2974 ** ----------------------------------------------------------------- 2975 ** Bit Default Description 2976 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2977 ** 11:04 00H Reserved. 2978 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2979 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2980 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2981 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2982 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2983 ** The ATU does not occupy I/O space, 2984 ** thus this bit must be zero. 2985 *********************************************************************************** 2986 */ 2987 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2988 /* 2989 *********************************************************************************** 2990 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2991 ** 2992 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2993 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2994 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2995 ** The programmed value within the base address register must comply with the PCI programming 2996 ** requirements for address alignment. 2997 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2998 ** from the PCI bus. 2999 ** Note: 3000 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 3001 ** the IAUBAR1 register attributes are read-only. 3002 ** This is the default for IABAR1. 3003 ** ----------------------------------------------------------------- 3004 ** Bit Default Description 3005 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 3006 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 3007 *********************************************************************************** 3008 */ 3009 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 3010 /* 3011 *********************************************************************************** 3012 ** Inbound ATU Base Address Register 2 - IABAR2 3013 ** 3014 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 3015 ** defines the block of memory addresses where the inbound translation window 2 begins. 3016 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3017 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 3018 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 3019 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3020 ** Warning: 3021 ** When a non-zero value is not written to IALR2 prior to host configuration, 3022 ** the user should not set either the Prefetchable Indicator 3023 ** or the Type Indicator for 64 bit addressability. 3024 ** This is the default for IABAR2. 3025 ** Assuming a non-zero value is written to IALR2, 3026 ** the user may set the Prefetchable Indicator 3027 ** or the Type Indicator: 3028 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3029 ** when the Prefetchable Indicator is not set prior to host configuration, 3030 ** the user should also leave the Type Indicator set for 32 bit addressability. 3031 ** This is the default for IABAR2. 3032 ** b. when the Prefetchable Indicator is set prior to host configuration, 3033 ** the user should also set the Type Indicator for 64 bit addressability. 3034 ** ----------------------------------------------------------------- 3035 ** Bit Default Description 3036 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 3037 ** the translation function is to respond to when addressed from the PCI bus. 3038 ** 11:04 00H Reserved. 3039 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3040 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3041 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3042 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3043 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3044 ** The ATU does not occupy I/O space, 3045 ** thus this bit must be zero. 3046 *********************************************************************************** 3047 */ 3048 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 3049 /* 3050 *********************************************************************************** 3051 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 3052 ** 3053 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3054 ** Together with the Translation Base Address this register defines the actual location 3055 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3056 ** The programmed value within the base address register must comply with the PCI programming 3057 ** requirements for address alignment. 3058 ** Note: 3059 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 3060 ** the IAUBAR2 register attributes are read-only. 3061 ** This is the default for IABAR2. 3062 ** ----------------------------------------------------------------- 3063 ** Bit Default Description 3064 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 3065 ** these bits define the actual location the translation function is to respond to 3066 ** when addressed from the PCI bus for addresses > 4GBytes. 3067 *********************************************************************************** 3068 */ 3069 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 3070 /* 3071 *********************************************************************************** 3072 ** ATU Subsystem Vendor ID Register - ASVIR 3073 ** ----------------------------------------------------------------- 3074 ** Bit Default Description 3075 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 3076 *********************************************************************************** 3077 */ 3078 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 3079 /* 3080 *********************************************************************************** 3081 ** ATU Subsystem ID Register - ASIR 3082 ** ----------------------------------------------------------------- 3083 ** Bit Default Description 3084 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 3085 *********************************************************************************** 3086 */ 3087 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 3088 /* 3089 *********************************************************************************** 3090 ** Expansion ROM Base Address Register -ERBAR 3091 ** ----------------------------------------------------------------- 3092 ** Bit Default Description 3093 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 3094 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 3095 ** 11:01 000H Reserved 3096 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 3097 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 3098 *********************************************************************************** 3099 */ 3100 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 3101 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 3102 /* 3103 *********************************************************************************** 3104 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 3105 ** ----------------------------------------------------------------- 3106 ** Bit Default Description 3107 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 3108 ** that points to the 80331 PCl Bus Power Management extended capability. 3109 *********************************************************************************** 3110 */ 3111 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 3112 /* 3113 *********************************************************************************** 3114 ** Determining Block Sizes for Base Address Registers 3115 ** The required address size and type can be determined by writing ones to a base address register and 3116 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 3117 ** address registers upwards, the programmer can determine the required address space size. The 3118 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 3119 ** Table 105 describes the relationship between the values read back and the byte sizes the base 3120 ** address register requires. 3121 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 3122 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 3123 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 3124 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 3125 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 3126 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 3127 ** associated limit registers to enable which bits within the base address register are read/write and 3128 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 3129 ** other PCI devices even though the limit is variable. 3130 ** Table 105. Memory Block Size Read Response 3131 ** Response After Writing all 1s 3132 ** to the Base Address Register 3133 ** Size 3134 ** (Bytes) 3135 ** Response After Writing all 1s 3136 ** to the Base Address Register 3137 ** Size 3138 ** (Bytes) 3139 ** FFFFFFF0H 16 FFF00000H 1 M 3140 ** FFFFFFE0H 32 FFE00000H 2 M 3141 ** FFFFFFC0H 64 FFC00000H 4 M 3142 ** FFFFFF80H 128 FF800000H 8 M 3143 ** FFFFFF00H 256 FF000000H 16 M 3144 ** FFFFFE00H 512 FE000000H 32 M 3145 ** FFFFFC00H 1K FC000000H 64 M 3146 ** FFFFF800H 2K F8000000H 128 M 3147 ** FFFFF000H 4K F0000000H 256 M 3148 ** FFFFE000H 8K E0000000H 512 M 3149 ** FFFFC000H 16K C0000000H 1 G 3150 ** FFFF8000H 32K 80000000H 2 G 3151 ** FFFF0000H 64K 3152 ** 00000000H 3153 ** Register not 3154 ** imple-mented, 3155 ** no 3156 ** address 3157 ** space 3158 ** required. 3159 ** FFFE0000H 128K 3160 ** FFFC0000H 256K 3161 ** FFF80000H 512K 3162 ** 3163 *************************************************************************************** 3164 */ 3165 3166 /* 3167 *********************************************************************************** 3168 ** ATU Interrupt Line Register - ATUILR 3169 ** ----------------------------------------------------------------- 3170 ** Bit Default Description 3171 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 3172 ** request line connects to the device's PCI interrupt request lines 3173 ** (as specified in the interrupt pin register). 3174 ** A value of FFH signifies ��no connection�� or ��unknown��. 3175 *********************************************************************************** 3176 */ 3177 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 3178 /* 3179 *********************************************************************************** 3180 ** ATU Interrupt Pin Register - ATUIPR 3181 ** ----------------------------------------------------------------- 3182 ** Bit Default Description 3183 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 3184 *********************************************************************************** 3185 */ 3186 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 3187 /* 3188 *********************************************************************************** 3189 ** ATU Minimum Grant Register - ATUMGNT 3190 ** ----------------------------------------------------------------- 3191 ** Bit Default Description 3192 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 3193 *********************************************************************************** 3194 */ 3195 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 3196 /* 3197 *********************************************************************************** 3198 ** ATU Maximum Latency Register - ATUMLAT 3199 ** ----------------------------------------------------------------- 3200 ** Bit Default Description 3201 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 3202 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 3203 *********************************************************************************** 3204 */ 3205 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 3206 /* 3207 *********************************************************************************** 3208 ** Inbound Address Translation 3209 ** 3210 ** The ATU allows external PCI bus initiators to directly access the internal bus. 3211 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 3212 ** The process of inbound address translation involves two steps: 3213 ** 1. Address Detection. 3214 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 3215 ** within the address windows defined for the inbound ATU. 3216 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 3217 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 3218 ** 2. Address Translation. 3219 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 3220 ** The ATU uses the following registers in inbound address window 0 translation: 3221 ** �E Inbound ATU Base Address Register 0 3222 ** �E Inbound ATU Limit Register 0 3223 ** �E Inbound ATU Translate Value Register 0 3224 ** The ATU uses the following registers in inbound address window 2 translation: 3225 ** �E Inbound ATU Base Address Register 2 3226 ** �E Inbound ATU Limit Register 2 3227 ** �E Inbound ATU Translate Value Register 2 3228 ** The ATU uses the following registers in inbound address window 3 translation: 3229 ** �E Inbound ATU Base Address Register 3 3230 ** �E Inbound ATU Limit Register 3 3231 ** �E Inbound ATU Translate Value Register 3 3232 ** Note: Inbound Address window 1 is not a translate window. 3233 ** Instead, window 1 may be used to allocate host memory for Private Devices. 3234 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 3235 ** thus the host BIOS does not configure window 3. 3236 ** Window 3 is intended to be used as a special window into local memory for private PCI 3237 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 3238 ** PCI-to-PCI Bridge in 80331 or 3239 ** Inbound address detection is determined from the 32-bit PCI address, 3240 ** (64-bit PCI address during DACs) the base address register and the limit register. 3241 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 3242 ** 3243 ** The algorithm for detection is: 3244 ** 3245 ** Equation 1. Inbound Address Detection 3246 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 3247 ** the PCI Address is claimed by the Inbound ATU. 3248 ** 3249 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 3250 ** with the associated inbound limit register. 3251 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 3252 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 3253 ** 3254 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 3255 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 3256 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 3257 ** lower 32-bits are used during address translation. 3258 ** The algorithm is: 3259 ** 3260 ** 3261 ** Equation 2. Inbound Translation 3262 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 3263 ** 3264 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 3265 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 3266 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 3267 ** read and write commands excluding inbound configuration read and writes. 3268 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3269 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3270 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3271 ** example: 3272 ** Register Values 3273 ** Base_Register=3A00 0000H 3274 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 3275 ** Value_Register=B100 0000H 3276 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3277 ** 3278 ** Address Detection (32-bit address) 3279 ** 3280 ** PCI_Address & Limit_Register == Base_Register 3281 ** 3A45 012CH & FF80 0000H == 3A00 0000H 3282 ** 3283 ** ANS: PCI_Address is in the Inbound Translation Window 3284 ** Address Translation (to get internal bus address) 3285 ** 3286 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3287 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3288 ** 3289 ** ANS:IB_Address=B145 012CH 3290 *********************************************************************************** 3291 */ 3292 3293 /* 3294 *********************************************************************************** 3295 ** Inbound ATU Limit Register 0 - IALR0 3296 ** 3297 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3298 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3299 ** PCI addresses to internal bus addresses. 3300 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3301 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3302 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3303 ** Specification, Revision 2.3 for additional information on programming base address registers. 3304 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3305 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3306 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3307 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3308 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3309 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3310 ** ----------------------------------------------------------------- 3311 ** Bit Default Description 3312 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3313 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3314 ** 11:00 000H Reserved 3315 *********************************************************************************** 3316 */ 3317 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3318 /* 3319 *********************************************************************************** 3320 ** Inbound ATU Translate Value Register 0 - IATVR0 3321 ** 3322 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3323 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3324 ** inbound ATU address translation. 3325 ** ----------------------------------------------------------------- 3326 ** Bit Default Description 3327 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3328 ** This value must be 64-bit aligned on the internal bus. 3329 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3330 ** 11:00 000H Reserved 3331 *********************************************************************************** 3332 */ 3333 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3334 /* 3335 *********************************************************************************** 3336 ** Expansion ROM Limit Register - ERLR 3337 ** 3338 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3339 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3340 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3341 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3342 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3343 ** the corresponding bit within the ERBAR read/write from PCI. 3344 ** ----------------------------------------------------------------- 3345 ** Bit Default Description 3346 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3347 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3348 ** 11:00 000H Reserved. 3349 *********************************************************************************** 3350 */ 3351 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3352 /* 3353 *********************************************************************************** 3354 ** Expansion ROM Translate Value Register - ERTVR 3355 ** 3356 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3357 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3358 ** Expansion ROM address translation. 3359 ** ----------------------------------------------------------------- 3360 ** Bit Default Description 3361 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3362 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3363 ** 11:00 000H Reserved 3364 *********************************************************************************** 3365 */ 3366 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3367 /* 3368 *********************************************************************************** 3369 ** Inbound ATU Limit Register 1 - IALR1 3370 ** 3371 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3372 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3373 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3374 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3375 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3376 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3377 ** register. 3378 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3379 ** not process any PCI bus transactions to this memory range. 3380 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3381 ** IAUBAR1, and IALR1. 3382 ** ----------------------------------------------------------------- 3383 ** Bit Default Description 3384 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3385 ** required for the ATUs memory window 1. 3386 ** 11:00 000H Reserved 3387 *********************************************************************************** 3388 */ 3389 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3390 /* 3391 *********************************************************************************** 3392 ** Inbound ATU Limit Register 2 - IALR2 3393 ** 3394 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3395 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3396 ** PCI addresses to internal bus addresses. 3397 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3398 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3399 ** register provides the block size requirements for the base address register. The remaining registers 3400 ** used for performing address translation are discussed in Section 3.2.1.1. 3401 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3402 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3403 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3404 ** Specification, Revision 2.3 for additional information on programming base address registers. 3405 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3406 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3407 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3408 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3409 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3410 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3411 ** register. 3412 ** ----------------------------------------------------------------- 3413 ** Bit Default Description 3414 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3415 ** required for the ATUs memory window 2. 3416 ** 11:00 000H Reserved 3417 *********************************************************************************** 3418 */ 3419 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3420 /* 3421 *********************************************************************************** 3422 ** Inbound ATU Translate Value Register 2 - IATVR2 3423 ** 3424 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3425 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3426 ** inbound ATU address translation. 3427 ** ----------------------------------------------------------------- 3428 ** Bit Default Description 3429 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3430 ** This value must be 64-bit aligned on the internal bus. 3431 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3432 ** 11:00 000H Reserved 3433 *********************************************************************************** 3434 */ 3435 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3436 /* 3437 *********************************************************************************** 3438 ** Outbound I/O Window Translate Value Register - OIOWTVR 3439 ** 3440 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3441 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3442 ** result of the outbound ATU address translation. 3443 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3444 ** length of 64 Kbytes. 3445 ** ----------------------------------------------------------------- 3446 ** Bit Default Description 3447 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3448 ** 15:00 0000H Reserved 3449 *********************************************************************************** 3450 */ 3451 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3452 /* 3453 *********************************************************************************** 3454 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3455 ** 3456 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3457 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3458 ** driven on the PCI bus as a result of the outbound ATU address translation. 3459 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3460 ** of 64 Mbytes. 3461 ** ----------------------------------------------------------------- 3462 ** Bit Default Description 3463 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3464 ** 25:02 00 0000H Reserved 3465 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3466 ** Only linear incrementing mode is supported. 3467 *********************************************************************************** 3468 */ 3469 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3470 /* 3471 *********************************************************************************** 3472 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3473 ** 3474 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3475 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3476 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3477 ** a SAC is generated on the PCI bus. 3478 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3479 ** length of 64 Mbytes. 3480 ** ----------------------------------------------------------------- 3481 ** Bit Default Description 3482 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3483 *********************************************************************************** 3484 */ 3485 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3486 /* 3487 *********************************************************************************** 3488 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3489 ** 3490 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3491 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3492 ** driven on the PCI bus as a result of the outbound ATU address translation. 3493 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3494 ** of 64 Mbytes. 3495 ** ----------------------------------------------------------------- 3496 ** Bit Default Description 3497 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3498 ** 25:02 00 0000H Reserved 3499 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3500 ** Only linear incrementing mode is supported. 3501 *********************************************************************************** 3502 */ 3503 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3504 /* 3505 *********************************************************************************** 3506 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3507 ** 3508 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3509 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3510 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3511 ** a SAC is generated on the PCI bus. 3512 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3513 ** of 64 Mbytes. 3514 ** ----------------------------------------------------------------- 3515 ** Bit Default Description 3516 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3517 *********************************************************************************** 3518 */ 3519 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3520 /* 3521 *********************************************************************************** 3522 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3523 ** 3524 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3525 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3526 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3527 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3528 ** ----------------------------------------------------------------- 3529 ** Bit Default Description 3530 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3531 *********************************************************************************** 3532 */ 3533 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3534 /* 3535 *********************************************************************************** 3536 ** ATU Configuration Register - ATUCR 3537 ** 3538 ** The ATU Configuration Register controls the outbound address translation for address translation 3539 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3540 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3541 ** interrupt enabling. 3542 ** ----------------------------------------------------------------- 3543 ** Bit Default Description 3544 ** 31:20 00H Reserved 3545 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3546 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3547 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3548 ** applicable in the PCI-X mode. 3549 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3550 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3551 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3552 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3553 ** When clear, no translation occurs. 3554 ** 17 0 2 Reserved 3555 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3556 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3557 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3558 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3559 ** 14:10 00000 2 Reserved 3560 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3561 ** when the ATU detects that SERR# was asserted. When clear, 3562 ** the Intel XScale core is not interrupted when SERR# is detected. 3563 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3564 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3565 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3566 ** the ATUCR. 3567 ** 07:04 0000 2 Reserved 3568 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3569 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3570 ** in the ATUBISTR register. 3571 ** 02 0 2 Reserved 3572 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3573 ** When cleared, disables the outbound ATU. 3574 ** 00 0 2 Reserved 3575 *********************************************************************************** 3576 */ 3577 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3578 /* 3579 *********************************************************************************** 3580 ** PCI Configuration and Status Register - PCSR 3581 ** 3582 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3583 ** various features of the PCI bus interface. 3584 ** ----------------------------------------------------------------- 3585 ** Bit Default Description 3586 ** 31:19 0000H Reserved 3587 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3588 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3589 ** Response bit is cleared. Set under the following conditions: 3590 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3591 ** 17:16 Varies with 3592 ** external state 3593 ** of DEVSEL#, 3594 ** STOP#, and 3595 ** TRDY#, 3596 ** during 3597 ** P_RST# 3598 ** PCI-X capability - These two bits define the mode of 3599 ** the PCI bus (conventional or PCI-X) as well as the 3600 ** operating frequency in the case of PCI-X mode. 3601 ** 00 - Conventional PCI mode 3602 ** 01 - PCI-X 66 3603 ** 10 - PCI-X 100 3604 ** 11 - PCI-X 133 3605 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3606 ** Revision 1.0a, the operating 3607 ** mode is determined by an initialization pattern on the PCI bus during 3608 ** P_RST# assertion: 3609 ** DEVSEL# STOP# TRDY# Mode 3610 ** Deasserted Deasserted Deasserted Conventional 3611 ** Deasserted Deasserted Asserted PCI-X 66 3612 ** Deasserted Asserted Deasserted PCI-X 100 3613 ** Deasserted Asserted Asserted PCI-X 133 3614 ** All other patterns are reserved. 3615 ** 15 0 2 3616 ** Outbound Transaction Queue Busy: 3617 ** 0=Outbound Transaction Queue Empty 3618 ** 1=Outbound Transaction Queue Busy 3619 ** 14 0 2 3620 ** Inbound Transaction Queue Busy: 3621 ** 0=Inbound Transaction Queue Empty 3622 ** 1=Inbound Transaction Queue Busy 3623 ** 13 0 2 Reserved. 3624 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3625 ** for the four discard timers attached to the queues holding read data. 3626 ** A value of 0 indicates the time-out value is 2 15 clocks. 3627 ** A value of 1 indicates the time-out value is 2 10 clocks. 3628 ** 11 0 2 Reserved. 3629 ** 10 Varies with 3630 ** external state 3631 ** of M66EN 3632 ** during 3633 ** P_RST# 3634 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3635 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3636 ** When clear, the interface 3637 ** has been initialized as a 33 MHz bus. 3638 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3639 ** 09 0 2 Reserved 3640 ** 08 Varies with 3641 ** external state 3642 ** of REQ64# 3643 ** during 3644 ** P_RST# 3645 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3646 ** configured as 64-bit capable by 3647 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3648 ** the PCI interface is configured as 3649 ** 32-bit only. 3650 ** 07:06 00 2 Reserved. 3651 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3652 ** and all units on the internal 3653 ** bus. In addition to the internal bus initialization, 3654 ** this bit triggers the assertion of the M_RST# pin for 3655 ** initialization of registered DIMMs. When set: 3656 ** When operating in the conventional PCI mode: 3657 ** �E All current PCI transactions being mastered by the ATU completes, 3658 ** and the ATU master interfaces 3659 ** proceeds to an idle state. No additional transactions is mastered by these units 3660 ** until the internal bus reset is complete. 3661 ** �E All current transactions being slaved by the ATU on either the PCI bus 3662 ** or the internal bus 3663 ** completes, and the ATU target interfaces proceeds to an idle state. 3664 ** All future slave transactions master aborts, 3665 ** with the exception of the completion cycle for the transaction that set the Reset 3666 ** Internal Bus bit in the PCSR. 3667 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3668 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3669 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3670 ** Internal Bus clocks. 3671 ** �E The 80331 hardware clears this bit after the reset operation completes. 3672 ** When operating in the PCI-X mode: 3673 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3674 ** However, this may create a problem in PCI-X mode for split requests in 3675 ** that there may still be an outstanding split completion that the 3676 ** ATU is either waiting to receive (Outbound Request) or initiate 3677 ** (Inbound Read Request). For a cleaner 3678 ** internal bus reset, host software can take the following steps prior 3679 ** to asserting Reset Internal bus: 3680 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3681 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3682 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3683 ** queue busy bits to be clear. 3684 ** 3. Set the Reset Internal Bus bit 3685 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3686 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3687 ** completion transactions. 3688 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3689 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3690 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3691 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3692 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3693 ** Bus Master Indicator signal P_BMI used 3694 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3695 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3696 ** 03 Varies with external state of PRIVDEV during 3697 ** P_RST# 3698 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3699 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3700 ** 0=Private Device control Disabled - SISR register bits default to zero 3701 ** 1=Private Device control Enabled - SISR register bits default to one 3702 ** 02 Varies with external state of RETRY during P_RST# 3703 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3704 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3705 ** configuration cycles. 3706 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3707 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3708 ** low, the bit is cleared. 3709 ** 01 Varies with external state of CORE_RST# during P_RST# 3710 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3711 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3712 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3713 ** XScale core reset. 3714 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3715 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3716 ** high, the bit is clear. 3717 ** 00 Varies with external state of PRIVMEM during P_RST# 3718 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3719 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3720 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3721 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3722 *********************************************************************************** 3723 */ 3724 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3725 /* 3726 *********************************************************************************** 3727 ** ATU Interrupt Status Register - ATUISR 3728 ** 3729 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3730 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3731 ** of the 80331. All bits in this register are Read/Clear. 3732 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3733 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3734 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3735 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3736 ** register. 3737 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3738 ** ----------------------------------------------------------------- 3739 ** Bit Default Description 3740 ** 31:18 0000H Reserved 3741 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3742 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3743 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3744 ** 16 0 2 Reserved 3745 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3746 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3747 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3748 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3749 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3750 ** Configure Register Write Interrupt. 3751 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3752 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3753 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3754 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3755 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3756 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3757 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3758 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3759 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3760 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3761 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3762 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3763 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3764 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3765 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3766 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3767 ** register bits 3:0. 3768 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3769 ** of the ATU Configure Register Write Interrupt. 3770 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3771 ** 06:05 00 2 Reserved. 3772 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3773 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3774 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3775 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3776 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3777 ** conditions: 3778 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3779 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3780 ** �E And the ATUCMD register��s Parity Error Response bit is set 3781 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3782 ** �E And the ATUCMD register��s Parity Error Response bit is set 3783 *********************************************************************************** 3784 */ 3785 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3786 /* 3787 *********************************************************************************** 3788 ** ATU Interrupt Mask Register - ATUIMR 3789 ** 3790 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3791 ** generated by the ATU. 3792 ** ----------------------------------------------------------------- 3793 ** Bit Default Description 3794 ** 31:15 0 0000H Reserved 3795 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3796 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3797 ** 0=Not Masked 3798 ** 1=Masked 3799 ** 13 0 2 Reserved 3800 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3801 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3802 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3803 ** 0=Not Masked 3804 ** 1=Masked 3805 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3806 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3807 ** IABAR1 register or the IAUBAR1 register. 3808 ** 0=Not Masked 3809 ** 1=Masked 3810 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3811 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3812 ** 0=Not Masked 3813 ** 1=Masked 3814 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3815 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3816 ** PCIXSR being set. 3817 ** 0=Not Masked 3818 ** 1=Masked 3819 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3820 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3821 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3822 ** 0=Not Masked 3823 ** 1=Masked 3824 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3825 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3826 ** 0=Not Masked 3827 ** 1=Masked 3828 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3829 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3830 ** 0=Not Masked 3831 ** 1=Masked 3832 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3833 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3834 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3835 ** 0=Not Masked 3836 ** 1=Masked 3837 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3838 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3839 ** 0=Not Masked 3840 ** 1=Masked 3841 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3842 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3843 ** 0=Not Masked 3844 ** 1=Masked 3845 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3846 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3847 ** 0=Not Masked 3848 ** 1=Masked 3849 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3850 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3851 ** inbound write transaction. 3852 ** 0=SERR# Not Asserted due to error 3853 ** 1=SERR# Asserted due to error 3854 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3855 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3856 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3857 ** actually requested from the inbound read queue. 3858 ** 0=Disconnect with data 3859 ** (the data being up to 64 bits of 1��s) 3860 ** 1=Target Abort 3861 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3862 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3863 ** independent of the setting of this bit. 3864 *********************************************************************************** 3865 */ 3866 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3867 /* 3868 *********************************************************************************** 3869 ** Inbound ATU Base Address Register 3 - IABAR3 3870 ** 3871 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3872 ** of memory addresses where the inbound translation window 3 begins. 3873 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3874 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3875 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3876 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3877 ** Note: 3878 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3879 ** IABAR3 is not configured by the host during normal system initialization. 3880 ** Warning: 3881 ** When a non-zero value is not written to IALR3, 3882 ** the user should not set either the Prefetchable Indicator 3883 ** or the Type Indicator for 64 bit addressability. 3884 ** This is the default for IABAR3. 3885 ** Assuming a non-zero value is written to IALR3, 3886 ** the user may set the Prefetchable Indicator 3887 ** or the Type Indicator: 3888 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3889 ** when the Prefetchable Indicator is not set, 3890 ** the user should also leave the Type Indicator set for 32 bit addressability. 3891 ** This is the default for IABAR3. 3892 ** b. when the Prefetchable Indicator is set, 3893 ** the user should also set the Type Indicator for 64 bit addressability. 3894 ** ----------------------------------------------------------------- 3895 ** Bit Default Description 3896 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3897 ** the translation function is to respond to when addressed from the PCI bus. 3898 ** 11:04 00H Reserved. 3899 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3900 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3901 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3902 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3903 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3904 ** The ATU does not occupy I/O space, 3905 ** thus this bit must be zero. 3906 *********************************************************************************** 3907 */ 3908 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3909 /* 3910 *********************************************************************************** 3911 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3912 ** 3913 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3914 ** Together with the Translation Base Address this register defines the actual location 3915 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3916 ** The programmed value within the base address register must comply with the PCI programming 3917 ** requirements for address alignment. 3918 ** Note: 3919 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3920 ** the IAUBAR3 register attributes are read-only. 3921 ** This is the default for IABAR3. 3922 ** ----------------------------------------------------------------- 3923 ** Bit Default Description 3924 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3925 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3926 *********************************************************************************** 3927 */ 3928 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3929 /* 3930 *********************************************************************************** 3931 ** Inbound ATU Limit Register 3 - IALR3 3932 ** 3933 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3934 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3935 ** PCI addresses to internal bus addresses. 3936 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3937 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3938 ** register provides the block size requirements for the base address register. The remaining registers 3939 ** used for performing address translation are discussed in Section 3.2.1.1. 3940 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3941 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3942 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3943 ** Specification, Revision 2.3 for additional information on programming base address registers. 3944 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3945 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3946 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3947 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3948 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3949 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3950 ** register. 3951 ** ----------------------------------------------------------------- 3952 ** Bit Default Description 3953 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3954 ** for the ATUs memory window 3. 3955 ** 11:00 000H Reserved 3956 *********************************************************************************** 3957 */ 3958 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3959 /* 3960 *********************************************************************************** 3961 ** Inbound ATU Translate Value Register 3 - IATVR3 3962 ** 3963 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3964 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3965 ** inbound ATU address translation. 3966 ** ----------------------------------------------------------------- 3967 ** Bit Default Description 3968 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3969 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3970 ** access the internal 80331 memory-mapped registers. 3971 ** 11:00 000H Reserved 3972 *********************************************************************************** 3973 */ 3974 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3975 /* 3976 *********************************************************************************** 3977 ** Outbound Configuration Cycle Address Register - OCCAR 3978 ** 3979 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3980 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3981 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3982 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3983 ** PCI bus. 3984 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3985 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3986 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3987 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3988 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3989 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3990 ** ----------------------------------------------------------------- 3991 ** Bit Default Description 3992 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3993 ** configuration read or write cycle. 3994 *********************************************************************************** 3995 */ 3996 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3997 /* 3998 *********************************************************************************** 3999 ** Outbound Configuration Cycle Data Register - OCCDR 4000 ** 4001 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 4002 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 4003 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 4004 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 4005 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 4006 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 4007 ** actually entered into the data register (which does not physically exist). 4008 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 4009 ** within the ATU configuration space. 4010 ** ----------------------------------------------------------------- 4011 ** Bit Default Description 4012 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 4013 ** or write cycle. 4014 *********************************************************************************** 4015 */ 4016 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 4017 /* 4018 *********************************************************************************** 4019 ** VPD Capability Identifier Register - VPD_CAPID 4020 ** 4021 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4022 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4023 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 4024 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 4025 ** ----------------------------------------------------------------- 4026 ** Bit Default Description 4027 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 4028 ** Headers as being the VPD capability registers. 4029 *********************************************************************************** 4030 */ 4031 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 4032 /* 4033 *********************************************************************************** 4034 ** VPD Next Item Pointer Register - VPD_NXTP 4035 ** 4036 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4037 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4038 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 4039 ** ----------------------------------------------------------------- 4040 ** Bit Default Description 4041 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4042 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 4043 ** extended capabilities in the 80331, the register is set to 00H. 4044 *********************************************************************************** 4045 */ 4046 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 4047 /* 4048 *********************************************************************************** 4049 ** VPD Address Register - VPD_AR 4050 ** 4051 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 4052 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 4053 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 4054 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 4055 ** write of the VPD through the VPD Data Register. 4056 ** ----------------------------------------------------------------- 4057 ** Bit Default Description 4058 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 4059 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 4060 ** how the 80331 handles the data transfer. 4061 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 4062 ** Vital Product Data from the VPD storage component. 4063 *********************************************************************************** 4064 */ 4065 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 4066 /* 4067 *********************************************************************************** 4068 ** VPD Data Register - VPD_DR 4069 ** 4070 ** This register is used to transfer data between the 80331 and the VPD storage component. 4071 ** ----------------------------------------------------------------- 4072 ** Bit Default Description 4073 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 4074 *********************************************************************************** 4075 */ 4076 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 4077 /* 4078 *********************************************************************************** 4079 ** Power Management Capability Identifier Register -PM_CAPID 4080 ** 4081 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4082 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4083 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 4084 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 4085 ** Interface Specification, Revision 1.1. 4086 ** ----------------------------------------------------------------- 4087 ** Bit Default Description 4088 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 4089 ** Headers as being the PCI Power Management Registers. 4090 *********************************************************************************** 4091 */ 4092 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 4093 /* 4094 *********************************************************************************** 4095 ** Power Management Next Item Pointer Register - PM_NXTP 4096 ** 4097 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4098 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4099 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 4100 ** ----------------------------------------------------------------- 4101 ** Bit Default Description 4102 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4103 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 4104 *********************************************************************************** 4105 */ 4106 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 4107 /* 4108 *********************************************************************************** 4109 ** Power Management Capabilities Register - PM_CAP 4110 ** 4111 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 4112 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 4113 ** information on the capabilities of the ATU function related to power management. 4114 ** ----------------------------------------------------------------- 4115 ** Bit Default Description 4116 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 4117 ** is not supported by the 80331. 4118 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 4119 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 4120 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 4121 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 4122 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 4123 ** following the transition to the D0 uninitialized state. 4124 ** 4 0 2 Reserved. 4125 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 4126 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 4127 ** Interface Specification, Revision 1.1 4128 *********************************************************************************** 4129 */ 4130 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 4131 /* 4132 *********************************************************************************** 4133 ** Power Management Control/Status Register - PM_CSR 4134 ** 4135 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 4136 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 4137 ** interface for the power management extended capability. 4138 ** ----------------------------------------------------------------- 4139 ** Bit Default Description 4140 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 4141 ** supported by the 80331. 4142 ** 14:9 00H Reserved 4143 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 4144 ** generation from any power state. 4145 ** 7:2 000000 2 Reserved 4146 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 4147 ** of a function and to set the function into a new power state. The definition of the values is: 4148 ** 00 2 - D0 4149 ** 01 2 - D1 4150 ** 10 2 - D2 (Unsupported) 4151 ** 11 2 - D3 hot 4152 ** The 80331 supports only the D0 and D3 hot states. 4153 ** 4154 *********************************************************************************** 4155 */ 4156 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 4157 /* 4158 *********************************************************************************** 4159 ** PCI-X Capability Identifier Register - PX_CAPID 4160 ** 4161 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4162 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4163 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 4164 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 4165 ** ----------------------------------------------------------------- 4166 ** Bit Default Description 4167 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 4168 ** Headers as being the PCI-X capability registers. 4169 *********************************************************************************** 4170 */ 4171 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 4172 /* 4173 *********************************************************************************** 4174 ** PCI-X Next Item Pointer Register - PX_NXTP 4175 ** 4176 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4177 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4178 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 4179 ** to 00H. 4180 ** However, this register may be written to B8H prior to host configuration to include the VPD 4181 ** capability located at off-set B8H. 4182 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 4183 ** produce unpredictable system behavior. 4184 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 4185 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 4186 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 4187 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 4188 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 4189 ** ----------------------------------------------------------------- 4190 ** Bit Default Description 4191 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4192 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 4193 ** extended capabilities in the 80331, the register is set to 00H. 4194 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 4195 ** VPD extended capabilities header. 4196 *********************************************************************************** 4197 */ 4198 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 4199 /* 4200 *********************************************************************************** 4201 ** PCI-X Command Register - PX_CMD 4202 ** 4203 ** This register controls various modes and features of ATU and Message Unit when operating in the 4204 ** PCI-X mode. 4205 ** ----------------------------------------------------------------- 4206 ** Bit Default Description 4207 ** 15:7 000000000 2 Reserved. 4208 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 4209 ** the device is permitted to have outstanding at one time. 4210 ** Register Maximum Outstanding 4211 ** 0 1 4212 ** 1 2 4213 ** 2 3 4214 ** 3 4 4215 ** 4 8 4216 ** 5 12 4217 ** 6 16 4218 ** 7 32 4219 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 4220 ** initiating a Sequence with one of the burst memory read commands. 4221 ** Register Maximum Byte Count 4222 ** 0 512 4223 ** 1 1024 4224 ** 2 2048 4225 ** 3 4096 4226 ** 1 0 2 4227 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 4228 ** of Transactions. 4229 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 4230 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 4231 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 4232 *********************************************************************************** 4233 */ 4234 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 4235 /* 4236 *********************************************************************************** 4237 ** PCI-X Status Register - PX_SR 4238 ** 4239 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 4240 ** Unit when operating in the PCI-X mode. 4241 ** ----------------------------------------------------------------- 4242 ** Bit Default Description 4243 ** 31:30 00 2 Reserved 4244 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 4245 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 4246 ** writes a 1 to this location. 4247 ** 0=no Split Completion error message received. 4248 ** 1=a Split Completion error message has been received. 4249 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 4250 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 4251 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 4252 ** 1 16 512 (Default) 4253 ** 2 32 1024 4254 ** 2 32 2048 4255 ** 2 32 4096 4256 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 4257 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 4258 ** to 1024 bytes. 4259 ** 20 1 2 80331 is a complex device. 4260 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 4261 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 4262 ** 0=no unexpected Split Completion has been received. 4263 ** 1=an unexpected Split Completion has been received. 4264 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 4265 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 4266 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4267 ** location. 4268 ** 0=no Split Completion has been discarded. 4269 ** 1=a Split Completion has been discarded. 4270 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4271 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4272 ** 17 1 2 80331 is a 133 MHz capable device. 4273 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4274 ** therefore this bit is always set. 4275 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4276 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4277 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4278 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4279 ** 0=The bus is 32 bits wide. 4280 ** 1=The bus is 64 bits wide. 4281 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4282 ** segment for the device containing this function. The function uses this number as part of its Requester 4283 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4284 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4285 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 4286 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4287 ** the following are true: 4288 ** 1. The transaction uses a Configuration Write command. 4289 ** 2. IDSEL is asserted during the address phase. 4290 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4291 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4292 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4293 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4294 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4295 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4296 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4297 ** time the function is addressed by a Configuration Write transaction, the device must update this register 4298 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4299 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 4300 ** Write transaction when all of the following are true: 4301 ** 1. The transaction uses a Configuration Write command. 4302 ** 2. IDSEL is asserted during the address phase. 4303 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4304 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4305 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4306 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4307 ** configuration transaction to which this function responds. The function uses this number as part of its 4308 ** Requester ID and Completer ID. 4309 ** 4310 ************************************************************************** 4311 */ 4312 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4313 4314 /* 4315 ************************************************************************** 4316 ** Inbound Read Transaction 4317 ** ======================================================================== 4318 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4319 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4320 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4321 ** (IRQ). 4322 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 4323 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4324 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4325 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4326 ** an inbound read transaction on the PCI bus is summarized in the following statements: 4327 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4328 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4329 ** Address Register during DACs) and Inbound Limit Register. 4330 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4331 ** information from a previous delayed read, the current transaction information is compared to 4332 ** the previous transaction information (based on the setting of the DRC Alias bit in 4333 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4334 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4335 ** match and the data is not available, a Retry is signaled with no other action taken. When there 4336 ** is not a match and when the ITQ has less than eight entries, capture the transaction 4337 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4338 ** when the ITQ is full, then signal a Retry with no other action taken. 4339 ** �X When an address parity error is detected, the address parity response defined in 4340 ** Section 3.7 is used. 4341 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4342 ** the IRQ, it continues until one of the following is true: 4343 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4344 ** data is flushed. 4345 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4346 ** Target Abort is never entered into the IRQ, and therefore is never returned. 4347 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4348 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4349 ** the initiator on the last data word available. 4350 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4351 ** command are latched into the available ITQ and a Split Response Termination is signalled to 4352 ** the initiator. 4353 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4354 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4355 ** before returning read data by generating the split completion transaction on the PCI-X bus. 4356 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4357 ** transfer by returning data in 1024 byte aligned chunks. 4358 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4359 ** continues until one of the following is true: 4360 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4361 ** ADB (when the requester is a bridge) 4362 ** �X The byte count is satisfied. 4363 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4364 ** Message (message class=2h - completer error, and message index=81h - target abort) to 4365 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4366 ** Refer to Section 3.7.1. 4367 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4368 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 4369 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4370 ** Refer to Section 3.7.1 4371 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4372 ** bus, the ATU PCI slave interface waits with no premature disconnects. 4373 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4374 ** taken by the target interface. Refer to Section 3.7.2.5. 4375 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 4376 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4377 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4378 ** target abort is used, when clear, a disconnect is used. 4379 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4380 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4381 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 4382 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4383 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4384 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4385 ** transaction is flushed. Refer to Section 3.7.1. 4386 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4387 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4388 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4389 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4390 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4391 ** error, and message index=80h - internal bus master abort) to inform the requester about the 4392 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4393 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4394 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4395 ** prevents it from accepting the completion it requested. In this case, since the Split Request 4396 ** addresses a location that has no read side effects, the completer must discard the Split 4397 ** Completion and take no further action. 4398 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 4399 ** statements: 4400 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4401 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4402 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4403 ** always uses conventional PCI ordering rules. 4404 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4405 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4406 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4407 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4408 ** master has been delivered the target abort). 4409 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4410 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4411 ** received by the IRQ until one of the following is true: 4412 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4413 ** initiator interface performs a initiator completion in this case. 4414 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4415 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4416 ** informed. 4417 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4418 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4419 ** Completion Message (message class=2h - completer error, and message index=81h - 4420 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4421 ** ITQ for this transaction is flushed. 4422 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 4423 ** received from the internal bus target. When the data has not been received up to the next 4424 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4425 ** When not, the bus returns to idle. 4426 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4427 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4428 ** obtain remaining data. 4429 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4430 ** from the internal bus target. The bus returns to idle. 4431 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4432 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4433 ** remaining data. 4434 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4435 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4436 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4437 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4438 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4439 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4440 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4441 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4442 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4443 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4444 ** commands did not match, only the address. 4445 ************************************************************************** 4446 */ 4447 /* 4448 ************************************************************************** 4449 ** Inbound Write Transaction 4450 **======================================================================== 4451 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4452 ** memory or a 80331 memory-mapped register. 4453 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 4454 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4455 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4456 ** Base Address Register during DACs) and Inbound Limit Register. 4457 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4458 ** available, the address is captured and the first data phase is accepted. 4459 ** �E The PCI interface continues to accept write data until one of the following is true: 4460 ** �X The initiator performs a disconnect. 4461 ** �X The transaction crosses a buffer boundary. 4462 ** �E When an address parity error is detected during the address phase of the transaction, the 4463 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4464 ** parity error response. 4465 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4466 ** parity error mechanism described in Section 3.7.1 is used. 4467 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4468 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4469 ** for details of the inbound write data parity error response. 4470 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4471 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4472 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4473 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4474 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4475 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4476 ** interface, when operating in the PCI mode. 4477 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4478 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4479 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4480 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4481 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4482 ** The ATU handles such transactions as independent transactions. 4483 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4484 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4485 ** with associated data in the IWQ. 4486 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4487 ** transaction by driving the translated address onto the internal bus. For details on inbound 4488 ** address translation. 4489 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4490 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4491 ** interface. 4492 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4493 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4494 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4495 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4496 ** internal bus ownership. 4497 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4498 ** bus when one of the following conditions becomes true: 4499 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4500 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4501 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4502 ** complete the delivery of remaining data using the same sequence ID but with the 4503 ** modified starting address and byte count. 4504 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4505 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4506 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4507 ** complete the delivery of remaining data using the same sequence ID but with the 4508 ** modified starting address and byte count. 4509 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4510 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4511 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4512 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4513 ** modified starting address and byte count. 4514 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4515 ** initiator termination is performed and the bus returns to idle. 4516 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4517 ** Data is flushed from the IWQ. 4518 ***************************************************************** 4519 */ 4520 4521 /* 4522 ************************************************************************** 4523 ** Inbound Read Completions Data Parity Errors 4524 **======================================================================== 4525 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4526 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4527 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4528 ** action is taken. 4529 ************************************************************************** 4530 */ 4531 4532 /* 4533 ************************************************************************** 4534 ** Inbound Configuration Write Completion Message Data Parity Errors 4535 **======================================================================== 4536 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4537 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4538 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4539 ** normally and no further action is taken. 4540 ************************************************************************** 4541 */ 4542 4543 /* 4544 ************************************************************************** 4545 ** Inbound Read Request Data Parity Errors 4546 **===================== Immediate Data Transfer ========================== 4547 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4548 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4549 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4550 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4551 ** required and no error bits are set. 4552 **=====================Split Response Termination========================= 4553 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4554 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4555 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4556 ** action is required and no error bits are set. 4557 ************************************************************************** 4558 */ 4559 4560 /* 4561 ************************************************************************** 4562 ** Inbound Write Request Data Parity Errors 4563 **======================================================================== 4564 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4565 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4566 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4567 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4568 ** the given constraints are taken by the ATU: 4569 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4570 ** following the data phase in which the data parity error is detected on the bus. This is only 4571 ** done when the Parity Error Response bit in the ATUCMD is set. 4572 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4573 ** actions is taken: 4574 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4575 ** Detected Parity Error bit in the ATUISR. When set, no action. 4576 *************************************************************************** 4577 */ 4578 4579 /* 4580 *************************************************************************** 4581 ** Inbound Configuration Write Request 4582 ** ===================================================================== 4583 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4584 ** =============================================== 4585 ** Conventional PCI Mode 4586 ** =============================================== 4587 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4588 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4589 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4590 ** parts of the transactions: 4591 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4592 ** address/command and data for delayed delivery to the internal configuration register. 4593 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4594 ** of the operation back to the original master. 4595 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4596 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4597 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4598 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4599 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4600 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4601 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4602 ** forwarded to the internal bus. PERR# is not asserted. 4603 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4604 ** actions is taken: 4605 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4606 ** Detected Parity Error bit in the ATUISR. When set, no action. 4607 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4608 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4609 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4610 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4611 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4612 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4613 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4614 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4615 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4616 ** actions is taken: 4617 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4618 ** Detected Parity Error bit in the ATUISR. When set, no action. 4619 ** =================================================== 4620 ** PCI-X Mode 4621 ** =================================================== 4622 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4623 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4624 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4625 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4626 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4627 ** cycles following the Split Response Termination in which the data parity error is detected on 4628 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4629 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4630 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4631 ** that addresses the requester of the configuration write. 4632 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4633 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4634 ** action. 4635 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4636 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4637 ** actions is taken: 4638 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4639 ** Detected Parity Error bit in the ATUISR. When set, no action. 4640 ** 4641 *************************************************************************** 4642 */ 4643 4644 /* 4645 *************************************************************************** 4646 ** Split Completion Messages 4647 ** ======================================================================= 4648 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4649 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4650 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4651 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4652 ** constraints are taken by the ATU: 4653 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4654 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4655 ** is set. When the ATU asserts PERR#, additional actions is taken: 4656 ** �X The Master Parity Error bit in the ATUSR is set. 4657 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4658 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4659 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4660 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4661 ** When the ATU asserts SERR#, additional actions is taken: 4662 ** Set the SERR# Asserted bit in the ATUSR. 4663 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4664 ** SERR# Asserted bit in the ATUISR. When set, no action. 4665 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4666 ** SERR# Detected bit in the ATUISR. When clear, no action. 4667 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4668 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4669 ** When the ATU sets this bit, additional actions is taken: 4670 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4671 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4672 ** When set, no action. 4673 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4674 ** actions is taken: 4675 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4676 ** Detected Parity Error bit in the ATUISR. When set, no action. 4677 ** �E The transaction associated with the Split Completion Message is discarded. 4678 ** �E When the discarded transaction was a read, a completion error message (with message 4679 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4680 ** the internal bus of the 80331. 4681 ***************************************************************************** 4682 */ 4683 4684 /* 4685 ****************************************************************************************************** 4686 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4687 ** ================================================================================================== 4688 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4689 ** notifies the respective system when new data arrives. 4690 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4691 ** window defined by: 4692 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4693 ** 2.Inbound ATU Limit Register 0 (IALR0) 4694 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4695 ** Error conditions and status can be found in : 4696 ** 1.ATUSR 4697 ** 2.ATUISR 4698 **==================================================================================================== 4699 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4700 **---------------------------------------------------------------------------------------------------- 4701 ** Message Registers 2 Inbound Optional Optional 4702 ** 2 Outbound 4703 **---------------------------------------------------------------------------------------------------- 4704 ** Doorbell Registers 1 Inbound Optional Optional 4705 ** 1 Outbound 4706 **---------------------------------------------------------------------------------------------------- 4707 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4708 **---------------------------------------------------------------------------------------------------- 4709 ** Index Registers 1004 32-bit Memory Locations No Optional 4710 **==================================================================================================== 4711 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4712 **==================================================================================================== 4713 ** 0000H Reserved 4714 ** 0004H Reserved 4715 ** 0008H Reserved 4716 ** 000CH Reserved 4717 **------------------------------------------------------------------------ 4718 ** 0010H Inbound Message Register 0 ] 4719 ** 0014H Inbound Message Register 1 ] 4720 ** 0018H Outbound Message Register 0 ] 4721 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4722 **------------------------------------------------------------------------ 4723 ** 0020H Inbound Doorbell Register ] 4724 ** 0024H Inbound Interrupt Status Register ] 4725 ** 0028H Inbound Interrupt Mask Register ] 4726 ** 002CH Outbound Doorbell Register ] 4727 ** 0030H Outbound Interrupt Status Register ] 4728 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4729 **------------------------------------------------------------------------ 4730 ** 0038H Reserved 4731 ** 003CH Reserved 4732 **------------------------------------------------------------------------ 4733 ** 0040H Inbound Queue Port ] 4734 ** 0044H Outbound Queue Port ] 2 Queue Ports 4735 **------------------------------------------------------------------------ 4736 ** 0048H Reserved 4737 ** 004CH Reserved 4738 **------------------------------------------------------------------------ 4739 ** 0050H ] 4740 ** : ] 4741 ** : Intel Xscale Microarchitecture Local Memory ] 4742 ** : ] 4743 ** 0FFCH ] 1004 Index Registers 4744 ******************************************************************************* 4745 */ 4746 /* 4747 ***************************************************************************** 4748 ** Theory of MU Operation 4749 ***************************************************************************** 4750 **-------------------- 4751 ** inbound_msgaddr0: 4752 ** inbound_msgaddr1: 4753 ** outbound_msgaddr0: 4754 ** outbound_msgaddr1: 4755 ** . The MU has four independent messaging mechanisms. 4756 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4757 ** Each holds a 32-bit value and generates an interrupt when written. 4758 **-------------------- 4759 ** inbound_doorbell: 4760 ** outbound_doorbell: 4761 ** . The two Doorbell Registers support software interrupts. 4762 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4763 **-------------------- 4764 ** inbound_queueport: 4765 ** outbound_queueport: 4766 ** 4767 ** 4768 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4769 ** The 4 circular queues are implemented in 80331 local memory. 4770 ** Two queues are used for inbound messages and two are used for outbound messages. 4771 ** Interrupts may be generated when the queue is written. 4772 **-------------------- 4773 ** local_buffer 0x0050 ....0x0FFF 4774 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4775 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4776 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4777 ** Each interrupt generated by the Messaging Unit can be masked. 4778 **-------------------- 4779 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4780 ** with the exception of Multi-DWORD reads to the index registers. 4781 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4782 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4783 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4784 ** and the data is returned through split completion transaction(s). 4785 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4786 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4787 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4788 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4789 **-------------------- 4790 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4791 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4792 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4793 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4794 **-------------------- 4795 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4796 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4797 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4798 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4799 **-------------------- 4800 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4801 ** The register interface, message registers, doorbell registers, 4802 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4803 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4804 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4805 ************************************************************************** 4806 */ 4807 /* 4808 ************************************************************************** 4809 ** Message Registers 4810 ** ============================== 4811 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4812 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4813 ** . Inbound messages are sent by the host processor and received by the 80331. 4814 ** Outbound messages are sent by the 80331 and received by the host processor. 4815 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4816 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4817 ** 4818 ** Inbound Messages: 4819 ** ----------------- 4820 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4821 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4822 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4823 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4824 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4825 ** The interrupt is cleared when the Intel XScale core writes a value of 4826 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4827 ** ------------------------------------------------------------------------ 4828 ** Inbound Message Register - IMRx 4829 ** 4830 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4831 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4832 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4833 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4834 ** ----------------------------------------------------------------- 4835 ** Bit Default Description 4836 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4837 ** When written, an interrupt to the Intel XScale core may be generated. 4838 ************************************************************************** 4839 */ 4840 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4841 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4842 /* 4843 ************************************************************************** 4844 ** Outbound Message Register - OMRx 4845 ** -------------------------------- 4846 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4847 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4848 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4849 ** Interrupt Mask Register. 4850 ** 4851 ** Bit Default Description 4852 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4853 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4854 ************************************************************************** 4855 */ 4856 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4857 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4858 /* 4859 ************************************************************************** 4860 ** Doorbell Registers 4861 ** ============================== 4862 ** There are two Doorbell Registers: 4863 ** Inbound Doorbell Register 4864 ** Outbound Doorbell Register 4865 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4866 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4867 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4868 ** 4869 ** Inbound Doorbells: 4870 ** ------------------ 4871 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4872 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4873 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4874 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4875 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4876 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4877 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4878 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4879 ** and not the values written to the Inbound Doorbell Register. 4880 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4881 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4882 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4883 ** ------------------------------------------------------------------------ 4884 ** Inbound Doorbell Register - IDR 4885 ** 4886 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4887 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4888 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4889 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4890 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4891 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4892 ** ------------------------------------------------------------------------ 4893 ** Bit Default Description 4894 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4895 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4896 ** When all bits are clear, do not generate a Normal Interrupt. 4897 ************************************************************************** 4898 */ 4899 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4900 /* 4901 ************************************************************************** 4902 ** Inbound Interrupt Status Register - IISR 4903 ** 4904 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4905 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4906 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4907 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4908 ** these two are routed to the Messaging Unit Error interrupt input. 4909 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4910 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4911 ** Some of the bits in this register are Read Only. 4912 ** For those bits, the interrupt must be cleared through another register. 4913 ** 4914 ** Bit Default Description 4915 ** 31:07 0000000H 0 2 Reserved 4916 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4917 ** when an Index Register has been written after a PCI transaction. 4918 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4919 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4920 ** An Error interrupt is generated for this condition. 4921 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4922 ** Once cleared, an interrupt does NOT be generated 4923 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4924 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4925 ** software must retain the information that the Inbound Post queue status is not empty. 4926 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4927 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4928 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4929 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4930 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4931 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4932 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4933 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4934 ************************************************************************** 4935 */ 4936 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4937 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4938 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4939 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4940 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4941 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4942 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4943 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4944 /* 4945 ************************************************************************** 4946 ** Inbound Interrupt Mask Register - IIMR 4947 ** 4948 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4949 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4950 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4951 ** They only affect the generation of the Intel XScale core interrupt. 4952 ** ------------------------------------------------------------------------ 4953 ** Bit Default Description 4954 ** 31:07 000000H 0 2 Reserved 4955 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4956 ** when an Index Register has been written after a PCI transaction. 4957 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4958 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4959 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4960 ** by the MU hardware when the Inbound Post Queue has been written. 4961 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4962 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4963 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4964 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4965 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4966 ** Interrupt generated by a write to the Inbound Message 1 Register. 4967 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4968 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4969 ************************************************************************** 4970 */ 4971 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4972 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4973 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4974 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4975 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4976 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4977 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4978 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4979 /* 4980 ************************************************************************** 4981 ** Outbound Doorbell Register - ODR 4982 ** 4983 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4984 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4985 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4986 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4987 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4988 ** be cleared by an external PCI agent. 4989 ** ---------------------------------------------------------------------- 4990 ** Bit Default Description 4991 ** 31 0 2 Reserved 4992 ** 30 0 2 Reserved. 4993 ** 29 0 2 Reserved 4994 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4995 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4996 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4997 ** When this bit is cleared, the P_INTC# interrupt output 4998 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4999 ** signal is deasserted. 5000 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 5001 ** (P_INTA# with BRG_EN and ARB_EN straps low) 5002 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 5003 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 5004 ** signal is deasserted. 5005 ************************************************************************** 5006 */ 5007 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 5008 /* 5009 ************************************************************************** 5010 ** Outbound Interrupt Status Register - OISR 5011 ** 5012 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 5013 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 5014 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 5015 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 5016 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 5017 ** register. 5018 ** ---------------------------------------------------------------------- 5019 ** Bit Default Description 5020 ** 31:05 000000H 000 2 Reserved 5021 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 5022 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 5023 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 5024 ** cleared when any prefetch data has been read from the Outbound Queue Port. 5025 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 5026 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 5027 ** Doorbell Register must all be clear. 5028 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 5029 ** written. Clearing this bit clears the interrupt. 5030 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 5031 ** written. Clearing this bit clears the interrupt. 5032 ************************************************************************** 5033 */ 5034 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 5035 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 5036 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 5037 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 5038 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 5039 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 5040 /* 5041 ************************************************************************** 5042 ** Outbound Interrupt Mask Register - OIMR 5043 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 5044 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 5045 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 5046 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 5047 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 5048 ** only affect the generation of the PCI interrupt. 5049 ** ---------------------------------------------------------------------- 5050 ** Bit Default Description 5051 ** 31:05 000000H Reserved 5052 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 5053 ** in the Outbound Doorbell Register is set. 5054 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 5055 ** the prefetch buffer is valid. 5056 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 5057 ** Doorbell Register. 5058 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 5059 ** generated by a write to the Outbound Message 1 Register. 5060 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 5061 ** generated by a write to the Outbound Message 0 Register. 5062 ************************************************************************** 5063 */ 5064 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 5065 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 5066 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 5067 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 5068 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 5069 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 5070 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 5071 /* 5072 ************************************************************************** 5073 ** 5074 ************************************************************************** 5075 */ 5076 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 5077 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 5078 /* 5079 ************************************************************************** 5080 ** Circular Queues 5081 ** ====================================================================== 5082 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 5083 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 5084 ** Inbound messages are either: 5085 ** �E posted messages by other processors for the Intel XScale core to process or 5086 ** �E free (or empty) messages that can be reused by other processors. 5087 ** Outbound messages are either: 5088 ** �E posted messages by the Intel XScale core for other processors to process or 5089 ** �E free (or empty) messages that can be reused by the Intel XScale core. 5090 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 5091 ** The four Circular Queues are used to pass messages in the following manner. 5092 ** . The two inbound queues are used to handle inbound messages 5093 ** and the two outbound queues are used to handle outbound messages. 5094 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 5095 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 5096 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 5097 ** 5098 ** ============================================================================================================= 5099 ** Circular Queue Summary 5100 ** _____________________________________________________________________________________________________________ 5101 ** | Queue Name | Purpose | Action on PCI Interface| 5102 ** |______________________|____________________________________________________________|_________________________| 5103 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 5104 ** | | waiting to be processed by the 80331 | | 5105 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 5106 ** | | available for use by other processors | | 5107 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 5108 ** | | that are being posted to the other processors | | 5109 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 5110 ** | | available for use by the 80331 | | 5111 ** |______________________|____________________________________________________________|_________________________| 5112 ** 5113 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 5114 ** queue and to receive free messages returning from the 80331. 5115 ** The host processor posts inbound messages, 5116 ** the Intel XScale core receives the posted message and when it is finished with the message, 5117 ** places it back on the inbound free queue for reuse by the host processor. 5118 ** 5119 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 5120 ** address space: 5121 ** Inbound Queue Port 5122 ** and Outbound Queue Port. 5123 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 5124 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 5125 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 5126 ** does not cause the MU hardware to increment the queue pointers. 5127 ** This is treated as when the PCI transaction did not occur. 5128 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 5129 ** ====================================================================================== 5130 ** Overview of Circular Queue Operation 5131 ** ====================================================================================== 5132 ** . The data storage for the circular queues must be provided by the 80331 local memory. 5133 ** . The base address of the circular queues is contained in the Queue Base Address Register. 5134 ** Each entry in the queue is a 32-bit data value. 5135 ** . Each read from or write to the queue may access only one queue entry. 5136 ** . Multi-DWORD accesses to the circular queues are not allowed. 5137 ** Sub-DWORD accesses are promoted to DWORD accesses. 5138 ** . Each circular queue has a head pointer and a tail pointer. 5139 ** The pointers are offsets from the Queue Base Address. 5140 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 5141 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 5142 ** Which unit maintains the pointer is determined by the writer of the queue. 5143 ** More details about the pointers are given in the queue descriptions below. 5144 ** The pointers are incremented after the queue access. 5145 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 5146 ** 5147 ** Messaging Unit... 5148 ** 5149 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 5150 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 5151 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 5152 ** . All four queues must be the same size and may be contiguous. 5153 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 5154 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 5155 ** . There is one base address for all four queues. 5156 ** It is stored in the Queue Base Address Register (QBAR). 5157 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 5158 ** here shows an example of how the circular queues should be set up based on the 5159 ** Intelligent I/O (I 2 O) Architecture Specification. 5160 ** Other ordering of the circular queues is possible. 5161 ** 5162 ** Queue Starting Address 5163 ** Inbound Free Queue QBAR 5164 ** Inbound Post Queue QBAR + Queue Size 5165 ** Outbound Post Queue QBAR + 2 * Queue Size 5166 ** Outbound Free Queue QBAR + 3 * Queue Size 5167 ** =================================================================================== 5168 ** Inbound Post Queue 5169 ** ------------------ 5170 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 5171 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 5172 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 5173 ** For a PCI write transaction that accesses the Inbound Queue Port, 5174 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 5175 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 5176 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 5177 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 5178 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 5179 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 5180 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 5181 ** that the full condition is recognized by the core processor. 5182 ** In addition, to guarantee that the queue does not get overwritten, 5183 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 5184 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 5185 ** Only a new message posting the in the inbound queue generates a new interrupt. 5186 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 5187 ** software must retain the information that the Inbound Post queue status. 5188 ** From the time that the PCI write transaction is received until the data is written 5189 ** in local memory and the Inbound Post Head Pointer Register is incremented, 5190 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 5191 ** The Intel XScale core may read messages from the Inbound Post Queue 5192 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 5193 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 5194 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 5195 ** the hardware retries any PCI writes until a slot in the queue becomes available. 5196 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 5197 ** =================================================================================== 5198 ** Inbound Free Queue 5199 ** ------------------ 5200 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 5201 ** This queue is read from the queue tail by external PCI agents. 5202 ** It is written to the queue head by the Intel XScale core. 5203 ** The tail pointer is maintained by the MU hardware. 5204 ** The head pointer is maintained by the Intel XScale core. 5205 ** For a PCI read transaction that accesses the Inbound Queue Port, 5206 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 5207 ** When the queue is not empty (head and tail pointers are not equal) 5208 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 5209 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 5210 ** the value of -1 (FFFF.FFFFH) is returned. 5211 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 5212 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 5213 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 5214 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 5215 ** When the PCI read access occurs, the data is read directly from the prefetch register. 5216 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 5217 ** when the head and tail pointers are equal and the queue is empty. 5218 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 5219 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 5220 ** and the Inbound Free Head Pointer Register is written. 5221 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 5222 ** A prefetch must appear atomic from the perspective of the external PCI agent. 5223 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 5224 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 5225 ** local memory location pointed to by the Inbound Free Head Pointer Register. 5226 ** The processor must then increment the Inbound Free Head Pointer Register. 5227 ** ================================================================================== 5228 ** Outbound Post Queue 5229 ** ------------------- 5230 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 5231 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 5232 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 5233 ** MU hardware. The head pointer is maintained by the Intel XScale core. 5234 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 5235 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 5236 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 5237 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 5238 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 5239 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 5240 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 5241 ** Register. 5242 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 5243 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 5244 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 5245 ** occurs, the data is read directly from the prefetch register. 5246 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 5247 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 5248 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 5249 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 5250 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 5251 ** Pointer Register when it adds messages to the queue. 5252 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 5253 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 5254 ** until the prefetch is completed. 5255 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 5256 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 5257 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 5258 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 5259 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 5260 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 5261 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 5262 ** increment the Outbound Post Head Pointer Register. 5263 ** ================================================== 5264 ** Outbound Free Queue 5265 ** ----------------------- 5266 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5267 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5268 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5269 ** XScale core. The head pointer is maintained by the MU hardware. 5270 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5271 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5272 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5273 ** Head Pointer Register. 5274 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5275 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5276 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5277 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5278 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5279 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5280 ** core processor. 5281 ** From the time that a PCI write transaction is received until the data is written in local memory and 5282 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5283 ** access the Outbound Free Queue Port is signalled a retry. 5284 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5285 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5286 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5287 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 5288 ** 5289 ** ================================================================================== 5290 ** Circular Queue Summary 5291 ** ---------------------- 5292 ** ________________________________________________________________________________________________________________________________________________ 5293 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5294 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5295 ** |Inbound Post | Inbound Queue | | | | | 5296 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5297 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5298 ** |Inbound Free | Inbound Queue | | | | | 5299 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5300 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5301 ** ================================================================================== 5302 ** Circular Queue Status Summary 5303 ** ---------------------- 5304 ** ____________________________________________________________________________________________________ 5305 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5306 ** |_____________________|________________|_____________________|_______________________________________| 5307 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5308 ** |_____________________|________________|_____________________|_______________________________________| 5309 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5310 ** |_____________________|________________|_____________________|_______________________________________| 5311 ************************************************************************** 5312 */ 5313 5314 /* 5315 ************************************************************************** 5316 ** Index Registers 5317 ** ======================== 5318 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5319 ** These registers are for inbound messages only. 5320 ** The interrupt is recorded in the Inbound Interrupt Status Register. 5321 ** The storage for the Index Registers is allocated from the 80331 local memory. 5322 ** PCI write accesses to the Index Registers write the data to local memory. 5323 ** PCI read accesses to the Index Registers read the data from local memory. 5324 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5325 ** to Inbound ATU Translate Value Register + FFFH. 5326 ** . The address of the first write access is stored in the Index Address Register. 5327 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5328 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 5329 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5330 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5331 ** Writes by the Intel XScale core to the local memory used by the Index Registers 5332 ** does not cause an interrupt and does not update the Index Address Register. 5333 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5334 ************************************************************************** 5335 */ 5336 /* 5337 ************************************************************************** 5338 ** Messaging Unit Internal Bus Memory Map 5339 ** ======================================= 5340 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5341 ** FFFF E300H reserved | 5342 ** .. .. | 5343 ** FFFF E30CH reserved | 5344 ** FFFF E310H Inbound Message Register 0 | Available through 5345 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5346 ** FFFF E318H Outbound Message Register 0 | 5347 ** FFFF E31CH Outbound Message Register 1 | or 5348 ** FFFF E320H Inbound Doorbell Register | 5349 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5350 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5351 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5352 ** FFFF E330H Outbound Interrupt Status Register | 5353 ** FFFF E334H Outbound Interrupt Mask Register | 5354 ** ______________________________________________________________________|________________________________________ 5355 ** FFFF E338H reserved | 5356 ** FFFF E33CH reserved | 5357 ** FFFF E340H reserved | 5358 ** FFFF E344H reserved | 5359 ** FFFF E348H reserved | 5360 ** FFFF E34CH reserved | 5361 ** FFFF E350H MU Configuration Register | 5362 ** FFFF E354H Queue Base Address Register | 5363 ** FFFF E358H reserved | 5364 ** FFFF E35CH reserved | must translate PCI address to 5365 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5366 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5367 ** FFFF E368H Inbound Post Head pointer Register | 5368 ** FFFF E36CH Inbound Post Tail Pointer Register | 5369 ** FFFF E370H Outbound Free Head Pointer Register | 5370 ** FFFF E374H Outbound Free Tail Pointer Register | 5371 ** FFFF E378H Outbound Post Head pointer Register | 5372 ** FFFF E37CH Outbound Post Tail Pointer Register | 5373 ** FFFF E380H Index Address Register | 5374 ** FFFF E384H reserved | 5375 ** .. .. | 5376 ** FFFF E3FCH reserved | 5377 ** ______________________________________________________________________|_______________________________________ 5378 ************************************************************************** 5379 */ 5380 /* 5381 ************************************************************************** 5382 ** MU Configuration Register - MUCR FFFF.E350H 5383 ** 5384 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5385 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 5386 ** The Circular Queues are disabled at reset to allow the software to initialize the head 5387 ** and tail pointer registers before any PCI accesses to the Queue Ports. 5388 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5389 ** ------------------------------------------------------------------------ 5390 ** Bit Default Description 5391 ** 31:06 000000H 00 2 Reserved 5392 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5393 ** All four queues are the same size. 5394 ** �E 00001 2 - 4K Entries (16 Kbytes) 5395 ** �E 00010 2 - 8K Entries (32 Kbytes) 5396 ** �E 00100 2 - 16K Entries (64 Kbytes) 5397 ** �E 01000 2 - 32K Entries (128 Kbytes) 5398 ** �E 10000 2 - 64K Entries (256 Kbytes) 5399 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5400 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5401 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5402 ** disabled. When set, the Circular Queues are fully enabled. 5403 ************************************************************************** 5404 */ 5405 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5406 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5407 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5408 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5409 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5410 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5411 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5412 /* 5413 ************************************************************************** 5414 ** Queue Base Address Register - QBAR 5415 ** 5416 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5417 ** The base address is required to be located on a 1 Mbyte address boundary. 5418 ** . All Circular Queue head and tail pointers are based on the QBAR. 5419 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5420 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5421 ** Warning: 5422 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5423 ** ------------------------------------------------------------------------ 5424 ** Bit Default Description 5425 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5426 ** 19:00 00000H Reserved 5427 ************************************************************************** 5428 */ 5429 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5430 /* 5431 ************************************************************************** 5432 ** Inbound Free Head Pointer Register - IFHPR 5433 ** 5434 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5435 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 5436 ** The Head Pointer must be aligned on a DWORD address boundary. 5437 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5438 ** Writes to the upper 12 bits of the register are ignored. 5439 ** This register is maintained by software. 5440 ** ------------------------------------------------------------------------ 5441 ** Bit Default Description 5442 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5443 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5444 ** 01:00 00 2 Reserved 5445 ************************************************************************** 5446 */ 5447 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5448 /* 5449 ************************************************************************** 5450 ** Inbound Free Tail Pointer Register - IFTPR 5451 ** 5452 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5453 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5454 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5455 ** of the register. Writes to the upper 12 bits of the register are ignored. 5456 ** ------------------------------------------------------------------------ 5457 ** Bit Default Description 5458 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5459 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5460 ** 01:00 00 2 Reserved 5461 ************************************************************************** 5462 */ 5463 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5464 /* 5465 ************************************************************************** 5466 ** Inbound Post Head Pointer Register - IPHPR 5467 ** 5468 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5469 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5470 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5471 ** of the register. Writes to the upper 12 bits of the register are ignored. 5472 ** ------------------------------------------------------------------------ 5473 ** Bit Default Description 5474 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5475 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5476 ** 01:00 00 2 Reserved 5477 ************************************************************************** 5478 */ 5479 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5480 /* 5481 ************************************************************************** 5482 ** Inbound Post Tail Pointer Register - IPTPR 5483 ** 5484 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5485 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5486 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5487 ** of the register. Writes to the upper 12 bits of the register are ignored. 5488 ** ------------------------------------------------------------------------ 5489 ** Bit Default Description 5490 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5491 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5492 ** 01:00 00 2 Reserved 5493 ************************************************************************** 5494 */ 5495 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5496 /* 5497 ************************************************************************** 5498 ** Index Address Register - IAR 5499 ** 5500 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5501 ** It is written by the MU when the Index Registers are written by a PCI agent. 5502 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5503 ** . The local memory address of the Index Register least recently accessed is computed 5504 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5505 ** ------------------------------------------------------------------------ 5506 ** Bit Default Description 5507 ** 31:12 000000H Reserved 5508 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5509 ** 01:00 00 2 Reserved 5510 ************************************************************************** 5511 */ 5512 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5513 /* 5514 ********************************************************************************************************** 5515 ** RS-232 Interface for Areca Raid Controller 5516 ** The low level command interface is exclusive with VT100 terminal 5517 ** -------------------------------------------------------------------- 5518 ** 1. Sequence of command execution 5519 ** -------------------------------------------------------------------- 5520 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5521 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5522 ** (C) Return data : variable length of data 5523 ** -------------------------------------------------------------------- 5524 ** 2. Command block 5525 ** -------------------------------------------------------------------- 5526 ** (A) 1st byte : command block length (low byte) 5527 ** (B) 2nd byte : command block length (high byte) 5528 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5529 ** (C) 3rd byte : command code 5530 ** (D) 4th and following bytes : variable length data bytes depends on command code 5531 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5532 ** -------------------------------------------------------------------- 5533 ** 3. Command code and associated data 5534 ** -------------------------------------------------------------------- 5535 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5536 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5537 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5538 ** enum 5539 ** { 5540 ** GUI_SET_SERIAL=0x10, 5541 ** GUI_SET_VENDOR, 5542 ** GUI_SET_MODEL, 5543 ** GUI_IDENTIFY, 5544 ** GUI_CHECK_PASSWORD, 5545 ** GUI_LOGOUT, 5546 ** GUI_HTTP, 5547 ** GUI_SET_ETHERNET_ADDR, 5548 ** GUI_SET_LOGO, 5549 ** GUI_POLL_EVENT, 5550 ** GUI_GET_EVENT, 5551 ** GUI_GET_HW_MONITOR, 5552 ** 5553 ** // GUI_QUICK_CREATE=0x20, (function removed) 5554 ** GUI_GET_INFO_R=0x20, 5555 ** GUI_GET_INFO_V, 5556 ** GUI_GET_INFO_P, 5557 ** GUI_GET_INFO_S, 5558 ** GUI_CLEAR_EVENT, 5559 ** 5560 ** GUI_MUTE_BEEPER=0x30, 5561 ** GUI_BEEPER_SETTING, 5562 ** GUI_SET_PASSWORD, 5563 ** GUI_HOST_INTERFACE_MODE, 5564 ** GUI_REBUILD_PRIORITY, 5565 ** GUI_MAX_ATA_MODE, 5566 ** GUI_RESET_CONTROLLER, 5567 ** GUI_COM_PORT_SETTING, 5568 ** GUI_NO_OPERATION, 5569 ** GUI_DHCP_IP, 5570 ** 5571 ** GUI_CREATE_PASS_THROUGH=0x40, 5572 ** GUI_MODIFY_PASS_THROUGH, 5573 ** GUI_DELETE_PASS_THROUGH, 5574 ** GUI_IDENTIFY_DEVICE, 5575 ** 5576 ** GUI_CREATE_RAIDSET=0x50, 5577 ** GUI_DELETE_RAIDSET, 5578 ** GUI_EXPAND_RAIDSET, 5579 ** GUI_ACTIVATE_RAIDSET, 5580 ** GUI_CREATE_HOT_SPARE, 5581 ** GUI_DELETE_HOT_SPARE, 5582 ** 5583 ** GUI_CREATE_VOLUME=0x60, 5584 ** GUI_MODIFY_VOLUME, 5585 ** GUI_DELETE_VOLUME, 5586 ** GUI_START_CHECK_VOLUME, 5587 ** GUI_STOP_CHECK_VOLUME 5588 ** }; 5589 ** 5590 ** Command description : 5591 ** 5592 ** GUI_SET_SERIAL : Set the controller serial# 5593 ** byte 0,1 : length 5594 ** byte 2 : command code 0x10 5595 ** byte 3 : password length (should be 0x0f) 5596 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5597 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5598 ** GUI_SET_VENDOR : Set vendor string for the controller 5599 ** byte 0,1 : length 5600 ** byte 2 : command code 0x11 5601 ** byte 3 : password length (should be 0x08) 5602 ** byte 4-0x13 : should be "ArEcAvAr" 5603 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5604 ** GUI_SET_MODEL : Set the model name of the controller 5605 ** byte 0,1 : length 5606 ** byte 2 : command code 0x12 5607 ** byte 3 : password length (should be 0x08) 5608 ** byte 4-0x13 : should be "ArEcAvAr" 5609 ** byte 0x14--0x1B : model string (must be 8 bytes) 5610 ** GUI_IDENTIFY : Identify device 5611 ** byte 0,1 : length 5612 ** byte 2 : command code 0x13 5613 ** return "Areca RAID Subsystem " 5614 ** GUI_CHECK_PASSWORD : Verify password 5615 ** byte 0,1 : length 5616 ** byte 2 : command code 0x14 5617 ** byte 3 : password length 5618 ** byte 4-0x?? : user password to be checked 5619 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5620 ** byte 0,1 : length 5621 ** byte 2 : command code 0x15 5622 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5623 ** 5624 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5625 ** byte 0,1 : length 5626 ** byte 2 : command code 0x17 5627 ** byte 3 : password length (should be 0x08) 5628 ** byte 4-0x13 : should be "ArEcAvAr" 5629 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5630 ** GUI_SET_LOGO : Set logo in HTTP 5631 ** byte 0,1 : length 5632 ** byte 2 : command code 0x18 5633 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5634 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5635 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5636 ** note .... page0 1st 2 byte must be actual length of the JPG file 5637 ** GUI_POLL_EVENT : Poll If Event Log Changed 5638 ** byte 0,1 : length 5639 ** byte 2 : command code 0x19 5640 ** GUI_GET_EVENT : Read Event 5641 ** byte 0,1 : length 5642 ** byte 2 : command code 0x1a 5643 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5644 ** GUI_GET_HW_MONITOR : Get HW monitor data 5645 ** byte 0,1 : length 5646 ** byte 2 : command code 0x1b 5647 ** byte 3 : # of FANs(example 2) 5648 ** byte 4 : # of Voltage sensor(example 3) 5649 ** byte 5 : # of temperature sensor(example 2) 5650 ** byte 6 : # of power 5651 ** byte 7/8 : Fan#0 (RPM) 5652 ** byte 9/10 : Fan#1 5653 ** byte 11/12 : Voltage#0 original value in *1000 5654 ** byte 13/14 : Voltage#0 value 5655 ** byte 15/16 : Voltage#1 org 5656 ** byte 17/18 : Voltage#1 5657 ** byte 19/20 : Voltage#2 org 5658 ** byte 21/22 : Voltage#2 5659 ** byte 23 : Temp#0 5660 ** byte 24 : Temp#1 5661 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5662 ** byte 26 : UPS indicator 5663 ** GUI_QUICK_CREATE : Quick create raid/volume set 5664 ** byte 0,1 : length 5665 ** byte 2 : command code 0x20 5666 ** byte 3/4/5/6 : raw capacity 5667 ** byte 7 : raid level 5668 ** byte 8 : stripe size 5669 ** byte 9 : spare 5670 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5671 ** This function is removed, application like to implement quick create function 5672 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5673 ** GUI_GET_INFO_R : Get Raid Set Information 5674 ** byte 0,1 : length 5675 ** byte 2 : command code 0x20 5676 ** byte 3 : raidset# 5677 ** 5678 ** typedef struct sGUI_RAIDSET 5679 ** { 5680 ** BYTE grsRaidSetName[16]; 5681 ** DWORD grsCapacity; 5682 ** DWORD grsCapacityX; 5683 ** DWORD grsFailMask; 5684 ** BYTE grsDevArray[32]; 5685 ** BYTE grsMemberDevices; 5686 ** BYTE grsNewMemberDevices; 5687 ** BYTE grsRaidState; 5688 ** BYTE grsVolumes; 5689 ** BYTE grsVolumeList[16]; 5690 ** BYTE grsRes1; 5691 ** BYTE grsRes2; 5692 ** BYTE grsRes3; 5693 ** BYTE grsFreeSegments; 5694 ** DWORD grsRawStripes[8]; 5695 ** DWORD grsRes4; 5696 ** DWORD grsRes5; // Total to 128 bytes 5697 ** DWORD grsRes6; // Total to 128 bytes 5698 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5699 ** GUI_GET_INFO_V : Get Volume Set Information 5700 ** byte 0,1 : length 5701 ** byte 2 : command code 0x21 5702 ** byte 3 : volumeset# 5703 ** 5704 ** typedef struct sGUI_VOLUMESET 5705 ** { 5706 ** BYTE gvsVolumeName[16]; // 16 5707 ** DWORD gvsCapacity; 5708 ** DWORD gvsCapacityX; 5709 ** DWORD gvsFailMask; 5710 ** DWORD gvsStripeSize; 5711 ** DWORD gvsNewFailMask; 5712 ** DWORD gvsNewStripeSize; 5713 ** DWORD gvsVolumeStatus; 5714 ** DWORD gvsProgress; // 32 5715 ** sSCSI_ATTR gvsScsi; 5716 ** BYTE gvsMemberDisks; 5717 ** BYTE gvsRaidLevel; // 8 5718 ** 5719 ** BYTE gvsNewMemberDisks; 5720 ** BYTE gvsNewRaidLevel; 5721 ** BYTE gvsRaidSetNumber; 5722 ** BYTE gvsRes0; // 4 5723 ** BYTE gvsRes1[4]; // 64 bytes 5724 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5725 ** 5726 ** GUI_GET_INFO_P : Get Physical Drive Information 5727 ** byte 0,1 : length 5728 ** byte 2 : command code 0x22 5729 ** byte 3 : drive # (from 0 to max-channels - 1) 5730 ** 5731 ** typedef struct sGUI_PHY_DRV 5732 ** { 5733 ** BYTE gpdModelName[40]; 5734 ** BYTE gpdSerialNumber[20]; 5735 ** BYTE gpdFirmRev[8]; 5736 ** DWORD gpdCapacity; 5737 ** DWORD gpdCapacityX; // Reserved for expansion 5738 ** BYTE gpdDeviceState; 5739 ** BYTE gpdPioMode; 5740 ** BYTE gpdCurrentUdmaMode; 5741 ** BYTE gpdUdmaMode; 5742 ** BYTE gpdDriveSelect; 5743 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5744 ** sSCSI_ATTR gpdScsi; 5745 ** BYTE gpdReserved[40]; // Total to 128 bytes 5746 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5747 ** 5748 ** GUI_GET_INFO_S : Get System Information 5749 ** byte 0,1 : length 5750 ** byte 2 : command code 0x23 5751 ** 5752 ** typedef struct sCOM_ATTR 5753 ** { 5754 ** BYTE comBaudRate; 5755 ** BYTE comDataBits; 5756 ** BYTE comStopBits; 5757 ** BYTE comParity; 5758 ** BYTE comFlowControl; 5759 ** } sCOM_ATTR, *pCOM_ATTR; 5760 ** 5761 ** typedef struct sSYSTEM_INFO 5762 ** { 5763 ** BYTE gsiVendorName[40]; 5764 ** BYTE gsiSerialNumber[16]; 5765 ** BYTE gsiFirmVersion[16]; 5766 ** BYTE gsiBootVersion[16]; 5767 ** BYTE gsiMbVersion[16]; 5768 ** BYTE gsiModelName[8]; 5769 ** BYTE gsiLocalIp[4]; 5770 ** BYTE gsiCurrentIp[4]; 5771 ** DWORD gsiTimeTick; 5772 ** DWORD gsiCpuSpeed; 5773 ** DWORD gsiICache; 5774 ** DWORD gsiDCache; 5775 ** DWORD gsiScache; 5776 ** DWORD gsiMemorySize; 5777 ** DWORD gsiMemorySpeed; 5778 ** DWORD gsiEvents; 5779 ** BYTE gsiMacAddress[6]; 5780 ** BYTE gsiDhcp; 5781 ** BYTE gsiBeeper; 5782 ** BYTE gsiChannelUsage; 5783 ** BYTE gsiMaxAtaMode; 5784 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5785 ** BYTE gsiRebuildPriority; 5786 ** sCOM_ATTR gsiComA; // 5 bytes 5787 ** sCOM_ATTR gsiComB; // 5 bytes 5788 ** BYTE gsiIdeChannels; 5789 ** BYTE gsiScsiHostChannels; 5790 ** BYTE gsiIdeHostChannels; 5791 ** BYTE gsiMaxVolumeSet; 5792 ** BYTE gsiMaxRaidSet; 5793 ** BYTE gsiEtherPort; // 1:if ether net port supported 5794 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5795 ** BYTE gsiRes[75]; 5796 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5797 ** 5798 ** GUI_CLEAR_EVENT : Clear System Event 5799 ** byte 0,1 : length 5800 ** byte 2 : command code 0x24 5801 ** 5802 ** GUI_MUTE_BEEPER : Mute current beeper 5803 ** byte 0,1 : length 5804 ** byte 2 : command code 0x30 5805 ** 5806 ** GUI_BEEPER_SETTING : Disable beeper 5807 ** byte 0,1 : length 5808 ** byte 2 : command code 0x31 5809 ** byte 3 : 0->disable, 1->enable 5810 ** 5811 ** GUI_SET_PASSWORD : Change password 5812 ** byte 0,1 : length 5813 ** byte 2 : command code 0x32 5814 ** byte 3 : pass word length ( must <= 15 ) 5815 ** byte 4 : password (must be alpha-numerical) 5816 ** 5817 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5818 ** byte 0,1 : length 5819 ** byte 2 : command code 0x33 5820 ** byte 3 : 0->Independent, 1->cluster 5821 ** 5822 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5823 ** byte 0,1 : length 5824 ** byte 2 : command code 0x34 5825 ** byte 3 : 0/1/2/3 (low->high) 5826 ** 5827 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5828 ** byte 0,1 : length 5829 ** byte 2 : command code 0x35 5830 ** byte 3 : 0/1/2/3 (133/100/66/33) 5831 ** 5832 ** GUI_RESET_CONTROLLER : Reset Controller 5833 ** byte 0,1 : length 5834 ** byte 2 : command code 0x36 5835 ** *Response with VT100 screen (discard it) 5836 ** 5837 ** GUI_COM_PORT_SETTING : COM port setting 5838 ** byte 0,1 : length 5839 ** byte 2 : command code 0x37 5840 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5841 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5842 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5843 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5844 ** byte 7 : parity (0:none, 1:off, 2:even) 5845 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5846 ** 5847 ** GUI_NO_OPERATION : No operation 5848 ** byte 0,1 : length 5849 ** byte 2 : command code 0x38 5850 ** 5851 ** GUI_DHCP_IP : Set DHCP option and local IP address 5852 ** byte 0,1 : length 5853 ** byte 2 : command code 0x39 5854 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5855 ** byte 4/5/6/7 : IP address 5856 ** 5857 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5858 ** byte 0,1 : length 5859 ** byte 2 : command code 0x40 5860 ** byte 3 : device # 5861 ** byte 4 : scsi channel (0/1) 5862 ** byte 5 : scsi id (0-->15) 5863 ** byte 6 : scsi lun (0-->7) 5864 ** byte 7 : tagged queue (1 : enabled) 5865 ** byte 8 : cache mode (1 : enabled) 5866 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5867 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5868 ** 5869 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5870 ** byte 0,1 : length 5871 ** byte 2 : command code 0x41 5872 ** byte 3 : device # 5873 ** byte 4 : scsi channel (0/1) 5874 ** byte 5 : scsi id (0-->15) 5875 ** byte 6 : scsi lun (0-->7) 5876 ** byte 7 : tagged queue (1 : enabled) 5877 ** byte 8 : cache mode (1 : enabled) 5878 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5879 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5880 ** 5881 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5882 ** byte 0,1 : length 5883 ** byte 2 : command code 0x42 5884 ** byte 3 : device# to be deleted 5885 ** 5886 ** GUI_IDENTIFY_DEVICE : Identify Device 5887 ** byte 0,1 : length 5888 ** byte 2 : command code 0x43 5889 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5890 ** byte 4/5/6/7 : IDE device mask to be flashed 5891 ** note .... no response data available 5892 ** 5893 ** GUI_CREATE_RAIDSET : Create Raid Set 5894 ** byte 0,1 : length 5895 ** byte 2 : command code 0x50 5896 ** byte 3/4/5/6 : device mask 5897 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5898 ** 5899 ** GUI_DELETE_RAIDSET : Delete Raid Set 5900 ** byte 0,1 : length 5901 ** byte 2 : command code 0x51 5902 ** byte 3 : raidset# 5903 ** 5904 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5905 ** byte 0,1 : length 5906 ** byte 2 : command code 0x52 5907 ** byte 3 : raidset# 5908 ** byte 4/5/6/7 : device mask for expansion 5909 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5910 ** byte 11/12/13 : repeat for each volume in the raidset .... 5911 ** 5912 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5913 ** byte 0,1 : length 5914 ** byte 2 : command code 0x53 5915 ** byte 3 : raidset# 5916 ** 5917 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5918 ** byte 0,1 : length 5919 ** byte 2 : command code 0x54 5920 ** byte 3/4/5/6 : device mask for hot spare creation 5921 ** 5922 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5923 ** byte 0,1 : length 5924 ** byte 2 : command code 0x55 5925 ** byte 3/4/5/6 : device mask for hot spare deletion 5926 ** 5927 ** GUI_CREATE_VOLUME : Create volume set 5928 ** byte 0,1 : length 5929 ** byte 2 : command code 0x60 5930 ** byte 3 : raidset# 5931 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5932 ** byte 20-27 : volume capacity (blocks) 5933 ** byte 28 : raid level 5934 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5935 ** byte 30 : channel 5936 ** byte 31 : ID 5937 ** byte 32 : LUN 5938 ** byte 33 : 1 enable tag 5939 ** byte 34 : 1 enable cache 5940 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5941 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5942 ** byte 36 : 1 to select quick init 5943 ** 5944 ** GUI_MODIFY_VOLUME : Modify volume Set 5945 ** byte 0,1 : length 5946 ** byte 2 : command code 0x61 5947 ** byte 3 : volumeset# 5948 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5949 ** byte 20-27 : new volume capacity (reserved) 5950 ** byte 28 : new raid level 5951 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5952 ** byte 30 : new channel 5953 ** byte 31 : new ID 5954 ** byte 32 : new LUN 5955 ** byte 33 : 1 enable tag 5956 ** byte 34 : 1 enable cache 5957 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5958 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5959 ** 5960 ** GUI_DELETE_VOLUME : Delete volume set 5961 ** byte 0,1 : length 5962 ** byte 2 : command code 0x62 5963 ** byte 3 : volumeset# 5964 ** 5965 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5966 ** byte 0,1 : length 5967 ** byte 2 : command code 0x63 5968 ** byte 3 : volumeset# 5969 ** 5970 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5971 ** byte 0,1 : length 5972 ** byte 2 : command code 0x64 5973 ** --------------------------------------------------------------------- 5974 ** 4. Returned data 5975 ** --------------------------------------------------------------------- 5976 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5977 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5978 ** (C) status or data : 5979 ** <1> If length == 1 ==> 1 byte status code 5980 ** #define GUI_OK 0x41 5981 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5982 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5983 ** #define GUI_NO_RAIDSET 0x44 5984 ** #define GUI_NO_VOLUMESET 0x45 5985 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5986 ** #define GUI_PARAMETER_ERROR 0x47 5987 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5988 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5989 ** #define GUI_INVALID_PASSWORD 0x4a 5990 ** #define GUI_NO_DISK_SPACE 0x4b 5991 ** #define GUI_CHECKSUM_ERROR 0x4c 5992 ** #define GUI_PASSWORD_REQUIRED 0x4d 5993 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5994 ** (E) Checksum : checksum of length and status or data byte 5995 ************************************************************************** 5996 */ 5997