xref: /freebsd/sys/dev/cesa/cesa.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (C) 2009-2011 Semihalf.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #ifndef _DEV_CESA_H_
30 #define _DEV_CESA_H_
31 
32 /* Maximum number of queued requests */
33 #define CESA_REQUESTS			256
34 
35 /*
36  * CESA is able to process data only in CESA SRAM, which is quite small (2 kB).
37  * We have to fit a packet there, which contains SA descriptor, keys, IV
38  * and data to be processed. Every request must be converted into chain of
39  * packets and each packet can hold about 1.75 kB of data.
40  *
41  * To process each packet we need at least 1 SA descriptor and at least 4 TDMA
42  * descriptors. However there are cases when we use 2 SA and 8 TDMA descriptors
43  * per packet. Number of used TDMA descriptors can increase beyond given values
44  * if data in the request is fragmented in physical memory.
45  *
46  * The driver uses preallocated SA and TDMA descriptors pools to get best
47  * performace. Size of these pools should match expected request size. Example:
48  *
49  * Expected average request size:			1.5 kB (Ethernet MTU)
50  * Packets per average request:				(1.5 kB / 1.75 kB) = 1
51  * SA decriptors per average request (worst case):	1 * 2 = 2
52  * TDMA desctiptors per average request (worst case):	1 * 8 = 8
53  *
54  * More TDMA descriptors should be allocated, if data fragmentation is expected
55  * (for example while processing mbufs larger than MCLBYTES). The driver may use
56  * 2 additional TDMA descriptors per each discontinuity in the physical data
57  * layout.
58  */
59 
60 /* Values below are optimized for requests containing about 1.5 kB of data */
61 #define CESA_SA_DESC_PER_REQ		2
62 #define CESA_TDMA_DESC_PER_REQ		8
63 
64 #define CESA_SA_DESCRIPTORS		(CESA_SA_DESC_PER_REQ * CESA_REQUESTS)
65 #define CESA_TDMA_DESCRIPTORS		(CESA_TDMA_DESC_PER_REQ * CESA_REQUESTS)
66 
67 /* Useful constants */
68 #define CESA_HMAC_TRUNC_LEN		12
69 #define CESA_MAX_FRAGMENTS		64
70 #define CESA_SRAM_SIZE			2048
71 
72 /*
73  * CESA_MAX_HASH_LEN is maximum length of hash generated by CESA.
74  * As CESA supports MD5, SHA1 and SHA-256 this equals to 32 bytes.
75  */
76 #define CESA_MAX_HASH_LEN		32
77 #define CESA_MAX_KEY_LEN		32
78 #define CESA_MAX_IV_LEN			16
79 #define CESA_MAX_HMAC_BLOCK_LEN		64
80 #define CESA_MAX_MKEY_LEN		CESA_MAX_HMAC_BLOCK_LEN
81 #define CESA_MAX_PACKET_SIZE		(CESA_SRAM_SIZE - CESA_DATA(0))
82 #define CESA_MAX_REQUEST_SIZE		65535
83 
84 /* Locking macros */
85 #define CESA_LOCK(sc, what)		mtx_lock(&(sc)->sc_ ## what ## _lock)
86 #define CESA_UNLOCK(sc, what)		mtx_unlock(&(sc)->sc_ ## what ## _lock)
87 #define CESA_LOCK_ASSERT(sc, what)	\
88 	mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED)
89 
90 /* Registers read/write macros */
91 #define CESA_REG_READ(sc, reg)		\
92 	bus_read_4((sc)->sc_res[RES_CESA_REGS], (reg))
93 #define CESA_REG_WRITE(sc, reg, val)	\
94 	bus_write_4((sc)->sc_res[RES_CESA_REGS], (reg), (val))
95 
96 #define CESA_TDMA_READ(sc, reg)		\
97 	bus_read_4((sc)->sc_res[RES_TDMA_REGS], (reg))
98 #define CESA_TDMA_WRITE(sc, reg, val)	\
99 	bus_write_4((sc)->sc_res[RES_TDMA_REGS], (reg), (val))
100 
101 /* Generic allocator for objects */
102 #define CESA_GENERIC_ALLOC_LOCKED(sc, obj, pool) do {		\
103 	CESA_LOCK(sc, pool);					\
104 								\
105 	if (STAILQ_EMPTY(&(sc)->sc_free_ ## pool))		\
106 		obj = NULL;					\
107 	else {							\
108 		obj = STAILQ_FIRST(&(sc)->sc_free_ ## pool);	\
109 		STAILQ_REMOVE_HEAD(&(sc)->sc_free_ ## pool,	\
110 		    obj ## _stq);				\
111 	}							\
112 								\
113 	CESA_UNLOCK(sc, pool);					\
114 } while (0)
115 
116 #define CESA_GENERIC_FREE_LOCKED(sc, obj, pool) do {		\
117 	CESA_LOCK(sc, pool);					\
118 	STAILQ_INSERT_TAIL(&(sc)->sc_free_ ## pool, obj,	\
119 	    obj ## _stq);					\
120 	CESA_UNLOCK(sc, pool);					\
121 } while (0)
122 
123 /* CESA SRAM offset calculation macros */
124 #define CESA_SA_DATA(member)					\
125 	(sizeof(struct cesa_sa_hdesc) + offsetof(struct cesa_sa_data, member))
126 #define CESA_DATA(offset)					\
127 	(sizeof(struct cesa_sa_hdesc) + sizeof(struct cesa_sa_data) + offset)
128 
129 /* CESA memory and IRQ resources */
130 enum cesa_res_type {
131 	RES_TDMA_REGS,
132 	RES_CESA_REGS,
133 	RES_CESA_IRQ,
134 	RES_CESA_NUM
135 };
136 
137 struct cesa_tdma_hdesc {
138 	uint16_t	cthd_byte_count;
139 	uint16_t	cthd_flags;
140 	uint32_t	cthd_src;
141 	uint32_t	cthd_dst;
142 	uint32_t	cthd_next;
143 };
144 
145 struct cesa_sa_hdesc {
146 	uint32_t	cshd_config;
147 	uint16_t	cshd_enc_src;
148 	uint16_t	cshd_enc_dst;
149 	uint32_t	cshd_enc_dlen;
150 	uint32_t	cshd_enc_key;
151 	uint16_t	cshd_enc_iv;
152 	uint16_t	cshd_enc_iv_buf;
153 	uint16_t	cshd_mac_src;
154 	uint16_t	cshd_mac_total_dlen;
155 	uint16_t	cshd_mac_dst;
156 	uint16_t	cshd_mac_dlen;
157 	uint16_t	cshd_mac_iv_in;
158 	uint16_t	cshd_mac_iv_out;
159 };
160 
161 struct cesa_sa_data {
162 	uint8_t		csd_key[CESA_MAX_KEY_LEN];
163 	uint8_t		csd_iv[CESA_MAX_IV_LEN];
164 	uint8_t		csd_hiv_in[CESA_MAX_HASH_LEN];
165 	uint8_t		csd_hiv_out[CESA_MAX_HASH_LEN];
166 	uint8_t		csd_hash[CESA_MAX_HASH_LEN];
167 };
168 
169 struct cesa_dma_mem {
170 	void		*cdm_vaddr;
171 	bus_addr_t	cdm_paddr;
172 	bus_dma_tag_t	cdm_tag;
173 	bus_dmamap_t	cdm_map;
174 };
175 
176 struct cesa_tdma_desc {
177 	struct cesa_tdma_hdesc		*ctd_cthd;
178 	bus_addr_t			ctd_cthd_paddr;
179 
180 	STAILQ_ENTRY(cesa_tdma_desc)	ctd_stq;
181 };
182 
183 struct cesa_sa_desc {
184 	struct cesa_sa_hdesc		*csd_cshd;
185 	bus_addr_t			csd_cshd_paddr;
186 
187 	STAILQ_ENTRY(cesa_sa_desc)	csd_stq;
188 };
189 
190 struct cesa_session {
191 	uint32_t			cs_config;
192 	unsigned int			cs_ivlen;
193 	unsigned int			cs_hlen;
194 	unsigned int			cs_mblen;
195 	uint8_t				cs_key[CESA_MAX_KEY_LEN];
196 	uint8_t				cs_aes_dkey[CESA_MAX_KEY_LEN];
197 	uint8_t				cs_hiv_in[CESA_MAX_HASH_LEN];
198 	uint8_t				cs_hiv_out[CESA_MAX_HASH_LEN];
199 };
200 
201 struct cesa_request {
202 	struct cesa_sa_data		*cr_csd;
203 	bus_addr_t			cr_csd_paddr;
204 	struct cryptop			*cr_crp;
205 	struct cesa_session		*cr_cs;
206 	bus_dmamap_t			cr_dmap;
207 	int				cr_dmap_loaded;
208 
209 	STAILQ_HEAD(, cesa_tdma_desc)	cr_tdesc;
210 	STAILQ_HEAD(, cesa_sa_desc)	cr_sdesc;
211 
212 	STAILQ_ENTRY(cesa_request)	cr_stq;
213 };
214 
215 struct cesa_packet {
216 	STAILQ_HEAD(, cesa_tdma_desc)	cp_copyin;
217 	STAILQ_HEAD(, cesa_tdma_desc)	cp_copyout;
218 	unsigned int			cp_size;
219 	unsigned int			cp_offset;
220 };
221 
222 struct cesa_softc {
223 	device_t			sc_dev;
224 	int32_t				sc_cid;
225 	uint32_t			sc_soc_id;
226 	struct resource			*sc_res[RES_CESA_NUM];
227 	void				*sc_icookie;
228 	bus_dma_tag_t			sc_data_dtag;
229 	int				sc_error;
230 	int				sc_tperr;
231 	uint8_t				sc_cesa_engine_id;
232 
233 	struct mtx			sc_sc_lock;
234 	int				sc_blocked;
235 
236 	/* TDMA descriptors pool */
237 	struct mtx			sc_tdesc_lock;
238 	struct cesa_tdma_desc		sc_tdesc[CESA_TDMA_DESCRIPTORS];
239 	struct cesa_dma_mem		sc_tdesc_cdm;
240 	STAILQ_HEAD(, cesa_tdma_desc)	sc_free_tdesc;
241 
242 	/* SA descriptors pool */
243 	struct mtx			sc_sdesc_lock;
244 	struct cesa_sa_desc		sc_sdesc[CESA_SA_DESCRIPTORS];
245 	struct cesa_dma_mem		sc_sdesc_cdm;
246 	STAILQ_HEAD(, cesa_sa_desc)	sc_free_sdesc;
247 
248 	/* Requests pool */
249 	struct mtx			sc_requests_lock;
250 	struct cesa_request		sc_requests[CESA_REQUESTS];
251 	struct cesa_dma_mem		sc_requests_cdm;
252 	STAILQ_HEAD(, cesa_request)	sc_free_requests;
253 	STAILQ_HEAD(, cesa_request)	sc_ready_requests;
254 	STAILQ_HEAD(, cesa_request)	sc_queued_requests;
255 
256 	struct mtx			sc_sessions_lock;
257 
258 	/* CESA SRAM Address */
259 	bus_addr_t			sc_sram_base_pa;
260 	void				*sc_sram_base_va;
261 	bus_size_t			sc_sram_size;
262 };
263 
264 struct cesa_chain_info {
265 	struct cesa_softc		*cci_sc;
266 	struct cesa_request		*cci_cr;
267 	uint32_t			cci_config;
268 	int				cci_error;
269 };
270 
271 /* CESA descriptors flags definitions */
272 #define CESA_CTHD_OWNED			(1 << 15)
273 
274 #define CESA_CSHD_MAC			(0 << 0)
275 #define CESA_CSHD_ENC			(1 << 0)
276 #define CESA_CSHD_MAC_AND_ENC		(2 << 0)
277 #define CESA_CSHD_ENC_AND_MAC		(3 << 0)
278 #define CESA_CSHD_OP_MASK		(3 << 0)
279 
280 #define CESA_CSHD_MD5			(4 << 4)
281 #define CESA_CSHD_SHA1			(5 << 4)
282 #define CESA_CSHD_SHA2_256		(1 << 4)
283 #define CESA_CSHD_MD5_HMAC		(6 << 4)
284 #define CESA_CSHD_SHA1_HMAC		(7 << 4)
285 #define CESA_CSHD_SHA2_256_HMAC		(3 << 4)
286 
287 #define CESA_CSHD_96_BIT_HMAC		(1 << 7)
288 
289 #define CESA_CSHD_DES			(1 << 8)
290 #define CESA_CSHD_3DES			(2 << 8)
291 #define CESA_CSHD_AES			(3 << 8)
292 
293 #define CESA_CSHD_DECRYPT		(1 << 12)
294 #define CESA_CSHD_CBC			(1 << 16)
295 #define CESA_CSHD_3DES_EDE		(1 << 20)
296 
297 #define CESA_CSH_AES_KLEN_128		(0 << 24)
298 #define CESA_CSH_AES_KLEN_192		(1 << 24)
299 #define CESA_CSH_AES_KLEN_256		(2 << 24)
300 #define CESA_CSH_AES_KLEN_MASK		(3 << 24)
301 
302 #define CESA_CSHD_FRAG_FIRST		(1 << 30)
303 #define CESA_CSHD_FRAG_LAST		(2U << 30)
304 #define CESA_CSHD_FRAG_MIDDLE		(3U << 30)
305 
306 /* CESA registers definitions */
307 #define CESA_ICR			0x0E20
308 #define CESA_ICR_ACCTDMA		(1 << 7)
309 #define CESA_ICR_TPERR			(1 << 12)
310 
311 #define CESA_ICM			0x0E24
312 #define CESA_ICM_ACCTDMA		CESA_ICR_ACCTDMA
313 #define CESA_ICM_TPERR			CESA_ICR_TPERR
314 
315 /* CESA TDMA registers definitions */
316 #define CESA_TDMA_ND			0x0830
317 
318 #define CESA_TDMA_CR			0x0840
319 #define CESA_TDMA_CR_DBL128		(4 << 0)
320 #define CESA_TDMA_CR_ORDEN		(1 << 4)
321 #define CESA_TDMA_CR_SBL128		(4 << 6)
322 #define CESA_TDMA_CR_NBS		(1 << 11)
323 #define CESA_TDMA_CR_ENABLE		(1 << 12)
324 #define CESA_TDMA_CR_FETCHND		(1 << 13)
325 #define CESA_TDMA_CR_ACTIVE		(1 << 14)
326 #define CESA_TDMA_NUM_OUTSTAND		(2 << 16)
327 
328 #define CESA_TDMA_ECR			0x08C8
329 #define CESA_TDMA_ECR_MISS		(1 << 0)
330 #define CESA_TDMA_ECR_DOUBLE_HIT	(1 << 1)
331 #define CESA_TDMA_ECR_BOTH_HIT		(1 << 2)
332 #define CESA_TDMA_ECR_DATA_ERROR	(1 << 3)
333 
334 #define CESA_TDMA_EMR			0x08CC
335 #define CESA_TDMA_EMR_MISS		CESA_TDMA_ECR_MISS
336 #define CESA_TDMA_EMR_DOUBLE_HIT	CESA_TDMA_ECR_DOUBLE_HIT
337 #define CESA_TDMA_EMR_BOTH_HIT		CESA_TDMA_ECR_BOTH_HIT
338 #define CESA_TDMA_EMR_DATA_ERROR	CESA_TDMA_ECR_DATA_ERROR
339 
340 /* CESA SA registers definitions */
341 #define CESA_SA_CMD			0x0E00
342 #define CESA_SA_CMD_ACTVATE		(1 << 0)
343 #define CESA_SA_CMD_SHA2		(1 << 31)
344 
345 #define CESA_SA_DPR			0x0E04
346 
347 #define CESA_SA_CR			0x0E08
348 #define CESA_SA_CR_WAIT_FOR_TDMA	(1 << 7)
349 #define CESA_SA_CR_ACTIVATE_TDMA	(1 << 9)
350 #define CESA_SA_CR_MULTI_MODE		(1 << 11)
351 
352 #define CESA_SA_SR			0x0E0C
353 #define CESA_SA_SR_ACTIVE		(1 << 0)
354 
355 #define CESA_TDMA_SIZE			0x1000
356 #define CESA_CESA_SIZE			0x1000
357 #define CESA0_TDMA_ADDR			0x90000
358 #define CESA0_CESA_ADDR			0x9D000
359 #define CESA1_TDMA_ADDR			0x92000
360 #define CESA1_CESA_ADDR			0x9F000
361 #endif
362