1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2000-2001 Jonathan Chen All rights reserved. 5 * Copyright (c) 2002-2004 M. Warner Losh <imp@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /*- 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/proc.h> 78 #include <sys/condvar.h> 79 #include <sys/errno.h> 80 #include <sys/kernel.h> 81 #include <sys/lock.h> 82 #include <sys/malloc.h> 83 #include <sys/mutex.h> 84 #include <sys/sysctl.h> 85 #include <sys/kthread.h> 86 #include <sys/bus.h> 87 #include <machine/bus.h> 88 #include <sys/rman.h> 89 #include <machine/resource.h> 90 #include <sys/module.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcib_private.h> 95 96 #include <dev/pccard/pccardreg.h> 97 #include <dev/pccard/pccardvar.h> 98 99 #include <dev/exca/excareg.h> 100 #include <dev/exca/excavar.h> 101 102 #include <dev/pccbb/pccbbreg.h> 103 #include <dev/pccbb/pccbbvar.h> 104 105 #include "power_if.h" 106 #include "card_if.h" 107 #include "pcib_if.h" 108 109 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 110 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 111 112 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 113 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 114 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 115 pci_write_config(DEV, REG, ( \ 116 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 117 118 static void cbb_chipinit(struct cbb_softc *sc); 119 static int cbb_pci_filt(void *arg); 120 121 static struct yenta_chipinfo { 122 uint32_t yc_id; 123 const char *yc_name; 124 int yc_chiptype; 125 } yc_chipsets[] = { 126 /* Texas Instruments chips */ 127 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 128 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 129 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 130 131 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 132 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 133 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 137 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 138 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 139 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 141 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 143 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 145 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 162 /* ENE */ 163 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 164 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 165 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 169 170 /* Ricoh chips */ 171 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 172 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 173 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 174 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 175 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 176 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 177 178 /* Toshiba products */ 179 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 180 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 181 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 182 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 183 184 /* Cirrus Logic */ 185 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 186 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 187 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 188 189 /* 02Micro */ 190 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 191 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 192 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 202 203 /* SMC */ 204 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 205 206 /* sentinel */ 207 {0 /* null id */, "unknown", CB_UNKNOWN}, 208 }; 209 210 /************************************************************************/ 211 /* Probe/Attach */ 212 /************************************************************************/ 213 214 static int 215 cbb_chipset(uint32_t pci_id, const char **namep) 216 { 217 struct yenta_chipinfo *ycp; 218 219 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 220 continue; 221 if (namep != NULL) 222 *namep = ycp->yc_name; 223 return (ycp->yc_chiptype); 224 } 225 226 static int 227 cbb_pci_probe(device_t brdev) 228 { 229 const char *name; 230 uint32_t progif; 231 uint32_t baseclass; 232 uint32_t subclass; 233 234 /* 235 * Do we know that we support the chipset? If so, then we 236 * accept the device. 237 */ 238 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 239 device_set_desc(brdev, name); 240 return (BUS_PROBE_DEFAULT); 241 } 242 243 /* 244 * We do support generic CardBus bridges. All that we've seen 245 * to date have progif 0 (the Yenta spec, and successors mandate 246 * this). 247 */ 248 baseclass = pci_get_class(brdev); 249 subclass = pci_get_subclass(brdev); 250 progif = pci_get_progif(brdev); 251 if (baseclass == PCIC_BRIDGE && 252 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 253 device_set_desc(brdev, "PCI-CardBus Bridge"); 254 return (BUS_PROBE_GENERIC); 255 } 256 return (ENXIO); 257 } 258 259 /* 260 * Print out the config space 261 */ 262 static void 263 cbb_print_config(device_t dev) 264 { 265 int i; 266 267 device_printf(dev, "PCI Configuration space:"); 268 for (i = 0; i < 256; i += 4) { 269 if (i % 16 == 0) 270 printf("\n 0x%02x: ", i); 271 printf("0x%08x ", pci_read_config(dev, i, 4)); 272 } 273 printf("\n"); 274 } 275 276 static int 277 cbb_pci_attach(device_t brdev) 278 { 279 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 280 struct sysctl_ctx_list *sctx; 281 struct sysctl_oid *soid; 282 int rid; 283 device_t parent; 284 285 parent = device_get_parent(brdev); 286 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 287 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 288 sc->dev = brdev; 289 sc->cbdev = NULL; 290 sc->domain = pci_get_domain(brdev); 291 sc->pribus = pcib_get_bus(parent); 292 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 293 pcib_setup_secbus(brdev, &sc->bus, 1); 294 SLIST_INIT(&sc->rl); 295 296 rid = CBBR_SOCKBASE; 297 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 298 RF_ACTIVE); 299 if (!sc->base_res) { 300 device_printf(brdev, "Could not map register memory\n"); 301 mtx_destroy(&sc->mtx); 302 return (ENOMEM); 303 } else { 304 DEVPRINTF((brdev, "Found memory at %jx\n", 305 rman_get_start(sc->base_res))); 306 } 307 308 /* attach children */ 309 sc->cbdev = device_add_child(brdev, "cardbus", DEVICE_UNIT_ANY); 310 if (sc->cbdev == NULL) 311 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 312 else if (device_probe_and_attach(sc->cbdev) != 0) 313 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 314 315 sc->bst = rman_get_bustag(sc->base_res); 316 sc->bsh = rman_get_bushandle(sc->base_res); 317 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 318 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 319 sc->exca.chipset = EXCA_CARDBUS; 320 sc->chipinit = cbb_chipinit; 321 sc->chipinit(sc); 322 323 /*Sysctls*/ 324 sctx = device_get_sysctl_ctx(brdev); 325 soid = device_get_sysctl_tree(brdev); 326 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 327 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 328 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 329 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 330 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 331 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 332 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 333 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 334 #if 0 335 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 336 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 337 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 338 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); 339 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 340 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 341 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 342 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 343 #endif 344 345 /* Map and establish the interrupt. */ 346 rid = 0; 347 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 348 RF_SHAREABLE | RF_ACTIVE); 349 if (sc->irq_res == NULL) { 350 device_printf(brdev, "Unable to map IRQ...\n"); 351 goto err; 352 } 353 354 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 355 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 356 device_printf(brdev, "couldn't establish interrupt\n"); 357 goto err; 358 } 359 360 /* reset 16-bit pcmcia bus */ 361 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 362 363 /* turn off power */ 364 cbb_power(brdev, CARD_OFF); 365 366 /* CSC Interrupt: Card detect interrupt on */ 367 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 368 369 /* reset interrupt */ 370 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 371 372 if (bootverbose) 373 cbb_print_config(brdev); 374 375 /* Start the thread */ 376 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 377 "%s event thread", device_get_nameunit(brdev))) { 378 device_printf(brdev, "unable to create event thread.\n"); 379 panic("cbb_create_event_thread"); 380 } 381 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 382 return (0); 383 err: 384 if (sc->irq_res) 385 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 386 if (sc->base_res) { 387 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 388 sc->base_res); 389 } 390 mtx_destroy(&sc->mtx); 391 return (ENOMEM); 392 } 393 394 static int 395 cbb_pci_detach(device_t brdev) 396 { 397 struct cbb_softc *sc = device_get_softc(brdev); 398 int error; 399 400 error = cbb_detach(brdev); 401 if (error == 0) 402 pcib_free_secbus(brdev, &sc->bus); 403 return (error); 404 } 405 406 static void 407 cbb_chipinit(struct cbb_softc *sc) 408 { 409 uint32_t mux, sysctrl, reg; 410 411 /* Set CardBus latency timer */ 412 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20) 413 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1); 414 415 /* Set PCI latency timer */ 416 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 417 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 418 419 /* Enable DMA, memory access for this card and I/O access for children */ 420 pci_enable_busmaster(sc->dev); 421 pci_enable_io(sc->dev, SYS_RES_IOPORT); 422 pci_enable_io(sc->dev, SYS_RES_MEMORY); 423 424 /* disable Legacy IO */ 425 switch (sc->chipset) { 426 case CB_RF5C46X: 427 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 428 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 429 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 430 break; 431 default: 432 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 433 break; 434 } 435 436 /* Use PCI interrupt for interrupt routing */ 437 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 438 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 439 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 440 | CBBM_BRIDGECTRL_WRITE_POST_EN, 441 2); 442 443 /* 444 * XXX this should be a function table, ala OLDCARD. This means 445 * that we could more easily support ISA interrupts for pccard 446 * cards if we had to. 447 */ 448 switch (sc->chipset) { 449 case CB_TI113X: 450 /* 451 * The TI 1031, TI 1130 and TI 1131 all require another bit 452 * be set to enable PCI routing of interrupts, and then 453 * a bit for each of the CSC and Function interrupts we 454 * want routed. 455 */ 456 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 457 | CBBM_CBCTRL_113X_PCI_INTR | 458 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 459 1); 460 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 461 & ~(CBBM_DEVCTRL_INT_SERIAL | 462 CBBM_DEVCTRL_INT_PCI), 1); 463 break; 464 case CB_TI12XX: 465 /* 466 * Some TI 12xx (and [14][45]xx) based pci cards 467 * sometimes have issues with the MFUNC register not 468 * being initialized due to a bad EEPROM on board. 469 * Laptops that this matters on have this register 470 * properly initialized. 471 * 472 * The TI125X parts have a different register. 473 * 474 * Note: Only the lower two nibbles matter. When set 475 * to 0, the MFUNC{0,1} pins are GPIO, which isn't 476 * going to work out too well because we specifically 477 * program these parts to parallel interrupt signalling 478 * elsewhere. We preserve the upper bits of this 479 * register since changing them have subtle side effects 480 * for different variants of the card and are 481 * extremely difficult to exaustively test. 482 * 483 * Also, the TI 1510/1520 changed the default for the MFUNC 484 * register from 0x0 to 0x1000 to enable IRQSER by default. 485 * We want to be careful to avoid overriding that, and the 486 * below test will do that. Should this check prove to be 487 * too permissive, we should just check against 0 and 0x1000 488 * and not touch it otherwise. 489 */ 490 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 491 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 492 if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) { 493 mux = (mux & ~CBBM_MFUNC_PIN0) | 494 CBBM_MFUNC_PIN0_INTA; 495 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 496 mux = (mux & ~CBBM_MFUNC_PIN1) | 497 CBBM_MFUNC_PIN1_INTB; 498 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 499 } 500 /*FALLTHROUGH*/ 501 case CB_TI125X: 502 /* 503 * Disable zoom video. Some machines initialize this 504 * improperly and exerpience has shown that this helps 505 * prevent strange behavior. We don't support zoom 506 * video anyway, so no harm can come from this. 507 */ 508 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 509 break; 510 case CB_O2MICRO: 511 /* 512 * Issue #1: INT# generated at the same time as 513 * selected ISA IRQ. When IREQ# or STSCHG# is active, 514 * in addition to the ISA IRQ being generated, INT# 515 * will also be generated at the same time. 516 * 517 * Some of the older controllers have an issue in 518 * which the slot's PCI INT# will be asserted whenever 519 * IREQ# or STSCGH# is asserted even if ExCA registers 520 * 03h or 05h have an ISA IRQ selected. 521 * 522 * The fix for this issue, which will work for any 523 * controller (old or new), is to set ExCA registers 524 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 525 * These bits are undocumented. By setting this 526 * register (of each slot) to '1010xxxxb' a routing of 527 * IREQ# to INTC# and STSCHG# to INTC# is selected. 528 * Since INTC# isn't connected there will be no 529 * unexpected PCI INT when IREQ# or STSCHG# is active. 530 * However, INTA# (slot 0) or INTB# (slot 1) will 531 * still be correctly generated if NO ISA IRQ is 532 * selected (ExCA regs 03h or 05h are cleared). 533 */ 534 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 535 reg = (reg & 0x0f) | 536 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 537 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 538 break; 539 case CB_TOPIC97: 540 /* 541 * Disable Zoom Video, ToPIC 97, 100. 542 */ 543 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 544 /* 545 * ToPIC 97, 100 546 * At offset 0xa1: INTERRUPT CONTROL register 547 * 0x1: Turn on INT interrupts. 548 */ 549 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 550 | TOPIC97_INTCTRL_INTIRQSEL, 1); 551 /* 552 * ToPIC97, 100 553 * Need to assert support for low voltage cards 554 */ 555 exca_setb(&sc->exca, EXCA_TOPIC97_CTRL, 556 EXCA_TOPIC97_CTRL_LV_MASK); 557 goto topic_common; 558 case CB_TOPIC95: 559 /* 560 * SOCKETCTRL appears to be TOPIC 95/B specific 561 */ 562 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 563 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 564 565 topic_common:; 566 /* 567 * At offset 0xa0: SLOT CONTROL 568 * 0x80 Enable CardBus Functionality 569 * 0x40 Enable CardBus and PC Card registers 570 * 0x20 Lock ID in exca regs 571 * 0x10 Write protect ID in config regs 572 * Clear the rest of the bits, which defaults the slot 573 * in legacy mode to 0x3e0 and offset 0. (legacy 574 * mode is determined elsewhere) 575 */ 576 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 577 TOPIC_SLOTCTRL_SLOTON | 578 TOPIC_SLOTCTRL_SLOTEN | 579 TOPIC_SLOTCTRL_ID_LOCK | 580 TOPIC_SLOTCTRL_ID_WP, 1); 581 582 /* 583 * At offset 0xa3 Card Detect Control Register 584 * 0x80 CARDBUS enbale 585 * 0x01 Cleared for hardware change detect 586 */ 587 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 588 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 589 break; 590 } 591 592 /* 593 * Need to tell ExCA registers to CSC interrupts route via PCI 594 * interrupts. There are two ways to do this. One is to set 595 * INTR_ENABLE and the other is to set CSC to 0. Since both 596 * methods are mutually compatible, we do both. 597 */ 598 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 599 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 600 601 cbb_disable_func_intr(sc); 602 603 /* close all memory and io windows */ 604 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 605 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 606 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 607 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 608 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 609 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 610 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 611 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 612 } 613 614 static int 615 cbb_route_interrupt(device_t pcib, device_t dev, int pin) 616 { 617 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 618 619 return (rman_get_start(sc->irq_res)); 620 } 621 622 static int 623 cbb_pci_shutdown(device_t brdev) 624 { 625 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 626 627 /* 628 * We're about to pull the rug out from the card, so mark it as 629 * gone to prevent harm. 630 */ 631 sc->cardok = 0; 632 633 /* 634 * Place the cards in reset, turn off the interrupts and power 635 * down the socket. 636 */ 637 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 638 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 639 cbb_set(sc, CBB_SOCKET_MASK, 0); 640 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 641 cbb_power(brdev, CARD_OFF); 642 643 /* 644 * For paranoia, turn off all address decoding. Really not needed, 645 * it seems, but it can't hurt 646 */ 647 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 648 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 649 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 650 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 651 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 652 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 653 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 654 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 655 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 656 return (0); 657 } 658 659 static int 660 cbb_pci_filt(void *arg) 661 { 662 struct cbb_softc *sc = arg; 663 uint32_t sockevent; 664 uint8_t csc; 665 int retval = FILTER_STRAY; 666 667 /* 668 * Some chips also require us to read the old ExCA registe for card 669 * status change when we route CSC vis PCI. This isn't supposed to be 670 * required, but it clears the interrupt state on some chipsets. 671 * Maybe there's a setting that would obviate its need. Maybe we 672 * should test the status bits and deal with them, but so far we've 673 * not found any machines that don't also give us the socket status 674 * indication above. 675 * 676 * This call used to be unconditional. However, further research 677 * suggests that we hit this condition when the card READY interrupt 678 * fired. So now we only read it for 16-bit cards, and we only claim 679 * the interrupt if READY is set. If this still causes problems, then 680 * the next step would be to read this if we have a 16-bit card *OR* 681 * we have no card. We treat the READY signal as if it were the power 682 * completion signal. Some bridges may double signal things here, bit 683 * signalling twice should be OK since we only sleep on the powerintr 684 * in one place and a double wakeup would be benign there. 685 */ 686 if (sc->flags & CBB_16BIT_CARD) { 687 csc = exca_getb(&sc->exca, EXCA_CSC); 688 if (csc & EXCA_CSC_READY) { 689 atomic_add_int(&sc->powerintr, 1); 690 wakeup((void *)&sc->powerintr); 691 retval = FILTER_HANDLED; 692 } 693 } 694 695 /* 696 * Read the socket event. Sometimes, the theory goes, the PCI bus is 697 * so loaded that it cannot satisfy the read request, so we get 698 * garbage back from the following read. We have to filter out the 699 * garbage so that we don't spontaneously reset the card under high 700 * load. PCI isn't supposed to act like this. No doubt this is a bug 701 * in the PCI bridge chipset (or cbb brige) that's being used in 702 * certain amd64 laptops today. Work around the issue by assuming 703 * that any bits we don't know about being set means that we got 704 * garbage. 705 */ 706 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 707 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 708 /* 709 * If anything has happened to the socket, we assume that the 710 * card is no longer OK, and we shouldn't call its ISR. We 711 * set cardok as soon as we've attached the card. This helps 712 * in a noisy eject, which happens all too often when users 713 * are ejecting their PC Cards. 714 * 715 * We use this method in preference to checking to see if the 716 * card is still there because the check suffers from a race 717 * condition in the bouncing case. 718 */ 719 #define DELTA (CBB_SOCKET_MASK_CD) 720 if (sockevent & DELTA) { 721 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 722 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 723 sc->cardok = 0; 724 cbb_disable_func_intr(sc); 725 wakeup(&sc->intrhand); 726 } 727 #undef DELTA 728 729 /* 730 * Wakeup anybody waiting for a power interrupt. We have to 731 * use atomic_add_int for wakups on other cores. 732 */ 733 if (sockevent & CBB_SOCKET_EVENT_POWER) { 734 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 735 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 736 atomic_add_int(&sc->powerintr, 1); 737 wakeup((void *)&sc->powerintr); 738 } 739 740 /* 741 * Status change interrupts aren't presently used in the 742 * rest of the driver. For now, just ACK them. 743 */ 744 if (sockevent & CBB_SOCKET_EVENT_CSTS) 745 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 746 retval = FILTER_HANDLED; 747 } 748 return retval; 749 } 750 751 static struct resource * 752 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 753 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 754 { 755 struct cbb_softc *sc; 756 757 sc = device_get_softc(bus); 758 if (type == PCI_RES_BUS) 759 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 760 count, flags)); 761 return (cbb_alloc_resource(bus, child, type, rid, start, end, count, 762 flags)); 763 } 764 765 static int 766 cbb_pci_adjust_resource(device_t bus, device_t child, 767 struct resource *r, rman_res_t start, rman_res_t end) 768 { 769 struct cbb_softc *sc; 770 771 sc = device_get_softc(bus); 772 if (rman_get_type(r) == PCI_RES_BUS) { 773 if (!rman_is_region_manager(r, &sc->bus.rman)) 774 return (EINVAL); 775 return (rman_adjust_resource(r, start, end)); 776 } 777 return (bus_generic_adjust_resource(bus, child, r, start, end)); 778 } 779 780 static int 781 cbb_pci_release_resource(device_t bus, device_t child, struct resource *r) 782 { 783 struct cbb_softc *sc; 784 int error; 785 786 sc = device_get_softc(bus); 787 if (rman_get_type(r) == PCI_RES_BUS) { 788 if (!rman_is_region_manager(r, &sc->bus.rman)) 789 return (EINVAL); 790 if (rman_get_flags(r) & RF_ACTIVE) { 791 error = bus_deactivate_resource(child, r); 792 if (error) 793 return (error); 794 } 795 return (rman_release_resource(r)); 796 } 797 return (cbb_release_resource(bus, child, r)); 798 } 799 800 /************************************************************************/ 801 /* PCI compat methods */ 802 /************************************************************************/ 803 804 static int 805 cbb_maxslots(device_t brdev) 806 { 807 return (0); 808 } 809 810 static uint32_t 811 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 812 { 813 /* 814 * Pass through to the next ppb up the chain (i.e. our grandparent). 815 */ 816 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 817 b, s, f, reg, width)); 818 } 819 820 static void 821 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 822 int width) 823 { 824 /* 825 * Pass through to the next ppb up the chain (i.e. our grandparent). 826 */ 827 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 828 b, s, f, reg, val, width); 829 } 830 831 static int 832 cbb_pci_suspend(device_t brdev) 833 { 834 int error = 0; 835 struct cbb_softc *sc = device_get_softc(brdev); 836 837 error = bus_generic_suspend(brdev); 838 if (error != 0) 839 return (error); 840 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 841 sc->cardok = 0; /* Card is bogus now */ 842 return (0); 843 } 844 845 static int 846 cbb_pci_resume(device_t brdev) 847 { 848 int error = 0; 849 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 850 uint32_t tmp; 851 852 /* 853 * In the APM and early ACPI era, BIOSes saved the PCI config 854 * registers. As chips became more complicated, that functionality moved 855 * into the ACPI code / tables. We must therefore, restore the settings 856 * we made here to make sure the device come back. Transitions to Dx 857 * from D0 and back to D0 cause the bridge to lose its config space, so 858 * all the bus mappings and such are preserved. 859 * 860 * The PCI layer handles standard PCI registers like the 861 * command register and BARs, but cbb-specific registers are 862 * handled here. 863 */ 864 sc->chipinit(sc); 865 866 /* reset interrupt -- Do we really need to do this? */ 867 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 868 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 869 870 /* CSC Interrupt: Card detect interrupt on */ 871 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 872 873 /* Signal the thread to wakeup. */ 874 wakeup(&sc->intrhand); 875 876 error = bus_generic_resume(brdev); 877 878 return (error); 879 } 880 881 static device_method_t cbb_methods[] = { 882 /* Device interface */ 883 DEVMETHOD(device_probe, cbb_pci_probe), 884 DEVMETHOD(device_attach, cbb_pci_attach), 885 DEVMETHOD(device_detach, cbb_pci_detach), 886 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 887 DEVMETHOD(device_suspend, cbb_pci_suspend), 888 DEVMETHOD(device_resume, cbb_pci_resume), 889 890 /* bus methods */ 891 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 892 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 893 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), 894 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), 895 DEVMETHOD(bus_release_resource, cbb_pci_release_resource), 896 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 897 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 898 DEVMETHOD(bus_driver_added, cbb_driver_added), 899 DEVMETHOD(bus_child_detached, cbb_child_detached), 900 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 901 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 902 DEVMETHOD(bus_child_present, cbb_child_present), 903 904 /* 16-bit card interface */ 905 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 906 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 907 908 /* power interface */ 909 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 910 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 911 912 /* pcib compatibility interface */ 913 DEVMETHOD(pcib_maxslots, cbb_maxslots), 914 DEVMETHOD(pcib_read_config, cbb_read_config), 915 DEVMETHOD(pcib_write_config, cbb_write_config), 916 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 917 918 DEVMETHOD_END 919 }; 920 921 static driver_t cbb_driver = { 922 "cbb", 923 cbb_methods, 924 sizeof(struct cbb_softc) 925 }; 926 927 DRIVER_MODULE(cbb, pci, cbb_driver, 0, 0); 928 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, cbb, yc_chipsets, 929 nitems(yc_chipsets) - 1); 930 MODULE_DEPEND(cbb, exca, 1, 1, 1); 931