1 /*-
2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/condvar.h>
31 #include <sys/kernel.h>
32 #include <sys/lock.h>
33 #include <sys/module.h>
34 #include <sys/mutex.h>
35 #include <sys/sbuf.h>
36 #include <sys/socket.h>
37 #include <sys/sysctl.h>
38 #include <sys/unistd.h>
39
40 #include <net/if.h>
41 #include <net/if_var.h>
42 #include <net/if_media.h>
43
44 /* needed for checksum offload */
45 #include <netinet/in.h>
46 #include <netinet/ip.h>
47
48 #include <dev/mii/mii.h>
49 #include <dev/mii/miivar.h>
50
51 #include <dev/usb/usb.h>
52 #include <dev/usb/usbdi.h>
53 #include <dev/usb/usbdi_util.h>
54 #include "usbdevs.h"
55
56 #define USB_DEBUG_VAR ure_debug
57 #include <dev/usb/usb_debug.h>
58 #include <dev/usb/usb_process.h>
59
60 #include <dev/usb/net/usb_ethernet.h>
61 #include <dev/usb/net/if_urereg.h>
62
63 #include "miibus_if.h"
64
65 #include "opt_inet6.h"
66
67 #ifdef USB_DEBUG
68 static int ure_debug = 0;
69
70 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
71 "USB ure");
72 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
73 "Debug level");
74 #endif
75
76 #ifdef USB_DEBUG_VAR
77 #ifdef USB_DEBUG
78 #define DEVPRINTFN(n,dev,fmt,...) do { \
79 if ((USB_DEBUG_VAR) >= (n)) { \
80 device_printf((dev), "%s: " fmt, \
81 __FUNCTION__ ,##__VA_ARGS__); \
82 } \
83 } while (0)
84 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__)
85 #else
86 #define DEVPRINTF(...) do { } while (0)
87 #define DEVPRINTFN(...) do { } while (0)
88 #endif
89 #endif
90
91 /*
92 * Various supported device vendors/products.
93 */
94 static const STRUCT_USB_HOST_ID ure_devs[] = {
95 #define URE_DEV(v,p,i) { \
96 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \
97 USB_IFACE_CLASS(UICLASS_VENDOR), \
98 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) }
99 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153),
100 URE_DEV(LENOVO, TBT3LANGEN2, 0),
101 URE_DEV(LENOVO, ONELINK, 0),
102 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153),
103 URE_DEV(LENOVO, ONELINKPLUS, URE_FLAG_8153),
104 URE_DEV(LENOVO, USBCLAN, 0),
105 URE_DEV(LENOVO, USBCLANGEN2, 0),
106 URE_DEV(LENOVO, USBCLANHYBRID, 0),
107 URE_DEV(MICROSOFT, WINDEVETH, 0),
108 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153),
109 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
110 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153),
111 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153),
112 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156),
113 #undef URE_DEV
114 };
115
116 static device_probe_t ure_probe;
117 static device_attach_t ure_attach;
118 static device_detach_t ure_detach;
119
120 static usb_callback_t ure_bulk_read_callback;
121 static usb_callback_t ure_bulk_write_callback;
122
123 static miibus_readreg_t ure_miibus_readreg;
124 static miibus_writereg_t ure_miibus_writereg;
125 static miibus_statchg_t ure_miibus_statchg;
126
127 static uether_fn_t ure_attach_post;
128 static uether_fn_t ure_init;
129 static uether_fn_t ure_stop;
130 static uether_fn_t ure_start;
131 static uether_fn_t ure_tick;
132 static uether_fn_t ure_rxfilter;
133
134 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
135 void *, int);
136 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
137 int);
138 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
139 int);
140 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
141 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
142 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
143 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
144 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
145 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
146 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
147 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
148 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t);
149
150 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS);
151
152 static void ure_read_chipver(struct ure_softc *);
153 static int ure_attach_post_sub(struct usb_ether *);
154 static void ure_reset(struct ure_softc *);
155 static int ure_ifmedia_upd(if_t);
156 static void ure_ifmedia_sts(if_t, struct ifmediareq *);
157 static void ure_add_media_types(struct ure_softc *);
158 static void ure_link_state(struct ure_softc *sc);
159 static int ure_get_link_status(struct ure_softc *);
160 static int ure_ioctl(if_t, u_long, caddr_t);
161 static void ure_rtl8152_init(struct ure_softc *);
162 static void ure_rtl8152_nic_reset(struct ure_softc *);
163 static void ure_rtl8153_init(struct ure_softc *);
164 static void ure_rtl8153b_init(struct ure_softc *);
165 static void ure_rtl8153b_nic_reset(struct ure_softc *);
166 static void ure_disable_teredo(struct ure_softc *);
167 static void ure_enable_aldps(struct ure_softc *, bool);
168 static uint16_t ure_phy_status(struct ure_softc *, uint16_t);
169 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m);
170 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout);
171
172 static device_method_t ure_methods[] = {
173 /* Device interface. */
174 DEVMETHOD(device_probe, ure_probe),
175 DEVMETHOD(device_attach, ure_attach),
176 DEVMETHOD(device_detach, ure_detach),
177
178 /* MII interface. */
179 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
180 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
181 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
182
183 DEVMETHOD_END
184 };
185
186 static driver_t ure_driver = {
187 .name = "ure",
188 .methods = ure_methods,
189 .size = sizeof(struct ure_softc),
190 };
191
192 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL);
193 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL);
194 MODULE_DEPEND(ure, uether, 1, 1, 1);
195 MODULE_DEPEND(ure, usb, 1, 1, 1);
196 MODULE_DEPEND(ure, ether, 1, 1, 1);
197 MODULE_DEPEND(ure, miibus, 1, 1, 1);
198 MODULE_VERSION(ure, 1);
199 USB_PNP_HOST_INFO(ure_devs);
200
201 static const struct usb_ether_methods ure_ue_methods = {
202 .ue_attach_post = ure_attach_post,
203 .ue_attach_post_sub = ure_attach_post_sub,
204 .ue_start = ure_start,
205 .ue_init = ure_init,
206 .ue_stop = ure_stop,
207 .ue_tick = ure_tick,
208 .ue_setmulti = ure_rxfilter,
209 .ue_setpromisc = ure_rxfilter,
210 .ue_mii_upd = ure_ifmedia_upd,
211 .ue_mii_sts = ure_ifmedia_sts,
212 };
213
214 #define URE_SETBIT_1(sc, reg, index, x) \
215 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
216 #define URE_SETBIT_2(sc, reg, index, x) \
217 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
218 #define URE_SETBIT_4(sc, reg, index, x) \
219 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
220
221 #define URE_CLRBIT_1(sc, reg, index, x) \
222 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
223 #define URE_CLRBIT_2(sc, reg, index, x) \
224 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
225 #define URE_CLRBIT_4(sc, reg, index, x) \
226 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
227
228 static int
ure_ctl(struct ure_softc * sc,uint8_t rw,uint16_t val,uint16_t index,void * buf,int len)229 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
230 void *buf, int len)
231 {
232 struct usb_device_request req;
233
234 URE_LOCK_ASSERT(sc, MA_OWNED);
235
236 if (rw == URE_CTL_WRITE)
237 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
238 else
239 req.bmRequestType = UT_READ_VENDOR_DEVICE;
240 req.bRequest = UR_SET_ADDRESS;
241 USETW(req.wValue, val);
242 USETW(req.wIndex, index);
243 USETW(req.wLength, len);
244
245 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
246 }
247
248 static int
ure_read_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)249 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
250 void *buf, int len)
251 {
252
253 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
254 }
255
256 static int
ure_write_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)257 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
258 void *buf, int len)
259 {
260
261 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
262 }
263
264 static uint8_t
ure_read_1(struct ure_softc * sc,uint16_t reg,uint16_t index)265 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
266 {
267 uint32_t val;
268 uint8_t temp[4];
269 uint8_t shift;
270
271 shift = (reg & 3) << 3;
272 reg &= ~3;
273
274 ure_read_mem(sc, reg, index, &temp, 4);
275 val = UGETDW(temp);
276 val >>= shift;
277
278 return (val & 0xff);
279 }
280
281 static uint16_t
ure_read_2(struct ure_softc * sc,uint16_t reg,uint16_t index)282 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
283 {
284 uint32_t val;
285 uint8_t temp[4];
286 uint8_t shift;
287
288 shift = (reg & 2) << 3;
289 reg &= ~3;
290
291 ure_read_mem(sc, reg, index, &temp, 4);
292 val = UGETDW(temp);
293 val >>= shift;
294
295 return (val & 0xffff);
296 }
297
298 static uint32_t
ure_read_4(struct ure_softc * sc,uint16_t reg,uint16_t index)299 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
300 {
301 uint8_t temp[4];
302
303 ure_read_mem(sc, reg, index, &temp, 4);
304 return (UGETDW(temp));
305 }
306
307 static int
ure_write_1(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)308 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
309 {
310 uint16_t byen;
311 uint8_t temp[4];
312 uint8_t shift;
313
314 byen = URE_BYTE_EN_BYTE;
315 shift = reg & 3;
316 val &= 0xff;
317
318 if (reg & 3) {
319 byen <<= shift;
320 val <<= (shift << 3);
321 reg &= ~3;
322 }
323
324 USETDW(temp, val);
325 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
326 }
327
328 static int
ure_write_2(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)329 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
330 {
331 uint16_t byen;
332 uint8_t temp[4];
333 uint8_t shift;
334
335 byen = URE_BYTE_EN_WORD;
336 shift = reg & 2;
337 val &= 0xffff;
338
339 if (reg & 2) {
340 byen <<= shift;
341 val <<= (shift << 3);
342 reg &= ~3;
343 }
344
345 USETDW(temp, val);
346 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
347 }
348
349 static int
ure_write_4(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)350 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
351 {
352 uint8_t temp[4];
353
354 USETDW(temp, val);
355 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
356 }
357
358 static uint16_t
ure_ocp_reg_read(struct ure_softc * sc,uint16_t addr)359 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
360 {
361 uint16_t reg;
362
363 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
364 reg = (addr & 0x0fff) | 0xb000;
365
366 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
367 }
368
369 static void
ure_ocp_reg_write(struct ure_softc * sc,uint16_t addr,uint16_t data)370 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
371 {
372 uint16_t reg;
373
374 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
375 reg = (addr & 0x0fff) | 0xb000;
376
377 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
378 }
379
380 static void
ure_sram_write(struct ure_softc * sc,uint16_t addr,uint16_t data)381 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
382 {
383 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr);
384 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data);
385 }
386
387 static int
ure_miibus_readreg(device_t dev,int phy,int reg)388 ure_miibus_readreg(device_t dev, int phy, int reg)
389 {
390 struct ure_softc *sc;
391 uint16_t val;
392 int locked;
393
394 sc = device_get_softc(dev);
395 locked = mtx_owned(&sc->sc_mtx);
396 if (!locked)
397 URE_LOCK(sc);
398
399 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
400 if (reg == URE_GMEDIASTAT) {
401 if (!locked)
402 URE_UNLOCK(sc);
403 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
404 }
405
406 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
407
408 if (!locked)
409 URE_UNLOCK(sc);
410 return (val);
411 }
412
413 static int
ure_miibus_writereg(device_t dev,int phy,int reg,int val)414 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
415 {
416 struct ure_softc *sc;
417 int locked;
418
419 sc = device_get_softc(dev);
420 if (sc->sc_phyno != phy)
421 return (0);
422
423 locked = mtx_owned(&sc->sc_mtx);
424 if (!locked)
425 URE_LOCK(sc);
426
427 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
428
429 if (!locked)
430 URE_UNLOCK(sc);
431 return (0);
432 }
433
434 static void
ure_miibus_statchg(device_t dev)435 ure_miibus_statchg(device_t dev)
436 {
437 struct ure_softc *sc;
438 struct mii_data *mii;
439 if_t ifp;
440 int locked;
441
442 sc = device_get_softc(dev);
443 mii = GET_MII(sc);
444 locked = mtx_owned(&sc->sc_mtx);
445 if (!locked)
446 URE_LOCK(sc);
447
448 ifp = uether_getifp(&sc->sc_ue);
449 if (mii == NULL || ifp == NULL ||
450 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
451 goto done;
452
453 sc->sc_flags &= ~URE_FLAG_LINK;
454 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
455 (IFM_ACTIVE | IFM_AVALID)) {
456 switch (IFM_SUBTYPE(mii->mii_media_active)) {
457 case IFM_10_T:
458 case IFM_100_TX:
459 sc->sc_flags |= URE_FLAG_LINK;
460 sc->sc_rxstarted = 0;
461 break;
462 case IFM_1000_T:
463 if ((sc->sc_flags & URE_FLAG_8152) != 0)
464 break;
465 sc->sc_flags |= URE_FLAG_LINK;
466 sc->sc_rxstarted = 0;
467 break;
468 default:
469 break;
470 }
471 }
472
473 /* Lost link, do nothing. */
474 if ((sc->sc_flags & URE_FLAG_LINK) == 0)
475 goto done;
476 done:
477 if (!locked)
478 URE_UNLOCK(sc);
479 }
480
481 /*
482 * Probe for a RTL8152/RTL8153/RTL8156 chip.
483 */
484 static int
ure_probe(device_t dev)485 ure_probe(device_t dev)
486 {
487 struct usb_attach_arg *uaa;
488
489 uaa = device_get_ivars(dev);
490 if (uaa->usb_mode != USB_MODE_HOST)
491 return (ENXIO);
492 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
493 return (ENXIO);
494
495 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
496 }
497
498 /*
499 * Attach the interface. Allocate softc structures, do ifmedia
500 * setup and ethernet/BPF attach.
501 */
502 static int
ure_attach(device_t dev)503 ure_attach(device_t dev)
504 {
505 struct usb_attach_arg *uaa = device_get_ivars(dev);
506 struct ure_softc *sc = device_get_softc(dev);
507 struct usb_ether *ue = &sc->sc_ue;
508 struct usb_config ure_config_rx[URE_MAX_RX];
509 struct usb_config ure_config_tx[URE_MAX_TX];
510 uint8_t iface_index;
511 int error;
512 int i;
513
514 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
515 device_set_usb_desc(dev);
516 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
517
518 iface_index = URE_IFACE_IDX;
519
520 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B))
521 sc->sc_rxbufsz = URE_8153_RX_BUFSZ;
522 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
523 sc->sc_rxbufsz = URE_8156_RX_BUFSZ;
524 else
525 sc->sc_rxbufsz = URE_8152_RX_BUFSZ;
526
527 for (i = 0; i < URE_MAX_RX; i++) {
528 ure_config_rx[i] = (struct usb_config) {
529 .type = UE_BULK,
530 .endpoint = UE_ADDR_ANY,
531 .direction = UE_DIR_IN,
532 .bufsize = sc->sc_rxbufsz,
533 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
534 .callback = ure_bulk_read_callback,
535 .timeout = 0, /* no timeout */
536 };
537 }
538 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer,
539 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx);
540 if (error != 0) {
541 device_printf(dev, "allocating USB RX transfers failed\n");
542 goto detach;
543 }
544
545 for (i = 0; i < URE_MAX_TX; i++) {
546 ure_config_tx[i] = (struct usb_config) {
547 .type = UE_BULK,
548 .endpoint = UE_ADDR_ANY,
549 .direction = UE_DIR_OUT,
550 .bufsize = URE_TX_BUFSZ,
551 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
552 .callback = ure_bulk_write_callback,
553 .timeout = 10000, /* 10 seconds */
554 };
555 }
556 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer,
557 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx);
558 if (error != 0) {
559 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
560 device_printf(dev, "allocating USB TX transfers failed\n");
561 goto detach;
562 }
563
564 ue->ue_sc = sc;
565 ue->ue_dev = dev;
566 ue->ue_udev = uaa->device;
567 ue->ue_mtx = &sc->sc_mtx;
568 ue->ue_methods = &ure_ue_methods;
569
570 error = uether_ifattach(ue);
571 if (error != 0) {
572 device_printf(dev, "could not attach interface\n");
573 goto detach;
574 }
575 return (0); /* success */
576
577 detach:
578 ure_detach(dev);
579 return (ENXIO); /* failure */
580 }
581
582 static int
ure_detach(device_t dev)583 ure_detach(device_t dev)
584 {
585 struct ure_softc *sc = device_get_softc(dev);
586 struct usb_ether *ue = &sc->sc_ue;
587
588 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX);
589 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
590 uether_ifdetach(ue);
591 mtx_destroy(&sc->sc_mtx);
592
593 return (0);
594 }
595
596 /*
597 * Copy from USB buffers to a new mbuf chain with pkt header.
598 *
599 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf
600 * clusters as necessary.
601 */
602 static struct mbuf *
ure_makembuf(struct usb_page_cache * pc,usb_frlength_t offset,usb_frlength_t len)603 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset,
604 usb_frlength_t len)
605 {
606 struct usb_page_search_res;
607 struct mbuf *m, *mb;
608 usb_frlength_t tlen;
609
610 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR);
611 if (m == NULL)
612 return (m);
613
614 /* uether_newbuf does this. */
615 m_adj(m, ETHER_ALIGN);
616
617 m->m_pkthdr.len = len;
618
619 for (mb = m; len > 0; mb = mb->m_next) {
620 tlen = MIN(len, M_TRAILINGSPACE(mb));
621
622 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen);
623 mb->m_len = tlen;
624
625 offset += tlen;
626 len -= tlen;
627 }
628
629 return (m);
630 }
631
632 static void
ure_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)633 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
634 {
635 struct ure_softc *sc = usbd_xfer_softc(xfer);
636 struct usb_ether *ue = &sc->sc_ue;
637 if_t ifp = uether_getifp(ue);
638 struct usb_page_cache *pc;
639 struct mbuf *m;
640 struct ure_rxpkt pkt;
641 int actlen, off, len;
642 int caps;
643 uint32_t pktcsum;
644
645 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
646
647 switch (USB_GET_STATE(xfer)) {
648 case USB_ST_TRANSFERRED:
649 off = 0;
650 pc = usbd_xfer_get_frame(xfer, 0);
651 caps = if_getcapenable(ifp);
652 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n");
653 while (actlen > 0) {
654 if (actlen < (int)(sizeof(pkt))) {
655 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
656 goto tr_setup;
657 }
658 usbd_copy_out(pc, off, &pkt, sizeof(pkt));
659
660 off += sizeof(pkt);
661 actlen -= sizeof(pkt);
662
663 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
664
665 DEVPRINTFN(13, sc->sc_ue.ue_dev,
666 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n",
667 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc,
668 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4);
669 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len);
670
671 if (len >= URE_RXPKT_LEN_MASK) {
672 /*
673 * drop the rest of this segment. With out
674 * more information, we cannot know where next
675 * packet starts. Blindly continuing would
676 * cause a packet in packet attack, allowing
677 * one VLAN to inject packets w/o a VLAN tag,
678 * or injecting packets into other VLANs.
679 */
680 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
681 goto tr_setup;
682 }
683
684 if (actlen < len) {
685 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
686 goto tr_setup;
687 }
688
689 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN))
690 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN);
691 else
692 m = NULL;
693 if (m == NULL) {
694 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
695 } else {
696 /* make mbuf and queue */
697 pktcsum = le32toh(pkt.ure_csum);
698 if (caps & IFCAP_VLAN_HWTAGGING &&
699 pktcsum & URE_RXPKT_RX_VLAN_TAG) {
700 m->m_pkthdr.ether_vtag =
701 bswap16(pktcsum &
702 URE_RXPKT_VLAN_MASK);
703 m->m_flags |= M_VLANTAG;
704 }
705
706 /* set the necessary flags for rx checksum */
707 ure_rxcsum(caps, &pkt, m);
708
709 uether_rxmbuf(ue, m, len - ETHER_CRC_LEN);
710 }
711
712 off += roundup(len, URE_RXPKT_ALIGN);
713 actlen -= roundup(len, URE_RXPKT_ALIGN);
714 }
715 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n");
716
717 /* FALLTHROUGH */
718 case USB_ST_SETUP:
719 tr_setup:
720 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
721 usbd_transfer_submit(xfer);
722 uether_rxflush(ue);
723 return;
724
725 default: /* Error */
726 DPRINTF("bulk read error, %s\n",
727 usbd_errstr(error));
728
729 if (error != USB_ERR_CANCELLED) {
730 /* try to clear stall first */
731 usbd_xfer_set_stall(xfer);
732 goto tr_setup;
733 }
734 return;
735 }
736 }
737
738 static void
ure_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)739 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
740 {
741 struct ure_softc *sc = usbd_xfer_softc(xfer);
742 if_t ifp = uether_getifp(&sc->sc_ue);
743 struct usb_page_cache *pc;
744 struct mbuf *m;
745 struct ure_txpkt txpkt;
746 uint32_t regtmp;
747 int len, pos;
748 int rem;
749 int caps;
750
751 switch (USB_GET_STATE(xfer)) {
752 case USB_ST_TRANSFERRED:
753 DPRINTFN(11, "transfer complete\n");
754 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
755
756 /* FALLTHROUGH */
757 case USB_ST_SETUP:
758 tr_setup:
759 if ((sc->sc_flags & URE_FLAG_LINK) == 0) {
760 /* don't send anything if there is no link! */
761 break;
762 }
763
764 pc = usbd_xfer_get_frame(xfer, 0);
765 caps = if_getcapenable(ifp);
766
767 pos = 0;
768 rem = URE_TX_BUFSZ;
769 while (rem > sizeof(txpkt)) {
770 m = if_dequeue(ifp);
771 if (m == NULL)
772 break;
773
774 /*
775 * make sure we don't ever send too large of a
776 * packet
777 */
778 len = m->m_pkthdr.len;
779 if ((len & URE_TXPKT_LEN_MASK) != len) {
780 device_printf(sc->sc_ue.ue_dev,
781 "pkt len too large: %#x", len);
782 pkterror:
783 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
784 m_freem(m);
785 continue;
786 }
787
788 if (sizeof(txpkt) +
789 roundup(len, URE_TXPKT_ALIGN) > rem) {
790 /* out of space */
791 if_sendq_prepend(ifp, m);
792 m = NULL;
793 break;
794 }
795
796 txpkt = (struct ure_txpkt){};
797 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
798 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
799 if (m->m_flags & M_VLANTAG) {
800 txpkt.ure_csum = htole32(
801 bswap16(m->m_pkthdr.ether_vtag &
802 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN);
803 }
804 if (ure_txcsum(m, caps, ®tmp)) {
805 device_printf(sc->sc_ue.ue_dev,
806 "pkt l4 off too large");
807 goto pkterror;
808 }
809 txpkt.ure_csum |= htole32(regtmp);
810
811 DEVPRINTFN(13, sc->sc_ue.ue_dev,
812 "txpkt: mbflg: %#x, %#x, %#x\n",
813 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen),
814 le32toh(txpkt.ure_csum));
815
816 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
817
818 pos += sizeof(txpkt);
819 rem -= sizeof(txpkt);
820
821 usbd_m_copy_in(pc, pos, m, 0, len);
822
823 pos += roundup(len, URE_TXPKT_ALIGN);
824 rem -= roundup(len, URE_TXPKT_ALIGN);
825
826 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
827
828 /*
829 * If there's a BPF listener, bounce a copy
830 * of this frame to him.
831 */
832 BPF_MTAP(ifp, m);
833
834 m_freem(m);
835 }
836
837 /* no packets to send */
838 if (pos == 0)
839 break;
840
841 /* Set frame length. */
842 usbd_xfer_set_frame_len(xfer, 0, pos);
843
844 usbd_transfer_submit(xfer);
845
846 return;
847
848 default: /* Error */
849 DPRINTFN(11, "transfer error, %s\n",
850 usbd_errstr(error));
851
852 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
853 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
854
855 if (error == USB_ERR_TIMEOUT) {
856 DEVPRINTFN(12, sc->sc_ue.ue_dev,
857 "pkt tx timeout\n");
858 }
859
860 if (error != USB_ERR_CANCELLED) {
861 /* try to clear stall first */
862 usbd_xfer_set_stall(xfer);
863 goto tr_setup;
864 }
865 }
866 }
867
868 static void
ure_read_chipver(struct ure_softc * sc)869 ure_read_chipver(struct ure_softc *sc)
870 {
871 uint16_t ver;
872
873 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
874 sc->sc_ver = ver;
875 switch (ver) {
876 case 0x4c00:
877 sc->sc_chip |= URE_CHIP_VER_4C00;
878 sc->sc_flags = URE_FLAG_8152;
879 break;
880 case 0x4c10:
881 sc->sc_chip |= URE_CHIP_VER_4C10;
882 sc->sc_flags = URE_FLAG_8152;
883 break;
884 case 0x5c00:
885 sc->sc_chip |= URE_CHIP_VER_5C00;
886 sc->sc_flags = URE_FLAG_8153;
887 break;
888 case 0x5c10:
889 sc->sc_chip |= URE_CHIP_VER_5C10;
890 sc->sc_flags = URE_FLAG_8153;
891 break;
892 case 0x5c20:
893 sc->sc_chip |= URE_CHIP_VER_5C20;
894 sc->sc_flags = URE_FLAG_8153;
895 break;
896 case 0x5c30:
897 sc->sc_chip |= URE_CHIP_VER_5C30;
898 sc->sc_flags = URE_FLAG_8153;
899 break;
900 case 0x6000:
901 sc->sc_flags = URE_FLAG_8153B;
902 sc->sc_chip |= URE_CHIP_VER_6000;
903 break;
904 case 0x6010:
905 sc->sc_flags = URE_FLAG_8153B;
906 sc->sc_chip |= URE_CHIP_VER_6010;
907 break;
908 case 0x7020:
909 sc->sc_flags = URE_FLAG_8156;
910 sc->sc_chip |= URE_CHIP_VER_7020;
911 break;
912 case 0x7030:
913 sc->sc_flags = URE_FLAG_8156;
914 sc->sc_chip |= URE_CHIP_VER_7030;
915 break;
916 case 0x7400:
917 sc->sc_flags = URE_FLAG_8156B;
918 sc->sc_chip |= URE_CHIP_VER_7400;
919 break;
920 case 0x7410:
921 sc->sc_flags = URE_FLAG_8156B;
922 sc->sc_chip |= URE_CHIP_VER_7410;
923 break;
924 default:
925 device_printf(sc->sc_ue.ue_dev,
926 "unknown version 0x%04x\n", ver);
927 break;
928 }
929 }
930
931 static int
ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)932 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)
933 {
934 struct sbuf sb;
935 struct ure_softc *sc = arg1;
936 int error;
937
938 sbuf_new_for_sysctl(&sb, NULL, 0, req);
939
940 sbuf_printf(&sb, "%04x", sc->sc_ver);
941
942 error = sbuf_finish(&sb);
943 sbuf_delete(&sb);
944
945 return (error);
946 }
947
948 static void
ure_attach_post(struct usb_ether * ue)949 ure_attach_post(struct usb_ether *ue)
950 {
951 struct ure_softc *sc = uether_getsc(ue);
952
953 sc->sc_rxstarted = 0;
954 sc->sc_phyno = 0;
955
956 /* Determine the chip version. */
957 ure_read_chipver(sc);
958
959 /* Initialize controller and get station address. */
960 if (sc->sc_flags & URE_FLAG_8152)
961 ure_rtl8152_init(sc);
962 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
963 ure_rtl8153b_init(sc);
964 else
965 ure_rtl8153_init(sc);
966
967 if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
968 (sc->sc_chip & URE_CHIP_VER_4C10))
969 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
970 ue->ue_eaddr, 8);
971 else
972 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
973 ue->ue_eaddr, 8);
974
975 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
976 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
977 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
978 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
979 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */
980 }
981 }
982
983 static int
ure_attach_post_sub(struct usb_ether * ue)984 ure_attach_post_sub(struct usb_ether *ue)
985 {
986 struct sysctl_ctx_list *sctx;
987 struct sysctl_oid *soid;
988 struct ure_softc *sc;
989 if_t ifp;
990 int error;
991
992 sc = uether_getsc(ue);
993 ifp = ue->ue_ifp;
994 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
995 if_setstartfn(ifp, uether_start);
996 if_setioctlfn(ifp, ure_ioctl);
997 if_setinitfn(ifp, uether_init);
998 /*
999 * Try to keep two transfers full at a time.
1000 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight)
1001 */
1002 if_setsendqlen(ifp, 512);
1003 if_setsendqready(ifp);
1004
1005 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1006 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
1007 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);
1008 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1009 #ifdef INET6
1010 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);
1011 #endif
1012 if_setcapenable(ifp, if_getcapabilities(ifp));
1013
1014 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1015 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd,
1016 ure_ifmedia_sts);
1017 ure_add_media_types(sc);
1018 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1019 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
1020 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
1021 error = 0;
1022 } else {
1023 bus_topo_lock();
1024 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
1025 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
1026 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
1027 bus_topo_unlock();
1028 }
1029
1030 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev);
1031 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev);
1032 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver",
1033 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1034 ure_sysctl_chipver, "A",
1035 "Return string with chip version.");
1036
1037 return (error);
1038 }
1039
1040 static void
ure_init(struct usb_ether * ue)1041 ure_init(struct usb_ether *ue)
1042 {
1043 struct ure_softc *sc = uether_getsc(ue);
1044 if_t ifp = uether_getifp(ue);
1045 uint16_t cpcr;
1046 uint32_t reg;
1047
1048 URE_LOCK_ASSERT(sc, MA_OWNED);
1049
1050 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1051 return;
1052
1053 /* Cancel pending I/O. */
1054 ure_stop(ue);
1055
1056 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1057 ure_rtl8153b_nic_reset(sc);
1058 else
1059 ure_reset(sc);
1060
1061 /* Set MAC address. */
1062 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1063 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
1064 if_getlladdr(ifp), 8);
1065 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1066
1067 /* Set RX EARLY timeout and size */
1068 if (sc->sc_flags & URE_FLAG_8153) {
1069 switch (usbd_get_speed(sc->sc_ue.ue_udev)) {
1070 case USB_SPEED_SUPER:
1071 reg = URE_COALESCE_SUPER / 8;
1072 break;
1073 case USB_SPEED_HIGH:
1074 reg = URE_COALESCE_HIGH / 8;
1075 break;
1076 default:
1077 reg = URE_COALESCE_SLOW / 8;
1078 break;
1079 }
1080 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg);
1081 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1082 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1083 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4);
1084 } else if (sc->sc_flags & URE_FLAG_8153B) {
1085 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158);
1086 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1087 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1088 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1089 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1090 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1091 URE_OWN_UPDATE | URE_OWN_CLEAR);
1092 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1093 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80);
1094 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1095 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1096 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1097 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1098 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1099 URE_OWN_UPDATE | URE_OWN_CLEAR);
1100 }
1101
1102 if (sc->sc_flags & URE_FLAG_8156B) {
1103 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1104 uether_pause(&sc->sc_ue, hz / 500);
1105 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1106 }
1107
1108 /* Reset the packet filter. */
1109 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1110 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1111
1112 /* Enable RX VLANs if enabled */
1113 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA);
1114 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1115 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n");
1116 cpcr |= URE_CPCR_RX_VLAN;
1117 } else {
1118 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n");
1119 cpcr &= ~URE_CPCR_RX_VLAN;
1120 }
1121 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr);
1122
1123 /* Enable transmit and receive. */
1124 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1125
1126 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1127
1128 /* Configure RX filters. */
1129 ure_rxfilter(ue);
1130
1131 usbd_xfer_set_stall(sc->sc_tx_xfer[0]);
1132
1133 /* Indicate we are up and running. */
1134 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1135
1136 /* Switch to selected media. */
1137 ure_ifmedia_upd(ifp);
1138 }
1139
1140 static void
ure_tick(struct usb_ether * ue)1141 ure_tick(struct usb_ether *ue)
1142 {
1143 struct ure_softc *sc = uether_getsc(ue);
1144 if_t ifp = uether_getifp(ue);
1145 struct mii_data *mii;
1146
1147 URE_LOCK_ASSERT(sc, MA_OWNED);
1148
1149 (void)ifp;
1150 for (int i = 0; i < URE_MAX_RX; i++)
1151 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1152 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i]));
1153
1154 for (int i = 0; i < URE_MAX_TX; i++)
1155 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1156 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i]));
1157
1158 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1159 ure_link_state(sc);
1160 } else {
1161 mii = GET_MII(sc);
1162 mii_tick(mii);
1163 if ((sc->sc_flags & URE_FLAG_LINK) == 0
1164 && mii->mii_media_status & IFM_ACTIVE &&
1165 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1166 sc->sc_flags |= URE_FLAG_LINK;
1167 sc->sc_rxstarted = 0;
1168 ure_start(ue);
1169 }
1170 }
1171 }
1172
1173 static u_int
ure_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1174 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1175 {
1176 uint32_t h, *hashes = arg;
1177
1178 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
1179 if (h < 32)
1180 hashes[0] |= (1 << h);
1181 else
1182 hashes[1] |= (1 << (h - 32));
1183 return (1);
1184 }
1185
1186 /*
1187 * Program the 64-bit multicast hash filter.
1188 */
1189 static void
ure_rxfilter(struct usb_ether * ue)1190 ure_rxfilter(struct usb_ether *ue)
1191 {
1192 struct ure_softc *sc = uether_getsc(ue);
1193 if_t ifp = uether_getifp(ue);
1194 uint32_t rxmode;
1195 uint32_t h, hashes[2] = { 0, 0 };
1196
1197 URE_LOCK_ASSERT(sc, MA_OWNED);
1198
1199 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
1200 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM);
1201 rxmode |= URE_RCR_APM; /* accept physical match packets */
1202 rxmode |= URE_RCR_AB; /* always accept broadcasts */
1203 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
1204 if (if_getflags(ifp) & IFF_PROMISC)
1205 rxmode |= URE_RCR_AAP;
1206 rxmode |= URE_RCR_AM;
1207 hashes[0] = hashes[1] = 0xffffffff;
1208 goto done;
1209 }
1210
1211 /* calculate multicast masks */
1212 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes);
1213
1214 h = bswap32(hashes[0]);
1215 hashes[0] = bswap32(hashes[1]);
1216 hashes[1] = h;
1217 rxmode |= URE_RCR_AM; /* accept multicast packets */
1218
1219 done:
1220 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n",
1221 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1222 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
1223 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
1224 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
1225 }
1226
1227 static void
ure_start(struct usb_ether * ue)1228 ure_start(struct usb_ether *ue)
1229 {
1230 struct ure_softc *sc = uether_getsc(ue);
1231 unsigned i;
1232
1233 URE_LOCK_ASSERT(sc, MA_OWNED);
1234
1235 if (!sc->sc_rxstarted) {
1236 sc->sc_rxstarted = 1;
1237 for (i = 0; i != URE_MAX_RX; i++)
1238 usbd_transfer_start(sc->sc_rx_xfer[i]);
1239 }
1240
1241 for (i = 0; i != URE_MAX_TX; i++)
1242 usbd_transfer_start(sc->sc_tx_xfer[i]);
1243 }
1244
1245 static void
ure_reset(struct ure_softc * sc)1246 ure_reset(struct ure_softc *sc)
1247 {
1248 int i;
1249
1250 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
1251
1252 for (i = 0; i < URE_TIMEOUT; i++) {
1253 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
1254 URE_CR_RST))
1255 break;
1256 uether_pause(&sc->sc_ue, hz / 100);
1257 }
1258 if (i == URE_TIMEOUT)
1259 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
1260 }
1261
1262 /*
1263 * Set media options.
1264 */
1265 static int
ure_ifmedia_upd(if_t ifp)1266 ure_ifmedia_upd(if_t ifp)
1267 {
1268 struct ure_softc *sc = if_getsoftc(ifp);
1269 struct ifmedia *ifm;
1270 struct mii_data *mii;
1271 struct mii_softc *miisc;
1272 int gig;
1273 int reg;
1274 int anar;
1275 int locked;
1276 int error;
1277
1278 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1279 ifm = &sc->sc_ifmedia;
1280 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1281 return (EINVAL);
1282
1283 locked = mtx_owned(&sc->sc_mtx);
1284 if (!locked)
1285 URE_LOCK(sc);
1286 reg = ure_ocp_reg_read(sc, 0xa5d4);
1287 reg &= ~URE_ADV_2500TFDX;
1288
1289 anar = gig = 0;
1290 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1291 case IFM_AUTO:
1292 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1293 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1294 reg |= URE_ADV_2500TFDX;
1295 break;
1296 case IFM_2500_T:
1297 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1298 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1299 reg |= URE_ADV_2500TFDX;
1300 if_setbaudrate(ifp, IF_Mbps(2500));
1301 break;
1302 case IFM_1000_T:
1303 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1304 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1305 if_setbaudrate(ifp, IF_Gbps(1));
1306 break;
1307 case IFM_100_TX:
1308 anar |= ANAR_TX | ANAR_TX_FD;
1309 if_setbaudrate(ifp, IF_Mbps(100));
1310 break;
1311 case IFM_10_T:
1312 anar |= ANAR_10 | ANAR_10_FD;
1313 if_setbaudrate(ifp, IF_Mbps(10));
1314 break;
1315 default:
1316 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n");
1317 if (!locked)
1318 URE_UNLOCK(sc);
1319 return (EINVAL);
1320 }
1321
1322 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2,
1323 anar | ANAR_PAUSE_ASYM | ANAR_FC);
1324 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
1325 ure_ocp_reg_write(sc, 0xa5d4, reg);
1326 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR,
1327 BMCR_AUTOEN | BMCR_STARTNEG);
1328 if (!locked)
1329 URE_UNLOCK(sc);
1330 return (0);
1331 }
1332
1333 mii = GET_MII(sc);
1334
1335 URE_LOCK_ASSERT(sc, MA_OWNED);
1336 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1337 PHY_RESET(miisc);
1338 error = mii_mediachg(mii);
1339 return (error);
1340 }
1341
1342 /*
1343 * Report current media status.
1344 */
1345 static void
ure_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1346 ure_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1347 {
1348 struct ure_softc *sc;
1349 struct mii_data *mii;
1350 uint16_t status;
1351
1352 sc = if_getsoftc(ifp);
1353 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1354 URE_LOCK(sc);
1355 ifmr->ifm_status = IFM_AVALID;
1356 if (ure_get_link_status(sc)) {
1357 ifmr->ifm_status |= IFM_ACTIVE;
1358 status = ure_read_2(sc, URE_PLA_PHYSTATUS,
1359 URE_MCU_TYPE_PLA);
1360 if ((status & URE_PHYSTATUS_FDX) ||
1361 (status & URE_PHYSTATUS_2500MBPS))
1362 ifmr->ifm_active |= IFM_FDX;
1363 else
1364 ifmr->ifm_active |= IFM_HDX;
1365 if (status & URE_PHYSTATUS_10MBPS)
1366 ifmr->ifm_active |= IFM_10_T;
1367 else if (status & URE_PHYSTATUS_100MBPS)
1368 ifmr->ifm_active |= IFM_100_TX;
1369 else if (status & URE_PHYSTATUS_1000MBPS)
1370 ifmr->ifm_active |= IFM_1000_T;
1371 else if (status & URE_PHYSTATUS_2500MBPS)
1372 ifmr->ifm_active |= IFM_2500_T;
1373 }
1374 URE_UNLOCK(sc);
1375 return;
1376 }
1377
1378 mii = GET_MII(sc);
1379
1380 URE_LOCK(sc);
1381 mii_pollstat(mii);
1382 ifmr->ifm_active = mii->mii_media_active;
1383 ifmr->ifm_status = mii->mii_media_status;
1384 URE_UNLOCK(sc);
1385 }
1386
1387 static void
ure_add_media_types(struct ure_softc * sc)1388 ure_add_media_types(struct ure_softc *sc)
1389 {
1390 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
1391 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1392 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
1393 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1394 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1395 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
1396 }
1397
1398 static void
ure_link_state(struct ure_softc * sc)1399 ure_link_state(struct ure_softc *sc)
1400 {
1401 if_t ifp = uether_getifp(&sc->sc_ue);
1402
1403 if (ure_get_link_status(sc)) {
1404 if (if_getlinkstate(ifp) != LINK_STATE_UP) {
1405 if_link_state_change(ifp, LINK_STATE_UP);
1406 /* Enable transmit and receive. */
1407 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1408
1409 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1410 URE_PHYSTATUS_2500MBPS)
1411 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1412 else
1413 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1414 }
1415 } else {
1416 if (if_getlinkstate(ifp) != LINK_STATE_DOWN) {
1417 if_link_state_change(ifp, LINK_STATE_DOWN);
1418 }
1419 }
1420 }
1421
1422 static int
ure_get_link_status(struct ure_softc * sc)1423 ure_get_link_status(struct ure_softc *sc)
1424 {
1425 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1426 URE_PHYSTATUS_LINK) {
1427 sc->sc_flags |= URE_FLAG_LINK;
1428 return (1);
1429 } else {
1430 sc->sc_flags &= ~URE_FLAG_LINK;
1431 return (0);
1432 }
1433 }
1434
1435 static int
ure_ioctl(if_t ifp,u_long cmd,caddr_t data)1436 ure_ioctl(if_t ifp, u_long cmd, caddr_t data)
1437 {
1438 struct usb_ether *ue = if_getsoftc(ifp);
1439 struct ure_softc *sc;
1440 struct ifreq *ifr;
1441 int error, mask, reinit;
1442
1443 sc = uether_getsc(ue);
1444 ifr = (struct ifreq *)data;
1445 error = 0;
1446 reinit = 0;
1447 switch (cmd) {
1448 case SIOCSIFCAP:
1449 URE_LOCK(sc);
1450 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1451 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1452 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1453 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1454 reinit++;
1455 }
1456 if ((mask & IFCAP_TXCSUM) != 0 &&
1457 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1458 if_togglecapenable(ifp, IFCAP_TXCSUM);
1459 }
1460 if ((mask & IFCAP_RXCSUM) != 0 &&
1461 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1462 if_togglecapenable(ifp, IFCAP_RXCSUM);
1463 }
1464 if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&
1465 (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) {
1466 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
1467 }
1468 if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&
1469 (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) {
1470 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
1471 }
1472 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1473 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1474 else
1475 reinit = 0;
1476 URE_UNLOCK(sc);
1477 if (reinit > 0)
1478 uether_init(ue);
1479 break;
1480
1481 case SIOCSIFMTU:
1482 /*
1483 * in testing large MTUs "crashes" the device, it
1484 * leaves the device w/ a broken state where link
1485 * is in a bad state.
1486 */
1487 if (ifr->ifr_mtu < ETHERMIN ||
1488 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN -
1489 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) {
1490 error = EINVAL;
1491 break;
1492 }
1493 URE_LOCK(sc);
1494 if (if_getmtu(ifp) != ifr->ifr_mtu)
1495 if_setmtu(ifp, ifr->ifr_mtu);
1496 URE_UNLOCK(sc);
1497 break;
1498
1499 case SIOCGIFMEDIA:
1500 case SIOCSIFMEDIA:
1501 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1502 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
1503 else
1504 error = uether_ioctl(ifp, cmd, data);
1505 break;
1506
1507 default:
1508 error = uether_ioctl(ifp, cmd, data);
1509 break;
1510 }
1511
1512 return (error);
1513 }
1514
1515 static void
ure_rtl8152_init(struct ure_softc * sc)1516 ure_rtl8152_init(struct ure_softc *sc)
1517 {
1518 uint32_t pwrctrl;
1519
1520 ure_enable_aldps(sc, false);
1521
1522 if (sc->sc_chip & URE_CHIP_VER_4C00) {
1523 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1524 }
1525
1526 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT);
1527
1528 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE);
1529
1530 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
1531
1532 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
1533 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
1534 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
1535 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
1536 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
1537 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
1538 URE_SPDWN_LINKCHG_MSK);
1539
1540 /* Enable Rx aggregation. */
1541 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1542
1543 ure_enable_aldps(sc, false);
1544
1545 ure_rtl8152_nic_reset(sc);
1546
1547 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
1548 URE_TX_AGG_MAX_THRESHOLD);
1549 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
1550 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
1551 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
1552 }
1553
1554 static void
ure_rtl8153_init(struct ure_softc * sc)1555 ure_rtl8153_init(struct ure_softc *sc)
1556 {
1557 uint16_t val;
1558 uint8_t u1u2[8];
1559 int i;
1560
1561 ure_enable_aldps(sc, false);
1562
1563 memset(u1u2, 0x00, sizeof(u1u2));
1564 ure_write_mem(sc, URE_USB_TOLERANCE,
1565 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1566
1567 for (i = 0; i < URE_TIMEOUT; i++) {
1568 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1569 URE_AUTOLOAD_DONE)
1570 break;
1571 uether_pause(&sc->sc_ue, hz / 100);
1572 }
1573 if (i == URE_TIMEOUT)
1574 device_printf(sc->sc_ue.ue_dev,
1575 "timeout waiting for chip autoload\n");
1576
1577 for (i = 0; i < URE_TIMEOUT; i++) {
1578 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1579 URE_PHY_STAT_MASK;
1580 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1581 break;
1582 uether_pause(&sc->sc_ue, hz / 100);
1583 }
1584 if (i == URE_TIMEOUT)
1585 device_printf(sc->sc_ue.ue_dev,
1586 "timeout waiting for phy to stabilize\n");
1587
1588 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1589
1590 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1591 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1592 val &= ~URE_PWD_DN_SCALE_MASK;
1593 val |= URE_PWD_DN_SCALE(96);
1594 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1595
1596 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1597 } else if (sc->sc_chip & URE_CHIP_VER_5C20)
1598 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS);
1599
1600 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1601 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1602 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1603 0)
1604 val &= ~URE_DYNAMIC_BURST;
1605 else
1606 val |= URE_DYNAMIC_BURST;
1607 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1608 }
1609
1610 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC);
1611
1612 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN);
1613
1614 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1615
1616 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1617 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1618 val = URE_LPM_TIMER_500MS;
1619 else
1620 val = URE_LPM_TIMER_500US;
1621 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1622 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1623
1624 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1625 val &= ~URE_SEN_VAL_MASK;
1626 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1627 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1628
1629 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1630
1631 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN);
1632
1633 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1634
1635 memset(u1u2, 0xff, sizeof(u1u2));
1636 ure_write_mem(sc, URE_USB_TOLERANCE,
1637 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1638
1639 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1640 URE_ALDPS_SPDWN_RATIO);
1641 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1642 URE_EEE_SPDWN_RATIO);
1643 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1644 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1645 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1646 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1647 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1648 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1649 URE_EEE_SPDWN_EN);
1650
1651 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1652 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1653 val |= URE_U2P3_ENABLE;
1654 else
1655 val &= ~URE_U2P3_ENABLE;
1656 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1657
1658 memset(u1u2, 0x00, sizeof(u1u2));
1659 ure_write_mem(sc, URE_USB_TOLERANCE,
1660 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1661
1662 ure_enable_aldps(sc, false);
1663
1664 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1665 URE_CHIP_VER_5C20)) {
1666 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1667 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1668 }
1669 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1670 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1671 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1672 ~URE_CTAP_SHORT_EN);
1673 }
1674 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1675 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1676 URE_EEE_CLKDIV_EN);
1677 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1678 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1679 URE_EN_10M_BGOFF);
1680 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1681 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1682 URE_EN_10M_PLLOFF);
1683 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13);
1684 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH);
1685
1686 /* Enable LPF corner auto tune. */
1687 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f);
1688
1689 /* Adjust 10M amplitude. */
1690 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af);
1691 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208);
1692
1693 ure_rtl8152_nic_reset(sc);
1694
1695 /* Enable Rx aggregation. */
1696 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1697
1698 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1699 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1700 val |= URE_U2P3_ENABLE;
1701 else
1702 val &= ~URE_U2P3_ENABLE;
1703 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1704
1705 memset(u1u2, 0xff, sizeof(u1u2));
1706 ure_write_mem(sc, URE_USB_TOLERANCE,
1707 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1708 }
1709
1710 static void
ure_rtl8153b_init(struct ure_softc * sc)1711 ure_rtl8153b_init(struct ure_softc *sc)
1712 {
1713 uint16_t val;
1714 int i;
1715
1716 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1717 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01);
1718 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0);
1719 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020);
1720 }
1721
1722 if (sc->sc_flags & URE_FLAG_8156B) {
1723 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08);
1724 }
1725
1726 ure_enable_aldps(sc, false);
1727
1728 /* Disable U1U2 */
1729 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1730
1731 /* Wait loading flash */
1732 if (sc->sc_chip == URE_CHIP_VER_7410) {
1733 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) &&
1734 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) {
1735 for (i=0; i < 100; i++) {
1736 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004)
1737 break;
1738 uether_pause(&sc->sc_ue, hz / 1000);
1739 }
1740 }
1741 }
1742
1743 for (i = 0; i < URE_TIMEOUT; i++) {
1744 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1745 URE_AUTOLOAD_DONE)
1746 break;
1747 uether_pause(&sc->sc_ue, hz / 100);
1748 }
1749 if (i == URE_TIMEOUT)
1750 device_printf(sc->sc_ue.ue_dev,
1751 "timeout waiting for chip autoload\n");
1752
1753 val = ure_phy_status(sc, 0);
1754 if ((val == URE_PHY_STAT_EXT_INIT) &
1755 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) {
1756 ure_ocp_reg_write(sc, 0xa468,
1757 ure_ocp_reg_read(sc, 0xa468) & ~0x0a);
1758 if (sc->sc_flags & URE_FLAG_8156B)
1759 ure_ocp_reg_write(sc, 0xa466,
1760 ure_ocp_reg_read(sc, 0xa466) & ~0x01);
1761 }
1762
1763 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR);
1764 if (val & BMCR_PDOWN) {
1765 val &= ~BMCR_PDOWN;
1766 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val);
1767 }
1768
1769 ure_phy_status(sc, URE_PHY_STAT_LAN_ON);
1770
1771 /* Disable U2P3 */
1772 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1773
1774 /* MSC timer, 32760 ms. */
1775 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff);
1776
1777 /* U1/U2/L1 idle timer, 500 us. */
1778 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500);
1779
1780 /* Disable power cut */
1781 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN);
1782 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1783
1784 /* Disable ups */
1785 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE);
1786 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01);
1787
1788 /* Disable queue wake */
1789 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3);
1790 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT);
1791 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG);
1792
1793 /* Disable runtime suspend */
1794 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1795 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN);
1796 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1797
1798 /* Enable U1U2 */
1799 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1800 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1801
1802 if (sc->sc_flags & URE_FLAG_8156B) {
1803 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800);
1804 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001);
1805
1806 /* enable fc timer and set timer to 600 ms. */
1807 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8));
1808
1809 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) {
1810 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
1811 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100;
1812 val &= ~0x08;
1813 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val);
1814 }
1815
1816 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1817 }
1818
1819 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1820 if (ure_get_link_status(sc))
1821 val |= URE_CUR_LINK_OK;
1822 else
1823 val &= ~URE_CUR_LINK_OK;
1824 val |= URE_POLL_LINK_CHG;
1825 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val);
1826
1827 /* MAC clock speed down */
1828 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1829 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);
1830 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA);
1831 val &= ~0xff;
1832 val |= URE_MAC_CLK_SPDWN_EN | 0x03;
1833 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val);
1834 } else {
1835 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN);
1836 }
1837 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1838
1839 /* Enable Rx aggregation. */
1840 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1841
1842 if (sc->sc_flags & URE_FLAG_8156)
1843 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02);
1844
1845 /* Reset tally */
1846 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET);
1847 }
1848
1849 static void
ure_rtl8153b_nic_reset(struct ure_softc * sc)1850 ure_rtl8153b_nic_reset(struct ure_softc *sc)
1851 {
1852 if_t ifp = uether_getifp(&sc->sc_ue);
1853 uint16_t val;
1854 int i;
1855
1856 /* Disable U1U2 */
1857 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1858
1859 /* Disable U2P3 */
1860 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1861
1862 ure_enable_aldps(sc, false);
1863
1864 /* Enable rxdy_gated */
1865 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1866
1867 /* Disable teredo */
1868 ure_disable_teredo(sc);
1869
1870 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1871 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
1872
1873 ure_reset(sc);
1874
1875 /* Reset BMU */
1876 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1877 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1878
1879 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
1880 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
1881 if (sc->sc_flags & URE_FLAG_8153B) {
1882 for (i = 0; i < URE_TIMEOUT; i++) {
1883 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1884 URE_LINK_LIST_READY)
1885 break;
1886 uether_pause(&sc->sc_ue, hz / 100);
1887 }
1888 if (i == URE_TIMEOUT)
1889 device_printf(sc->sc_ue.ue_dev,
1890 "timeout waiting for OOB control\n");
1891
1892 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
1893 for (i = 0; i < URE_TIMEOUT; i++) {
1894 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1895 URE_LINK_LIST_READY)
1896 break;
1897 uether_pause(&sc->sc_ue, hz / 100);
1898 }
1899 if (i == URE_TIMEOUT)
1900 device_printf(sc->sc_ue.ue_dev,
1901 "timeout waiting for OOB control\n");
1902 }
1903
1904 /* Configure rxvlan */
1905 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA);
1906 val &= ~0x00c0;
1907 if (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)
1908 val |= 0x00c0;
1909 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val);
1910
1911 val = if_getmtu(ifp);
1912 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val));
1913 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO);
1914
1915 if (sc->sc_flags & URE_FLAG_8153B) {
1916 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
1917 ure_reset(sc);
1918 }
1919
1920 /* Configure fc parameter */
1921 if (sc->sc_flags & URE_FLAG_8156) {
1922 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400);
1923 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800);
1924 } else if (sc->sc_flags & URE_FLAG_8156B) {
1925 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200);
1926 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400);
1927 }
1928
1929 /* Configure Rx FIFO threshold. */
1930 if (sc->sc_flags & URE_FLAG_8153B) {
1931 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL);
1932 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL);
1933 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL);
1934 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B);
1935 } else {
1936 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA,
1937 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08);
1938 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400);
1939 }
1940
1941 /* Configure Tx FIFO threshold. */
1942 if (sc->sc_flags & URE_FLAG_8153B) {
1943 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
1944 } else if (sc->sc_flags & URE_FLAG_8156) {
1945 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
1946 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002);
1947 } else if (sc->sc_flags & URE_FLAG_8156B) {
1948 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008);
1949 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA,
1950 (URE_FRAMELEN(val) + 0x100) / 16 );
1951 }
1952
1953 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1954
1955 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1956 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300);
1957
1958 ure_enable_aldps(sc, true);
1959
1960 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1961 /* Enable U2P3 */
1962 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1963 }
1964
1965 /* Enable U1U2 */
1966 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1967 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1968 }
1969
1970 static void
ure_stop(struct usb_ether * ue)1971 ure_stop(struct usb_ether *ue)
1972 {
1973 struct ure_softc *sc = uether_getsc(ue);
1974 if_t ifp = uether_getifp(ue);
1975
1976 URE_LOCK_ASSERT(sc, MA_OWNED);
1977
1978 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1979 sc->sc_flags &= ~URE_FLAG_LINK;
1980 sc->sc_rxstarted = 0;
1981
1982 /*
1983 * stop all the transfers, if not already stopped:
1984 */
1985 for (int i = 0; i < URE_MAX_RX; i++)
1986 usbd_transfer_stop(sc->sc_rx_xfer[i]);
1987 for (int i = 0; i < URE_MAX_TX; i++)
1988 usbd_transfer_stop(sc->sc_tx_xfer[i]);
1989 }
1990
1991 static void
ure_disable_teredo(struct ure_softc * sc)1992 ure_disable_teredo(struct ure_softc *sc)
1993 {
1994
1995 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1996 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);
1997 else {
1998 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1999 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
2000 }
2001 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE);
2002 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
2003 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
2004 }
2005
2006 static void
ure_enable_aldps(struct ure_softc * sc,bool enable)2007 ure_enable_aldps(struct ure_softc *sc, bool enable)
2008 {
2009 int i;
2010
2011 if (enable) {
2012 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
2013 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS);
2014 } else {
2015 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
2016 URE_DIS_SDSAVE);
2017 for (i = 0; i < 20; i++) {
2018 uether_pause(&sc->sc_ue, hz / 1000);
2019 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)
2020 break;
2021 }
2022 }
2023 }
2024
2025 static uint16_t
ure_phy_status(struct ure_softc * sc,uint16_t desired)2026 ure_phy_status(struct ure_softc *sc, uint16_t desired)
2027 {
2028 uint16_t val;
2029 int i;
2030
2031 for (i = 0; i < URE_TIMEOUT; i++) {
2032 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
2033 URE_PHY_STAT_MASK;
2034 if (desired) {
2035 if (val == desired)
2036 break;
2037 } else {
2038 if (val == URE_PHY_STAT_LAN_ON ||
2039 val == URE_PHY_STAT_PWRDN ||
2040 val == URE_PHY_STAT_EXT_INIT)
2041 break;
2042 }
2043 uether_pause(&sc->sc_ue, hz / 100);
2044 }
2045 if (i == URE_TIMEOUT)
2046 device_printf(sc->sc_ue.ue_dev,
2047 "timeout waiting for phy to stabilize\n");
2048
2049 return (val);
2050 }
2051
2052 static void
ure_rtl8152_nic_reset(struct ure_softc * sc)2053 ure_rtl8152_nic_reset(struct ure_softc *sc)
2054 {
2055 uint32_t rx_fifo1, rx_fifo2;
2056 int i;
2057
2058 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
2059
2060 ure_disable_teredo(sc);
2061
2062 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
2063 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
2064
2065 ure_reset(sc);
2066
2067 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
2068
2069 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
2070
2071 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
2072 for (i = 0; i < URE_TIMEOUT; i++) {
2073 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2074 URE_LINK_LIST_READY)
2075 break;
2076 uether_pause(&sc->sc_ue, hz / 100);
2077 }
2078 if (i == URE_TIMEOUT)
2079 device_printf(sc->sc_ue.ue_dev,
2080 "timeout waiting for OOB control\n");
2081 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
2082 for (i = 0; i < URE_TIMEOUT; i++) {
2083 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2084 URE_LINK_LIST_READY)
2085 break;
2086 uether_pause(&sc->sc_ue, hz / 100);
2087 }
2088 if (i == URE_TIMEOUT)
2089 device_printf(sc->sc_ue.ue_dev,
2090 "timeout waiting for OOB control\n");
2091
2092 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN);
2093
2094 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
2095
2096 /* Configure Rx FIFO threshold. */
2097 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
2098 URE_RXFIFO_THR1_NORMAL);
2099 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
2100 rx_fifo1 = URE_RXFIFO_THR2_FULL;
2101 rx_fifo2 = URE_RXFIFO_THR3_FULL;
2102 } else {
2103 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
2104 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
2105 }
2106 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
2107 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
2108
2109 /* Configure Tx FIFO threshold. */
2110 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
2111 URE_TXFIFO_THR_NORMAL);
2112 }
2113
2114 /*
2115 * Update mbuf for rx checksum from hardware
2116 */
2117 static void
ure_rxcsum(int capenb,struct ure_rxpkt * rp,struct mbuf * m)2118 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m)
2119 {
2120 int flags;
2121 uint32_t csum, misc;
2122 int tcp, udp;
2123
2124 m->m_pkthdr.csum_flags = 0;
2125
2126 if (!(capenb & IFCAP_RXCSUM))
2127 return;
2128
2129 csum = le32toh(rp->ure_csum);
2130 misc = le32toh(rp->ure_misc);
2131
2132 tcp = udp = 0;
2133
2134 flags = 0;
2135 if (csum & URE_RXPKT_IPV4_CS)
2136 flags |= CSUM_IP_CHECKED;
2137 else if (csum & URE_RXPKT_IPV6_CS)
2138 flags = 0;
2139
2140 tcp = rp->ure_csum & URE_RXPKT_TCP_CS;
2141 udp = rp->ure_csum & URE_RXPKT_UDP_CS;
2142
2143 if (__predict_true((flags & CSUM_IP_CHECKED) &&
2144 !(misc & URE_RXPKT_IP_F))) {
2145 flags |= CSUM_IP_VALID;
2146 }
2147 if (__predict_true(
2148 (tcp && !(misc & URE_RXPKT_TCP_F)) ||
2149 (udp && !(misc & URE_RXPKT_UDP_F)))) {
2150 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2151 m->m_pkthdr.csum_data = 0xFFFF;
2152 }
2153
2154 m->m_pkthdr.csum_flags = flags;
2155 }
2156
2157 /*
2158 * If the L4 checksum offset is larger than 0x7ff (2047), return failure.
2159 * We currently restrict MTU such that it can't happen, and even if we
2160 * did have a large enough MTU, only a very specially crafted IPv6 packet
2161 * with MANY headers could possibly come close.
2162 *
2163 * Returns 0 for success, and 1 if the packet cannot be checksummed and
2164 * should be dropped.
2165 */
2166 static int
ure_txcsum(struct mbuf * m,int caps,uint32_t * regout)2167 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout)
2168 {
2169 struct ip ip;
2170 struct ether_header *eh;
2171 int flags;
2172 uint32_t data;
2173 uint32_t reg;
2174 int l3off, l4off;
2175 uint16_t type;
2176
2177 *regout = 0;
2178 flags = m->m_pkthdr.csum_flags;
2179 if (flags == 0)
2180 return (0);
2181
2182 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
2183 eh = mtod(m, struct ether_header *);
2184 type = eh->ether_type;
2185 } else
2186 m_copydata(m, offsetof(struct ether_header, ether_type),
2187 sizeof(type), (caddr_t)&type);
2188
2189 switch (type = htons(type)) {
2190 case ETHERTYPE_IP:
2191 case ETHERTYPE_IPV6:
2192 l3off = ETHER_HDR_LEN;
2193 break;
2194 case ETHERTYPE_VLAN:
2195 /* XXX - what about QinQ? */
2196 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2197 break;
2198 default:
2199 return (0);
2200 }
2201
2202 reg = 0;
2203
2204 if (flags & CSUM_IP)
2205 reg |= URE_TXPKT_IPV4_CS;
2206
2207 data = m->m_pkthdr.csum_data;
2208 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) {
2209 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip);
2210 l4off = l3off + (ip.ip_hl << 2) + data;
2211 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2212 return (1);
2213
2214 reg |= URE_TXPKT_IPV4_CS;
2215 if (flags & CSUM_IP_TCP)
2216 reg |= URE_TXPKT_TCP_CS;
2217 else if (flags & CSUM_IP_UDP)
2218 reg |= URE_TXPKT_UDP_CS;
2219 reg |= l4off << URE_L4_OFFSET_SHIFT;
2220 }
2221 #ifdef INET6
2222 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) {
2223 l4off = l3off + data;
2224 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2225 return (1);
2226
2227 reg |= URE_TXPKT_IPV6_CS;
2228 if (flags & CSUM_IP6_TCP)
2229 reg |= URE_TXPKT_TCP_CS;
2230 else if (flags & CSUM_IP6_UDP)
2231 reg |= URE_TXPKT_UDP_CS;
2232 reg |= l4off << URE_L4_OFFSET_SHIFT;
2233 }
2234 #endif
2235 *regout = reg;
2236 return 0;
2237 }
2238