1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "link_hwss_dpia.h"
26 #include "core_types.h"
27 #include "link_hwss_dio.h"
28 #include "link_enc_cfg.h"
29
30 #define DC_LOGGER \
31 link->ctx->logger
32 #define DC_LOGGER_INIT(logger)
33
update_dpia_stream_allocation_table(struct dc_link * link,const struct link_resource * link_res,const struct link_mst_stream_allocation_table * table)34 static void update_dpia_stream_allocation_table(struct dc_link *link,
35 const struct link_resource *link_res,
36 const struct link_mst_stream_allocation_table *table)
37 {
38 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
39 static enum dc_status status;
40 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
41 int i;
42 DC_LOGGER_INIT(link->ctx->logger);
43
44 for (i = 0; i < table->stream_count; i++)
45 mst_alloc_slots += table->stream_allocations[i].slot_count;
46
47 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
48 mst_alloc_slots, &prev_mst_slots_in_use);
49 ASSERT(status == DC_OK);
50 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
51 status, mst_alloc_slots, prev_mst_slots_in_use);
52
53 if (link_enc)
54 link_enc->funcs->update_mst_stream_allocation_table(link_enc, table);
55 }
56
set_dio_dpia_link_test_pattern(struct dc_link * link,const struct link_resource * link_res,struct encoder_set_dp_phy_pattern_param * tp_params)57 static void set_dio_dpia_link_test_pattern(struct dc_link *link,
58 const struct link_resource *link_res,
59 struct encoder_set_dp_phy_pattern_param *tp_params)
60 {
61 if (tp_params->dp_phy_pattern != DP_TEST_PATTERN_VIDEO_MODE)
62 return;
63
64 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
65
66 if (!link_enc)
67 return;
68
69 link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params);
70 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
71 }
72
set_dio_dpia_lane_settings(struct dc_link * link,const struct link_resource * link_res,const struct dc_link_settings * link_settings,const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])73 static void set_dio_dpia_lane_settings(struct dc_link *link,
74 const struct link_resource *link_res,
75 const struct dc_link_settings *link_settings,
76 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
77 {
78 }
79
enable_dpia_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal,enum clock_source_id clock_source,const struct dc_link_settings * link_settings)80 static void enable_dpia_link_output(struct dc_link *link,
81 const struct link_resource *link_res,
82 enum signal_type signal,
83 enum clock_source_id clock_source,
84 const struct dc_link_settings *link_settings)
85 {
86 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
87
88 if (link_enc != NULL) {
89 if (link->dc->config.enable_dpia_pre_training && link_enc->funcs->enable_dpia_output) {
90 uint8_t fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);
91 uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;
92
93 link_enc->funcs->enable_dpia_output(
94 link_enc,
95 link_settings,
96 link->ddc_hw_inst,
97 digmode,
98 fec_rdy);
99 } else {
100 if (dc_is_dp_sst_signal(signal))
101 link_enc->funcs->enable_dp_output(
102 link_enc,
103 link_settings,
104 clock_source);
105 else
106 link_enc->funcs->enable_dp_mst_output(
107 link_enc,
108 link_settings,
109 clock_source);
110 }
111
112 }
113
114 link->dc->link_srv->dp_trace_source_sequence(link,
115 DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
116 }
117
disable_dpia_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)118 static void disable_dpia_link_output(struct dc_link *link,
119 const struct link_resource *link_res,
120 enum signal_type signal)
121 {
122 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
123
124 if (link_enc != NULL) {
125 if (link->dc->config.enable_dpia_pre_training && link_enc->funcs->disable_dpia_output) {
126 uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;
127
128 link_enc->funcs->disable_dpia_output(link_enc, link->ddc_hw_inst, digmode);
129 } else
130 link_enc->funcs->disable_output(link_enc, signal);
131 }
132
133 link->dc->link_srv->dp_trace_source_sequence(link,
134 DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
135 }
136
137 static const struct link_hwss dpia_link_hwss = {
138 .setup_stream_encoder = setup_dio_stream_encoder,
139 .reset_stream_encoder = reset_dio_stream_encoder,
140 .setup_stream_attribute = setup_dio_stream_attribute,
141 .disable_link_output = disable_dpia_link_output,
142 .setup_audio_output = setup_dio_audio_output,
143 .enable_audio_packet = enable_dio_audio_packet,
144 .disable_audio_packet = disable_dio_audio_packet,
145 .ext = {
146 .set_throttled_vcp_size = set_dio_throttled_vcp_size,
147 .enable_dp_link_output = enable_dpia_link_output,
148 .set_dp_link_test_pattern = set_dio_dpia_link_test_pattern,
149 .set_dp_lane_settings = set_dio_dpia_lane_settings,
150 .update_stream_allocation_table = update_dpia_stream_allocation_table,
151 },
152 };
153
can_use_dpia_link_hwss(const struct dc_link * link,const struct link_resource * link_res)154 bool can_use_dpia_link_hwss(const struct dc_link *link,
155 const struct link_resource *link_res)
156 {
157 return link->is_dig_mapping_flexible &&
158 link->dc->res_pool->funcs->link_encs_assign;
159 }
160
get_dpia_link_hwss(void)161 const struct link_hwss *get_dpia_link_hwss(void)
162 {
163 return &dpia_link_hwss;
164 }
165