xref: /linux/drivers/clk/qcom/camcc-sc7180.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/err.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_clock.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 
15 #include <dt-bindings/clock/qcom,camcc-sc7180.h>
16 
17 #include "clk-alpha-pll.h"
18 #include "clk-branch.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
21 #include "common.h"
22 #include "gdsc.h"
23 #include "reset.h"
24 
25 enum {
26 	P_BI_TCXO,
27 	P_CAM_CC_PLL0_OUT_EVEN,
28 	P_CAM_CC_PLL1_OUT_EVEN,
29 	P_CAM_CC_PLL2_OUT_AUX,
30 	P_CAM_CC_PLL2_OUT_EARLY,
31 	P_CAM_CC_PLL3_OUT_MAIN,
32 };
33 
34 static const struct pll_vco agera_vco[] = {
35 	{ 600000000, 3300000000UL, 0 },
36 };
37 
38 static const struct pll_vco fabia_vco[] = {
39 	{ 249600000, 2000000000UL, 0 },
40 };
41 
42 /* 600MHz configuration */
43 static const struct alpha_pll_config cam_cc_pll0_config = {
44 	.l = 0x1f,
45 	.alpha = 0x4000,
46 	.config_ctl_val = 0x20485699,
47 	.config_ctl_hi_val = 0x00002067,
48 	.test_ctl_val = 0x40000000,
49 	.user_ctl_hi_val = 0x00004805,
50 	.user_ctl_val = 0x00000001,
51 };
52 
53 static struct clk_alpha_pll cam_cc_pll0 = {
54 	.offset = 0x0,
55 	.vco_table = fabia_vco,
56 	.num_vco = ARRAY_SIZE(fabia_vco),
57 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
58 	.clkr = {
59 		.hw.init = &(struct clk_init_data){
60 			.name = "cam_cc_pll0",
61 			.parent_data = &(const struct clk_parent_data){
62 				.fw_name = "bi_tcxo",
63 			},
64 			.num_parents = 1,
65 			.ops = &clk_alpha_pll_fabia_ops,
66 		},
67 	},
68 };
69 
70 /* 860MHz configuration */
71 static const struct alpha_pll_config cam_cc_pll1_config = {
72 	.l = 0x2a,
73 	.alpha = 0x1555,
74 	.config_ctl_val = 0x20485699,
75 	.config_ctl_hi_val = 0x00002067,
76 	.test_ctl_val = 0x40000000,
77 	.user_ctl_hi_val = 0x00004805,
78 };
79 
80 static struct clk_alpha_pll cam_cc_pll1 = {
81 	.offset = 0x1000,
82 	.vco_table = fabia_vco,
83 	.num_vco = ARRAY_SIZE(fabia_vco),
84 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
85 	.clkr = {
86 		.hw.init = &(struct clk_init_data){
87 			.name = "cam_cc_pll1",
88 			.parent_data = &(const struct clk_parent_data){
89 				.fw_name = "bi_tcxo",
90 			},
91 			.num_parents = 1,
92 			.ops = &clk_alpha_pll_fabia_ops,
93 		},
94 	},
95 };
96 
97 /* 1920MHz configuration */
98 static const struct alpha_pll_config cam_cc_pll2_config = {
99 	.l = 0x64,
100 	.config_ctl_val = 0x20000800,
101 	.config_ctl_hi_val = 0x400003D2,
102 	.test_ctl_val = 0x04000400,
103 	.test_ctl_hi_val = 0x00004000,
104 	.user_ctl_val = 0x0000030F,
105 };
106 
107 static struct clk_alpha_pll cam_cc_pll2 = {
108 	.offset = 0x2000,
109 	.vco_table = agera_vco,
110 	.num_vco = ARRAY_SIZE(agera_vco),
111 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
112 	.clkr = {
113 		.hw.init = &(struct clk_init_data){
114 			.name = "cam_cc_pll2",
115 			.parent_data = &(const struct clk_parent_data){
116 				.fw_name = "bi_tcxo",
117 			},
118 			.num_parents = 1,
119 			.ops = &clk_alpha_pll_agera_ops,
120 		},
121 	},
122 };
123 
124 static struct clk_fixed_factor cam_cc_pll2_out_early = {
125 	.mult = 1,
126 	.div = 2,
127 	.hw.init = &(struct clk_init_data){
128 		.name = "cam_cc_pll2_out_early",
129 		.parent_hws = (const struct clk_hw*[]){
130 			&cam_cc_pll2.clkr.hw,
131 		},
132 		.num_parents = 1,
133 		.ops = &clk_fixed_factor_ops,
134 	},
135 };
136 
137 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = {
138 	{ 0x3, 4 },
139 	{ }
140 };
141 
142 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
143 	.offset = 0x2000,
144 	.post_div_shift = 8,
145 	.post_div_table = post_div_table_cam_cc_pll2_out_aux,
146 	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux),
147 	.width = 2,
148 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
149 	.clkr.hw.init = &(struct clk_init_data){
150 		.name = "cam_cc_pll2_out_aux",
151 		.parent_hws = (const struct clk_hw*[]){
152 			&cam_cc_pll2.clkr.hw,
153 		},
154 		.num_parents = 1,
155 		.flags = CLK_SET_RATE_PARENT,
156 		.ops = &clk_alpha_pll_postdiv_ops,
157 	},
158 };
159 
160 /* 1080MHz configuration */
161 static const struct alpha_pll_config cam_cc_pll3_config = {
162 	.l = 0x38,
163 	.alpha = 0x4000,
164 	.config_ctl_val = 0x20485699,
165 	.config_ctl_hi_val = 0x00002067,
166 	.test_ctl_val = 0x40000000,
167 	.user_ctl_hi_val = 0x00004805,
168 };
169 
170 static struct clk_alpha_pll cam_cc_pll3 = {
171 	.offset = 0x3000,
172 	.vco_table = fabia_vco,
173 	.num_vco = ARRAY_SIZE(fabia_vco),
174 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
175 	.clkr = {
176 		.hw.init = &(struct clk_init_data){
177 			.name = "cam_cc_pll3",
178 			.parent_data = &(const struct clk_parent_data){
179 				.fw_name = "bi_tcxo",
180 			},
181 			.num_parents = 1,
182 			.ops = &clk_alpha_pll_fabia_ops,
183 		},
184 	},
185 };
186 
187 static const struct parent_map cam_cc_parent_map_0[] = {
188 	{ P_BI_TCXO, 0 },
189 	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
190 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
191 };
192 
193 static const struct clk_parent_data cam_cc_parent_data_0[] = {
194 	{ .fw_name = "bi_tcxo" },
195 	{ .hw = &cam_cc_pll1.clkr.hw },
196 	{ .hw = &cam_cc_pll0.clkr.hw },
197 };
198 
199 static const struct parent_map cam_cc_parent_map_1[] = {
200 	{ P_BI_TCXO, 0 },
201 	{ P_CAM_CC_PLL2_OUT_AUX, 1 },
202 };
203 
204 static const struct clk_parent_data cam_cc_parent_data_1[] = {
205 	{ .fw_name = "bi_tcxo" },
206 	{ .hw = &cam_cc_pll2_out_aux.clkr.hw },
207 };
208 
209 static const struct parent_map cam_cc_parent_map_2[] = {
210 	{ P_BI_TCXO, 0 },
211 	{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
212 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
213 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
214 };
215 
216 static const struct clk_parent_data cam_cc_parent_data_2[] = {
217 	{ .fw_name = "bi_tcxo" },
218 	{ .hw = &cam_cc_pll2_out_early.hw },
219 	{ .hw = &cam_cc_pll3.clkr.hw },
220 	{ .hw = &cam_cc_pll0.clkr.hw },
221 };
222 
223 static const struct parent_map cam_cc_parent_map_3[] = {
224 	{ P_BI_TCXO, 0 },
225 	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
226 	{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
227 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
228 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
229 };
230 
231 static const struct clk_parent_data cam_cc_parent_data_3[] = {
232 	{ .fw_name = "bi_tcxo" },
233 	{ .hw = &cam_cc_pll1.clkr.hw },
234 	{ .hw = &cam_cc_pll2_out_early.hw },
235 	{ .hw = &cam_cc_pll3.clkr.hw },
236 	{ .hw = &cam_cc_pll0.clkr.hw },
237 };
238 
239 static const struct parent_map cam_cc_parent_map_4[] = {
240 	{ P_BI_TCXO, 0 },
241 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
242 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
243 };
244 
245 static const struct clk_parent_data cam_cc_parent_data_4[] = {
246 	{ .fw_name = "bi_tcxo" },
247 	{ .hw = &cam_cc_pll3.clkr.hw },
248 	{ .hw = &cam_cc_pll0.clkr.hw },
249 };
250 
251 static const struct parent_map cam_cc_parent_map_5[] = {
252 	{ P_BI_TCXO, 0 },
253 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
254 };
255 
256 static const struct clk_parent_data cam_cc_parent_data_5[] = {
257 	{ .fw_name = "bi_tcxo" },
258 	{ .hw = &cam_cc_pll0.clkr.hw },
259 };
260 
261 static const struct parent_map cam_cc_parent_map_6[] = {
262 	{ P_BI_TCXO, 0 },
263 	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
264 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
265 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
266 };
267 
268 static const struct clk_parent_data cam_cc_parent_data_6[] = {
269 	{ .fw_name = "bi_tcxo" },
270 	{ .hw = &cam_cc_pll1.clkr.hw },
271 	{ .hw = &cam_cc_pll3.clkr.hw },
272 	{ .hw = &cam_cc_pll0.clkr.hw },
273 };
274 
275 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
276 	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
277 	F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
278 	F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
279 	F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
280 	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
281 	{ }
282 };
283 
284 static struct clk_rcg2 cam_cc_bps_clk_src = {
285 	.cmd_rcgr = 0x6010,
286 	.mnd_width = 0,
287 	.hid_width = 5,
288 	.parent_map = cam_cc_parent_map_2,
289 	.freq_tbl = ftbl_cam_cc_bps_clk_src,
290 	.clkr.hw.init = &(struct clk_init_data){
291 		.name = "cam_cc_bps_clk_src",
292 		.parent_data = cam_cc_parent_data_2,
293 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
294 		.ops = &clk_rcg2_shared_ops,
295 	},
296 };
297 
298 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
299 	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
300 	F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
301 	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
302 	{ }
303 };
304 
305 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
306 	.cmd_rcgr = 0xb0d8,
307 	.mnd_width = 8,
308 	.hid_width = 5,
309 	.parent_map = cam_cc_parent_map_5,
310 	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
311 	.clkr.hw.init = &(struct clk_init_data){
312 		.name = "cam_cc_cci_0_clk_src",
313 		.parent_data = cam_cc_parent_data_5,
314 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
315 		.ops = &clk_rcg2_shared_ops,
316 	},
317 };
318 
319 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
320 	.cmd_rcgr = 0xb14c,
321 	.mnd_width = 8,
322 	.hid_width = 5,
323 	.parent_map = cam_cc_parent_map_5,
324 	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
325 	.clkr.hw.init = &(struct clk_init_data){
326 		.name = "cam_cc_cci_1_clk_src",
327 		.parent_data = cam_cc_parent_data_5,
328 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
329 		.ops = &clk_rcg2_shared_ops,
330 	},
331 };
332 
333 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
334 	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
335 	F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
336 	F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
337 	{ }
338 };
339 
340 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
341 	.cmd_rcgr = 0x9064,
342 	.mnd_width = 0,
343 	.hid_width = 5,
344 	.parent_map = cam_cc_parent_map_3,
345 	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
346 	.clkr.hw.init = &(struct clk_init_data){
347 		.name = "cam_cc_cphy_rx_clk_src",
348 		.parent_data = cam_cc_parent_data_3,
349 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
350 		.ops = &clk_rcg2_shared_ops,
351 	},
352 };
353 
354 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
355 	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
356 	{ }
357 };
358 
359 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
360 	.cmd_rcgr = 0x5004,
361 	.mnd_width = 0,
362 	.hid_width = 5,
363 	.parent_map = cam_cc_parent_map_0,
364 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
365 	.clkr.hw.init = &(struct clk_init_data){
366 		.name = "cam_cc_csi0phytimer_clk_src",
367 		.parent_data = cam_cc_parent_data_0,
368 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
369 		.ops = &clk_rcg2_shared_ops,
370 	},
371 };
372 
373 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
374 	.cmd_rcgr = 0x5028,
375 	.mnd_width = 0,
376 	.hid_width = 5,
377 	.parent_map = cam_cc_parent_map_0,
378 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
379 	.clkr.hw.init = &(struct clk_init_data){
380 		.name = "cam_cc_csi1phytimer_clk_src",
381 		.parent_data = cam_cc_parent_data_0,
382 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
383 		.ops = &clk_rcg2_shared_ops,
384 	},
385 };
386 
387 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
388 	.cmd_rcgr = 0x504c,
389 	.mnd_width = 0,
390 	.hid_width = 5,
391 	.parent_map = cam_cc_parent_map_0,
392 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
393 	.clkr.hw.init = &(struct clk_init_data){
394 		.name = "cam_cc_csi2phytimer_clk_src",
395 		.parent_data = cam_cc_parent_data_0,
396 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
397 		.ops = &clk_rcg2_shared_ops,
398 	},
399 };
400 
401 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
402 	.cmd_rcgr = 0x5070,
403 	.mnd_width = 0,
404 	.hid_width = 5,
405 	.parent_map = cam_cc_parent_map_0,
406 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
407 	.clkr.hw.init = &(struct clk_init_data){
408 		.name = "cam_cc_csi3phytimer_clk_src",
409 		.parent_data = cam_cc_parent_data_0,
410 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
411 		.ops = &clk_rcg2_shared_ops,
412 	},
413 };
414 
415 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
416 	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
417 	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
418 	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
419 	F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
420 	{ }
421 };
422 
423 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
424 	.cmd_rcgr = 0x603c,
425 	.mnd_width = 0,
426 	.hid_width = 5,
427 	.parent_map = cam_cc_parent_map_0,
428 	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
429 	.clkr.hw.init = &(struct clk_init_data){
430 		.name = "cam_cc_fast_ahb_clk_src",
431 		.parent_data = cam_cc_parent_data_0,
432 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
433 		.ops = &clk_rcg2_shared_ops,
434 	},
435 };
436 
437 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
438 	F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
439 	F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
440 	F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
441 	F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
442 	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
443 	{ }
444 };
445 
446 static struct clk_rcg2 cam_cc_icp_clk_src = {
447 	.cmd_rcgr = 0xb088,
448 	.mnd_width = 0,
449 	.hid_width = 5,
450 	.parent_map = cam_cc_parent_map_2,
451 	.freq_tbl = ftbl_cam_cc_icp_clk_src,
452 	.clkr.hw.init = &(struct clk_init_data){
453 		.name = "cam_cc_icp_clk_src",
454 		.parent_data = cam_cc_parent_data_2,
455 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
456 		.ops = &clk_rcg2_shared_ops,
457 	},
458 };
459 
460 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
461 	F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
462 	F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
463 	F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
464 	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
465 	{ }
466 };
467 
468 static struct clk_rcg2 cam_cc_ife_0_clk_src = {
469 	.cmd_rcgr = 0x9010,
470 	.mnd_width = 0,
471 	.hid_width = 5,
472 	.parent_map = cam_cc_parent_map_4,
473 	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
474 	.clkr.hw.init = &(struct clk_init_data){
475 		.name = "cam_cc_ife_0_clk_src",
476 		.parent_data = cam_cc_parent_data_4,
477 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
478 		.ops = &clk_rcg2_shared_ops,
479 	},
480 };
481 
482 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
483 	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
484 	F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
485 	F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
486 	F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
487 	{ }
488 };
489 
490 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
491 	.cmd_rcgr = 0x903c,
492 	.mnd_width = 0,
493 	.hid_width = 5,
494 	.parent_map = cam_cc_parent_map_3,
495 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
496 	.clkr.hw.init = &(struct clk_init_data){
497 		.name = "cam_cc_ife_0_csid_clk_src",
498 		.parent_data = cam_cc_parent_data_3,
499 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
500 		.ops = &clk_rcg2_shared_ops,
501 	},
502 };
503 
504 static struct clk_rcg2 cam_cc_ife_1_clk_src = {
505 	.cmd_rcgr = 0xa010,
506 	.mnd_width = 0,
507 	.hid_width = 5,
508 	.parent_map = cam_cc_parent_map_4,
509 	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
510 	.clkr.hw.init = &(struct clk_init_data){
511 		.name = "cam_cc_ife_1_clk_src",
512 		.parent_data = cam_cc_parent_data_4,
513 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
514 		.ops = &clk_rcg2_shared_ops,
515 	},
516 };
517 
518 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
519 	.cmd_rcgr = 0xa034,
520 	.mnd_width = 0,
521 	.hid_width = 5,
522 	.parent_map = cam_cc_parent_map_3,
523 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
524 	.clkr.hw.init = &(struct clk_init_data){
525 		.name = "cam_cc_ife_1_csid_clk_src",
526 		.parent_data = cam_cc_parent_data_3,
527 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
528 		.ops = &clk_rcg2_shared_ops,
529 	},
530 };
531 
532 static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
533 	.cmd_rcgr = 0xb004,
534 	.mnd_width = 0,
535 	.hid_width = 5,
536 	.parent_map = cam_cc_parent_map_4,
537 	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
538 	.clkr.hw.init = &(struct clk_init_data){
539 		.name = "cam_cc_ife_lite_clk_src",
540 		.parent_data = cam_cc_parent_data_4,
541 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
542 		.flags = CLK_SET_RATE_PARENT,
543 		.ops = &clk_rcg2_shared_ops,
544 	},
545 };
546 
547 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
548 	.cmd_rcgr = 0xb024,
549 	.mnd_width = 0,
550 	.hid_width = 5,
551 	.parent_map = cam_cc_parent_map_3,
552 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
553 	.clkr.hw.init = &(struct clk_init_data){
554 		.name = "cam_cc_ife_lite_csid_clk_src",
555 		.parent_data = cam_cc_parent_data_3,
556 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
557 		.ops = &clk_rcg2_shared_ops,
558 	},
559 };
560 
561 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
562 	F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
563 	F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
564 	F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
565 	F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0),
566 	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
567 	{ }
568 };
569 
570 static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
571 	.cmd_rcgr = 0x7010,
572 	.mnd_width = 0,
573 	.hid_width = 5,
574 	.parent_map = cam_cc_parent_map_2,
575 	.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
576 	.clkr.hw.init = &(struct clk_init_data){
577 		.name = "cam_cc_ipe_0_clk_src",
578 		.parent_data = cam_cc_parent_data_2,
579 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
580 		.ops = &clk_rcg2_shared_ops,
581 	},
582 };
583 
584 static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
585 	F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
586 	F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0),
587 	F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
588 	F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0),
589 	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
590 	{ }
591 };
592 
593 static struct clk_rcg2 cam_cc_jpeg_clk_src = {
594 	.cmd_rcgr = 0xb04c,
595 	.mnd_width = 0,
596 	.hid_width = 5,
597 	.parent_map = cam_cc_parent_map_2,
598 	.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
599 	.clkr.hw.init = &(struct clk_init_data){
600 		.name = "cam_cc_jpeg_clk_src",
601 		.parent_data = cam_cc_parent_data_2,
602 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
603 		.ops = &clk_rcg2_shared_ops,
604 	},
605 };
606 
607 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
608 	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
609 	F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
610 	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
611 	F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
612 	{ }
613 };
614 
615 static struct clk_rcg2 cam_cc_lrme_clk_src = {
616 	.cmd_rcgr = 0xb0f8,
617 	.mnd_width = 0,
618 	.hid_width = 5,
619 	.parent_map = cam_cc_parent_map_6,
620 	.freq_tbl = ftbl_cam_cc_lrme_clk_src,
621 	.clkr.hw.init = &(struct clk_init_data){
622 		.name = "cam_cc_lrme_clk_src",
623 		.parent_data = cam_cc_parent_data_6,
624 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
625 		.ops = &clk_rcg2_shared_ops,
626 	},
627 };
628 
629 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
630 	F(19200000, P_BI_TCXO, 1, 0, 0),
631 	F(24000000, P_CAM_CC_PLL2_OUT_AUX, 10, 1, 2),
632 	F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0),
633 	{ }
634 };
635 
636 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
637 	.cmd_rcgr = 0x4004,
638 	.mnd_width = 8,
639 	.hid_width = 5,
640 	.parent_map = cam_cc_parent_map_1,
641 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
642 	.clkr.hw.init = &(struct clk_init_data){
643 		.name = "cam_cc_mclk0_clk_src",
644 		.parent_data = cam_cc_parent_data_1,
645 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
646 		.ops = &clk_rcg2_shared_ops,
647 	},
648 };
649 
650 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
651 	.cmd_rcgr = 0x4024,
652 	.mnd_width = 8,
653 	.hid_width = 5,
654 	.parent_map = cam_cc_parent_map_1,
655 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
656 	.clkr.hw.init = &(struct clk_init_data){
657 		.name = "cam_cc_mclk1_clk_src",
658 		.parent_data = cam_cc_parent_data_1,
659 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
660 		.ops = &clk_rcg2_shared_ops,
661 	},
662 };
663 
664 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
665 	.cmd_rcgr = 0x4044,
666 	.mnd_width = 8,
667 	.hid_width = 5,
668 	.parent_map = cam_cc_parent_map_1,
669 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
670 	.clkr.hw.init = &(struct clk_init_data){
671 		.name = "cam_cc_mclk2_clk_src",
672 		.parent_data = cam_cc_parent_data_1,
673 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
674 		.ops = &clk_rcg2_shared_ops,
675 	},
676 };
677 
678 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
679 	.cmd_rcgr = 0x4064,
680 	.mnd_width = 8,
681 	.hid_width = 5,
682 	.parent_map = cam_cc_parent_map_1,
683 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
684 	.clkr.hw.init = &(struct clk_init_data){
685 		.name = "cam_cc_mclk3_clk_src",
686 		.parent_data = cam_cc_parent_data_1,
687 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
688 		.ops = &clk_rcg2_shared_ops,
689 	},
690 };
691 
692 static struct clk_rcg2 cam_cc_mclk4_clk_src = {
693 	.cmd_rcgr = 0x4084,
694 	.mnd_width = 8,
695 	.hid_width = 5,
696 	.parent_map = cam_cc_parent_map_1,
697 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
698 	.clkr.hw.init = &(struct clk_init_data){
699 		.name = "cam_cc_mclk4_clk_src",
700 		.parent_data = cam_cc_parent_data_1,
701 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
702 		.ops = &clk_rcg2_shared_ops,
703 	},
704 };
705 
706 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
707 	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
708 	{ }
709 };
710 
711 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
712 	.cmd_rcgr = 0x6058,
713 	.mnd_width = 0,
714 	.hid_width = 5,
715 	.parent_map = cam_cc_parent_map_0,
716 	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
717 	.clkr.hw.init = &(struct clk_init_data){
718 		.name = "cam_cc_slow_ahb_clk_src",
719 		.parent_data = cam_cc_parent_data_0,
720 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
721 		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
722 		.ops = &clk_rcg2_shared_ops,
723 	},
724 };
725 
726 static struct clk_branch cam_cc_bps_ahb_clk = {
727 	.halt_reg = 0x6070,
728 	.halt_check = BRANCH_HALT,
729 	.clkr = {
730 		.enable_reg = 0x6070,
731 		.enable_mask = BIT(0),
732 		.hw.init = &(struct clk_init_data){
733 			.name = "cam_cc_bps_ahb_clk",
734 			.parent_hws = (const struct clk_hw*[]){
735 				&cam_cc_slow_ahb_clk_src.clkr.hw,
736 			},
737 			.num_parents = 1,
738 			.flags = CLK_SET_RATE_PARENT,
739 			.ops = &clk_branch2_ops,
740 		},
741 	},
742 };
743 
744 static struct clk_branch cam_cc_bps_areg_clk = {
745 	.halt_reg = 0x6054,
746 	.halt_check = BRANCH_HALT,
747 	.clkr = {
748 		.enable_reg = 0x6054,
749 		.enable_mask = BIT(0),
750 		.hw.init = &(struct clk_init_data){
751 			.name = "cam_cc_bps_areg_clk",
752 			.parent_hws = (const struct clk_hw*[]){
753 				&cam_cc_fast_ahb_clk_src.clkr.hw,
754 			},
755 			.num_parents = 1,
756 			.flags = CLK_SET_RATE_PARENT,
757 			.ops = &clk_branch2_ops,
758 		},
759 	},
760 };
761 
762 static struct clk_branch cam_cc_bps_axi_clk = {
763 	.halt_reg = 0x6038,
764 	.halt_check = BRANCH_HALT,
765 	.clkr = {
766 		.enable_reg = 0x6038,
767 		.enable_mask = BIT(0),
768 		.hw.init = &(struct clk_init_data){
769 			.name = "cam_cc_bps_axi_clk",
770 			.ops = &clk_branch2_ops,
771 		},
772 	},
773 };
774 
775 static struct clk_branch cam_cc_bps_clk = {
776 	.halt_reg = 0x6028,
777 	.halt_check = BRANCH_HALT,
778 	.clkr = {
779 		.enable_reg = 0x6028,
780 		.enable_mask = BIT(0),
781 		.hw.init = &(struct clk_init_data){
782 			.name = "cam_cc_bps_clk",
783 			.parent_hws = (const struct clk_hw*[]){
784 				&cam_cc_bps_clk_src.clkr.hw,
785 			},
786 			.num_parents = 1,
787 			.flags = CLK_SET_RATE_PARENT,
788 			.ops = &clk_branch2_ops,
789 		},
790 	},
791 };
792 
793 static struct clk_branch cam_cc_camnoc_axi_clk = {
794 	.halt_reg = 0xb124,
795 	.halt_check = BRANCH_HALT,
796 	.clkr = {
797 		.enable_reg = 0xb124,
798 		.enable_mask = BIT(0),
799 		.hw.init = &(struct clk_init_data){
800 			.name = "cam_cc_camnoc_axi_clk",
801 			.ops = &clk_branch2_ops,
802 		},
803 	},
804 };
805 
806 static struct clk_branch cam_cc_cci_0_clk = {
807 	.halt_reg = 0xb0f0,
808 	.halt_check = BRANCH_HALT,
809 	.clkr = {
810 		.enable_reg = 0xb0f0,
811 		.enable_mask = BIT(0),
812 		.hw.init = &(struct clk_init_data){
813 			.name = "cam_cc_cci_0_clk",
814 			.parent_hws = (const struct clk_hw*[]){
815 				&cam_cc_cci_0_clk_src.clkr.hw,
816 			},
817 			.num_parents = 1,
818 			.flags = CLK_SET_RATE_PARENT,
819 			.ops = &clk_branch2_ops,
820 		},
821 	},
822 };
823 
824 static struct clk_branch cam_cc_cci_1_clk = {
825 	.halt_reg = 0xb164,
826 	.halt_check = BRANCH_HALT,
827 	.clkr = {
828 		.enable_reg = 0xb164,
829 		.enable_mask = BIT(0),
830 		.hw.init = &(struct clk_init_data){
831 			.name = "cam_cc_cci_1_clk",
832 			.parent_hws = (const struct clk_hw*[]){
833 				&cam_cc_cci_1_clk_src.clkr.hw,
834 			},
835 			.num_parents = 1,
836 			.flags = CLK_SET_RATE_PARENT,
837 			.ops = &clk_branch2_ops,
838 		},
839 	},
840 };
841 
842 static struct clk_branch cam_cc_core_ahb_clk = {
843 	.halt_reg = 0xb144,
844 	.halt_check = BRANCH_HALT_DELAY,
845 	.clkr = {
846 		.enable_reg = 0xb144,
847 		.enable_mask = BIT(0),
848 		.hw.init = &(struct clk_init_data){
849 			.name = "cam_cc_core_ahb_clk",
850 			.parent_hws = (const struct clk_hw*[]){
851 				&cam_cc_slow_ahb_clk_src.clkr.hw,
852 			},
853 			.num_parents = 1,
854 			.flags = CLK_SET_RATE_PARENT,
855 			.ops = &clk_branch2_ops,
856 		},
857 	},
858 };
859 
860 static struct clk_branch cam_cc_cpas_ahb_clk = {
861 	.halt_reg = 0xb11c,
862 	.halt_check = BRANCH_HALT,
863 	.clkr = {
864 		.enable_reg = 0xb11c,
865 		.enable_mask = BIT(0),
866 		.hw.init = &(struct clk_init_data){
867 			.name = "cam_cc_cpas_ahb_clk",
868 			.parent_hws = (const struct clk_hw*[]){
869 				&cam_cc_slow_ahb_clk_src.clkr.hw,
870 			},
871 			.num_parents = 1,
872 			.flags = CLK_SET_RATE_PARENT,
873 			.ops = &clk_branch2_ops,
874 		},
875 	},
876 };
877 
878 static struct clk_branch cam_cc_csi0phytimer_clk = {
879 	.halt_reg = 0x501c,
880 	.halt_check = BRANCH_HALT,
881 	.clkr = {
882 		.enable_reg = 0x501c,
883 		.enable_mask = BIT(0),
884 		.hw.init = &(struct clk_init_data){
885 			.name = "cam_cc_csi0phytimer_clk",
886 			.parent_hws = (const struct clk_hw*[]){
887 				&cam_cc_csi0phytimer_clk_src.clkr.hw,
888 			},
889 			.num_parents = 1,
890 			.flags = CLK_SET_RATE_PARENT,
891 			.ops = &clk_branch2_ops,
892 		},
893 	},
894 };
895 
896 static struct clk_branch cam_cc_csi1phytimer_clk = {
897 	.halt_reg = 0x5040,
898 	.halt_check = BRANCH_HALT,
899 	.clkr = {
900 		.enable_reg = 0x5040,
901 		.enable_mask = BIT(0),
902 		.hw.init = &(struct clk_init_data){
903 			.name = "cam_cc_csi1phytimer_clk",
904 			.parent_hws = (const struct clk_hw*[]){
905 				&cam_cc_csi1phytimer_clk_src.clkr.hw,
906 			},
907 			.num_parents = 1,
908 			.flags = CLK_SET_RATE_PARENT,
909 			.ops = &clk_branch2_ops,
910 		},
911 	},
912 };
913 
914 static struct clk_branch cam_cc_csi2phytimer_clk = {
915 	.halt_reg = 0x5064,
916 	.halt_check = BRANCH_HALT,
917 	.clkr = {
918 		.enable_reg = 0x5064,
919 		.enable_mask = BIT(0),
920 		.hw.init = &(struct clk_init_data){
921 			.name = "cam_cc_csi2phytimer_clk",
922 			.parent_hws = (const struct clk_hw*[]){
923 				&cam_cc_csi2phytimer_clk_src.clkr.hw,
924 			},
925 			.num_parents = 1,
926 			.flags = CLK_SET_RATE_PARENT,
927 			.ops = &clk_branch2_ops,
928 		},
929 	},
930 };
931 
932 static struct clk_branch cam_cc_csi3phytimer_clk = {
933 	.halt_reg = 0x5088,
934 	.halt_check = BRANCH_HALT,
935 	.clkr = {
936 		.enable_reg = 0x5088,
937 		.enable_mask = BIT(0),
938 		.hw.init = &(struct clk_init_data){
939 			.name = "cam_cc_csi3phytimer_clk",
940 			.parent_hws = (const struct clk_hw*[]){
941 				&cam_cc_csi3phytimer_clk_src.clkr.hw,
942 			},
943 			.num_parents = 1,
944 			.flags = CLK_SET_RATE_PARENT,
945 			.ops = &clk_branch2_ops,
946 		},
947 	},
948 };
949 
950 static struct clk_branch cam_cc_csiphy0_clk = {
951 	.halt_reg = 0x5020,
952 	.halt_check = BRANCH_HALT,
953 	.clkr = {
954 		.enable_reg = 0x5020,
955 		.enable_mask = BIT(0),
956 		.hw.init = &(struct clk_init_data){
957 			.name = "cam_cc_csiphy0_clk",
958 			.parent_hws = (const struct clk_hw*[]){
959 				&cam_cc_cphy_rx_clk_src.clkr.hw,
960 			},
961 			.num_parents = 1,
962 			.flags = CLK_SET_RATE_PARENT,
963 			.ops = &clk_branch2_ops,
964 		},
965 	},
966 };
967 
968 static struct clk_branch cam_cc_csiphy1_clk = {
969 	.halt_reg = 0x5044,
970 	.halt_check = BRANCH_HALT,
971 	.clkr = {
972 		.enable_reg = 0x5044,
973 		.enable_mask = BIT(0),
974 		.hw.init = &(struct clk_init_data){
975 			.name = "cam_cc_csiphy1_clk",
976 			.parent_hws = (const struct clk_hw*[]){
977 				&cam_cc_cphy_rx_clk_src.clkr.hw,
978 			},
979 			.num_parents = 1,
980 			.flags = CLK_SET_RATE_PARENT,
981 			.ops = &clk_branch2_ops,
982 		},
983 	},
984 };
985 
986 static struct clk_branch cam_cc_csiphy2_clk = {
987 	.halt_reg = 0x5068,
988 	.halt_check = BRANCH_HALT,
989 	.clkr = {
990 		.enable_reg = 0x5068,
991 		.enable_mask = BIT(0),
992 		.hw.init = &(struct clk_init_data){
993 			.name = "cam_cc_csiphy2_clk",
994 			.parent_hws = (const struct clk_hw*[]){
995 				&cam_cc_cphy_rx_clk_src.clkr.hw,
996 			},
997 			.num_parents = 1,
998 			.flags = CLK_SET_RATE_PARENT,
999 			.ops = &clk_branch2_ops,
1000 		},
1001 	},
1002 };
1003 
1004 static struct clk_branch cam_cc_csiphy3_clk = {
1005 	.halt_reg = 0x508c,
1006 	.halt_check = BRANCH_HALT,
1007 	.clkr = {
1008 		.enable_reg = 0x508c,
1009 		.enable_mask = BIT(0),
1010 		.hw.init = &(struct clk_init_data){
1011 			.name = "cam_cc_csiphy3_clk",
1012 			.parent_hws = (const struct clk_hw*[]){
1013 				&cam_cc_cphy_rx_clk_src.clkr.hw,
1014 			},
1015 			.num_parents = 1,
1016 			.flags = CLK_SET_RATE_PARENT,
1017 			.ops = &clk_branch2_ops,
1018 		},
1019 	},
1020 };
1021 
1022 static struct clk_branch cam_cc_icp_clk = {
1023 	.halt_reg = 0xb0a0,
1024 	.halt_check = BRANCH_HALT,
1025 	.clkr = {
1026 		.enable_reg = 0xb0a0,
1027 		.enable_mask = BIT(0),
1028 		.hw.init = &(struct clk_init_data){
1029 			.name = "cam_cc_icp_clk",
1030 			.parent_hws = (const struct clk_hw*[]){
1031 				&cam_cc_icp_clk_src.clkr.hw,
1032 			},
1033 			.num_parents = 1,
1034 			.flags = CLK_SET_RATE_PARENT,
1035 			.ops = &clk_branch2_ops,
1036 		},
1037 	},
1038 };
1039 
1040 static struct clk_branch cam_cc_ife_0_axi_clk = {
1041 	.halt_reg = 0x9080,
1042 	.halt_check = BRANCH_HALT,
1043 	.clkr = {
1044 		.enable_reg = 0x9080,
1045 		.enable_mask = BIT(0),
1046 		.hw.init = &(struct clk_init_data){
1047 			.name = "cam_cc_ife_0_axi_clk",
1048 			.ops = &clk_branch2_ops,
1049 		},
1050 	},
1051 };
1052 
1053 static struct clk_branch cam_cc_ife_0_clk = {
1054 	.halt_reg = 0x9028,
1055 	.halt_check = BRANCH_HALT,
1056 	.clkr = {
1057 		.enable_reg = 0x9028,
1058 		.enable_mask = BIT(0),
1059 		.hw.init = &(struct clk_init_data){
1060 			.name = "cam_cc_ife_0_clk",
1061 			.parent_hws = (const struct clk_hw*[]){
1062 				&cam_cc_ife_0_clk_src.clkr.hw,
1063 			},
1064 			.num_parents = 1,
1065 			.flags = CLK_SET_RATE_PARENT,
1066 			.ops = &clk_branch2_ops,
1067 		},
1068 	},
1069 };
1070 
1071 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1072 	.halt_reg = 0x907c,
1073 	.halt_check = BRANCH_HALT,
1074 	.clkr = {
1075 		.enable_reg = 0x907c,
1076 		.enable_mask = BIT(0),
1077 		.hw.init = &(struct clk_init_data){
1078 			.name = "cam_cc_ife_0_cphy_rx_clk",
1079 			.parent_hws = (const struct clk_hw*[]){
1080 				&cam_cc_cphy_rx_clk_src.clkr.hw,
1081 			},
1082 			.num_parents = 1,
1083 			.flags = CLK_SET_RATE_PARENT,
1084 			.ops = &clk_branch2_ops,
1085 		},
1086 	},
1087 };
1088 
1089 static struct clk_branch cam_cc_ife_0_csid_clk = {
1090 	.halt_reg = 0x9054,
1091 	.halt_check = BRANCH_HALT,
1092 	.clkr = {
1093 		.enable_reg = 0x9054,
1094 		.enable_mask = BIT(0),
1095 		.hw.init = &(struct clk_init_data){
1096 			.name = "cam_cc_ife_0_csid_clk",
1097 			.parent_hws = (const struct clk_hw*[]){
1098 				&cam_cc_ife_0_csid_clk_src.clkr.hw,
1099 			},
1100 			.num_parents = 1,
1101 			.flags = CLK_SET_RATE_PARENT,
1102 			.ops = &clk_branch2_ops,
1103 		},
1104 	},
1105 };
1106 
1107 static struct clk_branch cam_cc_ife_0_dsp_clk = {
1108 	.halt_reg = 0x9038,
1109 	.halt_check = BRANCH_HALT,
1110 	.clkr = {
1111 		.enable_reg = 0x9038,
1112 		.enable_mask = BIT(0),
1113 		.hw.init = &(struct clk_init_data){
1114 			.name = "cam_cc_ife_0_dsp_clk",
1115 			.parent_hws = (const struct clk_hw*[]){
1116 				&cam_cc_ife_0_clk_src.clkr.hw,
1117 			},
1118 			.num_parents = 1,
1119 			.flags = CLK_SET_RATE_PARENT,
1120 			.ops = &clk_branch2_ops,
1121 		},
1122 	},
1123 };
1124 
1125 static struct clk_branch cam_cc_ife_1_axi_clk = {
1126 	.halt_reg = 0xa058,
1127 	.halt_check = BRANCH_HALT,
1128 	.clkr = {
1129 		.enable_reg = 0xa058,
1130 		.enable_mask = BIT(0),
1131 		.hw.init = &(struct clk_init_data){
1132 			.name = "cam_cc_ife_1_axi_clk",
1133 			.ops = &clk_branch2_ops,
1134 		},
1135 	},
1136 };
1137 
1138 static struct clk_branch cam_cc_ife_1_clk = {
1139 	.halt_reg = 0xa028,
1140 	.halt_check = BRANCH_HALT,
1141 	.clkr = {
1142 		.enable_reg = 0xa028,
1143 		.enable_mask = BIT(0),
1144 		.hw.init = &(struct clk_init_data){
1145 			.name = "cam_cc_ife_1_clk",
1146 			.parent_hws = (const struct clk_hw*[]){
1147 				&cam_cc_ife_1_clk_src.clkr.hw,
1148 			},
1149 			.num_parents = 1,
1150 			.flags = CLK_SET_RATE_PARENT,
1151 			.ops = &clk_branch2_ops,
1152 		},
1153 	},
1154 };
1155 
1156 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1157 	.halt_reg = 0xa054,
1158 	.halt_check = BRANCH_HALT,
1159 	.clkr = {
1160 		.enable_reg = 0xa054,
1161 		.enable_mask = BIT(0),
1162 		.hw.init = &(struct clk_init_data){
1163 			.name = "cam_cc_ife_1_cphy_rx_clk",
1164 			.parent_hws = (const struct clk_hw*[]){
1165 				&cam_cc_cphy_rx_clk_src.clkr.hw,
1166 			},
1167 			.num_parents = 1,
1168 			.flags = CLK_SET_RATE_PARENT,
1169 			.ops = &clk_branch2_ops,
1170 		},
1171 	},
1172 };
1173 
1174 static struct clk_branch cam_cc_ife_1_csid_clk = {
1175 	.halt_reg = 0xa04c,
1176 	.halt_check = BRANCH_HALT,
1177 	.clkr = {
1178 		.enable_reg = 0xa04c,
1179 		.enable_mask = BIT(0),
1180 		.hw.init = &(struct clk_init_data){
1181 			.name = "cam_cc_ife_1_csid_clk",
1182 			.parent_hws = (const struct clk_hw*[]){
1183 				&cam_cc_ife_1_csid_clk_src.clkr.hw,
1184 			},
1185 			.num_parents = 1,
1186 			.flags = CLK_SET_RATE_PARENT,
1187 			.ops = &clk_branch2_ops,
1188 		},
1189 	},
1190 };
1191 
1192 static struct clk_branch cam_cc_ife_1_dsp_clk = {
1193 	.halt_reg = 0xa030,
1194 	.halt_check = BRANCH_HALT,
1195 	.clkr = {
1196 		.enable_reg = 0xa030,
1197 		.enable_mask = BIT(0),
1198 		.hw.init = &(struct clk_init_data){
1199 			.name = "cam_cc_ife_1_dsp_clk",
1200 			.parent_hws = (const struct clk_hw*[]){
1201 				&cam_cc_ife_1_clk_src.clkr.hw,
1202 			},
1203 			.num_parents = 1,
1204 			.flags = CLK_SET_RATE_PARENT,
1205 			.ops = &clk_branch2_ops,
1206 		},
1207 	},
1208 };
1209 
1210 static struct clk_branch cam_cc_ife_lite_clk = {
1211 	.halt_reg = 0xb01c,
1212 	.halt_check = BRANCH_HALT,
1213 	.clkr = {
1214 		.enable_reg = 0xb01c,
1215 		.enable_mask = BIT(0),
1216 		.hw.init = &(struct clk_init_data){
1217 			.name = "cam_cc_ife_lite_clk",
1218 			.parent_hws = (const struct clk_hw*[]){
1219 				&cam_cc_ife_lite_clk_src.clkr.hw,
1220 			},
1221 			.num_parents = 1,
1222 			.flags = CLK_SET_RATE_PARENT,
1223 			.ops = &clk_branch2_ops,
1224 		},
1225 	},
1226 };
1227 
1228 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
1229 	.halt_reg = 0xb044,
1230 	.halt_check = BRANCH_HALT,
1231 	.clkr = {
1232 		.enable_reg = 0xb044,
1233 		.enable_mask = BIT(0),
1234 		.hw.init = &(struct clk_init_data){
1235 			.name = "cam_cc_ife_lite_cphy_rx_clk",
1236 			.parent_hws = (const struct clk_hw*[]){
1237 				&cam_cc_cphy_rx_clk_src.clkr.hw,
1238 			},
1239 			.num_parents = 1,
1240 			.flags = CLK_SET_RATE_PARENT,
1241 			.ops = &clk_branch2_ops,
1242 		},
1243 	},
1244 };
1245 
1246 static struct clk_branch cam_cc_ife_lite_csid_clk = {
1247 	.halt_reg = 0xb03c,
1248 	.halt_check = BRANCH_HALT,
1249 	.clkr = {
1250 		.enable_reg = 0xb03c,
1251 		.enable_mask = BIT(0),
1252 		.hw.init = &(struct clk_init_data){
1253 			.name = "cam_cc_ife_lite_csid_clk",
1254 			.parent_hws = (const struct clk_hw*[]){
1255 				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
1256 			},
1257 			.num_parents = 1,
1258 			.flags = CLK_SET_RATE_PARENT,
1259 			.ops = &clk_branch2_ops,
1260 		},
1261 	},
1262 };
1263 
1264 static struct clk_branch cam_cc_ipe_0_ahb_clk = {
1265 	.halt_reg = 0x7040,
1266 	.halt_check = BRANCH_HALT,
1267 	.clkr = {
1268 		.enable_reg = 0x7040,
1269 		.enable_mask = BIT(0),
1270 		.hw.init = &(struct clk_init_data){
1271 			.name = "cam_cc_ipe_0_ahb_clk",
1272 			.parent_hws = (const struct clk_hw*[]){
1273 				&cam_cc_slow_ahb_clk_src.clkr.hw,
1274 			},
1275 			.num_parents = 1,
1276 			.flags = CLK_SET_RATE_PARENT,
1277 			.ops = &clk_branch2_ops,
1278 		},
1279 	},
1280 };
1281 
1282 static struct clk_branch cam_cc_ipe_0_areg_clk = {
1283 	.halt_reg = 0x703c,
1284 	.halt_check = BRANCH_HALT,
1285 	.clkr = {
1286 		.enable_reg = 0x703c,
1287 		.enable_mask = BIT(0),
1288 		.hw.init = &(struct clk_init_data){
1289 			.name = "cam_cc_ipe_0_areg_clk",
1290 			.parent_hws = (const struct clk_hw*[]){
1291 				&cam_cc_fast_ahb_clk_src.clkr.hw,
1292 			},
1293 			.num_parents = 1,
1294 			.flags = CLK_SET_RATE_PARENT,
1295 			.ops = &clk_branch2_ops,
1296 		},
1297 	},
1298 };
1299 
1300 static struct clk_branch cam_cc_ipe_0_axi_clk = {
1301 	.halt_reg = 0x7038,
1302 	.halt_check = BRANCH_HALT,
1303 	.clkr = {
1304 		.enable_reg = 0x7038,
1305 		.enable_mask = BIT(0),
1306 		.hw.init = &(struct clk_init_data){
1307 			.name = "cam_cc_ipe_0_axi_clk",
1308 			.ops = &clk_branch2_ops,
1309 		},
1310 	},
1311 };
1312 
1313 static struct clk_branch cam_cc_ipe_0_clk = {
1314 	.halt_reg = 0x7028,
1315 	.halt_check = BRANCH_HALT,
1316 	.clkr = {
1317 		.enable_reg = 0x7028,
1318 		.enable_mask = BIT(0),
1319 		.hw.init = &(struct clk_init_data){
1320 			.name = "cam_cc_ipe_0_clk",
1321 			.parent_hws = (const struct clk_hw*[]){
1322 				&cam_cc_ipe_0_clk_src.clkr.hw,
1323 			},
1324 			.num_parents = 1,
1325 			.flags = CLK_SET_RATE_PARENT,
1326 			.ops = &clk_branch2_ops,
1327 		},
1328 	},
1329 };
1330 
1331 static struct clk_branch cam_cc_jpeg_clk = {
1332 	.halt_reg = 0xb064,
1333 	.halt_check = BRANCH_HALT,
1334 	.clkr = {
1335 		.enable_reg = 0xb064,
1336 		.enable_mask = BIT(0),
1337 		.hw.init = &(struct clk_init_data){
1338 			.name = "cam_cc_jpeg_clk",
1339 			.parent_hws = (const struct clk_hw*[]){
1340 				&cam_cc_jpeg_clk_src.clkr.hw,
1341 			},
1342 			.num_parents = 1,
1343 			.flags = CLK_SET_RATE_PARENT,
1344 			.ops = &clk_branch2_ops,
1345 		},
1346 	},
1347 };
1348 
1349 static struct clk_branch cam_cc_lrme_clk = {
1350 	.halt_reg = 0xb110,
1351 	.halt_check = BRANCH_HALT,
1352 	.clkr = {
1353 		.enable_reg = 0xb110,
1354 		.enable_mask = BIT(0),
1355 		.hw.init = &(struct clk_init_data){
1356 			.name = "cam_cc_lrme_clk",
1357 			.parent_hws = (const struct clk_hw*[]){
1358 				&cam_cc_lrme_clk_src.clkr.hw,
1359 			},
1360 			.num_parents = 1,
1361 			.flags = CLK_SET_RATE_PARENT,
1362 			.ops = &clk_branch2_ops,
1363 		},
1364 	},
1365 };
1366 
1367 static struct clk_branch cam_cc_mclk0_clk = {
1368 	.halt_reg = 0x401c,
1369 	.halt_check = BRANCH_HALT,
1370 	.clkr = {
1371 		.enable_reg = 0x401c,
1372 		.enable_mask = BIT(0),
1373 		.hw.init = &(struct clk_init_data){
1374 			.name = "cam_cc_mclk0_clk",
1375 			.parent_hws = (const struct clk_hw*[]){
1376 				&cam_cc_mclk0_clk_src.clkr.hw,
1377 			},
1378 			.num_parents = 1,
1379 			.flags = CLK_SET_RATE_PARENT,
1380 			.ops = &clk_branch2_ops,
1381 		},
1382 	},
1383 };
1384 
1385 static struct clk_branch cam_cc_mclk1_clk = {
1386 	.halt_reg = 0x403c,
1387 	.halt_check = BRANCH_HALT,
1388 	.clkr = {
1389 		.enable_reg = 0x403c,
1390 		.enable_mask = BIT(0),
1391 		.hw.init = &(struct clk_init_data){
1392 			.name = "cam_cc_mclk1_clk",
1393 			.parent_hws = (const struct clk_hw*[]){
1394 				&cam_cc_mclk1_clk_src.clkr.hw,
1395 			},
1396 			.num_parents = 1,
1397 			.flags = CLK_SET_RATE_PARENT,
1398 			.ops = &clk_branch2_ops,
1399 		},
1400 	},
1401 };
1402 
1403 static struct clk_branch cam_cc_mclk2_clk = {
1404 	.halt_reg = 0x405c,
1405 	.halt_check = BRANCH_HALT,
1406 	.clkr = {
1407 		.enable_reg = 0x405c,
1408 		.enable_mask = BIT(0),
1409 		.hw.init = &(struct clk_init_data){
1410 			.name = "cam_cc_mclk2_clk",
1411 			.parent_hws = (const struct clk_hw*[]){
1412 				&cam_cc_mclk2_clk_src.clkr.hw,
1413 			},
1414 			.num_parents = 1,
1415 			.flags = CLK_SET_RATE_PARENT,
1416 			.ops = &clk_branch2_ops,
1417 		},
1418 	},
1419 };
1420 
1421 static struct clk_branch cam_cc_mclk3_clk = {
1422 	.halt_reg = 0x407c,
1423 	.halt_check = BRANCH_HALT,
1424 	.clkr = {
1425 		.enable_reg = 0x407c,
1426 		.enable_mask = BIT(0),
1427 		.hw.init = &(struct clk_init_data){
1428 			.name = "cam_cc_mclk3_clk",
1429 			.parent_hws = (const struct clk_hw*[]){
1430 				&cam_cc_mclk3_clk_src.clkr.hw,
1431 			},
1432 			.num_parents = 1,
1433 			.flags = CLK_SET_RATE_PARENT,
1434 			.ops = &clk_branch2_ops,
1435 		},
1436 	},
1437 };
1438 
1439 static struct clk_branch cam_cc_mclk4_clk = {
1440 	.halt_reg = 0x409c,
1441 	.halt_check = BRANCH_HALT,
1442 	.clkr = {
1443 		.enable_reg = 0x409c,
1444 		.enable_mask = BIT(0),
1445 		.hw.init = &(struct clk_init_data){
1446 			.name = "cam_cc_mclk4_clk",
1447 			.parent_hws = (const struct clk_hw*[]){
1448 				&cam_cc_mclk4_clk_src.clkr.hw,
1449 			},
1450 			.num_parents = 1,
1451 			.flags = CLK_SET_RATE_PARENT,
1452 			.ops = &clk_branch2_ops,
1453 		},
1454 	},
1455 };
1456 
1457 static struct clk_branch cam_cc_soc_ahb_clk = {
1458 	.halt_reg = 0xb140,
1459 	.halt_check = BRANCH_HALT,
1460 	.clkr = {
1461 		.enable_reg = 0xb140,
1462 		.enable_mask = BIT(0),
1463 		.hw.init = &(struct clk_init_data){
1464 			.name = "cam_cc_soc_ahb_clk",
1465 			.ops = &clk_branch2_ops,
1466 		},
1467 	},
1468 };
1469 
1470 static struct clk_branch cam_cc_sys_tmr_clk = {
1471 	.halt_reg = 0xb0a8,
1472 	.halt_check = BRANCH_HALT,
1473 	.clkr = {
1474 		.enable_reg = 0xb0a8,
1475 		.enable_mask = BIT(0),
1476 		.hw.init = &(struct clk_init_data){
1477 			.name = "cam_cc_sys_tmr_clk",
1478 			.ops = &clk_branch2_ops,
1479 		},
1480 	},
1481 };
1482 
1483 static struct gdsc titan_top_gdsc = {
1484 	.gdscr = 0xb134,
1485 	.pd = {
1486 		.name = "titan_top_gdsc",
1487 	},
1488 	.pwrsts = PWRSTS_OFF_ON,
1489 };
1490 
1491 static struct gdsc bps_gdsc = {
1492 	.gdscr = 0x6004,
1493 	.pd = {
1494 		.name = "bps_gdsc",
1495 	},
1496 	.pwrsts = PWRSTS_OFF_ON,
1497 	.parent = &titan_top_gdsc.pd,
1498 	.flags = HW_CTRL,
1499 };
1500 
1501 static struct gdsc ife_0_gdsc = {
1502 	.gdscr = 0x9004,
1503 	.pd = {
1504 		.name = "ife_0_gdsc",
1505 	},
1506 	.pwrsts = PWRSTS_OFF_ON,
1507 	.parent = &titan_top_gdsc.pd,
1508 };
1509 
1510 static struct gdsc ife_1_gdsc = {
1511 	.gdscr = 0xa004,
1512 	.pd = {
1513 		.name = "ife_1_gdsc",
1514 	},
1515 	.pwrsts = PWRSTS_OFF_ON,
1516 	.parent = &titan_top_gdsc.pd,
1517 };
1518 
1519 static struct gdsc ipe_0_gdsc = {
1520 	.gdscr = 0x7004,
1521 	.pd = {
1522 		.name = "ipe_0_gdsc",
1523 	},
1524 	.pwrsts = PWRSTS_OFF_ON,
1525 	.flags = HW_CTRL,
1526 	.parent = &titan_top_gdsc.pd,
1527 };
1528 
1529 
1530 static struct clk_hw *cam_cc_sc7180_hws[] = {
1531 	[CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw,
1532 };
1533 
1534 static struct clk_regmap *cam_cc_sc7180_clocks[] = {
1535 	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
1536 	[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
1537 	[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
1538 	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
1539 	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
1540 	[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
1541 	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
1542 	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
1543 	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
1544 	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
1545 	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
1546 	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
1547 	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
1548 	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
1549 	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
1550 	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
1551 	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
1552 	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
1553 	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
1554 	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
1555 	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
1556 	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
1557 	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
1558 	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
1559 	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
1560 	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
1561 	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
1562 	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
1563 	[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
1564 	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
1565 	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
1566 	[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
1567 	[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
1568 	[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
1569 	[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
1570 	[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
1571 	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
1572 	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
1573 	[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
1574 	[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
1575 	[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
1576 	[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
1577 	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
1578 	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
1579 	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
1580 	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
1581 	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
1582 	[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
1583 	[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
1584 	[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
1585 	[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
1586 	[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
1587 	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
1588 	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
1589 	[CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
1590 	[CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
1591 	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
1592 	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
1593 	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
1594 	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
1595 	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
1596 	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
1597 	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
1598 	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
1599 	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
1600 	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
1601 	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
1602 	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
1603 	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
1604 	[CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr,
1605 	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
1606 	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
1607 	[CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
1608 	[CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
1609 };
1610 static struct gdsc *cam_cc_sc7180_gdscs[] = {
1611 	[BPS_GDSC] = &bps_gdsc,
1612 	[IFE_0_GDSC] = &ife_0_gdsc,
1613 	[IFE_1_GDSC] = &ife_1_gdsc,
1614 	[IPE_0_GDSC] = &ipe_0_gdsc,
1615 	[TITAN_TOP_GDSC] = &titan_top_gdsc,
1616 };
1617 
1618 static const struct regmap_config cam_cc_sc7180_regmap_config = {
1619 	.reg_bits = 32,
1620 	.reg_stride = 4,
1621 	.val_bits = 32,
1622 	.max_register = 0xd028,
1623 	.fast_io = true,
1624 };
1625 
1626 static const struct qcom_cc_desc cam_cc_sc7180_desc = {
1627 	.config = &cam_cc_sc7180_regmap_config,
1628 	.clk_hws = cam_cc_sc7180_hws,
1629 	.num_clk_hws = ARRAY_SIZE(cam_cc_sc7180_hws),
1630 	.clks = cam_cc_sc7180_clocks,
1631 	.num_clks = ARRAY_SIZE(cam_cc_sc7180_clocks),
1632 	.gdscs = cam_cc_sc7180_gdscs,
1633 	.num_gdscs = ARRAY_SIZE(cam_cc_sc7180_gdscs),
1634 };
1635 
1636 static const struct of_device_id cam_cc_sc7180_match_table[] = {
1637 	{ .compatible = "qcom,sc7180-camcc" },
1638 	{ }
1639 };
1640 MODULE_DEVICE_TABLE(of, cam_cc_sc7180_match_table);
1641 
cam_cc_sc7180_probe(struct platform_device * pdev)1642 static int cam_cc_sc7180_probe(struct platform_device *pdev)
1643 {
1644 	struct regmap *regmap;
1645 	int ret;
1646 
1647 	ret = devm_pm_runtime_enable(&pdev->dev);
1648 	if (ret < 0)
1649 		return ret;
1650 
1651 	ret = devm_pm_clk_create(&pdev->dev);
1652 	if (ret < 0)
1653 		return ret;
1654 
1655 	ret = pm_clk_add(&pdev->dev, "xo");
1656 	if (ret < 0) {
1657 		dev_err(&pdev->dev, "Failed to acquire XO clock\n");
1658 		return ret;
1659 	}
1660 
1661 	ret = pm_clk_add(&pdev->dev, "iface");
1662 	if (ret < 0) {
1663 		dev_err(&pdev->dev, "Failed to acquire iface clock\n");
1664 		return ret;
1665 	}
1666 
1667 	ret = pm_runtime_resume_and_get(&pdev->dev);
1668 	if (ret)
1669 		return ret;
1670 
1671 	regmap = qcom_cc_map(pdev, &cam_cc_sc7180_desc);
1672 	if (IS_ERR(regmap)) {
1673 		ret = PTR_ERR(regmap);
1674 		pm_runtime_put(&pdev->dev);
1675 		return ret;
1676 	}
1677 
1678 	clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
1679 	clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
1680 	clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
1681 	clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
1682 
1683 	ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7180_desc, regmap);
1684 	pm_runtime_put(&pdev->dev);
1685 	if (ret < 0) {
1686 		dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");
1687 		return ret;
1688 	}
1689 
1690 	return 0;
1691 }
1692 
1693 static const struct dev_pm_ops cam_cc_pm_ops = {
1694 	SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
1695 };
1696 
1697 static struct platform_driver cam_cc_sc7180_driver = {
1698 	.probe = cam_cc_sc7180_probe,
1699 	.driver = {
1700 		.name = "cam_cc-sc7180",
1701 		.of_match_table = cam_cc_sc7180_match_table,
1702 		.pm = &cam_cc_pm_ops,
1703 	},
1704 };
1705 
1706 module_platform_driver(cam_cc_sc7180_driver);
1707 
1708 MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver");
1709 MODULE_LICENSE("GPL v2");
1710