1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/err.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14
15 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
16
17 #include "clk-alpha-pll.h"
18 #include "clk-branch.h"
19 #include "clk-rcg.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 P_BI_TCXO,
26 P_CAM_CC_PLL0_OUT_EVEN,
27 P_CAM_CC_PLL0_OUT_MAIN,
28 P_CAM_CC_PLL0_OUT_ODD,
29 P_CAM_CC_PLL1_OUT_EVEN,
30 P_CAM_CC_PLL2_OUT_AUX2,
31 P_CAM_CC_PLL2_OUT_EARLY,
32 P_CAM_CC_PLL3_OUT_EVEN,
33 P_CAM_CC_PLL4_OUT_EVEN,
34 P_CAM_CC_PLL5_OUT_EVEN,
35 P_CAM_CC_PLL6_OUT_EVEN,
36 P_CAM_CC_PLL6_OUT_MAIN,
37 P_CAM_CC_PLL6_OUT_ODD,
38 P_SLEEP_CLK,
39 };
40
41 static struct pll_vco lucid_vco[] = {
42 { 249600000, 2000000000, 0 },
43 };
44
45 static struct pll_vco zonda_vco[] = {
46 { 595200000UL, 3600000000UL, 0 },
47 };
48
49 /* 1200MHz Configuration */
50 static const struct alpha_pll_config cam_cc_pll0_config = {
51 .l = 0x3E,
52 .alpha = 0x8000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00002261,
55 .config_ctl_hi1_val = 0x329A299C,
56 .user_ctl_val = 0x00003101,
57 .user_ctl_hi_val = 0x00000805,
58 .user_ctl_hi1_val = 0x00000000,
59 };
60
61 static struct clk_alpha_pll cam_cc_pll0 = {
62 .offset = 0x0,
63 .vco_table = lucid_vco,
64 .num_vco = ARRAY_SIZE(lucid_vco),
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
66 .clkr = {
67 .hw.init = &(struct clk_init_data){
68 .name = "cam_cc_pll0",
69 .parent_data = &(const struct clk_parent_data){
70 .fw_name = "bi_tcxo",
71 },
72 .num_parents = 1,
73 .ops = &clk_alpha_pll_lucid_ops,
74 },
75 },
76 };
77
78 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
79 { 0x1, 2 },
80 { }
81 };
82
83 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
84 .offset = 0x0,
85 .post_div_shift = 8,
86 .post_div_table = post_div_table_cam_cc_pll0_out_even,
87 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
88 .width = 4,
89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
90 .clkr.hw.init = &(struct clk_init_data){
91 .name = "cam_cc_pll0_out_even",
92 .parent_hws = (const struct clk_hw*[]) {
93 &cam_cc_pll0.clkr.hw,
94 },
95 .num_parents = 1,
96 .flags = CLK_SET_RATE_PARENT,
97 .ops = &clk_alpha_pll_postdiv_lucid_ops,
98 },
99 };
100
101 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
102 { 0x3, 3 },
103 { }
104 };
105
106 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
107 .offset = 0x0,
108 .post_div_shift = 12,
109 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
110 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
111 .width = 4,
112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
113 .clkr.hw.init = &(struct clk_init_data){
114 .name = "cam_cc_pll0_out_odd",
115 .parent_hws = (const struct clk_hw*[]) {
116 &cam_cc_pll0.clkr.hw,
117 },
118 .num_parents = 1,
119 .flags = CLK_SET_RATE_PARENT,
120 .ops = &clk_alpha_pll_postdiv_lucid_ops,
121 },
122 };
123
124 /* 600MHz Configuration */
125 static const struct alpha_pll_config cam_cc_pll1_config = {
126 .l = 0x1F,
127 .alpha = 0x4000,
128 .config_ctl_val = 0x20485699,
129 .config_ctl_hi_val = 0x00002261,
130 .config_ctl_hi1_val = 0x329A299C,
131 .user_ctl_val = 0x00000101,
132 .user_ctl_hi_val = 0x00000805,
133 .user_ctl_hi1_val = 0x00000000,
134 };
135
136 static struct clk_alpha_pll cam_cc_pll1 = {
137 .offset = 0x1000,
138 .vco_table = lucid_vco,
139 .num_vco = ARRAY_SIZE(lucid_vco),
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
141 .clkr = {
142 .hw.init = &(struct clk_init_data){
143 .name = "cam_cc_pll1",
144 .parent_data = &(const struct clk_parent_data){
145 .fw_name = "bi_tcxo",
146 },
147 .num_parents = 1,
148 .ops = &clk_alpha_pll_lucid_ops,
149 },
150 },
151 };
152
153 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
154 { 0x1, 2 },
155 { }
156 };
157
158 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
159 .offset = 0x1000,
160 .post_div_shift = 8,
161 .post_div_table = post_div_table_cam_cc_pll1_out_even,
162 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
163 .width = 4,
164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
165 .clkr.hw.init = &(struct clk_init_data){
166 .name = "cam_cc_pll1_out_even",
167 .parent_hws = (const struct clk_hw*[]) {
168 &cam_cc_pll1.clkr.hw,
169 },
170 .num_parents = 1,
171 .flags = CLK_SET_RATE_PARENT,
172 .ops = &clk_alpha_pll_postdiv_lucid_ops,
173 },
174 };
175
176 /* 1440MHz Configuration */
177 static const struct alpha_pll_config cam_cc_pll2_config = {
178 .l = 0x4B,
179 .alpha = 0x0,
180 .config_ctl_val = 0x08200800,
181 .config_ctl_hi_val = 0x05022011,
182 .config_ctl_hi1_val = 0x08000000,
183 .user_ctl_val = 0x00000301,
184 };
185
186 static struct clk_alpha_pll cam_cc_pll2 = {
187 .offset = 0x2000,
188 .vco_table = zonda_vco,
189 .num_vco = ARRAY_SIZE(zonda_vco),
190 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
191 .clkr = {
192 .hw.init = &(struct clk_init_data){
193 .name = "cam_cc_pll2",
194 .parent_data = &(const struct clk_parent_data){
195 .fw_name = "bi_tcxo",
196 },
197 .num_parents = 1,
198 .ops = &clk_alpha_pll_zonda_ops,
199 },
200 },
201 };
202
203 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = {
204 { 0x3, 4 },
205 { }
206 };
207
208 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
209 .offset = 0x2000,
210 .post_div_shift = 8,
211 .post_div_table = post_div_table_cam_cc_pll2_out_aux,
212 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux),
213 .width = 2,
214 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
215 .clkr.hw.init = &(struct clk_init_data){
216 .name = "cam_cc_pll2_out_aux",
217 .parent_hws = (const struct clk_hw*[]) {
218 &cam_cc_pll2.clkr.hw,
219 },
220 .num_parents = 1,
221 .flags = CLK_SET_RATE_PARENT,
222 .ops = &clk_alpha_pll_postdiv_zonda_ops,
223 },
224 };
225
226 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = {
227 { 0x3, 4 },
228 { }
229 };
230
231 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = {
232 .offset = 0x2000,
233 .post_div_shift = 8,
234 .post_div_table = post_div_table_cam_cc_pll2_out_aux2,
235 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2),
236 .width = 2,
237 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
238 .clkr.hw.init = &(struct clk_init_data){
239 .name = "cam_cc_pll2_out_aux2",
240 .parent_hws = (const struct clk_hw*[]) {
241 &cam_cc_pll2.clkr.hw,
242 },
243 .num_parents = 1,
244 .flags = CLK_SET_RATE_PARENT,
245 .ops = &clk_alpha_pll_postdiv_zonda_ops,
246 },
247 };
248
249 /* 760MHz Configuration */
250 static const struct alpha_pll_config cam_cc_pll3_config = {
251 .l = 0x27,
252 .alpha = 0x9555,
253 .config_ctl_val = 0x20485699,
254 .config_ctl_hi_val = 0x00002261,
255 .config_ctl_hi1_val = 0x329A299C,
256 .user_ctl_val = 0x00000101,
257 .user_ctl_hi_val = 0x00000805,
258 .user_ctl_hi1_val = 0x00000000,
259 };
260
261 static struct clk_alpha_pll cam_cc_pll3 = {
262 .offset = 0x3000,
263 .vco_table = lucid_vco,
264 .num_vco = ARRAY_SIZE(lucid_vco),
265 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
266 .clkr = {
267 .hw.init = &(struct clk_init_data){
268 .name = "cam_cc_pll3",
269 .parent_data = &(const struct clk_parent_data){
270 .fw_name = "bi_tcxo",
271 },
272 .num_parents = 1,
273 .ops = &clk_alpha_pll_lucid_ops,
274 },
275 },
276 };
277
278 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
279 { 0x1, 2 },
280 { }
281 };
282
283 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
284 .offset = 0x3000,
285 .post_div_shift = 8,
286 .post_div_table = post_div_table_cam_cc_pll3_out_even,
287 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
288 .width = 4,
289 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
290 .clkr.hw.init = &(struct clk_init_data){
291 .name = "cam_cc_pll3_out_even",
292 .parent_hws = (const struct clk_hw*[]) {
293 &cam_cc_pll3.clkr.hw,
294 },
295 .num_parents = 1,
296 .flags = CLK_SET_RATE_PARENT,
297 .ops = &clk_alpha_pll_postdiv_lucid_ops,
298 },
299 };
300
301 /* 760MHz Configuration */
302 static const struct alpha_pll_config cam_cc_pll4_config = {
303 .l = 0x27,
304 .alpha = 0x9555,
305 .config_ctl_val = 0x20485699,
306 .config_ctl_hi_val = 0x00002261,
307 .config_ctl_hi1_val = 0x329A299C,
308 .user_ctl_val = 0x00000101,
309 .user_ctl_hi_val = 0x00000805,
310 .user_ctl_hi1_val = 0x00000000,
311 };
312
313 static struct clk_alpha_pll cam_cc_pll4 = {
314 .offset = 0x4000,
315 .vco_table = lucid_vco,
316 .num_vco = ARRAY_SIZE(lucid_vco),
317 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
318 .clkr = {
319 .hw.init = &(struct clk_init_data){
320 .name = "cam_cc_pll4",
321 .parent_data = &(const struct clk_parent_data){
322 .fw_name = "bi_tcxo",
323 },
324 .num_parents = 1,
325 .ops = &clk_alpha_pll_lucid_ops,
326 },
327 },
328 };
329
330 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
331 { 0x1, 2 },
332 { }
333 };
334
335 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
336 .offset = 0x4000,
337 .post_div_shift = 8,
338 .post_div_table = post_div_table_cam_cc_pll4_out_even,
339 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
340 .width = 4,
341 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
342 .clkr.hw.init = &(struct clk_init_data){
343 .name = "cam_cc_pll4_out_even",
344 .parent_hws = (const struct clk_hw*[]) {
345 &cam_cc_pll4.clkr.hw,
346 },
347 .num_parents = 1,
348 .flags = CLK_SET_RATE_PARENT,
349 .ops = &clk_alpha_pll_postdiv_lucid_ops,
350 },
351 };
352
353 /* 760MHz Configuration */
354 static const struct alpha_pll_config cam_cc_pll5_config = {
355 .l = 0x27,
356 .alpha = 0x9555,
357 .config_ctl_val = 0x20485699,
358 .config_ctl_hi_val = 0x00002261,
359 .config_ctl_hi1_val = 0x329A299C,
360 .user_ctl_val = 0x00000101,
361 .user_ctl_hi_val = 0x00000805,
362 .user_ctl_hi1_val = 0x00000000,
363 };
364
365 static struct clk_alpha_pll cam_cc_pll5 = {
366 .offset = 0x5000,
367 .vco_table = lucid_vco,
368 .num_vco = ARRAY_SIZE(lucid_vco),
369 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
370 .clkr = {
371 .hw.init = &(struct clk_init_data){
372 .name = "cam_cc_pll5",
373 .parent_data = &(const struct clk_parent_data){
374 .fw_name = "bi_tcxo",
375 },
376 .num_parents = 1,
377 .ops = &clk_alpha_pll_lucid_ops,
378 },
379 },
380 };
381
382 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
383 { 0x1, 2 },
384 { }
385 };
386
387 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
388 .offset = 0x5000,
389 .post_div_shift = 8,
390 .post_div_table = post_div_table_cam_cc_pll5_out_even,
391 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
392 .width = 4,
393 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
394 .clkr.hw.init = &(struct clk_init_data){
395 .name = "cam_cc_pll5_out_even",
396 .parent_hws = (const struct clk_hw*[]) {
397 &cam_cc_pll5.clkr.hw,
398 },
399 .num_parents = 1,
400 .flags = CLK_SET_RATE_PARENT,
401 .ops = &clk_alpha_pll_postdiv_lucid_ops,
402 },
403 };
404
405 /* 960MHz Configuration */
406 static const struct alpha_pll_config cam_cc_pll6_config = {
407 .l = 0x32,
408 .alpha = 0x0,
409 .config_ctl_val = 0x20485699,
410 .config_ctl_hi_val = 0x00002261,
411 .config_ctl_hi1_val = 0x329A299C,
412 .user_ctl_val = 0x00003101,
413 .user_ctl_hi_val = 0x00000805,
414 .user_ctl_hi1_val = 0x00000000,
415 };
416
417 static struct clk_alpha_pll cam_cc_pll6 = {
418 .offset = 0x6000,
419 .vco_table = lucid_vco,
420 .num_vco = ARRAY_SIZE(lucid_vco),
421 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
422 .clkr = {
423 .hw.init = &(struct clk_init_data){
424 .name = "cam_cc_pll6",
425 .parent_data = &(const struct clk_parent_data){
426 .fw_name = "bi_tcxo",
427 },
428 .num_parents = 1,
429 .ops = &clk_alpha_pll_lucid_ops,
430 },
431 },
432 };
433
434 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
435 { 0x1, 2 },
436 { }
437 };
438
439 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
440 .offset = 0x6000,
441 .post_div_shift = 8,
442 .post_div_table = post_div_table_cam_cc_pll6_out_even,
443 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
444 .width = 4,
445 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
446 .clkr.hw.init = &(struct clk_init_data){
447 .name = "cam_cc_pll6_out_even",
448 .parent_hws = (const struct clk_hw*[]) {
449 &cam_cc_pll6.clkr.hw,
450 },
451 .num_parents = 1,
452 .flags = CLK_SET_RATE_PARENT,
453 .ops = &clk_alpha_pll_postdiv_lucid_ops,
454 },
455 };
456
457 static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = {
458 { 0x3, 3 },
459 { }
460 };
461
462 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = {
463 .offset = 0x6000,
464 .post_div_shift = 12,
465 .post_div_table = post_div_table_cam_cc_pll6_out_odd,
466 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd),
467 .width = 4,
468 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
469 .clkr.hw.init = &(struct clk_init_data){
470 .name = "cam_cc_pll6_out_odd",
471 .parent_hws = (const struct clk_hw*[]) {
472 &cam_cc_pll6.clkr.hw,
473 },
474 .num_parents = 1,
475 .flags = CLK_SET_RATE_PARENT,
476 .ops = &clk_alpha_pll_postdiv_lucid_ops,
477 },
478 };
479
480 static const struct parent_map cam_cc_parent_map_0[] = {
481 { P_BI_TCXO, 0 },
482 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
483 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
484 { P_CAM_CC_PLL0_OUT_ODD, 3 },
485 { P_CAM_CC_PLL6_OUT_EVEN, 5 },
486 };
487
488 static const struct clk_parent_data cam_cc_parent_data_0[] = {
489 { .fw_name = "bi_tcxo" },
490 { .hw = &cam_cc_pll0.clkr.hw },
491 { .hw = &cam_cc_pll0_out_even.clkr.hw },
492 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
493 { .hw = &cam_cc_pll6_out_even.clkr.hw },
494 };
495
496 static const struct parent_map cam_cc_parent_map_1[] = {
497 { P_BI_TCXO, 0 },
498 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
499 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
500 { P_CAM_CC_PLL0_OUT_ODD, 3 },
501 { P_CAM_CC_PLL6_OUT_MAIN, 4 },
502 { P_CAM_CC_PLL6_OUT_EVEN, 5 },
503 };
504
505 static const struct clk_parent_data cam_cc_parent_data_1[] = {
506 { .fw_name = "bi_tcxo" },
507 { .hw = &cam_cc_pll0.clkr.hw },
508 { .hw = &cam_cc_pll0_out_even.clkr.hw },
509 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
510 { .hw = &cam_cc_pll6.clkr.hw },
511 { .hw = &cam_cc_pll6_out_even.clkr.hw },
512 };
513
514 static const struct parent_map cam_cc_parent_map_2[] = {
515 { P_BI_TCXO, 0 },
516 { P_CAM_CC_PLL2_OUT_AUX2, 3 },
517 { P_CAM_CC_PLL2_OUT_EARLY, 5 },
518 };
519
520 static const struct clk_parent_data cam_cc_parent_data_2[] = {
521 { .fw_name = "bi_tcxo" },
522 { .hw = &cam_cc_pll2_out_aux2.clkr.hw },
523 { .hw = &cam_cc_pll2.clkr.hw },
524 };
525
526 static const struct parent_map cam_cc_parent_map_3[] = {
527 { P_BI_TCXO, 0 },
528 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
529 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
530 { P_CAM_CC_PLL0_OUT_ODD, 3 },
531 { P_CAM_CC_PLL6_OUT_EVEN, 5 },
532 { P_CAM_CC_PLL6_OUT_ODD, 6 },
533 };
534
535 static const struct clk_parent_data cam_cc_parent_data_3[] = {
536 { .fw_name = "bi_tcxo" },
537 { .hw = &cam_cc_pll0.clkr.hw },
538 { .hw = &cam_cc_pll0_out_even.clkr.hw },
539 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
540 { .hw = &cam_cc_pll6_out_even.clkr.hw },
541 { .hw = &cam_cc_pll6_out_odd.clkr.hw },
542 };
543
544 static const struct parent_map cam_cc_parent_map_4[] = {
545 { P_BI_TCXO, 0 },
546 { P_CAM_CC_PLL3_OUT_EVEN, 6 },
547 };
548
549 static const struct clk_parent_data cam_cc_parent_data_4[] = {
550 { .fw_name = "bi_tcxo" },
551 { .hw = &cam_cc_pll3_out_even.clkr.hw },
552 };
553
554 static const struct parent_map cam_cc_parent_map_5[] = {
555 { P_BI_TCXO, 0 },
556 { P_CAM_CC_PLL4_OUT_EVEN, 6 },
557 };
558
559 static const struct clk_parent_data cam_cc_parent_data_5[] = {
560 { .fw_name = "bi_tcxo" },
561 { .hw = &cam_cc_pll4_out_even.clkr.hw },
562 };
563
564 static const struct parent_map cam_cc_parent_map_6[] = {
565 { P_BI_TCXO, 0 },
566 { P_CAM_CC_PLL5_OUT_EVEN, 6 },
567 };
568
569 static const struct clk_parent_data cam_cc_parent_data_6[] = {
570 { .fw_name = "bi_tcxo" },
571 { .hw = &cam_cc_pll5_out_even.clkr.hw },
572 };
573
574 static const struct parent_map cam_cc_parent_map_7[] = {
575 { P_BI_TCXO, 0 },
576 { P_CAM_CC_PLL1_OUT_EVEN, 4 },
577 };
578
579 static const struct clk_parent_data cam_cc_parent_data_7[] = {
580 { .fw_name = "bi_tcxo" },
581 { .hw = &cam_cc_pll1_out_even.clkr.hw },
582 };
583
584 static const struct parent_map cam_cc_parent_map_8[] = {
585 { P_SLEEP_CLK, 0 },
586 };
587
588 static const struct clk_parent_data cam_cc_parent_data_8[] = {
589 { .fw_name = "sleep_clk" },
590 };
591
592 static const struct parent_map cam_cc_parent_map_9[] = {
593 { P_BI_TCXO, 0 },
594 };
595
596 static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
597 { .fw_name = "bi_tcxo_ao" },
598 };
599
600 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
601 F(19200000, P_BI_TCXO, 1, 0, 0),
602 F(100000000, P_CAM_CC_PLL0_OUT_ODD, 4, 0, 0),
603 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
604 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
605 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
606 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
607 { }
608 };
609
610 static struct clk_rcg2 cam_cc_bps_clk_src = {
611 .cmd_rcgr = 0x7010,
612 .mnd_width = 0,
613 .hid_width = 5,
614 .parent_map = cam_cc_parent_map_0,
615 .freq_tbl = ftbl_cam_cc_bps_clk_src,
616 .clkr.hw.init = &(struct clk_init_data){
617 .name = "cam_cc_bps_clk_src",
618 .parent_data = cam_cc_parent_data_0,
619 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
620 .ops = &clk_rcg2_shared_ops,
621 },
622 };
623
624 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
625 F(19200000, P_BI_TCXO, 1, 0, 0),
626 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
627 F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0),
628 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
629 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
630 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
631 { }
632 };
633
634 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
635 .cmd_rcgr = 0xc124,
636 .mnd_width = 0,
637 .hid_width = 5,
638 .parent_map = cam_cc_parent_map_3,
639 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
640 .clkr.hw.init = &(struct clk_init_data){
641 .name = "cam_cc_camnoc_axi_clk_src",
642 .parent_data = cam_cc_parent_data_3,
643 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
644 .ops = &clk_rcg2_shared_ops,
645 },
646 };
647
648 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
649 F(19200000, P_BI_TCXO, 1, 0, 0),
650 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
651 { }
652 };
653
654 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
655 .cmd_rcgr = 0xc0e0,
656 .mnd_width = 8,
657 .hid_width = 5,
658 .parent_map = cam_cc_parent_map_0,
659 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
660 .clkr.hw.init = &(struct clk_init_data){
661 .name = "cam_cc_cci_0_clk_src",
662 .parent_data = cam_cc_parent_data_0,
663 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
664 .ops = &clk_rcg2_shared_ops,
665 },
666 };
667
668 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
669 .cmd_rcgr = 0xc0fc,
670 .mnd_width = 8,
671 .hid_width = 5,
672 .parent_map = cam_cc_parent_map_0,
673 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
674 .clkr.hw.init = &(struct clk_init_data){
675 .name = "cam_cc_cci_1_clk_src",
676 .parent_data = cam_cc_parent_data_0,
677 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
678 .ops = &clk_rcg2_shared_ops,
679 },
680 };
681
682 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
683 F(19200000, P_BI_TCXO, 1, 0, 0),
684 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
685 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
686 { }
687 };
688
689 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
690 .cmd_rcgr = 0xa064,
691 .mnd_width = 0,
692 .hid_width = 5,
693 .parent_map = cam_cc_parent_map_1,
694 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
695 .clkr.hw.init = &(struct clk_init_data){
696 .name = "cam_cc_cphy_rx_clk_src",
697 .parent_data = cam_cc_parent_data_1,
698 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
699 .ops = &clk_rcg2_shared_ops,
700 },
701 };
702
703 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
704 F(19200000, P_BI_TCXO, 1, 0, 0),
705 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
706 { }
707 };
708
709 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
710 .cmd_rcgr = 0xe0ac,
711 .mnd_width = 0,
712 .hid_width = 5,
713 .parent_map = cam_cc_parent_map_0,
714 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "cam_cc_csi0phytimer_clk_src",
717 .parent_data = cam_cc_parent_data_0,
718 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
719 .ops = &clk_rcg2_shared_ops,
720 },
721 };
722
723 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
724 .cmd_rcgr = 0xe0d0,
725 .mnd_width = 0,
726 .hid_width = 5,
727 .parent_map = cam_cc_parent_map_0,
728 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "cam_cc_csi1phytimer_clk_src",
731 .parent_data = cam_cc_parent_data_0,
732 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
733 .ops = &clk_rcg2_shared_ops,
734 },
735 };
736
737 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
738 .cmd_rcgr = 0xe0f4,
739 .mnd_width = 0,
740 .hid_width = 5,
741 .parent_map = cam_cc_parent_map_0,
742 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "cam_cc_csi2phytimer_clk_src",
745 .parent_data = cam_cc_parent_data_0,
746 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
747 .ops = &clk_rcg2_shared_ops,
748 },
749 };
750
751 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
752 .cmd_rcgr = 0xe11c,
753 .mnd_width = 0,
754 .hid_width = 5,
755 .parent_map = cam_cc_parent_map_0,
756 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
757 .clkr.hw.init = &(struct clk_init_data){
758 .name = "cam_cc_csi3phytimer_clk_src",
759 .parent_data = cam_cc_parent_data_0,
760 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
761 .ops = &clk_rcg2_shared_ops,
762 },
763 };
764
765 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
766 .cmd_rcgr = 0xe140,
767 .mnd_width = 0,
768 .hid_width = 5,
769 .parent_map = cam_cc_parent_map_0,
770 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
771 .clkr.hw.init = &(struct clk_init_data){
772 .name = "cam_cc_csi4phytimer_clk_src",
773 .parent_data = cam_cc_parent_data_0,
774 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
775 .ops = &clk_rcg2_shared_ops,
776 },
777 };
778
779 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
780 F(19200000, P_BI_TCXO, 1, 0, 0),
781 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
782 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
783 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
784 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
785 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
786 { }
787 };
788
789 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
790 .cmd_rcgr = 0x703c,
791 .mnd_width = 0,
792 .hid_width = 5,
793 .parent_map = cam_cc_parent_map_0,
794 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
795 .clkr.hw.init = &(struct clk_init_data){
796 .name = "cam_cc_fast_ahb_clk_src",
797 .parent_data = cam_cc_parent_data_0,
798 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
799 .ops = &clk_rcg2_shared_ops,
800 },
801 };
802
803 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
804 F(19200000, P_BI_TCXO, 1, 0, 0),
805 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
806 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
807 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
808 { }
809 };
810
811 static struct clk_rcg2 cam_cc_icp_clk_src = {
812 .cmd_rcgr = 0xc0b8,
813 .mnd_width = 0,
814 .hid_width = 5,
815 .parent_map = cam_cc_parent_map_0,
816 .freq_tbl = ftbl_cam_cc_icp_clk_src,
817 .clkr.hw.init = &(struct clk_init_data){
818 .name = "cam_cc_icp_clk_src",
819 .parent_data = cam_cc_parent_data_0,
820 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
821 .ops = &clk_rcg2_shared_ops,
822 },
823 };
824
825 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
826 F(19200000, P_BI_TCXO, 1, 0, 0),
827 F(380000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
828 F(510000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
829 F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
830 F(760000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
831 { }
832 };
833
834 static struct clk_rcg2 cam_cc_ife_0_clk_src = {
835 .cmd_rcgr = 0xa010,
836 .mnd_width = 0,
837 .hid_width = 5,
838 .parent_map = cam_cc_parent_map_4,
839 .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
840 .clkr.hw.init = &(struct clk_init_data){
841 .name = "cam_cc_ife_0_clk_src",
842 .parent_data = cam_cc_parent_data_4,
843 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
844 .flags = CLK_SET_RATE_PARENT,
845 .ops = &clk_rcg2_shared_ops,
846 },
847 };
848
849 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
850 F(19200000, P_BI_TCXO, 1, 0, 0),
851 F(380000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
852 F(510000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
853 F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
854 F(760000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
855 { }
856 };
857
858 static struct clk_rcg2 cam_cc_ife_1_clk_src = {
859 .cmd_rcgr = 0xb010,
860 .mnd_width = 0,
861 .hid_width = 5,
862 .parent_map = cam_cc_parent_map_5,
863 .freq_tbl = ftbl_cam_cc_ife_1_clk_src,
864 .clkr.hw.init = &(struct clk_init_data){
865 .name = "cam_cc_ife_1_clk_src",
866 .parent_data = cam_cc_parent_data_5,
867 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
868 .flags = CLK_SET_RATE_PARENT,
869 .ops = &clk_rcg2_shared_ops,
870 },
871 };
872
873 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
874 F(19200000, P_BI_TCXO, 1, 0, 0),
875 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
876 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
877 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
878 { }
879 };
880
881 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
882 .cmd_rcgr = 0xa03c,
883 .mnd_width = 0,
884 .hid_width = 5,
885 .parent_map = cam_cc_parent_map_1,
886 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
887 .clkr.hw.init = &(struct clk_init_data){
888 .name = "cam_cc_ife_0_csid_clk_src",
889 .parent_data = cam_cc_parent_data_1,
890 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
891 .ops = &clk_rcg2_shared_ops,
892 },
893 };
894
895 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
896 .cmd_rcgr = 0xb03c,
897 .mnd_width = 0,
898 .hid_width = 5,
899 .parent_map = cam_cc_parent_map_1,
900 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "cam_cc_ife_1_csid_clk_src",
903 .parent_data = cam_cc_parent_data_1,
904 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
905 .ops = &clk_rcg2_shared_ops,
906 },
907 };
908
909 static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
910 F(19200000, P_BI_TCXO, 1, 0, 0),
911 F(380000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
912 F(510000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
913 F(637000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
914 F(760000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
915 { }
916 };
917
918 static struct clk_rcg2 cam_cc_ife_2_clk_src = {
919 .cmd_rcgr = 0xb07c,
920 .mnd_width = 0,
921 .hid_width = 5,
922 .parent_map = cam_cc_parent_map_6,
923 .freq_tbl = ftbl_cam_cc_ife_2_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "cam_cc_ife_2_clk_src",
926 .parent_data = cam_cc_parent_data_6,
927 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
928 .flags = CLK_SET_RATE_PARENT,
929 .ops = &clk_rcg2_shared_ops,
930 },
931 };
932
933 static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = {
934 .cmd_rcgr = 0xb0a8,
935 .mnd_width = 0,
936 .hid_width = 5,
937 .parent_map = cam_cc_parent_map_1,
938 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "cam_cc_ife_2_csid_clk_src",
941 .parent_data = cam_cc_parent_data_1,
942 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
943 .ops = &clk_rcg2_shared_ops,
944 },
945 };
946
947 static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = {
948 F(19200000, P_BI_TCXO, 1, 0, 0),
949 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
950 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
951 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
952 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
953 { }
954 };
955
956 static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = {
957 .cmd_rcgr = 0xc004,
958 .mnd_width = 0,
959 .hid_width = 5,
960 .parent_map = cam_cc_parent_map_3,
961 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
962 .clkr.hw.init = &(struct clk_init_data){
963 .name = "cam_cc_ife_lite_0_clk_src",
964 .parent_data = cam_cc_parent_data_3,
965 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
966 .ops = &clk_rcg2_shared_ops,
967 },
968 };
969
970 static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = {
971 .cmd_rcgr = 0xc020,
972 .mnd_width = 0,
973 .hid_width = 5,
974 .parent_map = cam_cc_parent_map_1,
975 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "cam_cc_ife_lite_0_csid_clk_src",
978 .parent_data = cam_cc_parent_data_1,
979 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
980 .ops = &clk_rcg2_shared_ops,
981 },
982 };
983
984 static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = {
985 .cmd_rcgr = 0xc048,
986 .mnd_width = 0,
987 .hid_width = 5,
988 .parent_map = cam_cc_parent_map_3,
989 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
990 .clkr.hw.init = &(struct clk_init_data){
991 .name = "cam_cc_ife_lite_1_clk_src",
992 .parent_data = cam_cc_parent_data_3,
993 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
994 .ops = &clk_rcg2_shared_ops,
995 },
996 };
997
998 static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = {
999 .cmd_rcgr = 0xc064,
1000 .mnd_width = 0,
1001 .hid_width = 5,
1002 .parent_map = cam_cc_parent_map_1,
1003 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "cam_cc_ife_lite_1_csid_clk_src",
1006 .parent_data = cam_cc_parent_data_1,
1007 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1008 .ops = &clk_rcg2_shared_ops,
1009 },
1010 };
1011
1012 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
1013 F(19200000, P_BI_TCXO, 1, 0, 0),
1014 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1015 F(430000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1016 F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1017 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1018 { }
1019 };
1020
1021 static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
1022 .cmd_rcgr = 0x8010,
1023 .mnd_width = 0,
1024 .hid_width = 5,
1025 .parent_map = cam_cc_parent_map_7,
1026 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
1027 .clkr.hw.init = &(struct clk_init_data){
1028 .name = "cam_cc_ipe_0_clk_src",
1029 .parent_data = cam_cc_parent_data_7,
1030 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1031 .flags = CLK_SET_RATE_PARENT,
1032 .ops = &clk_rcg2_shared_ops,
1033 },
1034 };
1035
1036 static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1037 .cmd_rcgr = 0xc08c,
1038 .mnd_width = 0,
1039 .hid_width = 5,
1040 .parent_map = cam_cc_parent_map_0,
1041 .freq_tbl = ftbl_cam_cc_bps_clk_src,
1042 .clkr.hw.init = &(struct clk_init_data){
1043 .name = "cam_cc_jpeg_clk_src",
1044 .parent_data = cam_cc_parent_data_0,
1045 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1046 .ops = &clk_rcg2_shared_ops,
1047 },
1048 };
1049
1050 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
1051 F(19200000, P_BI_TCXO, 1, 0, 0),
1052 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
1053 F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0),
1054 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
1055 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
1056 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1057 { }
1058 };
1059
1060 static struct clk_rcg2 cam_cc_lrme_clk_src = {
1061 .cmd_rcgr = 0xc150,
1062 .mnd_width = 0,
1063 .hid_width = 5,
1064 .parent_map = cam_cc_parent_map_3,
1065 .freq_tbl = ftbl_cam_cc_lrme_clk_src,
1066 .clkr.hw.init = &(struct clk_init_data){
1067 .name = "cam_cc_lrme_clk_src",
1068 .parent_data = cam_cc_parent_data_3,
1069 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1070 .ops = &clk_rcg2_shared_ops,
1071 },
1072 };
1073
1074 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1075 F(19200000, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 75),
1076 F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6),
1077 F(34285714, P_CAM_CC_PLL2_OUT_EARLY, 2, 1, 21),
1078 { }
1079 };
1080
1081 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1082 .cmd_rcgr = 0xe000,
1083 .mnd_width = 8,
1084 .hid_width = 5,
1085 .parent_map = cam_cc_parent_map_2,
1086 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1087 .clkr.hw.init = &(struct clk_init_data){
1088 .name = "cam_cc_mclk0_clk_src",
1089 .parent_data = cam_cc_parent_data_2,
1090 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1091 .ops = &clk_rcg2_shared_ops,
1092 },
1093 };
1094
1095 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1096 .cmd_rcgr = 0xe01c,
1097 .mnd_width = 8,
1098 .hid_width = 5,
1099 .parent_map = cam_cc_parent_map_2,
1100 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1101 .clkr.hw.init = &(struct clk_init_data){
1102 .name = "cam_cc_mclk1_clk_src",
1103 .parent_data = cam_cc_parent_data_2,
1104 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1105 .ops = &clk_rcg2_shared_ops,
1106 },
1107 };
1108
1109 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1110 .cmd_rcgr = 0xe038,
1111 .mnd_width = 8,
1112 .hid_width = 5,
1113 .parent_map = cam_cc_parent_map_2,
1114 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1115 .clkr.hw.init = &(struct clk_init_data){
1116 .name = "cam_cc_mclk2_clk_src",
1117 .parent_data = cam_cc_parent_data_2,
1118 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1119 .ops = &clk_rcg2_shared_ops,
1120 },
1121 };
1122
1123 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1124 .cmd_rcgr = 0xe054,
1125 .mnd_width = 8,
1126 .hid_width = 5,
1127 .parent_map = cam_cc_parent_map_2,
1128 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1129 .clkr.hw.init = &(struct clk_init_data){
1130 .name = "cam_cc_mclk3_clk_src",
1131 .parent_data = cam_cc_parent_data_2,
1132 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1133 .ops = &clk_rcg2_shared_ops,
1134 },
1135 };
1136
1137 static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1138 .cmd_rcgr = 0xe070,
1139 .mnd_width = 8,
1140 .hid_width = 5,
1141 .parent_map = cam_cc_parent_map_2,
1142 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1143 .clkr.hw.init = &(struct clk_init_data){
1144 .name = "cam_cc_mclk4_clk_src",
1145 .parent_data = cam_cc_parent_data_2,
1146 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1147 .ops = &clk_rcg2_shared_ops,
1148 },
1149 };
1150
1151 static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1152 .cmd_rcgr = 0xe08c,
1153 .mnd_width = 8,
1154 .hid_width = 5,
1155 .parent_map = cam_cc_parent_map_2,
1156 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1157 .clkr.hw.init = &(struct clk_init_data){
1158 .name = "cam_cc_mclk5_clk_src",
1159 .parent_data = cam_cc_parent_data_2,
1160 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1161 .ops = &clk_rcg2_shared_ops,
1162 },
1163 };
1164
1165 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1166 F(32000, P_SLEEP_CLK, 1, 0, 0),
1167 { }
1168 };
1169
1170 static struct clk_rcg2 cam_cc_sleep_clk_src = {
1171 .cmd_rcgr = 0xc1c0,
1172 .mnd_width = 0,
1173 .hid_width = 5,
1174 .parent_map = cam_cc_parent_map_8,
1175 .freq_tbl = ftbl_cam_cc_sleep_clk_src,
1176 .clkr.hw.init = &(struct clk_init_data){
1177 .name = "cam_cc_sleep_clk_src",
1178 .parent_data = cam_cc_parent_data_8,
1179 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1180 .ops = &clk_rcg2_ops,
1181 },
1182 };
1183
1184 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1185 F(19200000, P_BI_TCXO, 1, 0, 0),
1186 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1187 { }
1188 };
1189
1190 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1191 .cmd_rcgr = 0x7058,
1192 .mnd_width = 8,
1193 .hid_width = 5,
1194 .parent_map = cam_cc_parent_map_0,
1195 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1196 .clkr.hw.init = &(struct clk_init_data){
1197 .name = "cam_cc_slow_ahb_clk_src",
1198 .parent_data = cam_cc_parent_data_0,
1199 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1200 .ops = &clk_rcg2_shared_ops,
1201 },
1202 };
1203
1204 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1205 F(19200000, P_BI_TCXO, 1, 0, 0),
1206 { }
1207 };
1208
1209 static struct clk_rcg2 cam_cc_xo_clk_src = {
1210 .cmd_rcgr = 0xc1a4,
1211 .mnd_width = 0,
1212 .hid_width = 5,
1213 .parent_map = cam_cc_parent_map_9,
1214 .freq_tbl = ftbl_cam_cc_xo_clk_src,
1215 .clkr.hw.init = &(struct clk_init_data){
1216 .name = "cam_cc_xo_clk_src",
1217 .parent_data = cam_cc_parent_data_9_ao,
1218 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
1219 .ops = &clk_rcg2_ops,
1220 },
1221 };
1222
1223 static struct clk_branch cam_cc_bps_ahb_clk = {
1224 .halt_reg = 0x7070,
1225 .halt_check = BRANCH_HALT,
1226 .clkr = {
1227 .enable_reg = 0x7070,
1228 .enable_mask = BIT(0),
1229 .hw.init = &(struct clk_init_data){
1230 .name = "cam_cc_bps_ahb_clk",
1231 .parent_hws = (const struct clk_hw*[]) {
1232 &cam_cc_slow_ahb_clk_src.clkr.hw,
1233 },
1234 .num_parents = 1,
1235 .flags = CLK_SET_RATE_PARENT,
1236 .ops = &clk_branch2_ops,
1237 },
1238 },
1239 };
1240
1241 static struct clk_branch cam_cc_bps_areg_clk = {
1242 .halt_reg = 0x7054,
1243 .halt_check = BRANCH_HALT,
1244 .clkr = {
1245 .enable_reg = 0x7054,
1246 .enable_mask = BIT(0),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "cam_cc_bps_areg_clk",
1249 .parent_hws = (const struct clk_hw*[]) {
1250 &cam_cc_fast_ahb_clk_src.clkr.hw,
1251 },
1252 .num_parents = 1,
1253 .flags = CLK_SET_RATE_PARENT,
1254 .ops = &clk_branch2_ops,
1255 },
1256 },
1257 };
1258
1259 static struct clk_branch cam_cc_bps_axi_clk = {
1260 .halt_reg = 0x7038,
1261 .halt_check = BRANCH_HALT,
1262 .clkr = {
1263 .enable_reg = 0x7038,
1264 .enable_mask = BIT(0),
1265 .hw.init = &(struct clk_init_data){
1266 .name = "cam_cc_bps_axi_clk",
1267 .parent_hws = (const struct clk_hw*[]) {
1268 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1269 },
1270 .num_parents = 1,
1271 .flags = CLK_SET_RATE_PARENT,
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275 };
1276
1277 static struct clk_branch cam_cc_bps_clk = {
1278 .halt_reg = 0x7028,
1279 .halt_check = BRANCH_HALT,
1280 .clkr = {
1281 .enable_reg = 0x7028,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "cam_cc_bps_clk",
1285 .parent_hws = (const struct clk_hw*[]) {
1286 &cam_cc_bps_clk_src.clkr.hw,
1287 },
1288 .num_parents = 1,
1289 .flags = CLK_SET_RATE_PARENT,
1290 .ops = &clk_branch2_ops,
1291 },
1292 },
1293 };
1294
1295 static struct clk_branch cam_cc_camnoc_axi_clk = {
1296 .halt_reg = 0xc140,
1297 .halt_check = BRANCH_HALT,
1298 .clkr = {
1299 .enable_reg = 0xc140,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "cam_cc_camnoc_axi_clk",
1303 .parent_hws = (const struct clk_hw*[]) {
1304 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1305 },
1306 .num_parents = 1,
1307 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops,
1309 },
1310 },
1311 };
1312
1313 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1314 .halt_reg = 0xc148,
1315 .halt_check = BRANCH_HALT,
1316 .clkr = {
1317 .enable_reg = 0xc148,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "cam_cc_camnoc_dcd_xo_clk",
1321 .parent_hws = (const struct clk_hw*[]) {
1322 &cam_cc_xo_clk_src.clkr.hw,
1323 },
1324 .num_parents = 1,
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1327 },
1328 },
1329 };
1330
1331 static struct clk_branch cam_cc_cci_0_clk = {
1332 .halt_reg = 0xc0f8,
1333 .halt_check = BRANCH_HALT,
1334 .clkr = {
1335 .enable_reg = 0xc0f8,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "cam_cc_cci_0_clk",
1339 .parent_hws = (const struct clk_hw*[]) {
1340 &cam_cc_cci_0_clk_src.clkr.hw,
1341 },
1342 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1345 },
1346 },
1347 };
1348
1349 static struct clk_branch cam_cc_cci_1_clk = {
1350 .halt_reg = 0xc114,
1351 .halt_check = BRANCH_HALT,
1352 .clkr = {
1353 .enable_reg = 0xc114,
1354 .enable_mask = BIT(0),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "cam_cc_cci_1_clk",
1357 .parent_hws = (const struct clk_hw*[]) {
1358 &cam_cc_cci_1_clk_src.clkr.hw,
1359 },
1360 .num_parents = 1,
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1363 },
1364 },
1365 };
1366
1367 static struct clk_branch cam_cc_core_ahb_clk = {
1368 .halt_reg = 0xc1a0,
1369 .halt_check = BRANCH_HALT_DELAY,
1370 .clkr = {
1371 .enable_reg = 0xc1a0,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "cam_cc_core_ahb_clk",
1375 .parent_hws = (const struct clk_hw*[]) {
1376 &cam_cc_slow_ahb_clk_src.clkr.hw,
1377 },
1378 .num_parents = 1,
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1381 },
1382 },
1383 };
1384
1385 static struct clk_branch cam_cc_cpas_ahb_clk = {
1386 .halt_reg = 0xc11c,
1387 .halt_check = BRANCH_HALT,
1388 .clkr = {
1389 .enable_reg = 0xc11c,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "cam_cc_cpas_ahb_clk",
1393 .parent_hws = (const struct clk_hw*[]) {
1394 &cam_cc_slow_ahb_clk_src.clkr.hw,
1395 },
1396 .num_parents = 1,
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1399 },
1400 },
1401 };
1402
1403 static struct clk_branch cam_cc_csi0phytimer_clk = {
1404 .halt_reg = 0xe0c4,
1405 .halt_check = BRANCH_HALT,
1406 .clkr = {
1407 .enable_reg = 0xe0c4,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "cam_cc_csi0phytimer_clk",
1411 .parent_hws = (const struct clk_hw*[]) {
1412 &cam_cc_csi0phytimer_clk_src.clkr.hw,
1413 },
1414 .num_parents = 1,
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419 };
1420
1421 static struct clk_branch cam_cc_csi1phytimer_clk = {
1422 .halt_reg = 0xe0e8,
1423 .halt_check = BRANCH_HALT,
1424 .clkr = {
1425 .enable_reg = 0xe0e8,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "cam_cc_csi1phytimer_clk",
1429 .parent_hws = (const struct clk_hw*[]) {
1430 &cam_cc_csi1phytimer_clk_src.clkr.hw,
1431 },
1432 .num_parents = 1,
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1435 },
1436 },
1437 };
1438
1439 static struct clk_branch cam_cc_csi2phytimer_clk = {
1440 .halt_reg = 0xe10c,
1441 .halt_check = BRANCH_HALT,
1442 .clkr = {
1443 .enable_reg = 0xe10c,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "cam_cc_csi2phytimer_clk",
1447 .parent_hws = (const struct clk_hw*[]) {
1448 &cam_cc_csi2phytimer_clk_src.clkr.hw,
1449 },
1450 .num_parents = 1,
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1453 },
1454 },
1455 };
1456
1457 static struct clk_branch cam_cc_csi3phytimer_clk = {
1458 .halt_reg = 0xe134,
1459 .halt_check = BRANCH_HALT,
1460 .clkr = {
1461 .enable_reg = 0xe134,
1462 .enable_mask = BIT(0),
1463 .hw.init = &(struct clk_init_data){
1464 .name = "cam_cc_csi3phytimer_clk",
1465 .parent_hws = (const struct clk_hw*[]) {
1466 &cam_cc_csi3phytimer_clk_src.clkr.hw,
1467 },
1468 .num_parents = 1,
1469 .flags = CLK_SET_RATE_PARENT,
1470 .ops = &clk_branch2_ops,
1471 },
1472 },
1473 };
1474
1475 static struct clk_branch cam_cc_csi4phytimer_clk = {
1476 .halt_reg = 0xe158,
1477 .halt_check = BRANCH_HALT,
1478 .clkr = {
1479 .enable_reg = 0xe158,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "cam_cc_csi4phytimer_clk",
1483 .parent_hws = (const struct clk_hw*[]) {
1484 &cam_cc_csi4phytimer_clk_src.clkr.hw,
1485 },
1486 .num_parents = 1,
1487 .flags = CLK_SET_RATE_PARENT,
1488 .ops = &clk_branch2_ops,
1489 },
1490 },
1491 };
1492
1493 static struct clk_branch cam_cc_csiphy0_clk = {
1494 .halt_reg = 0xe0c8,
1495 .halt_check = BRANCH_HALT,
1496 .clkr = {
1497 .enable_reg = 0xe0c8,
1498 .enable_mask = BIT(0),
1499 .hw.init = &(struct clk_init_data){
1500 .name = "cam_cc_csiphy0_clk",
1501 .parent_hws = (const struct clk_hw*[]) {
1502 &cam_cc_cphy_rx_clk_src.clkr.hw,
1503 },
1504 .num_parents = 1,
1505 .flags = CLK_SET_RATE_PARENT,
1506 .ops = &clk_branch2_ops,
1507 },
1508 },
1509 };
1510
1511 static struct clk_branch cam_cc_csiphy1_clk = {
1512 .halt_reg = 0xe0ec,
1513 .halt_check = BRANCH_HALT,
1514 .clkr = {
1515 .enable_reg = 0xe0ec,
1516 .enable_mask = BIT(0),
1517 .hw.init = &(struct clk_init_data){
1518 .name = "cam_cc_csiphy1_clk",
1519 .parent_hws = (const struct clk_hw*[]) {
1520 &cam_cc_cphy_rx_clk_src.clkr.hw,
1521 },
1522 .num_parents = 1,
1523 .flags = CLK_SET_RATE_PARENT,
1524 .ops = &clk_branch2_ops,
1525 },
1526 },
1527 };
1528
1529 static struct clk_branch cam_cc_csiphy2_clk = {
1530 .halt_reg = 0xe110,
1531 .halt_check = BRANCH_HALT,
1532 .clkr = {
1533 .enable_reg = 0xe110,
1534 .enable_mask = BIT(0),
1535 .hw.init = &(struct clk_init_data){
1536 .name = "cam_cc_csiphy2_clk",
1537 .parent_hws = (const struct clk_hw*[]) {
1538 &cam_cc_cphy_rx_clk_src.clkr.hw,
1539 },
1540 .num_parents = 1,
1541 .flags = CLK_SET_RATE_PARENT,
1542 .ops = &clk_branch2_ops,
1543 },
1544 },
1545 };
1546
1547 static struct clk_branch cam_cc_csiphy3_clk = {
1548 .halt_reg = 0xe138,
1549 .halt_check = BRANCH_HALT,
1550 .clkr = {
1551 .enable_reg = 0xe138,
1552 .enable_mask = BIT(0),
1553 .hw.init = &(struct clk_init_data){
1554 .name = "cam_cc_csiphy3_clk",
1555 .parent_hws = (const struct clk_hw*[]) {
1556 &cam_cc_cphy_rx_clk_src.clkr.hw,
1557 },
1558 .num_parents = 1,
1559 .flags = CLK_SET_RATE_PARENT,
1560 .ops = &clk_branch2_ops,
1561 },
1562 },
1563 };
1564
1565 static struct clk_branch cam_cc_csiphy4_clk = {
1566 .halt_reg = 0xe15c,
1567 .halt_check = BRANCH_HALT,
1568 .clkr = {
1569 .enable_reg = 0xe15c,
1570 .enable_mask = BIT(0),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "cam_cc_csiphy4_clk",
1573 .parent_hws = (const struct clk_hw*[]) {
1574 &cam_cc_cphy_rx_clk_src.clkr.hw,
1575 },
1576 .num_parents = 1,
1577 .flags = CLK_SET_RATE_PARENT,
1578 .ops = &clk_branch2_ops,
1579 },
1580 },
1581 };
1582
1583 static struct clk_branch cam_cc_gdsc_clk = {
1584 .halt_reg = 0xc1bc,
1585 .halt_check = BRANCH_HALT,
1586 .clkr = {
1587 .enable_reg = 0xc1bc,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "cam_cc_gdsc_clk",
1591 .parent_hws = (const struct clk_hw*[]) {
1592 &cam_cc_xo_clk_src.clkr.hw,
1593 },
1594 .num_parents = 1,
1595 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1596 .ops = &clk_branch2_ops,
1597 },
1598 },
1599 };
1600
1601 static struct clk_branch cam_cc_icp_ahb_clk = {
1602 .halt_reg = 0xc0d8,
1603 .halt_check = BRANCH_HALT,
1604 .clkr = {
1605 .enable_reg = 0xc0d8,
1606 .enable_mask = BIT(0),
1607 .hw.init = &(struct clk_init_data){
1608 .name = "cam_cc_icp_ahb_clk",
1609 .parent_hws = (const struct clk_hw*[]) {
1610 &cam_cc_slow_ahb_clk_src.clkr.hw,
1611 },
1612 .num_parents = 1,
1613 .flags = CLK_SET_RATE_PARENT,
1614 .ops = &clk_branch2_ops,
1615 },
1616 },
1617 };
1618
1619 static struct clk_branch cam_cc_icp_clk = {
1620 .halt_reg = 0xc0d0,
1621 .halt_check = BRANCH_HALT,
1622 .clkr = {
1623 .enable_reg = 0xc0d0,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "cam_cc_icp_clk",
1627 .parent_hws = (const struct clk_hw*[]) {
1628 &cam_cc_icp_clk_src.clkr.hw,
1629 },
1630 .num_parents = 1,
1631 .flags = CLK_SET_RATE_PARENT,
1632 .ops = &clk_branch2_ops,
1633 },
1634 },
1635 };
1636
1637 static struct clk_branch cam_cc_ife_0_axi_clk = {
1638 .halt_reg = 0xa080,
1639 .halt_check = BRANCH_HALT,
1640 .clkr = {
1641 .enable_reg = 0xa080,
1642 .enable_mask = BIT(0),
1643 .hw.init = &(struct clk_init_data){
1644 .name = "cam_cc_ife_0_axi_clk",
1645 .parent_hws = (const struct clk_hw*[]) {
1646 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1647 },
1648 .num_parents = 1,
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1651 },
1652 },
1653 };
1654
1655 static struct clk_branch cam_cc_ife_0_clk = {
1656 .halt_reg = 0xa028,
1657 .halt_check = BRANCH_HALT,
1658 .clkr = {
1659 .enable_reg = 0xa028,
1660 .enable_mask = BIT(0),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "cam_cc_ife_0_clk",
1663 .parent_hws = (const struct clk_hw*[]) {
1664 &cam_cc_ife_0_clk_src.clkr.hw,
1665 },
1666 .num_parents = 1,
1667 .flags = CLK_SET_RATE_PARENT,
1668 .ops = &clk_branch2_ops,
1669 },
1670 },
1671 };
1672
1673 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1674 .halt_reg = 0xa07c,
1675 .halt_check = BRANCH_HALT,
1676 .clkr = {
1677 .enable_reg = 0xa07c,
1678 .enable_mask = BIT(0),
1679 .hw.init = &(struct clk_init_data){
1680 .name = "cam_cc_ife_0_cphy_rx_clk",
1681 .parent_hws = (const struct clk_hw*[]) {
1682 &cam_cc_cphy_rx_clk_src.clkr.hw,
1683 },
1684 .num_parents = 1,
1685 .flags = CLK_SET_RATE_PARENT,
1686 .ops = &clk_branch2_ops,
1687 },
1688 },
1689 };
1690
1691 static struct clk_branch cam_cc_ife_0_csid_clk = {
1692 .halt_reg = 0xa054,
1693 .halt_check = BRANCH_HALT,
1694 .clkr = {
1695 .enable_reg = 0xa054,
1696 .enable_mask = BIT(0),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "cam_cc_ife_0_csid_clk",
1699 .parent_hws = (const struct clk_hw*[]) {
1700 &cam_cc_ife_0_csid_clk_src.clkr.hw,
1701 },
1702 .num_parents = 1,
1703 .flags = CLK_SET_RATE_PARENT,
1704 .ops = &clk_branch2_ops,
1705 },
1706 },
1707 };
1708
1709 static struct clk_branch cam_cc_ife_0_dsp_clk = {
1710 .halt_reg = 0xa038,
1711 .halt_check = BRANCH_HALT,
1712 .clkr = {
1713 .enable_reg = 0xa038,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "cam_cc_ife_0_dsp_clk",
1717 .parent_hws = (const struct clk_hw*[]) {
1718 &cam_cc_ife_0_clk_src.clkr.hw,
1719 },
1720 .num_parents = 1,
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1723 },
1724 },
1725 };
1726
1727 static struct clk_branch cam_cc_ife_1_axi_clk = {
1728 .halt_reg = 0xb068,
1729 .halt_check = BRANCH_HALT,
1730 .clkr = {
1731 .enable_reg = 0xb068,
1732 .enable_mask = BIT(0),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "cam_cc_ife_1_axi_clk",
1735 .parent_hws = (const struct clk_hw*[]) {
1736 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1737 },
1738 .num_parents = 1,
1739 .flags = CLK_SET_RATE_PARENT,
1740 .ops = &clk_branch2_ops,
1741 },
1742 },
1743 };
1744
1745 static struct clk_branch cam_cc_ife_1_clk = {
1746 .halt_reg = 0xb028,
1747 .halt_check = BRANCH_HALT,
1748 .clkr = {
1749 .enable_reg = 0xb028,
1750 .enable_mask = BIT(0),
1751 .hw.init = &(struct clk_init_data){
1752 .name = "cam_cc_ife_1_clk",
1753 .parent_hws = (const struct clk_hw*[]) {
1754 &cam_cc_ife_1_clk_src.clkr.hw,
1755 },
1756 .num_parents = 1,
1757 .flags = CLK_SET_RATE_PARENT,
1758 .ops = &clk_branch2_ops,
1759 },
1760 },
1761 };
1762
1763 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1764 .halt_reg = 0xb064,
1765 .halt_check = BRANCH_HALT,
1766 .clkr = {
1767 .enable_reg = 0xb064,
1768 .enable_mask = BIT(0),
1769 .hw.init = &(struct clk_init_data){
1770 .name = "cam_cc_ife_1_cphy_rx_clk",
1771 .parent_hws = (const struct clk_hw*[]) {
1772 &cam_cc_cphy_rx_clk_src.clkr.hw,
1773 },
1774 .num_parents = 1,
1775 .flags = CLK_SET_RATE_PARENT,
1776 .ops = &clk_branch2_ops,
1777 },
1778 },
1779 };
1780
1781 static struct clk_branch cam_cc_ife_1_csid_clk = {
1782 .halt_reg = 0xb054,
1783 .halt_check = BRANCH_HALT,
1784 .clkr = {
1785 .enable_reg = 0xb054,
1786 .enable_mask = BIT(0),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "cam_cc_ife_1_csid_clk",
1789 .parent_hws = (const struct clk_hw*[]) {
1790 &cam_cc_ife_1_csid_clk_src.clkr.hw,
1791 },
1792 .num_parents = 1,
1793 .flags = CLK_SET_RATE_PARENT,
1794 .ops = &clk_branch2_ops,
1795 },
1796 },
1797 };
1798
1799 static struct clk_branch cam_cc_ife_1_dsp_clk = {
1800 .halt_reg = 0xb038,
1801 .halt_check = BRANCH_HALT,
1802 .clkr = {
1803 .enable_reg = 0xb038,
1804 .enable_mask = BIT(0),
1805 .hw.init = &(struct clk_init_data){
1806 .name = "cam_cc_ife_1_dsp_clk",
1807 .parent_hws = (const struct clk_hw*[]) {
1808 &cam_cc_ife_1_clk_src.clkr.hw,
1809 },
1810 .num_parents = 1,
1811 .flags = CLK_SET_RATE_PARENT,
1812 .ops = &clk_branch2_ops,
1813 },
1814 },
1815 };
1816
1817 static struct clk_branch cam_cc_ife_2_axi_clk = {
1818 .halt_reg = 0xb0d4,
1819 .halt_check = BRANCH_HALT,
1820 .clkr = {
1821 .enable_reg = 0xb0d4,
1822 .enable_mask = BIT(0),
1823 .hw.init = &(struct clk_init_data){
1824 .name = "cam_cc_ife_2_axi_clk",
1825 .parent_hws = (const struct clk_hw*[]) {
1826 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1827 },
1828 .num_parents = 1,
1829 .flags = CLK_SET_RATE_PARENT,
1830 .ops = &clk_branch2_ops,
1831 },
1832 },
1833 };
1834
1835 static struct clk_branch cam_cc_ife_2_clk = {
1836 .halt_reg = 0xb094,
1837 .halt_check = BRANCH_HALT,
1838 .clkr = {
1839 .enable_reg = 0xb094,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "cam_cc_ife_2_clk",
1843 .parent_hws = (const struct clk_hw*[]) {
1844 &cam_cc_ife_2_clk_src.clkr.hw,
1845 },
1846 .num_parents = 1,
1847 .flags = CLK_SET_RATE_PARENT,
1848 .ops = &clk_branch2_ops,
1849 },
1850 },
1851 };
1852
1853 static struct clk_branch cam_cc_ife_2_cphy_rx_clk = {
1854 .halt_reg = 0xb0d0,
1855 .halt_check = BRANCH_HALT,
1856 .clkr = {
1857 .enable_reg = 0xb0d0,
1858 .enable_mask = BIT(0),
1859 .hw.init = &(struct clk_init_data){
1860 .name = "cam_cc_ife_2_cphy_rx_clk",
1861 .parent_hws = (const struct clk_hw*[]) {
1862 &cam_cc_cphy_rx_clk_src.clkr.hw,
1863 },
1864 .num_parents = 1,
1865 .flags = CLK_SET_RATE_PARENT,
1866 .ops = &clk_branch2_ops,
1867 },
1868 },
1869 };
1870
1871 static struct clk_branch cam_cc_ife_2_csid_clk = {
1872 .halt_reg = 0xb0c0,
1873 .halt_check = BRANCH_HALT,
1874 .clkr = {
1875 .enable_reg = 0xb0c0,
1876 .enable_mask = BIT(0),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "cam_cc_ife_2_csid_clk",
1879 .parent_hws = (const struct clk_hw*[]) {
1880 &cam_cc_ife_2_csid_clk_src.clkr.hw,
1881 },
1882 .num_parents = 1,
1883 .flags = CLK_SET_RATE_PARENT,
1884 .ops = &clk_branch2_ops,
1885 },
1886 },
1887 };
1888
1889 static struct clk_branch cam_cc_ife_2_dsp_clk = {
1890 .halt_reg = 0xb0a4,
1891 .halt_check = BRANCH_HALT,
1892 .clkr = {
1893 .enable_reg = 0xb0a4,
1894 .enable_mask = BIT(0),
1895 .hw.init = &(struct clk_init_data){
1896 .name = "cam_cc_ife_2_dsp_clk",
1897 .parent_hws = (const struct clk_hw*[]) {
1898 &cam_cc_ife_2_clk_src.clkr.hw,
1899 },
1900 .num_parents = 1,
1901 .flags = CLK_SET_RATE_PARENT,
1902 .ops = &clk_branch2_ops,
1903 },
1904 },
1905 };
1906
1907 static struct clk_branch cam_cc_ife_lite_0_clk = {
1908 .halt_reg = 0xc01c,
1909 .halt_check = BRANCH_HALT,
1910 .clkr = {
1911 .enable_reg = 0xc01c,
1912 .enable_mask = BIT(0),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "cam_cc_ife_lite_0_clk",
1915 .parent_hws = (const struct clk_hw*[]) {
1916 &cam_cc_ife_lite_0_clk_src.clkr.hw,
1917 },
1918 .num_parents = 1,
1919 .flags = CLK_SET_RATE_PARENT,
1920 .ops = &clk_branch2_ops,
1921 },
1922 },
1923 };
1924
1925 static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = {
1926 .halt_reg = 0xc040,
1927 .halt_check = BRANCH_HALT,
1928 .clkr = {
1929 .enable_reg = 0xc040,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "cam_cc_ife_lite_0_cphy_rx_clk",
1933 .parent_hws = (const struct clk_hw*[]) {
1934 &cam_cc_cphy_rx_clk_src.clkr.hw,
1935 },
1936 .num_parents = 1,
1937 .flags = CLK_SET_RATE_PARENT,
1938 .ops = &clk_branch2_ops,
1939 },
1940 },
1941 };
1942
1943 static struct clk_branch cam_cc_ife_lite_0_csid_clk = {
1944 .halt_reg = 0xc038,
1945 .halt_check = BRANCH_HALT,
1946 .clkr = {
1947 .enable_reg = 0xc038,
1948 .enable_mask = BIT(0),
1949 .hw.init = &(struct clk_init_data){
1950 .name = "cam_cc_ife_lite_0_csid_clk",
1951 .parent_hws = (const struct clk_hw*[]) {
1952 &cam_cc_ife_lite_0_csid_clk_src.clkr.hw,
1953 },
1954 .num_parents = 1,
1955 .flags = CLK_SET_RATE_PARENT,
1956 .ops = &clk_branch2_ops,
1957 },
1958 },
1959 };
1960
1961 static struct clk_branch cam_cc_ife_lite_1_clk = {
1962 .halt_reg = 0xc060,
1963 .halt_check = BRANCH_HALT,
1964 .clkr = {
1965 .enable_reg = 0xc060,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "cam_cc_ife_lite_1_clk",
1969 .parent_hws = (const struct clk_hw*[]) {
1970 &cam_cc_ife_lite_1_clk_src.clkr.hw,
1971 },
1972 .num_parents = 1,
1973 .flags = CLK_SET_RATE_PARENT,
1974 .ops = &clk_branch2_ops,
1975 },
1976 },
1977 };
1978
1979 static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = {
1980 .halt_reg = 0xc084,
1981 .halt_check = BRANCH_HALT,
1982 .clkr = {
1983 .enable_reg = 0xc084,
1984 .enable_mask = BIT(0),
1985 .hw.init = &(struct clk_init_data){
1986 .name = "cam_cc_ife_lite_1_cphy_rx_clk",
1987 .parent_hws = (const struct clk_hw*[]) {
1988 &cam_cc_cphy_rx_clk_src.clkr.hw,
1989 },
1990 .num_parents = 1,
1991 .flags = CLK_SET_RATE_PARENT,
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995 };
1996
1997 static struct clk_branch cam_cc_ife_lite_1_csid_clk = {
1998 .halt_reg = 0xc07c,
1999 .halt_check = BRANCH_HALT,
2000 .clkr = {
2001 .enable_reg = 0xc07c,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "cam_cc_ife_lite_1_csid_clk",
2005 .parent_hws = (const struct clk_hw*[]) {
2006 &cam_cc_ife_lite_1_csid_clk_src.clkr.hw,
2007 },
2008 .num_parents = 1,
2009 .flags = CLK_SET_RATE_PARENT,
2010 .ops = &clk_branch2_ops,
2011 },
2012 },
2013 };
2014
2015 static struct clk_branch cam_cc_ipe_0_ahb_clk = {
2016 .halt_reg = 0x8040,
2017 .halt_check = BRANCH_HALT,
2018 .clkr = {
2019 .enable_reg = 0x8040,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "cam_cc_ipe_0_ahb_clk",
2023 .parent_hws = (const struct clk_hw*[]) {
2024 &cam_cc_slow_ahb_clk_src.clkr.hw,
2025 },
2026 .num_parents = 1,
2027 .flags = CLK_SET_RATE_PARENT,
2028 .ops = &clk_branch2_ops,
2029 },
2030 },
2031 };
2032
2033 static struct clk_branch cam_cc_ipe_0_areg_clk = {
2034 .halt_reg = 0x803c,
2035 .halt_check = BRANCH_HALT,
2036 .clkr = {
2037 .enable_reg = 0x803c,
2038 .enable_mask = BIT(0),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "cam_cc_ipe_0_areg_clk",
2041 .parent_hws = (const struct clk_hw*[]) {
2042 &cam_cc_fast_ahb_clk_src.clkr.hw,
2043 },
2044 .num_parents = 1,
2045 .flags = CLK_SET_RATE_PARENT,
2046 .ops = &clk_branch2_ops,
2047 },
2048 },
2049 };
2050
2051 static struct clk_branch cam_cc_ipe_0_axi_clk = {
2052 .halt_reg = 0x8038,
2053 .halt_check = BRANCH_HALT,
2054 .clkr = {
2055 .enable_reg = 0x8038,
2056 .enable_mask = BIT(0),
2057 .hw.init = &(struct clk_init_data){
2058 .name = "cam_cc_ipe_0_axi_clk",
2059 .parent_hws = (const struct clk_hw*[]) {
2060 &cam_cc_camnoc_axi_clk_src.clkr.hw,
2061 },
2062 .num_parents = 1,
2063 .flags = CLK_SET_RATE_PARENT,
2064 .ops = &clk_branch2_ops,
2065 },
2066 },
2067 };
2068
2069 static struct clk_branch cam_cc_ipe_0_clk = {
2070 .halt_reg = 0x8028,
2071 .halt_check = BRANCH_HALT,
2072 .clkr = {
2073 .enable_reg = 0x8028,
2074 .enable_mask = BIT(0),
2075 .hw.init = &(struct clk_init_data){
2076 .name = "cam_cc_ipe_0_clk",
2077 .parent_hws = (const struct clk_hw*[]) {
2078 &cam_cc_ipe_0_clk_src.clkr.hw,
2079 },
2080 .num_parents = 1,
2081 .flags = CLK_SET_RATE_PARENT,
2082 .ops = &clk_branch2_ops,
2083 },
2084 },
2085 };
2086
2087 static struct clk_branch cam_cc_jpeg_clk = {
2088 .halt_reg = 0xc0a4,
2089 .halt_check = BRANCH_HALT,
2090 .clkr = {
2091 .enable_reg = 0xc0a4,
2092 .enable_mask = BIT(0),
2093 .hw.init = &(struct clk_init_data){
2094 .name = "cam_cc_jpeg_clk",
2095 .parent_hws = (const struct clk_hw*[]) {
2096 &cam_cc_jpeg_clk_src.clkr.hw,
2097 },
2098 .num_parents = 1,
2099 .flags = CLK_SET_RATE_PARENT,
2100 .ops = &clk_branch2_ops,
2101 },
2102 },
2103 };
2104
2105 static struct clk_branch cam_cc_lrme_clk = {
2106 .halt_reg = 0xc168,
2107 .halt_check = BRANCH_HALT,
2108 .clkr = {
2109 .enable_reg = 0xc168,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "cam_cc_lrme_clk",
2113 .parent_hws = (const struct clk_hw*[]) {
2114 &cam_cc_lrme_clk_src.clkr.hw,
2115 },
2116 .num_parents = 1,
2117 .flags = CLK_SET_RATE_PARENT,
2118 .ops = &clk_branch2_ops,
2119 },
2120 },
2121 };
2122
2123 static struct clk_branch cam_cc_mclk0_clk = {
2124 .halt_reg = 0xe018,
2125 .halt_check = BRANCH_HALT,
2126 .clkr = {
2127 .enable_reg = 0xe018,
2128 .enable_mask = BIT(0),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "cam_cc_mclk0_clk",
2131 .parent_hws = (const struct clk_hw*[]) {
2132 &cam_cc_mclk0_clk_src.clkr.hw,
2133 },
2134 .num_parents = 1,
2135 .flags = CLK_SET_RATE_PARENT,
2136 .ops = &clk_branch2_ops,
2137 },
2138 },
2139 };
2140
2141 static struct clk_branch cam_cc_mclk1_clk = {
2142 .halt_reg = 0xe034,
2143 .halt_check = BRANCH_HALT,
2144 .clkr = {
2145 .enable_reg = 0xe034,
2146 .enable_mask = BIT(0),
2147 .hw.init = &(struct clk_init_data){
2148 .name = "cam_cc_mclk1_clk",
2149 .parent_hws = (const struct clk_hw*[]) {
2150 &cam_cc_mclk1_clk_src.clkr.hw,
2151 },
2152 .num_parents = 1,
2153 .flags = CLK_SET_RATE_PARENT,
2154 .ops = &clk_branch2_ops,
2155 },
2156 },
2157 };
2158
2159 static struct clk_branch cam_cc_mclk2_clk = {
2160 .halt_reg = 0xe050,
2161 .halt_check = BRANCH_HALT,
2162 .clkr = {
2163 .enable_reg = 0xe050,
2164 .enable_mask = BIT(0),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "cam_cc_mclk2_clk",
2167 .parent_hws = (const struct clk_hw*[]) {
2168 &cam_cc_mclk2_clk_src.clkr.hw,
2169 },
2170 .num_parents = 1,
2171 .flags = CLK_SET_RATE_PARENT,
2172 .ops = &clk_branch2_ops,
2173 },
2174 },
2175 };
2176
2177 static struct clk_branch cam_cc_mclk3_clk = {
2178 .halt_reg = 0xe06c,
2179 .halt_check = BRANCH_HALT,
2180 .clkr = {
2181 .enable_reg = 0xe06c,
2182 .enable_mask = BIT(0),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "cam_cc_mclk3_clk",
2185 .parent_hws = (const struct clk_hw*[]) {
2186 &cam_cc_mclk3_clk_src.clkr.hw,
2187 },
2188 .num_parents = 1,
2189 .flags = CLK_SET_RATE_PARENT,
2190 .ops = &clk_branch2_ops,
2191 },
2192 },
2193 };
2194
2195 static struct clk_branch cam_cc_mclk4_clk = {
2196 .halt_reg = 0xe088,
2197 .halt_check = BRANCH_HALT,
2198 .clkr = {
2199 .enable_reg = 0xe088,
2200 .enable_mask = BIT(0),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "cam_cc_mclk4_clk",
2203 .parent_hws = (const struct clk_hw*[]) {
2204 &cam_cc_mclk4_clk_src.clkr.hw,
2205 },
2206 .num_parents = 1,
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2209 },
2210 },
2211 };
2212
2213 static struct clk_branch cam_cc_mclk5_clk = {
2214 .halt_reg = 0xe0a4,
2215 .halt_check = BRANCH_HALT,
2216 .clkr = {
2217 .enable_reg = 0xe0a4,
2218 .enable_mask = BIT(0),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "cam_cc_mclk5_clk",
2221 .parent_hws = (const struct clk_hw*[]) {
2222 &cam_cc_mclk5_clk_src.clkr.hw,
2223 },
2224 .num_parents = 1,
2225 .flags = CLK_SET_RATE_PARENT,
2226 .ops = &clk_branch2_ops,
2227 },
2228 },
2229 };
2230
2231 static struct clk_branch cam_cc_sleep_clk = {
2232 .halt_reg = 0xc1d8,
2233 .halt_check = BRANCH_HALT,
2234 .clkr = {
2235 .enable_reg = 0xc1d8,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "cam_cc_sleep_clk",
2239 .parent_hws = (const struct clk_hw*[]) {
2240 &cam_cc_sleep_clk_src.clkr.hw,
2241 },
2242 .num_parents = 1,
2243 .flags = CLK_SET_RATE_PARENT,
2244 .ops = &clk_branch2_ops,
2245 },
2246 },
2247 };
2248
2249 static struct gdsc cam_cc_titan_top_gdsc = {
2250 .gdscr = 0xc194,
2251 .en_rest_wait_val = 0x2,
2252 .en_few_wait_val = 0x2,
2253 .clk_dis_wait_val = 0xf,
2254 .pd = {
2255 .name = "cam_cc_titan_top_gdsc",
2256 },
2257 .pwrsts = PWRSTS_OFF_ON,
2258 .flags = RETAIN_FF_ENABLE,
2259 };
2260
2261 static struct gdsc cam_cc_bps_gdsc = {
2262 .gdscr = 0x7004,
2263 .en_rest_wait_val = 0x2,
2264 .en_few_wait_val = 0x2,
2265 .clk_dis_wait_val = 0xf,
2266 .pd = {
2267 .name = "cam_cc_bps_gdsc",
2268 },
2269 .pwrsts = PWRSTS_OFF_ON,
2270 .parent = &cam_cc_titan_top_gdsc.pd,
2271 .flags = HW_CTRL | RETAIN_FF_ENABLE,
2272 };
2273
2274 static struct gdsc cam_cc_ife_0_gdsc = {
2275 .gdscr = 0xa004,
2276 .en_rest_wait_val = 0x2,
2277 .en_few_wait_val = 0x2,
2278 .clk_dis_wait_val = 0xf,
2279 .pd = {
2280 .name = "cam_cc_ife_0_gdsc",
2281 },
2282 .pwrsts = PWRSTS_OFF_ON,
2283 .parent = &cam_cc_titan_top_gdsc.pd,
2284 .flags = RETAIN_FF_ENABLE,
2285 };
2286
2287 static struct gdsc cam_cc_ife_1_gdsc = {
2288 .gdscr = 0xb004,
2289 .en_rest_wait_val = 0x2,
2290 .en_few_wait_val = 0x2,
2291 .clk_dis_wait_val = 0xf,
2292 .pd = {
2293 .name = "cam_cc_ife_1_gdsc",
2294 },
2295 .pwrsts = PWRSTS_OFF_ON,
2296 .parent = &cam_cc_titan_top_gdsc.pd,
2297 .flags = RETAIN_FF_ENABLE,
2298 };
2299
2300 static struct gdsc cam_cc_ife_2_gdsc = {
2301 .gdscr = 0xb070,
2302 .en_rest_wait_val = 0x2,
2303 .en_few_wait_val = 0x2,
2304 .clk_dis_wait_val = 0xf,
2305 .pd = {
2306 .name = "cam_cc_ife_2_gdsc",
2307 },
2308 .pwrsts = PWRSTS_OFF_ON,
2309 .parent = &cam_cc_titan_top_gdsc.pd,
2310 .flags = RETAIN_FF_ENABLE,
2311 };
2312
2313 static struct gdsc cam_cc_ipe_0_gdsc = {
2314 .gdscr = 0x8004,
2315 .en_rest_wait_val = 0x2,
2316 .en_few_wait_val = 0x2,
2317 .clk_dis_wait_val = 0xf,
2318 .pd = {
2319 .name = "cam_cc_ipe_0_gdsc",
2320 },
2321 .pwrsts = PWRSTS_OFF_ON,
2322 .parent = &cam_cc_titan_top_gdsc.pd,
2323 .flags = HW_CTRL | RETAIN_FF_ENABLE,
2324 };
2325
2326 static struct clk_regmap *cam_cc_sc7280_clocks[] = {
2327 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2328 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
2329 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
2330 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2331 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2332 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2333 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2334 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2335 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2336 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2337 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2338 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2339 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2340 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2341 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2342 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2343 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2344 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2345 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2346 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2347 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2348 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2349 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2350 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2351 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2352 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2353 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2354 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2355 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2356 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2357 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2358 [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
2359 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2360 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2361 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2362 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
2363 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2364 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2365 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
2366 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
2367 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
2368 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2369 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
2370 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2371 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2372 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
2373 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
2374 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
2375 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2376 [CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr,
2377 [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
2378 [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
2379 [CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr,
2380 [CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr,
2381 [CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr,
2382 [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
2383 [CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr,
2384 [CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr,
2385 [CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr,
2386 [CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr,
2387 [CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr,
2388 [CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr,
2389 [CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr,
2390 [CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr,
2391 [CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr,
2392 [CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr,
2393 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
2394 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
2395 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
2396 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
2397 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
2398 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2399 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2400 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
2401 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
2402 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2403 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2404 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2405 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2406 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2407 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2408 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2409 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2410 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2411 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2412 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2413 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2414 [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2415 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2416 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2417 [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2418 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2419 [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2420 [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr,
2421 [CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr,
2422 [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2423 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2424 [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2425 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2426 [CAM_CC_PLL5] = &cam_cc_pll5.clkr,
2427 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
2428 [CAM_CC_PLL6] = &cam_cc_pll6.clkr,
2429 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
2430 [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr,
2431 [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2432 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2433 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2434 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2435 };
2436
2437 static struct gdsc *cam_cc_sc7280_gdscs[] = {
2438 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
2439 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
2440 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
2441 [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
2442 [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
2443 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
2444 };
2445
2446 static const struct regmap_config cam_cc_sc7280_regmap_config = {
2447 .reg_bits = 32,
2448 .reg_stride = 4,
2449 .val_bits = 32,
2450 .max_register = 0xf00c,
2451 .fast_io = true,
2452 };
2453
2454 static const struct qcom_cc_desc cam_cc_sc7280_desc = {
2455 .config = &cam_cc_sc7280_regmap_config,
2456 .clks = cam_cc_sc7280_clocks,
2457 .num_clks = ARRAY_SIZE(cam_cc_sc7280_clocks),
2458 .gdscs = cam_cc_sc7280_gdscs,
2459 .num_gdscs = ARRAY_SIZE(cam_cc_sc7280_gdscs),
2460 };
2461
2462 static const struct of_device_id cam_cc_sc7280_match_table[] = {
2463 { .compatible = "qcom,sc7280-camcc" },
2464 { }
2465 };
2466 MODULE_DEVICE_TABLE(of, cam_cc_sc7280_match_table);
2467
cam_cc_sc7280_probe(struct platform_device * pdev)2468 static int cam_cc_sc7280_probe(struct platform_device *pdev)
2469 {
2470 struct regmap *regmap;
2471
2472 regmap = qcom_cc_map(pdev, &cam_cc_sc7280_desc);
2473 if (IS_ERR(regmap))
2474 return PTR_ERR(regmap);
2475
2476 clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2477 clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2478 clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2479 clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2480 clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2481 clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
2482 clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
2483
2484 return qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7280_desc, regmap);
2485 }
2486
2487 static struct platform_driver cam_cc_sc7280_driver = {
2488 .probe = cam_cc_sc7280_probe,
2489 .driver = {
2490 .name = "cam_cc-sc7280",
2491 .of_match_table = cam_cc_sc7280_match_table,
2492 },
2493 };
2494
2495 module_platform_driver(cam_cc_sc7280_driver);
2496
2497 MODULE_DESCRIPTION("QTI CAM_CC SC7280 Driver");
2498 MODULE_LICENSE("GPL v2");
2499