1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * 3 * Copyright (C) 2005 David Brownell 4 */ 5 6 #ifndef __LINUX_SPI_H 7 #define __LINUX_SPI_H 8 9 #include <linux/acpi.h> 10 #include <linux/bits.h> 11 #include <linux/completion.h> 12 #include <linux/device.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/kthread.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/overflow.h> 17 #include <linux/scatterlist.h> 18 #include <linux/slab.h> 19 #include <linux/u64_stats_sync.h> 20 21 #include <uapi/linux/spi/spi.h> 22 23 /* Max no. of CS supported per spi device */ 24 #define SPI_DEVICE_CS_CNT_MAX 4 25 26 struct dma_chan; 27 struct software_node; 28 struct ptp_system_timestamp; 29 struct spi_controller; 30 struct spi_transfer; 31 struct spi_controller_mem_ops; 32 struct spi_controller_mem_caps; 33 struct spi_message; 34 struct spi_offload; 35 struct spi_offload_config; 36 37 /* 38 * INTERFACES between SPI controller-side drivers and SPI target protocol handlers, 39 * and SPI infrastructure. 40 */ 41 extern const struct bus_type spi_bus_type; 42 43 /** 44 * struct spi_statistics - statistics for spi transfers 45 * @syncp: seqcount to protect members in this struct for per-cpu update 46 * on 32-bit systems 47 * 48 * @messages: number of spi-messages handled 49 * @transfers: number of spi_transfers handled 50 * @errors: number of errors during spi_transfer 51 * @timedout: number of timeouts during spi_transfer 52 * 53 * @spi_sync: number of times spi_sync is used 54 * @spi_sync_immediate: 55 * number of times spi_sync is executed immediately 56 * in calling context without queuing and scheduling 57 * @spi_async: number of times spi_async is used 58 * 59 * @bytes: number of bytes transferred to/from device 60 * @bytes_tx: number of bytes sent to device 61 * @bytes_rx: number of bytes received from device 62 * 63 * @transfer_bytes_histo: 64 * transfer bytes histogram 65 * 66 * @transfers_split_maxsize: 67 * number of transfers that have been split because of 68 * maxsize limit 69 */ 70 struct spi_statistics { 71 struct u64_stats_sync syncp; 72 73 u64_stats_t messages; 74 u64_stats_t transfers; 75 u64_stats_t errors; 76 u64_stats_t timedout; 77 78 u64_stats_t spi_sync; 79 u64_stats_t spi_sync_immediate; 80 u64_stats_t spi_async; 81 82 u64_stats_t bytes; 83 u64_stats_t bytes_rx; 84 u64_stats_t bytes_tx; 85 86 #define SPI_STATISTICS_HISTO_SIZE 17 87 u64_stats_t transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE]; 88 89 u64_stats_t transfers_split_maxsize; 90 }; 91 92 #define SPI_STATISTICS_ADD_TO_FIELD(pcpu_stats, field, count) \ 93 do { \ 94 struct spi_statistics *__lstats; \ 95 get_cpu(); \ 96 __lstats = this_cpu_ptr(pcpu_stats); \ 97 u64_stats_update_begin(&__lstats->syncp); \ 98 u64_stats_add(&__lstats->field, count); \ 99 u64_stats_update_end(&__lstats->syncp); \ 100 put_cpu(); \ 101 } while (0) 102 103 #define SPI_STATISTICS_INCREMENT_FIELD(pcpu_stats, field) \ 104 do { \ 105 struct spi_statistics *__lstats; \ 106 get_cpu(); \ 107 __lstats = this_cpu_ptr(pcpu_stats); \ 108 u64_stats_update_begin(&__lstats->syncp); \ 109 u64_stats_inc(&__lstats->field); \ 110 u64_stats_update_end(&__lstats->syncp); \ 111 put_cpu(); \ 112 } while (0) 113 114 /** 115 * struct spi_delay - SPI delay information 116 * @value: Value for the delay 117 * @unit: Unit for the delay 118 */ 119 struct spi_delay { 120 #define SPI_DELAY_UNIT_USECS 0 121 #define SPI_DELAY_UNIT_NSECS 1 122 #define SPI_DELAY_UNIT_SCK 2 123 u16 value; 124 u8 unit; 125 }; 126 127 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer); 128 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); 129 extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg, 130 struct spi_transfer *xfer); 131 132 /** 133 * struct spi_device - Controller side proxy for an SPI target device 134 * @dev: Driver model representation of the device. 135 * @controller: SPI controller used with the device. 136 * @max_speed_hz: Maximum clock rate to be used with this chip 137 * (on this board); may be changed by the device's driver. 138 * The spi_transfer.speed_hz can override this for each transfer. 139 * @bits_per_word: Data transfers involve one or more words; word sizes 140 * like eight or 12 bits are common. In-memory wordsizes are 141 * powers of two bytes (e.g. 20 bit samples use 32 bits). 142 * This may be changed by the device's driver, or left at the 143 * default (0) indicating protocol words are eight bit bytes. 144 * The spi_transfer.bits_per_word can override this for each transfer. 145 * @rt: Make the pump thread real time priority. 146 * @mode: The spi mode defines how data is clocked out and in. 147 * This may be changed by the device's driver. 148 * The "active low" default for chipselect mode can be overridden 149 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for 150 * each word in a transfer (by specifying SPI_LSB_FIRST). 151 * @irq: Negative, or the number passed to request_irq() to receive 152 * interrupts from this device. 153 * @controller_state: Controller's runtime state 154 * @controller_data: Board-specific definitions for controller, such as 155 * FIFO initialization parameters; from board_info.controller_data 156 * @modalias: Name of the driver to use with this device, or an alias 157 * for that name. This appears in the sysfs "modalias" attribute 158 * for driver coldplugging, and in uevents used for hotplugging 159 * @driver_override: If the name of a driver is written to this attribute, then 160 * the device will bind to the named driver and only the named driver. 161 * Do not set directly, because core frees it; use driver_set_override() to 162 * set or clear it. 163 * @pcpu_statistics: statistics for the spi_device 164 * @word_delay: delay to be inserted between consecutive 165 * words of a transfer 166 * @cs_setup: delay to be introduced by the controller after CS is asserted 167 * @cs_hold: delay to be introduced by the controller before CS is deasserted 168 * @cs_inactive: delay to be introduced by the controller after CS is 169 * deasserted. If @cs_change_delay is used from @spi_transfer, then the 170 * two delays will be added up. 171 * @chip_select: Array of physical chipselect, spi->chipselect[i] gives 172 * the corresponding physical CS for logical CS i. 173 * @num_chipselect: Number of physical chipselects used. 174 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array 175 * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines 176 * (optional, NULL when not using a GPIO line) 177 * 178 * A @spi_device is used to interchange data between an SPI target device 179 * (usually a discrete chip) and CPU memory. 180 * 181 * In @dev, the platform_data is used to hold information about this 182 * device that's meaningful to the device's protocol driver, but not 183 * to its controller. One example might be an identifier for a chip 184 * variant with slightly different functionality; another might be 185 * information about how this particular board wires the chip's pins. 186 */ 187 struct spi_device { 188 struct device dev; 189 struct spi_controller *controller; 190 u32 max_speed_hz; 191 u8 bits_per_word; 192 bool rt; 193 #define SPI_NO_TX BIT(31) /* No transmit wire */ 194 #define SPI_NO_RX BIT(30) /* No receive wire */ 195 /* 196 * TPM specification defines flow control over SPI. Client device 197 * can insert a wait state on MISO when address is transmitted by 198 * controller on MOSI. Detecting the wait state in software is only 199 * possible for full duplex controllers. For controllers that support 200 * only half-duplex, the wait state detection needs to be implemented 201 * in hardware. TPM devices would set this flag when hardware flow 202 * control is expected from SPI controller. 203 */ 204 #define SPI_TPM_HW_FLOW BIT(29) /* TPM HW flow control */ 205 /* 206 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. 207 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, 208 * which is defined in 'include/uapi/linux/spi/spi.h'. 209 * The bits defined here are from bit 31 downwards, while in 210 * SPI_MODE_USER_MASK are from 0 upwards. 211 * These bits must not overlap. A static assert check should make sure of that. 212 * If adding extra bits, make sure to decrease the bit index below as well. 213 */ 214 #define SPI_MODE_KERNEL_MASK (~(BIT(29) - 1)) 215 u32 mode; 216 int irq; 217 void *controller_state; 218 void *controller_data; 219 char modalias[SPI_NAME_SIZE]; 220 const char *driver_override; 221 222 /* The statistics */ 223 struct spi_statistics __percpu *pcpu_statistics; 224 225 struct spi_delay word_delay; /* Inter-word delay */ 226 227 /* CS delays */ 228 struct spi_delay cs_setup; 229 struct spi_delay cs_hold; 230 struct spi_delay cs_inactive; 231 232 u8 chip_select[SPI_DEVICE_CS_CNT_MAX]; 233 u8 num_chipselect; 234 235 /* 236 * Bit mask of the chipselect(s) that the driver need to use from 237 * the chipselect array. When the controller is capable to handle 238 * multiple chip selects & memories are connected in parallel 239 * then more than one bit need to be set in cs_index_mask. 240 */ 241 u32 cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 242 243 struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio desc */ 244 245 /* 246 * Likely need more hooks for more protocol options affecting how 247 * the controller talks to each chip, like: 248 * - memory packing (12 bit samples into low bits, others zeroed) 249 * - priority 250 * - chipselect delays 251 * - ... 252 */ 253 }; 254 255 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */ 256 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0, 257 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap"); 258 259 #define to_spi_device(__dev) container_of_const(__dev, struct spi_device, dev) 260 261 /* Most drivers won't need to care about device refcounting */ 262 static inline struct spi_device *spi_dev_get(struct spi_device *spi) 263 { 264 return (spi && get_device(&spi->dev)) ? spi : NULL; 265 } 266 267 static inline void spi_dev_put(struct spi_device *spi) 268 { 269 if (spi) 270 put_device(&spi->dev); 271 } 272 273 /* ctldata is for the bus_controller driver's runtime state */ 274 static inline void *spi_get_ctldata(const struct spi_device *spi) 275 { 276 return spi->controller_state; 277 } 278 279 static inline void spi_set_ctldata(struct spi_device *spi, void *state) 280 { 281 spi->controller_state = state; 282 } 283 284 /* Device driver data */ 285 286 static inline void spi_set_drvdata(struct spi_device *spi, void *data) 287 { 288 dev_set_drvdata(&spi->dev, data); 289 } 290 291 static inline void *spi_get_drvdata(const struct spi_device *spi) 292 { 293 return dev_get_drvdata(&spi->dev); 294 } 295 296 static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx) 297 { 298 return spi->chip_select[idx]; 299 } 300 301 static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect) 302 { 303 spi->chip_select[idx] = chipselect; 304 } 305 306 static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx) 307 { 308 return spi->cs_gpiod[idx]; 309 } 310 311 static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod) 312 { 313 spi->cs_gpiod[idx] = csgpiod; 314 } 315 316 static inline bool spi_is_csgpiod(struct spi_device *spi) 317 { 318 u8 idx; 319 320 for (idx = 0; idx < spi->num_chipselect; idx++) { 321 if (spi_get_csgpiod(spi, idx)) 322 return true; 323 } 324 return false; 325 } 326 327 /** 328 * struct spi_driver - Host side "protocol" driver 329 * @id_table: List of SPI devices supported by this driver 330 * @probe: Binds this driver to the SPI device. Drivers can verify 331 * that the device is actually present, and may need to configure 332 * characteristics (such as bits_per_word) which weren't needed for 333 * the initial configuration done during system setup. 334 * @remove: Unbinds this driver from the SPI device 335 * @shutdown: Standard shutdown callback used during system state 336 * transitions such as powerdown/halt and kexec 337 * @driver: SPI device drivers should initialize the name and owner 338 * field of this structure. 339 * 340 * This represents the kind of device driver that uses SPI messages to 341 * interact with the hardware at the other end of a SPI link. It's called 342 * a "protocol" driver because it works through messages rather than talking 343 * directly to SPI hardware (which is what the underlying SPI controller 344 * driver does to pass those messages). These protocols are defined in the 345 * specification for the device(s) supported by the driver. 346 * 347 * As a rule, those device protocols represent the lowest level interface 348 * supported by a driver, and it will support upper level interfaces too. 349 * Examples of such upper levels include frameworks like MTD, networking, 350 * MMC, RTC, filesystem character device nodes, and hardware monitoring. 351 */ 352 struct spi_driver { 353 const struct spi_device_id *id_table; 354 int (*probe)(struct spi_device *spi); 355 void (*remove)(struct spi_device *spi); 356 void (*shutdown)(struct spi_device *spi); 357 struct device_driver driver; 358 }; 359 360 #define to_spi_driver(__drv) \ 361 ( __drv ? container_of_const(__drv, struct spi_driver, driver) : NULL ) 362 363 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv); 364 365 /** 366 * spi_unregister_driver - reverse effect of spi_register_driver 367 * @sdrv: the driver to unregister 368 * Context: can sleep 369 */ 370 static inline void spi_unregister_driver(struct spi_driver *sdrv) 371 { 372 if (sdrv) 373 driver_unregister(&sdrv->driver); 374 } 375 376 extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 chip_select); 377 378 /* Use a define to avoid include chaining to get THIS_MODULE */ 379 #define spi_register_driver(driver) \ 380 __spi_register_driver(THIS_MODULE, driver) 381 382 /** 383 * module_spi_driver() - Helper macro for registering a SPI driver 384 * @__spi_driver: spi_driver struct 385 * 386 * Helper macro for SPI drivers which do not do anything special in module 387 * init/exit. This eliminates a lot of boilerplate. Each module may only 388 * use this macro once, and calling it replaces module_init() and module_exit() 389 */ 390 #define module_spi_driver(__spi_driver) \ 391 module_driver(__spi_driver, spi_register_driver, \ 392 spi_unregister_driver) 393 394 /** 395 * struct spi_controller - interface to SPI host or target controller 396 * @dev: device interface to this driver 397 * @list: link with the global spi_controller list 398 * @bus_num: board-specific (and often SOC-specific) identifier for a 399 * given SPI controller. 400 * @num_chipselect: chipselects are used to distinguish individual 401 * SPI targets, and are numbered from zero to num_chipselects. 402 * each target has a chipselect signal, but it's common that not 403 * every chipselect is connected to a target. 404 * @dma_alignment: SPI controller constraint on DMA buffers alignment. 405 * @mode_bits: flags understood by this controller driver 406 * @buswidth_override_bits: flags to override for this controller driver 407 * @bits_per_word_mask: A mask indicating which values of bits_per_word are 408 * supported by the driver. Bit n indicates that a bits_per_word n+1 is 409 * supported. If set, the SPI core will reject any transfer with an 410 * unsupported bits_per_word. If not set, this value is simply ignored, 411 * and it's up to the individual driver to perform any validation. 412 * @min_speed_hz: Lowest supported transfer speed 413 * @max_speed_hz: Highest supported transfer speed 414 * @flags: other constraints relevant to this driver 415 * @slave: indicates that this is an SPI slave controller 416 * @target: indicates that this is an SPI target controller 417 * @devm_allocated: whether the allocation of this struct is devres-managed 418 * @max_transfer_size: function that returns the max transfer size for 419 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 420 * @max_message_size: function that returns the max message size for 421 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used. 422 * @io_mutex: mutex for physical bus access 423 * @add_lock: mutex to avoid adding devices to the same chipselect 424 * @bus_lock_spinlock: spinlock for SPI bus locking 425 * @bus_lock_mutex: mutex for exclusion of multiple callers 426 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use 427 * @setup: updates the device mode and clocking records used by a 428 * device's SPI controller; protocol code may call this. This 429 * must fail if an unrecognized or unsupported mode is requested. 430 * It's always safe to call this unless transfers are pending on 431 * the device whose settings are being modified. 432 * @set_cs_timing: optional hook for SPI devices to request SPI 433 * controller for configuring specific CS setup time, hold time and inactive 434 * delay in terms of clock counts 435 * @transfer: adds a message to the controller's transfer queue. 436 * @cleanup: frees controller-specific state 437 * @can_dma: determine whether this controller supports DMA 438 * @dma_map_dev: device which can be used for DMA mapping 439 * @cur_rx_dma_dev: device which is currently used for RX DMA mapping 440 * @cur_tx_dma_dev: device which is currently used for TX DMA mapping 441 * @queued: whether this controller is providing an internal message queue 442 * @kworker: pointer to thread struct for message pump 443 * @pump_messages: work struct for scheduling work to the message pump 444 * @queue_lock: spinlock to synchronise access to message queue 445 * @queue: message queue 446 * @cur_msg: the currently in-flight message 447 * @cur_msg_completion: a completion for the current in-flight message 448 * @cur_msg_incomplete: Flag used internally to opportunistically skip 449 * the @cur_msg_completion. This flag is used to check if the driver has 450 * already called spi_finalize_current_message(). 451 * @cur_msg_need_completion: Flag used internally to opportunistically skip 452 * the @cur_msg_completion. This flag is used to signal the context that 453 * is running spi_finalize_current_message() that it needs to complete() 454 * @fallback: fallback to PIO if DMA transfer return failure with 455 * SPI_TRANS_FAIL_NO_START. 456 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs. 457 * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip 458 * selected 459 * @last_cs_index_mask: bit mask the last chip selects that were used 460 * @xfer_completion: used by core transfer_one_message() 461 * @busy: message pump is busy 462 * @running: message pump is running 463 * @rt: whether this queue is set to run as a realtime task 464 * @auto_runtime_pm: the core should ensure a runtime PM reference is held 465 * while the hardware is prepared, using the parent 466 * device for the spidev 467 * @max_dma_len: Maximum length of a DMA transfer for the device. 468 * @prepare_transfer_hardware: a message will soon arrive from the queue 469 * so the subsystem requests the driver to prepare the transfer hardware 470 * by issuing this call 471 * @transfer_one_message: the subsystem calls the driver to transfer a single 472 * message while queuing transfers that arrive in the meantime. When the 473 * driver is finished with this message, it must call 474 * spi_finalize_current_message() so the subsystem can issue the next 475 * message 476 * @unprepare_transfer_hardware: there are currently no more messages on the 477 * queue so the subsystem notifies the driver that it may relax the 478 * hardware by issuing this call 479 * 480 * @set_cs: set the logic level of the chip select line. May be called 481 * from interrupt context. 482 * @optimize_message: optimize the message for reuse 483 * @unoptimize_message: release resources allocated by optimize_message 484 * @prepare_message: set up the controller to transfer a single message, 485 * for example doing DMA mapping. Called from threaded 486 * context. 487 * @transfer_one: transfer a single spi_transfer. 488 * 489 * - return 0 if the transfer is finished, 490 * - return 1 if the transfer is still in progress. When 491 * the driver is finished with this transfer it must 492 * call spi_finalize_current_transfer() so the subsystem 493 * can issue the next transfer. If the transfer fails, the 494 * driver must set the flag SPI_TRANS_FAIL_IO to 495 * spi_transfer->error first, before calling 496 * spi_finalize_current_transfer(). 497 * Note: transfer_one and transfer_one_message are mutually 498 * exclusive; when both are set, the generic subsystem does 499 * not call your transfer_one callback. 500 * @handle_err: the subsystem calls the driver to handle an error that occurs 501 * in the generic implementation of transfer_one_message(). 502 * @mem_ops: optimized/dedicated operations for interactions with SPI memory. 503 * This field is optional and should only be implemented if the 504 * controller has native support for memory like operations. 505 * @get_offload: callback for controllers with offload support to get matching 506 * offload instance. Implementations should return -ENODEV if no match is 507 * found. 508 * @put_offload: release the offload instance acquired by @get_offload. 509 * @mem_caps: controller capabilities for the handling of memory operations. 510 * @dtr_caps: true if controller has dtr(single/dual transfer rate) capability. 511 * QSPI based controller should fill this based on controller's capability. 512 * @unprepare_message: undo any work done by prepare_message(). 513 * @target_abort: abort the ongoing transfer request on an SPI target controller 514 * @cs_gpiods: Array of GPIO descriptors to use as chip select lines; one per CS 515 * number. Any individual value may be NULL for CS lines that 516 * are not GPIOs (driven by the SPI controller itself). 517 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab 518 * GPIO descriptors. This will fill in @cs_gpiods and SPI devices will have 519 * the cs_gpiod assigned if a GPIO line is found for the chipselect. 520 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will 521 * fill in this field with the first unused native CS, to be used by SPI 522 * controller drivers that need to drive a native CS when using GPIO CS. 523 * @max_native_cs: When cs_gpiods is used, and this field is filled in, 524 * spi_register_controller() will validate all native CS (including the 525 * unused native CS) against this value. 526 * @pcpu_statistics: statistics for the spi_controller 527 * @dma_tx: DMA transmit channel 528 * @dma_rx: DMA receive channel 529 * @dummy_rx: dummy receive buffer for full-duplex devices 530 * @dummy_tx: dummy transmit buffer for full-duplex devices 531 * @fw_translate_cs: If the boot firmware uses different numbering scheme 532 * what Linux expects, this optional hook can be used to translate 533 * between the two. 534 * @ptp_sts_supported: If the driver sets this to true, it must provide a 535 * time snapshot in @spi_transfer->ptp_sts as close as possible to the 536 * moment in time when @spi_transfer->ptp_sts_word_pre and 537 * @spi_transfer->ptp_sts_word_post were transmitted. 538 * If the driver does not set this, the SPI core takes the snapshot as 539 * close to the driver hand-over as possible. 540 * @irq_flags: Interrupt enable state during PTP system timestamping 541 * @queue_empty: signal green light for opportunistically skipping the queue 542 * for spi_sync transfers. 543 * @must_async: disable all fast paths in the core 544 * @defer_optimize_message: set to true if controller cannot pre-optimize messages 545 * and needs to defer the optimization step until the message is actually 546 * being transferred 547 * 548 * Each SPI controller can communicate with one or more @spi_device 549 * children. These make a small bus, sharing MOSI, MISO and SCK signals 550 * but not chip select signals. Each device may be configured to use a 551 * different clock rate, since those shared signals are ignored unless 552 * the chip is selected. 553 * 554 * The driver for an SPI controller manages access to those devices through 555 * a queue of spi_message transactions, copying data between CPU memory and 556 * an SPI target device. For each such message it queues, it calls the 557 * message's completion function when the transaction completes. 558 */ 559 struct spi_controller { 560 struct device dev; 561 562 struct list_head list; 563 564 /* 565 * Other than negative (== assign one dynamically), bus_num is fully 566 * board-specific. Usually that simplifies to being SoC-specific. 567 * example: one SoC has three SPI controllers, numbered 0..2, 568 * and one board's schematics might show it using SPI-2. Software 569 * would normally use bus_num=2 for that controller. 570 */ 571 s16 bus_num; 572 573 /* 574 * Chipselects will be integral to many controllers; some others 575 * might use board-specific GPIOs. 576 */ 577 u16 num_chipselect; 578 579 /* Some SPI controllers pose alignment requirements on DMAable 580 * buffers; let protocol drivers know about these requirements. 581 */ 582 u16 dma_alignment; 583 584 /* spi_device.mode flags understood by this controller driver */ 585 u32 mode_bits; 586 587 /* spi_device.mode flags override flags for this controller */ 588 u32 buswidth_override_bits; 589 590 /* Bitmask of supported bits_per_word for transfers */ 591 u32 bits_per_word_mask; 592 #define SPI_BPW_MASK(bits) BIT((bits) - 1) 593 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1) 594 595 /* Limits on transfer speed */ 596 u32 min_speed_hz; 597 u32 max_speed_hz; 598 599 /* Other constraints relevant to this driver */ 600 u16 flags; 601 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* Can't do full duplex */ 602 #define SPI_CONTROLLER_NO_RX BIT(1) /* Can't do buffer read */ 603 #define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ 604 #define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ 605 #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ 606 #define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select target device */ 607 #define SPI_CONTROLLER_SUSPENDED BIT(6) /* Currently suspended */ 608 /* 609 * The spi-controller has multi chip select capability and can 610 * assert/de-assert more than one chip select at once. 611 */ 612 #define SPI_CONTROLLER_MULTI_CS BIT(7) 613 614 /* Flag indicating if the allocation of this struct is devres-managed */ 615 bool devm_allocated; 616 617 union { 618 /* Flag indicating this is an SPI slave controller */ 619 bool slave; 620 /* Flag indicating this is an SPI target controller */ 621 bool target; 622 }; 623 624 /* 625 * On some hardware transfer / message size may be constrained 626 * the limit may depend on device transfer settings. 627 */ 628 size_t (*max_transfer_size)(struct spi_device *spi); 629 size_t (*max_message_size)(struct spi_device *spi); 630 631 /* I/O mutex */ 632 struct mutex io_mutex; 633 634 /* Used to avoid adding the same CS twice */ 635 struct mutex add_lock; 636 637 /* Lock and mutex for SPI bus locking */ 638 spinlock_t bus_lock_spinlock; 639 struct mutex bus_lock_mutex; 640 641 /* Flag indicating that the SPI bus is locked for exclusive use */ 642 bool bus_lock_flag; 643 644 /* 645 * Setup mode and clock, etc (SPI driver may call many times). 646 * 647 * IMPORTANT: this may be called when transfers to another 648 * device are active. DO NOT UPDATE SHARED REGISTERS in ways 649 * which could break those transfers. 650 */ 651 int (*setup)(struct spi_device *spi); 652 653 /* 654 * set_cs_timing() method is for SPI controllers that supports 655 * configuring CS timing. 656 * 657 * This hook allows SPI client drivers to request SPI controllers 658 * to configure specific CS timing through spi_set_cs_timing() after 659 * spi_setup(). 660 */ 661 int (*set_cs_timing)(struct spi_device *spi); 662 663 /* 664 * Bidirectional bulk transfers 665 * 666 * + The transfer() method may not sleep; its main role is 667 * just to add the message to the queue. 668 * + For now there's no remove-from-queue operation, or 669 * any other request management 670 * + To a given spi_device, message queueing is pure FIFO 671 * 672 * + The controller's main job is to process its message queue, 673 * selecting a chip (for controllers), then transferring data 674 * + If there are multiple spi_device children, the i/o queue 675 * arbitration algorithm is unspecified (round robin, FIFO, 676 * priority, reservations, preemption, etc) 677 * 678 * + Chipselect stays active during the entire message 679 * (unless modified by spi_transfer.cs_change != 0). 680 * + The message transfers use clock and SPI mode parameters 681 * previously established by setup() for this device 682 */ 683 int (*transfer)(struct spi_device *spi, 684 struct spi_message *mesg); 685 686 /* Called on release() to free memory provided by spi_controller */ 687 void (*cleanup)(struct spi_device *spi); 688 689 /* 690 * Used to enable core support for DMA handling, if can_dma() 691 * exists and returns true then the transfer will be mapped 692 * prior to transfer_one() being called. The driver should 693 * not modify or store xfer and dma_tx and dma_rx must be set 694 * while the device is prepared. 695 */ 696 bool (*can_dma)(struct spi_controller *ctlr, 697 struct spi_device *spi, 698 struct spi_transfer *xfer); 699 struct device *dma_map_dev; 700 struct device *cur_rx_dma_dev; 701 struct device *cur_tx_dma_dev; 702 703 /* 704 * These hooks are for drivers that want to use the generic 705 * controller transfer queueing mechanism. If these are used, the 706 * transfer() function above must NOT be specified by the driver. 707 * Over time we expect SPI drivers to be phased over to this API. 708 */ 709 bool queued; 710 struct kthread_worker *kworker; 711 struct kthread_work pump_messages; 712 spinlock_t queue_lock; 713 struct list_head queue; 714 struct spi_message *cur_msg; 715 struct completion cur_msg_completion; 716 bool cur_msg_incomplete; 717 bool cur_msg_need_completion; 718 bool busy; 719 bool running; 720 bool rt; 721 bool auto_runtime_pm; 722 bool fallback; 723 bool last_cs_mode_high; 724 s8 last_cs[SPI_DEVICE_CS_CNT_MAX]; 725 u32 last_cs_index_mask : SPI_DEVICE_CS_CNT_MAX; 726 struct completion xfer_completion; 727 size_t max_dma_len; 728 729 int (*optimize_message)(struct spi_message *msg); 730 int (*unoptimize_message)(struct spi_message *msg); 731 int (*prepare_transfer_hardware)(struct spi_controller *ctlr); 732 int (*transfer_one_message)(struct spi_controller *ctlr, 733 struct spi_message *mesg); 734 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr); 735 int (*prepare_message)(struct spi_controller *ctlr, 736 struct spi_message *message); 737 int (*unprepare_message)(struct spi_controller *ctlr, 738 struct spi_message *message); 739 int (*target_abort)(struct spi_controller *ctlr); 740 741 /* 742 * These hooks are for drivers that use a generic implementation 743 * of transfer_one_message() provided by the core. 744 */ 745 void (*set_cs)(struct spi_device *spi, bool enable); 746 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, 747 struct spi_transfer *transfer); 748 void (*handle_err)(struct spi_controller *ctlr, 749 struct spi_message *message); 750 751 /* Optimized handlers for SPI memory-like operations. */ 752 const struct spi_controller_mem_ops *mem_ops; 753 const struct spi_controller_mem_caps *mem_caps; 754 755 /* SPI or QSPI controller can set to true if supports SDR/DDR transfer rate */ 756 bool dtr_caps; 757 758 struct spi_offload *(*get_offload)(struct spi_device *spi, 759 const struct spi_offload_config *config); 760 void (*put_offload)(struct spi_offload *offload); 761 762 /* GPIO chip select */ 763 struct gpio_desc **cs_gpiods; 764 bool use_gpio_descriptors; 765 s8 unused_native_cs; 766 s8 max_native_cs; 767 768 /* Statistics */ 769 struct spi_statistics __percpu *pcpu_statistics; 770 771 /* DMA channels for use with core dmaengine helpers */ 772 struct dma_chan *dma_tx; 773 struct dma_chan *dma_rx; 774 775 /* Dummy data for full duplex devices */ 776 void *dummy_rx; 777 void *dummy_tx; 778 779 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); 780 781 /* 782 * Driver sets this field to indicate it is able to snapshot SPI 783 * transfers (needed e.g. for reading the time of POSIX clocks) 784 */ 785 bool ptp_sts_supported; 786 787 /* Interrupt enable state during PTP system timestamping */ 788 unsigned long irq_flags; 789 790 /* Flag for enabling opportunistic skipping of the queue in spi_sync */ 791 bool queue_empty; 792 bool must_async; 793 bool defer_optimize_message; 794 }; 795 796 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr) 797 { 798 return dev_get_drvdata(&ctlr->dev); 799 } 800 801 static inline void spi_controller_set_devdata(struct spi_controller *ctlr, 802 void *data) 803 { 804 dev_set_drvdata(&ctlr->dev, data); 805 } 806 807 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr) 808 { 809 if (!ctlr || !get_device(&ctlr->dev)) 810 return NULL; 811 return ctlr; 812 } 813 814 static inline void spi_controller_put(struct spi_controller *ctlr) 815 { 816 if (ctlr) 817 put_device(&ctlr->dev); 818 } 819 820 static inline bool spi_controller_is_target(struct spi_controller *ctlr) 821 { 822 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target; 823 } 824 825 /* PM calls that need to be issued by the driver */ 826 extern int spi_controller_suspend(struct spi_controller *ctlr); 827 extern int spi_controller_resume(struct spi_controller *ctlr); 828 829 /* Calls the driver make to interact with the message queue */ 830 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr); 831 extern void spi_finalize_current_message(struct spi_controller *ctlr); 832 extern void spi_finalize_current_transfer(struct spi_controller *ctlr); 833 834 /* Helper calls for driver to timestamp transfer */ 835 void spi_take_timestamp_pre(struct spi_controller *ctlr, 836 struct spi_transfer *xfer, 837 size_t progress, bool irqs_off); 838 void spi_take_timestamp_post(struct spi_controller *ctlr, 839 struct spi_transfer *xfer, 840 size_t progress, bool irqs_off); 841 842 /* The SPI driver core manages memory for the spi_controller classdev */ 843 extern struct spi_controller *__spi_alloc_controller(struct device *host, 844 unsigned int size, bool target); 845 846 static inline struct spi_controller *spi_alloc_host(struct device *dev, 847 unsigned int size) 848 { 849 return __spi_alloc_controller(dev, size, false); 850 } 851 852 static inline struct spi_controller *spi_alloc_target(struct device *dev, 853 unsigned int size) 854 { 855 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 856 return NULL; 857 858 return __spi_alloc_controller(dev, size, true); 859 } 860 861 struct spi_controller *__devm_spi_alloc_controller(struct device *dev, 862 unsigned int size, 863 bool target); 864 865 static inline struct spi_controller *devm_spi_alloc_host(struct device *dev, 866 unsigned int size) 867 { 868 return __devm_spi_alloc_controller(dev, size, false); 869 } 870 871 static inline struct spi_controller *devm_spi_alloc_target(struct device *dev, 872 unsigned int size) 873 { 874 if (!IS_ENABLED(CONFIG_SPI_SLAVE)) 875 return NULL; 876 877 return __devm_spi_alloc_controller(dev, size, true); 878 } 879 880 extern int spi_register_controller(struct spi_controller *ctlr); 881 extern int devm_spi_register_controller(struct device *dev, 882 struct spi_controller *ctlr); 883 extern void spi_unregister_controller(struct spi_controller *ctlr); 884 885 #if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SPI_MASTER) 886 extern struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev); 887 extern struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 888 struct acpi_device *adev, 889 int index); 890 int acpi_spi_count_resources(struct acpi_device *adev); 891 #else 892 static inline struct spi_controller *acpi_spi_find_controller_by_adev(struct acpi_device *adev) 893 { 894 return NULL; 895 } 896 897 static inline struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, 898 struct acpi_device *adev, 899 int index) 900 { 901 return ERR_PTR(-ENODEV); 902 } 903 904 static inline int acpi_spi_count_resources(struct acpi_device *adev) 905 { 906 return 0; 907 } 908 #endif 909 910 /* 911 * SPI resource management while processing a SPI message 912 */ 913 914 typedef void (*spi_res_release_t)(struct spi_controller *ctlr, 915 struct spi_message *msg, 916 void *res); 917 918 /** 919 * struct spi_res - SPI resource management structure 920 * @entry: list entry 921 * @release: release code called prior to freeing this resource 922 * @data: extra data allocated for the specific use-case 923 * 924 * This is based on ideas from devres, but focused on life-cycle 925 * management during spi_message processing. 926 */ 927 struct spi_res { 928 struct list_head entry; 929 spi_res_release_t release; 930 unsigned long long data[]; /* Guarantee ull alignment */ 931 }; 932 933 /*---------------------------------------------------------------------------*/ 934 935 /* 936 * I/O INTERFACE between SPI controller and protocol drivers 937 * 938 * Protocol drivers use a queue of spi_messages, each transferring data 939 * between the controller and memory buffers. 940 * 941 * The spi_messages themselves consist of a series of read+write transfer 942 * segments. Those segments always read the same number of bits as they 943 * write; but one or the other is easily ignored by passing a NULL buffer 944 * pointer. (This is unlike most types of I/O API, because SPI hardware 945 * is full duplex.) 946 * 947 * NOTE: Allocation of spi_transfer and spi_message memory is entirely 948 * up to the protocol driver, which guarantees the integrity of both (as 949 * well as the data buffers) for as long as the message is queued. 950 */ 951 952 /** 953 * struct spi_transfer - a read/write buffer pair 954 * @tx_buf: data to be written (DMA-safe memory), or NULL 955 * @rx_buf: data to be read (DMA-safe memory), or NULL 956 * @tx_dma: DMA address of tx_buf, currently not for client use 957 * @rx_dma: DMA address of rx_buf, currently not for client use 958 * @tx_nbits: number of bits used for writing. If 0 the default 959 * (SPI_NBITS_SINGLE) is used. 960 * @rx_nbits: number of bits used for reading. If 0 the default 961 * (SPI_NBITS_SINGLE) is used. 962 * @len: size of rx and tx buffers (in bytes) 963 * @speed_hz: Select a speed other than the device default for this 964 * transfer. If 0 the default (from @spi_device) is used. 965 * @bits_per_word: select a bits_per_word other than the device default 966 * for this transfer. If 0 the default (from @spi_device) is used. 967 * @dummy_data: indicates transfer is dummy bytes transfer. 968 * @cs_off: performs the transfer with chipselect off. 969 * @cs_change: affects chipselect after this transfer completes 970 * @cs_change_delay: delay between cs deassert and assert when 971 * @cs_change is set and @spi_transfer is not the last in @spi_message 972 * @delay: delay to be introduced after this transfer before 973 * (optionally) changing the chipselect status, then starting 974 * the next transfer or completing this @spi_message. 975 * @word_delay: inter word delay to be introduced after each word size 976 * (set by bits_per_word) transmission. 977 * @effective_speed_hz: the effective SCK-speed that was used to 978 * transfer this transfer. Set to 0 if the SPI bus driver does 979 * not support it. 980 * @transfer_list: transfers are sequenced through @spi_message.transfers 981 * @tx_sg_mapped: If true, the @tx_sg is mapped for DMA 982 * @rx_sg_mapped: If true, the @rx_sg is mapped for DMA 983 * @tx_sg: Scatterlist for transmit, currently not for client use 984 * @rx_sg: Scatterlist for receive, currently not for client use 985 * @offload_flags: Flags that are only applicable to specialized SPI offload 986 * transfers. See %SPI_OFFLOAD_XFER_* in spi-offload.h. 987 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset 988 * within @tx_buf for which the SPI device is requesting that the time 989 * snapshot for this transfer begins. Upon completing the SPI transfer, 990 * this value may have changed compared to what was requested, depending 991 * on the available snapshotting resolution (DMA transfer, 992 * @ptp_sts_supported is false, etc). 993 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning 994 * that a single byte should be snapshotted). 995 * If the core takes care of the timestamp (if @ptp_sts_supported is false 996 * for this controller), it will set @ptp_sts_word_pre to 0, and 997 * @ptp_sts_word_post to the length of the transfer. This is done 998 * purposefully (instead of setting to spi_transfer->len - 1) to denote 999 * that a transfer-level snapshot taken from within the driver may still 1000 * be of higher quality. 1001 * @ptp_sts: Pointer to a memory location held by the SPI target device where a 1002 * PTP system timestamp structure may lie. If drivers use PIO or their 1003 * hardware has some sort of assist for retrieving exact transfer timing, 1004 * they can (and should) assert @ptp_sts_supported and populate this 1005 * structure using the ptp_read_system_*ts helper functions. 1006 * The timestamp must represent the time at which the SPI target device has 1007 * processed the word, i.e. the "pre" timestamp should be taken before 1008 * transmitting the "pre" word, and the "post" timestamp after receiving 1009 * transmit confirmation from the controller for the "post" word. 1010 * @dtr_mode: true if supports double transfer rate. 1011 * @timestamped: true if the transfer has been timestamped 1012 * @error: Error status logged by SPI controller driver. 1013 * 1014 * SPI transfers always write the same number of bytes as they read. 1015 * Protocol drivers should always provide @rx_buf and/or @tx_buf. 1016 * In some cases, they may also want to provide DMA addresses for 1017 * the data being transferred; that may reduce overhead, when the 1018 * underlying driver uses DMA. 1019 * 1020 * If the transmit buffer is NULL, zeroes will be shifted out 1021 * while filling @rx_buf. If the receive buffer is NULL, the data 1022 * shifted in will be discarded. Only "len" bytes shift out (or in). 1023 * It's an error to try to shift out a partial word. (For example, by 1024 * shifting out three bytes with word size of sixteen or twenty bits; 1025 * the former uses two bytes per word, the latter uses four bytes.) 1026 * 1027 * In-memory data values are always in native CPU byte order, translated 1028 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So 1029 * for example when bits_per_word is sixteen, buffers are 2N bytes long 1030 * (@len = 2N) and hold N sixteen bit words in CPU byte order. 1031 * 1032 * When the word size of the SPI transfer is not a power-of-two multiple 1033 * of eight bits, those in-memory words include extra bits. In-memory 1034 * words are always seen by protocol drivers as right-justified, so the 1035 * undefined (rx) or unused (tx) bits are always the most significant bits. 1036 * 1037 * All SPI transfers start with the relevant chipselect active. Normally 1038 * it stays selected until after the last transfer in a message. Drivers 1039 * can affect the chipselect signal using cs_change. 1040 * 1041 * (i) If the transfer isn't the last one in the message, this flag is 1042 * used to make the chipselect briefly go inactive in the middle of the 1043 * message. Toggling chipselect in this way may be needed to terminate 1044 * a chip command, letting a single spi_message perform all of group of 1045 * chip transactions together. 1046 * 1047 * (ii) When the transfer is the last one in the message, the chip may 1048 * stay selected until the next transfer. On multi-device SPI busses 1049 * with nothing blocking messages going to other devices, this is just 1050 * a performance hint; starting a message to another device deselects 1051 * this one. But in other cases, this can be used to ensure correctness. 1052 * Some devices need protocol transactions to be built from a series of 1053 * spi_message submissions, where the content of one message is determined 1054 * by the results of previous messages and where the whole transaction 1055 * ends when the chipselect goes inactive. 1056 * 1057 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information 1058 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these 1059 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) 1060 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. 1061 * 1062 * User may also set dtr_mode to true to use dual transfer mode if desired. if 1063 * not, default considered as single transfer mode. 1064 * 1065 * The code that submits an spi_message (and its spi_transfers) 1066 * to the lower layers is responsible for managing its memory. 1067 * Zero-initialize every field you don't set up explicitly, to 1068 * insulate against future API updates. After you submit a message 1069 * and its transfers, ignore them until its completion callback. 1070 */ 1071 struct spi_transfer { 1072 /* 1073 * It's okay if tx_buf == rx_buf (right?). 1074 * For MicroWire, one buffer must be NULL. 1075 * Buffers must work with dma_*map_single() calls. 1076 */ 1077 const void *tx_buf; 1078 void *rx_buf; 1079 unsigned len; 1080 1081 #define SPI_TRANS_FAIL_NO_START BIT(0) 1082 #define SPI_TRANS_FAIL_IO BIT(1) 1083 u16 error; 1084 1085 bool tx_sg_mapped; 1086 bool rx_sg_mapped; 1087 1088 struct sg_table tx_sg; 1089 struct sg_table rx_sg; 1090 dma_addr_t tx_dma; 1091 dma_addr_t rx_dma; 1092 1093 unsigned dummy_data:1; 1094 unsigned cs_off:1; 1095 unsigned cs_change:1; 1096 unsigned tx_nbits:4; 1097 unsigned rx_nbits:4; 1098 unsigned timestamped:1; 1099 bool dtr_mode; 1100 #define SPI_NBITS_SINGLE 0x01 /* 1-bit transfer */ 1101 #define SPI_NBITS_DUAL 0x02 /* 2-bit transfer */ 1102 #define SPI_NBITS_QUAD 0x04 /* 4-bit transfer */ 1103 #define SPI_NBITS_OCTAL 0x08 /* 8-bit transfer */ 1104 u8 bits_per_word; 1105 struct spi_delay delay; 1106 struct spi_delay cs_change_delay; 1107 struct spi_delay word_delay; 1108 u32 speed_hz; 1109 1110 u32 effective_speed_hz; 1111 1112 /* Use %SPI_OFFLOAD_XFER_* from spi-offload.h */ 1113 unsigned int offload_flags; 1114 1115 unsigned int ptp_sts_word_pre; 1116 unsigned int ptp_sts_word_post; 1117 1118 struct ptp_system_timestamp *ptp_sts; 1119 1120 struct list_head transfer_list; 1121 }; 1122 1123 /** 1124 * struct spi_message - one multi-segment SPI transaction 1125 * @transfers: list of transfer segments in this transaction 1126 * @spi: SPI device to which the transaction is queued 1127 * @pre_optimized: peripheral driver pre-optimized the message 1128 * @optimized: the message is in the optimized state 1129 * @prepared: spi_prepare_message was called for the this message 1130 * @status: zero for success, else negative errno 1131 * @complete: called to report transaction completions 1132 * @context: the argument to complete() when it's called 1133 * @frame_length: the total number of bytes in the message 1134 * @actual_length: the total number of bytes that were transferred in all 1135 * successful segments 1136 * @queue: for use by whichever driver currently owns the message 1137 * @state: for use by whichever driver currently owns the message 1138 * @opt_state: for use by whichever driver currently owns the message 1139 * @resources: for resource management when the SPI message is processed 1140 * @offload: (optional) offload instance used by this message 1141 * 1142 * A @spi_message is used to execute an atomic sequence of data transfers, 1143 * each represented by a struct spi_transfer. The sequence is "atomic" 1144 * in the sense that no other spi_message may use that SPI bus until that 1145 * sequence completes. On some systems, many such sequences can execute as 1146 * a single programmed DMA transfer. On all systems, these messages are 1147 * queued, and might complete after transactions to other devices. Messages 1148 * sent to a given spi_device are always executed in FIFO order. 1149 * 1150 * The code that submits an spi_message (and its spi_transfers) 1151 * to the lower layers is responsible for managing its memory. 1152 * Zero-initialize every field you don't set up explicitly, to 1153 * insulate against future API updates. After you submit a message 1154 * and its transfers, ignore them until its completion callback. 1155 */ 1156 struct spi_message { 1157 struct list_head transfers; 1158 1159 struct spi_device *spi; 1160 1161 /* spi_optimize_message() was called for this message */ 1162 bool pre_optimized; 1163 /* __spi_optimize_message() was called for this message */ 1164 bool optimized; 1165 1166 /* spi_prepare_message() was called for this message */ 1167 bool prepared; 1168 1169 /* 1170 * REVISIT: we might want a flag affecting the behavior of the 1171 * last transfer ... allowing things like "read 16 bit length L" 1172 * immediately followed by "read L bytes". Basically imposing 1173 * a specific message scheduling algorithm. 1174 * 1175 * Some controller drivers (message-at-a-time queue processing) 1176 * could provide that as their default scheduling algorithm. But 1177 * others (with multi-message pipelines) could need a flag to 1178 * tell them about such special cases. 1179 */ 1180 1181 /* Completion is reported through a callback */ 1182 int status; 1183 void (*complete)(void *context); 1184 void *context; 1185 unsigned frame_length; 1186 unsigned actual_length; 1187 1188 /* 1189 * For optional use by whatever driver currently owns the 1190 * spi_message ... between calls to spi_async and then later 1191 * complete(), that's the spi_controller controller driver. 1192 */ 1193 struct list_head queue; 1194 void *state; 1195 /* 1196 * Optional state for use by controller driver between calls to 1197 * __spi_optimize_message() and __spi_unoptimize_message(). 1198 */ 1199 void *opt_state; 1200 1201 /* 1202 * Optional offload instance used by this message. This must be set 1203 * by the peripheral driver before calling spi_optimize_message(). 1204 */ 1205 struct spi_offload *offload; 1206 1207 /* List of spi_res resources when the SPI message is processed */ 1208 struct list_head resources; 1209 }; 1210 1211 static inline void spi_message_init_no_memset(struct spi_message *m) 1212 { 1213 INIT_LIST_HEAD(&m->transfers); 1214 INIT_LIST_HEAD(&m->resources); 1215 } 1216 1217 static inline void spi_message_init(struct spi_message *m) 1218 { 1219 memset(m, 0, sizeof *m); 1220 spi_message_init_no_memset(m); 1221 } 1222 1223 static inline void 1224 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) 1225 { 1226 list_add_tail(&t->transfer_list, &m->transfers); 1227 } 1228 1229 static inline void 1230 spi_transfer_del(struct spi_transfer *t) 1231 { 1232 list_del(&t->transfer_list); 1233 } 1234 1235 static inline int 1236 spi_transfer_delay_exec(struct spi_transfer *t) 1237 { 1238 return spi_delay_exec(&t->delay, t); 1239 } 1240 1241 /** 1242 * spi_message_init_with_transfers - Initialize spi_message and append transfers 1243 * @m: spi_message to be initialized 1244 * @xfers: An array of SPI transfers 1245 * @num_xfers: Number of items in the xfer array 1246 * 1247 * This function initializes the given spi_message and adds each spi_transfer in 1248 * the given array to the message. 1249 */ 1250 static inline void 1251 spi_message_init_with_transfers(struct spi_message *m, 1252 struct spi_transfer *xfers, unsigned int num_xfers) 1253 { 1254 unsigned int i; 1255 1256 spi_message_init(m); 1257 for (i = 0; i < num_xfers; ++i) 1258 spi_message_add_tail(&xfers[i], m); 1259 } 1260 1261 /* 1262 * It's fine to embed message and transaction structures in other data 1263 * structures so long as you don't free them while they're in use. 1264 */ 1265 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) 1266 { 1267 struct spi_message_with_transfers { 1268 struct spi_message m; 1269 struct spi_transfer t[]; 1270 } *mwt; 1271 unsigned i; 1272 1273 mwt = kzalloc(struct_size(mwt, t, ntrans), flags); 1274 if (!mwt) 1275 return NULL; 1276 1277 spi_message_init_no_memset(&mwt->m); 1278 for (i = 0; i < ntrans; i++) 1279 spi_message_add_tail(&mwt->t[i], &mwt->m); 1280 1281 return &mwt->m; 1282 } 1283 1284 static inline void spi_message_free(struct spi_message *m) 1285 { 1286 kfree(m); 1287 } 1288 1289 extern int spi_optimize_message(struct spi_device *spi, struct spi_message *msg); 1290 extern void spi_unoptimize_message(struct spi_message *msg); 1291 extern int devm_spi_optimize_message(struct device *dev, struct spi_device *spi, 1292 struct spi_message *msg); 1293 1294 extern int spi_setup(struct spi_device *spi); 1295 extern int spi_async(struct spi_device *spi, struct spi_message *message); 1296 extern int spi_target_abort(struct spi_device *spi); 1297 1298 static inline size_t 1299 spi_max_message_size(struct spi_device *spi) 1300 { 1301 struct spi_controller *ctlr = spi->controller; 1302 1303 if (!ctlr->max_message_size) 1304 return SIZE_MAX; 1305 return ctlr->max_message_size(spi); 1306 } 1307 1308 static inline size_t 1309 spi_max_transfer_size(struct spi_device *spi) 1310 { 1311 struct spi_controller *ctlr = spi->controller; 1312 size_t tr_max = SIZE_MAX; 1313 size_t msg_max = spi_max_message_size(spi); 1314 1315 if (ctlr->max_transfer_size) 1316 tr_max = ctlr->max_transfer_size(spi); 1317 1318 /* Transfer size limit must not be greater than message size limit */ 1319 return min(tr_max, msg_max); 1320 } 1321 1322 /** 1323 * spi_is_bpw_supported - Check if bits per word is supported 1324 * @spi: SPI device 1325 * @bpw: Bits per word 1326 * 1327 * This function checks to see if the SPI controller supports @bpw. 1328 * 1329 * Returns: 1330 * True if @bpw is supported, false otherwise. 1331 */ 1332 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw) 1333 { 1334 u32 bpw_mask = spi->controller->bits_per_word_mask; 1335 1336 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw))) 1337 return true; 1338 1339 return false; 1340 } 1341 1342 /** 1343 * spi_bpw_to_bytes - Covert bits per word to bytes 1344 * @bpw: Bits per word 1345 * 1346 * This function converts the given @bpw to bytes. The result is always 1347 * power-of-two, e.g., 1348 * 1349 * =============== ================= 1350 * Input (in bits) Output (in bytes) 1351 * =============== ================= 1352 * 5 1 1353 * 9 2 1354 * 21 4 1355 * 37 8 1356 * =============== ================= 1357 * 1358 * It will return 0 for the 0 input. 1359 * 1360 * Returns: 1361 * Bytes for the given @bpw. 1362 */ 1363 static inline u32 spi_bpw_to_bytes(u32 bpw) 1364 { 1365 return roundup_pow_of_two(BITS_TO_BYTES(bpw)); 1366 } 1367 1368 /** 1369 * spi_controller_xfer_timeout - Compute a suitable timeout value 1370 * @ctlr: SPI device 1371 * @xfer: Transfer descriptor 1372 * 1373 * Compute a relevant timeout value for the given transfer. We derive the time 1374 * that it would take on a single data line and take twice this amount of time 1375 * with a minimum of 500ms to avoid false positives on loaded systems. 1376 * 1377 * Returns: Transfer timeout value in milliseconds. 1378 */ 1379 static inline unsigned int spi_controller_xfer_timeout(struct spi_controller *ctlr, 1380 struct spi_transfer *xfer) 1381 { 1382 return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U); 1383 } 1384 1385 /*---------------------------------------------------------------------------*/ 1386 1387 /* SPI transfer replacement methods which make use of spi_res */ 1388 1389 struct spi_replaced_transfers; 1390 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr, 1391 struct spi_message *msg, 1392 struct spi_replaced_transfers *res); 1393 /** 1394 * struct spi_replaced_transfers - structure describing the spi_transfer 1395 * replacements that have occurred 1396 * so that they can get reverted 1397 * @release: some extra release code to get executed prior to 1398 * releasing this structure 1399 * @extradata: pointer to some extra data if requested or NULL 1400 * @replaced_transfers: transfers that have been replaced and which need 1401 * to get restored 1402 * @replaced_after: the transfer after which the @replaced_transfers 1403 * are to get re-inserted 1404 * @inserted: number of transfers inserted 1405 * @inserted_transfers: array of spi_transfers of array-size @inserted, 1406 * that have been replacing replaced_transfers 1407 * 1408 * Note: that @extradata will point to @inserted_transfers[@inserted] 1409 * if some extra allocation is requested, so alignment will be the same 1410 * as for spi_transfers. 1411 */ 1412 struct spi_replaced_transfers { 1413 spi_replaced_release_t release; 1414 void *extradata; 1415 struct list_head replaced_transfers; 1416 struct list_head *replaced_after; 1417 size_t inserted; 1418 struct spi_transfer inserted_transfers[]; 1419 }; 1420 1421 /*---------------------------------------------------------------------------*/ 1422 1423 /* SPI transfer transformation methods */ 1424 1425 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr, 1426 struct spi_message *msg, 1427 size_t maxsize); 1428 extern int spi_split_transfers_maxwords(struct spi_controller *ctlr, 1429 struct spi_message *msg, 1430 size_t maxwords); 1431 1432 /*---------------------------------------------------------------------------*/ 1433 1434 /* 1435 * All these synchronous SPI transfer routines are utilities layered 1436 * over the core async transfer primitive. Here, "synchronous" means 1437 * they will sleep uninterruptibly until the async transfer completes. 1438 */ 1439 1440 extern int spi_sync(struct spi_device *spi, struct spi_message *message); 1441 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); 1442 extern int spi_bus_lock(struct spi_controller *ctlr); 1443 extern int spi_bus_unlock(struct spi_controller *ctlr); 1444 1445 /** 1446 * spi_sync_transfer - synchronous SPI data transfer 1447 * @spi: device with which data will be exchanged 1448 * @xfers: An array of spi_transfers 1449 * @num_xfers: Number of items in the xfer array 1450 * Context: can sleep 1451 * 1452 * Does a synchronous SPI data transfer of the given spi_transfer array. 1453 * 1454 * For more specific semantics see spi_sync(). 1455 * 1456 * Return: zero on success, else a negative error code. 1457 */ 1458 static inline int 1459 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, 1460 unsigned int num_xfers) 1461 { 1462 struct spi_message msg; 1463 1464 spi_message_init_with_transfers(&msg, xfers, num_xfers); 1465 1466 return spi_sync(spi, &msg); 1467 } 1468 1469 /** 1470 * spi_write - SPI synchronous write 1471 * @spi: device to which data will be written 1472 * @buf: data buffer 1473 * @len: data buffer size 1474 * Context: can sleep 1475 * 1476 * This function writes the buffer @buf. 1477 * Callable only from contexts that can sleep. 1478 * 1479 * Return: zero on success, else a negative error code. 1480 */ 1481 static inline int 1482 spi_write(struct spi_device *spi, const void *buf, size_t len) 1483 { 1484 struct spi_transfer t = { 1485 .tx_buf = buf, 1486 .len = len, 1487 }; 1488 1489 return spi_sync_transfer(spi, &t, 1); 1490 } 1491 1492 /** 1493 * spi_read - SPI synchronous read 1494 * @spi: device from which data will be read 1495 * @buf: data buffer 1496 * @len: data buffer size 1497 * Context: can sleep 1498 * 1499 * This function reads the buffer @buf. 1500 * Callable only from contexts that can sleep. 1501 * 1502 * Return: zero on success, else a negative error code. 1503 */ 1504 static inline int 1505 spi_read(struct spi_device *spi, void *buf, size_t len) 1506 { 1507 struct spi_transfer t = { 1508 .rx_buf = buf, 1509 .len = len, 1510 }; 1511 1512 return spi_sync_transfer(spi, &t, 1); 1513 } 1514 1515 /* This copies txbuf and rxbuf data; for small transfers only! */ 1516 extern int spi_write_then_read(struct spi_device *spi, 1517 const void *txbuf, unsigned n_tx, 1518 void *rxbuf, unsigned n_rx); 1519 1520 /** 1521 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read 1522 * @spi: device with which data will be exchanged 1523 * @cmd: command to be written before data is read back 1524 * Context: can sleep 1525 * 1526 * Callable only from contexts that can sleep. 1527 * 1528 * Return: the (unsigned) eight bit number returned by the 1529 * device, or else a negative error code. 1530 */ 1531 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) 1532 { 1533 ssize_t status; 1534 u8 result; 1535 1536 status = spi_write_then_read(spi, &cmd, 1, &result, 1); 1537 1538 /* Return negative errno or unsigned value */ 1539 return (status < 0) ? status : result; 1540 } 1541 1542 /** 1543 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read 1544 * @spi: device with which data will be exchanged 1545 * @cmd: command to be written before data is read back 1546 * Context: can sleep 1547 * 1548 * The number is returned in wire-order, which is at least sometimes 1549 * big-endian. 1550 * 1551 * Callable only from contexts that can sleep. 1552 * 1553 * Return: the (unsigned) sixteen bit number returned by the 1554 * device, or else a negative error code. 1555 */ 1556 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) 1557 { 1558 ssize_t status; 1559 u16 result; 1560 1561 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1562 1563 /* Return negative errno or unsigned value */ 1564 return (status < 0) ? status : result; 1565 } 1566 1567 /** 1568 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read 1569 * @spi: device with which data will be exchanged 1570 * @cmd: command to be written before data is read back 1571 * Context: can sleep 1572 * 1573 * This function is similar to spi_w8r16, with the exception that it will 1574 * convert the read 16 bit data word from big-endian to native endianness. 1575 * 1576 * Callable only from contexts that can sleep. 1577 * 1578 * Return: the (unsigned) sixteen bit number returned by the device in CPU 1579 * endianness, or else a negative error code. 1580 */ 1581 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd) 1582 1583 { 1584 ssize_t status; 1585 __be16 result; 1586 1587 status = spi_write_then_read(spi, &cmd, 1, &result, 2); 1588 if (status < 0) 1589 return status; 1590 1591 return be16_to_cpu(result); 1592 } 1593 1594 /*---------------------------------------------------------------------------*/ 1595 1596 /* 1597 * INTERFACE between board init code and SPI infrastructure. 1598 * 1599 * No SPI driver ever sees these SPI device table segments, but 1600 * it's how the SPI core (or adapters that get hotplugged) grows 1601 * the driver model tree. 1602 * 1603 * As a rule, SPI devices can't be probed. Instead, board init code 1604 * provides a table listing the devices which are present, with enough 1605 * information to bind and set up the device's driver. There's basic 1606 * support for non-static configurations too; enough to handle adding 1607 * parport adapters, or microcontrollers acting as USB-to-SPI bridges. 1608 */ 1609 1610 /** 1611 * struct spi_board_info - board-specific template for a SPI device 1612 * @modalias: Initializes spi_device.modalias; identifies the driver. 1613 * @platform_data: Initializes spi_device.platform_data; the particular 1614 * data stored there is driver-specific. 1615 * @swnode: Software node for the device. 1616 * @controller_data: Initializes spi_device.controller_data; some 1617 * controllers need hints about hardware setup, e.g. for DMA. 1618 * @irq: Initializes spi_device.irq; depends on how the board is wired. 1619 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits 1620 * from the chip datasheet and board-specific signal quality issues. 1621 * @bus_num: Identifies which spi_controller parents the spi_device; unused 1622 * by spi_new_device(), and otherwise depends on board wiring. 1623 * @chip_select: Initializes spi_device.chip_select; depends on how 1624 * the board is wired. 1625 * @mode: Initializes spi_device.mode; based on the chip datasheet, board 1626 * wiring (some devices support both 3WIRE and standard modes), and 1627 * possibly presence of an inverter in the chipselect path. 1628 * 1629 * When adding new SPI devices to the device tree, these structures serve 1630 * as a partial device template. They hold information which can't always 1631 * be determined by drivers. Information that probe() can establish (such 1632 * as the default transfer wordsize) is not included here. 1633 * 1634 * These structures are used in two places. Their primary role is to 1635 * be stored in tables of board-specific device descriptors, which are 1636 * declared early in board initialization and then used (much later) to 1637 * populate a controller's device tree after the that controller's driver 1638 * initializes. A secondary (and atypical) role is as a parameter to 1639 * spi_new_device() call, which happens after those controller drivers 1640 * are active in some dynamic board configuration models. 1641 */ 1642 struct spi_board_info { 1643 /* 1644 * The device name and module name are coupled, like platform_bus; 1645 * "modalias" is normally the driver name. 1646 * 1647 * platform_data goes to spi_device.dev.platform_data, 1648 * controller_data goes to spi_device.controller_data, 1649 * IRQ is copied too. 1650 */ 1651 char modalias[SPI_NAME_SIZE]; 1652 const void *platform_data; 1653 const struct software_node *swnode; 1654 void *controller_data; 1655 int irq; 1656 1657 /* Slower signaling on noisy or low voltage boards */ 1658 u32 max_speed_hz; 1659 1660 1661 /* 1662 * bus_num is board specific and matches the bus_num of some 1663 * spi_controller that will probably be registered later. 1664 * 1665 * chip_select reflects how this chip is wired to that controller; 1666 * it's less than num_chipselect. 1667 */ 1668 u16 bus_num; 1669 u16 chip_select; 1670 1671 /* 1672 * mode becomes spi_device.mode, and is essential for chips 1673 * where the default of SPI_CS_HIGH = 0 is wrong. 1674 */ 1675 u32 mode; 1676 1677 /* 1678 * ... may need additional spi_device chip config data here. 1679 * avoid stuff protocol drivers can set; but include stuff 1680 * needed to behave without being bound to a driver: 1681 * - quirks like clock rate mattering when not selected 1682 */ 1683 }; 1684 1685 #ifdef CONFIG_SPI 1686 extern int 1687 spi_register_board_info(struct spi_board_info const *info, unsigned n); 1688 #else 1689 /* Board init code may ignore whether SPI is configured or not */ 1690 static inline int 1691 spi_register_board_info(struct spi_board_info const *info, unsigned n) 1692 { return 0; } 1693 #endif 1694 1695 /* 1696 * If you're hotplugging an adapter with devices (parport, USB, etc) 1697 * use spi_new_device() to describe each device. You can also call 1698 * spi_unregister_device() to start making that device vanish, but 1699 * normally that would be handled by spi_unregister_controller(). 1700 * 1701 * You can also use spi_alloc_device() and spi_add_device() to use a two 1702 * stage registration sequence for each spi_device. This gives the caller 1703 * some more control over the spi_device structure before it is registered, 1704 * but requires that caller to initialize fields that would otherwise 1705 * be defined using the board info. 1706 */ 1707 extern struct spi_device * 1708 spi_alloc_device(struct spi_controller *ctlr); 1709 1710 extern int 1711 spi_add_device(struct spi_device *spi); 1712 1713 extern struct spi_device * 1714 spi_new_device(struct spi_controller *, struct spi_board_info *); 1715 1716 extern void spi_unregister_device(struct spi_device *spi); 1717 1718 extern const struct spi_device_id * 1719 spi_get_device_id(const struct spi_device *sdev); 1720 1721 extern const void * 1722 spi_get_device_match_data(const struct spi_device *sdev); 1723 1724 static inline bool 1725 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer) 1726 { 1727 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers); 1728 } 1729 1730 #endif /* __LINUX_SPI_H */ 1731