1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #define BXE_DRIVER_VERSION "1.78.91"
31
32 #include "bxe.h"
33 #include <net/rss_config.h>
34 #include "ecore_sp.h"
35 #include "ecore_init.h"
36 #include "ecore_init_ops.h"
37
38 #include "57710_int_offsets.h"
39 #include "57711_int_offsets.h"
40 #include "57712_int_offsets.h"
41
42 /*
43 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these
44 * explicitly here for older kernels that don't include this changeset.
45 */
46 #ifndef CTLTYPE_U64
47 #define CTLTYPE_U64 CTLTYPE_QUAD
48 #define sysctl_handle_64 sysctl_handle_quad
49 #endif
50
51 /*
52 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these
53 * here as zero(0) for older kernels that don't include this changeset
54 * thereby masking the functionality.
55 */
56 #ifndef CSUM_TCP_IPV6
57 #define CSUM_TCP_IPV6 0
58 #define CSUM_UDP_IPV6 0
59 #endif
60
61 #define BXE_DEF_SB_ATT_IDX 0x0001
62 #define BXE_DEF_SB_IDX 0x0002
63
64 /*
65 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
66 * function HW initialization.
67 */
68 #define FLR_WAIT_USEC 10000 /* 10 msecs */
69 #define FLR_WAIT_INTERVAL 50 /* usecs */
70 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
71
72 struct pbf_pN_buf_regs {
73 int pN;
74 uint32_t init_crd;
75 uint32_t crd;
76 uint32_t crd_freed;
77 };
78
79 struct pbf_pN_cmd_regs {
80 int pN;
81 uint32_t lines_occup;
82 uint32_t lines_freed;
83 };
84
85 /*
86 * PCI Device ID Table used by bxe_probe().
87 */
88 #define BXE_DEVDESC_MAX 64
89 static struct bxe_device_type bxe_devs[] = {
90 {
91 BRCM_VENDORID,
92 CHIP_NUM_57710,
93 PCI_ANY_ID, PCI_ANY_ID,
94 "QLogic NetXtreme II BCM57710 10GbE"
95 },
96 {
97 BRCM_VENDORID,
98 CHIP_NUM_57711,
99 PCI_ANY_ID, PCI_ANY_ID,
100 "QLogic NetXtreme II BCM57711 10GbE"
101 },
102 {
103 BRCM_VENDORID,
104 CHIP_NUM_57711E,
105 PCI_ANY_ID, PCI_ANY_ID,
106 "QLogic NetXtreme II BCM57711E 10GbE"
107 },
108 {
109 BRCM_VENDORID,
110 CHIP_NUM_57712,
111 PCI_ANY_ID, PCI_ANY_ID,
112 "QLogic NetXtreme II BCM57712 10GbE"
113 },
114 {
115 BRCM_VENDORID,
116 CHIP_NUM_57712_MF,
117 PCI_ANY_ID, PCI_ANY_ID,
118 "QLogic NetXtreme II BCM57712 MF 10GbE"
119 },
120 {
121 BRCM_VENDORID,
122 CHIP_NUM_57800,
123 PCI_ANY_ID, PCI_ANY_ID,
124 "QLogic NetXtreme II BCM57800 10GbE"
125 },
126 {
127 BRCM_VENDORID,
128 CHIP_NUM_57800_MF,
129 PCI_ANY_ID, PCI_ANY_ID,
130 "QLogic NetXtreme II BCM57800 MF 10GbE"
131 },
132 {
133 BRCM_VENDORID,
134 CHIP_NUM_57810,
135 PCI_ANY_ID, PCI_ANY_ID,
136 "QLogic NetXtreme II BCM57810 10GbE"
137 },
138 {
139 BRCM_VENDORID,
140 CHIP_NUM_57810_MF,
141 PCI_ANY_ID, PCI_ANY_ID,
142 "QLogic NetXtreme II BCM57810 MF 10GbE"
143 },
144 {
145 BRCM_VENDORID,
146 CHIP_NUM_57811,
147 PCI_ANY_ID, PCI_ANY_ID,
148 "QLogic NetXtreme II BCM57811 10GbE"
149 },
150 {
151 BRCM_VENDORID,
152 CHIP_NUM_57811_MF,
153 PCI_ANY_ID, PCI_ANY_ID,
154 "QLogic NetXtreme II BCM57811 MF 10GbE"
155 },
156 {
157 BRCM_VENDORID,
158 CHIP_NUM_57840_4_10,
159 PCI_ANY_ID, PCI_ANY_ID,
160 "QLogic NetXtreme II BCM57840 4x10GbE"
161 },
162 {
163 QLOGIC_VENDORID,
164 CHIP_NUM_57840_4_10,
165 PCI_ANY_ID, PCI_ANY_ID,
166 "QLogic NetXtreme II BCM57840 4x10GbE"
167 },
168 {
169 BRCM_VENDORID,
170 CHIP_NUM_57840_2_20,
171 PCI_ANY_ID, PCI_ANY_ID,
172 "QLogic NetXtreme II BCM57840 2x20GbE"
173 },
174 {
175 BRCM_VENDORID,
176 CHIP_NUM_57840_MF,
177 PCI_ANY_ID, PCI_ANY_ID,
178 "QLogic NetXtreme II BCM57840 MF 10GbE"
179 },
180 {
181 0, 0, 0, 0, NULL
182 }
183 };
184
185 MALLOC_DECLARE(M_BXE_ILT);
186 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer");
187
188 /*
189 * FreeBSD device entry points.
190 */
191 static int bxe_probe(device_t);
192 static int bxe_attach(device_t);
193 static int bxe_detach(device_t);
194 static int bxe_shutdown(device_t);
195
196
197 /*
198 * FreeBSD KLD module/device interface event handler method.
199 */
200 static device_method_t bxe_methods[] = {
201 /* Device interface (device_if.h) */
202 DEVMETHOD(device_probe, bxe_probe),
203 DEVMETHOD(device_attach, bxe_attach),
204 DEVMETHOD(device_detach, bxe_detach),
205 DEVMETHOD(device_shutdown, bxe_shutdown),
206 /* Bus interface (bus_if.h) */
207 DEVMETHOD(bus_print_child, bus_generic_print_child),
208 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
209 KOBJMETHOD_END
210 };
211
212 /*
213 * FreeBSD KLD Module data declaration
214 */
215 static driver_t bxe_driver = {
216 "bxe", /* module name */
217 bxe_methods, /* event handler */
218 sizeof(struct bxe_softc) /* extra data */
219 };
220
221 MODULE_DEPEND(bxe, pci, 1, 1, 1);
222 MODULE_DEPEND(bxe, ether, 1, 1, 1);
223 DRIVER_MODULE(bxe, pci, bxe_driver, 0, 0);
224
225 DEBUGNET_DEFINE(bxe);
226
227 /* resources needed for unloading a previously loaded device */
228
229 #define BXE_PREV_WAIT_NEEDED 1
230 struct mtx bxe_prev_mtx;
231 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF);
232 struct bxe_prev_list_node {
233 LIST_ENTRY(bxe_prev_list_node) node;
234 uint8_t bus;
235 uint8_t slot;
236 uint8_t path;
237 uint8_t aer; /* XXX automatic error recovery */
238 uint8_t undi;
239 };
240 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list);
241
242 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
243
244 /* Tunable device values... */
245
246 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
247 "bxe driver parameters");
248
249 /* Debug */
250 unsigned long bxe_debug = 0;
251 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, CTLFLAG_RDTUN,
252 &bxe_debug, 0, "Debug logging mode");
253
254 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
255 static int bxe_interrupt_mode = INTR_MODE_MSIX;
256 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN,
257 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
258
259 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */
260 static int bxe_queue_count = 4;
261 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
262 &bxe_queue_count, 0, "Multi-Queue queue count");
263
264 /* max number of buffers per queue (default RX_BD_USABLE) */
265 static int bxe_max_rx_bufs = 0;
266 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN,
267 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue");
268
269 /* Host interrupt coalescing RX tick timer (usecs) */
270 static int bxe_hc_rx_ticks = 25;
271 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN,
272 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks");
273
274 /* Host interrupt coalescing TX tick timer (usecs) */
275 static int bxe_hc_tx_ticks = 50;
276 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN,
277 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks");
278
279 /* Maximum number of Rx packets to process at a time */
280 static int bxe_rx_budget = 0xffffffff;
281 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_RDTUN,
282 &bxe_rx_budget, 0, "Rx processing budget");
283
284 /* Maximum LRO aggregation size */
285 static int bxe_max_aggregation_size = 0;
286 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_RDTUN,
287 &bxe_max_aggregation_size, 0, "max aggregation size");
288
289 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
290 static int bxe_mrrs = -1;
291 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN,
292 &bxe_mrrs, 0, "PCIe maximum read request size");
293
294 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */
295 static int bxe_autogreeen = 0;
296 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN,
297 &bxe_autogreeen, 0, "AutoGrEEEn support");
298
299 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */
300 static int bxe_udp_rss = 0;
301 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN,
302 &bxe_udp_rss, 0, "UDP RSS support");
303
304
305 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */
306
307 #define STATS_OFFSET32(stat_name) \
308 (offsetof(struct bxe_eth_stats, stat_name) / 4)
309
310 #define Q_STATS_OFFSET32(stat_name) \
311 (offsetof(struct bxe_eth_q_stats, stat_name) / 4)
312
313 static const struct {
314 uint32_t offset;
315 uint32_t size;
316 uint32_t flags;
317 #define STATS_FLAGS_PORT 1
318 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */
319 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
320 char string[STAT_NAME_LEN];
321 } bxe_eth_stats_arr[] = {
322 { STATS_OFFSET32(total_bytes_received_hi),
323 8, STATS_FLAGS_BOTH, "rx_bytes" },
324 { STATS_OFFSET32(error_bytes_received_hi),
325 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
326 { STATS_OFFSET32(total_unicast_packets_received_hi),
327 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
328 { STATS_OFFSET32(total_multicast_packets_received_hi),
329 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
330 { STATS_OFFSET32(total_broadcast_packets_received_hi),
331 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
332 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
333 8, STATS_FLAGS_PORT, "rx_crc_errors" },
334 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
335 8, STATS_FLAGS_PORT, "rx_align_errors" },
336 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
337 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
338 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
339 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
340 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
341 8, STATS_FLAGS_PORT, "rx_fragments" },
342 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
343 8, STATS_FLAGS_PORT, "rx_jabbers" },
344 { STATS_OFFSET32(no_buff_discard_hi),
345 8, STATS_FLAGS_BOTH, "rx_discards" },
346 { STATS_OFFSET32(mac_filter_discard),
347 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
348 { STATS_OFFSET32(mf_tag_discard),
349 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
350 { STATS_OFFSET32(pfc_frames_received_hi),
351 8, STATS_FLAGS_PORT, "pfc_frames_received" },
352 { STATS_OFFSET32(pfc_frames_sent_hi),
353 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
354 { STATS_OFFSET32(brb_drop_hi),
355 8, STATS_FLAGS_PORT, "rx_brb_discard" },
356 { STATS_OFFSET32(brb_truncate_hi),
357 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
358 { STATS_OFFSET32(pause_frames_received_hi),
359 8, STATS_FLAGS_PORT, "rx_pause_frames" },
360 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
361 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
362 { STATS_OFFSET32(nig_timer_max),
363 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
364 { STATS_OFFSET32(total_bytes_transmitted_hi),
365 8, STATS_FLAGS_BOTH, "tx_bytes" },
366 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
367 8, STATS_FLAGS_PORT, "tx_error_bytes" },
368 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
369 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
370 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
371 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
372 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
373 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
374 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
375 8, STATS_FLAGS_PORT, "tx_mac_errors" },
376 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
377 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
378 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
379 8, STATS_FLAGS_PORT, "tx_single_collisions" },
380 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
381 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
382 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
383 8, STATS_FLAGS_PORT, "tx_deferred" },
384 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
385 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
386 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
387 8, STATS_FLAGS_PORT, "tx_late_collisions" },
388 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
389 8, STATS_FLAGS_PORT, "tx_total_collisions" },
390 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
391 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
392 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
393 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
394 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
395 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
396 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
397 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
398 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
399 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
400 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
401 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
402 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
403 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
404 { STATS_OFFSET32(pause_frames_sent_hi),
405 8, STATS_FLAGS_PORT, "tx_pause_frames" },
406 { STATS_OFFSET32(total_tpa_aggregations_hi),
407 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
408 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
409 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
410 { STATS_OFFSET32(total_tpa_bytes_hi),
411 8, STATS_FLAGS_FUNC, "tpa_bytes"},
412 { STATS_OFFSET32(eee_tx_lpi),
413 4, STATS_FLAGS_PORT, "eee_tx_lpi"},
414 { STATS_OFFSET32(rx_calls),
415 4, STATS_FLAGS_FUNC, "rx_calls"},
416 { STATS_OFFSET32(rx_pkts),
417 4, STATS_FLAGS_FUNC, "rx_pkts"},
418 { STATS_OFFSET32(rx_tpa_pkts),
419 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"},
420 { STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
421 4, STATS_FLAGS_FUNC, "rx_erroneous_jumbo_sge_pkts"},
422 { STATS_OFFSET32(rx_bxe_service_rxsgl),
423 4, STATS_FLAGS_FUNC, "rx_bxe_service_rxsgl"},
424 { STATS_OFFSET32(rx_jumbo_sge_pkts),
425 4, STATS_FLAGS_FUNC, "rx_jumbo_sge_pkts"},
426 { STATS_OFFSET32(rx_soft_errors),
427 4, STATS_FLAGS_FUNC, "rx_soft_errors"},
428 { STATS_OFFSET32(rx_hw_csum_errors),
429 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"},
430 { STATS_OFFSET32(rx_ofld_frames_csum_ip),
431 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"},
432 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
433 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"},
434 { STATS_OFFSET32(rx_budget_reached),
435 4, STATS_FLAGS_FUNC, "rx_budget_reached"},
436 { STATS_OFFSET32(tx_pkts),
437 4, STATS_FLAGS_FUNC, "tx_pkts"},
438 { STATS_OFFSET32(tx_soft_errors),
439 4, STATS_FLAGS_FUNC, "tx_soft_errors"},
440 { STATS_OFFSET32(tx_ofld_frames_csum_ip),
441 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"},
442 { STATS_OFFSET32(tx_ofld_frames_csum_tcp),
443 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"},
444 { STATS_OFFSET32(tx_ofld_frames_csum_udp),
445 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"},
446 { STATS_OFFSET32(tx_ofld_frames_lso),
447 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"},
448 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
449 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"},
450 { STATS_OFFSET32(tx_encap_failures),
451 4, STATS_FLAGS_FUNC, "tx_encap_failures"},
452 { STATS_OFFSET32(tx_hw_queue_full),
453 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"},
454 { STATS_OFFSET32(tx_hw_max_queue_depth),
455 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"},
456 { STATS_OFFSET32(tx_dma_mapping_failure),
457 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"},
458 { STATS_OFFSET32(tx_max_drbr_queue_depth),
459 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"},
460 { STATS_OFFSET32(tx_window_violation_std),
461 4, STATS_FLAGS_FUNC, "tx_window_violation_std"},
462 { STATS_OFFSET32(tx_window_violation_tso),
463 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"},
464 { STATS_OFFSET32(tx_chain_lost_mbuf),
465 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"},
466 { STATS_OFFSET32(tx_frames_deferred),
467 4, STATS_FLAGS_FUNC, "tx_frames_deferred"},
468 { STATS_OFFSET32(tx_queue_xoff),
469 4, STATS_FLAGS_FUNC, "tx_queue_xoff"},
470 { STATS_OFFSET32(mbuf_defrag_attempts),
471 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"},
472 { STATS_OFFSET32(mbuf_defrag_failures),
473 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"},
474 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
475 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"},
476 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
477 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"},
478 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
479 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"},
480 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
481 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"},
482 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
483 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"},
484 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
485 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"},
486 { STATS_OFFSET32(mbuf_alloc_tx),
487 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"},
488 { STATS_OFFSET32(mbuf_alloc_rx),
489 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"},
490 { STATS_OFFSET32(mbuf_alloc_sge),
491 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"},
492 { STATS_OFFSET32(mbuf_alloc_tpa),
493 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"},
494 { STATS_OFFSET32(tx_queue_full_return),
495 4, STATS_FLAGS_FUNC, "tx_queue_full_return"},
496 { STATS_OFFSET32(bxe_tx_mq_sc_state_failures),
497 4, STATS_FLAGS_FUNC, "bxe_tx_mq_sc_state_failures"},
498 { STATS_OFFSET32(tx_request_link_down_failures),
499 4, STATS_FLAGS_FUNC, "tx_request_link_down_failures"},
500 { STATS_OFFSET32(bd_avail_too_less_failures),
501 4, STATS_FLAGS_FUNC, "bd_avail_too_less_failures"},
502 { STATS_OFFSET32(tx_mq_not_empty),
503 4, STATS_FLAGS_FUNC, "tx_mq_not_empty"},
504 { STATS_OFFSET32(nsegs_path1_errors),
505 4, STATS_FLAGS_FUNC, "nsegs_path1_errors"},
506 { STATS_OFFSET32(nsegs_path2_errors),
507 4, STATS_FLAGS_FUNC, "nsegs_path2_errors"}
508
509
510 };
511
512 static const struct {
513 uint32_t offset;
514 uint32_t size;
515 char string[STAT_NAME_LEN];
516 } bxe_eth_q_stats_arr[] = {
517 { Q_STATS_OFFSET32(total_bytes_received_hi),
518 8, "rx_bytes" },
519 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
520 8, "rx_ucast_packets" },
521 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
522 8, "rx_mcast_packets" },
523 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
524 8, "rx_bcast_packets" },
525 { Q_STATS_OFFSET32(no_buff_discard_hi),
526 8, "rx_discards" },
527 { Q_STATS_OFFSET32(total_bytes_transmitted_hi),
528 8, "tx_bytes" },
529 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
530 8, "tx_ucast_packets" },
531 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
532 8, "tx_mcast_packets" },
533 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
534 8, "tx_bcast_packets" },
535 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
536 8, "tpa_aggregations" },
537 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
538 8, "tpa_aggregated_frames"},
539 { Q_STATS_OFFSET32(total_tpa_bytes_hi),
540 8, "tpa_bytes"},
541 { Q_STATS_OFFSET32(rx_calls),
542 4, "rx_calls"},
543 { Q_STATS_OFFSET32(rx_pkts),
544 4, "rx_pkts"},
545 { Q_STATS_OFFSET32(rx_tpa_pkts),
546 4, "rx_tpa_pkts"},
547 { Q_STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
548 4, "rx_erroneous_jumbo_sge_pkts"},
549 { Q_STATS_OFFSET32(rx_bxe_service_rxsgl),
550 4, "rx_bxe_service_rxsgl"},
551 { Q_STATS_OFFSET32(rx_jumbo_sge_pkts),
552 4, "rx_jumbo_sge_pkts"},
553 { Q_STATS_OFFSET32(rx_soft_errors),
554 4, "rx_soft_errors"},
555 { Q_STATS_OFFSET32(rx_hw_csum_errors),
556 4, "rx_hw_csum_errors"},
557 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip),
558 4, "rx_ofld_frames_csum_ip"},
559 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
560 4, "rx_ofld_frames_csum_tcp_udp"},
561 { Q_STATS_OFFSET32(rx_budget_reached),
562 4, "rx_budget_reached"},
563 { Q_STATS_OFFSET32(tx_pkts),
564 4, "tx_pkts"},
565 { Q_STATS_OFFSET32(tx_soft_errors),
566 4, "tx_soft_errors"},
567 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip),
568 4, "tx_ofld_frames_csum_ip"},
569 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp),
570 4, "tx_ofld_frames_csum_tcp"},
571 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp),
572 4, "tx_ofld_frames_csum_udp"},
573 { Q_STATS_OFFSET32(tx_ofld_frames_lso),
574 4, "tx_ofld_frames_lso"},
575 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
576 4, "tx_ofld_frames_lso_hdr_splits"},
577 { Q_STATS_OFFSET32(tx_encap_failures),
578 4, "tx_encap_failures"},
579 { Q_STATS_OFFSET32(tx_hw_queue_full),
580 4, "tx_hw_queue_full"},
581 { Q_STATS_OFFSET32(tx_hw_max_queue_depth),
582 4, "tx_hw_max_queue_depth"},
583 { Q_STATS_OFFSET32(tx_dma_mapping_failure),
584 4, "tx_dma_mapping_failure"},
585 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth),
586 4, "tx_max_drbr_queue_depth"},
587 { Q_STATS_OFFSET32(tx_window_violation_std),
588 4, "tx_window_violation_std"},
589 { Q_STATS_OFFSET32(tx_window_violation_tso),
590 4, "tx_window_violation_tso"},
591 { Q_STATS_OFFSET32(tx_chain_lost_mbuf),
592 4, "tx_chain_lost_mbuf"},
593 { Q_STATS_OFFSET32(tx_frames_deferred),
594 4, "tx_frames_deferred"},
595 { Q_STATS_OFFSET32(tx_queue_xoff),
596 4, "tx_queue_xoff"},
597 { Q_STATS_OFFSET32(mbuf_defrag_attempts),
598 4, "mbuf_defrag_attempts"},
599 { Q_STATS_OFFSET32(mbuf_defrag_failures),
600 4, "mbuf_defrag_failures"},
601 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
602 4, "mbuf_rx_bd_alloc_failed"},
603 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
604 4, "mbuf_rx_bd_mapping_failed"},
605 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
606 4, "mbuf_rx_tpa_alloc_failed"},
607 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
608 4, "mbuf_rx_tpa_mapping_failed"},
609 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
610 4, "mbuf_rx_sge_alloc_failed"},
611 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
612 4, "mbuf_rx_sge_mapping_failed"},
613 { Q_STATS_OFFSET32(mbuf_alloc_tx),
614 4, "mbuf_alloc_tx"},
615 { Q_STATS_OFFSET32(mbuf_alloc_rx),
616 4, "mbuf_alloc_rx"},
617 { Q_STATS_OFFSET32(mbuf_alloc_sge),
618 4, "mbuf_alloc_sge"},
619 { Q_STATS_OFFSET32(mbuf_alloc_tpa),
620 4, "mbuf_alloc_tpa"},
621 { Q_STATS_OFFSET32(tx_queue_full_return),
622 4, "tx_queue_full_return"},
623 { Q_STATS_OFFSET32(bxe_tx_mq_sc_state_failures),
624 4, "bxe_tx_mq_sc_state_failures"},
625 { Q_STATS_OFFSET32(tx_request_link_down_failures),
626 4, "tx_request_link_down_failures"},
627 { Q_STATS_OFFSET32(bd_avail_too_less_failures),
628 4, "bd_avail_too_less_failures"},
629 { Q_STATS_OFFSET32(tx_mq_not_empty),
630 4, "tx_mq_not_empty"},
631 { Q_STATS_OFFSET32(nsegs_path1_errors),
632 4, "nsegs_path1_errors"},
633 { Q_STATS_OFFSET32(nsegs_path2_errors),
634 4, "nsegs_path2_errors"}
635
636
637 };
638
639 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr)
640 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr)
641
642
643 static void bxe_cmng_fns_init(struct bxe_softc *sc,
644 uint8_t read_cfg,
645 uint8_t cmng_type);
646 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc);
647 static void storm_memset_cmng(struct bxe_softc *sc,
648 struct cmng_init *cmng,
649 uint8_t port);
650 static void bxe_set_reset_global(struct bxe_softc *sc);
651 static void bxe_set_reset_in_progress(struct bxe_softc *sc);
652 static uint8_t bxe_reset_is_done(struct bxe_softc *sc,
653 int engine);
654 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc);
655 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc,
656 uint8_t *global,
657 uint8_t print);
658 static void bxe_int_disable(struct bxe_softc *sc);
659 static int bxe_release_leader_lock(struct bxe_softc *sc);
660 static void bxe_pf_disable(struct bxe_softc *sc);
661 static void bxe_free_fp_buffers(struct bxe_softc *sc);
662 static inline void bxe_update_rx_prod(struct bxe_softc *sc,
663 struct bxe_fastpath *fp,
664 uint16_t rx_bd_prod,
665 uint16_t rx_cq_prod,
666 uint16_t rx_sge_prod);
667 static void bxe_link_report_locked(struct bxe_softc *sc);
668 static void bxe_link_report(struct bxe_softc *sc);
669 static void bxe_link_status_update(struct bxe_softc *sc);
670 static void bxe_periodic_callout_func(void *xsc);
671 static void bxe_periodic_start(struct bxe_softc *sc);
672 static void bxe_periodic_stop(struct bxe_softc *sc);
673 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
674 uint16_t prev_index,
675 uint16_t index);
676 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
677 int queue);
678 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
679 uint16_t index);
680 static uint8_t bxe_txeof(struct bxe_softc *sc,
681 struct bxe_fastpath *fp);
682 static void bxe_task_fp(struct bxe_fastpath *fp);
683 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc,
684 struct mbuf *m,
685 uint8_t contents);
686 static int bxe_alloc_mem(struct bxe_softc *sc);
687 static void bxe_free_mem(struct bxe_softc *sc);
688 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc);
689 static void bxe_free_fw_stats_mem(struct bxe_softc *sc);
690 static int bxe_interrupt_attach(struct bxe_softc *sc);
691 static void bxe_interrupt_detach(struct bxe_softc *sc);
692 static void bxe_set_rx_mode(struct bxe_softc *sc);
693 static int bxe_init_locked(struct bxe_softc *sc);
694 static int bxe_stop_locked(struct bxe_softc *sc);
695 static void bxe_sp_err_timeout_task(void *arg, int pending);
696 void bxe_parity_recover(struct bxe_softc *sc);
697 void bxe_handle_error(struct bxe_softc *sc);
698 static __noinline int bxe_nic_load(struct bxe_softc *sc,
699 int load_mode);
700 static __noinline int bxe_nic_unload(struct bxe_softc *sc,
701 uint32_t unload_mode,
702 uint8_t keep_link);
703
704 static void bxe_handle_sp_tq(void *context, int pending);
705 static void bxe_handle_fp_tq(void *context, int pending);
706
707 static int bxe_add_cdev(struct bxe_softc *sc);
708 static void bxe_del_cdev(struct bxe_softc *sc);
709 int bxe_grc_dump(struct bxe_softc *sc);
710 static int bxe_alloc_buf_rings(struct bxe_softc *sc);
711 static void bxe_free_buf_rings(struct bxe_softc *sc);
712
713 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */
714 uint32_t
calc_crc32(uint8_t * crc32_packet,uint32_t crc32_length,uint32_t crc32_seed,uint8_t complement)715 calc_crc32(uint8_t *crc32_packet,
716 uint32_t crc32_length,
717 uint32_t crc32_seed,
718 uint8_t complement)
719 {
720 uint32_t byte = 0;
721 uint32_t bit = 0;
722 uint8_t msb = 0;
723 uint32_t temp = 0;
724 uint32_t shft = 0;
725 uint8_t current_byte = 0;
726 uint32_t crc32_result = crc32_seed;
727 const uint32_t CRC32_POLY = 0x1edc6f41;
728
729 if ((crc32_packet == NULL) ||
730 (crc32_length == 0) ||
731 ((crc32_length % 8) != 0))
732 {
733 return (crc32_result);
734 }
735
736 for (byte = 0; byte < crc32_length; byte = byte + 1)
737 {
738 current_byte = crc32_packet[byte];
739 for (bit = 0; bit < 8; bit = bit + 1)
740 {
741 /* msb = crc32_result[31]; */
742 msb = (uint8_t)(crc32_result >> 31);
743
744 crc32_result = crc32_result << 1;
745
746 /* it (msb != current_byte[bit]) */
747 if (msb != (0x1 & (current_byte >> bit)))
748 {
749 crc32_result = crc32_result ^ CRC32_POLY;
750 /* crc32_result[0] = 1 */
751 crc32_result |= 1;
752 }
753 }
754 }
755
756 /* Last step is to:
757 * 1. "mirror" every bit
758 * 2. swap the 4 bytes
759 * 3. complement each bit
760 */
761
762 /* Mirror */
763 temp = crc32_result;
764 shft = sizeof(crc32_result) * 8 - 1;
765
766 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1)
767 {
768 temp <<= 1;
769 temp |= crc32_result & 1;
770 shft-- ;
771 }
772
773 /* temp[31-bit] = crc32_result[bit] */
774 temp <<= shft;
775
776 /* Swap */
777 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */
778 {
779 uint32_t t0, t1, t2, t3;
780 t0 = (0x000000ff & (temp >> 24));
781 t1 = (0x0000ff00 & (temp >> 8));
782 t2 = (0x00ff0000 & (temp << 8));
783 t3 = (0xff000000 & (temp << 24));
784 crc32_result = t0 | t1 | t2 | t3;
785 }
786
787 /* Complement */
788 if (complement)
789 {
790 crc32_result = ~crc32_result;
791 }
792
793 return (crc32_result);
794 }
795
796 int
bxe_test_bit(int nr,volatile unsigned long * addr)797 bxe_test_bit(int nr,
798 volatile unsigned long *addr)
799 {
800 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0);
801 }
802
803 void
bxe_set_bit(unsigned int nr,volatile unsigned long * addr)804 bxe_set_bit(unsigned int nr,
805 volatile unsigned long *addr)
806 {
807 atomic_set_acq_long(addr, (1 << nr));
808 }
809
810 void
bxe_clear_bit(int nr,volatile unsigned long * addr)811 bxe_clear_bit(int nr,
812 volatile unsigned long *addr)
813 {
814 atomic_clear_acq_long(addr, (1 << nr));
815 }
816
817 int
bxe_test_and_set_bit(int nr,volatile unsigned long * addr)818 bxe_test_and_set_bit(int nr,
819 volatile unsigned long *addr)
820 {
821 unsigned long x;
822 nr = (1 << nr);
823 do {
824 x = *addr;
825 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0);
826 // if (x & nr) bit_was_set; else bit_was_not_set;
827 return (x & nr);
828 }
829
830 int
bxe_test_and_clear_bit(int nr,volatile unsigned long * addr)831 bxe_test_and_clear_bit(int nr,
832 volatile unsigned long *addr)
833 {
834 unsigned long x;
835 nr = (1 << nr);
836 do {
837 x = *addr;
838 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0);
839 // if (x & nr) bit_was_set; else bit_was_not_set;
840 return (x & nr);
841 }
842
843 int
bxe_cmpxchg(volatile int * addr,int old,int new)844 bxe_cmpxchg(volatile int *addr,
845 int old,
846 int new)
847 {
848 int x;
849 do {
850 x = *addr;
851 } while (atomic_cmpset_acq_int(addr, old, new) == 0);
852 return (x);
853 }
854
855 /*
856 * Get DMA memory from the OS.
857 *
858 * Validates that the OS has provided DMA buffers in response to a
859 * bus_dmamap_load call and saves the physical address of those buffers.
860 * When the callback is used the OS will return 0 for the mapping function
861 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
862 * failures back to the caller.
863 *
864 * Returns:
865 * Nothing.
866 */
867 static void
bxe_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)868 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
869 {
870 struct bxe_dma *dma = arg;
871
872 if (error) {
873 dma->paddr = 0;
874 dma->nseg = 0;
875 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error);
876 } else {
877 dma->paddr = segs->ds_addr;
878 dma->nseg = nseg;
879 }
880 }
881
882 /*
883 * Allocate a block of memory and map it for DMA. No partial completions
884 * allowed and release any resources acquired if we can't acquire all
885 * resources.
886 *
887 * Returns:
888 * 0 = Success, !0 = Failure
889 */
890 int
bxe_dma_alloc(struct bxe_softc * sc,bus_size_t size,struct bxe_dma * dma,const char * msg)891 bxe_dma_alloc(struct bxe_softc *sc,
892 bus_size_t size,
893 struct bxe_dma *dma,
894 const char *msg)
895 {
896 int rc;
897
898 if (dma->size > 0) {
899 BLOGE(sc, "dma block '%s' already has size %lu\n", msg,
900 (unsigned long)dma->size);
901 return (1);
902 }
903
904 memset(dma, 0, sizeof(*dma)); /* sanity */
905 dma->sc = sc;
906 dma->size = size;
907 snprintf(dma->msg, sizeof(dma->msg), "%s", msg);
908
909 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
910 BCM_PAGE_SIZE, /* alignment */
911 0, /* boundary limit */
912 BUS_SPACE_MAXADDR, /* restricted low */
913 BUS_SPACE_MAXADDR, /* restricted hi */
914 NULL, /* addr filter() */
915 NULL, /* addr filter() arg */
916 size, /* max map size */
917 1, /* num discontinuous */
918 size, /* max seg size */
919 BUS_DMA_ALLOCNOW, /* flags */
920 NULL, /* lock() */
921 NULL, /* lock() arg */
922 &dma->tag); /* returned dma tag */
923 if (rc != 0) {
924 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc);
925 memset(dma, 0, sizeof(*dma));
926 return (1);
927 }
928
929 rc = bus_dmamem_alloc(dma->tag,
930 (void **)&dma->vaddr,
931 (BUS_DMA_NOWAIT | BUS_DMA_ZERO),
932 &dma->map);
933 if (rc != 0) {
934 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc);
935 bus_dma_tag_destroy(dma->tag);
936 memset(dma, 0, sizeof(*dma));
937 return (1);
938 }
939
940 rc = bus_dmamap_load(dma->tag,
941 dma->map,
942 dma->vaddr,
943 size,
944 bxe_dma_map_addr, /* BLOGD in here */
945 dma,
946 BUS_DMA_NOWAIT);
947 if (rc != 0) {
948 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc);
949 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
950 bus_dma_tag_destroy(dma->tag);
951 memset(dma, 0, sizeof(*dma));
952 return (1);
953 }
954
955 return (0);
956 }
957
958 void
bxe_dma_free(struct bxe_softc * sc,struct bxe_dma * dma)959 bxe_dma_free(struct bxe_softc *sc,
960 struct bxe_dma *dma)
961 {
962 if (dma->size > 0) {
963 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL"));
964
965 bus_dmamap_sync(dma->tag, dma->map,
966 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE));
967 bus_dmamap_unload(dma->tag, dma->map);
968 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
969 bus_dma_tag_destroy(dma->tag);
970 }
971
972 memset(dma, 0, sizeof(*dma));
973 }
974
975 /*
976 * These indirect read and write routines are only during init.
977 * The locking is handled by the MCP.
978 */
979
980 void
bxe_reg_wr_ind(struct bxe_softc * sc,uint32_t addr,uint32_t val)981 bxe_reg_wr_ind(struct bxe_softc *sc,
982 uint32_t addr,
983 uint32_t val)
984 {
985 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
986 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4);
987 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
988 }
989
990 uint32_t
bxe_reg_rd_ind(struct bxe_softc * sc,uint32_t addr)991 bxe_reg_rd_ind(struct bxe_softc *sc,
992 uint32_t addr)
993 {
994 uint32_t val;
995
996 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
997 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4);
998 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
999
1000 return (val);
1001 }
1002
1003 static int
bxe_acquire_hw_lock(struct bxe_softc * sc,uint32_t resource)1004 bxe_acquire_hw_lock(struct bxe_softc *sc,
1005 uint32_t resource)
1006 {
1007 uint32_t lock_status;
1008 uint32_t resource_bit = (1 << resource);
1009 int func = SC_FUNC(sc);
1010 uint32_t hw_lock_control_reg;
1011 int cnt;
1012
1013 /* validate the resource is within range */
1014 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1015 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1016 " resource_bit 0x%x\n", resource, resource_bit);
1017 return (-1);
1018 }
1019
1020 if (func <= 5) {
1021 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1022 } else {
1023 hw_lock_control_reg =
1024 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1025 }
1026
1027 /* validate the resource is not already taken */
1028 lock_status = REG_RD(sc, hw_lock_control_reg);
1029 if (lock_status & resource_bit) {
1030 BLOGE(sc, "resource (0x%x) in use (status 0x%x bit 0x%x)\n",
1031 resource, lock_status, resource_bit);
1032 return (-1);
1033 }
1034
1035 /* try every 5ms for 5 seconds */
1036 for (cnt = 0; cnt < 1000; cnt++) {
1037 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1038 lock_status = REG_RD(sc, hw_lock_control_reg);
1039 if (lock_status & resource_bit) {
1040 return (0);
1041 }
1042 DELAY(5000);
1043 }
1044
1045 BLOGE(sc, "Resource 0x%x resource_bit 0x%x lock timeout!\n",
1046 resource, resource_bit);
1047 return (-1);
1048 }
1049
1050 static int
bxe_release_hw_lock(struct bxe_softc * sc,uint32_t resource)1051 bxe_release_hw_lock(struct bxe_softc *sc,
1052 uint32_t resource)
1053 {
1054 uint32_t lock_status;
1055 uint32_t resource_bit = (1 << resource);
1056 int func = SC_FUNC(sc);
1057 uint32_t hw_lock_control_reg;
1058
1059 /* validate the resource is within range */
1060 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1061 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1062 " resource_bit 0x%x\n", resource, resource_bit);
1063 return (-1);
1064 }
1065
1066 if (func <= 5) {
1067 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1068 } else {
1069 hw_lock_control_reg =
1070 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1071 }
1072
1073 /* validate the resource is currently taken */
1074 lock_status = REG_RD(sc, hw_lock_control_reg);
1075 if (!(lock_status & resource_bit)) {
1076 BLOGE(sc, "resource (0x%x) not in use (status 0x%x bit 0x%x)\n",
1077 resource, lock_status, resource_bit);
1078 return (-1);
1079 }
1080
1081 REG_WR(sc, hw_lock_control_reg, resource_bit);
1082 return (0);
1083 }
bxe_acquire_phy_lock(struct bxe_softc * sc)1084 static void bxe_acquire_phy_lock(struct bxe_softc *sc)
1085 {
1086 BXE_PHY_LOCK(sc);
1087 bxe_acquire_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1088 }
1089
bxe_release_phy_lock(struct bxe_softc * sc)1090 static void bxe_release_phy_lock(struct bxe_softc *sc)
1091 {
1092 bxe_release_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1093 BXE_PHY_UNLOCK(sc);
1094 }
1095 /*
1096 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1097 * had we done things the other way around, if two pfs from the same port
1098 * would attempt to access nvram at the same time, we could run into a
1099 * scenario such as:
1100 * pf A takes the port lock.
1101 * pf B succeeds in taking the same lock since they are from the same port.
1102 * pf A takes the per pf misc lock. Performs eeprom access.
1103 * pf A finishes. Unlocks the per pf misc lock.
1104 * Pf B takes the lock and proceeds to perform it's own access.
1105 * pf A unlocks the per port lock, while pf B is still working (!).
1106 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1107 * access corrupted by pf B).*
1108 */
1109 static int
bxe_acquire_nvram_lock(struct bxe_softc * sc)1110 bxe_acquire_nvram_lock(struct bxe_softc *sc)
1111 {
1112 int port = SC_PORT(sc);
1113 int count, i;
1114 uint32_t val = 0;
1115
1116 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1117 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1118
1119 /* adjust timeout for emulation/FPGA */
1120 count = NVRAM_TIMEOUT_COUNT;
1121 if (CHIP_REV_IS_SLOW(sc)) {
1122 count *= 100;
1123 }
1124
1125 /* request access to nvram interface */
1126 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1127 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1128
1129 for (i = 0; i < count*10; i++) {
1130 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1131 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1132 break;
1133 }
1134
1135 DELAY(5);
1136 }
1137
1138 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1139 BLOGE(sc, "Cannot get access to nvram interface "
1140 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1141 port, val);
1142 return (-1);
1143 }
1144
1145 return (0);
1146 }
1147
1148 static int
bxe_release_nvram_lock(struct bxe_softc * sc)1149 bxe_release_nvram_lock(struct bxe_softc *sc)
1150 {
1151 int port = SC_PORT(sc);
1152 int count, i;
1153 uint32_t val = 0;
1154
1155 /* adjust timeout for emulation/FPGA */
1156 count = NVRAM_TIMEOUT_COUNT;
1157 if (CHIP_REV_IS_SLOW(sc)) {
1158 count *= 100;
1159 }
1160
1161 /* relinquish nvram interface */
1162 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1163 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1164
1165 for (i = 0; i < count*10; i++) {
1166 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1167 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1168 break;
1169 }
1170
1171 DELAY(5);
1172 }
1173
1174 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1175 BLOGE(sc, "Cannot free access to nvram interface "
1176 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1177 port, val);
1178 return (-1);
1179 }
1180
1181 /* release HW lock: protect against other PFs in PF Direct Assignment */
1182 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1183
1184 return (0);
1185 }
1186
1187 static void
bxe_enable_nvram_access(struct bxe_softc * sc)1188 bxe_enable_nvram_access(struct bxe_softc *sc)
1189 {
1190 uint32_t val;
1191
1192 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1193
1194 /* enable both bits, even on read */
1195 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1196 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
1197 }
1198
1199 static void
bxe_disable_nvram_access(struct bxe_softc * sc)1200 bxe_disable_nvram_access(struct bxe_softc *sc)
1201 {
1202 uint32_t val;
1203
1204 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1205
1206 /* disable both bits, even after read */
1207 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1208 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1209 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1210 }
1211
1212 static int
bxe_nvram_read_dword(struct bxe_softc * sc,uint32_t offset,uint32_t * ret_val,uint32_t cmd_flags)1213 bxe_nvram_read_dword(struct bxe_softc *sc,
1214 uint32_t offset,
1215 uint32_t *ret_val,
1216 uint32_t cmd_flags)
1217 {
1218 int count, i, rc;
1219 uint32_t val;
1220
1221 /* build the command word */
1222 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1223
1224 /* need to clear DONE bit separately */
1225 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1226
1227 /* address of the NVRAM to read from */
1228 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1229 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1230
1231 /* issue a read command */
1232 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1233
1234 /* adjust timeout for emulation/FPGA */
1235 count = NVRAM_TIMEOUT_COUNT;
1236 if (CHIP_REV_IS_SLOW(sc)) {
1237 count *= 100;
1238 }
1239
1240 /* wait for completion */
1241 *ret_val = 0;
1242 rc = -1;
1243 for (i = 0; i < count; i++) {
1244 DELAY(5);
1245 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1246
1247 if (val & MCPR_NVM_COMMAND_DONE) {
1248 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1249 /* we read nvram data in cpu order
1250 * but ethtool sees it as an array of bytes
1251 * converting to big-endian will do the work
1252 */
1253 *ret_val = htobe32(val);
1254 rc = 0;
1255 break;
1256 }
1257 }
1258
1259 if (rc == -1) {
1260 BLOGE(sc, "nvram read timeout expired "
1261 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1262 offset, cmd_flags, val);
1263 }
1264
1265 return (rc);
1266 }
1267
1268 static int
bxe_nvram_read(struct bxe_softc * sc,uint32_t offset,uint8_t * ret_buf,int buf_size)1269 bxe_nvram_read(struct bxe_softc *sc,
1270 uint32_t offset,
1271 uint8_t *ret_buf,
1272 int buf_size)
1273 {
1274 uint32_t cmd_flags;
1275 uint32_t val;
1276 int rc;
1277
1278 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1279 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1280 offset, buf_size);
1281 return (-1);
1282 }
1283
1284 if ((offset + buf_size) > sc->devinfo.flash_size) {
1285 BLOGE(sc, "Invalid parameter, "
1286 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1287 offset, buf_size, sc->devinfo.flash_size);
1288 return (-1);
1289 }
1290
1291 /* request access to nvram interface */
1292 rc = bxe_acquire_nvram_lock(sc);
1293 if (rc) {
1294 return (rc);
1295 }
1296
1297 /* enable access to nvram interface */
1298 bxe_enable_nvram_access(sc);
1299
1300 /* read the first word(s) */
1301 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1302 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1303 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1304 memcpy(ret_buf, &val, 4);
1305
1306 /* advance to the next dword */
1307 offset += sizeof(uint32_t);
1308 ret_buf += sizeof(uint32_t);
1309 buf_size -= sizeof(uint32_t);
1310 cmd_flags = 0;
1311 }
1312
1313 if (rc == 0) {
1314 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1315 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1316 memcpy(ret_buf, &val, 4);
1317 }
1318
1319 /* disable access to nvram interface */
1320 bxe_disable_nvram_access(sc);
1321 bxe_release_nvram_lock(sc);
1322
1323 return (rc);
1324 }
1325
1326 static int
bxe_nvram_write_dword(struct bxe_softc * sc,uint32_t offset,uint32_t val,uint32_t cmd_flags)1327 bxe_nvram_write_dword(struct bxe_softc *sc,
1328 uint32_t offset,
1329 uint32_t val,
1330 uint32_t cmd_flags)
1331 {
1332 int count, i, rc;
1333
1334 /* build the command word */
1335 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR);
1336
1337 /* need to clear DONE bit separately */
1338 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1339
1340 /* write the data */
1341 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
1342
1343 /* address of the NVRAM to write to */
1344 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1345 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1346
1347 /* issue the write command */
1348 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1349
1350 /* adjust timeout for emulation/FPGA */
1351 count = NVRAM_TIMEOUT_COUNT;
1352 if (CHIP_REV_IS_SLOW(sc)) {
1353 count *= 100;
1354 }
1355
1356 /* wait for completion */
1357 rc = -1;
1358 for (i = 0; i < count; i++) {
1359 DELAY(5);
1360 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1361 if (val & MCPR_NVM_COMMAND_DONE) {
1362 rc = 0;
1363 break;
1364 }
1365 }
1366
1367 if (rc == -1) {
1368 BLOGE(sc, "nvram write timeout expired "
1369 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1370 offset, cmd_flags, val);
1371 }
1372
1373 return (rc);
1374 }
1375
1376 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1377
1378 static int
bxe_nvram_write1(struct bxe_softc * sc,uint32_t offset,uint8_t * data_buf,int buf_size)1379 bxe_nvram_write1(struct bxe_softc *sc,
1380 uint32_t offset,
1381 uint8_t *data_buf,
1382 int buf_size)
1383 {
1384 uint32_t cmd_flags;
1385 uint32_t align_offset;
1386 uint32_t val;
1387 int rc;
1388
1389 if ((offset + buf_size) > sc->devinfo.flash_size) {
1390 BLOGE(sc, "Invalid parameter, "
1391 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1392 offset, buf_size, sc->devinfo.flash_size);
1393 return (-1);
1394 }
1395
1396 /* request access to nvram interface */
1397 rc = bxe_acquire_nvram_lock(sc);
1398 if (rc) {
1399 return (rc);
1400 }
1401
1402 /* enable access to nvram interface */
1403 bxe_enable_nvram_access(sc);
1404
1405 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1406 align_offset = (offset & ~0x03);
1407 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
1408
1409 if (rc == 0) {
1410 val &= ~(0xff << BYTE_OFFSET(offset));
1411 val |= (*data_buf << BYTE_OFFSET(offset));
1412
1413 /* nvram data is returned as an array of bytes
1414 * convert it back to cpu order
1415 */
1416 val = be32toh(val);
1417
1418 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
1419 }
1420
1421 /* disable access to nvram interface */
1422 bxe_disable_nvram_access(sc);
1423 bxe_release_nvram_lock(sc);
1424
1425 return (rc);
1426 }
1427
1428 static int
bxe_nvram_write(struct bxe_softc * sc,uint32_t offset,uint8_t * data_buf,int buf_size)1429 bxe_nvram_write(struct bxe_softc *sc,
1430 uint32_t offset,
1431 uint8_t *data_buf,
1432 int buf_size)
1433 {
1434 uint32_t cmd_flags;
1435 uint32_t val;
1436 uint32_t written_so_far;
1437 int rc;
1438
1439 if (buf_size == 1) {
1440 return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
1441 }
1442
1443 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) {
1444 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1445 offset, buf_size);
1446 return (-1);
1447 }
1448
1449 if (buf_size == 0) {
1450 return (0); /* nothing to do */
1451 }
1452
1453 if ((offset + buf_size) > sc->devinfo.flash_size) {
1454 BLOGE(sc, "Invalid parameter, "
1455 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1456 offset, buf_size, sc->devinfo.flash_size);
1457 return (-1);
1458 }
1459
1460 /* request access to nvram interface */
1461 rc = bxe_acquire_nvram_lock(sc);
1462 if (rc) {
1463 return (rc);
1464 }
1465
1466 /* enable access to nvram interface */
1467 bxe_enable_nvram_access(sc);
1468
1469 written_so_far = 0;
1470 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1471 while ((written_so_far < buf_size) && (rc == 0)) {
1472 if (written_so_far == (buf_size - sizeof(uint32_t))) {
1473 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1474 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) {
1475 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1476 } else if ((offset % NVRAM_PAGE_SIZE) == 0) {
1477 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1478 }
1479
1480 memcpy(&val, data_buf, 4);
1481
1482 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
1483
1484 /* advance to the next dword */
1485 offset += sizeof(uint32_t);
1486 data_buf += sizeof(uint32_t);
1487 written_so_far += sizeof(uint32_t);
1488 cmd_flags = 0;
1489 }
1490
1491 /* disable access to nvram interface */
1492 bxe_disable_nvram_access(sc);
1493 bxe_release_nvram_lock(sc);
1494
1495 return (rc);
1496 }
1497
1498 /* copy command into DMAE command memory and set DMAE command Go */
1499 void
bxe_post_dmae(struct bxe_softc * sc,struct dmae_cmd * dmae,int idx)1500 bxe_post_dmae(struct bxe_softc *sc,
1501 struct dmae_cmd *dmae,
1502 int idx)
1503 {
1504 uint32_t cmd_offset;
1505 int i;
1506
1507 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_cmd) * idx));
1508 for (i = 0; i < ((sizeof(struct dmae_cmd) / 4)); i++) {
1509 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1510 }
1511
1512 REG_WR(sc, dmae_reg_go_c[idx], 1);
1513 }
1514
1515 uint32_t
bxe_dmae_opcode_add_comp(uint32_t opcode,uint8_t comp_type)1516 bxe_dmae_opcode_add_comp(uint32_t opcode,
1517 uint8_t comp_type)
1518 {
1519 return (opcode | ((comp_type << DMAE_CMD_C_DST_SHIFT) |
1520 DMAE_CMD_C_TYPE_ENABLE));
1521 }
1522
1523 uint32_t
bxe_dmae_opcode_clr_src_reset(uint32_t opcode)1524 bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
1525 {
1526 return (opcode & ~DMAE_CMD_SRC_RESET);
1527 }
1528
1529 uint32_t
bxe_dmae_opcode(struct bxe_softc * sc,uint8_t src_type,uint8_t dst_type,uint8_t with_comp,uint8_t comp_type)1530 bxe_dmae_opcode(struct bxe_softc *sc,
1531 uint8_t src_type,
1532 uint8_t dst_type,
1533 uint8_t with_comp,
1534 uint8_t comp_type)
1535 {
1536 uint32_t opcode = 0;
1537
1538 opcode |= ((src_type << DMAE_CMD_SRC_SHIFT) |
1539 (dst_type << DMAE_CMD_DST_SHIFT));
1540
1541 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
1542
1543 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
1544
1545 opcode |= ((SC_VN(sc) << DMAE_CMD_E1HVN_SHIFT) |
1546 (SC_VN(sc) << DMAE_CMD_DST_VN_SHIFT));
1547
1548 opcode |= (DMAE_COM_SET_ERR << DMAE_CMD_ERR_POLICY_SHIFT);
1549
1550 #ifdef __BIG_ENDIAN
1551 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
1552 #else
1553 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
1554 #endif
1555
1556 if (with_comp) {
1557 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type);
1558 }
1559
1560 return (opcode);
1561 }
1562
1563 static void
bxe_prep_dmae_with_comp(struct bxe_softc * sc,struct dmae_cmd * dmae,uint8_t src_type,uint8_t dst_type)1564 bxe_prep_dmae_with_comp(struct bxe_softc *sc,
1565 struct dmae_cmd *dmae,
1566 uint8_t src_type,
1567 uint8_t dst_type)
1568 {
1569 memset(dmae, 0, sizeof(struct dmae_cmd));
1570
1571 /* set the opcode */
1572 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1573 TRUE, DMAE_COMP_PCI);
1574
1575 /* fill in the completion parameters */
1576 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1577 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1578 dmae->comp_val = DMAE_COMP_VAL;
1579 }
1580
1581 /* issue a DMAE command over the init channel and wait for completion */
1582 static int
bxe_issue_dmae_with_comp(struct bxe_softc * sc,struct dmae_cmd * dmae)1583 bxe_issue_dmae_with_comp(struct bxe_softc *sc,
1584 struct dmae_cmd *dmae)
1585 {
1586 uint32_t *wb_comp = BXE_SP(sc, wb_comp);
1587 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
1588
1589 BXE_DMAE_LOCK(sc);
1590
1591 /* reset completion */
1592 *wb_comp = 0;
1593
1594 /* post the command on the channel used for initializations */
1595 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1596
1597 /* wait for completion */
1598 DELAY(5);
1599
1600 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
1601 if (!timeout ||
1602 (sc->recovery_state != BXE_RECOVERY_DONE &&
1603 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) {
1604 BLOGE(sc, "DMAE timeout! *wb_comp 0x%x recovery_state 0x%x\n",
1605 *wb_comp, sc->recovery_state);
1606 BXE_DMAE_UNLOCK(sc);
1607 return (DMAE_TIMEOUT);
1608 }
1609
1610 timeout--;
1611 DELAY(50);
1612 }
1613
1614 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
1615 BLOGE(sc, "DMAE PCI error! *wb_comp 0x%x recovery_state 0x%x\n",
1616 *wb_comp, sc->recovery_state);
1617 BXE_DMAE_UNLOCK(sc);
1618 return (DMAE_PCI_ERROR);
1619 }
1620
1621 BXE_DMAE_UNLOCK(sc);
1622 return (0);
1623 }
1624
1625 void
bxe_read_dmae(struct bxe_softc * sc,uint32_t src_addr,uint32_t len32)1626 bxe_read_dmae(struct bxe_softc *sc,
1627 uint32_t src_addr,
1628 uint32_t len32)
1629 {
1630 struct dmae_cmd dmae;
1631 uint32_t *data;
1632 int i, rc;
1633
1634 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32));
1635
1636 if (!sc->dmae_ready) {
1637 data = BXE_SP(sc, wb_data[0]);
1638
1639 for (i = 0; i < len32; i++) {
1640 data[i] = (CHIP_IS_E1(sc)) ?
1641 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) :
1642 REG_RD(sc, (src_addr + (i * 4)));
1643 }
1644
1645 return;
1646 }
1647
1648 /* set opcode and fixed command fields */
1649 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1650
1651 /* fill in addresses and len */
1652 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1653 dmae.src_addr_hi = 0;
1654 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1655 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1656 dmae.len = len32;
1657
1658 /* issue the command and wait for completion */
1659 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1660 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1661 }
1662 }
1663
1664 void
bxe_write_dmae(struct bxe_softc * sc,bus_addr_t dma_addr,uint32_t dst_addr,uint32_t len32)1665 bxe_write_dmae(struct bxe_softc *sc,
1666 bus_addr_t dma_addr,
1667 uint32_t dst_addr,
1668 uint32_t len32)
1669 {
1670 struct dmae_cmd dmae;
1671 int rc;
1672
1673 if (!sc->dmae_ready) {
1674 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32));
1675
1676 if (CHIP_IS_E1(sc)) {
1677 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1678 } else {
1679 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1680 }
1681
1682 return;
1683 }
1684
1685 /* set opcode and fixed command fields */
1686 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1687
1688 /* fill in addresses and len */
1689 dmae.src_addr_lo = U64_LO(dma_addr);
1690 dmae.src_addr_hi = U64_HI(dma_addr);
1691 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1692 dmae.dst_addr_hi = 0;
1693 dmae.len = len32;
1694
1695 /* issue the command and wait for completion */
1696 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1697 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1698 }
1699 }
1700
1701 void
bxe_write_dmae_phys_len(struct bxe_softc * sc,bus_addr_t phys_addr,uint32_t addr,uint32_t len)1702 bxe_write_dmae_phys_len(struct bxe_softc *sc,
1703 bus_addr_t phys_addr,
1704 uint32_t addr,
1705 uint32_t len)
1706 {
1707 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
1708 int offset = 0;
1709
1710 while (len > dmae_wr_max) {
1711 bxe_write_dmae(sc,
1712 (phys_addr + offset), /* src DMA address */
1713 (addr + offset), /* dst GRC address */
1714 dmae_wr_max);
1715 offset += (dmae_wr_max * 4);
1716 len -= dmae_wr_max;
1717 }
1718
1719 bxe_write_dmae(sc,
1720 (phys_addr + offset), /* src DMA address */
1721 (addr + offset), /* dst GRC address */
1722 len);
1723 }
1724
1725 void
bxe_set_ctx_validation(struct bxe_softc * sc,struct eth_context * cxt,uint32_t cid)1726 bxe_set_ctx_validation(struct bxe_softc *sc,
1727 struct eth_context *cxt,
1728 uint32_t cid)
1729 {
1730 /* ustorm cxt validation */
1731 cxt->ustorm_ag_context.cdu_usage =
1732 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1733 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
1734 /* xcontext validation */
1735 cxt->xstorm_ag_context.cdu_reserved =
1736 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1737 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
1738 }
1739
1740 static void
bxe_storm_memset_hc_timeout(struct bxe_softc * sc,uint8_t port,uint8_t fw_sb_id,uint8_t sb_index,uint8_t ticks)1741 bxe_storm_memset_hc_timeout(struct bxe_softc *sc,
1742 uint8_t port,
1743 uint8_t fw_sb_id,
1744 uint8_t sb_index,
1745 uint8_t ticks)
1746 {
1747 uint32_t addr =
1748 (BAR_CSTRORM_INTMEM +
1749 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
1750
1751 REG_WR8(sc, addr, ticks);
1752
1753 BLOGD(sc, DBG_LOAD,
1754 "port %d fw_sb_id %d sb_index %d ticks %d\n",
1755 port, fw_sb_id, sb_index, ticks);
1756 }
1757
1758 static void
bxe_storm_memset_hc_disable(struct bxe_softc * sc,uint8_t port,uint16_t fw_sb_id,uint8_t sb_index,uint8_t disable)1759 bxe_storm_memset_hc_disable(struct bxe_softc *sc,
1760 uint8_t port,
1761 uint16_t fw_sb_id,
1762 uint8_t sb_index,
1763 uint8_t disable)
1764 {
1765 uint32_t enable_flag =
1766 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
1767 uint32_t addr =
1768 (BAR_CSTRORM_INTMEM +
1769 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
1770 uint8_t flags;
1771
1772 /* clear and set */
1773 flags = REG_RD8(sc, addr);
1774 flags &= ~HC_INDEX_DATA_HC_ENABLED;
1775 flags |= enable_flag;
1776 REG_WR8(sc, addr, flags);
1777
1778 BLOGD(sc, DBG_LOAD,
1779 "port %d fw_sb_id %d sb_index %d disable %d\n",
1780 port, fw_sb_id, sb_index, disable);
1781 }
1782
1783 void
bxe_update_coalesce_sb_index(struct bxe_softc * sc,uint8_t fw_sb_id,uint8_t sb_index,uint8_t disable,uint16_t usec)1784 bxe_update_coalesce_sb_index(struct bxe_softc *sc,
1785 uint8_t fw_sb_id,
1786 uint8_t sb_index,
1787 uint8_t disable,
1788 uint16_t usec)
1789 {
1790 int port = SC_PORT(sc);
1791 uint8_t ticks = (usec / 4); /* XXX ??? */
1792
1793 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks);
1794
1795 disable = (disable) ? 1 : ((usec) ? 0 : 1);
1796 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable);
1797 }
1798
1799 void
elink_cb_udelay(struct bxe_softc * sc,uint32_t usecs)1800 elink_cb_udelay(struct bxe_softc *sc,
1801 uint32_t usecs)
1802 {
1803 DELAY(usecs);
1804 }
1805
1806 uint32_t
elink_cb_reg_read(struct bxe_softc * sc,uint32_t reg_addr)1807 elink_cb_reg_read(struct bxe_softc *sc,
1808 uint32_t reg_addr)
1809 {
1810 return (REG_RD(sc, reg_addr));
1811 }
1812
1813 void
elink_cb_reg_write(struct bxe_softc * sc,uint32_t reg_addr,uint32_t val)1814 elink_cb_reg_write(struct bxe_softc *sc,
1815 uint32_t reg_addr,
1816 uint32_t val)
1817 {
1818 REG_WR(sc, reg_addr, val);
1819 }
1820
1821 void
elink_cb_reg_wb_write(struct bxe_softc * sc,uint32_t offset,uint32_t * wb_write,uint16_t len)1822 elink_cb_reg_wb_write(struct bxe_softc *sc,
1823 uint32_t offset,
1824 uint32_t *wb_write,
1825 uint16_t len)
1826 {
1827 REG_WR_DMAE(sc, offset, wb_write, len);
1828 }
1829
1830 void
elink_cb_reg_wb_read(struct bxe_softc * sc,uint32_t offset,uint32_t * wb_write,uint16_t len)1831 elink_cb_reg_wb_read(struct bxe_softc *sc,
1832 uint32_t offset,
1833 uint32_t *wb_write,
1834 uint16_t len)
1835 {
1836 REG_RD_DMAE(sc, offset, wb_write, len);
1837 }
1838
1839 uint8_t
elink_cb_path_id(struct bxe_softc * sc)1840 elink_cb_path_id(struct bxe_softc *sc)
1841 {
1842 return (SC_PATH(sc));
1843 }
1844
1845 void
elink_cb_event_log(struct bxe_softc * sc,const elink_log_id_t elink_log_id,...)1846 elink_cb_event_log(struct bxe_softc *sc,
1847 const elink_log_id_t elink_log_id,
1848 ...)
1849 {
1850 /* XXX */
1851 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id);
1852 }
1853
1854 static int
bxe_set_spio(struct bxe_softc * sc,int spio,uint32_t mode)1855 bxe_set_spio(struct bxe_softc *sc,
1856 int spio,
1857 uint32_t mode)
1858 {
1859 uint32_t spio_reg;
1860
1861 /* Only 2 SPIOs are configurable */
1862 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
1863 BLOGE(sc, "Invalid SPIO 0x%x mode 0x%x\n", spio, mode);
1864 return (-1);
1865 }
1866
1867 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1868
1869 /* read SPIO and mask except the float bits */
1870 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
1871
1872 switch (mode) {
1873 case MISC_SPIO_OUTPUT_LOW:
1874 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio);
1875 /* clear FLOAT and set CLR */
1876 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1877 spio_reg |= (spio << MISC_SPIO_CLR_POS);
1878 break;
1879
1880 case MISC_SPIO_OUTPUT_HIGH:
1881 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio);
1882 /* clear FLOAT and set SET */
1883 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1884 spio_reg |= (spio << MISC_SPIO_SET_POS);
1885 break;
1886
1887 case MISC_SPIO_INPUT_HI_Z:
1888 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio);
1889 /* set FLOAT */
1890 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
1891 break;
1892
1893 default:
1894 break;
1895 }
1896
1897 REG_WR(sc, MISC_REG_SPIO, spio_reg);
1898 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1899
1900 return (0);
1901 }
1902
1903 static int
bxe_gpio_read(struct bxe_softc * sc,int gpio_num,uint8_t port)1904 bxe_gpio_read(struct bxe_softc *sc,
1905 int gpio_num,
1906 uint8_t port)
1907 {
1908 /* The GPIO should be swapped if swap register is set and active */
1909 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1910 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1911 int gpio_shift = (gpio_num +
1912 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1913 uint32_t gpio_mask = (1 << gpio_shift);
1914 uint32_t gpio_reg;
1915
1916 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1917 BLOGE(sc, "Invalid GPIO %d port 0x%x gpio_port %d gpio_shift %d"
1918 " gpio_mask 0x%x\n", gpio_num, port, gpio_port, gpio_shift,
1919 gpio_mask);
1920 return (-1);
1921 }
1922
1923 /* read GPIO value */
1924 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
1925
1926 /* get the requested pin value */
1927 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
1928 }
1929
1930 static int
bxe_gpio_write(struct bxe_softc * sc,int gpio_num,uint32_t mode,uint8_t port)1931 bxe_gpio_write(struct bxe_softc *sc,
1932 int gpio_num,
1933 uint32_t mode,
1934 uint8_t port)
1935 {
1936 /* The GPIO should be swapped if swap register is set and active */
1937 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1938 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1939 int gpio_shift = (gpio_num +
1940 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1941 uint32_t gpio_mask = (1 << gpio_shift);
1942 uint32_t gpio_reg;
1943
1944 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1945 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
1946 " gpio_shift %d gpio_mask 0x%x\n",
1947 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
1948 return (-1);
1949 }
1950
1951 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1952
1953 /* read GPIO and mask except the float bits */
1954 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1955
1956 switch (mode) {
1957 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1958 BLOGD(sc, DBG_PHY,
1959 "Set GPIO %d (shift %d) -> output low\n",
1960 gpio_num, gpio_shift);
1961 /* clear FLOAT and set CLR */
1962 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1963 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1964 break;
1965
1966 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1967 BLOGD(sc, DBG_PHY,
1968 "Set GPIO %d (shift %d) -> output high\n",
1969 gpio_num, gpio_shift);
1970 /* clear FLOAT and set SET */
1971 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1972 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1973 break;
1974
1975 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1976 BLOGD(sc, DBG_PHY,
1977 "Set GPIO %d (shift %d) -> input\n",
1978 gpio_num, gpio_shift);
1979 /* set FLOAT */
1980 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1981 break;
1982
1983 default:
1984 break;
1985 }
1986
1987 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
1988 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1989
1990 return (0);
1991 }
1992
1993 static int
bxe_gpio_mult_write(struct bxe_softc * sc,uint8_t pins,uint32_t mode)1994 bxe_gpio_mult_write(struct bxe_softc *sc,
1995 uint8_t pins,
1996 uint32_t mode)
1997 {
1998 uint32_t gpio_reg;
1999
2000 /* any port swapping should be handled by caller */
2001
2002 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2003
2004 /* read GPIO and mask except the float bits */
2005 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2006 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2007 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2008 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2009
2010 switch (mode) {
2011 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2012 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins);
2013 /* set CLR */
2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2015 break;
2016
2017 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2018 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins);
2019 /* set SET */
2020 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2021 break;
2022
2023 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2024 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins);
2025 /* set FLOAT */
2026 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2027 break;
2028
2029 default:
2030 BLOGE(sc, "Invalid GPIO mode assignment pins 0x%x mode 0x%x"
2031 " gpio_reg 0x%x\n", pins, mode, gpio_reg);
2032 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2033 return (-1);
2034 }
2035
2036 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2037 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2038
2039 return (0);
2040 }
2041
2042 static int
bxe_gpio_int_write(struct bxe_softc * sc,int gpio_num,uint32_t mode,uint8_t port)2043 bxe_gpio_int_write(struct bxe_softc *sc,
2044 int gpio_num,
2045 uint32_t mode,
2046 uint8_t port)
2047 {
2048 /* The GPIO should be swapped if swap register is set and active */
2049 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2050 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2051 int gpio_shift = (gpio_num +
2052 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2053 uint32_t gpio_mask = (1 << gpio_shift);
2054 uint32_t gpio_reg;
2055
2056 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2057 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
2058 " gpio_shift %d gpio_mask 0x%x\n",
2059 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
2060 return (-1);
2061 }
2062
2063 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2064
2065 /* read GPIO int */
2066 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
2067
2068 switch (mode) {
2069 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2070 BLOGD(sc, DBG_PHY,
2071 "Clear GPIO INT %d (shift %d) -> output low\n",
2072 gpio_num, gpio_shift);
2073 /* clear SET and set CLR */
2074 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2075 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2076 break;
2077
2078 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2079 BLOGD(sc, DBG_PHY,
2080 "Set GPIO INT %d (shift %d) -> output high\n",
2081 gpio_num, gpio_shift);
2082 /* clear CLR and set SET */
2083 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2084 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2085 break;
2086
2087 default:
2088 break;
2089 }
2090
2091 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
2092 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2093
2094 return (0);
2095 }
2096
2097 uint32_t
elink_cb_gpio_read(struct bxe_softc * sc,uint16_t gpio_num,uint8_t port)2098 elink_cb_gpio_read(struct bxe_softc *sc,
2099 uint16_t gpio_num,
2100 uint8_t port)
2101 {
2102 return (bxe_gpio_read(sc, gpio_num, port));
2103 }
2104
2105 uint8_t
elink_cb_gpio_write(struct bxe_softc * sc,uint16_t gpio_num,uint8_t mode,uint8_t port)2106 elink_cb_gpio_write(struct bxe_softc *sc,
2107 uint16_t gpio_num,
2108 uint8_t mode, /* 0=low 1=high */
2109 uint8_t port)
2110 {
2111 return (bxe_gpio_write(sc, gpio_num, mode, port));
2112 }
2113
2114 uint8_t
elink_cb_gpio_mult_write(struct bxe_softc * sc,uint8_t pins,uint8_t mode)2115 elink_cb_gpio_mult_write(struct bxe_softc *sc,
2116 uint8_t pins,
2117 uint8_t mode) /* 0=low 1=high */
2118 {
2119 return (bxe_gpio_mult_write(sc, pins, mode));
2120 }
2121
2122 uint8_t
elink_cb_gpio_int_write(struct bxe_softc * sc,uint16_t gpio_num,uint8_t mode,uint8_t port)2123 elink_cb_gpio_int_write(struct bxe_softc *sc,
2124 uint16_t gpio_num,
2125 uint8_t mode, /* 0=low 1=high */
2126 uint8_t port)
2127 {
2128 return (bxe_gpio_int_write(sc, gpio_num, mode, port));
2129 }
2130
2131 void
elink_cb_notify_link_changed(struct bxe_softc * sc)2132 elink_cb_notify_link_changed(struct bxe_softc *sc)
2133 {
2134 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
2135 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
2136 }
2137
2138 /* send the MCP a request, block until there is a reply */
2139 uint32_t
elink_cb_fw_command(struct bxe_softc * sc,uint32_t command,uint32_t param)2140 elink_cb_fw_command(struct bxe_softc *sc,
2141 uint32_t command,
2142 uint32_t param)
2143 {
2144 int mb_idx = SC_FW_MB_IDX(sc);
2145 uint32_t seq;
2146 uint32_t rc = 0;
2147 uint32_t cnt = 1;
2148 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
2149
2150 BXE_FWMB_LOCK(sc);
2151
2152 seq = ++sc->fw_seq;
2153 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
2154 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
2155
2156 BLOGD(sc, DBG_PHY,
2157 "wrote command 0x%08x to FW MB param 0x%08x\n",
2158 (command | seq), param);
2159
2160 /* Let the FW do it's magic. GIve it up to 5 seconds... */
2161 do {
2162 DELAY(delay * 1000);
2163 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
2164 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2165
2166 BLOGD(sc, DBG_PHY,
2167 "[after %d ms] read 0x%x seq 0x%x from FW MB\n",
2168 cnt*delay, rc, seq);
2169
2170 /* is this a reply to our command? */
2171 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
2172 rc &= FW_MSG_CODE_MASK;
2173 } else {
2174 /* Ruh-roh! */
2175 BLOGE(sc, "FW failed to respond!\n");
2176 // XXX bxe_fw_dump(sc);
2177 rc = 0;
2178 }
2179
2180 BXE_FWMB_UNLOCK(sc);
2181 return (rc);
2182 }
2183
2184 static uint32_t
bxe_fw_command(struct bxe_softc * sc,uint32_t command,uint32_t param)2185 bxe_fw_command(struct bxe_softc *sc,
2186 uint32_t command,
2187 uint32_t param)
2188 {
2189 return (elink_cb_fw_command(sc, command, param));
2190 }
2191
2192 static void
__storm_memset_dma_mapping(struct bxe_softc * sc,uint32_t addr,bus_addr_t mapping)2193 __storm_memset_dma_mapping(struct bxe_softc *sc,
2194 uint32_t addr,
2195 bus_addr_t mapping)
2196 {
2197 REG_WR(sc, addr, U64_LO(mapping));
2198 REG_WR(sc, (addr + 4), U64_HI(mapping));
2199 }
2200
2201 static void
storm_memset_spq_addr(struct bxe_softc * sc,bus_addr_t mapping,uint16_t abs_fid)2202 storm_memset_spq_addr(struct bxe_softc *sc,
2203 bus_addr_t mapping,
2204 uint16_t abs_fid)
2205 {
2206 uint32_t addr = (XSEM_REG_FAST_MEMORY +
2207 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
2208 __storm_memset_dma_mapping(sc, addr, mapping);
2209 }
2210
2211 static void
storm_memset_vf_to_pf(struct bxe_softc * sc,uint16_t abs_fid,uint16_t pf_id)2212 storm_memset_vf_to_pf(struct bxe_softc *sc,
2213 uint16_t abs_fid,
2214 uint16_t pf_id)
2215 {
2216 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2217 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2218 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2219 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2220 }
2221
2222 static void
storm_memset_func_en(struct bxe_softc * sc,uint16_t abs_fid,uint8_t enable)2223 storm_memset_func_en(struct bxe_softc *sc,
2224 uint16_t abs_fid,
2225 uint8_t enable)
2226 {
2227 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2228 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2229 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2230 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2231 }
2232
2233 static void
storm_memset_eq_data(struct bxe_softc * sc,struct event_ring_data * eq_data,uint16_t pfid)2234 storm_memset_eq_data(struct bxe_softc *sc,
2235 struct event_ring_data *eq_data,
2236 uint16_t pfid)
2237 {
2238 uint32_t addr;
2239 size_t size;
2240
2241 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
2242 size = sizeof(struct event_ring_data);
2243 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data);
2244 }
2245
2246 static void
storm_memset_eq_prod(struct bxe_softc * sc,uint16_t eq_prod,uint16_t pfid)2247 storm_memset_eq_prod(struct bxe_softc *sc,
2248 uint16_t eq_prod,
2249 uint16_t pfid)
2250 {
2251 uint32_t addr = (BAR_CSTRORM_INTMEM +
2252 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
2253 REG_WR16(sc, addr, eq_prod);
2254 }
2255
2256 /*
2257 * Post a slowpath command.
2258 *
2259 * A slowpath command is used to propagate a configuration change through
2260 * the controller in a controlled manner, allowing each STORM processor and
2261 * other H/W blocks to phase in the change. The commands sent on the
2262 * slowpath are referred to as ramrods. Depending on the ramrod used the
2263 * completion of the ramrod will occur in different ways. Here's a
2264 * breakdown of ramrods and how they complete:
2265 *
2266 * RAMROD_CMD_ID_ETH_PORT_SETUP
2267 * Used to setup the leading connection on a port. Completes on the
2268 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
2269 *
2270 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
2271 * Used to setup an additional connection on a port. Completes on the
2272 * RCQ of the multi-queue/RSS connection being initialized.
2273 *
2274 * RAMROD_CMD_ID_ETH_STAT_QUERY
2275 * Used to force the storm processors to update the statistics database
2276 * in host memory. This ramrod is send on the leading connection CID and
2277 * completes as an index increment of the CSTORM on the default status
2278 * block.
2279 *
2280 * RAMROD_CMD_ID_ETH_UPDATE
2281 * Used to update the state of the leading connection, usually to udpate
2282 * the RSS indirection table. Completes on the RCQ of the leading
2283 * connection. (Not currently used under FreeBSD until OS support becomes
2284 * available.)
2285 *
2286 * RAMROD_CMD_ID_ETH_HALT
2287 * Used when tearing down a connection prior to driver unload. Completes
2288 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
2289 * use this on the leading connection.
2290 *
2291 * RAMROD_CMD_ID_ETH_SET_MAC
2292 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
2293 * the RCQ of the leading connection.
2294 *
2295 * RAMROD_CMD_ID_ETH_CFC_DEL
2296 * Used when tearing down a conneciton prior to driver unload. Completes
2297 * on the RCQ of the leading connection (since the current connection
2298 * has been completely removed from controller memory).
2299 *
2300 * RAMROD_CMD_ID_ETH_PORT_DEL
2301 * Used to tear down the leading connection prior to driver unload,
2302 * typically fp[0]. Completes as an index increment of the CSTORM on the
2303 * default status block.
2304 *
2305 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
2306 * Used for connection offload. Completes on the RCQ of the multi-queue
2307 * RSS connection that is being offloaded. (Not currently used under
2308 * FreeBSD.)
2309 *
2310 * There can only be one command pending per function.
2311 *
2312 * Returns:
2313 * 0 = Success, !0 = Failure.
2314 */
2315
2316 /* must be called under the spq lock */
2317 static inline
bxe_sp_get_next(struct bxe_softc * sc)2318 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc)
2319 {
2320 struct eth_spe *next_spe = sc->spq_prod_bd;
2321
2322 if (sc->spq_prod_bd == sc->spq_last_bd) {
2323 /* wrap back to the first eth_spq */
2324 sc->spq_prod_bd = sc->spq;
2325 sc->spq_prod_idx = 0;
2326 } else {
2327 sc->spq_prod_bd++;
2328 sc->spq_prod_idx++;
2329 }
2330
2331 return (next_spe);
2332 }
2333
2334 /* must be called under the spq lock */
2335 static inline
bxe_sp_prod_update(struct bxe_softc * sc)2336 void bxe_sp_prod_update(struct bxe_softc *sc)
2337 {
2338 int func = SC_FUNC(sc);
2339
2340 /*
2341 * Make sure that BD data is updated before writing the producer.
2342 * BD data is written to the memory, the producer is read from the
2343 * memory, thus we need a full memory barrier to ensure the ordering.
2344 */
2345 mb();
2346
2347 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
2348 sc->spq_prod_idx);
2349
2350 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
2351 BUS_SPACE_BARRIER_WRITE);
2352 }
2353
2354 /**
2355 * bxe_is_contextless_ramrod - check if the current command ends on EQ
2356 *
2357 * @cmd: command to check
2358 * @cmd_type: command type
2359 */
2360 static inline
bxe_is_contextless_ramrod(int cmd,int cmd_type)2361 int bxe_is_contextless_ramrod(int cmd,
2362 int cmd_type)
2363 {
2364 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2365 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
2366 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2367 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2368 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2369 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2370 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
2371 return (TRUE);
2372 } else {
2373 return (FALSE);
2374 }
2375 }
2376
2377 /**
2378 * bxe_sp_post - place a single command on an SP ring
2379 *
2380 * @sc: driver handle
2381 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2382 * @cid: SW CID the command is related to
2383 * @data_hi: command private data address (high 32 bits)
2384 * @data_lo: command private data address (low 32 bits)
2385 * @cmd_type: command type (e.g. NONE, ETH)
2386 *
2387 * SP data is handled as if it's always an address pair, thus data fields are
2388 * not swapped to little endian in upper functions. Instead this function swaps
2389 * data as if it's two uint32 fields.
2390 */
2391 int
bxe_sp_post(struct bxe_softc * sc,int command,int cid,uint32_t data_hi,uint32_t data_lo,int cmd_type)2392 bxe_sp_post(struct bxe_softc *sc,
2393 int command,
2394 int cid,
2395 uint32_t data_hi,
2396 uint32_t data_lo,
2397 int cmd_type)
2398 {
2399 struct eth_spe *spe;
2400 uint16_t type;
2401 int common;
2402
2403 common = bxe_is_contextless_ramrod(command, cmd_type);
2404
2405 BXE_SP_LOCK(sc);
2406
2407 if (common) {
2408 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
2409 BLOGE(sc, "EQ ring is full!\n");
2410 BXE_SP_UNLOCK(sc);
2411 return (-1);
2412 }
2413 } else {
2414 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
2415 BLOGE(sc, "SPQ ring is full!\n");
2416 BXE_SP_UNLOCK(sc);
2417 return (-1);
2418 }
2419 }
2420
2421 spe = bxe_sp_get_next(sc);
2422
2423 /* CID needs port number to be encoded int it */
2424 spe->hdr.conn_and_cmd_data =
2425 htole32((command << SPE_HDR_T_CMD_ID_SHIFT) | HW_CID(sc, cid));
2426
2427 type = (cmd_type << SPE_HDR_T_CONN_TYPE_SHIFT) & SPE_HDR_T_CONN_TYPE;
2428
2429 /* TBD: Check if it works for VFs */
2430 type |= ((SC_FUNC(sc) << SPE_HDR_T_FUNCTION_ID_SHIFT) &
2431 SPE_HDR_T_FUNCTION_ID);
2432
2433 spe->hdr.type = htole16(type);
2434
2435 spe->data.update_data_addr.hi = htole32(data_hi);
2436 spe->data.update_data_addr.lo = htole32(data_lo);
2437
2438 /*
2439 * It's ok if the actual decrement is issued towards the memory
2440 * somewhere between the lock and unlock. Thus no more explict
2441 * memory barrier is needed.
2442 */
2443 if (common) {
2444 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
2445 } else {
2446 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
2447 }
2448
2449 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr);
2450 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n",
2451 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata));
2452 BLOGD(sc, DBG_SP,
2453 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n",
2454 sc->spq_prod_idx,
2455 (uint32_t)U64_HI(sc->spq_dma.paddr),
2456 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq),
2457 command,
2458 common,
2459 HW_CID(sc, cid),
2460 data_hi,
2461 data_lo,
2462 type,
2463 atomic_load_acq_long(&sc->cq_spq_left),
2464 atomic_load_acq_long(&sc->eq_spq_left));
2465
2466 bxe_sp_prod_update(sc);
2467
2468 BXE_SP_UNLOCK(sc);
2469 return (0);
2470 }
2471
2472 /**
2473 * bxe_debug_print_ind_table - prints the indirection table configuration.
2474 *
2475 * @sc: driver hanlde
2476 * @p: pointer to rss configuration
2477 */
2478
2479 /*
2480 * FreeBSD Device probe function.
2481 *
2482 * Compares the device found to the driver's list of supported devices and
2483 * reports back to the bsd loader whether this is the right driver for the device.
2484 * This is the driver entry function called from the "kldload" command.
2485 *
2486 * Returns:
2487 * BUS_PROBE_DEFAULT on success, positive value on failure.
2488 */
2489 static int
bxe_probe(device_t dev)2490 bxe_probe(device_t dev)
2491 {
2492 struct bxe_device_type *t;
2493 uint16_t did, sdid, svid, vid;
2494
2495 /* Find our device structure */
2496 t = bxe_devs;
2497
2498 /* Get the data for the device to be probed. */
2499 vid = pci_get_vendor(dev);
2500 did = pci_get_device(dev);
2501 svid = pci_get_subvendor(dev);
2502 sdid = pci_get_subdevice(dev);
2503
2504 /* Look through the list of known devices for a match. */
2505 while (t->bxe_name != NULL) {
2506 if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
2507 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
2508 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
2509 device_set_descf(dev,
2510 "%s (%c%d) BXE v:%s", t->bxe_name,
2511 (((pci_read_config(dev, PCIR_REVID, 4) &
2512 0xf0) >> 4) + 'A'),
2513 (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
2514 BXE_DRIVER_VERSION);
2515 return (BUS_PROBE_DEFAULT);
2516 }
2517 t++;
2518 }
2519
2520 return (ENXIO);
2521 }
2522
2523 static void
bxe_init_mutexes(struct bxe_softc * sc)2524 bxe_init_mutexes(struct bxe_softc *sc)
2525 {
2526 #ifdef BXE_CORE_LOCK_SX
2527 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name),
2528 "bxe%d_core_lock", sc->unit);
2529 sx_init(&sc->core_sx, sc->core_sx_name);
2530 #else
2531 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name),
2532 "bxe%d_core_lock", sc->unit);
2533 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF);
2534 #endif
2535
2536 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name),
2537 "bxe%d_sp_lock", sc->unit);
2538 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF);
2539
2540 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name),
2541 "bxe%d_dmae_lock", sc->unit);
2542 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF);
2543
2544 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name),
2545 "bxe%d_phy_lock", sc->unit);
2546 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF);
2547
2548 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name),
2549 "bxe%d_fwmb_lock", sc->unit);
2550 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF);
2551
2552 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name),
2553 "bxe%d_print_lock", sc->unit);
2554 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF);
2555
2556 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name),
2557 "bxe%d_stats_lock", sc->unit);
2558 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF);
2559
2560 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name),
2561 "bxe%d_mcast_lock", sc->unit);
2562 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF);
2563 }
2564
2565 static void
bxe_release_mutexes(struct bxe_softc * sc)2566 bxe_release_mutexes(struct bxe_softc *sc)
2567 {
2568 #ifdef BXE_CORE_LOCK_SX
2569 sx_destroy(&sc->core_sx);
2570 #else
2571 if (mtx_initialized(&sc->core_mtx)) {
2572 mtx_destroy(&sc->core_mtx);
2573 }
2574 #endif
2575
2576 if (mtx_initialized(&sc->sp_mtx)) {
2577 mtx_destroy(&sc->sp_mtx);
2578 }
2579
2580 if (mtx_initialized(&sc->dmae_mtx)) {
2581 mtx_destroy(&sc->dmae_mtx);
2582 }
2583
2584 if (mtx_initialized(&sc->port.phy_mtx)) {
2585 mtx_destroy(&sc->port.phy_mtx);
2586 }
2587
2588 if (mtx_initialized(&sc->fwmb_mtx)) {
2589 mtx_destroy(&sc->fwmb_mtx);
2590 }
2591
2592 if (mtx_initialized(&sc->print_mtx)) {
2593 mtx_destroy(&sc->print_mtx);
2594 }
2595
2596 if (mtx_initialized(&sc->stats_mtx)) {
2597 mtx_destroy(&sc->stats_mtx);
2598 }
2599
2600 if (mtx_initialized(&sc->mcast_mtx)) {
2601 mtx_destroy(&sc->mcast_mtx);
2602 }
2603 }
2604
2605 static void
bxe_tx_disable(struct bxe_softc * sc)2606 bxe_tx_disable(struct bxe_softc* sc)
2607 {
2608 if_t ifp = sc->ifp;
2609
2610 /* tell the stack the driver is stopped and TX queue is full */
2611 if (ifp != NULL) {
2612 if_setdrvflags(ifp, 0);
2613 }
2614 }
2615
2616 static void
bxe_drv_pulse(struct bxe_softc * sc)2617 bxe_drv_pulse(struct bxe_softc *sc)
2618 {
2619 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
2620 sc->fw_drv_pulse_wr_seq);
2621 }
2622
2623 static inline uint16_t
bxe_tx_avail(struct bxe_softc * sc,struct bxe_fastpath * fp)2624 bxe_tx_avail(struct bxe_softc *sc,
2625 struct bxe_fastpath *fp)
2626 {
2627 int16_t used;
2628 uint16_t prod;
2629 uint16_t cons;
2630
2631 prod = fp->tx_bd_prod;
2632 cons = fp->tx_bd_cons;
2633
2634 used = SUB_S16(prod, cons);
2635
2636 return (int16_t)(sc->tx_ring_size) - used;
2637 }
2638
2639 static inline int
bxe_tx_queue_has_work(struct bxe_fastpath * fp)2640 bxe_tx_queue_has_work(struct bxe_fastpath *fp)
2641 {
2642 uint16_t hw_cons;
2643
2644 mb(); /* status block fields can change */
2645 hw_cons = le16toh(*fp->tx_cons_sb);
2646 return (hw_cons != fp->tx_pkt_cons);
2647 }
2648
2649 static inline uint8_t
bxe_has_tx_work(struct bxe_fastpath * fp)2650 bxe_has_tx_work(struct bxe_fastpath *fp)
2651 {
2652 /* expand this for multi-cos if ever supported */
2653 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE;
2654 }
2655
2656 static inline int
bxe_has_rx_work(struct bxe_fastpath * fp)2657 bxe_has_rx_work(struct bxe_fastpath *fp)
2658 {
2659 uint16_t rx_cq_cons_sb;
2660
2661 mb(); /* status block fields can change */
2662 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
2663 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX)
2664 rx_cq_cons_sb++;
2665 return (fp->rx_cq_cons != rx_cq_cons_sb);
2666 }
2667
2668 static void
bxe_sp_event(struct bxe_softc * sc,struct bxe_fastpath * fp,union eth_rx_cqe * rr_cqe)2669 bxe_sp_event(struct bxe_softc *sc,
2670 struct bxe_fastpath *fp,
2671 union eth_rx_cqe *rr_cqe)
2672 {
2673 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2674 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2675 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
2676 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
2677
2678 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n",
2679 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type);
2680
2681 switch (command) {
2682 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
2683 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid);
2684 drv_cmd = ECORE_Q_CMD_UPDATE;
2685 break;
2686
2687 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
2688 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid);
2689 drv_cmd = ECORE_Q_CMD_SETUP;
2690 break;
2691
2692 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
2693 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
2694 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
2695 break;
2696
2697 case (RAMROD_CMD_ID_ETH_HALT):
2698 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid);
2699 drv_cmd = ECORE_Q_CMD_HALT;
2700 break;
2701
2702 case (RAMROD_CMD_ID_ETH_TERMINATE):
2703 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid);
2704 drv_cmd = ECORE_Q_CMD_TERMINATE;
2705 break;
2706
2707 case (RAMROD_CMD_ID_ETH_EMPTY):
2708 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid);
2709 drv_cmd = ECORE_Q_CMD_EMPTY;
2710 break;
2711
2712 default:
2713 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n",
2714 command, fp->index);
2715 return;
2716 }
2717
2718 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
2719 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
2720 /*
2721 * q_obj->complete_cmd() failure means that this was
2722 * an unexpected completion.
2723 *
2724 * In this case we don't want to increase the sc->spq_left
2725 * because apparently we haven't sent this command the first
2726 * place.
2727 */
2728 // bxe_panic(sc, ("Unexpected SP completion\n"));
2729 return;
2730 }
2731
2732 atomic_add_acq_long(&sc->cq_spq_left, 1);
2733
2734 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n",
2735 atomic_load_acq_long(&sc->cq_spq_left));
2736 }
2737
2738 /*
2739 * The current mbuf is part of an aggregation. Move the mbuf into the TPA
2740 * aggregation queue, put an empty mbuf back onto the receive chain, and mark
2741 * the current aggregation queue as in-progress.
2742 */
2743 static void
bxe_tpa_start(struct bxe_softc * sc,struct bxe_fastpath * fp,uint16_t queue,uint16_t cons,uint16_t prod,struct eth_fast_path_rx_cqe * cqe)2744 bxe_tpa_start(struct bxe_softc *sc,
2745 struct bxe_fastpath *fp,
2746 uint16_t queue,
2747 uint16_t cons,
2748 uint16_t prod,
2749 struct eth_fast_path_rx_cqe *cqe)
2750 {
2751 struct bxe_sw_rx_bd tmp_bd;
2752 struct bxe_sw_rx_bd *rx_buf;
2753 struct eth_rx_bd *rx_bd;
2754 int max_agg_queues __diagused;
2755 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
2756 uint16_t index;
2757
2758 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START "
2759 "cons=%d prod=%d\n",
2760 fp->index, queue, cons, prod);
2761
2762 max_agg_queues = MAX_AGG_QS(sc);
2763
2764 KASSERT((queue < max_agg_queues),
2765 ("fp[%02d] invalid aggr queue (%d >= %d)!",
2766 fp->index, queue, max_agg_queues));
2767
2768 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP),
2769 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!",
2770 fp->index, queue));
2771
2772 /* copy the existing mbuf and mapping from the TPA pool */
2773 tmp_bd = tpa_info->bd;
2774
2775 if (tmp_bd.m == NULL) {
2776 uint32_t *tmp;
2777
2778 tmp = (uint32_t *)cqe;
2779
2780 BLOGE(sc, "fp[%02d].tpa[%02d] cons[%d] prod[%d]mbuf not allocated!\n",
2781 fp->index, queue, cons, prod);
2782 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2783 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2784
2785 /* XXX Error handling? */
2786 return;
2787 }
2788
2789 /* change the TPA queue to the start state */
2790 tpa_info->state = BXE_TPA_STATE_START;
2791 tpa_info->placement_offset = cqe->placement_offset;
2792 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags);
2793 tpa_info->vlan_tag = le16toh(cqe->vlan_tag);
2794 tpa_info->len_on_bd = le16toh(cqe->len_on_bd);
2795
2796 fp->rx_tpa_queue_used |= (1 << queue);
2797
2798 /*
2799 * If all the buffer descriptors are filled with mbufs then fill in
2800 * the current consumer index with a new BD. Else if a maximum Rx
2801 * buffer limit is imposed then fill in the next producer index.
2802 */
2803 index = (sc->max_rx_bufs != RX_BD_USABLE) ?
2804 prod : cons;
2805
2806 /* move the received mbuf and mapping to TPA pool */
2807 tpa_info->bd = fp->rx_mbuf_chain[cons];
2808
2809 /* release any existing RX BD mbuf mappings */
2810 if (cons != index) {
2811 rx_buf = &fp->rx_mbuf_chain[cons];
2812
2813 if (rx_buf->m_map != NULL) {
2814 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
2815 BUS_DMASYNC_POSTREAD);
2816 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
2817 }
2818
2819 /*
2820 * We get here when the maximum number of rx buffers is less than
2821 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL
2822 * it out here without concern of a memory leak.
2823 */
2824 fp->rx_mbuf_chain[cons].m = NULL;
2825 }
2826
2827 /* update the Rx SW BD with the mbuf info from the TPA pool */
2828 fp->rx_mbuf_chain[index] = tmp_bd;
2829
2830 /* update the Rx BD with the empty mbuf phys address from the TPA pool */
2831 rx_bd = &fp->rx_chain[index];
2832 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr));
2833 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr));
2834 }
2835
2836 /*
2837 * When a TPA aggregation is completed, loop through the individual mbufs
2838 * of the aggregation, combining them into a single mbuf which will be sent
2839 * up the stack. Refill all freed SGEs with mbufs as we go along.
2840 */
2841 static int
bxe_fill_frag_mbuf(struct bxe_softc * sc,struct bxe_fastpath * fp,struct bxe_sw_tpa_info * tpa_info,uint16_t queue,uint16_t pages,struct mbuf * m,struct eth_end_agg_rx_cqe * cqe,uint16_t cqe_idx)2842 bxe_fill_frag_mbuf(struct bxe_softc *sc,
2843 struct bxe_fastpath *fp,
2844 struct bxe_sw_tpa_info *tpa_info,
2845 uint16_t queue,
2846 uint16_t pages,
2847 struct mbuf *m,
2848 struct eth_end_agg_rx_cqe *cqe,
2849 uint16_t cqe_idx)
2850 {
2851 struct mbuf *m_frag;
2852 uint32_t frag_len, frag_size, i;
2853 uint16_t sge_idx;
2854 int rc = 0;
2855 int j;
2856
2857 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd;
2858
2859 BLOGD(sc, DBG_LRO,
2860 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n",
2861 fp->index, queue, tpa_info->len_on_bd, frag_size, pages);
2862
2863 /* make sure the aggregated frame is not too big to handle */
2864 if (pages > 8 * PAGES_PER_SGE) {
2865
2866 uint32_t *tmp = (uint32_t *)cqe;
2867
2868 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! "
2869 "pkt_len=%d len_on_bd=%d frag_size=%d\n",
2870 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len),
2871 tpa_info->len_on_bd, frag_size);
2872
2873 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2874 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2875
2876 bxe_panic(sc, ("sge page count error\n"));
2877 return (EINVAL);
2878 }
2879
2880 /*
2881 * Scan through the scatter gather list pulling individual mbufs into a
2882 * single mbuf for the host stack.
2883 */
2884 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
2885 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j]));
2886
2887 /*
2888 * Firmware gives the indices of the SGE as if the ring is an array
2889 * (meaning that the "next" element will consume 2 indices).
2890 */
2891 frag_len = min(frag_size, (uint32_t)(SGE_PAGES));
2892
2893 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d "
2894 "sge_idx=%d frag_size=%d frag_len=%d\n",
2895 fp->index, queue, i, j, sge_idx, frag_size, frag_len);
2896
2897 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
2898
2899 /* allocate a new mbuf for the SGE */
2900 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
2901 if (rc) {
2902 /* Leave all remaining SGEs in the ring! */
2903 return (rc);
2904 }
2905
2906 /* update the fragment length */
2907 m_frag->m_len = frag_len;
2908
2909 /* concatenate the fragment to the head mbuf */
2910 m_cat(m, m_frag);
2911 fp->eth_q_stats.mbuf_alloc_sge--;
2912
2913 /* update the TPA mbuf size and remaining fragment size */
2914 m->m_pkthdr.len += frag_len;
2915 frag_size -= frag_len;
2916 }
2917
2918 BLOGD(sc, DBG_LRO,
2919 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n",
2920 fp->index, queue, frag_size);
2921
2922 return (rc);
2923 }
2924
2925 static inline void
bxe_clear_sge_mask_next_elems(struct bxe_fastpath * fp)2926 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
2927 {
2928 int i, j;
2929
2930 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) {
2931 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1;
2932
2933 for (j = 0; j < 2; j++) {
2934 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
2935 idx--;
2936 }
2937 }
2938 }
2939
2940 static inline void
bxe_init_sge_ring_bit_mask(struct bxe_fastpath * fp)2941 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
2942 {
2943 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */
2944 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
2945
2946 /*
2947 * Clear the two last indices in the page to 1. These are the indices that
2948 * correspond to the "next" element, hence will never be indicated and
2949 * should be removed from the calculations.
2950 */
2951 bxe_clear_sge_mask_next_elems(fp);
2952 }
2953
2954 static inline void
bxe_update_last_max_sge(struct bxe_fastpath * fp,uint16_t idx)2955 bxe_update_last_max_sge(struct bxe_fastpath *fp,
2956 uint16_t idx)
2957 {
2958 uint16_t last_max = fp->last_max_sge;
2959
2960 if (SUB_S16(idx, last_max) > 0) {
2961 fp->last_max_sge = idx;
2962 }
2963 }
2964
2965 static inline void
bxe_update_sge_prod(struct bxe_softc * sc,struct bxe_fastpath * fp,uint16_t sge_len,union eth_sgl_or_raw_data * cqe)2966 bxe_update_sge_prod(struct bxe_softc *sc,
2967 struct bxe_fastpath *fp,
2968 uint16_t sge_len,
2969 union eth_sgl_or_raw_data *cqe)
2970 {
2971 uint16_t last_max, last_elem, first_elem;
2972 uint16_t delta = 0;
2973 uint16_t i;
2974
2975 if (!sge_len) {
2976 return;
2977 }
2978
2979 /* first mark all used pages */
2980 for (i = 0; i < sge_len; i++) {
2981 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
2982 RX_SGE(le16toh(cqe->sgl[i])));
2983 }
2984
2985 BLOGD(sc, DBG_LRO,
2986 "fp[%02d] fp_cqe->sgl[%d] = %d\n",
2987 fp->index, sge_len - 1,
2988 le16toh(cqe->sgl[sge_len - 1]));
2989
2990 /* assume that the last SGE index is the biggest */
2991 bxe_update_last_max_sge(fp,
2992 le16toh(cqe->sgl[sge_len - 1]));
2993
2994 last_max = RX_SGE(fp->last_max_sge);
2995 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
2996 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
2997
2998 /* if ring is not full */
2999 if (last_elem + 1 != first_elem) {
3000 last_elem++;
3001 }
3002
3003 /* now update the prod */
3004 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) {
3005 if (__predict_true(fp->sge_mask[i])) {
3006 break;
3007 }
3008
3009 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
3010 delta += BIT_VEC64_ELEM_SZ;
3011 }
3012
3013 if (delta > 0) {
3014 fp->rx_sge_prod += delta;
3015 /* clear page-end entries */
3016 bxe_clear_sge_mask_next_elems(fp);
3017 }
3018
3019 BLOGD(sc, DBG_LRO,
3020 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n",
3021 fp->index, fp->last_max_sge, fp->rx_sge_prod);
3022 }
3023
3024 /*
3025 * The aggregation on the current TPA queue has completed. Pull the individual
3026 * mbuf fragments together into a single mbuf, perform all necessary checksum
3027 * calculations, and send the resuting mbuf to the stack.
3028 */
3029 static void
bxe_tpa_stop(struct bxe_softc * sc,struct bxe_fastpath * fp,struct bxe_sw_tpa_info * tpa_info,uint16_t queue,uint16_t pages,struct eth_end_agg_rx_cqe * cqe,uint16_t cqe_idx)3030 bxe_tpa_stop(struct bxe_softc *sc,
3031 struct bxe_fastpath *fp,
3032 struct bxe_sw_tpa_info *tpa_info,
3033 uint16_t queue,
3034 uint16_t pages,
3035 struct eth_end_agg_rx_cqe *cqe,
3036 uint16_t cqe_idx)
3037 {
3038 if_t ifp = sc->ifp;
3039 struct mbuf *m;
3040 int rc = 0;
3041
3042 BLOGD(sc, DBG_LRO,
3043 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n",
3044 fp->index, queue, tpa_info->placement_offset,
3045 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag);
3046
3047 m = tpa_info->bd.m;
3048
3049 /* allocate a replacement before modifying existing mbuf */
3050 rc = bxe_alloc_rx_tpa_mbuf(fp, queue);
3051 if (rc) {
3052 /* drop the frame and log an error */
3053 fp->eth_q_stats.rx_soft_errors++;
3054 goto bxe_tpa_stop_exit;
3055 }
3056
3057 /* we have a replacement, fixup the current mbuf */
3058 m_adj(m, tpa_info->placement_offset);
3059 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd;
3060
3061 /* mark the checksums valid (taken care of by the firmware) */
3062 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3063 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3064 m->m_pkthdr.csum_data = 0xffff;
3065 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
3066 CSUM_IP_VALID |
3067 CSUM_DATA_VALID |
3068 CSUM_PSEUDO_HDR);
3069
3070 /* aggregate all of the SGEs into a single mbuf */
3071 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx);
3072 if (rc) {
3073 /* drop the packet and log an error */
3074 fp->eth_q_stats.rx_soft_errors++;
3075 m_freem(m);
3076 } else {
3077 if (tpa_info->parsing_flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3078 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag;
3079 m->m_flags |= M_VLANTAG;
3080 }
3081
3082 /* assign packet to this interface interface */
3083 if_setrcvif(m, ifp);
3084
3085 /* specify what RSS queue was used for this flow */
3086 m->m_pkthdr.flowid = fp->index;
3087 BXE_SET_FLOWID(m);
3088
3089 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3090 fp->eth_q_stats.rx_tpa_pkts++;
3091
3092 /* pass the frame to the stack */
3093 if_input(ifp, m);
3094 }
3095
3096 /* we passed an mbuf up the stack or dropped the frame */
3097 fp->eth_q_stats.mbuf_alloc_tpa--;
3098
3099 bxe_tpa_stop_exit:
3100
3101 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP;
3102 fp->rx_tpa_queue_used &= ~(1 << queue);
3103 }
3104
3105 static uint8_t
bxe_service_rxsgl(struct bxe_fastpath * fp,uint16_t len,uint16_t lenonbd,struct mbuf * m,struct eth_fast_path_rx_cqe * cqe_fp)3106 bxe_service_rxsgl(
3107 struct bxe_fastpath *fp,
3108 uint16_t len,
3109 uint16_t lenonbd,
3110 struct mbuf *m,
3111 struct eth_fast_path_rx_cqe *cqe_fp)
3112 {
3113 struct mbuf *m_frag;
3114 uint16_t frags, frag_len;
3115 uint16_t sge_idx = 0;
3116 uint16_t j;
3117 uint8_t i, rc = 0;
3118 uint32_t frag_size;
3119
3120 /* adjust the mbuf */
3121 m->m_len = lenonbd;
3122
3123 frag_size = len - lenonbd;
3124 frags = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3125
3126 for (i = 0, j = 0; i < frags; i += PAGES_PER_SGE, j++) {
3127 sge_idx = RX_SGE(le16toh(cqe_fp->sgl_or_raw_data.sgl[j]));
3128
3129 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
3130 frag_len = min(frag_size, (uint32_t)(SGE_PAGE_SIZE));
3131 m_frag->m_len = frag_len;
3132
3133 /* allocate a new mbuf for the SGE */
3134 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
3135 if (rc) {
3136 /* Leave all remaining SGEs in the ring! */
3137 return (rc);
3138 }
3139 fp->eth_q_stats.mbuf_alloc_sge--;
3140
3141 /* concatenate the fragment to the head mbuf */
3142 m_cat(m, m_frag);
3143
3144 frag_size -= frag_len;
3145 }
3146
3147 bxe_update_sge_prod(fp->sc, fp, frags, &cqe_fp->sgl_or_raw_data);
3148
3149 return rc;
3150 }
3151
3152 static uint8_t
bxe_rxeof(struct bxe_softc * sc,struct bxe_fastpath * fp)3153 bxe_rxeof(struct bxe_softc *sc,
3154 struct bxe_fastpath *fp)
3155 {
3156 if_t ifp = sc->ifp;
3157 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
3158 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
3159 int rx_pkts = 0;
3160 int rc = 0;
3161
3162 BXE_FP_RX_LOCK(fp);
3163
3164 /* CQ "next element" is of the size of the regular element */
3165 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
3166 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) {
3167 hw_cq_cons++;
3168 }
3169
3170 bd_cons = fp->rx_bd_cons;
3171 bd_prod = fp->rx_bd_prod;
3172 bd_prod_fw = bd_prod;
3173 sw_cq_cons = fp->rx_cq_cons;
3174 sw_cq_prod = fp->rx_cq_prod;
3175
3176 /*
3177 * Memory barrier necessary as speculative reads of the rx
3178 * buffer can be ahead of the index in the status block
3179 */
3180 rmb();
3181
3182 BLOGD(sc, DBG_RX,
3183 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n",
3184 fp->index, hw_cq_cons, sw_cq_cons);
3185
3186 while (sw_cq_cons != hw_cq_cons) {
3187 struct bxe_sw_rx_bd *rx_buf = NULL;
3188 union eth_rx_cqe *cqe;
3189 struct eth_fast_path_rx_cqe *cqe_fp;
3190 uint8_t cqe_fp_flags;
3191 enum eth_rx_cqe_type cqe_fp_type;
3192 uint16_t len, lenonbd, pad;
3193 struct mbuf *m = NULL;
3194
3195 comp_ring_cons = RCQ(sw_cq_cons);
3196 bd_prod = RX_BD(bd_prod);
3197 bd_cons = RX_BD(bd_cons);
3198
3199 cqe = &fp->rcq_chain[comp_ring_cons];
3200 cqe_fp = &cqe->fast_path_cqe;
3201 cqe_fp_flags = cqe_fp->type_error_flags;
3202 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
3203
3204 BLOGD(sc, DBG_RX,
3205 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d "
3206 "BD prod=%d cons=%d CQE type=0x%x err=0x%x "
3207 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u lenonbd=%u\n",
3208 fp->index,
3209 hw_cq_cons,
3210 sw_cq_cons,
3211 bd_prod,
3212 bd_cons,
3213 CQE_TYPE(cqe_fp_flags),
3214 cqe_fp_flags,
3215 cqe_fp->status_flags,
3216 le32toh(cqe_fp->rss_hash_result),
3217 le16toh(cqe_fp->vlan_tag),
3218 le16toh(cqe_fp->pkt_len_or_gro_seg_len),
3219 le16toh(cqe_fp->len_on_bd));
3220
3221 /* is this a slowpath msg? */
3222 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) {
3223 bxe_sp_event(sc, fp, cqe);
3224 goto next_cqe;
3225 }
3226
3227 rx_buf = &fp->rx_mbuf_chain[bd_cons];
3228
3229 if (!CQE_TYPE_FAST(cqe_fp_type)) {
3230 struct bxe_sw_tpa_info *tpa_info;
3231 uint16_t frag_size, pages;
3232 uint8_t queue;
3233
3234 if (CQE_TYPE_START(cqe_fp_type)) {
3235 bxe_tpa_start(sc, fp, cqe_fp->queue_index,
3236 bd_cons, bd_prod, cqe_fp);
3237 m = NULL; /* packet not ready yet */
3238 goto next_rx;
3239 }
3240
3241 KASSERT(CQE_TYPE_STOP(cqe_fp_type),
3242 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type));
3243
3244 queue = cqe->end_agg_cqe.queue_index;
3245 tpa_info = &fp->rx_tpa_info[queue];
3246
3247 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n",
3248 fp->index, queue);
3249
3250 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) -
3251 tpa_info->len_on_bd);
3252 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3253
3254 bxe_tpa_stop(sc, fp, tpa_info, queue, pages,
3255 &cqe->end_agg_cqe, comp_ring_cons);
3256
3257 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe.sgl_or_raw_data);
3258
3259 goto next_cqe;
3260 }
3261
3262 /* non TPA */
3263
3264 /* is this an error packet? */
3265 if (__predict_false(cqe_fp_flags &
3266 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
3267 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons);
3268 fp->eth_q_stats.rx_soft_errors++;
3269 goto next_rx;
3270 }
3271
3272 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len);
3273 lenonbd = le16toh(cqe_fp->len_on_bd);
3274 pad = cqe_fp->placement_offset;
3275
3276 m = rx_buf->m;
3277
3278 if (__predict_false(m == NULL)) {
3279 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n",
3280 bd_cons, fp->index);
3281 goto next_rx;
3282 }
3283
3284 /* XXX double copy if packet length under a threshold */
3285
3286 /*
3287 * If all the buffer descriptors are filled with mbufs then fill in
3288 * the current consumer index with a new BD. Else if a maximum Rx
3289 * buffer limit is imposed then fill in the next producer index.
3290 */
3291 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons,
3292 (sc->max_rx_bufs != RX_BD_USABLE) ?
3293 bd_prod : bd_cons);
3294 if (rc != 0) {
3295
3296 /* we simply reuse the received mbuf and don't post it to the stack */
3297 m = NULL;
3298
3299 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
3300 fp->index, rc);
3301 fp->eth_q_stats.rx_soft_errors++;
3302
3303 if (sc->max_rx_bufs != RX_BD_USABLE) {
3304 /* copy this consumer index to the producer index */
3305 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf,
3306 sizeof(struct bxe_sw_rx_bd));
3307 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd));
3308 }
3309
3310 goto next_rx;
3311 }
3312
3313 /* current mbuf was detached from the bd */
3314 fp->eth_q_stats.mbuf_alloc_rx--;
3315
3316 /* we allocated a replacement mbuf, fixup the current one */
3317 m_adj(m, pad);
3318 m->m_pkthdr.len = m->m_len = len;
3319
3320 if ((len > 60) && (len > lenonbd)) {
3321 fp->eth_q_stats.rx_bxe_service_rxsgl++;
3322 rc = bxe_service_rxsgl(fp, len, lenonbd, m, cqe_fp);
3323 if (rc)
3324 break;
3325 fp->eth_q_stats.rx_jumbo_sge_pkts++;
3326 } else if (lenonbd < len) {
3327 fp->eth_q_stats.rx_erroneous_jumbo_sge_pkts++;
3328 }
3329
3330 /* assign packet to this interface interface */
3331 if_setrcvif(m, ifp);
3332
3333 /* assume no hardware checksum has complated */
3334 m->m_pkthdr.csum_flags = 0;
3335
3336 /* validate checksum if offload enabled */
3337 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
3338 /* check for a valid IP frame */
3339 if (!(cqe->fast_path_cqe.status_flags &
3340 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
3341 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3342 if (__predict_false(cqe_fp_flags &
3343 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
3344 fp->eth_q_stats.rx_hw_csum_errors++;
3345 } else {
3346 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3347 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3348 }
3349 }
3350
3351 /* check for a valid TCP/UDP frame */
3352 if (!(cqe->fast_path_cqe.status_flags &
3353 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
3354 if (__predict_false(cqe_fp_flags &
3355 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
3356 fp->eth_q_stats.rx_hw_csum_errors++;
3357 } else {
3358 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3359 m->m_pkthdr.csum_data = 0xFFFF;
3360 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
3361 CSUM_PSEUDO_HDR);
3362 }
3363 }
3364 }
3365
3366 /* if there is a VLAN tag then flag that info */
3367 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3368 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag;
3369 m->m_flags |= M_VLANTAG;
3370 }
3371
3372 /* specify what RSS queue was used for this flow */
3373 m->m_pkthdr.flowid = fp->index;
3374 BXE_SET_FLOWID(m);
3375
3376 next_rx:
3377
3378 bd_cons = RX_BD_NEXT(bd_cons);
3379 bd_prod = RX_BD_NEXT(bd_prod);
3380 bd_prod_fw = RX_BD_NEXT(bd_prod_fw);
3381
3382 /* pass the frame to the stack */
3383 if (__predict_true(m != NULL)) {
3384 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3385 rx_pkts++;
3386 if_input(ifp, m);
3387 }
3388
3389 next_cqe:
3390
3391 sw_cq_prod = RCQ_NEXT(sw_cq_prod);
3392 sw_cq_cons = RCQ_NEXT(sw_cq_cons);
3393
3394 /* limit spinning on the queue */
3395 if (rc != 0)
3396 break;
3397
3398 if (rx_pkts == sc->rx_budget) {
3399 fp->eth_q_stats.rx_budget_reached++;
3400 break;
3401 }
3402 } /* while work to do */
3403
3404 fp->rx_bd_cons = bd_cons;
3405 fp->rx_bd_prod = bd_prod_fw;
3406 fp->rx_cq_cons = sw_cq_cons;
3407 fp->rx_cq_prod = sw_cq_prod;
3408
3409 /* Update producers */
3410 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod);
3411
3412 fp->eth_q_stats.rx_pkts += rx_pkts;
3413 fp->eth_q_stats.rx_calls++;
3414
3415 BXE_FP_RX_UNLOCK(fp);
3416
3417 return (sw_cq_cons != hw_cq_cons);
3418 }
3419
3420 static uint16_t
bxe_free_tx_pkt(struct bxe_softc * sc,struct bxe_fastpath * fp,uint16_t idx)3421 bxe_free_tx_pkt(struct bxe_softc *sc,
3422 struct bxe_fastpath *fp,
3423 uint16_t idx)
3424 {
3425 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx];
3426 struct eth_tx_start_bd *tx_start_bd;
3427 uint16_t bd_idx = TX_BD(tx_buf->first_bd);
3428 uint16_t new_cons;
3429 int nbd;
3430
3431 /* unmap the mbuf from non-paged memory */
3432 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
3433
3434 tx_start_bd = &fp->tx_chain[bd_idx].start_bd;
3435 nbd = le16toh(tx_start_bd->nbd) - 1;
3436
3437 new_cons = (tx_buf->first_bd + nbd);
3438
3439 /* free the mbuf */
3440 if (__predict_true(tx_buf->m != NULL)) {
3441 m_freem(tx_buf->m);
3442 fp->eth_q_stats.mbuf_alloc_tx--;
3443 } else {
3444 fp->eth_q_stats.tx_chain_lost_mbuf++;
3445 }
3446
3447 tx_buf->m = NULL;
3448 tx_buf->first_bd = 0;
3449
3450 return (new_cons);
3451 }
3452
3453 /* transmit timeout watchdog */
3454 static int
bxe_watchdog(struct bxe_softc * sc,struct bxe_fastpath * fp)3455 bxe_watchdog(struct bxe_softc *sc,
3456 struct bxe_fastpath *fp)
3457 {
3458 BXE_FP_TX_LOCK(fp);
3459
3460 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) {
3461 BXE_FP_TX_UNLOCK(fp);
3462 return (0);
3463 }
3464
3465 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index);
3466
3467 BXE_FP_TX_UNLOCK(fp);
3468 BXE_SET_ERROR_BIT(sc, BXE_ERR_TXQ_STUCK);
3469 taskqueue_enqueue_timeout(taskqueue_thread,
3470 &sc->sp_err_timeout_task, hz/10);
3471
3472 return (-1);
3473 }
3474
3475 /* processes transmit completions */
3476 static uint8_t
bxe_txeof(struct bxe_softc * sc,struct bxe_fastpath * fp)3477 bxe_txeof(struct bxe_softc *sc,
3478 struct bxe_fastpath *fp)
3479 {
3480 if_t ifp = sc->ifp;
3481 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons;
3482 uint16_t tx_bd_avail;
3483
3484 BXE_FP_TX_LOCK_ASSERT(fp);
3485
3486 bd_cons = fp->tx_bd_cons;
3487 hw_cons = le16toh(*fp->tx_cons_sb);
3488 sw_cons = fp->tx_pkt_cons;
3489
3490 while (sw_cons != hw_cons) {
3491 pkt_cons = TX_BD(sw_cons);
3492
3493 BLOGD(sc, DBG_TX,
3494 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n",
3495 fp->index, hw_cons, sw_cons, pkt_cons);
3496
3497 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons);
3498
3499 sw_cons++;
3500 }
3501
3502 fp->tx_pkt_cons = sw_cons;
3503 fp->tx_bd_cons = bd_cons;
3504
3505 BLOGD(sc, DBG_TX,
3506 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n",
3507 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod);
3508
3509 mb();
3510
3511 tx_bd_avail = bxe_tx_avail(sc, fp);
3512
3513 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
3514 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
3515 } else {
3516 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3517 }
3518
3519 if (fp->tx_pkt_prod != fp->tx_pkt_cons) {
3520 /* reset the watchdog timer if there are pending transmits */
3521 fp->watchdog_timer = BXE_TX_TIMEOUT;
3522 return (TRUE);
3523 } else {
3524 /* clear watchdog when there are no pending transmits */
3525 fp->watchdog_timer = 0;
3526 return (FALSE);
3527 }
3528 }
3529
3530 static void
bxe_drain_tx_queues(struct bxe_softc * sc)3531 bxe_drain_tx_queues(struct bxe_softc *sc)
3532 {
3533 struct bxe_fastpath *fp;
3534 int i, count;
3535
3536 /* wait until all TX fastpath tasks have completed */
3537 for (i = 0; i < sc->num_queues; i++) {
3538 fp = &sc->fp[i];
3539
3540 count = 1000;
3541
3542 while (bxe_has_tx_work(fp)) {
3543
3544 BXE_FP_TX_LOCK(fp);
3545 bxe_txeof(sc, fp);
3546 BXE_FP_TX_UNLOCK(fp);
3547
3548 if (count == 0) {
3549 BLOGE(sc, "Timeout waiting for fp[%d] "
3550 "transmits to complete!\n", i);
3551 bxe_panic(sc, ("tx drain failure\n"));
3552 return;
3553 }
3554
3555 count--;
3556 DELAY(1000);
3557 rmb();
3558 }
3559 }
3560
3561 return;
3562 }
3563
3564 static int
bxe_del_all_macs(struct bxe_softc * sc,struct ecore_vlan_mac_obj * mac_obj,int mac_type,uint8_t wait_for_comp)3565 bxe_del_all_macs(struct bxe_softc *sc,
3566 struct ecore_vlan_mac_obj *mac_obj,
3567 int mac_type,
3568 uint8_t wait_for_comp)
3569 {
3570 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3571 int rc;
3572
3573 /* wait for completion of requested */
3574 if (wait_for_comp) {
3575 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
3576 }
3577
3578 /* Set the mac type of addresses we want to clear */
3579 bxe_set_bit(mac_type, &vlan_mac_flags);
3580
3581 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
3582 if (rc < 0) {
3583 BLOGE(sc, "Failed to delete MACs (%d) mac_type %d wait_for_comp 0x%x\n",
3584 rc, mac_type, wait_for_comp);
3585 }
3586
3587 return (rc);
3588 }
3589
3590 static int
bxe_fill_accept_flags(struct bxe_softc * sc,uint32_t rx_mode,unsigned long * rx_accept_flags,unsigned long * tx_accept_flags)3591 bxe_fill_accept_flags(struct bxe_softc *sc,
3592 uint32_t rx_mode,
3593 unsigned long *rx_accept_flags,
3594 unsigned long *tx_accept_flags)
3595 {
3596 /* Clear the flags first */
3597 *rx_accept_flags = 0;
3598 *tx_accept_flags = 0;
3599
3600 switch (rx_mode) {
3601 case BXE_RX_MODE_NONE:
3602 /*
3603 * 'drop all' supersedes any accept flags that may have been
3604 * passed to the function.
3605 */
3606 break;
3607
3608 case BXE_RX_MODE_NORMAL:
3609 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3610 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
3611 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3612
3613 /* internal switching mode */
3614 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3615 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
3616 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3617
3618 break;
3619
3620 case BXE_RX_MODE_ALLMULTI:
3621 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3622 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3623 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3624
3625 /* internal switching mode */
3626 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3627 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3628 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3629
3630 break;
3631
3632 case BXE_RX_MODE_PROMISC:
3633 /*
3634 * According to deffinition of SI mode, iface in promisc mode
3635 * should receive matched and unmatched (in resolution of port)
3636 * unicast packets.
3637 */
3638 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
3639 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3640 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3641 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3642
3643 /* internal switching mode */
3644 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3645 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3646
3647 if (IS_MF_SI(sc)) {
3648 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
3649 } else {
3650 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3651 }
3652
3653 break;
3654
3655 default:
3656 BLOGE(sc, "Unknown rx_mode (0x%x)\n", rx_mode);
3657 return (-1);
3658 }
3659
3660 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
3661 if (rx_mode != BXE_RX_MODE_NONE) {
3662 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
3663 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
3664 }
3665
3666 return (0);
3667 }
3668
3669 static int
bxe_set_q_rx_mode(struct bxe_softc * sc,uint8_t cl_id,unsigned long rx_mode_flags,unsigned long rx_accept_flags,unsigned long tx_accept_flags,unsigned long ramrod_flags)3670 bxe_set_q_rx_mode(struct bxe_softc *sc,
3671 uint8_t cl_id,
3672 unsigned long rx_mode_flags,
3673 unsigned long rx_accept_flags,
3674 unsigned long tx_accept_flags,
3675 unsigned long ramrod_flags)
3676 {
3677 struct ecore_rx_mode_ramrod_params ramrod_param;
3678 int rc;
3679
3680 memset(&ramrod_param, 0, sizeof(ramrod_param));
3681
3682 /* Prepare ramrod parameters */
3683 ramrod_param.cid = 0;
3684 ramrod_param.cl_id = cl_id;
3685 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
3686 ramrod_param.func_id = SC_FUNC(sc);
3687
3688 ramrod_param.pstate = &sc->sp_state;
3689 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
3690
3691 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata);
3692 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata);
3693
3694 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
3695
3696 ramrod_param.ramrod_flags = ramrod_flags;
3697 ramrod_param.rx_mode_flags = rx_mode_flags;
3698
3699 ramrod_param.rx_accept_flags = rx_accept_flags;
3700 ramrod_param.tx_accept_flags = tx_accept_flags;
3701
3702 rc = ecore_config_rx_mode(sc, &ramrod_param);
3703 if (rc < 0) {
3704 BLOGE(sc, "Set rx_mode %d cli_id 0x%x rx_mode_flags 0x%x "
3705 "rx_accept_flags 0x%x tx_accept_flags 0x%x "
3706 "ramrod_flags 0x%x rc %d failed\n", sc->rx_mode, cl_id,
3707 (uint32_t)rx_mode_flags, (uint32_t)rx_accept_flags,
3708 (uint32_t)tx_accept_flags, (uint32_t)ramrod_flags, rc);
3709 return (rc);
3710 }
3711
3712 return (0);
3713 }
3714
3715 static int
bxe_set_storm_rx_mode(struct bxe_softc * sc)3716 bxe_set_storm_rx_mode(struct bxe_softc *sc)
3717 {
3718 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
3719 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
3720 int rc;
3721
3722 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
3723 &tx_accept_flags);
3724 if (rc) {
3725 return (rc);
3726 }
3727
3728 bxe_set_bit(RAMROD_RX, &ramrod_flags);
3729 bxe_set_bit(RAMROD_TX, &ramrod_flags);
3730
3731 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */
3732 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
3733 rx_accept_flags, tx_accept_flags,
3734 ramrod_flags));
3735 }
3736
3737 /* returns the "mcp load_code" according to global load_count array */
3738 static int
bxe_nic_load_no_mcp(struct bxe_softc * sc)3739 bxe_nic_load_no_mcp(struct bxe_softc *sc)
3740 {
3741 int path = SC_PATH(sc);
3742 int port = SC_PORT(sc);
3743
3744 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3745 path, load_count[path][0], load_count[path][1],
3746 load_count[path][2]);
3747 load_count[path][0]++;
3748 load_count[path][1 + port]++;
3749 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3750 path, load_count[path][0], load_count[path][1],
3751 load_count[path][2]);
3752 if (load_count[path][0] == 1) {
3753 return (FW_MSG_CODE_DRV_LOAD_COMMON);
3754 } else if (load_count[path][1 + port] == 1) {
3755 return (FW_MSG_CODE_DRV_LOAD_PORT);
3756 } else {
3757 return (FW_MSG_CODE_DRV_LOAD_FUNCTION);
3758 }
3759 }
3760
3761 /* returns the "mcp load_code" according to global load_count array */
3762 static int
bxe_nic_unload_no_mcp(struct bxe_softc * sc)3763 bxe_nic_unload_no_mcp(struct bxe_softc *sc)
3764 {
3765 int port = SC_PORT(sc);
3766 int path = SC_PATH(sc);
3767
3768 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3769 path, load_count[path][0], load_count[path][1],
3770 load_count[path][2]);
3771 load_count[path][0]--;
3772 load_count[path][1 + port]--;
3773 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3774 path, load_count[path][0], load_count[path][1],
3775 load_count[path][2]);
3776 if (load_count[path][0] == 0) {
3777 return (FW_MSG_CODE_DRV_UNLOAD_COMMON);
3778 } else if (load_count[path][1 + port] == 0) {
3779 return (FW_MSG_CODE_DRV_UNLOAD_PORT);
3780 } else {
3781 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
3782 }
3783 }
3784
3785 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
3786 static uint32_t
bxe_send_unload_req(struct bxe_softc * sc,int unload_mode)3787 bxe_send_unload_req(struct bxe_softc *sc,
3788 int unload_mode)
3789 {
3790 uint32_t reset_code = 0;
3791
3792 /* Select the UNLOAD request mode */
3793 if (unload_mode == UNLOAD_NORMAL) {
3794 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3795 } else {
3796 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3797 }
3798
3799 /* Send the request to the MCP */
3800 if (!BXE_NOMCP(sc)) {
3801 reset_code = bxe_fw_command(sc, reset_code, 0);
3802 } else {
3803 reset_code = bxe_nic_unload_no_mcp(sc);
3804 }
3805
3806 return (reset_code);
3807 }
3808
3809 /* send UNLOAD_DONE command to the MCP */
3810 static void
bxe_send_unload_done(struct bxe_softc * sc,uint8_t keep_link)3811 bxe_send_unload_done(struct bxe_softc *sc,
3812 uint8_t keep_link)
3813 {
3814 uint32_t reset_param =
3815 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
3816
3817 /* Report UNLOAD_DONE to MCP */
3818 if (!BXE_NOMCP(sc)) {
3819 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
3820 }
3821 }
3822
3823 static int
bxe_func_wait_started(struct bxe_softc * sc)3824 bxe_func_wait_started(struct bxe_softc *sc)
3825 {
3826 int tout = 50;
3827
3828 if (!sc->port.pmf) {
3829 return (0);
3830 }
3831
3832 /*
3833 * (assumption: No Attention from MCP at this stage)
3834 * PMF probably in the middle of TX disable/enable transaction
3835 * 1. Sync IRS for default SB
3836 * 2. Sync SP queue - this guarantees us that attention handling started
3837 * 3. Wait, that TX disable/enable transaction completes
3838 *
3839 * 1+2 guarantee that if DCBX attention was scheduled it already changed
3840 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
3841 * received completion for the transaction the state is TX_STOPPED.
3842 * State will return to STARTED after completion of TX_STOPPED-->STARTED
3843 * transaction.
3844 */
3845
3846 /* XXX make sure default SB ISR is done */
3847 /* need a way to synchronize an irq (intr_mtx?) */
3848
3849 /* XXX flush any work queues */
3850
3851 while (ecore_func_get_state(sc, &sc->func_obj) !=
3852 ECORE_F_STATE_STARTED && tout--) {
3853 DELAY(20000);
3854 }
3855
3856 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
3857 /*
3858 * Failed to complete the transaction in a "good way"
3859 * Force both transactions with CLR bit.
3860 */
3861 struct ecore_func_state_params func_params = { NULL };
3862
3863 BLOGE(sc, "Unexpected function state! "
3864 "Forcing STARTED-->TX_STOPPED-->STARTED\n");
3865
3866 func_params.f_obj = &sc->func_obj;
3867 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
3868
3869 /* STARTED-->TX_STOPPED */
3870 func_params.cmd = ECORE_F_CMD_TX_STOP;
3871 ecore_func_state_change(sc, &func_params);
3872
3873 /* TX_STOPPED-->STARTED */
3874 func_params.cmd = ECORE_F_CMD_TX_START;
3875 return (ecore_func_state_change(sc, &func_params));
3876 }
3877
3878 return (0);
3879 }
3880
3881 static int
bxe_stop_queue(struct bxe_softc * sc,int index)3882 bxe_stop_queue(struct bxe_softc *sc,
3883 int index)
3884 {
3885 struct bxe_fastpath *fp = &sc->fp[index];
3886 struct ecore_queue_state_params q_params = { NULL };
3887 int rc;
3888
3889 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index);
3890
3891 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
3892 /* We want to wait for completion in this context */
3893 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
3894
3895 /* Stop the primary connection: */
3896
3897 /* ...halt the connection */
3898 q_params.cmd = ECORE_Q_CMD_HALT;
3899 rc = ecore_queue_state_change(sc, &q_params);
3900 if (rc) {
3901 return (rc);
3902 }
3903
3904 /* ...terminate the connection */
3905 q_params.cmd = ECORE_Q_CMD_TERMINATE;
3906 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate));
3907 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
3908 rc = ecore_queue_state_change(sc, &q_params);
3909 if (rc) {
3910 return (rc);
3911 }
3912
3913 /* ...delete cfc entry */
3914 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
3915 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
3916 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
3917 return (ecore_queue_state_change(sc, &q_params));
3918 }
3919
3920 /* wait for the outstanding SP commands */
3921 static inline uint8_t
bxe_wait_sp_comp(struct bxe_softc * sc,unsigned long mask)3922 bxe_wait_sp_comp(struct bxe_softc *sc,
3923 unsigned long mask)
3924 {
3925 unsigned long tmp;
3926 int tout = 5000; /* wait for 5 secs tops */
3927
3928 while (tout--) {
3929 mb();
3930 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
3931 return (TRUE);
3932 }
3933
3934 DELAY(1000);
3935 }
3936
3937 mb();
3938
3939 tmp = atomic_load_acq_long(&sc->sp_state);
3940 if (tmp & mask) {
3941 BLOGE(sc, "Filtering completion timed out: "
3942 "sp_state 0x%lx, mask 0x%lx\n",
3943 tmp, mask);
3944 return (FALSE);
3945 }
3946
3947 return (FALSE);
3948 }
3949
3950 static int
bxe_func_stop(struct bxe_softc * sc)3951 bxe_func_stop(struct bxe_softc *sc)
3952 {
3953 struct ecore_func_state_params func_params = { NULL };
3954 int rc;
3955
3956 /* prepare parameters for function state transitions */
3957 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
3958 func_params.f_obj = &sc->func_obj;
3959 func_params.cmd = ECORE_F_CMD_STOP;
3960
3961 /*
3962 * Try to stop the function the 'good way'. If it fails (in case
3963 * of a parity error during bxe_chip_cleanup()) and we are
3964 * not in a debug mode, perform a state transaction in order to
3965 * enable further HW_RESET transaction.
3966 */
3967 rc = ecore_func_state_change(sc, &func_params);
3968 if (rc) {
3969 BLOGE(sc, "FUNC_STOP ramrod failed. "
3970 "Running a dry transaction (%d)\n", rc);
3971 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
3972 return (ecore_func_state_change(sc, &func_params));
3973 }
3974
3975 return (0);
3976 }
3977
3978 static int
bxe_reset_hw(struct bxe_softc * sc,uint32_t load_code)3979 bxe_reset_hw(struct bxe_softc *sc,
3980 uint32_t load_code)
3981 {
3982 struct ecore_func_state_params func_params = { NULL };
3983
3984 /* Prepare parameters for function state transitions */
3985 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
3986
3987 func_params.f_obj = &sc->func_obj;
3988 func_params.cmd = ECORE_F_CMD_HW_RESET;
3989
3990 func_params.params.hw_init.load_phase = load_code;
3991
3992 return (ecore_func_state_change(sc, &func_params));
3993 }
3994
3995 static void
bxe_int_disable_sync(struct bxe_softc * sc,int disable_hw)3996 bxe_int_disable_sync(struct bxe_softc *sc,
3997 int disable_hw)
3998 {
3999 if (disable_hw) {
4000 /* prevent the HW from sending interrupts */
4001 bxe_int_disable(sc);
4002 }
4003
4004 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */
4005 /* make sure all ISRs are done */
4006
4007 /* XXX make sure sp_task is not running */
4008 /* cancel and flush work queues */
4009 }
4010
4011 static void
bxe_chip_cleanup(struct bxe_softc * sc,uint32_t unload_mode,uint8_t keep_link)4012 bxe_chip_cleanup(struct bxe_softc *sc,
4013 uint32_t unload_mode,
4014 uint8_t keep_link)
4015 {
4016 int port = SC_PORT(sc);
4017 struct ecore_mcast_ramrod_params rparam = { NULL };
4018 uint32_t reset_code;
4019 int i, rc = 0;
4020
4021 bxe_drain_tx_queues(sc);
4022
4023 /* give HW time to discard old tx messages */
4024 DELAY(1000);
4025
4026 /* Clean all ETH MACs */
4027 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE);
4028 if (rc < 0) {
4029 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc);
4030 }
4031
4032 /* Clean up UC list */
4033 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE);
4034 if (rc < 0) {
4035 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc);
4036 }
4037
4038 /* Disable LLH */
4039 if (!CHIP_IS_E1(sc)) {
4040 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
4041 }
4042
4043 /* Set "drop all" to stop Rx */
4044
4045 /*
4046 * We need to take the BXE_MCAST_LOCK() here in order to prevent
4047 * a race between the completion code and this code.
4048 */
4049 BXE_MCAST_LOCK(sc);
4050
4051 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
4052 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
4053 } else {
4054 bxe_set_storm_rx_mode(sc);
4055 }
4056
4057 /* Clean up multicast configuration */
4058 rparam.mcast_obj = &sc->mcast_obj;
4059 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4060 if (rc < 0) {
4061 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4062 }
4063
4064 BXE_MCAST_UNLOCK(sc);
4065
4066 // XXX bxe_iov_chip_cleanup(sc);
4067
4068 /*
4069 * Send the UNLOAD_REQUEST to the MCP. This will return if
4070 * this function should perform FUNCTION, PORT, or COMMON HW
4071 * reset.
4072 */
4073 reset_code = bxe_send_unload_req(sc, unload_mode);
4074
4075 /*
4076 * (assumption: No Attention from MCP at this stage)
4077 * PMF probably in the middle of TX disable/enable transaction
4078 */
4079 rc = bxe_func_wait_started(sc);
4080 if (rc) {
4081 BLOGE(sc, "bxe_func_wait_started failed (%d)\n", rc);
4082 }
4083
4084 /*
4085 * Close multi and leading connections
4086 * Completions for ramrods are collected in a synchronous way
4087 */
4088 for (i = 0; i < sc->num_queues; i++) {
4089 if (bxe_stop_queue(sc, i)) {
4090 goto unload_error;
4091 }
4092 }
4093
4094 /*
4095 * If SP settings didn't get completed so far - something
4096 * very wrong has happen.
4097 */
4098 if (!bxe_wait_sp_comp(sc, ~0x0UL)) {
4099 BLOGE(sc, "Common slow path ramrods got stuck!(%d)\n", rc);
4100 }
4101
4102 unload_error:
4103
4104 rc = bxe_func_stop(sc);
4105 if (rc) {
4106 BLOGE(sc, "Function stop failed!(%d)\n", rc);
4107 }
4108
4109 /* disable HW interrupts */
4110 bxe_int_disable_sync(sc, TRUE);
4111
4112 /* detach interrupts */
4113 bxe_interrupt_detach(sc);
4114
4115 /* Reset the chip */
4116 rc = bxe_reset_hw(sc, reset_code);
4117 if (rc) {
4118 BLOGE(sc, "Hardware reset failed(%d)\n", rc);
4119 }
4120
4121 /* Report UNLOAD_DONE to MCP */
4122 bxe_send_unload_done(sc, keep_link);
4123 }
4124
4125 static void
bxe_disable_close_the_gate(struct bxe_softc * sc)4126 bxe_disable_close_the_gate(struct bxe_softc *sc)
4127 {
4128 uint32_t val;
4129 int port = SC_PORT(sc);
4130
4131 BLOGD(sc, DBG_LOAD,
4132 "Disabling 'close the gates'\n");
4133
4134 if (CHIP_IS_E1(sc)) {
4135 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4136 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4137 val = REG_RD(sc, addr);
4138 val &= ~(0x300);
4139 REG_WR(sc, addr, val);
4140 } else {
4141 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
4142 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
4143 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
4144 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
4145 }
4146 }
4147
4148 /*
4149 * Cleans the object that have internal lists without sending
4150 * ramrods. Should be run when interrupts are disabled.
4151 */
4152 static void
bxe_squeeze_objects(struct bxe_softc * sc)4153 bxe_squeeze_objects(struct bxe_softc *sc)
4154 {
4155 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
4156 struct ecore_mcast_ramrod_params rparam = { NULL };
4157 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
4158 int rc;
4159
4160 /* Cleanup MACs' object first... */
4161
4162 /* Wait for completion of requested */
4163 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
4164 /* Perform a dry cleanup */
4165 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
4166
4167 /* Clean ETH primary MAC */
4168 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
4169 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
4170 &ramrod_flags);
4171 if (rc != 0) {
4172 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc);
4173 }
4174
4175 /* Cleanup UC list */
4176 vlan_mac_flags = 0;
4177 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
4178 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags,
4179 &ramrod_flags);
4180 if (rc != 0) {
4181 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc);
4182 }
4183
4184 /* Now clean mcast object... */
4185
4186 rparam.mcast_obj = &sc->mcast_obj;
4187 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
4188
4189 /* Add a DEL command... */
4190 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4191 if (rc < 0) {
4192 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4193 }
4194
4195 /* now wait until all pending commands are cleared */
4196
4197 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4198 while (rc != 0) {
4199 if (rc < 0) {
4200 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc);
4201 return;
4202 }
4203
4204 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4205 }
4206 }
4207
4208 /* stop the controller */
4209 static __noinline int
bxe_nic_unload(struct bxe_softc * sc,uint32_t unload_mode,uint8_t keep_link)4210 bxe_nic_unload(struct bxe_softc *sc,
4211 uint32_t unload_mode,
4212 uint8_t keep_link)
4213 {
4214 uint8_t global = FALSE;
4215 uint32_t val;
4216 int i;
4217
4218 BXE_CORE_LOCK_ASSERT(sc);
4219
4220 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING);
4221
4222 for (i = 0; i < sc->num_queues; i++) {
4223 struct bxe_fastpath *fp;
4224
4225 fp = &sc->fp[i];
4226 fp->watchdog_timer = 0;
4227 BXE_FP_TX_LOCK(fp);
4228 BXE_FP_TX_UNLOCK(fp);
4229 }
4230
4231 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n");
4232
4233 /* mark driver as unloaded in shmem2 */
4234 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
4235 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
4236 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
4237 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
4238 }
4239
4240 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE &&
4241 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) {
4242
4243 if(CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
4244 /*
4245 * We can get here if the driver has been unloaded
4246 * during parity error recovery and is either waiting for a
4247 * leader to complete or for other functions to unload and
4248 * then ifconfig down has been issued. In this case we want to
4249 * unload and let other functions to complete a recovery
4250 * process.
4251 */
4252 sc->recovery_state = BXE_RECOVERY_DONE;
4253 sc->is_leader = 0;
4254 bxe_release_leader_lock(sc);
4255 mb();
4256 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n");
4257 }
4258 BLOGE(sc, "Can't unload in closed or error state recover_state 0x%x"
4259 " state = 0x%x\n", sc->recovery_state, sc->state);
4260 return (-1);
4261 }
4262
4263 /*
4264 * Nothing to do during unload if previous bxe_nic_load()
4265 * did not completed successfully - all resourses are released.
4266 */
4267 if ((sc->state == BXE_STATE_CLOSED) ||
4268 (sc->state == BXE_STATE_ERROR)) {
4269 return (0);
4270 }
4271
4272 sc->state = BXE_STATE_CLOSING_WAITING_HALT;
4273 mb();
4274
4275 /* stop tx */
4276 bxe_tx_disable(sc);
4277
4278 sc->rx_mode = BXE_RX_MODE_NONE;
4279 /* XXX set rx mode ??? */
4280
4281 if (IS_PF(sc) && !sc->grcdump_done) {
4282 /* set ALWAYS_ALIVE bit in shmem */
4283 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
4284
4285 bxe_drv_pulse(sc);
4286
4287 bxe_stats_handle(sc, STATS_EVENT_STOP);
4288 bxe_save_statistics(sc);
4289 }
4290
4291 /* wait till consumers catch up with producers in all queues */
4292 bxe_drain_tx_queues(sc);
4293
4294 /* if VF indicate to PF this function is going down (PF will delete sp
4295 * elements and clear initializations
4296 */
4297 if (IS_VF(sc)) {
4298 ; /* bxe_vfpf_close_vf(sc); */
4299 } else if (unload_mode != UNLOAD_RECOVERY) {
4300 /* if this is a normal/close unload need to clean up chip */
4301 if (!sc->grcdump_done)
4302 bxe_chip_cleanup(sc, unload_mode, keep_link);
4303 } else {
4304 /* Send the UNLOAD_REQUEST to the MCP */
4305 bxe_send_unload_req(sc, unload_mode);
4306
4307 /*
4308 * Prevent transactions to host from the functions on the
4309 * engine that doesn't reset global blocks in case of global
4310 * attention once gloabl blocks are reset and gates are opened
4311 * (the engine which leader will perform the recovery
4312 * last).
4313 */
4314 if (!CHIP_IS_E1x(sc)) {
4315 bxe_pf_disable(sc);
4316 }
4317
4318 /* disable HW interrupts */
4319 bxe_int_disable_sync(sc, TRUE);
4320
4321 /* detach interrupts */
4322 bxe_interrupt_detach(sc);
4323
4324 /* Report UNLOAD_DONE to MCP */
4325 bxe_send_unload_done(sc, FALSE);
4326 }
4327
4328 /*
4329 * At this stage no more interrupts will arrive so we may safely clean
4330 * the queue'able objects here in case they failed to get cleaned so far.
4331 */
4332 if (IS_PF(sc)) {
4333 bxe_squeeze_objects(sc);
4334 }
4335
4336 /* There should be no more pending SP commands at this stage */
4337 sc->sp_state = 0;
4338
4339 sc->port.pmf = 0;
4340
4341 bxe_free_fp_buffers(sc);
4342
4343 if (IS_PF(sc)) {
4344 bxe_free_mem(sc);
4345 }
4346
4347 bxe_free_fw_stats_mem(sc);
4348
4349 sc->state = BXE_STATE_CLOSED;
4350
4351 /*
4352 * Check if there are pending parity attentions. If there are - set
4353 * RECOVERY_IN_PROGRESS.
4354 */
4355 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) {
4356 bxe_set_reset_in_progress(sc);
4357
4358 /* Set RESET_IS_GLOBAL if needed */
4359 if (global) {
4360 bxe_set_reset_global(sc);
4361 }
4362 }
4363
4364 /*
4365 * The last driver must disable a "close the gate" if there is no
4366 * parity attention or "process kill" pending.
4367 */
4368 if (IS_PF(sc) && !bxe_clear_pf_load(sc) &&
4369 bxe_reset_is_done(sc, SC_PATH(sc))) {
4370 bxe_disable_close_the_gate(sc);
4371 }
4372
4373 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n");
4374
4375 bxe_link_report(sc);
4376
4377 return (0);
4378 }
4379
4380 /*
4381 * Called by the OS to set various media options (i.e. link, speed, etc.) when
4382 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...".
4383 */
4384 static int
bxe_ifmedia_update(if_t ifp)4385 bxe_ifmedia_update(if_t ifp)
4386 {
4387 struct bxe_softc *sc = (struct bxe_softc *)if_getsoftc(ifp);
4388 struct ifmedia *ifm;
4389
4390 ifm = &sc->ifmedia;
4391
4392 /* We only support Ethernet media type. */
4393 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
4394 return (EINVAL);
4395 }
4396
4397 switch (IFM_SUBTYPE(ifm->ifm_media)) {
4398 case IFM_AUTO:
4399 break;
4400 case IFM_10G_CX4:
4401 case IFM_10G_SR:
4402 case IFM_10G_T:
4403 case IFM_10G_TWINAX:
4404 default:
4405 /* We don't support changing the media type. */
4406 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n",
4407 IFM_SUBTYPE(ifm->ifm_media));
4408 return (EINVAL);
4409 }
4410
4411 return (0);
4412 }
4413
4414 /*
4415 * Called by the OS to get the current media status (i.e. link, speed, etc.).
4416 */
4417 static void
bxe_ifmedia_status(if_t ifp,struct ifmediareq * ifmr)4418 bxe_ifmedia_status(if_t ifp, struct ifmediareq *ifmr)
4419 {
4420 struct bxe_softc *sc = if_getsoftc(ifp);
4421
4422 /* Bug 165447: the 'ifconfig' tool skips printing of the "status: ..."
4423 line if the IFM_AVALID flag is *NOT* set. So we need to set this
4424 flag unconditionally (irrespective of the admininistrative
4425 'up/down' state of the interface) to ensure that the line is always
4426 displayed.
4427 */
4428 ifmr->ifm_status = IFM_AVALID;
4429
4430 /* Setup the default interface info. */
4431 ifmr->ifm_active = IFM_ETHER;
4432
4433 /* Report link down if the driver isn't running. */
4434 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4435 ifmr->ifm_active |= IFM_NONE;
4436 BLOGD(sc, DBG_PHY, "in %s : nic still not loaded fully\n", __func__);
4437 BLOGD(sc, DBG_PHY, "in %s : link_up (1) : %d\n",
4438 __func__, sc->link_vars.link_up);
4439 return;
4440 }
4441
4442
4443 if (sc->link_vars.link_up) {
4444 ifmr->ifm_status |= IFM_ACTIVE;
4445 ifmr->ifm_active |= IFM_FDX;
4446 } else {
4447 ifmr->ifm_active |= IFM_NONE;
4448 BLOGD(sc, DBG_PHY, "in %s : setting IFM_NONE\n",
4449 __func__);
4450 return;
4451 }
4452
4453 ifmr->ifm_active |= sc->media;
4454 return;
4455 }
4456
4457 static void
bxe_handle_chip_tq(void * context,int pending)4458 bxe_handle_chip_tq(void *context,
4459 int pending)
4460 {
4461 struct bxe_softc *sc = (struct bxe_softc *)context;
4462 long work = atomic_load_acq_long(&sc->chip_tq_flags);
4463
4464 switch (work)
4465 {
4466
4467 case CHIP_TQ_REINIT:
4468 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
4469 /* restart the interface */
4470 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n");
4471 bxe_periodic_stop(sc);
4472 BXE_CORE_LOCK(sc);
4473 bxe_stop_locked(sc);
4474 bxe_init_locked(sc);
4475 BXE_CORE_UNLOCK(sc);
4476 }
4477 break;
4478
4479 default:
4480 break;
4481 }
4482 }
4483
4484 /*
4485 * Handles any IOCTL calls from the operating system.
4486 *
4487 * Returns:
4488 * 0 = Success, >0 Failure
4489 */
4490 static int
bxe_ioctl(if_t ifp,u_long command,caddr_t data)4491 bxe_ioctl(if_t ifp,
4492 u_long command,
4493 caddr_t data)
4494 {
4495 struct bxe_softc *sc = if_getsoftc(ifp);
4496 struct ifreq *ifr = (struct ifreq *)data;
4497 int mask = 0;
4498 int reinit = 0;
4499 int error = 0;
4500
4501 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN);
4502 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING);
4503
4504 switch (command)
4505 {
4506 case SIOCSIFMTU:
4507 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n",
4508 ifr->ifr_mtu);
4509
4510 if (sc->mtu == ifr->ifr_mtu) {
4511 /* nothing to change */
4512 break;
4513 }
4514
4515 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) {
4516 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n",
4517 ifr->ifr_mtu, mtu_min, mtu_max);
4518 error = EINVAL;
4519 break;
4520 }
4521
4522 atomic_store_rel_int((volatile unsigned int *)&sc->mtu,
4523 (unsigned long)ifr->ifr_mtu);
4524 /*
4525 atomic_store_rel_long((volatile unsigned long *)&if_getmtu(ifp),
4526 (unsigned long)ifr->ifr_mtu);
4527 XXX - Not sure why it needs to be atomic
4528 */
4529 if_setmtu(ifp, ifr->ifr_mtu);
4530 reinit = 1;
4531 break;
4532
4533 case SIOCSIFFLAGS:
4534 /* toggle the interface state up or down */
4535 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n");
4536
4537 BXE_CORE_LOCK(sc);
4538 /* check if the interface is up */
4539 if (if_getflags(ifp) & IFF_UP) {
4540 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4541 /* set the receive mode flags */
4542 bxe_set_rx_mode(sc);
4543 } else if(sc->state != BXE_STATE_DISABLED) {
4544 bxe_init_locked(sc);
4545 }
4546 } else {
4547 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4548 bxe_periodic_stop(sc);
4549 bxe_stop_locked(sc);
4550 }
4551 }
4552 BXE_CORE_UNLOCK(sc);
4553
4554 break;
4555
4556 case SIOCADDMULTI:
4557 case SIOCDELMULTI:
4558 /* add/delete multicast addresses */
4559 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n");
4560
4561 /* check if the interface is up */
4562 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4563 /* set the receive mode flags */
4564 BXE_CORE_LOCK(sc);
4565 bxe_set_rx_mode(sc);
4566 BXE_CORE_UNLOCK(sc);
4567 }
4568
4569 break;
4570
4571 case SIOCSIFCAP:
4572 /* find out which capabilities have changed */
4573 mask = (ifr->ifr_reqcap ^ if_getcapenable(ifp));
4574
4575 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n",
4576 mask);
4577
4578 /* toggle the LRO capabilites enable flag */
4579 if (mask & IFCAP_LRO) {
4580 if_togglecapenable(ifp, IFCAP_LRO);
4581 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n",
4582 (if_getcapenable(ifp) & IFCAP_LRO) ? "ON" : "OFF");
4583 reinit = 1;
4584 }
4585
4586 /* toggle the TXCSUM checksum capabilites enable flag */
4587 if (mask & IFCAP_TXCSUM) {
4588 if_togglecapenable(ifp, IFCAP_TXCSUM);
4589 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n",
4590 (if_getcapenable(ifp) & IFCAP_TXCSUM) ? "ON" : "OFF");
4591 if (if_getcapenable(ifp) & IFCAP_TXCSUM) {
4592 if_sethwassistbits(ifp, (CSUM_IP |
4593 CSUM_TCP |
4594 CSUM_UDP |
4595 CSUM_TSO |
4596 CSUM_TCP_IPV6 |
4597 CSUM_UDP_IPV6), 0);
4598 } else {
4599 if_clearhwassist(ifp); /* XXX */
4600 }
4601 }
4602
4603 /* toggle the RXCSUM checksum capabilities enable flag */
4604 if (mask & IFCAP_RXCSUM) {
4605 if_togglecapenable(ifp, IFCAP_RXCSUM);
4606 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n",
4607 (if_getcapenable(ifp) & IFCAP_RXCSUM) ? "ON" : "OFF");
4608 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
4609 if_sethwassistbits(ifp, (CSUM_IP |
4610 CSUM_TCP |
4611 CSUM_UDP |
4612 CSUM_TSO |
4613 CSUM_TCP_IPV6 |
4614 CSUM_UDP_IPV6), 0);
4615 } else {
4616 if_clearhwassist(ifp); /* XXX */
4617 }
4618 }
4619
4620 /* toggle TSO4 capabilities enabled flag */
4621 if (mask & IFCAP_TSO4) {
4622 if_togglecapenable(ifp, IFCAP_TSO4);
4623 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n",
4624 (if_getcapenable(ifp) & IFCAP_TSO4) ? "ON" : "OFF");
4625 }
4626
4627 /* toggle TSO6 capabilities enabled flag */
4628 if (mask & IFCAP_TSO6) {
4629 if_togglecapenable(ifp, IFCAP_TSO6);
4630 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n",
4631 (if_getcapenable(ifp) & IFCAP_TSO6) ? "ON" : "OFF");
4632 }
4633
4634 /* toggle VLAN_HWTSO capabilities enabled flag */
4635 if (mask & IFCAP_VLAN_HWTSO) {
4636
4637 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
4638 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n",
4639 (if_getcapenable(ifp) & IFCAP_VLAN_HWTSO) ? "ON" : "OFF");
4640 }
4641
4642 /* toggle VLAN_HWCSUM capabilities enabled flag */
4643 if (mask & IFCAP_VLAN_HWCSUM) {
4644 /* XXX investigate this... */
4645 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n");
4646 error = EINVAL;
4647 }
4648
4649 /* toggle VLAN_MTU capabilities enable flag */
4650 if (mask & IFCAP_VLAN_MTU) {
4651 /* XXX investigate this... */
4652 BLOGE(sc, "Changing VLAN_MTU is not supported!\n");
4653 error = EINVAL;
4654 }
4655
4656 /* toggle VLAN_HWTAGGING capabilities enabled flag */
4657 if (mask & IFCAP_VLAN_HWTAGGING) {
4658 /* XXX investigate this... */
4659 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n");
4660 error = EINVAL;
4661 }
4662
4663 /* toggle VLAN_HWFILTER capabilities enabled flag */
4664 if (mask & IFCAP_VLAN_HWFILTER) {
4665 /* XXX investigate this... */
4666 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n");
4667 error = EINVAL;
4668 }
4669
4670 /* XXX not yet...
4671 * IFCAP_WOL_MAGIC
4672 */
4673
4674 break;
4675
4676 case SIOCSIFMEDIA:
4677 case SIOCGIFMEDIA:
4678 /* set/get interface media */
4679 BLOGD(sc, DBG_IOCTL,
4680 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n",
4681 (command & 0xff));
4682 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
4683 break;
4684
4685 default:
4686 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n",
4687 (command & 0xff));
4688 error = ether_ioctl(ifp, command, data);
4689 break;
4690 }
4691
4692 if (reinit && (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) {
4693 BLOGD(sc, DBG_LOAD | DBG_IOCTL,
4694 "Re-initializing hardware from IOCTL change\n");
4695 bxe_periodic_stop(sc);
4696 BXE_CORE_LOCK(sc);
4697 bxe_stop_locked(sc);
4698 bxe_init_locked(sc);
4699 BXE_CORE_UNLOCK(sc);
4700 }
4701
4702 return (error);
4703 }
4704
4705 static __noinline void
bxe_dump_mbuf(struct bxe_softc * sc,struct mbuf * m,uint8_t contents)4706 bxe_dump_mbuf(struct bxe_softc *sc,
4707 struct mbuf *m,
4708 uint8_t contents)
4709 {
4710 char * type;
4711 int i = 0;
4712
4713 if (!(sc->debug & DBG_MBUF)) {
4714 return;
4715 }
4716
4717 if (m == NULL) {
4718 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n");
4719 return;
4720 }
4721
4722 while (m) {
4723
4724 BLOGD(sc, DBG_MBUF,
4725 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4726 i, m, m->m_len, m->m_flags, M_FLAG_BITS, m->m_data);
4727
4728 if (m->m_flags & M_PKTHDR) {
4729 BLOGD(sc, DBG_MBUF,
4730 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4731 i, m->m_pkthdr.len, m->m_flags, M_FLAG_BITS,
4732 (int)m->m_pkthdr.csum_flags, CSUM_BITS);
4733 }
4734
4735 if (m->m_flags & M_EXT) {
4736 switch (m->m_ext.ext_type) {
4737 case EXT_CLUSTER: type = "EXT_CLUSTER"; break;
4738 case EXT_SFBUF: type = "EXT_SFBUF"; break;
4739 case EXT_JUMBOP: type = "EXT_JUMBOP"; break;
4740 case EXT_JUMBO9: type = "EXT_JUMBO9"; break;
4741 case EXT_JUMBO16: type = "EXT_JUMBO16"; break;
4742 case EXT_PACKET: type = "EXT_PACKET"; break;
4743 case EXT_MBUF: type = "EXT_MBUF"; break;
4744 case EXT_NET_DRV: type = "EXT_NET_DRV"; break;
4745 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break;
4746 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break;
4747 case EXT_EXTREF: type = "EXT_EXTREF"; break;
4748 default: type = "UNKNOWN"; break;
4749 }
4750
4751 BLOGD(sc, DBG_MBUF,
4752 "%02d: - m_ext: %p ext_size=%d type=%s\n",
4753 i, m->m_ext.ext_buf, m->m_ext.ext_size, type);
4754 }
4755
4756 if (contents) {
4757 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE);
4758 }
4759
4760 m = m->m_next;
4761 i++;
4762 }
4763 }
4764
4765 /*
4766 * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
4767 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS.
4768 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD
4769 * The headers comes in a separate bd in FreeBSD so 13-3=10.
4770 * Returns: 0 if OK to send, 1 if packet needs further defragmentation
4771 */
4772 static int
bxe_chktso_window(struct bxe_softc * sc,int nsegs,bus_dma_segment_t * segs,struct mbuf * m)4773 bxe_chktso_window(struct bxe_softc *sc,
4774 int nsegs,
4775 bus_dma_segment_t *segs,
4776 struct mbuf *m)
4777 {
4778 uint32_t num_wnds, wnd_size, wnd_sum;
4779 int32_t frag_idx, wnd_idx;
4780 unsigned short lso_mss;
4781
4782 wnd_sum = 0;
4783 wnd_size = 10;
4784 num_wnds = nsegs - wnd_size;
4785 lso_mss = htole16(m->m_pkthdr.tso_segsz);
4786
4787 /*
4788 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the
4789 * first window sum of data while skipping the first assuming it is the
4790 * header in FreeBSD.
4791 */
4792 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) {
4793 wnd_sum += htole16(segs[frag_idx].ds_len);
4794 }
4795
4796 /* check the first 10 bd window size */
4797 if (wnd_sum < lso_mss) {
4798 return (1);
4799 }
4800
4801 /* run through the windows */
4802 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
4803 /* subtract the first mbuf->m_len of the last wndw(-header) */
4804 wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
4805 /* add the next mbuf len to the len of our new window */
4806 wnd_sum += htole16(segs[frag_idx].ds_len);
4807 if (wnd_sum < lso_mss) {
4808 return (1);
4809 }
4810 }
4811
4812 return (0);
4813 }
4814
4815 static uint8_t
bxe_set_pbd_csum_e2(struct bxe_fastpath * fp,struct mbuf * m,uint32_t * parsing_data)4816 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp,
4817 struct mbuf *m,
4818 uint32_t *parsing_data)
4819 {
4820 struct ether_vlan_header *eh = NULL;
4821 struct ip *ip4 = NULL;
4822 struct ip6_hdr *ip6 = NULL;
4823 caddr_t ip = NULL;
4824 struct tcphdr *th = NULL;
4825 int e_hlen, ip_hlen, l4_off;
4826 uint16_t proto;
4827
4828 if (m->m_pkthdr.csum_flags == CSUM_IP) {
4829 /* no L4 checksum offload needed */
4830 return (0);
4831 }
4832
4833 /* get the Ethernet header */
4834 eh = mtod(m, struct ether_vlan_header *);
4835
4836 /* handle VLAN encapsulation if present */
4837 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4838 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4839 proto = ntohs(eh->evl_proto);
4840 } else {
4841 e_hlen = ETHER_HDR_LEN;
4842 proto = ntohs(eh->evl_encap_proto);
4843 }
4844
4845 switch (proto) {
4846 case ETHERTYPE_IP:
4847 /* get the IP header, if mbuf len < 20 then header in next mbuf */
4848 ip4 = (m->m_len < sizeof(struct ip)) ?
4849 (struct ip *)m->m_next->m_data :
4850 (struct ip *)(m->m_data + e_hlen);
4851 /* ip_hl is number of 32-bit words */
4852 ip_hlen = (ip4->ip_hl << 2);
4853 ip = (caddr_t)ip4;
4854 break;
4855 case ETHERTYPE_IPV6:
4856 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
4857 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
4858 (struct ip6_hdr *)m->m_next->m_data :
4859 (struct ip6_hdr *)(m->m_data + e_hlen);
4860 /* XXX cannot support offload with IPv6 extensions */
4861 ip_hlen = sizeof(struct ip6_hdr);
4862 ip = (caddr_t)ip6;
4863 break;
4864 default:
4865 /* We can't offload in this case... */
4866 /* XXX error stat ??? */
4867 return (0);
4868 }
4869
4870 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
4871 l4_off = (e_hlen + ip_hlen);
4872
4873 *parsing_data |=
4874 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
4875 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W);
4876
4877 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
4878 CSUM_TSO |
4879 CSUM_TCP_IPV6)) {
4880 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
4881 th = (struct tcphdr *)(ip + ip_hlen);
4882 /* th_off is number of 32-bit words */
4883 *parsing_data |= ((th->th_off <<
4884 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
4885 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW);
4886 return (l4_off + (th->th_off << 2)); /* entire header length */
4887 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
4888 CSUM_UDP_IPV6)) {
4889 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
4890 return (l4_off + sizeof(struct udphdr)); /* entire header length */
4891 } else {
4892 /* XXX error stat ??? */
4893 return (0);
4894 }
4895 }
4896
4897 static uint8_t
bxe_set_pbd_csum(struct bxe_fastpath * fp,struct mbuf * m,struct eth_tx_parse_bd_e1x * pbd)4898 bxe_set_pbd_csum(struct bxe_fastpath *fp,
4899 struct mbuf *m,
4900 struct eth_tx_parse_bd_e1x *pbd)
4901 {
4902 struct ether_vlan_header *eh = NULL;
4903 struct ip *ip4 = NULL;
4904 struct ip6_hdr *ip6 = NULL;
4905 caddr_t ip = NULL;
4906 struct tcphdr *th = NULL;
4907 struct udphdr *uh = NULL;
4908 int e_hlen, ip_hlen;
4909 uint16_t proto;
4910 uint8_t hlen;
4911 uint16_t tmp_csum;
4912 uint32_t *tmp_uh;
4913
4914 /* get the Ethernet header */
4915 eh = mtod(m, struct ether_vlan_header *);
4916
4917 /* handle VLAN encapsulation if present */
4918 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4919 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4920 proto = ntohs(eh->evl_proto);
4921 } else {
4922 e_hlen = ETHER_HDR_LEN;
4923 proto = ntohs(eh->evl_encap_proto);
4924 }
4925
4926 switch (proto) {
4927 case ETHERTYPE_IP:
4928 /* get the IP header, if mbuf len < 20 then header in next mbuf */
4929 ip4 = (m->m_len < sizeof(struct ip)) ?
4930 (struct ip *)m->m_next->m_data :
4931 (struct ip *)(m->m_data + e_hlen);
4932 /* ip_hl is number of 32-bit words */
4933 ip_hlen = (ip4->ip_hl << 1);
4934 ip = (caddr_t)ip4;
4935 break;
4936 case ETHERTYPE_IPV6:
4937 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
4938 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
4939 (struct ip6_hdr *)m->m_next->m_data :
4940 (struct ip6_hdr *)(m->m_data + e_hlen);
4941 /* XXX cannot support offload with IPv6 extensions */
4942 ip_hlen = (sizeof(struct ip6_hdr) >> 1);
4943 ip = (caddr_t)ip6;
4944 break;
4945 default:
4946 /* We can't offload in this case... */
4947 /* XXX error stat ??? */
4948 return (0);
4949 }
4950
4951 hlen = (e_hlen >> 1);
4952
4953 /* note that rest of global_data is indirectly zeroed here */
4954 if (m->m_flags & M_VLANTAG) {
4955 pbd->global_data =
4956 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
4957 } else {
4958 pbd->global_data = htole16(hlen);
4959 }
4960
4961 pbd->ip_hlen_w = ip_hlen;
4962
4963 hlen += pbd->ip_hlen_w;
4964
4965 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
4966
4967 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
4968 CSUM_TSO |
4969 CSUM_TCP_IPV6)) {
4970 th = (struct tcphdr *)(ip + (ip_hlen << 1));
4971 /* th_off is number of 32-bit words */
4972 hlen += (uint16_t)(th->th_off << 1);
4973 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
4974 CSUM_UDP_IPV6)) {
4975 uh = (struct udphdr *)(ip + (ip_hlen << 1));
4976 hlen += (sizeof(struct udphdr) / 2);
4977 } else {
4978 /* valid case as only CSUM_IP was set */
4979 return (0);
4980 }
4981
4982 pbd->total_hlen_w = htole16(hlen);
4983
4984 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
4985 CSUM_TSO |
4986 CSUM_TCP_IPV6)) {
4987 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
4988 pbd->tcp_pseudo_csum = ntohs(th->th_sum);
4989 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
4990 CSUM_UDP_IPV6)) {
4991 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
4992
4993 /*
4994 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP
4995 * checksums and does not know anything about the UDP header and where
4996 * the checksum field is located. It only knows about TCP. Therefore
4997 * we "lie" to the hardware for outgoing UDP packets w/ checksum
4998 * offload. Since the checksum field offset for TCP is 16 bytes and
4999 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10
5000 * bytes less than the start of the UDP header. This allows the
5001 * hardware to write the checksum in the correct spot. But the
5002 * hardware will compute a checksum which includes the last 10 bytes
5003 * of the IP header. To correct this we tweak the stack computed
5004 * pseudo checksum by folding in the calculation of the inverse
5005 * checksum for those final 10 bytes of the IP header. This allows
5006 * the correct checksum to be computed by the hardware.
5007 */
5008
5009 /* set pointer 10 bytes before UDP header */
5010 tmp_uh = (uint32_t *)((uint8_t *)uh - 10);
5011
5012 /* calculate a pseudo header checksum over the first 10 bytes */
5013 tmp_csum = in_pseudo(*tmp_uh,
5014 *(tmp_uh + 1),
5015 *(uint16_t *)(tmp_uh + 2));
5016
5017 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum));
5018 }
5019
5020 return (hlen * 2); /* entire header length, number of bytes */
5021 }
5022
5023 static void
bxe_set_pbd_lso_e2(struct mbuf * m,uint32_t * parsing_data)5024 bxe_set_pbd_lso_e2(struct mbuf *m,
5025 uint32_t *parsing_data)
5026 {
5027 *parsing_data |= ((m->m_pkthdr.tso_segsz <<
5028 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
5029 ETH_TX_PARSE_BD_E2_LSO_MSS);
5030
5031 /* XXX test for IPv6 with extension header... */
5032 }
5033
5034 static void
bxe_set_pbd_lso(struct mbuf * m,struct eth_tx_parse_bd_e1x * pbd)5035 bxe_set_pbd_lso(struct mbuf *m,
5036 struct eth_tx_parse_bd_e1x *pbd)
5037 {
5038 struct ether_vlan_header *eh = NULL;
5039 struct ip *ip = NULL;
5040 struct tcphdr *th = NULL;
5041 int e_hlen;
5042
5043 /* get the Ethernet header */
5044 eh = mtod(m, struct ether_vlan_header *);
5045
5046 /* handle VLAN encapsulation if present */
5047 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ?
5048 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN;
5049
5050 /* get the IP and TCP header, with LSO entire header in first mbuf */
5051 /* XXX assuming IPv4 */
5052 ip = (struct ip *)(m->m_data + e_hlen);
5053 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
5054
5055 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz);
5056 pbd->tcp_send_seq = ntohl(th->th_seq);
5057 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff);
5058
5059 #if 1
5060 /* XXX IPv4 */
5061 pbd->ip_id = ntohs(ip->ip_id);
5062 pbd->tcp_pseudo_csum =
5063 ntohs(in_pseudo(ip->ip_src.s_addr,
5064 ip->ip_dst.s_addr,
5065 htons(IPPROTO_TCP)));
5066 #else
5067 /* XXX IPv6 */
5068 pbd->tcp_pseudo_csum =
5069 ntohs(in_pseudo(&ip6->ip6_src,
5070 &ip6->ip6_dst,
5071 htons(IPPROTO_TCP)));
5072 #endif
5073
5074 pbd->global_data |=
5075 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
5076 }
5077
5078 /*
5079 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
5080 * visible to the controller.
5081 *
5082 * If an mbuf is submitted to this routine and cannot be given to the
5083 * controller (e.g. it has too many fragments) then the function may free
5084 * the mbuf and return to the caller.
5085 *
5086 * Returns:
5087 * 0 = Success, !0 = Failure
5088 * Note the side effect that an mbuf may be freed if it causes a problem.
5089 */
5090 static int
bxe_tx_encap(struct bxe_fastpath * fp,struct mbuf ** m_head)5091 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
5092 {
5093 bus_dma_segment_t segs[32];
5094 struct mbuf *m0;
5095 struct bxe_sw_tx_bd *tx_buf;
5096 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
5097 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
5098 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */
5099 struct eth_tx_bd *tx_data_bd;
5100 struct eth_tx_bd *tx_total_pkt_size_bd;
5101 struct eth_tx_start_bd *tx_start_bd;
5102 uint16_t bd_prod, pkt_prod, total_pkt_size;
5103 uint8_t mac_type;
5104 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan;
5105 struct bxe_softc *sc;
5106 uint16_t tx_bd_avail;
5107 struct ether_vlan_header *eh;
5108 uint32_t pbd_e2_parsing_data = 0;
5109 uint8_t hlen = 0;
5110 int tmp_bd;
5111 int i;
5112
5113 sc = fp->sc;
5114
5115 M_ASSERTPKTHDR(*m_head);
5116
5117 m0 = *m_head;
5118 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
5119 tx_start_bd = NULL;
5120 tx_data_bd = NULL;
5121 tx_total_pkt_size_bd = NULL;
5122
5123 /* get the H/W pointer for packets and BDs */
5124 pkt_prod = fp->tx_pkt_prod;
5125 bd_prod = fp->tx_bd_prod;
5126
5127 mac_type = UNICAST_ADDRESS;
5128
5129 /* map the mbuf into the next open DMAable memory */
5130 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)];
5131 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5132 tx_buf->m_map, m0,
5133 segs, &nsegs, BUS_DMA_NOWAIT);
5134
5135 /* mapping errors */
5136 if(__predict_false(error != 0)) {
5137 fp->eth_q_stats.tx_dma_mapping_failure++;
5138 if (error == ENOMEM) {
5139 /* resource issue, try again later */
5140 rc = ENOMEM;
5141 } else if (error == EFBIG) {
5142 /* possibly recoverable with defragmentation */
5143 fp->eth_q_stats.mbuf_defrag_attempts++;
5144 m0 = m_defrag(*m_head, M_NOWAIT);
5145 if (m0 == NULL) {
5146 fp->eth_q_stats.mbuf_defrag_failures++;
5147 rc = ENOBUFS;
5148 } else {
5149 /* defrag successful, try mapping again */
5150 *m_head = m0;
5151 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5152 tx_buf->m_map, m0,
5153 segs, &nsegs, BUS_DMA_NOWAIT);
5154 if (error) {
5155 fp->eth_q_stats.tx_dma_mapping_failure++;
5156 rc = error;
5157 }
5158 }
5159 } else {
5160 /* unknown, unrecoverable mapping error */
5161 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error);
5162 bxe_dump_mbuf(sc, m0, FALSE);
5163 rc = error;
5164 }
5165
5166 goto bxe_tx_encap_continue;
5167 }
5168
5169 tx_bd_avail = bxe_tx_avail(sc, fp);
5170
5171 /* make sure there is enough room in the send queue */
5172 if (__predict_false(tx_bd_avail < (nsegs + 2))) {
5173 /* Recoverable, try again later. */
5174 fp->eth_q_stats.tx_hw_queue_full++;
5175 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5176 rc = ENOMEM;
5177 goto bxe_tx_encap_continue;
5178 }
5179
5180 /* capture the current H/W TX chain high watermark */
5181 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth <
5182 (TX_BD_USABLE - tx_bd_avail))) {
5183 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail);
5184 }
5185
5186 /* make sure it fits in the packet window */
5187 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5188 /*
5189 * The mbuf may be to big for the controller to handle. If the frame
5190 * is a TSO frame we'll need to do an additional check.
5191 */
5192 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5193 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) {
5194 goto bxe_tx_encap_continue; /* OK to send */
5195 } else {
5196 fp->eth_q_stats.tx_window_violation_tso++;
5197 }
5198 } else {
5199 fp->eth_q_stats.tx_window_violation_std++;
5200 }
5201
5202 /* lets try to defragment this mbuf and remap it */
5203 fp->eth_q_stats.mbuf_defrag_attempts++;
5204 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5205
5206 m0 = m_defrag(*m_head, M_NOWAIT);
5207 if (m0 == NULL) {
5208 fp->eth_q_stats.mbuf_defrag_failures++;
5209 /* Ugh, just drop the frame... :( */
5210 rc = ENOBUFS;
5211 } else {
5212 /* defrag successful, try mapping again */
5213 *m_head = m0;
5214 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5215 tx_buf->m_map, m0,
5216 segs, &nsegs, BUS_DMA_NOWAIT);
5217 if (error) {
5218 fp->eth_q_stats.tx_dma_mapping_failure++;
5219 /* No sense in trying to defrag/copy chain, drop it. :( */
5220 rc = error;
5221 } else {
5222 /* if the chain is still too long then drop it */
5223 if(m0->m_pkthdr.csum_flags & CSUM_TSO) {
5224 /*
5225 * in case TSO is enabled nsegs should be checked against
5226 * BXE_TSO_MAX_SEGMENTS
5227 */
5228 if (__predict_false(nsegs > BXE_TSO_MAX_SEGMENTS)) {
5229 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5230 fp->eth_q_stats.nsegs_path1_errors++;
5231 rc = ENODEV;
5232 }
5233 } else {
5234 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5235 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5236 fp->eth_q_stats.nsegs_path2_errors++;
5237 rc = ENODEV;
5238 }
5239 }
5240 }
5241 }
5242 }
5243
5244 bxe_tx_encap_continue:
5245
5246 /* Check for errors */
5247 if (rc) {
5248 if (rc == ENOMEM) {
5249 /* recoverable try again later */
5250 } else {
5251 fp->eth_q_stats.tx_soft_errors++;
5252 fp->eth_q_stats.mbuf_alloc_tx--;
5253 m_freem(*m_head);
5254 *m_head = NULL;
5255 }
5256
5257 return (rc);
5258 }
5259
5260 /* set flag according to packet type (UNICAST_ADDRESS is default) */
5261 if (m0->m_flags & M_BCAST) {
5262 mac_type = BROADCAST_ADDRESS;
5263 } else if (m0->m_flags & M_MCAST) {
5264 mac_type = MULTICAST_ADDRESS;
5265 }
5266
5267 /* store the mbuf into the mbuf ring */
5268 tx_buf->m = m0;
5269 tx_buf->first_bd = fp->tx_bd_prod;
5270 tx_buf->flags = 0;
5271
5272 /* prepare the first transmit (start) BD for the mbuf */
5273 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd;
5274
5275 BLOGD(sc, DBG_TX,
5276 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n",
5277 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
5278
5279 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
5280 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
5281 tx_start_bd->nbytes = htole16(segs[0].ds_len);
5282 total_pkt_size += tx_start_bd->nbytes;
5283 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
5284
5285 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
5286
5287 /* all frames have at least Start BD + Parsing BD */
5288 nbds = nsegs + 1;
5289 tx_start_bd->nbd = htole16(nbds);
5290
5291 if (m0->m_flags & M_VLANTAG) {
5292 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag);
5293 tx_start_bd->bd_flags.as_bitfield |=
5294 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
5295 } else {
5296 /* vf tx, start bd must hold the ethertype for fw to enforce it */
5297 if (IS_VF(sc)) {
5298 /* map ethernet header to find type and header length */
5299 eh = mtod(m0, struct ether_vlan_header *);
5300 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto;
5301 } else {
5302 /* used by FW for packet accounting */
5303 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod);
5304 }
5305 }
5306
5307 /*
5308 * add a parsing BD from the chain. The parsing BD is always added
5309 * though it is only used for TSO and chksum
5310 */
5311 bd_prod = TX_BD_NEXT(bd_prod);
5312
5313 if (m0->m_pkthdr.csum_flags) {
5314 if (m0->m_pkthdr.csum_flags & CSUM_IP) {
5315 fp->eth_q_stats.tx_ofld_frames_csum_ip++;
5316 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
5317 }
5318
5319 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) {
5320 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5321 ETH_TX_BD_FLAGS_L4_CSUM);
5322 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) {
5323 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5324 ETH_TX_BD_FLAGS_IS_UDP |
5325 ETH_TX_BD_FLAGS_L4_CSUM);
5326 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) ||
5327 (m0->m_pkthdr.csum_flags & CSUM_TSO)) {
5328 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
5329 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
5330 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM |
5331 ETH_TX_BD_FLAGS_IS_UDP);
5332 }
5333 }
5334
5335 if (!CHIP_IS_E1x(sc)) {
5336 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2;
5337 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
5338
5339 if (m0->m_pkthdr.csum_flags) {
5340 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data);
5341 }
5342
5343 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE,
5344 mac_type);
5345 } else {
5346 uint16_t global_data = 0;
5347
5348 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x;
5349 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
5350
5351 if (m0->m_pkthdr.csum_flags) {
5352 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x);
5353 }
5354
5355 SET_FLAG(global_data,
5356 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
5357 pbd_e1x->global_data |= htole16(global_data);
5358 }
5359
5360 /* setup the parsing BD with TSO specific info */
5361 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5362 fp->eth_q_stats.tx_ofld_frames_lso++;
5363 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
5364
5365 if (__predict_false(tx_start_bd->nbytes > hlen)) {
5366 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++;
5367
5368 /* split the first BD into header/data making the fw job easy */
5369 nbds++;
5370 tx_start_bd->nbd = htole16(nbds);
5371 tx_start_bd->nbytes = htole16(hlen);
5372
5373 bd_prod = TX_BD_NEXT(bd_prod);
5374
5375 /* new transmit BD after the tx_parse_bd */
5376 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5377 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen));
5378 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen));
5379 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen);
5380 if (tx_total_pkt_size_bd == NULL) {
5381 tx_total_pkt_size_bd = tx_data_bd;
5382 }
5383
5384 BLOGD(sc, DBG_TX,
5385 "TSO split header size is %d (%x:%x) nbds %d\n",
5386 le16toh(tx_start_bd->nbytes),
5387 le32toh(tx_start_bd->addr_hi),
5388 le32toh(tx_start_bd->addr_lo),
5389 nbds);
5390 }
5391
5392 if (!CHIP_IS_E1x(sc)) {
5393 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data);
5394 } else {
5395 bxe_set_pbd_lso(m0, pbd_e1x);
5396 }
5397 }
5398
5399 if (pbd_e2_parsing_data) {
5400 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data);
5401 }
5402
5403 /* prepare remaining BDs, start tx bd contains first seg/frag */
5404 for (i = 1; i < nsegs ; i++) {
5405 bd_prod = TX_BD_NEXT(bd_prod);
5406 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5407 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
5408 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
5409 tx_data_bd->nbytes = htole16(segs[i].ds_len);
5410 if (tx_total_pkt_size_bd == NULL) {
5411 tx_total_pkt_size_bd = tx_data_bd;
5412 }
5413 total_pkt_size += tx_data_bd->nbytes;
5414 }
5415
5416 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd);
5417
5418 if (tx_total_pkt_size_bd != NULL) {
5419 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
5420 }
5421
5422 if (__predict_false(sc->debug & DBG_TX)) {
5423 tmp_bd = tx_buf->first_bd;
5424 for (i = 0; i < nbds; i++)
5425 {
5426 if (i == 0) {
5427 BLOGD(sc, DBG_TX,
5428 "TX Strt: %p bd=%d nbd=%d vlan=0x%x "
5429 "bd_flags=0x%x hdr_nbds=%d\n",
5430 tx_start_bd,
5431 tmp_bd,
5432 le16toh(tx_start_bd->nbd),
5433 le16toh(tx_start_bd->vlan_or_ethertype),
5434 tx_start_bd->bd_flags.as_bitfield,
5435 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS));
5436 } else if (i == 1) {
5437 if (pbd_e1x) {
5438 BLOGD(sc, DBG_TX,
5439 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u "
5440 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x "
5441 "tcp_seq=%u total_hlen_w=%u\n",
5442 pbd_e1x,
5443 tmp_bd,
5444 pbd_e1x->global_data,
5445 pbd_e1x->ip_hlen_w,
5446 pbd_e1x->ip_id,
5447 pbd_e1x->lso_mss,
5448 pbd_e1x->tcp_flags,
5449 pbd_e1x->tcp_pseudo_csum,
5450 pbd_e1x->tcp_send_seq,
5451 le16toh(pbd_e1x->total_hlen_w));
5452 } else { /* if (pbd_e2) */
5453 BLOGD(sc, DBG_TX,
5454 "-> Parse: %p bd=%d dst=%02x:%02x:%02x "
5455 "src=%02x:%02x:%02x parsing_data=0x%x\n",
5456 pbd_e2,
5457 tmp_bd,
5458 pbd_e2->data.mac_addr.dst_hi,
5459 pbd_e2->data.mac_addr.dst_mid,
5460 pbd_e2->data.mac_addr.dst_lo,
5461 pbd_e2->data.mac_addr.src_hi,
5462 pbd_e2->data.mac_addr.src_mid,
5463 pbd_e2->data.mac_addr.src_lo,
5464 pbd_e2->parsing_data);
5465 }
5466 }
5467
5468 if (i != 1) { /* skip parse db as it doesn't hold data */
5469 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd;
5470 BLOGD(sc, DBG_TX,
5471 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n",
5472 tx_data_bd,
5473 tmp_bd,
5474 le16toh(tx_data_bd->nbytes),
5475 le32toh(tx_data_bd->addr_hi),
5476 le32toh(tx_data_bd->addr_lo));
5477 }
5478
5479 tmp_bd = TX_BD_NEXT(tmp_bd);
5480 }
5481 }
5482
5483 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod);
5484
5485 /* update TX BD producer index value for next TX */
5486 bd_prod = TX_BD_NEXT(bd_prod);
5487
5488 /*
5489 * If the chain of tx_bd's describing this frame is adjacent to or spans
5490 * an eth_tx_next_bd element then we need to increment the nbds value.
5491 */
5492 if (TX_BD_IDX(bd_prod) < nbds) {
5493 nbds++;
5494 }
5495
5496 /* don't allow reordering of writes for nbd and packets */
5497 mb();
5498
5499 fp->tx_db.data.prod += nbds;
5500
5501 /* producer points to the next free tx_bd at this point */
5502 fp->tx_pkt_prod++;
5503 fp->tx_bd_prod = bd_prod;
5504
5505 DOORBELL(sc, fp->index, fp->tx_db.raw);
5506
5507 fp->eth_q_stats.tx_pkts++;
5508
5509 /* Prevent speculative reads from getting ahead of the status block. */
5510 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle,
5511 0, 0, BUS_SPACE_BARRIER_READ);
5512
5513 /* Prevent speculative reads from getting ahead of the doorbell. */
5514 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle,
5515 0, 0, BUS_SPACE_BARRIER_READ);
5516
5517 return (0);
5518 }
5519
5520 static void
bxe_tx_start_locked(struct bxe_softc * sc,if_t ifp,struct bxe_fastpath * fp)5521 bxe_tx_start_locked(struct bxe_softc *sc,
5522 if_t ifp,
5523 struct bxe_fastpath *fp)
5524 {
5525 struct mbuf *m = NULL;
5526 int tx_count = 0;
5527 uint16_t tx_bd_avail;
5528
5529 BXE_FP_TX_LOCK_ASSERT(fp);
5530
5531 /* keep adding entries while there are frames to send */
5532 while (!if_sendq_empty(ifp)) {
5533
5534 /*
5535 * check for any frames to send
5536 * dequeue can still be NULL even if queue is not empty
5537 */
5538 m = if_dequeue(ifp);
5539 if (__predict_false(m == NULL)) {
5540 break;
5541 }
5542
5543 /* the mbuf now belongs to us */
5544 fp->eth_q_stats.mbuf_alloc_tx++;
5545
5546 /*
5547 * Put the frame into the transmit ring. If we don't have room,
5548 * place the mbuf back at the head of the TX queue, set the
5549 * OACTIVE flag, and wait for the NIC to drain the chain.
5550 */
5551 if (__predict_false(bxe_tx_encap(fp, &m))) {
5552 fp->eth_q_stats.tx_encap_failures++;
5553 if (m != NULL) {
5554 /* mark the TX queue as full and return the frame */
5555 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5556 if_sendq_prepend(ifp, m);
5557 fp->eth_q_stats.mbuf_alloc_tx--;
5558 fp->eth_q_stats.tx_queue_xoff++;
5559 }
5560
5561 /* stop looking for more work */
5562 break;
5563 }
5564
5565 /* the frame was enqueued successfully */
5566 tx_count++;
5567
5568 /* send a copy of the frame to any BPF listeners. */
5569 ether_bpf_mtap_if(ifp, m);
5570
5571 tx_bd_avail = bxe_tx_avail(sc, fp);
5572
5573 /* handle any completions if we're running low */
5574 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5575 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5576 bxe_txeof(sc, fp);
5577 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
5578 break;
5579 }
5580 }
5581 }
5582
5583 /* all TX packets were dequeued and/or the tx ring is full */
5584 if (tx_count > 0) {
5585 /* reset the TX watchdog timeout timer */
5586 fp->watchdog_timer = BXE_TX_TIMEOUT;
5587 }
5588 }
5589
5590 /* Legacy (non-RSS) dispatch routine */
5591 static void
bxe_tx_start(if_t ifp)5592 bxe_tx_start(if_t ifp)
5593 {
5594 struct bxe_softc *sc;
5595 struct bxe_fastpath *fp;
5596
5597 sc = if_getsoftc(ifp);
5598
5599 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
5600 BLOGW(sc, "Interface not running, ignoring transmit request\n");
5601 return;
5602 }
5603
5604 if (!sc->link_vars.link_up) {
5605 BLOGW(sc, "Interface link is down, ignoring transmit request\n");
5606 return;
5607 }
5608
5609 fp = &sc->fp[0];
5610
5611 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
5612 fp->eth_q_stats.tx_queue_full_return++;
5613 return;
5614 }
5615
5616 BXE_FP_TX_LOCK(fp);
5617 bxe_tx_start_locked(sc, ifp, fp);
5618 BXE_FP_TX_UNLOCK(fp);
5619 }
5620
5621 static int
bxe_tx_mq_start_locked(struct bxe_softc * sc,if_t ifp,struct bxe_fastpath * fp,struct mbuf * m)5622 bxe_tx_mq_start_locked(struct bxe_softc *sc,
5623 if_t ifp,
5624 struct bxe_fastpath *fp,
5625 struct mbuf *m)
5626 {
5627 struct buf_ring *tx_br = fp->tx_br;
5628 struct mbuf *next;
5629 int depth, rc, tx_count;
5630 uint16_t tx_bd_avail;
5631
5632 rc = tx_count = 0;
5633
5634 BXE_FP_TX_LOCK_ASSERT(fp);
5635
5636 if (sc->state != BXE_STATE_OPEN) {
5637 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++;
5638 return ENETDOWN;
5639 }
5640
5641 if (!tx_br) {
5642 BLOGE(sc, "Multiqueue TX and no buf_ring!\n");
5643 return (EINVAL);
5644 }
5645
5646 if (m != NULL) {
5647 rc = drbr_enqueue(ifp, tx_br, m);
5648 if (rc != 0) {
5649 fp->eth_q_stats.tx_soft_errors++;
5650 goto bxe_tx_mq_start_locked_exit;
5651 }
5652 }
5653
5654 if (!sc->link_vars.link_up || !(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
5655 fp->eth_q_stats.tx_request_link_down_failures++;
5656 goto bxe_tx_mq_start_locked_exit;
5657 }
5658
5659 /* fetch the depth of the driver queue */
5660 depth = drbr_inuse(ifp, tx_br);
5661 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) {
5662 fp->eth_q_stats.tx_max_drbr_queue_depth = depth;
5663 }
5664
5665 /* keep adding entries while there are frames to send */
5666 while ((next = drbr_peek(ifp, tx_br)) != NULL) {
5667 /* handle any completions if we're running low */
5668 tx_bd_avail = bxe_tx_avail(sc, fp);
5669 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5670 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5671 bxe_txeof(sc, fp);
5672 tx_bd_avail = bxe_tx_avail(sc, fp);
5673 if (tx_bd_avail < (BXE_TSO_MAX_SEGMENTS + 1)) {
5674 fp->eth_q_stats.bd_avail_too_less_failures++;
5675 m_freem(next);
5676 drbr_advance(ifp, tx_br);
5677 rc = ENOBUFS;
5678 break;
5679 }
5680 }
5681
5682 /* the mbuf now belongs to us */
5683 fp->eth_q_stats.mbuf_alloc_tx++;
5684
5685 /*
5686 * Put the frame into the transmit ring. If we don't have room,
5687 * place the mbuf back at the head of the TX queue, set the
5688 * OACTIVE flag, and wait for the NIC to drain the chain.
5689 */
5690 rc = bxe_tx_encap(fp, &next);
5691 if (__predict_false(rc != 0)) {
5692 fp->eth_q_stats.tx_encap_failures++;
5693 if (next != NULL) {
5694 /* mark the TX queue as full and save the frame */
5695 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5696 drbr_putback(ifp, tx_br, next);
5697 fp->eth_q_stats.mbuf_alloc_tx--;
5698 fp->eth_q_stats.tx_frames_deferred++;
5699 } else
5700 drbr_advance(ifp, tx_br);
5701
5702 /* stop looking for more work */
5703 break;
5704 }
5705
5706 /* the transmit frame was enqueued successfully */
5707 tx_count++;
5708
5709 /* send a copy of the frame to any BPF listeners */
5710 ether_bpf_mtap_if(ifp, next);
5711
5712 drbr_advance(ifp, tx_br);
5713 }
5714
5715 /* all TX packets were dequeued and/or the tx ring is full */
5716 if (tx_count > 0) {
5717 /* reset the TX watchdog timeout timer */
5718 fp->watchdog_timer = BXE_TX_TIMEOUT;
5719 }
5720
5721 bxe_tx_mq_start_locked_exit:
5722 /* If we didn't drain the drbr, enqueue a task in the future to do it. */
5723 if (!drbr_empty(ifp, tx_br)) {
5724 fp->eth_q_stats.tx_mq_not_empty++;
5725 taskqueue_enqueue_timeout(fp->tq, &fp->tx_timeout_task, 1);
5726 }
5727
5728 return (rc);
5729 }
5730
5731 static void
bxe_tx_mq_start_deferred(void * arg,int pending)5732 bxe_tx_mq_start_deferred(void *arg,
5733 int pending)
5734 {
5735 struct bxe_fastpath *fp = (struct bxe_fastpath *)arg;
5736 struct bxe_softc *sc = fp->sc;
5737 if_t ifp = sc->ifp;
5738
5739 BXE_FP_TX_LOCK(fp);
5740 bxe_tx_mq_start_locked(sc, ifp, fp, NULL);
5741 BXE_FP_TX_UNLOCK(fp);
5742 }
5743
5744 /* Multiqueue (TSS) dispatch routine. */
5745 static int
bxe_tx_mq_start(if_t ifp,struct mbuf * m)5746 bxe_tx_mq_start(if_t ifp,
5747 struct mbuf *m)
5748 {
5749 struct bxe_softc *sc = if_getsoftc(ifp);
5750 struct bxe_fastpath *fp;
5751 int fp_index, rc;
5752
5753 fp_index = 0; /* default is the first queue */
5754
5755 /* check if flowid is set */
5756
5757 if (BXE_VALID_FLOWID(m))
5758 fp_index = (m->m_pkthdr.flowid % sc->num_queues);
5759
5760 fp = &sc->fp[fp_index];
5761
5762 if (sc->state != BXE_STATE_OPEN) {
5763 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++;
5764 return ENETDOWN;
5765 }
5766
5767 if (BXE_FP_TX_TRYLOCK(fp)) {
5768 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m);
5769 BXE_FP_TX_UNLOCK(fp);
5770 } else {
5771 rc = drbr_enqueue(ifp, fp->tx_br, m);
5772 taskqueue_enqueue(fp->tq, &fp->tx_task);
5773 }
5774
5775 return (rc);
5776 }
5777
5778 static void
bxe_mq_flush(if_t ifp)5779 bxe_mq_flush(if_t ifp)
5780 {
5781 struct bxe_softc *sc = if_getsoftc(ifp);
5782 struct bxe_fastpath *fp;
5783 struct mbuf *m;
5784 int i;
5785
5786 for (i = 0; i < sc->num_queues; i++) {
5787 fp = &sc->fp[i];
5788
5789 if (fp->state != BXE_FP_STATE_IRQ) {
5790 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n",
5791 fp->index, fp->state);
5792 continue;
5793 }
5794
5795 if (fp->tx_br != NULL) {
5796 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index);
5797 BXE_FP_TX_LOCK(fp);
5798 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) {
5799 m_freem(m);
5800 }
5801 BXE_FP_TX_UNLOCK(fp);
5802 }
5803 }
5804
5805 if_qflush(ifp);
5806 }
5807
5808 static uint16_t
bxe_cid_ilt_lines(struct bxe_softc * sc)5809 bxe_cid_ilt_lines(struct bxe_softc *sc)
5810 {
5811 if (IS_SRIOV(sc)) {
5812 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS);
5813 }
5814 return (L2_ILT_LINES(sc));
5815 }
5816
5817 static void
bxe_ilt_set_info(struct bxe_softc * sc)5818 bxe_ilt_set_info(struct bxe_softc *sc)
5819 {
5820 struct ilt_client_info *ilt_client;
5821 struct ecore_ilt *ilt = sc->ilt;
5822 uint16_t line = 0;
5823
5824 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
5825 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line);
5826
5827 /* CDU */
5828 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
5829 ilt_client->client_num = ILT_CLIENT_CDU;
5830 ilt_client->page_size = CDU_ILT_PAGE_SZ;
5831 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
5832 ilt_client->start = line;
5833 line += bxe_cid_ilt_lines(sc);
5834
5835 if (CNIC_SUPPORT(sc)) {
5836 line += CNIC_ILT_LINES;
5837 }
5838
5839 ilt_client->end = (line - 1);
5840
5841 BLOGD(sc, DBG_LOAD,
5842 "ilt client[CDU]: start %d, end %d, "
5843 "psz 0x%x, flags 0x%x, hw psz %d\n",
5844 ilt_client->start, ilt_client->end,
5845 ilt_client->page_size,
5846 ilt_client->flags,
5847 ilog2(ilt_client->page_size >> 12));
5848
5849 /* QM */
5850 if (QM_INIT(sc->qm_cid_count)) {
5851 ilt_client = &ilt->clients[ILT_CLIENT_QM];
5852 ilt_client->client_num = ILT_CLIENT_QM;
5853 ilt_client->page_size = QM_ILT_PAGE_SZ;
5854 ilt_client->flags = 0;
5855 ilt_client->start = line;
5856
5857 /* 4 bytes for each cid */
5858 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
5859 QM_ILT_PAGE_SZ);
5860
5861 ilt_client->end = (line - 1);
5862
5863 BLOGD(sc, DBG_LOAD,
5864 "ilt client[QM]: start %d, end %d, "
5865 "psz 0x%x, flags 0x%x, hw psz %d\n",
5866 ilt_client->start, ilt_client->end,
5867 ilt_client->page_size, ilt_client->flags,
5868 ilog2(ilt_client->page_size >> 12));
5869 }
5870
5871 if (CNIC_SUPPORT(sc)) {
5872 /* SRC */
5873 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
5874 ilt_client->client_num = ILT_CLIENT_SRC;
5875 ilt_client->page_size = SRC_ILT_PAGE_SZ;
5876 ilt_client->flags = 0;
5877 ilt_client->start = line;
5878 line += SRC_ILT_LINES;
5879 ilt_client->end = (line - 1);
5880
5881 BLOGD(sc, DBG_LOAD,
5882 "ilt client[SRC]: start %d, end %d, "
5883 "psz 0x%x, flags 0x%x, hw psz %d\n",
5884 ilt_client->start, ilt_client->end,
5885 ilt_client->page_size, ilt_client->flags,
5886 ilog2(ilt_client->page_size >> 12));
5887
5888 /* TM */
5889 ilt_client = &ilt->clients[ILT_CLIENT_TM];
5890 ilt_client->client_num = ILT_CLIENT_TM;
5891 ilt_client->page_size = TM_ILT_PAGE_SZ;
5892 ilt_client->flags = 0;
5893 ilt_client->start = line;
5894 line += TM_ILT_LINES;
5895 ilt_client->end = (line - 1);
5896
5897 BLOGD(sc, DBG_LOAD,
5898 "ilt client[TM]: start %d, end %d, "
5899 "psz 0x%x, flags 0x%x, hw psz %d\n",
5900 ilt_client->start, ilt_client->end,
5901 ilt_client->page_size, ilt_client->flags,
5902 ilog2(ilt_client->page_size >> 12));
5903 } else {
5904 ilt->clients[ILT_CLIENT_SRC].flags =
5905 (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
5906 ilt->clients[ILT_CLIENT_TM].flags =
5907 (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
5908 }
5909
5910 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!"));
5911 }
5912
5913 static void
bxe_set_fp_rx_buf_size(struct bxe_softc * sc)5914 bxe_set_fp_rx_buf_size(struct bxe_softc *sc)
5915 {
5916 int i;
5917 uint32_t rx_buf_size;
5918
5919 rx_buf_size = (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
5920
5921 for (i = 0; i < sc->num_queues; i++) {
5922 if(rx_buf_size <= MCLBYTES){
5923 sc->fp[i].rx_buf_size = rx_buf_size;
5924 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5925 }else if (rx_buf_size <= MJUMPAGESIZE){
5926 sc->fp[i].rx_buf_size = rx_buf_size;
5927 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
5928 }else if (rx_buf_size <= (MJUMPAGESIZE + MCLBYTES)){
5929 sc->fp[i].rx_buf_size = MCLBYTES;
5930 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5931 }else if (rx_buf_size <= (2 * MJUMPAGESIZE)){
5932 sc->fp[i].rx_buf_size = MJUMPAGESIZE;
5933 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
5934 }else {
5935 sc->fp[i].rx_buf_size = MCLBYTES;
5936 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5937 }
5938 }
5939 }
5940
5941 static int
bxe_alloc_ilt_mem(struct bxe_softc * sc)5942 bxe_alloc_ilt_mem(struct bxe_softc *sc)
5943 {
5944 int rc = 0;
5945
5946 if ((sc->ilt =
5947 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt),
5948 M_BXE_ILT,
5949 (M_NOWAIT | M_ZERO))) == NULL) {
5950 rc = 1;
5951 }
5952
5953 return (rc);
5954 }
5955
5956 static int
bxe_alloc_ilt_lines_mem(struct bxe_softc * sc)5957 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc)
5958 {
5959 int rc = 0;
5960
5961 if ((sc->ilt->lines =
5962 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES),
5963 M_BXE_ILT,
5964 (M_NOWAIT | M_ZERO))) == NULL) {
5965 rc = 1;
5966 }
5967
5968 return (rc);
5969 }
5970
5971 static void
bxe_free_ilt_mem(struct bxe_softc * sc)5972 bxe_free_ilt_mem(struct bxe_softc *sc)
5973 {
5974 if (sc->ilt != NULL) {
5975 free(sc->ilt, M_BXE_ILT);
5976 sc->ilt = NULL;
5977 }
5978 }
5979
5980 static void
bxe_free_ilt_lines_mem(struct bxe_softc * sc)5981 bxe_free_ilt_lines_mem(struct bxe_softc *sc)
5982 {
5983 if (sc->ilt->lines != NULL) {
5984 free(sc->ilt->lines, M_BXE_ILT);
5985 sc->ilt->lines = NULL;
5986 }
5987 }
5988
5989 static void
bxe_free_mem(struct bxe_softc * sc)5990 bxe_free_mem(struct bxe_softc *sc)
5991 {
5992 int i;
5993
5994 for (i = 0; i < L2_ILT_LINES(sc); i++) {
5995 bxe_dma_free(sc, &sc->context[i].vcxt_dma);
5996 sc->context[i].vcxt = NULL;
5997 sc->context[i].size = 0;
5998 }
5999
6000 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
6001
6002 bxe_free_ilt_lines_mem(sc);
6003
6004 }
6005
6006 static int
bxe_alloc_mem(struct bxe_softc * sc)6007 bxe_alloc_mem(struct bxe_softc *sc)
6008 {
6009
6010 int context_size;
6011 int allocated;
6012 int i;
6013
6014 /*
6015 * Allocate memory for CDU context:
6016 * This memory is allocated separately and not in the generic ILT
6017 * functions because CDU differs in few aspects:
6018 * 1. There can be multiple entities allocating memory for context -
6019 * regular L2, CNIC, and SRIOV drivers. Each separately controls
6020 * its own ILT lines.
6021 * 2. Since CDU page-size is not a single 4KB page (which is the case
6022 * for the other ILT clients), to be efficient we want to support
6023 * allocation of sub-page-size in the last entry.
6024 * 3. Context pointers are used by the driver to pass to FW / update
6025 * the context (for the other ILT clients the pointers are used just to
6026 * free the memory during unload).
6027 */
6028 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc));
6029 for (i = 0, allocated = 0; allocated < context_size; i++) {
6030 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
6031 (context_size - allocated));
6032
6033 if (bxe_dma_alloc(sc, sc->context[i].size,
6034 &sc->context[i].vcxt_dma,
6035 "cdu context") != 0) {
6036 bxe_free_mem(sc);
6037 return (-1);
6038 }
6039
6040 sc->context[i].vcxt =
6041 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
6042
6043 allocated += sc->context[i].size;
6044 }
6045
6046 bxe_alloc_ilt_lines_mem(sc);
6047
6048 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n",
6049 sc->ilt, sc->ilt->start_line, sc->ilt->lines);
6050 {
6051 for (i = 0; i < 4; i++) {
6052 BLOGD(sc, DBG_LOAD,
6053 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n",
6054 i,
6055 sc->ilt->clients[i].page_size,
6056 sc->ilt->clients[i].start,
6057 sc->ilt->clients[i].end,
6058 sc->ilt->clients[i].client_num,
6059 sc->ilt->clients[i].flags);
6060 }
6061 }
6062 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
6063 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n");
6064 bxe_free_mem(sc);
6065 return (-1);
6066 }
6067
6068 return (0);
6069 }
6070
6071 static void
bxe_free_rx_bd_chain(struct bxe_fastpath * fp)6072 bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
6073 {
6074 int i;
6075
6076 if (fp->rx_mbuf_tag == NULL) {
6077 return;
6078 }
6079
6080 /* free all mbufs and unload all maps */
6081 for (i = 0; i < RX_BD_TOTAL; i++) {
6082 if (fp->rx_mbuf_chain[i].m_map != NULL) {
6083 bus_dmamap_sync(fp->rx_mbuf_tag,
6084 fp->rx_mbuf_chain[i].m_map,
6085 BUS_DMASYNC_POSTREAD);
6086 bus_dmamap_unload(fp->rx_mbuf_tag,
6087 fp->rx_mbuf_chain[i].m_map);
6088 }
6089
6090 if (fp->rx_mbuf_chain[i].m != NULL) {
6091 m_freem(fp->rx_mbuf_chain[i].m);
6092 fp->rx_mbuf_chain[i].m = NULL;
6093 fp->eth_q_stats.mbuf_alloc_rx--;
6094 }
6095 }
6096 }
6097
6098 static void
bxe_free_tpa_pool(struct bxe_fastpath * fp)6099 bxe_free_tpa_pool(struct bxe_fastpath *fp)
6100 {
6101 struct bxe_softc *sc;
6102 int i, max_agg_queues;
6103
6104 sc = fp->sc;
6105
6106 if (fp->rx_mbuf_tag == NULL) {
6107 return;
6108 }
6109
6110 max_agg_queues = MAX_AGG_QS(sc);
6111
6112 /* release all mbufs and unload all DMA maps in the TPA pool */
6113 for (i = 0; i < max_agg_queues; i++) {
6114 if (fp->rx_tpa_info[i].bd.m_map != NULL) {
6115 bus_dmamap_sync(fp->rx_mbuf_tag,
6116 fp->rx_tpa_info[i].bd.m_map,
6117 BUS_DMASYNC_POSTREAD);
6118 bus_dmamap_unload(fp->rx_mbuf_tag,
6119 fp->rx_tpa_info[i].bd.m_map);
6120 }
6121
6122 if (fp->rx_tpa_info[i].bd.m != NULL) {
6123 m_freem(fp->rx_tpa_info[i].bd.m);
6124 fp->rx_tpa_info[i].bd.m = NULL;
6125 fp->eth_q_stats.mbuf_alloc_tpa--;
6126 }
6127 }
6128 }
6129
6130 static void
bxe_free_sge_chain(struct bxe_fastpath * fp)6131 bxe_free_sge_chain(struct bxe_fastpath *fp)
6132 {
6133 int i;
6134
6135 if (fp->rx_sge_mbuf_tag == NULL) {
6136 return;
6137 }
6138
6139 /* rree all mbufs and unload all maps */
6140 for (i = 0; i < RX_SGE_TOTAL; i++) {
6141 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) {
6142 bus_dmamap_sync(fp->rx_sge_mbuf_tag,
6143 fp->rx_sge_mbuf_chain[i].m_map,
6144 BUS_DMASYNC_POSTREAD);
6145 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
6146 fp->rx_sge_mbuf_chain[i].m_map);
6147 }
6148
6149 if (fp->rx_sge_mbuf_chain[i].m != NULL) {
6150 m_freem(fp->rx_sge_mbuf_chain[i].m);
6151 fp->rx_sge_mbuf_chain[i].m = NULL;
6152 fp->eth_q_stats.mbuf_alloc_sge--;
6153 }
6154 }
6155 }
6156
6157 static void
bxe_free_fp_buffers(struct bxe_softc * sc)6158 bxe_free_fp_buffers(struct bxe_softc *sc)
6159 {
6160 struct bxe_fastpath *fp;
6161 int i;
6162
6163 for (i = 0; i < sc->num_queues; i++) {
6164 fp = &sc->fp[i];
6165
6166 if (fp->tx_br != NULL) {
6167 /* just in case bxe_mq_flush() wasn't called */
6168 if (mtx_initialized(&fp->tx_mtx)) {
6169 struct mbuf *m;
6170
6171 BXE_FP_TX_LOCK(fp);
6172 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL)
6173 m_freem(m);
6174 BXE_FP_TX_UNLOCK(fp);
6175 }
6176 }
6177
6178 /* free all RX buffers */
6179 bxe_free_rx_bd_chain(fp);
6180 bxe_free_tpa_pool(fp);
6181 bxe_free_sge_chain(fp);
6182
6183 if (fp->eth_q_stats.mbuf_alloc_rx != 0) {
6184 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n",
6185 fp->eth_q_stats.mbuf_alloc_rx);
6186 }
6187
6188 if (fp->eth_q_stats.mbuf_alloc_sge != 0) {
6189 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6190 fp->eth_q_stats.mbuf_alloc_sge);
6191 }
6192
6193 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) {
6194 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6195 fp->eth_q_stats.mbuf_alloc_tpa);
6196 }
6197
6198 if (fp->eth_q_stats.mbuf_alloc_tx != 0) {
6199 BLOGE(sc, "failed to release tx mbufs (%d left)\n",
6200 fp->eth_q_stats.mbuf_alloc_tx);
6201 }
6202
6203 /* XXX verify all mbufs were reclaimed */
6204 }
6205 }
6206
6207 static int
bxe_alloc_rx_bd_mbuf(struct bxe_fastpath * fp,uint16_t prev_index,uint16_t index)6208 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
6209 uint16_t prev_index,
6210 uint16_t index)
6211 {
6212 struct bxe_sw_rx_bd *rx_buf;
6213 struct eth_rx_bd *rx_bd;
6214 bus_dma_segment_t segs[1];
6215 bus_dmamap_t map;
6216 struct mbuf *m;
6217 int nsegs, rc;
6218
6219 rc = 0;
6220
6221 /* allocate the new RX BD mbuf */
6222 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6223 if (__predict_false(m == NULL)) {
6224 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++;
6225 return (ENOBUFS);
6226 }
6227
6228 fp->eth_q_stats.mbuf_alloc_rx++;
6229
6230 /* initialize the mbuf buffer length */
6231 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6232
6233 /* map the mbuf into non-paged pool */
6234 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6235 fp->rx_mbuf_spare_map,
6236 m, segs, &nsegs, BUS_DMA_NOWAIT);
6237 if (__predict_false(rc != 0)) {
6238 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++;
6239 m_freem(m);
6240 fp->eth_q_stats.mbuf_alloc_rx--;
6241 return (rc);
6242 }
6243
6244 /* all mbufs must map to a single segment */
6245 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6246
6247 /* release any existing RX BD mbuf mappings */
6248
6249 if (prev_index != index) {
6250 rx_buf = &fp->rx_mbuf_chain[prev_index];
6251
6252 if (rx_buf->m_map != NULL) {
6253 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6254 BUS_DMASYNC_POSTREAD);
6255 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6256 }
6257
6258 /*
6259 * We only get here from bxe_rxeof() when the maximum number
6260 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already
6261 * holds the mbuf in the prev_index so it's OK to NULL it out
6262 * here without concern of a memory leak.
6263 */
6264 fp->rx_mbuf_chain[prev_index].m = NULL;
6265 }
6266
6267 rx_buf = &fp->rx_mbuf_chain[index];
6268
6269 if (rx_buf->m_map != NULL) {
6270 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6271 BUS_DMASYNC_POSTREAD);
6272 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6273 }
6274
6275 /* save the mbuf and mapping info for a future packet */
6276 map = (prev_index != index) ?
6277 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map;
6278 rx_buf->m_map = fp->rx_mbuf_spare_map;
6279 fp->rx_mbuf_spare_map = map;
6280 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6281 BUS_DMASYNC_PREREAD);
6282 rx_buf->m = m;
6283
6284 rx_bd = &fp->rx_chain[index];
6285 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6286 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6287
6288 return (rc);
6289 }
6290
6291 static int
bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath * fp,int queue)6292 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
6293 int queue)
6294 {
6295 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
6296 bus_dma_segment_t segs[1];
6297 bus_dmamap_t map;
6298 struct mbuf *m;
6299 int nsegs;
6300 int rc = 0;
6301
6302 /* allocate the new TPA mbuf */
6303 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6304 if (__predict_false(m == NULL)) {
6305 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++;
6306 return (ENOBUFS);
6307 }
6308
6309 fp->eth_q_stats.mbuf_alloc_tpa++;
6310
6311 /* initialize the mbuf buffer length */
6312 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6313
6314 /* map the mbuf into non-paged pool */
6315 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6316 fp->rx_tpa_info_mbuf_spare_map,
6317 m, segs, &nsegs, BUS_DMA_NOWAIT);
6318 if (__predict_false(rc != 0)) {
6319 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++;
6320 m_free(m);
6321 fp->eth_q_stats.mbuf_alloc_tpa--;
6322 return (rc);
6323 }
6324
6325 /* all mbufs must map to a single segment */
6326 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6327
6328 /* release any existing TPA mbuf mapping */
6329 if (tpa_info->bd.m_map != NULL) {
6330 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6331 BUS_DMASYNC_POSTREAD);
6332 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map);
6333 }
6334
6335 /* save the mbuf and mapping info for the TPA mbuf */
6336 map = tpa_info->bd.m_map;
6337 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map;
6338 fp->rx_tpa_info_mbuf_spare_map = map;
6339 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6340 BUS_DMASYNC_PREREAD);
6341 tpa_info->bd.m = m;
6342 tpa_info->seg = segs[0];
6343
6344 return (rc);
6345 }
6346
6347 /*
6348 * Allocate an mbuf and assign it to the receive scatter gather chain. The
6349 * caller must take care to save a copy of the existing mbuf in the SG mbuf
6350 * chain.
6351 */
6352 static int
bxe_alloc_rx_sge_mbuf(struct bxe_fastpath * fp,uint16_t index)6353 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
6354 uint16_t index)
6355 {
6356 struct bxe_sw_rx_bd *sge_buf;
6357 struct eth_rx_sge *sge;
6358 bus_dma_segment_t segs[1];
6359 bus_dmamap_t map;
6360 struct mbuf *m;
6361 int nsegs;
6362 int rc = 0;
6363
6364 /* allocate a new SGE mbuf */
6365 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE);
6366 if (__predict_false(m == NULL)) {
6367 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++;
6368 return (ENOMEM);
6369 }
6370
6371 fp->eth_q_stats.mbuf_alloc_sge++;
6372
6373 /* initialize the mbuf buffer length */
6374 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE;
6375
6376 /* map the SGE mbuf into non-paged pool */
6377 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag,
6378 fp->rx_sge_mbuf_spare_map,
6379 m, segs, &nsegs, BUS_DMA_NOWAIT);
6380 if (__predict_false(rc != 0)) {
6381 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++;
6382 m_freem(m);
6383 fp->eth_q_stats.mbuf_alloc_sge--;
6384 return (rc);
6385 }
6386
6387 /* all mbufs must map to a single segment */
6388 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6389
6390 sge_buf = &fp->rx_sge_mbuf_chain[index];
6391
6392 /* release any existing SGE mbuf mapping */
6393 if (sge_buf->m_map != NULL) {
6394 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6395 BUS_DMASYNC_POSTREAD);
6396 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map);
6397 }
6398
6399 /* save the mbuf and mapping info for a future packet */
6400 map = sge_buf->m_map;
6401 sge_buf->m_map = fp->rx_sge_mbuf_spare_map;
6402 fp->rx_sge_mbuf_spare_map = map;
6403 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6404 BUS_DMASYNC_PREREAD);
6405 sge_buf->m = m;
6406
6407 sge = &fp->rx_sge_chain[index];
6408 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6409 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6410
6411 return (rc);
6412 }
6413
6414 static __noinline int
bxe_alloc_fp_buffers(struct bxe_softc * sc)6415 bxe_alloc_fp_buffers(struct bxe_softc *sc)
6416 {
6417 struct bxe_fastpath *fp;
6418 int i, j, rc = 0;
6419 int ring_prod, cqe_ring_prod;
6420 int max_agg_queues;
6421
6422 for (i = 0; i < sc->num_queues; i++) {
6423 fp = &sc->fp[i];
6424
6425 ring_prod = cqe_ring_prod = 0;
6426 fp->rx_bd_cons = 0;
6427 fp->rx_cq_cons = 0;
6428
6429 /* allocate buffers for the RX BDs in RX BD chain */
6430 for (j = 0; j < sc->max_rx_bufs; j++) {
6431 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod);
6432 if (rc != 0) {
6433 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
6434 i, rc);
6435 goto bxe_alloc_fp_buffers_error;
6436 }
6437
6438 ring_prod = RX_BD_NEXT(ring_prod);
6439 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod);
6440 }
6441
6442 fp->rx_bd_prod = ring_prod;
6443 fp->rx_cq_prod = cqe_ring_prod;
6444 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0;
6445
6446 max_agg_queues = MAX_AGG_QS(sc);
6447
6448 fp->tpa_enable = TRUE;
6449
6450 /* fill the TPA pool */
6451 for (j = 0; j < max_agg_queues; j++) {
6452 rc = bxe_alloc_rx_tpa_mbuf(fp, j);
6453 if (rc != 0) {
6454 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n",
6455 i, j);
6456 fp->tpa_enable = FALSE;
6457 goto bxe_alloc_fp_buffers_error;
6458 }
6459
6460 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP;
6461 }
6462
6463 if (fp->tpa_enable) {
6464 /* fill the RX SGE chain */
6465 ring_prod = 0;
6466 for (j = 0; j < RX_SGE_USABLE; j++) {
6467 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod);
6468 if (rc != 0) {
6469 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n",
6470 i, ring_prod);
6471 fp->tpa_enable = FALSE;
6472 ring_prod = 0;
6473 goto bxe_alloc_fp_buffers_error;
6474 }
6475
6476 ring_prod = RX_SGE_NEXT(ring_prod);
6477 }
6478
6479 fp->rx_sge_prod = ring_prod;
6480 }
6481 }
6482
6483 return (0);
6484
6485 bxe_alloc_fp_buffers_error:
6486
6487 /* unwind what was already allocated */
6488 bxe_free_rx_bd_chain(fp);
6489 bxe_free_tpa_pool(fp);
6490 bxe_free_sge_chain(fp);
6491
6492 return (ENOBUFS);
6493 }
6494
6495 static void
bxe_free_fw_stats_mem(struct bxe_softc * sc)6496 bxe_free_fw_stats_mem(struct bxe_softc *sc)
6497 {
6498 bxe_dma_free(sc, &sc->fw_stats_dma);
6499
6500 sc->fw_stats_num = 0;
6501
6502 sc->fw_stats_req_size = 0;
6503 sc->fw_stats_req = NULL;
6504 sc->fw_stats_req_mapping = 0;
6505
6506 sc->fw_stats_data_size = 0;
6507 sc->fw_stats_data = NULL;
6508 sc->fw_stats_data_mapping = 0;
6509 }
6510
6511 static int
bxe_alloc_fw_stats_mem(struct bxe_softc * sc)6512 bxe_alloc_fw_stats_mem(struct bxe_softc *sc)
6513 {
6514 uint8_t num_queue_stats;
6515 int num_groups;
6516
6517 /* number of queues for statistics is number of eth queues */
6518 num_queue_stats = BXE_NUM_ETH_QUEUES(sc);
6519
6520 /*
6521 * Total number of FW statistics requests =
6522 * 1 for port stats + 1 for PF stats + num of queues
6523 */
6524 sc->fw_stats_num = (2 + num_queue_stats);
6525
6526 /*
6527 * Request is built from stats_query_header and an array of
6528 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
6529 * rules. The real number or requests is configured in the
6530 * stats_query_header.
6531 */
6532 num_groups =
6533 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) +
6534 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0));
6535
6536 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n",
6537 sc->fw_stats_num, num_groups);
6538
6539 sc->fw_stats_req_size =
6540 (sizeof(struct stats_query_header) +
6541 (num_groups * sizeof(struct stats_query_cmd_group)));
6542
6543 /*
6544 * Data for statistics requests + stats_counter.
6545 * stats_counter holds per-STORM counters that are incremented when
6546 * STORM has finished with the current request. Memory for FCoE
6547 * offloaded statistics are counted anyway, even if they will not be sent.
6548 * VF stats are not accounted for here as the data of VF stats is stored
6549 * in memory allocated by the VF, not here.
6550 */
6551 sc->fw_stats_data_size =
6552 (sizeof(struct stats_counter) +
6553 sizeof(struct per_port_stats) +
6554 sizeof(struct per_pf_stats) +
6555 /* sizeof(struct fcoe_statistics_params) + */
6556 (sizeof(struct per_queue_stats) * num_queue_stats));
6557
6558 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
6559 &sc->fw_stats_dma, "fw stats") != 0) {
6560 bxe_free_fw_stats_mem(sc);
6561 return (-1);
6562 }
6563
6564 /* set up the shortcuts */
6565
6566 sc->fw_stats_req =
6567 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr;
6568 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
6569
6570 sc->fw_stats_data =
6571 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr +
6572 sc->fw_stats_req_size);
6573 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
6574 sc->fw_stats_req_size);
6575
6576 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n",
6577 (uintmax_t)sc->fw_stats_req_mapping);
6578
6579 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n",
6580 (uintmax_t)sc->fw_stats_data_mapping);
6581
6582 return (0);
6583 }
6584
6585 /*
6586 * Bits map:
6587 * 0-7 - Engine0 load counter.
6588 * 8-15 - Engine1 load counter.
6589 * 16 - Engine0 RESET_IN_PROGRESS bit.
6590 * 17 - Engine1 RESET_IN_PROGRESS bit.
6591 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
6592 * function on the engine
6593 * 19 - Engine1 ONE_IS_LOADED.
6594 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
6595 * leader to complete (check for both RESET_IN_PROGRESS bits and not
6596 * for just the one belonging to its engine).
6597 */
6598 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
6599 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff
6600 #define BXE_PATH0_LOAD_CNT_SHIFT 0
6601 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00
6602 #define BXE_PATH1_LOAD_CNT_SHIFT 8
6603 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000
6604 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000
6605 #define BXE_GLOBAL_RESET_BIT 0x00040000
6606
6607 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
6608 static void
bxe_set_reset_global(struct bxe_softc * sc)6609 bxe_set_reset_global(struct bxe_softc *sc)
6610 {
6611 uint32_t val;
6612 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6613 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6614 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT);
6615 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6616 }
6617
6618 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
6619 static void
bxe_clear_reset_global(struct bxe_softc * sc)6620 bxe_clear_reset_global(struct bxe_softc *sc)
6621 {
6622 uint32_t val;
6623 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6624 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6625 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT));
6626 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6627 }
6628
6629 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
6630 static uint8_t
bxe_reset_is_global(struct bxe_softc * sc)6631 bxe_reset_is_global(struct bxe_softc *sc)
6632 {
6633 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6634 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val);
6635 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE;
6636 }
6637
6638 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
6639 static void
bxe_set_reset_done(struct bxe_softc * sc)6640 bxe_set_reset_done(struct bxe_softc *sc)
6641 {
6642 uint32_t val;
6643 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6644 BXE_PATH0_RST_IN_PROG_BIT;
6645
6646 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6647
6648 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6649 /* Clear the bit */
6650 val &= ~bit;
6651 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6652
6653 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6654 }
6655
6656 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
6657 static void
bxe_set_reset_in_progress(struct bxe_softc * sc)6658 bxe_set_reset_in_progress(struct bxe_softc *sc)
6659 {
6660 uint32_t val;
6661 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6662 BXE_PATH0_RST_IN_PROG_BIT;
6663
6664 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6665
6666 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6667 /* Set the bit */
6668 val |= bit;
6669 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6670
6671 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6672 }
6673
6674 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
6675 static uint8_t
bxe_reset_is_done(struct bxe_softc * sc,int engine)6676 bxe_reset_is_done(struct bxe_softc *sc,
6677 int engine)
6678 {
6679 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6680 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT :
6681 BXE_PATH0_RST_IN_PROG_BIT;
6682
6683 /* return false if bit is set */
6684 return (val & bit) ? FALSE : TRUE;
6685 }
6686
6687 /* get the load status for an engine, should be run under rtnl lock */
6688 static uint8_t
bxe_get_load_status(struct bxe_softc * sc,int engine)6689 bxe_get_load_status(struct bxe_softc *sc,
6690 int engine)
6691 {
6692 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK :
6693 BXE_PATH0_LOAD_CNT_MASK;
6694 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT :
6695 BXE_PATH0_LOAD_CNT_SHIFT;
6696 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6697
6698 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6699
6700 val = ((val & mask) >> shift);
6701
6702 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val);
6703
6704 return (val != 0);
6705 }
6706
6707 /* set pf load mark */
6708 /* XXX needs to be under rtnl lock */
6709 static void
bxe_set_pf_load(struct bxe_softc * sc)6710 bxe_set_pf_load(struct bxe_softc *sc)
6711 {
6712 uint32_t val;
6713 uint32_t val1;
6714 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6715 BXE_PATH0_LOAD_CNT_MASK;
6716 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6717 BXE_PATH0_LOAD_CNT_SHIFT;
6718
6719 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6720
6721 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6722 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6723
6724 /* get the current counter value */
6725 val1 = ((val & mask) >> shift);
6726
6727 /* set bit of this PF */
6728 val1 |= (1 << SC_ABS_FUNC(sc));
6729
6730 /* clear the old value */
6731 val &= ~mask;
6732
6733 /* set the new one */
6734 val |= ((val1 << shift) & mask);
6735
6736 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6737
6738 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6739 }
6740
6741 /* clear pf load mark */
6742 /* XXX needs to be under rtnl lock */
6743 static uint8_t
bxe_clear_pf_load(struct bxe_softc * sc)6744 bxe_clear_pf_load(struct bxe_softc *sc)
6745 {
6746 uint32_t val1, val;
6747 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6748 BXE_PATH0_LOAD_CNT_MASK;
6749 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6750 BXE_PATH0_LOAD_CNT_SHIFT;
6751
6752 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6753 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6754 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val);
6755
6756 /* get the current counter value */
6757 val1 = (val & mask) >> shift;
6758
6759 /* clear bit of that PF */
6760 val1 &= ~(1 << SC_ABS_FUNC(sc));
6761
6762 /* clear the old value */
6763 val &= ~mask;
6764
6765 /* set the new one */
6766 val |= ((val1 << shift) & mask);
6767
6768 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6769 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6770 return (val1 != 0);
6771 }
6772
6773 /* send load requrest to mcp and analyze response */
6774 static int
bxe_nic_load_request(struct bxe_softc * sc,uint32_t * load_code)6775 bxe_nic_load_request(struct bxe_softc *sc,
6776 uint32_t *load_code)
6777 {
6778 /* init fw_seq */
6779 sc->fw_seq =
6780 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
6781 DRV_MSG_SEQ_NUMBER_MASK);
6782
6783 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq);
6784
6785 /* get the current FW pulse sequence */
6786 sc->fw_drv_pulse_wr_seq =
6787 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
6788 DRV_PULSE_SEQ_MASK);
6789
6790 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n",
6791 sc->fw_drv_pulse_wr_seq);
6792
6793 /* load request */
6794 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6795 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6796
6797 /* if the MCP fails to respond we must abort */
6798 if (!(*load_code)) {
6799 BLOGE(sc, "MCP response failure!\n");
6800 return (-1);
6801 }
6802
6803 /* if MCP refused then must abort */
6804 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
6805 BLOGE(sc, "MCP refused load request\n");
6806 return (-1);
6807 }
6808
6809 return (0);
6810 }
6811
6812 /*
6813 * Check whether another PF has already loaded FW to chip. In virtualized
6814 * environments a pf from anoth VM may have already initialized the device
6815 * including loading FW.
6816 */
6817 static int
bxe_nic_load_analyze_req(struct bxe_softc * sc,uint32_t load_code)6818 bxe_nic_load_analyze_req(struct bxe_softc *sc,
6819 uint32_t load_code)
6820 {
6821 uint32_t my_fw, loaded_fw;
6822
6823 /* is another pf loaded on this engine? */
6824 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6825 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6826 /* build my FW version dword */
6827 my_fw = (BCM_5710_FW_MAJOR_VERSION +
6828 (BCM_5710_FW_MINOR_VERSION << 8 ) +
6829 (BCM_5710_FW_REVISION_VERSION << 16) +
6830 (BCM_5710_FW_ENGINEERING_VERSION << 24));
6831
6832 /* read loaded FW from chip */
6833 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
6834 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n",
6835 loaded_fw, my_fw);
6836
6837 /* abort nic load if version mismatch */
6838 if (my_fw != loaded_fw) {
6839 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)",
6840 loaded_fw, my_fw);
6841 return (-1);
6842 }
6843 }
6844
6845 return (0);
6846 }
6847
6848 /* mark PMF if applicable */
6849 static void
bxe_nic_load_pmf(struct bxe_softc * sc,uint32_t load_code)6850 bxe_nic_load_pmf(struct bxe_softc *sc,
6851 uint32_t load_code)
6852 {
6853 uint32_t ncsi_oem_data_addr;
6854
6855 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6856 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
6857 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
6858 /*
6859 * Barrier here for ordering between the writing to sc->port.pmf here
6860 * and reading it from the periodic task.
6861 */
6862 sc->port.pmf = 1;
6863 mb();
6864 } else {
6865 sc->port.pmf = 0;
6866 }
6867
6868 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf);
6869
6870 /* XXX needed? */
6871 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
6872 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
6873 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
6874 if (ncsi_oem_data_addr) {
6875 REG_WR(sc,
6876 (ncsi_oem_data_addr +
6877 offsetof(struct glob_ncsi_oem_data, driver_version)),
6878 0);
6879 }
6880 }
6881 }
6882 }
6883
6884 static void
bxe_read_mf_cfg(struct bxe_softc * sc)6885 bxe_read_mf_cfg(struct bxe_softc *sc)
6886 {
6887 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
6888 int abs_func;
6889 int vn;
6890
6891 if (BXE_NOMCP(sc)) {
6892 return; /* what should be the default bvalue in this case */
6893 }
6894
6895 /*
6896 * The formula for computing the absolute function number is...
6897 * For 2 port configuration (4 functions per port):
6898 * abs_func = 2 * vn + SC_PORT + SC_PATH
6899 * For 4 port configuration (2 functions per port):
6900 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
6901 */
6902 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
6903 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
6904 if (abs_func >= E1H_FUNC_MAX) {
6905 break;
6906 }
6907 sc->devinfo.mf_info.mf_config[vn] =
6908 MFCFG_RD(sc, func_mf_config[abs_func].config);
6909 }
6910
6911 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
6912 FUNC_MF_CFG_FUNC_DISABLED) {
6913 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n");
6914 sc->flags |= BXE_MF_FUNC_DIS;
6915 } else {
6916 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n");
6917 sc->flags &= ~BXE_MF_FUNC_DIS;
6918 }
6919 }
6920
6921 /* acquire split MCP access lock register */
bxe_acquire_alr(struct bxe_softc * sc)6922 static int bxe_acquire_alr(struct bxe_softc *sc)
6923 {
6924 uint32_t j, val;
6925
6926 for (j = 0; j < 1000; j++) {
6927 val = (1UL << 31);
6928 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
6929 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
6930 if (val & (1L << 31))
6931 break;
6932
6933 DELAY(5000);
6934 }
6935
6936 if (!(val & (1L << 31))) {
6937 BLOGE(sc, "Cannot acquire MCP access lock register\n");
6938 return (-1);
6939 }
6940
6941 return (0);
6942 }
6943
6944 /* release split MCP access lock register */
bxe_release_alr(struct bxe_softc * sc)6945 static void bxe_release_alr(struct bxe_softc *sc)
6946 {
6947 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
6948 }
6949
6950 static void
bxe_fan_failure(struct bxe_softc * sc)6951 bxe_fan_failure(struct bxe_softc *sc)
6952 {
6953 int port = SC_PORT(sc);
6954 uint32_t ext_phy_config;
6955
6956 /* mark the failure */
6957 ext_phy_config =
6958 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
6959
6960 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
6961 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
6962 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
6963 ext_phy_config);
6964
6965 /* log the failure */
6966 BLOGW(sc, "Fan Failure has caused the driver to shutdown "
6967 "the card to prevent permanent damage. "
6968 "Please contact OEM Support for assistance\n");
6969
6970 /* XXX */
6971 #if 1
6972 bxe_panic(sc, ("Schedule task to handle fan failure\n"));
6973 #else
6974 /*
6975 * Schedule device reset (unload)
6976 * This is due to some boards consuming sufficient power when driver is
6977 * up to overheat if fan fails.
6978 */
6979 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state);
6980 schedule_delayed_work(&sc->sp_rtnl_task, 0);
6981 #endif
6982 }
6983
6984 /* this function is called upon a link interrupt */
6985 static void
bxe_link_attn(struct bxe_softc * sc)6986 bxe_link_attn(struct bxe_softc *sc)
6987 {
6988 uint32_t pause_enabled = 0;
6989 struct host_port_stats *pstats;
6990 int cmng_fns;
6991 struct bxe_fastpath *fp;
6992 int i;
6993
6994 /* Make sure that we are synced with the current statistics */
6995 bxe_stats_handle(sc, STATS_EVENT_STOP);
6996 BLOGD(sc, DBG_LOAD, "link_vars phy_flags : %x\n", sc->link_vars.phy_flags);
6997 elink_link_update(&sc->link_params, &sc->link_vars);
6998
6999 if (sc->link_vars.link_up) {
7000
7001 /* dropless flow control */
7002 if (!CHIP_IS_E1(sc) && sc->dropless_fc) {
7003 pause_enabled = 0;
7004
7005 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
7006 pause_enabled = 1;
7007 }
7008
7009 REG_WR(sc,
7010 (BAR_USTRORM_INTMEM +
7011 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
7012 pause_enabled);
7013 }
7014
7015 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
7016 pstats = BXE_SP(sc, port_stats);
7017 /* reset old mac stats */
7018 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx));
7019 }
7020
7021 if (sc->state == BXE_STATE_OPEN) {
7022 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
7023 /* Restart tx when the link comes back. */
7024 FOR_EACH_ETH_QUEUE(sc, i) {
7025 fp = &sc->fp[i];
7026 taskqueue_enqueue(fp->tq, &fp->tx_task);
7027 }
7028 }
7029
7030 }
7031
7032 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
7033 cmng_fns = bxe_get_cmng_fns_mode(sc);
7034
7035 if (cmng_fns != CMNG_FNS_NONE) {
7036 bxe_cmng_fns_init(sc, FALSE, cmng_fns);
7037 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7038 } else {
7039 /* rate shaping and fairness are disabled */
7040 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n");
7041 }
7042 }
7043
7044 bxe_link_report_locked(sc);
7045
7046 if (IS_MF(sc)) {
7047 ; // XXX bxe_link_sync_notify(sc);
7048 }
7049 }
7050
7051 static void
bxe_attn_int_asserted(struct bxe_softc * sc,uint32_t asserted)7052 bxe_attn_int_asserted(struct bxe_softc *sc,
7053 uint32_t asserted)
7054 {
7055 int port = SC_PORT(sc);
7056 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7057 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7058 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
7059 NIG_REG_MASK_INTERRUPT_PORT0;
7060 uint32_t aeu_mask;
7061 uint32_t nig_mask = 0;
7062 uint32_t reg_addr;
7063 uint32_t igu_acked;
7064 uint32_t cnt;
7065
7066 if (sc->attn_state & asserted) {
7067 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted);
7068 }
7069
7070 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7071
7072 aeu_mask = REG_RD(sc, aeu_addr);
7073
7074 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n",
7075 aeu_mask, asserted);
7076
7077 aeu_mask &= ~(asserted & 0x3ff);
7078
7079 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
7080
7081 REG_WR(sc, aeu_addr, aeu_mask);
7082
7083 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7084
7085 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
7086 sc->attn_state |= asserted;
7087 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
7088
7089 if (asserted & ATTN_HARD_WIRED_MASK) {
7090 if (asserted & ATTN_NIG_FOR_FUNC) {
7091
7092 bxe_acquire_phy_lock(sc);
7093 /* save nig interrupt mask */
7094 nig_mask = REG_RD(sc, nig_int_mask_addr);
7095
7096 /* If nig_mask is not set, no need to call the update function */
7097 if (nig_mask) {
7098 REG_WR(sc, nig_int_mask_addr, 0);
7099
7100 bxe_link_attn(sc);
7101 }
7102
7103 /* handle unicore attn? */
7104 }
7105
7106 if (asserted & ATTN_SW_TIMER_4_FUNC) {
7107 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n");
7108 }
7109
7110 if (asserted & GPIO_2_FUNC) {
7111 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n");
7112 }
7113
7114 if (asserted & GPIO_3_FUNC) {
7115 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n");
7116 }
7117
7118 if (asserted & GPIO_4_FUNC) {
7119 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n");
7120 }
7121
7122 if (port == 0) {
7123 if (asserted & ATTN_GENERAL_ATTN_1) {
7124 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n");
7125 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
7126 }
7127 if (asserted & ATTN_GENERAL_ATTN_2) {
7128 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n");
7129 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
7130 }
7131 if (asserted & ATTN_GENERAL_ATTN_3) {
7132 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n");
7133 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
7134 }
7135 } else {
7136 if (asserted & ATTN_GENERAL_ATTN_4) {
7137 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n");
7138 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
7139 }
7140 if (asserted & ATTN_GENERAL_ATTN_5) {
7141 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n");
7142 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
7143 }
7144 if (asserted & ATTN_GENERAL_ATTN_6) {
7145 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n");
7146 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
7147 }
7148 }
7149 } /* hardwired */
7150
7151 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7152 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET);
7153 } else {
7154 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
7155 }
7156
7157 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n",
7158 asserted,
7159 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
7160 REG_WR(sc, reg_addr, asserted);
7161
7162 /* now set back the mask */
7163 if (asserted & ATTN_NIG_FOR_FUNC) {
7164 /*
7165 * Verify that IGU ack through BAR was written before restoring
7166 * NIG mask. This loop should exit after 2-3 iterations max.
7167 */
7168 if (sc->devinfo.int_block != INT_BLOCK_HC) {
7169 cnt = 0;
7170
7171 do {
7172 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
7173 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
7174 (++cnt < MAX_IGU_ATTN_ACK_TO));
7175
7176 if (!igu_acked) {
7177 BLOGE(sc, "Failed to verify IGU ack on time\n");
7178 }
7179
7180 mb();
7181 }
7182
7183 REG_WR(sc, nig_int_mask_addr, nig_mask);
7184
7185 bxe_release_phy_lock(sc);
7186 }
7187 }
7188
7189 static void
bxe_print_next_block(struct bxe_softc * sc,int idx,const char * blk)7190 bxe_print_next_block(struct bxe_softc *sc,
7191 int idx,
7192 const char *blk)
7193 {
7194 BLOGI(sc, "%s%s", idx ? ", " : "", blk);
7195 }
7196
7197 static int
bxe_check_blocks_with_parity0(struct bxe_softc * sc,uint32_t sig,int par_num,uint8_t print)7198 bxe_check_blocks_with_parity0(struct bxe_softc *sc,
7199 uint32_t sig,
7200 int par_num,
7201 uint8_t print)
7202 {
7203 uint32_t cur_bit = 0;
7204 int i = 0;
7205
7206 for (i = 0; sig; i++) {
7207 cur_bit = ((uint32_t)0x1 << i);
7208 if (sig & cur_bit) {
7209 switch (cur_bit) {
7210 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
7211 if (print)
7212 bxe_print_next_block(sc, par_num++, "BRB");
7213 break;
7214 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
7215 if (print)
7216 bxe_print_next_block(sc, par_num++, "PARSER");
7217 break;
7218 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
7219 if (print)
7220 bxe_print_next_block(sc, par_num++, "TSDM");
7221 break;
7222 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
7223 if (print)
7224 bxe_print_next_block(sc, par_num++, "SEARCHER");
7225 break;
7226 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
7227 if (print)
7228 bxe_print_next_block(sc, par_num++, "TCM");
7229 break;
7230 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
7231 if (print)
7232 bxe_print_next_block(sc, par_num++, "TSEMI");
7233 break;
7234 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
7235 if (print)
7236 bxe_print_next_block(sc, par_num++, "XPB");
7237 break;
7238 }
7239
7240 /* Clear the bit */
7241 sig &= ~cur_bit;
7242 }
7243 }
7244
7245 return (par_num);
7246 }
7247
7248 static int
bxe_check_blocks_with_parity1(struct bxe_softc * sc,uint32_t sig,int par_num,uint8_t * global,uint8_t print)7249 bxe_check_blocks_with_parity1(struct bxe_softc *sc,
7250 uint32_t sig,
7251 int par_num,
7252 uint8_t *global,
7253 uint8_t print)
7254 {
7255 int i = 0;
7256 uint32_t cur_bit = 0;
7257 for (i = 0; sig; i++) {
7258 cur_bit = ((uint32_t)0x1 << i);
7259 if (sig & cur_bit) {
7260 switch (cur_bit) {
7261 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
7262 if (print)
7263 bxe_print_next_block(sc, par_num++, "PBF");
7264 break;
7265 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
7266 if (print)
7267 bxe_print_next_block(sc, par_num++, "QM");
7268 break;
7269 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
7270 if (print)
7271 bxe_print_next_block(sc, par_num++, "TM");
7272 break;
7273 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
7274 if (print)
7275 bxe_print_next_block(sc, par_num++, "XSDM");
7276 break;
7277 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
7278 if (print)
7279 bxe_print_next_block(sc, par_num++, "XCM");
7280 break;
7281 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
7282 if (print)
7283 bxe_print_next_block(sc, par_num++, "XSEMI");
7284 break;
7285 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
7286 if (print)
7287 bxe_print_next_block(sc, par_num++, "DOORBELLQ");
7288 break;
7289 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
7290 if (print)
7291 bxe_print_next_block(sc, par_num++, "NIG");
7292 break;
7293 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
7294 if (print)
7295 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE");
7296 *global = TRUE;
7297 break;
7298 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
7299 if (print)
7300 bxe_print_next_block(sc, par_num++, "DEBUG");
7301 break;
7302 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
7303 if (print)
7304 bxe_print_next_block(sc, par_num++, "USDM");
7305 break;
7306 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
7307 if (print)
7308 bxe_print_next_block(sc, par_num++, "UCM");
7309 break;
7310 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
7311 if (print)
7312 bxe_print_next_block(sc, par_num++, "USEMI");
7313 break;
7314 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
7315 if (print)
7316 bxe_print_next_block(sc, par_num++, "UPB");
7317 break;
7318 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
7319 if (print)
7320 bxe_print_next_block(sc, par_num++, "CSDM");
7321 break;
7322 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
7323 if (print)
7324 bxe_print_next_block(sc, par_num++, "CCM");
7325 break;
7326 }
7327
7328 /* Clear the bit */
7329 sig &= ~cur_bit;
7330 }
7331 }
7332
7333 return (par_num);
7334 }
7335
7336 static int
bxe_check_blocks_with_parity2(struct bxe_softc * sc,uint32_t sig,int par_num,uint8_t print)7337 bxe_check_blocks_with_parity2(struct bxe_softc *sc,
7338 uint32_t sig,
7339 int par_num,
7340 uint8_t print)
7341 {
7342 uint32_t cur_bit = 0;
7343 int i = 0;
7344
7345 for (i = 0; sig; i++) {
7346 cur_bit = ((uint32_t)0x1 << i);
7347 if (sig & cur_bit) {
7348 switch (cur_bit) {
7349 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
7350 if (print)
7351 bxe_print_next_block(sc, par_num++, "CSEMI");
7352 break;
7353 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
7354 if (print)
7355 bxe_print_next_block(sc, par_num++, "PXP");
7356 break;
7357 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
7358 if (print)
7359 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT");
7360 break;
7361 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
7362 if (print)
7363 bxe_print_next_block(sc, par_num++, "CFC");
7364 break;
7365 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
7366 if (print)
7367 bxe_print_next_block(sc, par_num++, "CDU");
7368 break;
7369 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
7370 if (print)
7371 bxe_print_next_block(sc, par_num++, "DMAE");
7372 break;
7373 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
7374 if (print)
7375 bxe_print_next_block(sc, par_num++, "IGU");
7376 break;
7377 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
7378 if (print)
7379 bxe_print_next_block(sc, par_num++, "MISC");
7380 break;
7381 }
7382
7383 /* Clear the bit */
7384 sig &= ~cur_bit;
7385 }
7386 }
7387
7388 return (par_num);
7389 }
7390
7391 static int
bxe_check_blocks_with_parity3(struct bxe_softc * sc,uint32_t sig,int par_num,uint8_t * global,uint8_t print)7392 bxe_check_blocks_with_parity3(struct bxe_softc *sc,
7393 uint32_t sig,
7394 int par_num,
7395 uint8_t *global,
7396 uint8_t print)
7397 {
7398 uint32_t cur_bit = 0;
7399 int i = 0;
7400
7401 for (i = 0; sig; i++) {
7402 cur_bit = ((uint32_t)0x1 << i);
7403 if (sig & cur_bit) {
7404 switch (cur_bit) {
7405 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
7406 if (print)
7407 bxe_print_next_block(sc, par_num++, "MCP ROM");
7408 *global = TRUE;
7409 break;
7410 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
7411 if (print)
7412 bxe_print_next_block(sc, par_num++,
7413 "MCP UMP RX");
7414 *global = TRUE;
7415 break;
7416 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
7417 if (print)
7418 bxe_print_next_block(sc, par_num++,
7419 "MCP UMP TX");
7420 *global = TRUE;
7421 break;
7422 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
7423 if (print)
7424 bxe_print_next_block(sc, par_num++,
7425 "MCP SCPAD");
7426 *global = TRUE;
7427 break;
7428 }
7429
7430 /* Clear the bit */
7431 sig &= ~cur_bit;
7432 }
7433 }
7434
7435 return (par_num);
7436 }
7437
7438 static int
bxe_check_blocks_with_parity4(struct bxe_softc * sc,uint32_t sig,int par_num,uint8_t print)7439 bxe_check_blocks_with_parity4(struct bxe_softc *sc,
7440 uint32_t sig,
7441 int par_num,
7442 uint8_t print)
7443 {
7444 uint32_t cur_bit = 0;
7445 int i = 0;
7446
7447 for (i = 0; sig; i++) {
7448 cur_bit = ((uint32_t)0x1 << i);
7449 if (sig & cur_bit) {
7450 switch (cur_bit) {
7451 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
7452 if (print)
7453 bxe_print_next_block(sc, par_num++, "PGLUE_B");
7454 break;
7455 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
7456 if (print)
7457 bxe_print_next_block(sc, par_num++, "ATC");
7458 break;
7459 }
7460
7461 /* Clear the bit */
7462 sig &= ~cur_bit;
7463 }
7464 }
7465
7466 return (par_num);
7467 }
7468
7469 static uint8_t
bxe_parity_attn(struct bxe_softc * sc,uint8_t * global,uint8_t print,uint32_t * sig)7470 bxe_parity_attn(struct bxe_softc *sc,
7471 uint8_t *global,
7472 uint8_t print,
7473 uint32_t *sig)
7474 {
7475 int par_num = 0;
7476
7477 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
7478 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
7479 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
7480 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
7481 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
7482 BLOGE(sc, "Parity error: HW block parity attention:\n"
7483 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
7484 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0),
7485 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1),
7486 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2),
7487 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3),
7488 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4));
7489
7490 if (print)
7491 BLOGI(sc, "Parity errors detected in blocks: ");
7492
7493 par_num =
7494 bxe_check_blocks_with_parity0(sc, sig[0] &
7495 HW_PRTY_ASSERT_SET_0,
7496 par_num, print);
7497 par_num =
7498 bxe_check_blocks_with_parity1(sc, sig[1] &
7499 HW_PRTY_ASSERT_SET_1,
7500 par_num, global, print);
7501 par_num =
7502 bxe_check_blocks_with_parity2(sc, sig[2] &
7503 HW_PRTY_ASSERT_SET_2,
7504 par_num, print);
7505 par_num =
7506 bxe_check_blocks_with_parity3(sc, sig[3] &
7507 HW_PRTY_ASSERT_SET_3,
7508 par_num, global, print);
7509 par_num =
7510 bxe_check_blocks_with_parity4(sc, sig[4] &
7511 HW_PRTY_ASSERT_SET_4,
7512 par_num, print);
7513
7514 if (print)
7515 BLOGI(sc, "\n");
7516
7517 if( *global == TRUE ) {
7518 BXE_SET_ERROR_BIT(sc, BXE_ERR_GLOBAL);
7519 }
7520
7521 return (TRUE);
7522 }
7523
7524 return (FALSE);
7525 }
7526
7527 static uint8_t
bxe_chk_parity_attn(struct bxe_softc * sc,uint8_t * global,uint8_t print)7528 bxe_chk_parity_attn(struct bxe_softc *sc,
7529 uint8_t *global,
7530 uint8_t print)
7531 {
7532 struct attn_route attn = { {0} };
7533 int port = SC_PORT(sc);
7534
7535 if(sc->state != BXE_STATE_OPEN)
7536 return FALSE;
7537
7538 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
7539 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
7540 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
7541 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
7542
7543 /*
7544 * Since MCP attentions can't be disabled inside the block, we need to
7545 * read AEU registers to see whether they're currently disabled
7546 */
7547 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
7548 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0)) &
7549 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
7550 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
7551
7552
7553 if (!CHIP_IS_E1x(sc))
7554 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
7555
7556 return (bxe_parity_attn(sc, global, print, attn.sig));
7557 }
7558
7559 static void
bxe_attn_int_deasserted4(struct bxe_softc * sc,uint32_t attn)7560 bxe_attn_int_deasserted4(struct bxe_softc *sc,
7561 uint32_t attn)
7562 {
7563 uint32_t val;
7564 bool err_flg = false;
7565
7566 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
7567 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
7568 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val);
7569 err_flg = true;
7570 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
7571 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
7572 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
7573 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
7574 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
7575 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
7576 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
7577 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
7578 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
7579 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
7580 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
7581 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
7582 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
7583 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
7584 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
7585 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
7586 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
7587 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
7588 }
7589
7590 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
7591 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
7592 BLOGE(sc, "ATC hw attention 0x%08x\n", val);
7593 err_flg = true;
7594 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
7595 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
7596 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
7597 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
7598 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
7599 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
7600 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
7601 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
7602 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
7603 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
7604 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
7605 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
7606 }
7607
7608 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7609 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
7610 BLOGE(sc, "FATAL parity attention set4 0x%08x\n",
7611 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7612 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
7613 err_flg = true;
7614 }
7615 if (err_flg) {
7616 BXE_SET_ERROR_BIT(sc, BXE_ERR_MISC);
7617 taskqueue_enqueue_timeout(taskqueue_thread,
7618 &sc->sp_err_timeout_task, hz/10);
7619 }
7620
7621 }
7622
7623 static void
bxe_e1h_disable(struct bxe_softc * sc)7624 bxe_e1h_disable(struct bxe_softc *sc)
7625 {
7626 int port = SC_PORT(sc);
7627
7628 bxe_tx_disable(sc);
7629
7630 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7631 }
7632
7633 static void
bxe_e1h_enable(struct bxe_softc * sc)7634 bxe_e1h_enable(struct bxe_softc *sc)
7635 {
7636 int port = SC_PORT(sc);
7637
7638 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7639
7640 // XXX bxe_tx_enable(sc);
7641 }
7642
7643 /*
7644 * called due to MCP event (on pmf):
7645 * reread new bandwidth configuration
7646 * configure FW
7647 * notify others function about the change
7648 */
7649 static void
bxe_config_mf_bw(struct bxe_softc * sc)7650 bxe_config_mf_bw(struct bxe_softc *sc)
7651 {
7652 if (sc->link_vars.link_up) {
7653 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
7654 // XXX bxe_link_sync_notify(sc);
7655 }
7656
7657 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7658 }
7659
7660 static void
bxe_set_mf_bw(struct bxe_softc * sc)7661 bxe_set_mf_bw(struct bxe_softc *sc)
7662 {
7663 bxe_config_mf_bw(sc);
7664 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
7665 }
7666
7667 static void
bxe_handle_eee_event(struct bxe_softc * sc)7668 bxe_handle_eee_event(struct bxe_softc *sc)
7669 {
7670 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n");
7671 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
7672 }
7673
7674 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
7675
7676 static void
bxe_drv_info_ether_stat(struct bxe_softc * sc)7677 bxe_drv_info_ether_stat(struct bxe_softc *sc)
7678 {
7679 struct eth_stats_info *ether_stat =
7680 &sc->sp->drv_info_to_mcp.ether_stat;
7681
7682 strlcpy(ether_stat->version, BXE_DRIVER_VERSION,
7683 ETH_STAT_INFO_VERSION_LEN);
7684
7685 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */
7686 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
7687 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
7688 ether_stat->mac_local + MAC_PAD,
7689 MAC_PAD, ETH_ALEN);
7690
7691 ether_stat->mtu_size = sc->mtu;
7692
7693 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
7694 if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) {
7695 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
7696 }
7697
7698 // XXX ether_stat->feature_flags |= ???;
7699
7700 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
7701
7702 ether_stat->txq_size = sc->tx_ring_size;
7703 ether_stat->rxq_size = sc->rx_ring_size;
7704 }
7705
7706 static void
bxe_handle_drv_info_req(struct bxe_softc * sc)7707 bxe_handle_drv_info_req(struct bxe_softc *sc)
7708 {
7709 enum drv_info_opcode op_code;
7710 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
7711
7712 /* if drv_info version supported by MFW doesn't match - send NACK */
7713 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
7714 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7715 return;
7716 }
7717
7718 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
7719 DRV_INFO_CONTROL_OP_CODE_SHIFT);
7720
7721 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
7722
7723 switch (op_code) {
7724 case ETH_STATS_OPCODE:
7725 bxe_drv_info_ether_stat(sc);
7726 break;
7727 case FCOE_STATS_OPCODE:
7728 case ISCSI_STATS_OPCODE:
7729 default:
7730 /* if op code isn't supported - send NACK */
7731 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7732 return;
7733 }
7734
7735 /*
7736 * If we got drv_info attn from MFW then these fields are defined in
7737 * shmem2 for sure
7738 */
7739 SHMEM2_WR(sc, drv_info_host_addr_lo,
7740 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7741 SHMEM2_WR(sc, drv_info_host_addr_hi,
7742 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7743
7744 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
7745 }
7746
7747 static void
bxe_dcc_event(struct bxe_softc * sc,uint32_t dcc_event)7748 bxe_dcc_event(struct bxe_softc *sc,
7749 uint32_t dcc_event)
7750 {
7751 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event);
7752
7753 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
7754 /*
7755 * This is the only place besides the function initialization
7756 * where the sc->flags can change so it is done without any
7757 * locks
7758 */
7759 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
7760 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n");
7761 sc->flags |= BXE_MF_FUNC_DIS;
7762 bxe_e1h_disable(sc);
7763 } else {
7764 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n");
7765 sc->flags &= ~BXE_MF_FUNC_DIS;
7766 bxe_e1h_enable(sc);
7767 }
7768 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
7769 }
7770
7771 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
7772 bxe_config_mf_bw(sc);
7773 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
7774 }
7775
7776 /* Report results to MCP */
7777 if (dcc_event)
7778 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
7779 else
7780 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
7781 }
7782
7783 static void
bxe_pmf_update(struct bxe_softc * sc)7784 bxe_pmf_update(struct bxe_softc *sc)
7785 {
7786 int port = SC_PORT(sc);
7787 uint32_t val;
7788
7789 sc->port.pmf = 1;
7790 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf);
7791
7792 /*
7793 * We need the mb() to ensure the ordering between the writing to
7794 * sc->port.pmf here and reading it from the bxe_periodic_task().
7795 */
7796 mb();
7797
7798 /* queue a periodic task */
7799 // XXX schedule task...
7800
7801 // XXX bxe_dcbx_pmf_update(sc);
7802
7803 /* enable nig attention */
7804 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
7805 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7806 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val);
7807 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val);
7808 } else if (!CHIP_IS_E1x(sc)) {
7809 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
7810 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
7811 }
7812
7813 bxe_stats_handle(sc, STATS_EVENT_PMF);
7814 }
7815
7816 static int
bxe_mc_assert(struct bxe_softc * sc)7817 bxe_mc_assert(struct bxe_softc *sc)
7818 {
7819 char last_idx;
7820 int i, rc = 0;
7821 uint32_t row0, row1, row2, row3;
7822
7823 /* XSTORM */
7824 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
7825 if (last_idx)
7826 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7827
7828 /* print the asserts */
7829 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7830
7831 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
7832 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);
7833 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);
7834 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);
7835
7836 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7837 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7838 i, row3, row2, row1, row0);
7839 rc++;
7840 } else {
7841 break;
7842 }
7843 }
7844
7845 /* TSTORM */
7846 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
7847 if (last_idx) {
7848 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7849 }
7850
7851 /* print the asserts */
7852 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7853
7854 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
7855 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);
7856 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);
7857 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);
7858
7859 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7860 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7861 i, row3, row2, row1, row0);
7862 rc++;
7863 } else {
7864 break;
7865 }
7866 }
7867
7868 /* CSTORM */
7869 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
7870 if (last_idx) {
7871 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7872 }
7873
7874 /* print the asserts */
7875 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7876
7877 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
7878 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);
7879 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);
7880 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);
7881
7882 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7883 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7884 i, row3, row2, row1, row0);
7885 rc++;
7886 } else {
7887 break;
7888 }
7889 }
7890
7891 /* USTORM */
7892 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
7893 if (last_idx) {
7894 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7895 }
7896
7897 /* print the asserts */
7898 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7899
7900 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
7901 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);
7902 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);
7903 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);
7904
7905 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7906 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7907 i, row3, row2, row1, row0);
7908 rc++;
7909 } else {
7910 break;
7911 }
7912 }
7913
7914 return (rc);
7915 }
7916
7917 static void
bxe_attn_int_deasserted3(struct bxe_softc * sc,uint32_t attn)7918 bxe_attn_int_deasserted3(struct bxe_softc *sc,
7919 uint32_t attn)
7920 {
7921 int func = SC_FUNC(sc);
7922 uint32_t val;
7923
7924 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
7925
7926 if (attn & BXE_PMF_LINK_ASSERT(sc)) {
7927
7928 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7929 bxe_read_mf_cfg(sc);
7930 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
7931 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7932 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
7933
7934 if (val & DRV_STATUS_DCC_EVENT_MASK)
7935 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK));
7936
7937 if (val & DRV_STATUS_SET_MF_BW)
7938 bxe_set_mf_bw(sc);
7939
7940 if (val & DRV_STATUS_DRV_INFO_REQ)
7941 bxe_handle_drv_info_req(sc);
7942
7943 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
7944 bxe_pmf_update(sc);
7945
7946 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
7947 bxe_handle_eee_event(sc);
7948
7949 if (sc->link_vars.periodic_flags &
7950 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
7951 /* sync with link */
7952 bxe_acquire_phy_lock(sc);
7953 sc->link_vars.periodic_flags &=
7954 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
7955 bxe_release_phy_lock(sc);
7956 if (IS_MF(sc))
7957 ; // XXX bxe_link_sync_notify(sc);
7958 bxe_link_report(sc);
7959 }
7960
7961 /*
7962 * Always call it here: bxe_link_report() will
7963 * prevent the link indication duplication.
7964 */
7965 bxe_link_status_update(sc);
7966
7967 } else if (attn & BXE_MC_ASSERT_BITS) {
7968
7969 BLOGE(sc, "MC assert!\n");
7970 bxe_mc_assert(sc);
7971 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
7972 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
7973 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
7974 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
7975 bxe_int_disable(sc);
7976 BXE_SET_ERROR_BIT(sc, BXE_ERR_MC_ASSERT);
7977 taskqueue_enqueue_timeout(taskqueue_thread,
7978 &sc->sp_err_timeout_task, hz/10);
7979
7980 } else if (attn & BXE_MCP_ASSERT) {
7981
7982 BLOGE(sc, "MCP assert!\n");
7983 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
7984 BXE_SET_ERROR_BIT(sc, BXE_ERR_MCP_ASSERT);
7985 taskqueue_enqueue_timeout(taskqueue_thread,
7986 &sc->sp_err_timeout_task, hz/10);
7987 bxe_int_disable(sc); /*avoid repetive assert alert */
7988
7989
7990 } else {
7991 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn);
7992 }
7993 }
7994
7995 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
7996 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn);
7997 if (attn & BXE_GRC_TIMEOUT) {
7998 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
7999 BLOGE(sc, "GRC time-out 0x%08x\n", val);
8000 }
8001 if (attn & BXE_GRC_RSV) {
8002 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
8003 BLOGE(sc, "GRC reserved 0x%08x\n", val);
8004 }
8005 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
8006 }
8007 }
8008
8009 static void
bxe_attn_int_deasserted2(struct bxe_softc * sc,uint32_t attn)8010 bxe_attn_int_deasserted2(struct bxe_softc *sc,
8011 uint32_t attn)
8012 {
8013 int port = SC_PORT(sc);
8014 int reg_offset;
8015 uint32_t val0, mask0, val1, mask1;
8016 uint32_t val;
8017 bool err_flg = false;
8018
8019 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
8020 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
8021 BLOGE(sc, "CFC hw attention 0x%08x\n", val);
8022 /* CFC error attention */
8023 if (val & 0x2) {
8024 BLOGE(sc, "FATAL error from CFC\n");
8025 err_flg = true;
8026 }
8027 }
8028
8029 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
8030 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
8031 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val);
8032 /* RQ_USDMDP_FIFO_OVERFLOW */
8033 if (val & 0x18000) {
8034 BLOGE(sc, "FATAL error from PXP\n");
8035 err_flg = true;
8036 }
8037
8038 if (!CHIP_IS_E1x(sc)) {
8039 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
8040 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val);
8041 err_flg = true;
8042 }
8043 }
8044
8045 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
8046 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
8047
8048 if (attn & AEU_PXP2_HW_INT_BIT) {
8049 /* CQ47854 workaround do not panic on
8050 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8051 */
8052 if (!CHIP_IS_E1x(sc)) {
8053 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
8054 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
8055 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
8056 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
8057 /*
8058 * If the only PXP2_EOP_ERROR_BIT is set in
8059 * STS0 and STS1 - clear it
8060 *
8061 * probably we lose additional attentions between
8062 * STS0 and STS_CLR0, in this case user will not
8063 * be notified about them
8064 */
8065 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
8066 !(val1 & mask1))
8067 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
8068
8069 /* print the register, since no one can restore it */
8070 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0);
8071
8072 /*
8073 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8074 * then notify
8075 */
8076 if (val0 & PXP2_EOP_ERROR_BIT) {
8077 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n");
8078 err_flg = true;
8079
8080 /*
8081 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
8082 * set then clear attention from PXP2 block without panic
8083 */
8084 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
8085 ((val1 & mask1) == 0))
8086 attn &= ~AEU_PXP2_HW_INT_BIT;
8087 }
8088 }
8089 }
8090
8091 if (attn & HW_INTERRUT_ASSERT_SET_2) {
8092 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
8093 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
8094
8095 val = REG_RD(sc, reg_offset);
8096 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
8097 REG_WR(sc, reg_offset, val);
8098
8099 BLOGE(sc, "FATAL HW block attention set2 0x%x\n",
8100 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2));
8101 err_flg = true;
8102 bxe_panic(sc, ("HW block attention set2\n"));
8103 }
8104 if(err_flg) {
8105 BXE_SET_ERROR_BIT(sc, BXE_ERR_GLOBAL);
8106 taskqueue_enqueue_timeout(taskqueue_thread,
8107 &sc->sp_err_timeout_task, hz/10);
8108 }
8109
8110 }
8111
8112 static void
bxe_attn_int_deasserted1(struct bxe_softc * sc,uint32_t attn)8113 bxe_attn_int_deasserted1(struct bxe_softc *sc,
8114 uint32_t attn)
8115 {
8116 int port = SC_PORT(sc);
8117 int reg_offset;
8118 uint32_t val;
8119 bool err_flg = false;
8120
8121 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
8122 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
8123 BLOGE(sc, "DB hw attention 0x%08x\n", val);
8124 /* DORQ discard attention */
8125 if (val & 0x2) {
8126 BLOGE(sc, "FATAL error from DORQ\n");
8127 err_flg = true;
8128 }
8129 }
8130
8131 if (attn & HW_INTERRUT_ASSERT_SET_1) {
8132 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
8133 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
8134
8135 val = REG_RD(sc, reg_offset);
8136 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
8137 REG_WR(sc, reg_offset, val);
8138
8139 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n",
8140 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1));
8141 err_flg = true;
8142 bxe_panic(sc, ("HW block attention set1\n"));
8143 }
8144 if(err_flg) {
8145 BXE_SET_ERROR_BIT(sc, BXE_ERR_MISC);
8146 taskqueue_enqueue_timeout(taskqueue_thread,
8147 &sc->sp_err_timeout_task, hz/10);
8148 }
8149
8150 }
8151
8152 static void
bxe_attn_int_deasserted0(struct bxe_softc * sc,uint32_t attn)8153 bxe_attn_int_deasserted0(struct bxe_softc *sc,
8154 uint32_t attn)
8155 {
8156 int port = SC_PORT(sc);
8157 int reg_offset;
8158 uint32_t val;
8159
8160 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
8161 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8162
8163 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
8164 val = REG_RD(sc, reg_offset);
8165 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
8166 REG_WR(sc, reg_offset, val);
8167
8168 BLOGW(sc, "SPIO5 hw attention\n");
8169
8170 /* Fan failure attention */
8171 elink_hw_reset_phy(&sc->link_params);
8172 bxe_fan_failure(sc);
8173 }
8174
8175 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
8176 bxe_acquire_phy_lock(sc);
8177 elink_handle_module_detect_int(&sc->link_params);
8178 bxe_release_phy_lock(sc);
8179 }
8180
8181 if (attn & HW_INTERRUT_ASSERT_SET_0) {
8182 val = REG_RD(sc, reg_offset);
8183 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
8184 REG_WR(sc, reg_offset, val);
8185
8186
8187 BXE_SET_ERROR_BIT(sc, BXE_ERR_MISC);
8188 taskqueue_enqueue_timeout(taskqueue_thread,
8189 &sc->sp_err_timeout_task, hz/10);
8190
8191 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n",
8192 (attn & HW_INTERRUT_ASSERT_SET_0)));
8193 }
8194 }
8195
8196 static void
bxe_attn_int_deasserted(struct bxe_softc * sc,uint32_t deasserted)8197 bxe_attn_int_deasserted(struct bxe_softc *sc,
8198 uint32_t deasserted)
8199 {
8200 struct attn_route attn;
8201 struct attn_route *group_mask;
8202 int port = SC_PORT(sc);
8203 int index;
8204 uint32_t reg_addr;
8205 uint32_t val;
8206 uint32_t aeu_mask;
8207 uint8_t global = FALSE;
8208
8209 /*
8210 * Need to take HW lock because MCP or other port might also
8211 * try to handle this event.
8212 */
8213 bxe_acquire_alr(sc);
8214
8215 if (bxe_chk_parity_attn(sc, &global, TRUE)) {
8216 /* XXX
8217 * In case of parity errors don't handle attentions so that
8218 * other function would "see" parity errors.
8219 */
8220 // XXX schedule a recovery task...
8221 /* disable HW interrupts */
8222 bxe_int_disable(sc);
8223 BXE_SET_ERROR_BIT(sc, BXE_ERR_PARITY);
8224 taskqueue_enqueue_timeout(taskqueue_thread,
8225 &sc->sp_err_timeout_task, hz/10);
8226 bxe_release_alr(sc);
8227 return;
8228 }
8229
8230 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
8231 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
8232 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
8233 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
8234 if (!CHIP_IS_E1x(sc)) {
8235 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
8236 } else {
8237 attn.sig[4] = 0;
8238 }
8239
8240 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8241 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
8242
8243 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
8244 if (deasserted & (1 << index)) {
8245 group_mask = &sc->attn_group[index];
8246
8247 BLOGD(sc, DBG_INTR,
8248 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index,
8249 group_mask->sig[0], group_mask->sig[1],
8250 group_mask->sig[2], group_mask->sig[3],
8251 group_mask->sig[4]);
8252
8253 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]);
8254 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]);
8255 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]);
8256 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]);
8257 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]);
8258 }
8259 }
8260
8261 bxe_release_alr(sc);
8262
8263 if (sc->devinfo.int_block == INT_BLOCK_HC) {
8264 reg_addr = (HC_REG_COMMAND_REG + port*32 +
8265 COMMAND_REG_ATTN_BITS_CLR);
8266 } else {
8267 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
8268 }
8269
8270 val = ~deasserted;
8271 BLOGD(sc, DBG_INTR,
8272 "about to mask 0x%08x at %s addr 0x%08x\n", val,
8273 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
8274 REG_WR(sc, reg_addr, val);
8275
8276 if (~sc->attn_state & deasserted) {
8277 BLOGE(sc, "IGU error\n");
8278 }
8279
8280 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8281 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8282
8283 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8284
8285 aeu_mask = REG_RD(sc, reg_addr);
8286
8287 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n",
8288 aeu_mask, deasserted);
8289 aeu_mask |= (deasserted & 0x3ff);
8290 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
8291
8292 REG_WR(sc, reg_addr, aeu_mask);
8293 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8294
8295 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
8296 sc->attn_state &= ~deasserted;
8297 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
8298 }
8299
8300 static void
bxe_attn_int(struct bxe_softc * sc)8301 bxe_attn_int(struct bxe_softc *sc)
8302 {
8303 /* read local copy of bits */
8304 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
8305 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
8306 uint32_t attn_state = sc->attn_state;
8307
8308 /* look for changed bits */
8309 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
8310 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
8311
8312 BLOGD(sc, DBG_INTR,
8313 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n",
8314 attn_bits, attn_ack, asserted, deasserted);
8315
8316 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
8317 BLOGE(sc, "BAD attention state\n");
8318 }
8319
8320 /* handle bits that were raised */
8321 if (asserted) {
8322 bxe_attn_int_asserted(sc, asserted);
8323 }
8324
8325 if (deasserted) {
8326 bxe_attn_int_deasserted(sc, deasserted);
8327 }
8328 }
8329
8330 static uint16_t
bxe_update_dsb_idx(struct bxe_softc * sc)8331 bxe_update_dsb_idx(struct bxe_softc *sc)
8332 {
8333 struct host_sp_status_block *def_sb = sc->def_sb;
8334 uint16_t rc = 0;
8335
8336 mb(); /* status block is written to by the chip */
8337
8338 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
8339 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
8340 rc |= BXE_DEF_SB_ATT_IDX;
8341 }
8342
8343 if (sc->def_idx != def_sb->sp_sb.running_index) {
8344 sc->def_idx = def_sb->sp_sb.running_index;
8345 rc |= BXE_DEF_SB_IDX;
8346 }
8347
8348 mb();
8349
8350 return (rc);
8351 }
8352
8353 static inline struct ecore_queue_sp_obj *
bxe_cid_to_q_obj(struct bxe_softc * sc,uint32_t cid)8354 bxe_cid_to_q_obj(struct bxe_softc *sc,
8355 uint32_t cid)
8356 {
8357 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid);
8358 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj);
8359 }
8360
8361 static void
bxe_handle_mcast_eqe(struct bxe_softc * sc)8362 bxe_handle_mcast_eqe(struct bxe_softc *sc)
8363 {
8364 struct ecore_mcast_ramrod_params rparam;
8365 int rc;
8366
8367 memset(&rparam, 0, sizeof(rparam));
8368
8369 rparam.mcast_obj = &sc->mcast_obj;
8370
8371 BXE_MCAST_LOCK(sc);
8372
8373 /* clear pending state for the last command */
8374 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
8375
8376 /* if there are pending mcast commands - send them */
8377 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
8378 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
8379 if (rc < 0) {
8380 BLOGD(sc, DBG_SP,
8381 "ERROR: Failed to send pending mcast commands (%d)\n", rc);
8382 }
8383 }
8384
8385 BXE_MCAST_UNLOCK(sc);
8386 }
8387
8388 static void
bxe_handle_classification_eqe(struct bxe_softc * sc,union event_ring_elem * elem)8389 bxe_handle_classification_eqe(struct bxe_softc *sc,
8390 union event_ring_elem *elem)
8391 {
8392 unsigned long ramrod_flags = 0;
8393 int rc = 0;
8394 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8395 struct ecore_vlan_mac_obj *vlan_mac_obj;
8396
8397 /* always push next commands out, don't wait here */
8398 bit_set(&ramrod_flags, RAMROD_CONT);
8399
8400 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) {
8401 case ECORE_FILTER_MAC_PENDING:
8402 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n");
8403 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
8404 break;
8405
8406 case ECORE_FILTER_MCAST_PENDING:
8407 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n");
8408 /*
8409 * This is only relevant for 57710 where multicast MACs are
8410 * configured as unicast MACs using the same ramrod.
8411 */
8412 bxe_handle_mcast_eqe(sc);
8413 return;
8414
8415 default:
8416 BLOGE(sc, "Unsupported classification command: %d\n",
8417 elem->message.data.eth_event.echo);
8418 return;
8419 }
8420
8421 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
8422
8423 if (rc < 0) {
8424 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc);
8425 } else if (rc > 0) {
8426 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n");
8427 }
8428 }
8429
8430 static void
bxe_handle_rx_mode_eqe(struct bxe_softc * sc,union event_ring_elem * elem)8431 bxe_handle_rx_mode_eqe(struct bxe_softc *sc,
8432 union event_ring_elem *elem)
8433 {
8434 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
8435
8436 /* send rx_mode command again if was requested */
8437 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED,
8438 &sc->sp_state)) {
8439 bxe_set_storm_rx_mode(sc);
8440 }
8441 }
8442
8443 static void
bxe_update_eq_prod(struct bxe_softc * sc,uint16_t prod)8444 bxe_update_eq_prod(struct bxe_softc *sc,
8445 uint16_t prod)
8446 {
8447 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
8448 wmb(); /* keep prod updates ordered */
8449 }
8450
8451 static void
bxe_eq_int(struct bxe_softc * sc)8452 bxe_eq_int(struct bxe_softc *sc)
8453 {
8454 uint16_t hw_cons, sw_cons, sw_prod;
8455 union event_ring_elem *elem;
8456 uint8_t echo;
8457 uint32_t cid;
8458 uint8_t opcode;
8459 int spqe_cnt = 0;
8460 struct ecore_queue_sp_obj *q_obj;
8461 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
8462 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
8463
8464 hw_cons = le16toh(*sc->eq_cons_sb);
8465
8466 /*
8467 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
8468 * when we get to the next-page we need to adjust so the loop
8469 * condition below will be met. The next element is the size of a
8470 * regular element and hence incrementing by 1
8471 */
8472 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
8473 hw_cons++;
8474 }
8475
8476 /*
8477 * This function may never run in parallel with itself for a
8478 * specific sc and no need for a read memory barrier here.
8479 */
8480 sw_cons = sc->eq_cons;
8481 sw_prod = sc->eq_prod;
8482
8483 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n",
8484 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left));
8485
8486 for (;
8487 sw_cons != hw_cons;
8488 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
8489
8490 elem = &sc->eq[EQ_DESC(sw_cons)];
8491
8492 /* elem CID originates from FW, actually LE */
8493 cid = SW_CID(elem->message.data.cfc_del_event.cid);
8494 opcode = elem->message.opcode;
8495
8496 /* handle eq element */
8497 switch (opcode) {
8498
8499 case EVENT_RING_OPCODE_STAT_QUERY:
8500 BLOGD(sc, DBG_SP, "got statistics completion event %d\n",
8501 sc->stats_comp++);
8502 /* nothing to do with stats comp */
8503 goto next_spqe;
8504
8505 case EVENT_RING_OPCODE_CFC_DEL:
8506 /* handle according to cid range */
8507 /* we may want to verify here that the sc state is HALTING */
8508 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid);
8509 q_obj = bxe_cid_to_q_obj(sc, cid);
8510 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
8511 break;
8512 }
8513 goto next_spqe;
8514
8515 case EVENT_RING_OPCODE_STOP_TRAFFIC:
8516 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n");
8517 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
8518 break;
8519 }
8520 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED);
8521 goto next_spqe;
8522
8523 case EVENT_RING_OPCODE_START_TRAFFIC:
8524 BLOGD(sc, DBG_SP, "got START TRAFFIC\n");
8525 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) {
8526 break;
8527 }
8528 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED);
8529 goto next_spqe;
8530
8531 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
8532 echo = elem->message.data.function_update_event.echo;
8533 if (echo == SWITCH_UPDATE) {
8534 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n");
8535 if (f_obj->complete_cmd(sc, f_obj,
8536 ECORE_F_CMD_SWITCH_UPDATE)) {
8537 break;
8538 }
8539 }
8540 else {
8541 BLOGD(sc, DBG_SP,
8542 "AFEX: ramrod completed FUNCTION_UPDATE\n");
8543 }
8544 goto next_spqe;
8545
8546 case EVENT_RING_OPCODE_FORWARD_SETUP:
8547 q_obj = &bxe_fwd_sp_obj(sc, q_obj);
8548 if (q_obj->complete_cmd(sc, q_obj,
8549 ECORE_Q_CMD_SETUP_TX_ONLY)) {
8550 break;
8551 }
8552 goto next_spqe;
8553
8554 case EVENT_RING_OPCODE_FUNCTION_START:
8555 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n");
8556 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
8557 break;
8558 }
8559 goto next_spqe;
8560
8561 case EVENT_RING_OPCODE_FUNCTION_STOP:
8562 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n");
8563 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
8564 break;
8565 }
8566 goto next_spqe;
8567 }
8568
8569 switch (opcode | sc->state) {
8570 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN):
8571 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT):
8572 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8573 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid);
8574 rss_raw->clear_pending(rss_raw);
8575 break;
8576
8577 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN):
8578 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG):
8579 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT):
8580 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN):
8581 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG):
8582 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8583 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n");
8584 bxe_handle_classification_eqe(sc, elem);
8585 break;
8586
8587 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN):
8588 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG):
8589 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8590 BLOGD(sc, DBG_SP, "got mcast ramrod\n");
8591 bxe_handle_mcast_eqe(sc);
8592 break;
8593
8594 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN):
8595 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG):
8596 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8597 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n");
8598 bxe_handle_rx_mode_eqe(sc, elem);
8599 break;
8600
8601 default:
8602 /* unknown event log error and continue */
8603 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n",
8604 elem->message.opcode, sc->state);
8605 }
8606
8607 next_spqe:
8608 spqe_cnt++;
8609 } /* for */
8610
8611 mb();
8612 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
8613
8614 sc->eq_cons = sw_cons;
8615 sc->eq_prod = sw_prod;
8616
8617 /* make sure that above mem writes were issued towards the memory */
8618 wmb();
8619
8620 /* update producer */
8621 bxe_update_eq_prod(sc, sc->eq_prod);
8622 }
8623
8624 static void
bxe_handle_sp_tq(void * context,int pending)8625 bxe_handle_sp_tq(void *context,
8626 int pending)
8627 {
8628 struct bxe_softc *sc = (struct bxe_softc *)context;
8629 uint16_t status;
8630
8631 BLOGD(sc, DBG_SP, "---> SP TASK <---\n");
8632
8633 /* what work needs to be performed? */
8634 status = bxe_update_dsb_idx(sc);
8635
8636 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status);
8637
8638 /* HW attentions */
8639 if (status & BXE_DEF_SB_ATT_IDX) {
8640 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n");
8641 bxe_attn_int(sc);
8642 status &= ~BXE_DEF_SB_ATT_IDX;
8643 }
8644
8645 /* SP events: STAT_QUERY and others */
8646 if (status & BXE_DEF_SB_IDX) {
8647 /* handle EQ completions */
8648 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n");
8649 bxe_eq_int(sc);
8650 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
8651 le16toh(sc->def_idx), IGU_INT_NOP, 1);
8652 status &= ~BXE_DEF_SB_IDX;
8653 }
8654
8655 /* if status is non zero then something went wrong */
8656 if (__predict_false(status)) {
8657 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status);
8658 }
8659
8660 /* ack status block only if something was actually handled */
8661 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
8662 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
8663
8664 /*
8665 * Must be called after the EQ processing (since eq leads to sriov
8666 * ramrod completion flows).
8667 * This flow may have been scheduled by the arrival of a ramrod
8668 * completion, or by the sriov code rescheduling itself.
8669 */
8670 // XXX bxe_iov_sp_task(sc);
8671
8672 }
8673
8674 static void
bxe_handle_fp_tq(void * context,int pending)8675 bxe_handle_fp_tq(void *context,
8676 int pending)
8677 {
8678 struct bxe_fastpath *fp = (struct bxe_fastpath *)context;
8679 struct bxe_softc *sc = fp->sc;
8680 /* uint8_t more_tx = FALSE; */
8681 uint8_t more_rx = FALSE;
8682
8683 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index);
8684
8685 /* XXX
8686 * IFF_DRV_RUNNING state can't be checked here since we process
8687 * slowpath events on a client queue during setup. Instead
8688 * we need to add a "process/continue" flag here that the driver
8689 * can use to tell the task here not to do anything.
8690 */
8691 #if 0
8692 if (!(if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) {
8693 return;
8694 }
8695 #endif
8696
8697 /* update the fastpath index */
8698 bxe_update_fp_sb_idx(fp);
8699
8700 /* XXX add loop here if ever support multiple tx CoS */
8701 /* fp->txdata[cos] */
8702 if (bxe_has_tx_work(fp)) {
8703 BXE_FP_TX_LOCK(fp);
8704 /* more_tx = */ bxe_txeof(sc, fp);
8705 BXE_FP_TX_UNLOCK(fp);
8706 }
8707
8708 if (bxe_has_rx_work(fp)) {
8709 more_rx = bxe_rxeof(sc, fp);
8710 }
8711
8712 if (more_rx /*|| more_tx*/) {
8713 /* still more work to do */
8714 taskqueue_enqueue(fp->tq, &fp->tq_task);
8715 return;
8716 }
8717
8718 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8719 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8720 }
8721
8722 static void
bxe_task_fp(struct bxe_fastpath * fp)8723 bxe_task_fp(struct bxe_fastpath *fp)
8724 {
8725 struct bxe_softc *sc = fp->sc;
8726 /* uint8_t more_tx = FALSE; */
8727 uint8_t more_rx = FALSE;
8728
8729 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index);
8730
8731 /* update the fastpath index */
8732 bxe_update_fp_sb_idx(fp);
8733
8734 /* XXX add loop here if ever support multiple tx CoS */
8735 /* fp->txdata[cos] */
8736 if (bxe_has_tx_work(fp)) {
8737 BXE_FP_TX_LOCK(fp);
8738 /* more_tx = */ bxe_txeof(sc, fp);
8739 BXE_FP_TX_UNLOCK(fp);
8740 }
8741
8742 if (bxe_has_rx_work(fp)) {
8743 more_rx = bxe_rxeof(sc, fp);
8744 }
8745
8746 if (more_rx /*|| more_tx*/) {
8747 /* still more work to do, bail out if this ISR and process later */
8748 taskqueue_enqueue(fp->tq, &fp->tq_task);
8749 return;
8750 }
8751
8752 /*
8753 * Here we write the fastpath index taken before doing any tx or rx work.
8754 * It is very well possible other hw events occurred up to this point and
8755 * they were actually processed accordingly above. Since we're going to
8756 * write an older fastpath index, an interrupt is coming which we might
8757 * not do any work in.
8758 */
8759 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8760 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8761 }
8762
8763 /*
8764 * Legacy interrupt entry point.
8765 *
8766 * Verifies that the controller generated the interrupt and
8767 * then calls a separate routine to handle the various
8768 * interrupt causes: link, RX, and TX.
8769 */
8770 static void
bxe_intr_legacy(void * xsc)8771 bxe_intr_legacy(void *xsc)
8772 {
8773 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8774 struct bxe_fastpath *fp;
8775 uint16_t status, mask;
8776 int i;
8777
8778 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n");
8779
8780 /*
8781 * 0 for ustorm, 1 for cstorm
8782 * the bits returned from ack_int() are 0-15
8783 * bit 0 = attention status block
8784 * bit 1 = fast path status block
8785 * a mask of 0x2 or more = tx/rx event
8786 * a mask of 1 = slow path event
8787 */
8788
8789 status = bxe_ack_int(sc);
8790
8791 /* the interrupt is not for us */
8792 if (__predict_false(status == 0)) {
8793 BLOGD(sc, DBG_INTR, "Not our interrupt!\n");
8794 return;
8795 }
8796
8797 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status);
8798
8799 FOR_EACH_ETH_QUEUE(sc, i) {
8800 fp = &sc->fp[i];
8801 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
8802 if (status & mask) {
8803 /* acknowledge and disable further fastpath interrupts */
8804 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8805 bxe_task_fp(fp);
8806 status &= ~mask;
8807 }
8808 }
8809
8810 if (__predict_false(status & 0x1)) {
8811 /* acknowledge and disable further slowpath interrupts */
8812 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8813
8814 /* schedule slowpath handler */
8815 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task);
8816
8817 status &= ~0x1;
8818 }
8819
8820 if (__predict_false(status)) {
8821 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status);
8822 }
8823 }
8824
8825 /* slowpath interrupt entry point */
8826 static void
bxe_intr_sp(void * xsc)8827 bxe_intr_sp(void *xsc)
8828 {
8829 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8830
8831 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n");
8832
8833 /* acknowledge and disable further slowpath interrupts */
8834 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8835
8836 /* schedule slowpath handler */
8837 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task);
8838 }
8839
8840 /* fastpath interrupt entry point */
8841 static void
bxe_intr_fp(void * xfp)8842 bxe_intr_fp(void *xfp)
8843 {
8844 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp;
8845 struct bxe_softc *sc = fp->sc;
8846
8847 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index);
8848
8849 BLOGD(sc, DBG_INTR,
8850 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n",
8851 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id);
8852
8853 /* acknowledge and disable further fastpath interrupts */
8854 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8855
8856 bxe_task_fp(fp);
8857 }
8858
8859 /* Release all interrupts allocated by the driver. */
8860 static void
bxe_interrupt_free(struct bxe_softc * sc)8861 bxe_interrupt_free(struct bxe_softc *sc)
8862 {
8863 int i;
8864
8865 switch (sc->interrupt_mode) {
8866 case INTR_MODE_INTX:
8867 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n");
8868 if (sc->intr[0].resource != NULL) {
8869 bus_release_resource(sc->dev,
8870 SYS_RES_IRQ,
8871 sc->intr[0].rid,
8872 sc->intr[0].resource);
8873 }
8874 break;
8875 case INTR_MODE_MSI:
8876 for (i = 0; i < sc->intr_count; i++) {
8877 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i);
8878 if (sc->intr[i].resource && sc->intr[i].rid) {
8879 bus_release_resource(sc->dev,
8880 SYS_RES_IRQ,
8881 sc->intr[i].rid,
8882 sc->intr[i].resource);
8883 }
8884 }
8885 pci_release_msi(sc->dev);
8886 break;
8887 case INTR_MODE_MSIX:
8888 for (i = 0; i < sc->intr_count; i++) {
8889 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i);
8890 if (sc->intr[i].resource && sc->intr[i].rid) {
8891 bus_release_resource(sc->dev,
8892 SYS_RES_IRQ,
8893 sc->intr[i].rid,
8894 sc->intr[i].resource);
8895 }
8896 }
8897 pci_release_msi(sc->dev);
8898 break;
8899 default:
8900 /* nothing to do as initial allocation failed */
8901 break;
8902 }
8903 }
8904
8905 /*
8906 * This function determines and allocates the appropriate
8907 * interrupt based on system capabilites and user request.
8908 *
8909 * The user may force a particular interrupt mode, specify
8910 * the number of receive queues, specify the method for
8911 * distribuitng received frames to receive queues, or use
8912 * the default settings which will automatically select the
8913 * best supported combination. In addition, the OS may or
8914 * may not support certain combinations of these settings.
8915 * This routine attempts to reconcile the settings requested
8916 * by the user with the capabilites available from the system
8917 * to select the optimal combination of features.
8918 *
8919 * Returns:
8920 * 0 = Success, !0 = Failure.
8921 */
8922 static int
bxe_interrupt_alloc(struct bxe_softc * sc)8923 bxe_interrupt_alloc(struct bxe_softc *sc)
8924 {
8925 int msix_count = 0;
8926 int msi_count = 0;
8927 int num_requested = 0;
8928 int num_allocated = 0;
8929 int rid, i, j;
8930 int rc;
8931
8932 /* get the number of available MSI/MSI-X interrupts from the OS */
8933 if (sc->interrupt_mode > 0) {
8934 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) {
8935 msix_count = pci_msix_count(sc->dev);
8936 }
8937
8938 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) {
8939 msi_count = pci_msi_count(sc->dev);
8940 }
8941
8942 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n",
8943 msi_count, msix_count);
8944 }
8945
8946 do { /* try allocating MSI-X interrupt resources (at least 2) */
8947 if (sc->interrupt_mode != INTR_MODE_MSIX) {
8948 break;
8949 }
8950
8951 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) ||
8952 (msix_count < 2)) {
8953 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8954 break;
8955 }
8956
8957 /* ask for the necessary number of MSI-X vectors */
8958 num_requested = min((sc->num_queues + 1), msix_count);
8959
8960 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested);
8961
8962 num_allocated = num_requested;
8963 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) {
8964 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc);
8965 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8966 break;
8967 }
8968
8969 if (num_allocated < 2) { /* possible? */
8970 BLOGE(sc, "MSI-X allocation less than 2!\n");
8971 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8972 pci_release_msi(sc->dev);
8973 break;
8974 }
8975
8976 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n",
8977 num_requested, num_allocated);
8978
8979 /* best effort so use the number of vectors allocated to us */
8980 sc->intr_count = num_allocated;
8981 sc->num_queues = num_allocated - 1;
8982
8983 rid = 1; /* initial resource identifier */
8984
8985 /* allocate the MSI-X vectors */
8986 for (i = 0; i < num_allocated; i++) {
8987 sc->intr[i].rid = (rid + i);
8988
8989 if ((sc->intr[i].resource =
8990 bus_alloc_resource_any(sc->dev,
8991 SYS_RES_IRQ,
8992 &sc->intr[i].rid,
8993 RF_ACTIVE)) == NULL) {
8994 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n",
8995 i, (rid + i));
8996
8997 for (j = (i - 1); j >= 0; j--) {
8998 bus_release_resource(sc->dev,
8999 SYS_RES_IRQ,
9000 sc->intr[j].rid,
9001 sc->intr[j].resource);
9002 }
9003
9004 sc->intr_count = 0;
9005 sc->num_queues = 0;
9006 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9007 pci_release_msi(sc->dev);
9008 break;
9009 }
9010
9011 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i));
9012 }
9013 } while (0);
9014
9015 do { /* try allocating MSI vector resources (at least 2) */
9016 if (sc->interrupt_mode != INTR_MODE_MSI) {
9017 break;
9018 }
9019
9020 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) ||
9021 (msi_count < 1)) {
9022 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9023 break;
9024 }
9025
9026 /* ask for a single MSI vector */
9027 num_requested = 1;
9028
9029 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested);
9030
9031 num_allocated = num_requested;
9032 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) {
9033 BLOGE(sc, "MSI alloc failed (%d)!\n", rc);
9034 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9035 break;
9036 }
9037
9038 if (num_allocated != 1) { /* possible? */
9039 BLOGE(sc, "MSI allocation is not 1!\n");
9040 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9041 pci_release_msi(sc->dev);
9042 break;
9043 }
9044
9045 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n",
9046 num_requested, num_allocated);
9047
9048 /* best effort so use the number of vectors allocated to us */
9049 sc->intr_count = num_allocated;
9050 sc->num_queues = num_allocated;
9051
9052 rid = 1; /* initial resource identifier */
9053
9054 sc->intr[0].rid = rid;
9055
9056 if ((sc->intr[0].resource =
9057 bus_alloc_resource_any(sc->dev,
9058 SYS_RES_IRQ,
9059 &sc->intr[0].rid,
9060 RF_ACTIVE)) == NULL) {
9061 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid);
9062 sc->intr_count = 0;
9063 sc->num_queues = 0;
9064 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9065 pci_release_msi(sc->dev);
9066 break;
9067 }
9068
9069 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid);
9070 } while (0);
9071
9072 do { /* try allocating INTx vector resources */
9073 if (sc->interrupt_mode != INTR_MODE_INTX) {
9074 break;
9075 }
9076
9077 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n");
9078
9079 /* only one vector for INTx */
9080 sc->intr_count = 1;
9081 sc->num_queues = 1;
9082
9083 rid = 0; /* initial resource identifier */
9084
9085 sc->intr[0].rid = rid;
9086
9087 if ((sc->intr[0].resource =
9088 bus_alloc_resource_any(sc->dev,
9089 SYS_RES_IRQ,
9090 &sc->intr[0].rid,
9091 (RF_ACTIVE | RF_SHAREABLE))) == NULL) {
9092 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid);
9093 sc->intr_count = 0;
9094 sc->num_queues = 0;
9095 sc->interrupt_mode = -1; /* Failed! */
9096 break;
9097 }
9098
9099 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid);
9100 } while (0);
9101
9102 if (sc->interrupt_mode == -1) {
9103 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n");
9104 rc = 1;
9105 } else {
9106 BLOGD(sc, DBG_LOAD,
9107 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n",
9108 sc->interrupt_mode, sc->num_queues);
9109 rc = 0;
9110 }
9111
9112 return (rc);
9113 }
9114
9115 static void
bxe_interrupt_detach(struct bxe_softc * sc)9116 bxe_interrupt_detach(struct bxe_softc *sc)
9117 {
9118 struct bxe_fastpath *fp;
9119 int i;
9120
9121 /* release interrupt resources */
9122 for (i = 0; i < sc->intr_count; i++) {
9123 if (sc->intr[i].resource && sc->intr[i].tag) {
9124 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i);
9125 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag);
9126 }
9127 }
9128
9129 for (i = 0; i < sc->num_queues; i++) {
9130 fp = &sc->fp[i];
9131 if (fp->tq) {
9132 taskqueue_drain(fp->tq, &fp->tq_task);
9133 taskqueue_drain(fp->tq, &fp->tx_task);
9134 while (taskqueue_cancel_timeout(fp->tq, &fp->tx_timeout_task,
9135 NULL))
9136 taskqueue_drain_timeout(fp->tq, &fp->tx_timeout_task);
9137 }
9138
9139 for (i = 0; i < sc->num_queues; i++) {
9140 fp = &sc->fp[i];
9141 if (fp->tq != NULL) {
9142 taskqueue_free(fp->tq);
9143 fp->tq = NULL;
9144 }
9145 }
9146 }
9147
9148 if (sc->sp_tq) {
9149 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task);
9150 taskqueue_free(sc->sp_tq);
9151 sc->sp_tq = NULL;
9152 }
9153 }
9154
9155 /*
9156 * Enables interrupts and attach to the ISR.
9157 *
9158 * When using multiple MSI/MSI-X vectors the first vector
9159 * is used for slowpath operations while all remaining
9160 * vectors are used for fastpath operations. If only a
9161 * single MSI/MSI-X vector is used (SINGLE_ISR) then the
9162 * ISR must look for both slowpath and fastpath completions.
9163 */
9164 static int
bxe_interrupt_attach(struct bxe_softc * sc)9165 bxe_interrupt_attach(struct bxe_softc *sc)
9166 {
9167 struct bxe_fastpath *fp;
9168 int rc = 0;
9169 int i;
9170
9171 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name),
9172 "bxe%d_sp_tq", sc->unit);
9173 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc);
9174 sc->sp_tq = taskqueue_create(sc->sp_tq_name, M_NOWAIT,
9175 taskqueue_thread_enqueue,
9176 &sc->sp_tq);
9177 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */
9178 "%s", sc->sp_tq_name);
9179
9180
9181 for (i = 0; i < sc->num_queues; i++) {
9182 fp = &sc->fp[i];
9183 snprintf(fp->tq_name, sizeof(fp->tq_name),
9184 "bxe%d_fp%d_tq", sc->unit, i);
9185 NET_TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp);
9186 TASK_INIT(&fp->tx_task, 0, bxe_tx_mq_start_deferred, fp);
9187 fp->tq = taskqueue_create(fp->tq_name, M_NOWAIT,
9188 taskqueue_thread_enqueue,
9189 &fp->tq);
9190 TIMEOUT_TASK_INIT(fp->tq, &fp->tx_timeout_task, 0,
9191 bxe_tx_mq_start_deferred, fp);
9192 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */
9193 "%s", fp->tq_name);
9194 }
9195
9196 /* setup interrupt handlers */
9197 if (sc->interrupt_mode == INTR_MODE_MSIX) {
9198 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n");
9199
9200 /*
9201 * Setup the interrupt handler. Note that we pass the driver instance
9202 * to the interrupt handler for the slowpath.
9203 */
9204 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9205 (INTR_TYPE_NET | INTR_MPSAFE),
9206 NULL, bxe_intr_sp, sc,
9207 &sc->intr[0].tag)) != 0) {
9208 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc);
9209 goto bxe_interrupt_attach_exit;
9210 }
9211
9212 bus_describe_intr(sc->dev, sc->intr[0].resource,
9213 sc->intr[0].tag, "sp");
9214
9215 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */
9216
9217 /* initialize the fastpath vectors (note the first was used for sp) */
9218 for (i = 0; i < sc->num_queues; i++) {
9219 fp = &sc->fp[i];
9220 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1));
9221
9222 /*
9223 * Setup the interrupt handler. Note that we pass the
9224 * fastpath context to the interrupt handler in this
9225 * case.
9226 */
9227 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource,
9228 (INTR_TYPE_NET | INTR_MPSAFE),
9229 NULL, bxe_intr_fp, fp,
9230 &sc->intr[i + 1].tag)) != 0) {
9231 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n",
9232 (i + 1), rc);
9233 goto bxe_interrupt_attach_exit;
9234 }
9235
9236 bus_describe_intr(sc->dev, sc->intr[i + 1].resource,
9237 sc->intr[i + 1].tag, "fp%02d", i);
9238
9239 /* bind the fastpath instance to a cpu */
9240 if (sc->num_queues > 1) {
9241 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i);
9242 }
9243
9244 fp->state = BXE_FP_STATE_IRQ;
9245 }
9246 } else if (sc->interrupt_mode == INTR_MODE_MSI) {
9247 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n");
9248
9249 /*
9250 * Setup the interrupt handler. Note that we pass the
9251 * driver instance to the interrupt handler which
9252 * will handle both the slowpath and fastpath.
9253 */
9254 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9255 (INTR_TYPE_NET | INTR_MPSAFE),
9256 NULL, bxe_intr_legacy, sc,
9257 &sc->intr[0].tag)) != 0) {
9258 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc);
9259 goto bxe_interrupt_attach_exit;
9260 }
9261
9262 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */
9263 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n");
9264
9265 /*
9266 * Setup the interrupt handler. Note that we pass the
9267 * driver instance to the interrupt handler which
9268 * will handle both the slowpath and fastpath.
9269 */
9270 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9271 (INTR_TYPE_NET | INTR_MPSAFE),
9272 NULL, bxe_intr_legacy, sc,
9273 &sc->intr[0].tag)) != 0) {
9274 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc);
9275 goto bxe_interrupt_attach_exit;
9276 }
9277 }
9278
9279 bxe_interrupt_attach_exit:
9280
9281 return (rc);
9282 }
9283
9284 static int bxe_init_hw_common_chip(struct bxe_softc *sc);
9285 static int bxe_init_hw_common(struct bxe_softc *sc);
9286 static int bxe_init_hw_port(struct bxe_softc *sc);
9287 static int bxe_init_hw_func(struct bxe_softc *sc);
9288 static void bxe_reset_common(struct bxe_softc *sc);
9289 static void bxe_reset_port(struct bxe_softc *sc);
9290 static void bxe_reset_func(struct bxe_softc *sc);
9291 static int bxe_gunzip_init(struct bxe_softc *sc);
9292 static void bxe_gunzip_end(struct bxe_softc *sc);
9293 static int bxe_init_firmware(struct bxe_softc *sc);
9294 static void bxe_release_firmware(struct bxe_softc *sc);
9295
9296 static struct
9297 ecore_func_sp_drv_ops bxe_func_sp_drv = {
9298 .init_hw_cmn_chip = bxe_init_hw_common_chip,
9299 .init_hw_cmn = bxe_init_hw_common,
9300 .init_hw_port = bxe_init_hw_port,
9301 .init_hw_func = bxe_init_hw_func,
9302
9303 .reset_hw_cmn = bxe_reset_common,
9304 .reset_hw_port = bxe_reset_port,
9305 .reset_hw_func = bxe_reset_func,
9306
9307 .gunzip_init = bxe_gunzip_init,
9308 .gunzip_end = bxe_gunzip_end,
9309
9310 .init_fw = bxe_init_firmware,
9311 .release_fw = bxe_release_firmware,
9312 };
9313
9314 static void
bxe_init_func_obj(struct bxe_softc * sc)9315 bxe_init_func_obj(struct bxe_softc *sc)
9316 {
9317 sc->dmae_ready = 0;
9318
9319 ecore_init_func_obj(sc,
9320 &sc->func_obj,
9321 BXE_SP(sc, func_rdata),
9322 BXE_SP_MAPPING(sc, func_rdata),
9323 BXE_SP(sc, func_afex_rdata),
9324 BXE_SP_MAPPING(sc, func_afex_rdata),
9325 &bxe_func_sp_drv);
9326 }
9327
9328 static int
bxe_init_hw(struct bxe_softc * sc,uint32_t load_code)9329 bxe_init_hw(struct bxe_softc *sc,
9330 uint32_t load_code)
9331 {
9332 struct ecore_func_state_params func_params = { NULL };
9333 int rc;
9334
9335 /* prepare the parameters for function state transitions */
9336 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
9337
9338 func_params.f_obj = &sc->func_obj;
9339 func_params.cmd = ECORE_F_CMD_HW_INIT;
9340
9341 func_params.params.hw_init.load_phase = load_code;
9342
9343 /*
9344 * Via a plethora of function pointers, we will eventually reach
9345 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func().
9346 */
9347 rc = ecore_func_state_change(sc, &func_params);
9348
9349 return (rc);
9350 }
9351
9352 static void
bxe_fill(struct bxe_softc * sc,uint32_t addr,int fill,uint32_t len)9353 bxe_fill(struct bxe_softc *sc,
9354 uint32_t addr,
9355 int fill,
9356 uint32_t len)
9357 {
9358 uint32_t i;
9359
9360 if (!(len % 4) && !(addr % 4)) {
9361 for (i = 0; i < len; i += 4) {
9362 REG_WR(sc, (addr + i), fill);
9363 }
9364 } else {
9365 for (i = 0; i < len; i++) {
9366 REG_WR8(sc, (addr + i), fill);
9367 }
9368 }
9369 }
9370
9371 /* writes FP SP data to FW - data_size in dwords */
9372 static void
bxe_wr_fp_sb_data(struct bxe_softc * sc,int fw_sb_id,uint32_t * sb_data_p,uint32_t data_size)9373 bxe_wr_fp_sb_data(struct bxe_softc *sc,
9374 int fw_sb_id,
9375 uint32_t *sb_data_p,
9376 uint32_t data_size)
9377 {
9378 int index;
9379
9380 for (index = 0; index < data_size; index++) {
9381 REG_WR(sc,
9382 (BAR_CSTRORM_INTMEM +
9383 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
9384 (sizeof(uint32_t) * index)),
9385 *(sb_data_p + index));
9386 }
9387 }
9388
9389 static void
bxe_zero_fp_sb(struct bxe_softc * sc,int fw_sb_id)9390 bxe_zero_fp_sb(struct bxe_softc *sc,
9391 int fw_sb_id)
9392 {
9393 struct hc_status_block_data_e2 sb_data_e2;
9394 struct hc_status_block_data_e1x sb_data_e1x;
9395 uint32_t *sb_data_p;
9396 uint32_t data_size = 0;
9397
9398 if (!CHIP_IS_E1x(sc)) {
9399 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9400 sb_data_e2.common.state = SB_DISABLED;
9401 sb_data_e2.common.p_func.vf_valid = FALSE;
9402 sb_data_p = (uint32_t *)&sb_data_e2;
9403 data_size = (sizeof(struct hc_status_block_data_e2) /
9404 sizeof(uint32_t));
9405 } else {
9406 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9407 sb_data_e1x.common.state = SB_DISABLED;
9408 sb_data_e1x.common.p_func.vf_valid = FALSE;
9409 sb_data_p = (uint32_t *)&sb_data_e1x;
9410 data_size = (sizeof(struct hc_status_block_data_e1x) /
9411 sizeof(uint32_t));
9412 }
9413
9414 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9415
9416 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)),
9417 0, CSTORM_STATUS_BLOCK_SIZE);
9418 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
9419 0, CSTORM_SYNC_BLOCK_SIZE);
9420 }
9421
9422 static void
bxe_wr_sp_sb_data(struct bxe_softc * sc,struct hc_sp_status_block_data * sp_sb_data)9423 bxe_wr_sp_sb_data(struct bxe_softc *sc,
9424 struct hc_sp_status_block_data *sp_sb_data)
9425 {
9426 int i;
9427
9428 for (i = 0;
9429 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
9430 i++) {
9431 REG_WR(sc,
9432 (BAR_CSTRORM_INTMEM +
9433 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
9434 (i * sizeof(uint32_t))),
9435 *((uint32_t *)sp_sb_data + i));
9436 }
9437 }
9438
9439 static void
bxe_zero_sp_sb(struct bxe_softc * sc)9440 bxe_zero_sp_sb(struct bxe_softc *sc)
9441 {
9442 struct hc_sp_status_block_data sp_sb_data;
9443
9444 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9445
9446 sp_sb_data.state = SB_DISABLED;
9447 sp_sb_data.p_func.vf_valid = FALSE;
9448
9449 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9450
9451 bxe_fill(sc,
9452 (BAR_CSTRORM_INTMEM +
9453 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
9454 0, CSTORM_SP_STATUS_BLOCK_SIZE);
9455 bxe_fill(sc,
9456 (BAR_CSTRORM_INTMEM +
9457 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
9458 0, CSTORM_SP_SYNC_BLOCK_SIZE);
9459 }
9460
9461 static void
bxe_setup_ndsb_state_machine(struct hc_status_block_sm * hc_sm,int igu_sb_id,int igu_seg_id)9462 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
9463 int igu_sb_id,
9464 int igu_seg_id)
9465 {
9466 hc_sm->igu_sb_id = igu_sb_id;
9467 hc_sm->igu_seg_id = igu_seg_id;
9468 hc_sm->timer_value = 0xFF;
9469 hc_sm->time_to_expire = 0xFFFFFFFF;
9470 }
9471
9472 static void
bxe_map_sb_state_machines(struct hc_index_data * index_data)9473 bxe_map_sb_state_machines(struct hc_index_data *index_data)
9474 {
9475 /* zero out state machine indices */
9476
9477 /* rx indices */
9478 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9479
9480 /* tx indices */
9481 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9482 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
9483 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
9484 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
9485
9486 /* map indices */
9487
9488 /* rx indices */
9489 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
9490 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9491
9492 /* tx indices */
9493 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
9494 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9495 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
9496 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9497 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
9498 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9499 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
9500 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9501 }
9502
9503 static void
bxe_init_sb(struct bxe_softc * sc,bus_addr_t busaddr,int vfid,uint8_t vf_valid,int fw_sb_id,int igu_sb_id)9504 bxe_init_sb(struct bxe_softc *sc,
9505 bus_addr_t busaddr,
9506 int vfid,
9507 uint8_t vf_valid,
9508 int fw_sb_id,
9509 int igu_sb_id)
9510 {
9511 struct hc_status_block_data_e2 sb_data_e2;
9512 struct hc_status_block_data_e1x sb_data_e1x;
9513 struct hc_status_block_sm *hc_sm_p;
9514 uint32_t *sb_data_p;
9515 int igu_seg_id;
9516 int data_size;
9517
9518 if (CHIP_INT_MODE_IS_BC(sc)) {
9519 igu_seg_id = HC_SEG_ACCESS_NORM;
9520 } else {
9521 igu_seg_id = IGU_SEG_ACCESS_NORM;
9522 }
9523
9524 bxe_zero_fp_sb(sc, fw_sb_id);
9525
9526 if (!CHIP_IS_E1x(sc)) {
9527 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9528 sb_data_e2.common.state = SB_ENABLED;
9529 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
9530 sb_data_e2.common.p_func.vf_id = vfid;
9531 sb_data_e2.common.p_func.vf_valid = vf_valid;
9532 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
9533 sb_data_e2.common.same_igu_sb_1b = TRUE;
9534 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
9535 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
9536 hc_sm_p = sb_data_e2.common.state_machine;
9537 sb_data_p = (uint32_t *)&sb_data_e2;
9538 data_size = (sizeof(struct hc_status_block_data_e2) /
9539 sizeof(uint32_t));
9540 bxe_map_sb_state_machines(sb_data_e2.index_data);
9541 } else {
9542 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9543 sb_data_e1x.common.state = SB_ENABLED;
9544 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
9545 sb_data_e1x.common.p_func.vf_id = 0xff;
9546 sb_data_e1x.common.p_func.vf_valid = FALSE;
9547 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
9548 sb_data_e1x.common.same_igu_sb_1b = TRUE;
9549 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
9550 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
9551 hc_sm_p = sb_data_e1x.common.state_machine;
9552 sb_data_p = (uint32_t *)&sb_data_e1x;
9553 data_size = (sizeof(struct hc_status_block_data_e1x) /
9554 sizeof(uint32_t));
9555 bxe_map_sb_state_machines(sb_data_e1x.index_data);
9556 }
9557
9558 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
9559 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
9560
9561 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id);
9562
9563 /* write indices to HW - PCI guarantees endianity of regpairs */
9564 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9565 }
9566
9567 static inline uint8_t
bxe_fp_qzone_id(struct bxe_fastpath * fp)9568 bxe_fp_qzone_id(struct bxe_fastpath *fp)
9569 {
9570 if (CHIP_IS_E1x(fp->sc)) {
9571 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
9572 } else {
9573 return (fp->cl_id);
9574 }
9575 }
9576
9577 static inline uint32_t
bxe_rx_ustorm_prods_offset(struct bxe_softc * sc,struct bxe_fastpath * fp)9578 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc,
9579 struct bxe_fastpath *fp)
9580 {
9581 uint32_t offset = BAR_USTRORM_INTMEM;
9582
9583 if (!CHIP_IS_E1x(sc)) {
9584 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
9585 } else {
9586 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
9587 }
9588
9589 return (offset);
9590 }
9591
9592 static void
bxe_init_eth_fp(struct bxe_softc * sc,int idx)9593 bxe_init_eth_fp(struct bxe_softc *sc,
9594 int idx)
9595 {
9596 struct bxe_fastpath *fp = &sc->fp[idx];
9597 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
9598 unsigned long q_type = 0;
9599 int cos;
9600
9601 fp->sc = sc;
9602 fp->index = idx;
9603
9604 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
9605 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
9606
9607 fp->cl_id = (CHIP_IS_E1x(sc)) ?
9608 (SC_L_ID(sc) + idx) :
9609 /* want client ID same as IGU SB ID for non-E1 */
9610 fp->igu_sb_id;
9611 fp->cl_qzone_id = bxe_fp_qzone_id(fp);
9612
9613 /* setup sb indices */
9614 if (!CHIP_IS_E1x(sc)) {
9615 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
9616 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
9617 } else {
9618 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
9619 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index;
9620 }
9621
9622 /* init shortcut */
9623 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp);
9624
9625 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
9626
9627 /*
9628 * XXX If multiple CoS is ever supported then each fastpath structure
9629 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
9630 */
9631 for (cos = 0; cos < sc->max_cos; cos++) {
9632 cids[cos] = idx;
9633 }
9634 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
9635
9636 /* nothing more for a VF to do */
9637 if (IS_VF(sc)) {
9638 return;
9639 }
9640
9641 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE,
9642 fp->fw_sb_id, fp->igu_sb_id);
9643
9644 bxe_update_fp_sb_idx(fp);
9645
9646 /* Configure Queue State object */
9647 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX);
9648 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX);
9649
9650 ecore_init_queue_obj(sc,
9651 &sc->sp_objs[idx].q_obj,
9652 fp->cl_id,
9653 cids,
9654 sc->max_cos,
9655 SC_FUNC(sc),
9656 BXE_SP(sc, q_rdata),
9657 BXE_SP_MAPPING(sc, q_rdata),
9658 q_type);
9659
9660 /* configure classification DBs */
9661 ecore_init_mac_obj(sc,
9662 &sc->sp_objs[idx].mac_obj,
9663 fp->cl_id,
9664 idx,
9665 SC_FUNC(sc),
9666 BXE_SP(sc, mac_rdata),
9667 BXE_SP_MAPPING(sc, mac_rdata),
9668 ECORE_FILTER_MAC_PENDING,
9669 &sc->sp_state,
9670 ECORE_OBJ_TYPE_RX_TX,
9671 &sc->macs_pool);
9672
9673 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n",
9674 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id);
9675 }
9676
9677 static inline void
bxe_update_rx_prod(struct bxe_softc * sc,struct bxe_fastpath * fp,uint16_t rx_bd_prod,uint16_t rx_cq_prod,uint16_t rx_sge_prod)9678 bxe_update_rx_prod(struct bxe_softc *sc,
9679 struct bxe_fastpath *fp,
9680 uint16_t rx_bd_prod,
9681 uint16_t rx_cq_prod,
9682 uint16_t rx_sge_prod)
9683 {
9684 struct ustorm_eth_rx_producers rx_prods = { 0 };
9685 uint32_t i;
9686
9687 /* update producers */
9688 rx_prods.bd_prod = rx_bd_prod;
9689 rx_prods.cqe_prod = rx_cq_prod;
9690 rx_prods.sge_prod = rx_sge_prod;
9691
9692 /*
9693 * Make sure that the BD and SGE data is updated before updating the
9694 * producers since FW might read the BD/SGE right after the producer
9695 * is updated.
9696 * This is only applicable for weak-ordered memory model archs such
9697 * as IA-64. The following barrier is also mandatory since FW will
9698 * assumes BDs must have buffers.
9699 */
9700 wmb();
9701
9702 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
9703 REG_WR(sc,
9704 (fp->ustorm_rx_prods_offset + (i * 4)),
9705 ((uint32_t *)&rx_prods)[i]);
9706 }
9707
9708 wmb(); /* keep prod updates ordered */
9709
9710 BLOGD(sc, DBG_RX,
9711 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n",
9712 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod);
9713 }
9714
9715 static void
bxe_init_rx_rings(struct bxe_softc * sc)9716 bxe_init_rx_rings(struct bxe_softc *sc)
9717 {
9718 struct bxe_fastpath *fp;
9719 int i;
9720
9721 for (i = 0; i < sc->num_queues; i++) {
9722 fp = &sc->fp[i];
9723
9724 fp->rx_bd_cons = 0;
9725
9726 /*
9727 * Activate the BD ring...
9728 * Warning, this will generate an interrupt (to the TSTORM)
9729 * so this can only be done after the chip is initialized
9730 */
9731 bxe_update_rx_prod(sc, fp,
9732 fp->rx_bd_prod,
9733 fp->rx_cq_prod,
9734 fp->rx_sge_prod);
9735
9736 if (i != 0) {
9737 continue;
9738 }
9739
9740 if (CHIP_IS_E1(sc)) {
9741 REG_WR(sc,
9742 (BAR_USTRORM_INTMEM +
9743 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))),
9744 U64_LO(fp->rcq_dma.paddr));
9745 REG_WR(sc,
9746 (BAR_USTRORM_INTMEM +
9747 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4),
9748 U64_HI(fp->rcq_dma.paddr));
9749 }
9750 }
9751 }
9752
9753 static void
bxe_init_tx_ring_one(struct bxe_fastpath * fp)9754 bxe_init_tx_ring_one(struct bxe_fastpath *fp)
9755 {
9756 SET_FLAG(fp->tx_db.data.header.data, DOORBELL_HDR_T_DB_TYPE, 1);
9757 fp->tx_db.data.zero_fill1 = 0;
9758 fp->tx_db.data.prod = 0;
9759
9760 fp->tx_pkt_prod = 0;
9761 fp->tx_pkt_cons = 0;
9762 fp->tx_bd_prod = 0;
9763 fp->tx_bd_cons = 0;
9764 fp->eth_q_stats.tx_pkts = 0;
9765 }
9766
9767 static inline void
bxe_init_tx_rings(struct bxe_softc * sc)9768 bxe_init_tx_rings(struct bxe_softc *sc)
9769 {
9770 int i;
9771
9772 for (i = 0; i < sc->num_queues; i++) {
9773 bxe_init_tx_ring_one(&sc->fp[i]);
9774 }
9775 }
9776
9777 static void
bxe_init_def_sb(struct bxe_softc * sc)9778 bxe_init_def_sb(struct bxe_softc *sc)
9779 {
9780 struct host_sp_status_block *def_sb = sc->def_sb;
9781 bus_addr_t mapping = sc->def_sb_dma.paddr;
9782 int igu_sp_sb_index;
9783 int igu_seg_id;
9784 int port = SC_PORT(sc);
9785 int func = SC_FUNC(sc);
9786 int reg_offset, reg_offset_en5;
9787 uint64_t section;
9788 int index, sindex;
9789 struct hc_sp_status_block_data sp_sb_data;
9790
9791 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9792
9793 if (CHIP_INT_MODE_IS_BC(sc)) {
9794 igu_sp_sb_index = DEF_SB_IGU_ID;
9795 igu_seg_id = HC_SEG_ACCESS_DEF;
9796 } else {
9797 igu_sp_sb_index = sc->igu_dsb_id;
9798 igu_seg_id = IGU_SEG_ACCESS_DEF;
9799 }
9800
9801 /* attentions */
9802 section = ((uint64_t)mapping +
9803 offsetof(struct host_sp_status_block, atten_status_block));
9804 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
9805 sc->attn_state = 0;
9806
9807 reg_offset = (port) ?
9808 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
9809 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
9810 reg_offset_en5 = (port) ?
9811 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
9812 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
9813
9814 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
9815 /* take care of sig[0]..sig[4] */
9816 for (sindex = 0; sindex < 4; sindex++) {
9817 sc->attn_group[index].sig[sindex] =
9818 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
9819 }
9820
9821 if (!CHIP_IS_E1x(sc)) {
9822 /*
9823 * enable5 is separate from the rest of the registers,
9824 * and the address skip is 4 and not 16 between the
9825 * different groups
9826 */
9827 sc->attn_group[index].sig[4] =
9828 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
9829 } else {
9830 sc->attn_group[index].sig[4] = 0;
9831 }
9832 }
9833
9834 if (sc->devinfo.int_block == INT_BLOCK_HC) {
9835 reg_offset = (port) ?
9836 HC_REG_ATTN_MSG1_ADDR_L :
9837 HC_REG_ATTN_MSG0_ADDR_L;
9838 REG_WR(sc, reg_offset, U64_LO(section));
9839 REG_WR(sc, (reg_offset + 4), U64_HI(section));
9840 } else if (!CHIP_IS_E1x(sc)) {
9841 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
9842 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
9843 }
9844
9845 section = ((uint64_t)mapping +
9846 offsetof(struct host_sp_status_block, sp_sb));
9847
9848 bxe_zero_sp_sb(sc);
9849
9850 /* PCI guarantees endianity of regpair */
9851 sp_sb_data.state = SB_ENABLED;
9852 sp_sb_data.host_sb_addr.lo = U64_LO(section);
9853 sp_sb_data.host_sb_addr.hi = U64_HI(section);
9854 sp_sb_data.igu_sb_id = igu_sp_sb_index;
9855 sp_sb_data.igu_seg_id = igu_seg_id;
9856 sp_sb_data.p_func.pf_id = func;
9857 sp_sb_data.p_func.vnic_id = SC_VN(sc);
9858 sp_sb_data.p_func.vf_id = 0xff;
9859
9860 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9861
9862 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
9863 }
9864
9865 static void
bxe_init_sp_ring(struct bxe_softc * sc)9866 bxe_init_sp_ring(struct bxe_softc *sc)
9867 {
9868 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
9869 sc->spq_prod_idx = 0;
9870 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
9871 sc->spq_prod_bd = sc->spq;
9872 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
9873 }
9874
9875 static void
bxe_init_eq_ring(struct bxe_softc * sc)9876 bxe_init_eq_ring(struct bxe_softc *sc)
9877 {
9878 union event_ring_elem *elem;
9879 int i;
9880
9881 for (i = 1; i <= NUM_EQ_PAGES; i++) {
9882 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
9883
9884 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
9885 BCM_PAGE_SIZE *
9886 (i % NUM_EQ_PAGES)));
9887 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
9888 BCM_PAGE_SIZE *
9889 (i % NUM_EQ_PAGES)));
9890 }
9891
9892 sc->eq_cons = 0;
9893 sc->eq_prod = NUM_EQ_DESC;
9894 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
9895
9896 atomic_store_rel_long(&sc->eq_spq_left,
9897 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
9898 NUM_EQ_DESC) - 1));
9899 }
9900
9901 static void
bxe_init_internal_common(struct bxe_softc * sc)9902 bxe_init_internal_common(struct bxe_softc *sc)
9903 {
9904 int i;
9905
9906 /*
9907 * Zero this manually as its initialization is currently missing
9908 * in the initTool.
9909 */
9910 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
9911 REG_WR(sc,
9912 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
9913 0);
9914 }
9915
9916 if (!CHIP_IS_E1x(sc)) {
9917 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
9918 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
9919 }
9920 }
9921
9922 static void
bxe_init_internal(struct bxe_softc * sc,uint32_t load_code)9923 bxe_init_internal(struct bxe_softc *sc,
9924 uint32_t load_code)
9925 {
9926 switch (load_code) {
9927 case FW_MSG_CODE_DRV_LOAD_COMMON:
9928 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
9929 bxe_init_internal_common(sc);
9930 /* no break */
9931
9932 case FW_MSG_CODE_DRV_LOAD_PORT:
9933 /* nothing to do */
9934 /* no break */
9935
9936 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
9937 /* internal memory per function is initialized inside bxe_pf_init */
9938 break;
9939
9940 default:
9941 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code);
9942 break;
9943 }
9944 }
9945
9946 static void
storm_memset_func_cfg(struct bxe_softc * sc,struct tstorm_eth_function_common_config * tcfg,uint16_t abs_fid)9947 storm_memset_func_cfg(struct bxe_softc *sc,
9948 struct tstorm_eth_function_common_config *tcfg,
9949 uint16_t abs_fid)
9950 {
9951 uint32_t addr;
9952 size_t size;
9953
9954 addr = (BAR_TSTRORM_INTMEM +
9955 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
9956 size = sizeof(struct tstorm_eth_function_common_config);
9957 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg);
9958 }
9959
9960 static void
bxe_func_init(struct bxe_softc * sc,struct bxe_func_init_params * p)9961 bxe_func_init(struct bxe_softc *sc,
9962 struct bxe_func_init_params *p)
9963 {
9964 struct tstorm_eth_function_common_config tcfg = { 0 };
9965
9966 if (CHIP_IS_E1x(sc)) {
9967 storm_memset_func_cfg(sc, &tcfg, p->func_id);
9968 }
9969
9970 /* Enable the function in the FW */
9971 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
9972 storm_memset_func_en(sc, p->func_id, 1);
9973
9974 /* spq */
9975 if (p->func_flgs & FUNC_FLG_SPQ) {
9976 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
9977 REG_WR(sc,
9978 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)),
9979 p->spq_prod);
9980 }
9981 }
9982
9983 /*
9984 * Calculates the sum of vn_min_rates.
9985 * It's needed for further normalizing of the min_rates.
9986 * Returns:
9987 * sum of vn_min_rates.
9988 * or
9989 * 0 - if all the min_rates are 0.
9990 * In the later case fainess algorithm should be deactivated.
9991 * If all min rates are not zero then those that are zeroes will be set to 1.
9992 */
9993 static void
bxe_calc_vn_min(struct bxe_softc * sc,struct cmng_init_input * input)9994 bxe_calc_vn_min(struct bxe_softc *sc,
9995 struct cmng_init_input *input)
9996 {
9997 uint32_t vn_cfg;
9998 uint32_t vn_min_rate;
9999 int all_zero = 1;
10000 int vn;
10001
10002 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10003 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10004 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
10005 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
10006
10007 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10008 /* skip hidden VNs */
10009 vn_min_rate = 0;
10010 } else if (!vn_min_rate) {
10011 /* If min rate is zero - set it to 100 */
10012 vn_min_rate = DEF_MIN_RATE;
10013 } else {
10014 all_zero = 0;
10015 }
10016
10017 input->vnic_min_rate[vn] = vn_min_rate;
10018 }
10019
10020 /* if ETS or all min rates are zeros - disable fairness */
10021 if (BXE_IS_ETS_ENABLED(sc)) {
10022 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10023 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n");
10024 } else if (all_zero) {
10025 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10026 BLOGD(sc, DBG_LOAD,
10027 "Fariness disabled (all MIN values are zeroes)\n");
10028 } else {
10029 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10030 }
10031 }
10032
10033 static inline uint16_t
bxe_extract_max_cfg(struct bxe_softc * sc,uint32_t mf_cfg)10034 bxe_extract_max_cfg(struct bxe_softc *sc,
10035 uint32_t mf_cfg)
10036 {
10037 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
10038 FUNC_MF_CFG_MAX_BW_SHIFT);
10039
10040 if (!max_cfg) {
10041 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n");
10042 max_cfg = 100;
10043 }
10044
10045 return (max_cfg);
10046 }
10047
10048 static void
bxe_calc_vn_max(struct bxe_softc * sc,int vn,struct cmng_init_input * input)10049 bxe_calc_vn_max(struct bxe_softc *sc,
10050 int vn,
10051 struct cmng_init_input *input)
10052 {
10053 uint16_t vn_max_rate;
10054 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10055 uint32_t max_cfg;
10056
10057 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10058 vn_max_rate = 0;
10059 } else {
10060 max_cfg = bxe_extract_max_cfg(sc, vn_cfg);
10061
10062 if (IS_MF_SI(sc)) {
10063 /* max_cfg in percents of linkspeed */
10064 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100);
10065 } else { /* SD modes */
10066 /* max_cfg is absolute in 100Mb units */
10067 vn_max_rate = (max_cfg * 100);
10068 }
10069 }
10070
10071 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
10072
10073 input->vnic_max_rate[vn] = vn_max_rate;
10074 }
10075
10076 static void
bxe_cmng_fns_init(struct bxe_softc * sc,uint8_t read_cfg,uint8_t cmng_type)10077 bxe_cmng_fns_init(struct bxe_softc *sc,
10078 uint8_t read_cfg,
10079 uint8_t cmng_type)
10080 {
10081 struct cmng_init_input input;
10082 int vn;
10083
10084 memset(&input, 0, sizeof(struct cmng_init_input));
10085
10086 input.port_rate = sc->link_vars.line_speed;
10087
10088 if (cmng_type == CMNG_FNS_MINMAX) {
10089 /* read mf conf from shmem */
10090 if (read_cfg) {
10091 bxe_read_mf_cfg(sc);
10092 }
10093
10094 /* get VN min rate and enable fairness if not 0 */
10095 bxe_calc_vn_min(sc, &input);
10096
10097 /* get VN max rate */
10098 if (sc->port.pmf) {
10099 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10100 bxe_calc_vn_max(sc, vn, &input);
10101 }
10102 }
10103
10104 /* always enable rate shaping and fairness */
10105 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
10106
10107 ecore_init_cmng(&input, &sc->cmng);
10108 return;
10109 }
10110
10111 /* rate shaping and fairness are disabled */
10112 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n");
10113 }
10114
10115 static int
bxe_get_cmng_fns_mode(struct bxe_softc * sc)10116 bxe_get_cmng_fns_mode(struct bxe_softc *sc)
10117 {
10118 if (CHIP_REV_IS_SLOW(sc)) {
10119 return (CMNG_FNS_NONE);
10120 }
10121
10122 if (IS_MF(sc)) {
10123 return (CMNG_FNS_MINMAX);
10124 }
10125
10126 return (CMNG_FNS_NONE);
10127 }
10128
10129 static void
storm_memset_cmng(struct bxe_softc * sc,struct cmng_init * cmng,uint8_t port)10130 storm_memset_cmng(struct bxe_softc *sc,
10131 struct cmng_init *cmng,
10132 uint8_t port)
10133 {
10134 int vn;
10135 int func;
10136 uint32_t addr;
10137 size_t size;
10138
10139 addr = (BAR_XSTRORM_INTMEM +
10140 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
10141 size = sizeof(struct cmng_struct_per_port);
10142 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port);
10143
10144 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10145 func = func_by_vn(sc, vn);
10146
10147 addr = (BAR_XSTRORM_INTMEM +
10148 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
10149 size = sizeof(struct rate_shaping_vars_per_vn);
10150 ecore_storm_memset_struct(sc, addr, size,
10151 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]);
10152
10153 addr = (BAR_XSTRORM_INTMEM +
10154 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
10155 size = sizeof(struct fairness_vars_per_vn);
10156 ecore_storm_memset_struct(sc, addr, size,
10157 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]);
10158 }
10159 }
10160
10161 static void
bxe_pf_init(struct bxe_softc * sc)10162 bxe_pf_init(struct bxe_softc *sc)
10163 {
10164 struct bxe_func_init_params func_init = { 0 };
10165 struct event_ring_data eq_data = { { 0 } };
10166 uint16_t flags;
10167
10168 if (!CHIP_IS_E1x(sc)) {
10169 /* reset IGU PF statistics: MSIX + ATTN */
10170 /* PF */
10171 REG_WR(sc,
10172 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10173 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10174 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10175 0);
10176 /* ATTN */
10177 REG_WR(sc,
10178 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10179 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10180 (BXE_IGU_STAS_MSG_PF_CNT * 4) +
10181 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10182 0);
10183 }
10184
10185 /* function setup flags */
10186 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
10187
10188 /*
10189 * This flag is relevant for E1x only.
10190 * E2 doesn't have a TPA configuration in a function level.
10191 */
10192 flags |= (if_getcapenable(sc->ifp) & IFCAP_LRO) ? FUNC_FLG_TPA : 0;
10193
10194 func_init.func_flgs = flags;
10195 func_init.pf_id = SC_FUNC(sc);
10196 func_init.func_id = SC_FUNC(sc);
10197 func_init.spq_map = sc->spq_dma.paddr;
10198 func_init.spq_prod = sc->spq_prod_idx;
10199
10200 bxe_func_init(sc, &func_init);
10201
10202 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
10203
10204 /*
10205 * Congestion management values depend on the link rate.
10206 * There is no active link so initial link rate is set to 10Gbps.
10207 * When the link comes up the congestion management values are
10208 * re-calculated according to the actual link rate.
10209 */
10210 sc->link_vars.line_speed = SPEED_10000;
10211 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc));
10212
10213 /* Only the PMF sets the HW */
10214 if (sc->port.pmf) {
10215 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
10216 }
10217
10218 /* init Event Queue - PCI bus guarantees correct endainity */
10219 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
10220 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
10221 eq_data.producer = sc->eq_prod;
10222 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
10223 eq_data.sb_id = DEF_SB_ID;
10224 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
10225 }
10226
10227 static void
bxe_hc_int_enable(struct bxe_softc * sc)10228 bxe_hc_int_enable(struct bxe_softc *sc)
10229 {
10230 int port = SC_PORT(sc);
10231 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10232 uint32_t val = REG_RD(sc, addr);
10233 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10234 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10235 (sc->intr_count == 1)) ? TRUE : FALSE;
10236 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10237
10238 if (msix) {
10239 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10240 HC_CONFIG_0_REG_INT_LINE_EN_0);
10241 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10242 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10243 if (single_msix) {
10244 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
10245 }
10246 } else if (msi) {
10247 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
10248 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10249 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10250 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10251 } else {
10252 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10253 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10254 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10255 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10256
10257 if (!CHIP_IS_E1(sc)) {
10258 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n",
10259 val, port, addr);
10260
10261 REG_WR(sc, addr, val);
10262
10263 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
10264 }
10265 }
10266
10267 if (CHIP_IS_E1(sc)) {
10268 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF);
10269 }
10270
10271 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
10272 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10273
10274 REG_WR(sc, addr, val);
10275
10276 /* ensure that HC_CONFIG is written before leading/trailing edge config */
10277 mb();
10278
10279 if (!CHIP_IS_E1(sc)) {
10280 /* init leading/trailing edge */
10281 if (IS_MF(sc)) {
10282 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10283 if (sc->port.pmf) {
10284 /* enable nig and gpio3 attention */
10285 val |= 0x1100;
10286 }
10287 } else {
10288 val = 0xffff;
10289 }
10290
10291 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val);
10292 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val);
10293 }
10294
10295 /* make sure that interrupts are indeed enabled from here on */
10296 mb();
10297 }
10298
10299 static void
bxe_igu_int_enable(struct bxe_softc * sc)10300 bxe_igu_int_enable(struct bxe_softc *sc)
10301 {
10302 uint32_t val;
10303 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10304 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10305 (sc->intr_count == 1)) ? TRUE : FALSE;
10306 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10307
10308 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10309
10310 if (msix) {
10311 val &= ~(IGU_PF_CONF_INT_LINE_EN |
10312 IGU_PF_CONF_SINGLE_ISR_EN);
10313 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10314 IGU_PF_CONF_ATTN_BIT_EN);
10315 if (single_msix) {
10316 val |= IGU_PF_CONF_SINGLE_ISR_EN;
10317 }
10318 } else if (msi) {
10319 val &= ~IGU_PF_CONF_INT_LINE_EN;
10320 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10321 IGU_PF_CONF_ATTN_BIT_EN |
10322 IGU_PF_CONF_SINGLE_ISR_EN);
10323 } else {
10324 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
10325 val |= (IGU_PF_CONF_INT_LINE_EN |
10326 IGU_PF_CONF_ATTN_BIT_EN |
10327 IGU_PF_CONF_SINGLE_ISR_EN);
10328 }
10329
10330 /* clean previous status - need to configure igu prior to ack*/
10331 if ((!msix) || single_msix) {
10332 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10333 bxe_ack_int(sc);
10334 }
10335
10336 val |= IGU_PF_CONF_FUNC_EN;
10337
10338 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n",
10339 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10340
10341 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10342
10343 mb();
10344
10345 /* init leading/trailing edge */
10346 if (IS_MF(sc)) {
10347 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10348 if (sc->port.pmf) {
10349 /* enable nig and gpio3 attention */
10350 val |= 0x1100;
10351 }
10352 } else {
10353 val = 0xffff;
10354 }
10355
10356 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
10357 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
10358
10359 /* make sure that interrupts are indeed enabled from here on */
10360 mb();
10361 }
10362
10363 static void
bxe_int_enable(struct bxe_softc * sc)10364 bxe_int_enable(struct bxe_softc *sc)
10365 {
10366 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10367 bxe_hc_int_enable(sc);
10368 } else {
10369 bxe_igu_int_enable(sc);
10370 }
10371 }
10372
10373 static void
bxe_hc_int_disable(struct bxe_softc * sc)10374 bxe_hc_int_disable(struct bxe_softc *sc)
10375 {
10376 int port = SC_PORT(sc);
10377 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10378 uint32_t val = REG_RD(sc, addr);
10379
10380 /*
10381 * In E1 we must use only PCI configuration space to disable MSI/MSIX
10382 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC
10383 * block
10384 */
10385 if (CHIP_IS_E1(sc)) {
10386 /*
10387 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register
10388 * to prevent from HC sending interrupts after we exit the function
10389 */
10390 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0);
10391
10392 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10395 } else {
10396 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10397 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10398 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10399 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10400 }
10401
10402 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr);
10403
10404 /* flush all outstanding writes */
10405 mb();
10406
10407 REG_WR(sc, addr, val);
10408 if (REG_RD(sc, addr) != val) {
10409 BLOGE(sc, "proper val not read from HC IGU!\n");
10410 }
10411 }
10412
10413 static void
bxe_igu_int_disable(struct bxe_softc * sc)10414 bxe_igu_int_disable(struct bxe_softc *sc)
10415 {
10416 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10417
10418 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
10419 IGU_PF_CONF_INT_LINE_EN |
10420 IGU_PF_CONF_ATTN_BIT_EN);
10421
10422 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val);
10423
10424 /* flush all outstanding writes */
10425 mb();
10426
10427 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10428 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
10429 BLOGE(sc, "proper val not read from IGU!\n");
10430 }
10431 }
10432
10433 static void
bxe_int_disable(struct bxe_softc * sc)10434 bxe_int_disable(struct bxe_softc *sc)
10435 {
10436 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10437 bxe_hc_int_disable(sc);
10438 } else {
10439 bxe_igu_int_disable(sc);
10440 }
10441 }
10442
10443 static void
bxe_nic_init(struct bxe_softc * sc,int load_code)10444 bxe_nic_init(struct bxe_softc *sc,
10445 int load_code)
10446 {
10447 int i;
10448
10449 for (i = 0; i < sc->num_queues; i++) {
10450 bxe_init_eth_fp(sc, i);
10451 }
10452
10453 rmb(); /* ensure status block indices were read */
10454
10455 bxe_init_rx_rings(sc);
10456 bxe_init_tx_rings(sc);
10457
10458 if (IS_VF(sc)) {
10459 return;
10460 }
10461
10462 /* initialize MOD_ABS interrupts */
10463 elink_init_mod_abs_int(sc, &sc->link_vars,
10464 sc->devinfo.chip_id,
10465 sc->devinfo.shmem_base,
10466 sc->devinfo.shmem2_base,
10467 SC_PORT(sc));
10468
10469 bxe_init_def_sb(sc);
10470 bxe_update_dsb_idx(sc);
10471 bxe_init_sp_ring(sc);
10472 bxe_init_eq_ring(sc);
10473 bxe_init_internal(sc, load_code);
10474 bxe_pf_init(sc);
10475 bxe_stats_init(sc);
10476
10477 /* flush all before enabling interrupts */
10478 mb();
10479
10480 bxe_int_enable(sc);
10481
10482 /* check for SPIO5 */
10483 bxe_attn_int_deasserted0(sc,
10484 REG_RD(sc,
10485 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
10486 SC_PORT(sc)*4)) &
10487 AEU_INPUTS_ATTN_BITS_SPIO5);
10488 }
10489
10490 static inline void
bxe_init_objs(struct bxe_softc * sc)10491 bxe_init_objs(struct bxe_softc *sc)
10492 {
10493 /* mcast rules must be added to tx if tx switching is enabled */
10494 ecore_obj_type o_type =
10495 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX :
10496 ECORE_OBJ_TYPE_RX;
10497
10498 /* RX_MODE controlling object */
10499 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
10500
10501 /* multicast configuration controlling object */
10502 ecore_init_mcast_obj(sc,
10503 &sc->mcast_obj,
10504 sc->fp[0].cl_id,
10505 sc->fp[0].index,
10506 SC_FUNC(sc),
10507 SC_FUNC(sc),
10508 BXE_SP(sc, mcast_rdata),
10509 BXE_SP_MAPPING(sc, mcast_rdata),
10510 ECORE_FILTER_MCAST_PENDING,
10511 &sc->sp_state,
10512 o_type);
10513
10514 /* Setup CAM credit pools */
10515 ecore_init_mac_credit_pool(sc,
10516 &sc->macs_pool,
10517 SC_FUNC(sc),
10518 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10519 VNICS_PER_PATH(sc));
10520
10521 ecore_init_vlan_credit_pool(sc,
10522 &sc->vlans_pool,
10523 SC_ABS_FUNC(sc) >> 1,
10524 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10525 VNICS_PER_PATH(sc));
10526
10527 /* RSS configuration object */
10528 ecore_init_rss_config_obj(sc,
10529 &sc->rss_conf_obj,
10530 sc->fp[0].cl_id,
10531 sc->fp[0].index,
10532 SC_FUNC(sc),
10533 SC_FUNC(sc),
10534 BXE_SP(sc, rss_rdata),
10535 BXE_SP_MAPPING(sc, rss_rdata),
10536 ECORE_FILTER_RSS_CONF_PENDING,
10537 &sc->sp_state, ECORE_OBJ_TYPE_RX);
10538 }
10539
10540 /*
10541 * Initialize the function. This must be called before sending CLIENT_SETUP
10542 * for the first client.
10543 */
10544 static inline int
bxe_func_start(struct bxe_softc * sc)10545 bxe_func_start(struct bxe_softc *sc)
10546 {
10547 struct ecore_func_state_params func_params = { NULL };
10548 struct ecore_func_start_params *start_params = &func_params.params.start;
10549
10550 /* Prepare parameters for function state transitions */
10551 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
10552
10553 func_params.f_obj = &sc->func_obj;
10554 func_params.cmd = ECORE_F_CMD_START;
10555
10556 /* Function parameters */
10557 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
10558 start_params->sd_vlan_tag = OVLAN(sc);
10559
10560 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
10561 start_params->network_cos_mode = STATIC_COS;
10562 } else { /* CHIP_IS_E1X */
10563 start_params->network_cos_mode = FW_WRR;
10564 }
10565
10566 //start_params->gre_tunnel_mode = 0;
10567 //start_params->gre_tunnel_rss = 0;
10568
10569 return (ecore_func_state_change(sc, &func_params));
10570 }
10571
10572 static int
bxe_set_power_state(struct bxe_softc * sc,uint8_t state)10573 bxe_set_power_state(struct bxe_softc *sc,
10574 uint8_t state)
10575 {
10576 uint16_t pmcsr;
10577
10578 /* If there is no power capability, silently succeed */
10579 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) {
10580 BLOGW(sc, "No power capability\n");
10581 return (0);
10582 }
10583
10584 pmcsr = pci_read_config(sc->dev,
10585 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10586 2);
10587
10588 switch (state) {
10589 case PCI_PM_D0:
10590 pci_write_config(sc->dev,
10591 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10592 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2);
10593
10594 if (pmcsr & PCIM_PSTAT_DMASK) {
10595 /* delay required during transition out of D3hot */
10596 DELAY(20000);
10597 }
10598
10599 break;
10600
10601 case PCI_PM_D3hot:
10602 /* XXX if there are other clients above don't shut down the power */
10603
10604 /* don't shut down the power for emulation and FPGA */
10605 if (CHIP_REV_IS_SLOW(sc)) {
10606 return (0);
10607 }
10608
10609 pmcsr &= ~PCIM_PSTAT_DMASK;
10610 pmcsr |= PCIM_PSTAT_D3;
10611
10612 if (sc->wol) {
10613 pmcsr |= PCIM_PSTAT_PMEENABLE;
10614 }
10615
10616 pci_write_config(sc->dev,
10617 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10618 pmcsr, 4);
10619
10620 /*
10621 * No more memory access after this point until device is brought back
10622 * to D0 state.
10623 */
10624 break;
10625
10626 default:
10627 BLOGE(sc, "Can't support PCI power state = 0x%x pmcsr 0x%x\n",
10628 state, pmcsr);
10629 return (-1);
10630 }
10631
10632 return (0);
10633 }
10634
10635
10636 /* return true if succeeded to acquire the lock */
10637 static uint8_t
bxe_trylock_hw_lock(struct bxe_softc * sc,uint32_t resource)10638 bxe_trylock_hw_lock(struct bxe_softc *sc,
10639 uint32_t resource)
10640 {
10641 uint32_t lock_status;
10642 uint32_t resource_bit = (1 << resource);
10643 int func = SC_FUNC(sc);
10644 uint32_t hw_lock_control_reg;
10645
10646 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource);
10647
10648 /* Validating that the resource is within range */
10649 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
10650 BLOGD(sc, DBG_LOAD,
10651 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
10652 resource, HW_LOCK_MAX_RESOURCE_VALUE);
10653 return (FALSE);
10654 }
10655
10656 if (func <= 5) {
10657 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
10658 } else {
10659 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
10660 }
10661
10662 /* try to acquire the lock */
10663 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
10664 lock_status = REG_RD(sc, hw_lock_control_reg);
10665 if (lock_status & resource_bit) {
10666 return (TRUE);
10667 }
10668
10669 BLOGE(sc, "Failed to get a resource lock 0x%x func %d "
10670 "lock_status 0x%x resource_bit 0x%x\n", resource, func,
10671 lock_status, resource_bit);
10672
10673 return (FALSE);
10674 }
10675
10676 /*
10677 * Get the recovery leader resource id according to the engine this function
10678 * belongs to. Currently only only 2 engines is supported.
10679 */
10680 static int
bxe_get_leader_lock_resource(struct bxe_softc * sc)10681 bxe_get_leader_lock_resource(struct bxe_softc *sc)
10682 {
10683 if (SC_PATH(sc)) {
10684 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1);
10685 } else {
10686 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0);
10687 }
10688 }
10689
10690 /* try to acquire a leader lock for current engine */
10691 static uint8_t
bxe_trylock_leader_lock(struct bxe_softc * sc)10692 bxe_trylock_leader_lock(struct bxe_softc *sc)
10693 {
10694 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10695 }
10696
10697 static int
bxe_release_leader_lock(struct bxe_softc * sc)10698 bxe_release_leader_lock(struct bxe_softc *sc)
10699 {
10700 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10701 }
10702
10703 /* close gates #2, #3 and #4 */
10704 static void
bxe_set_234_gates(struct bxe_softc * sc,uint8_t close)10705 bxe_set_234_gates(struct bxe_softc *sc,
10706 uint8_t close)
10707 {
10708 uint32_t val;
10709
10710 /* gates #2 and #4a are closed/opened for "not E1" only */
10711 if (!CHIP_IS_E1(sc)) {
10712 /* #4 */
10713 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
10714 /* #2 */
10715 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
10716 }
10717
10718 /* #3 */
10719 if (CHIP_IS_E1x(sc)) {
10720 /* prevent interrupts from HC on both ports */
10721 val = REG_RD(sc, HC_REG_CONFIG_1);
10722 REG_WR(sc, HC_REG_CONFIG_1,
10723 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
10724 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
10725
10726 val = REG_RD(sc, HC_REG_CONFIG_0);
10727 REG_WR(sc, HC_REG_CONFIG_0,
10728 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
10729 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
10730 } else {
10731 /* Prevent incoming interrupts in IGU */
10732 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
10733
10734 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
10735 (!close) ?
10736 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
10737 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
10738 }
10739
10740 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n",
10741 close ? "closing" : "opening");
10742
10743 wmb();
10744 }
10745
10746 /* poll for pending writes bit, it should get cleared in no more than 1s */
10747 static int
bxe_er_poll_igu_vq(struct bxe_softc * sc)10748 bxe_er_poll_igu_vq(struct bxe_softc *sc)
10749 {
10750 uint32_t cnt = 1000;
10751 uint32_t pend_bits = 0;
10752
10753 do {
10754 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
10755
10756 if (pend_bits == 0) {
10757 break;
10758 }
10759
10760 DELAY(1000);
10761 } while (--cnt > 0);
10762
10763 if (cnt == 0) {
10764 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits);
10765 return (-1);
10766 }
10767
10768 return (0);
10769 }
10770
10771 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
10772
10773 static void
bxe_clp_reset_prep(struct bxe_softc * sc,uint32_t * magic_val)10774 bxe_clp_reset_prep(struct bxe_softc *sc,
10775 uint32_t *magic_val)
10776 {
10777 /* Do some magic... */
10778 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10779 *magic_val = val & SHARED_MF_CLP_MAGIC;
10780 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
10781 }
10782
10783 /* restore the value of the 'magic' bit */
10784 static void
bxe_clp_reset_done(struct bxe_softc * sc,uint32_t magic_val)10785 bxe_clp_reset_done(struct bxe_softc *sc,
10786 uint32_t magic_val)
10787 {
10788 /* Restore the 'magic' bit value... */
10789 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10790 MFCFG_WR(sc, shared_mf_config.clp_mb,
10791 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
10792 }
10793
10794 /* prepare for MCP reset, takes care of CLP configurations */
10795 static void
bxe_reset_mcp_prep(struct bxe_softc * sc,uint32_t * magic_val)10796 bxe_reset_mcp_prep(struct bxe_softc *sc,
10797 uint32_t *magic_val)
10798 {
10799 uint32_t shmem;
10800 uint32_t validity_offset;
10801
10802 /* set `magic' bit in order to save MF config */
10803 if (!CHIP_IS_E1(sc)) {
10804 bxe_clp_reset_prep(sc, magic_val);
10805 }
10806
10807 /* get shmem offset */
10808 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10809 validity_offset =
10810 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
10811
10812 /* Clear validity map flags */
10813 if (shmem > 0) {
10814 REG_WR(sc, shmem + validity_offset, 0);
10815 }
10816 }
10817
10818 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
10819 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
10820
10821 static void
bxe_mcp_wait_one(struct bxe_softc * sc)10822 bxe_mcp_wait_one(struct bxe_softc *sc)
10823 {
10824 /* special handling for emulation and FPGA (10 times longer) */
10825 if (CHIP_REV_IS_SLOW(sc)) {
10826 DELAY((MCP_ONE_TIMEOUT*10) * 1000);
10827 } else {
10828 DELAY((MCP_ONE_TIMEOUT) * 1000);
10829 }
10830 }
10831
10832 /* initialize shmem_base and waits for validity signature to appear */
10833 static int
bxe_init_shmem(struct bxe_softc * sc)10834 bxe_init_shmem(struct bxe_softc *sc)
10835 {
10836 int cnt = 0;
10837 uint32_t val = 0;
10838
10839 do {
10840 sc->devinfo.shmem_base =
10841 sc->link_params.shmem_base =
10842 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10843
10844 if (sc->devinfo.shmem_base) {
10845 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
10846 if (val & SHR_MEM_VALIDITY_MB)
10847 return (0);
10848 }
10849
10850 bxe_mcp_wait_one(sc);
10851
10852 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
10853
10854 BLOGE(sc, "BAD MCP validity signature\n");
10855
10856 return (-1);
10857 }
10858
10859 static int
bxe_reset_mcp_comp(struct bxe_softc * sc,uint32_t magic_val)10860 bxe_reset_mcp_comp(struct bxe_softc *sc,
10861 uint32_t magic_val)
10862 {
10863 int rc = bxe_init_shmem(sc);
10864
10865 /* Restore the `magic' bit value */
10866 if (!CHIP_IS_E1(sc)) {
10867 bxe_clp_reset_done(sc, magic_val);
10868 }
10869
10870 return (rc);
10871 }
10872
10873 static void
bxe_pxp_prep(struct bxe_softc * sc)10874 bxe_pxp_prep(struct bxe_softc *sc)
10875 {
10876 if (!CHIP_IS_E1(sc)) {
10877 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
10878 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
10879 wmb();
10880 }
10881 }
10882
10883 /*
10884 * Reset the whole chip except for:
10885 * - PCIE core
10886 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
10887 * - IGU
10888 * - MISC (including AEU)
10889 * - GRC
10890 * - RBCN, RBCP
10891 */
10892 static void
bxe_process_kill_chip_reset(struct bxe_softc * sc,uint8_t global)10893 bxe_process_kill_chip_reset(struct bxe_softc *sc,
10894 uint8_t global)
10895 {
10896 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
10897 uint32_t global_bits2, stay_reset2;
10898
10899 /*
10900 * Bits that have to be set in reset_mask2 if we want to reset 'global'
10901 * (per chip) blocks.
10902 */
10903 global_bits2 =
10904 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
10905 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
10906
10907 /*
10908 * Don't reset the following blocks.
10909 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
10910 * reset, as in 4 port device they might still be owned
10911 * by the MCP (there is only one leader per path).
10912 */
10913 not_reset_mask1 =
10914 MISC_REGISTERS_RESET_REG_1_RST_HC |
10915 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
10916 MISC_REGISTERS_RESET_REG_1_RST_PXP;
10917
10918 not_reset_mask2 =
10919 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
10920 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
10921 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
10922 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
10923 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
10924 MISC_REGISTERS_RESET_REG_2_RST_GRC |
10925 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
10926 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
10927 MISC_REGISTERS_RESET_REG_2_RST_ATC |
10928 MISC_REGISTERS_RESET_REG_2_PGLC |
10929 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
10930 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
10931 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
10932 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
10933 MISC_REGISTERS_RESET_REG_2_UMAC0 |
10934 MISC_REGISTERS_RESET_REG_2_UMAC1;
10935
10936 /*
10937 * Keep the following blocks in reset:
10938 * - all xxMACs are handled by the elink code.
10939 */
10940 stay_reset2 =
10941 MISC_REGISTERS_RESET_REG_2_XMAC |
10942 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
10943
10944 /* Full reset masks according to the chip */
10945 reset_mask1 = 0xffffffff;
10946
10947 if (CHIP_IS_E1(sc))
10948 reset_mask2 = 0xffff;
10949 else if (CHIP_IS_E1H(sc))
10950 reset_mask2 = 0x1ffff;
10951 else if (CHIP_IS_E2(sc))
10952 reset_mask2 = 0xfffff;
10953 else /* CHIP_IS_E3 */
10954 reset_mask2 = 0x3ffffff;
10955
10956 /* Don't reset global blocks unless we need to */
10957 if (!global)
10958 reset_mask2 &= ~global_bits2;
10959
10960 /*
10961 * In case of attention in the QM, we need to reset PXP
10962 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
10963 * because otherwise QM reset would release 'close the gates' shortly
10964 * before resetting the PXP, then the PSWRQ would send a write
10965 * request to PGLUE. Then when PXP is reset, PGLUE would try to
10966 * read the payload data from PSWWR, but PSWWR would not
10967 * respond. The write queue in PGLUE would stuck, dmae commands
10968 * would not return. Therefore it's important to reset the second
10969 * reset register (containing the
10970 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
10971 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
10972 * bit).
10973 */
10974 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
10975 reset_mask2 & (~not_reset_mask2));
10976
10977 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
10978 reset_mask1 & (~not_reset_mask1));
10979
10980 mb();
10981 wmb();
10982
10983 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
10984 reset_mask2 & (~stay_reset2));
10985
10986 mb();
10987 wmb();
10988
10989 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
10990 wmb();
10991 }
10992
10993 static int
bxe_process_kill(struct bxe_softc * sc,uint8_t global)10994 bxe_process_kill(struct bxe_softc *sc,
10995 uint8_t global)
10996 {
10997 int cnt = 1000;
10998 uint32_t val = 0;
10999 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
11000 uint32_t tags_63_32 = 0;
11001
11002 /* Empty the Tetris buffer, wait for 1s */
11003 do {
11004 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
11005 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
11006 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
11007 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
11008 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
11009 if (CHIP_IS_E3(sc)) {
11010 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
11011 }
11012
11013 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
11014 ((port_is_idle_0 & 0x1) == 0x1) &&
11015 ((port_is_idle_1 & 0x1) == 0x1) &&
11016 (pgl_exp_rom2 == 0xffffffff) &&
11017 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
11018 break;
11019 DELAY(1000);
11020 } while (cnt-- > 0);
11021
11022 if (cnt <= 0) {
11023 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there "
11024 "are still outstanding read requests after 1s! "
11025 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
11026 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
11027 sr_cnt, blk_cnt, port_is_idle_0,
11028 port_is_idle_1, pgl_exp_rom2);
11029 return (-1);
11030 }
11031
11032 mb();
11033
11034 /* Close gates #2, #3 and #4 */
11035 bxe_set_234_gates(sc, TRUE);
11036
11037 /* Poll for IGU VQs for 57712 and newer chips */
11038 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) {
11039 return (-1);
11040 }
11041
11042 /* XXX indicate that "process kill" is in progress to MCP */
11043
11044 /* clear "unprepared" bit */
11045 REG_WR(sc, MISC_REG_UNPREPARED, 0);
11046 mb();
11047
11048 /* Make sure all is written to the chip before the reset */
11049 wmb();
11050
11051 /*
11052 * Wait for 1ms to empty GLUE and PCI-E core queues,
11053 * PSWHST, GRC and PSWRD Tetris buffer.
11054 */
11055 DELAY(1000);
11056
11057 /* Prepare to chip reset: */
11058 /* MCP */
11059 if (global) {
11060 bxe_reset_mcp_prep(sc, &val);
11061 }
11062
11063 /* PXP */
11064 bxe_pxp_prep(sc);
11065 mb();
11066
11067 /* reset the chip */
11068 bxe_process_kill_chip_reset(sc, global);
11069 mb();
11070
11071 /* clear errors in PGB */
11072 if (!CHIP_IS_E1(sc))
11073 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
11074
11075 /* Recover after reset: */
11076 /* MCP */
11077 if (global && bxe_reset_mcp_comp(sc, val)) {
11078 return (-1);
11079 }
11080
11081 /* XXX add resetting the NO_MCP mode DB here */
11082
11083 /* Open the gates #2, #3 and #4 */
11084 bxe_set_234_gates(sc, FALSE);
11085
11086 /* XXX
11087 * IGU/AEU preparation bring back the AEU/IGU to a reset state
11088 * re-enable attentions
11089 */
11090
11091 return (0);
11092 }
11093
11094 static int
bxe_leader_reset(struct bxe_softc * sc)11095 bxe_leader_reset(struct bxe_softc *sc)
11096 {
11097 int rc = 0;
11098 uint8_t global = bxe_reset_is_global(sc);
11099 uint32_t load_code;
11100
11101 /*
11102 * If not going to reset MCP, load "fake" driver to reset HW while
11103 * driver is owner of the HW.
11104 */
11105 if (!global && !BXE_NOMCP(sc)) {
11106 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
11107 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
11108 if (!load_code) {
11109 BLOGE(sc, "MCP response failure, aborting\n");
11110 rc = -1;
11111 goto exit_leader_reset;
11112 }
11113
11114 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
11115 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
11116 BLOGE(sc, "MCP unexpected response, aborting\n");
11117 rc = -1;
11118 goto exit_leader_reset2;
11119 }
11120
11121 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
11122 if (!load_code) {
11123 BLOGE(sc, "MCP response failure, aborting\n");
11124 rc = -1;
11125 goto exit_leader_reset2;
11126 }
11127 }
11128
11129 /* try to recover after the failure */
11130 if (bxe_process_kill(sc, global)) {
11131 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc));
11132 rc = -1;
11133 goto exit_leader_reset2;
11134 }
11135
11136 /*
11137 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
11138 * state.
11139 */
11140 bxe_set_reset_done(sc);
11141 if (global) {
11142 bxe_clear_reset_global(sc);
11143 }
11144
11145 exit_leader_reset2:
11146
11147 /* unload "fake driver" if it was loaded */
11148 if (!global && !BXE_NOMCP(sc)) {
11149 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
11150 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
11151 }
11152
11153 exit_leader_reset:
11154
11155 sc->is_leader = 0;
11156 bxe_release_leader_lock(sc);
11157
11158 mb();
11159 return (rc);
11160 }
11161
11162 /*
11163 * prepare INIT transition, parameters configured:
11164 * - HC configuration
11165 * - Queue's CDU context
11166 */
11167 static void
bxe_pf_q_prep_init(struct bxe_softc * sc,struct bxe_fastpath * fp,struct ecore_queue_init_params * init_params)11168 bxe_pf_q_prep_init(struct bxe_softc *sc,
11169 struct bxe_fastpath *fp,
11170 struct ecore_queue_init_params *init_params)
11171 {
11172 uint8_t cos;
11173 int cxt_index, cxt_offset;
11174
11175 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
11176 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
11177
11178 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
11179 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
11180
11181 /* HC rate */
11182 init_params->rx.hc_rate =
11183 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
11184 init_params->tx.hc_rate =
11185 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
11186
11187 /* FW SB ID */
11188 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
11189
11190 /* CQ index among the SB indices */
11191 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11192 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
11193
11194 /* set maximum number of COSs supported by this queue */
11195 init_params->max_cos = sc->max_cos;
11196
11197 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n",
11198 fp->index, init_params->max_cos);
11199
11200 /* set the context pointers queue object */
11201 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
11202 /* XXX change index/cid here if ever support multiple tx CoS */
11203 /* fp->txdata[cos]->cid */
11204 cxt_index = fp->index / ILT_PAGE_CIDS;
11205 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
11206 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth;
11207 }
11208 }
11209
11210 /* set flags that are common for the Tx-only and not normal connections */
11211 static unsigned long
bxe_get_common_flags(struct bxe_softc * sc,struct bxe_fastpath * fp,uint8_t zero_stats)11212 bxe_get_common_flags(struct bxe_softc *sc,
11213 struct bxe_fastpath *fp,
11214 uint8_t zero_stats)
11215 {
11216 unsigned long flags = 0;
11217
11218 /* PF driver will always initialize the Queue to an ACTIVE state */
11219 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
11220
11221 /*
11222 * tx only connections collect statistics (on the same index as the
11223 * parent connection). The statistics are zeroed when the parent
11224 * connection is initialized.
11225 */
11226
11227 bxe_set_bit(ECORE_Q_FLG_STATS, &flags);
11228 if (zero_stats) {
11229 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
11230 }
11231
11232 /*
11233 * tx only connections can support tx-switching, though their
11234 * CoS-ness doesn't survive the loopback
11235 */
11236 if (sc->flags & BXE_TX_SWITCHING) {
11237 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
11238 }
11239
11240 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
11241
11242 return (flags);
11243 }
11244
11245 static unsigned long
bxe_get_q_flags(struct bxe_softc * sc,struct bxe_fastpath * fp,uint8_t leading)11246 bxe_get_q_flags(struct bxe_softc *sc,
11247 struct bxe_fastpath *fp,
11248 uint8_t leading)
11249 {
11250 unsigned long flags = 0;
11251
11252 if (IS_MF_SD(sc)) {
11253 bxe_set_bit(ECORE_Q_FLG_OV, &flags);
11254 }
11255
11256 if (if_getcapenable(sc->ifp) & IFCAP_LRO) {
11257 bxe_set_bit(ECORE_Q_FLG_TPA, &flags);
11258 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags);
11259 }
11260
11261 if (leading) {
11262 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
11263 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags);
11264 }
11265
11266 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags);
11267
11268 /* merge with common flags */
11269 return (flags | bxe_get_common_flags(sc, fp, TRUE));
11270 }
11271
11272 static void
bxe_pf_q_prep_general(struct bxe_softc * sc,struct bxe_fastpath * fp,struct ecore_general_setup_params * gen_init,uint8_t cos)11273 bxe_pf_q_prep_general(struct bxe_softc *sc,
11274 struct bxe_fastpath *fp,
11275 struct ecore_general_setup_params *gen_init,
11276 uint8_t cos)
11277 {
11278 gen_init->stat_id = bxe_stats_id(fp);
11279 gen_init->spcl_id = fp->cl_id;
11280 gen_init->mtu = sc->mtu;
11281 gen_init->cos = cos;
11282 }
11283
11284 static void
bxe_pf_rx_q_prep(struct bxe_softc * sc,struct bxe_fastpath * fp,struct rxq_pause_params * pause,struct ecore_rxq_setup_params * rxq_init)11285 bxe_pf_rx_q_prep(struct bxe_softc *sc,
11286 struct bxe_fastpath *fp,
11287 struct rxq_pause_params *pause,
11288 struct ecore_rxq_setup_params *rxq_init)
11289 {
11290 uint8_t max_sge = 0;
11291 uint16_t sge_sz = 0;
11292 uint16_t tpa_agg_size = 0;
11293
11294 pause->sge_th_lo = SGE_TH_LO(sc);
11295 pause->sge_th_hi = SGE_TH_HI(sc);
11296
11297 /* validate SGE ring has enough to cross high threshold */
11298 if (sc->dropless_fc &&
11299 (pause->sge_th_hi + FW_PREFETCH_CNT) >
11300 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) {
11301 BLOGW(sc, "sge ring threshold limit\n");
11302 }
11303
11304 /* minimum max_aggregation_size is 2*MTU (two full buffers) */
11305 tpa_agg_size = (2 * sc->mtu);
11306 if (tpa_agg_size < sc->max_aggregation_size) {
11307 tpa_agg_size = sc->max_aggregation_size;
11308 }
11309
11310 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT;
11311 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
11312 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
11313 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff);
11314
11315 /* pause - not for e1 */
11316 if (!CHIP_IS_E1(sc)) {
11317 pause->bd_th_lo = BD_TH_LO(sc);
11318 pause->bd_th_hi = BD_TH_HI(sc);
11319
11320 pause->rcq_th_lo = RCQ_TH_LO(sc);
11321 pause->rcq_th_hi = RCQ_TH_HI(sc);
11322
11323 /* validate rings have enough entries to cross high thresholds */
11324 if (sc->dropless_fc &&
11325 pause->bd_th_hi + FW_PREFETCH_CNT >
11326 sc->rx_ring_size) {
11327 BLOGW(sc, "rx bd ring threshold limit\n");
11328 }
11329
11330 if (sc->dropless_fc &&
11331 pause->rcq_th_hi + FW_PREFETCH_CNT >
11332 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) {
11333 BLOGW(sc, "rcq ring threshold limit\n");
11334 }
11335
11336 pause->pri_map = 1;
11337 }
11338
11339 /* rxq setup */
11340 rxq_init->dscr_map = fp->rx_dma.paddr;
11341 rxq_init->sge_map = fp->rx_sge_dma.paddr;
11342 rxq_init->rcq_map = fp->rcq_dma.paddr;
11343 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE);
11344
11345 /*
11346 * This should be a maximum number of data bytes that may be
11347 * placed on the BD (not including paddings).
11348 */
11349 rxq_init->buf_sz = (fp->rx_buf_size -
11350 IP_HEADER_ALIGNMENT_PADDING);
11351
11352 rxq_init->cl_qzone_id = fp->cl_qzone_id;
11353 rxq_init->tpa_agg_sz = tpa_agg_size;
11354 rxq_init->sge_buf_sz = sge_sz;
11355 rxq_init->max_sges_pkt = max_sge;
11356 rxq_init->rss_engine_id = SC_FUNC(sc);
11357 rxq_init->mcast_engine_id = SC_FUNC(sc);
11358
11359 /*
11360 * Maximum number or simultaneous TPA aggregation for this Queue.
11361 * For PF Clients it should be the maximum available number.
11362 * VF driver(s) may want to define it to a smaller value.
11363 */
11364 rxq_init->max_tpa_queues = MAX_AGG_QS(sc);
11365
11366 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT;
11367 rxq_init->fw_sb_id = fp->fw_sb_id;
11368
11369 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11370
11371 /*
11372 * configure silent vlan removal
11373 * if multi function mode is afex, then mask default vlan
11374 */
11375 if (IS_MF_AFEX(sc)) {
11376 rxq_init->silent_removal_value =
11377 sc->devinfo.mf_info.afex_def_vlan_tag;
11378 rxq_init->silent_removal_mask = EVL_VLID_MASK;
11379 }
11380 }
11381
11382 static void
bxe_pf_tx_q_prep(struct bxe_softc * sc,struct bxe_fastpath * fp,struct ecore_txq_setup_params * txq_init,uint8_t cos)11383 bxe_pf_tx_q_prep(struct bxe_softc *sc,
11384 struct bxe_fastpath *fp,
11385 struct ecore_txq_setup_params *txq_init,
11386 uint8_t cos)
11387 {
11388 /*
11389 * XXX If multiple CoS is ever supported then each fastpath structure
11390 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
11391 * fp->txdata[cos]->tx_dma.paddr;
11392 */
11393 txq_init->dscr_map = fp->tx_dma.paddr;
11394 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
11395 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
11396 txq_init->fw_sb_id = fp->fw_sb_id;
11397
11398 /*
11399 * set the TSS leading client id for TX classfication to the
11400 * leading RSS client id
11401 */
11402 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id);
11403 }
11404
11405 /*
11406 * This function performs 2 steps in a queue state machine:
11407 * 1) RESET->INIT
11408 * 2) INIT->SETUP
11409 */
11410 static int
bxe_setup_queue(struct bxe_softc * sc,struct bxe_fastpath * fp,uint8_t leading)11411 bxe_setup_queue(struct bxe_softc *sc,
11412 struct bxe_fastpath *fp,
11413 uint8_t leading)
11414 {
11415 struct ecore_queue_state_params q_params = { NULL };
11416 struct ecore_queue_setup_params *setup_params =
11417 &q_params.params.setup;
11418 int rc;
11419
11420 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index);
11421
11422 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
11423
11424 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
11425
11426 /* we want to wait for completion in this context */
11427 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
11428
11429 /* prepare the INIT parameters */
11430 bxe_pf_q_prep_init(sc, fp, &q_params.params.init);
11431
11432 /* Set the command */
11433 q_params.cmd = ECORE_Q_CMD_INIT;
11434
11435 /* Change the state to INIT */
11436 rc = ecore_queue_state_change(sc, &q_params);
11437 if (rc) {
11438 BLOGE(sc, "Queue(%d) INIT failed rc = %d\n", fp->index, rc);
11439 return (rc);
11440 }
11441
11442 BLOGD(sc, DBG_LOAD, "init complete\n");
11443
11444 /* now move the Queue to the SETUP state */
11445 memset(setup_params, 0, sizeof(*setup_params));
11446
11447 /* set Queue flags */
11448 setup_params->flags = bxe_get_q_flags(sc, fp, leading);
11449
11450 /* set general SETUP parameters */
11451 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params,
11452 FIRST_TX_COS_INDEX);
11453
11454 bxe_pf_rx_q_prep(sc, fp,
11455 &setup_params->pause_params,
11456 &setup_params->rxq_params);
11457
11458 bxe_pf_tx_q_prep(sc, fp,
11459 &setup_params->txq_params,
11460 FIRST_TX_COS_INDEX);
11461
11462 /* Set the command */
11463 q_params.cmd = ECORE_Q_CMD_SETUP;
11464
11465 /* change the state to SETUP */
11466 rc = ecore_queue_state_change(sc, &q_params);
11467 if (rc) {
11468 BLOGE(sc, "Queue(%d) SETUP failed (rc = %d)\n", fp->index, rc);
11469 return (rc);
11470 }
11471
11472 return (rc);
11473 }
11474
11475 static int
bxe_setup_leading(struct bxe_softc * sc)11476 bxe_setup_leading(struct bxe_softc *sc)
11477 {
11478 return (bxe_setup_queue(sc, &sc->fp[0], TRUE));
11479 }
11480
11481 static int
bxe_config_rss_pf(struct bxe_softc * sc,struct ecore_rss_config_obj * rss_obj,uint8_t config_hash)11482 bxe_config_rss_pf(struct bxe_softc *sc,
11483 struct ecore_rss_config_obj *rss_obj,
11484 uint8_t config_hash)
11485 {
11486 struct ecore_config_rss_params params = { NULL };
11487
11488 /*
11489 * Although RSS is meaningless when there is a single HW queue we
11490 * still need it enabled in order to have HW Rx hash generated.
11491 */
11492
11493 params.rss_obj = rss_obj;
11494
11495 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
11496
11497 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
11498
11499 /* RSS configuration */
11500 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
11501 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
11502 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
11503 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
11504 if (rss_obj->udp_rss_v4) {
11505 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
11506 }
11507 if (rss_obj->udp_rss_v6) {
11508 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
11509 }
11510
11511 /* Hash bits */
11512 params.rss_result_mask = MULTI_MASK;
11513
11514 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
11515
11516 if (config_hash) {
11517 uint8_t key[RSS_KEYSIZE];
11518 unsigned int i;
11519
11520 /* The searcher consumes the key in reverse byte order. */
11521 _Static_assert(sizeof(params.rss_key) == RSS_KEYSIZE,
11522 "RSS key size mismatch");
11523 rss_getkey(key);
11524 for (i = 0; i < sizeof(key); i++)
11525 ((uint8_t *)params.rss_key)[sizeof(key) - 1 - i] = key[i];
11526
11527 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
11528 }
11529
11530 return (ecore_config_rss(sc, ¶ms));
11531 }
11532
11533 static int
bxe_config_rss_eth(struct bxe_softc * sc,uint8_t config_hash)11534 bxe_config_rss_eth(struct bxe_softc *sc,
11535 uint8_t config_hash)
11536 {
11537 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash));
11538 }
11539
11540 static int
bxe_init_rss_pf(struct bxe_softc * sc)11541 bxe_init_rss_pf(struct bxe_softc *sc)
11542 {
11543 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc);
11544 int i;
11545
11546 /*
11547 * Prepare the initial contents of the indirection table if
11548 * RSS is enabled
11549 */
11550 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
11551 sc->rss_conf_obj.ind_table[i] =
11552 (sc->fp->cl_id + (i % num_eth_queues));
11553 }
11554
11555 if (sc->udp_rss) {
11556 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
11557 }
11558
11559 /*
11560 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
11561 * per-port, so if explicit configuration is needed, do it only
11562 * for a PMF.
11563 *
11564 * For 57712 and newer it's a per-function configuration.
11565 */
11566 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc)));
11567 }
11568
11569 static int
bxe_set_mac_one(struct bxe_softc * sc,uint8_t * mac,struct ecore_vlan_mac_obj * obj,uint8_t set,int mac_type,unsigned long * ramrod_flags)11570 bxe_set_mac_one(struct bxe_softc *sc,
11571 uint8_t *mac,
11572 struct ecore_vlan_mac_obj *obj,
11573 uint8_t set,
11574 int mac_type,
11575 unsigned long *ramrod_flags)
11576 {
11577 struct ecore_vlan_mac_ramrod_params ramrod_param;
11578 int rc;
11579
11580 memset(&ramrod_param, 0, sizeof(ramrod_param));
11581
11582 /* fill in general parameters */
11583 ramrod_param.vlan_mac_obj = obj;
11584 ramrod_param.ramrod_flags = *ramrod_flags;
11585
11586 /* fill a user request section if needed */
11587 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) {
11588 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
11589
11590 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
11591
11592 /* Set the command: ADD or DEL */
11593 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
11594 ECORE_VLAN_MAC_DEL;
11595 }
11596
11597 rc = ecore_config_vlan_mac(sc, &ramrod_param);
11598
11599 if (rc == ECORE_EXISTS) {
11600 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
11601 /* do not treat adding same MAC as error */
11602 rc = 0;
11603 } else if (rc < 0) {
11604 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc);
11605 }
11606
11607 return (rc);
11608 }
11609
11610 static int
bxe_set_eth_mac(struct bxe_softc * sc,uint8_t set)11611 bxe_set_eth_mac(struct bxe_softc *sc,
11612 uint8_t set)
11613 {
11614 unsigned long ramrod_flags = 0;
11615
11616 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n");
11617
11618 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11619
11620 /* Eth MAC is set on RSS leading client (fp[0]) */
11621 return (bxe_set_mac_one(sc, sc->link_params.mac_addr,
11622 &sc->sp_objs->mac_obj,
11623 set, ECORE_ETH_MAC, &ramrod_flags));
11624 }
11625
11626 static int
bxe_get_cur_phy_idx(struct bxe_softc * sc)11627 bxe_get_cur_phy_idx(struct bxe_softc *sc)
11628 {
11629 uint32_t sel_phy_idx = 0;
11630
11631 if (sc->link_params.num_phys <= 1) {
11632 return (ELINK_INT_PHY);
11633 }
11634
11635 if (sc->link_vars.link_up) {
11636 sel_phy_idx = ELINK_EXT_PHY1;
11637 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
11638 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
11639 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
11640 ELINK_SUPPORTED_FIBRE))
11641 sel_phy_idx = ELINK_EXT_PHY2;
11642 } else {
11643 switch (elink_phy_selection(&sc->link_params)) {
11644 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
11645 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11646 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11647 sel_phy_idx = ELINK_EXT_PHY1;
11648 break;
11649 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11650 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11651 sel_phy_idx = ELINK_EXT_PHY2;
11652 break;
11653 }
11654 }
11655
11656 return (sel_phy_idx);
11657 }
11658
11659 static int
bxe_get_link_cfg_idx(struct bxe_softc * sc)11660 bxe_get_link_cfg_idx(struct bxe_softc *sc)
11661 {
11662 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc);
11663
11664 /*
11665 * The selected activated PHY is always after swapping (in case PHY
11666 * swapping is enabled). So when swapping is enabled, we need to reverse
11667 * the configuration
11668 */
11669
11670 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11671 if (sel_phy_idx == ELINK_EXT_PHY1)
11672 sel_phy_idx = ELINK_EXT_PHY2;
11673 else if (sel_phy_idx == ELINK_EXT_PHY2)
11674 sel_phy_idx = ELINK_EXT_PHY1;
11675 }
11676
11677 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx));
11678 }
11679
11680 static void
bxe_set_requested_fc(struct bxe_softc * sc)11681 bxe_set_requested_fc(struct bxe_softc *sc)
11682 {
11683 /*
11684 * Initialize link parameters structure variables
11685 * It is recommended to turn off RX FC for jumbo frames
11686 * for better performance
11687 */
11688 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
11689 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
11690 } else {
11691 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
11692 }
11693 }
11694
11695 static void
bxe_calc_fc_adv(struct bxe_softc * sc)11696 bxe_calc_fc_adv(struct bxe_softc *sc)
11697 {
11698 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc);
11699
11700
11701 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
11702 ADVERTISED_Pause);
11703
11704 switch (sc->link_vars.ieee_fc &
11705 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
11706
11707 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
11708 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
11709 ADVERTISED_Pause);
11710 break;
11711
11712 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
11713 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
11714 break;
11715
11716 default:
11717 break;
11718
11719 }
11720 }
11721
11722 static uint16_t
bxe_get_mf_speed(struct bxe_softc * sc)11723 bxe_get_mf_speed(struct bxe_softc *sc)
11724 {
11725 uint16_t line_speed = sc->link_vars.line_speed;
11726 if (IS_MF(sc)) {
11727 uint16_t maxCfg =
11728 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]);
11729
11730 /* calculate the current MAX line speed limit for the MF devices */
11731 if (IS_MF_SI(sc)) {
11732 line_speed = (line_speed * maxCfg) / 100;
11733 } else { /* SD mode */
11734 uint16_t vn_max_rate = maxCfg * 100;
11735
11736 if (vn_max_rate < line_speed) {
11737 line_speed = vn_max_rate;
11738 }
11739 }
11740 }
11741
11742 return (line_speed);
11743 }
11744
11745 static void
bxe_fill_report_data(struct bxe_softc * sc,struct bxe_link_report_data * data)11746 bxe_fill_report_data(struct bxe_softc *sc,
11747 struct bxe_link_report_data *data)
11748 {
11749 uint16_t line_speed = bxe_get_mf_speed(sc);
11750
11751 memset(data, 0, sizeof(*data));
11752
11753 /* fill the report data with the effective line speed */
11754 data->line_speed = line_speed;
11755
11756 /* Link is down */
11757 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) {
11758 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags);
11759 }
11760
11761 /* Full DUPLEX */
11762 if (sc->link_vars.duplex == DUPLEX_FULL) {
11763 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags);
11764 }
11765
11766 /* Rx Flow Control is ON */
11767 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
11768 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
11769 }
11770
11771 /* Tx Flow Control is ON */
11772 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
11773 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
11774 }
11775 }
11776
11777 /* report link status to OS, should be called under phy_lock */
11778 static void
bxe_link_report_locked(struct bxe_softc * sc)11779 bxe_link_report_locked(struct bxe_softc *sc)
11780 {
11781 struct bxe_link_report_data cur_data;
11782
11783 /* reread mf_cfg */
11784 if (IS_PF(sc) && !CHIP_IS_E1(sc)) {
11785 bxe_read_mf_cfg(sc);
11786 }
11787
11788 /* Read the current link report info */
11789 bxe_fill_report_data(sc, &cur_data);
11790
11791 /* Don't report link down or exactly the same link status twice */
11792 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
11793 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11794 &sc->last_reported_link.link_report_flags) &&
11795 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11796 &cur_data.link_report_flags))) {
11797 return;
11798 }
11799
11800 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x\n",
11801 cur_data.link_report_flags, sc->last_reported_link.link_report_flags);
11802 sc->link_cnt++;
11803
11804 ELINK_DEBUG_P1(sc, "link status change count = %x\n", sc->link_cnt);
11805 /* report new link params and remember the state for the next time */
11806 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
11807
11808 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11809 &cur_data.link_report_flags)) {
11810 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
11811 } else {
11812 const char *duplex;
11813 const char *flow;
11814
11815 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX,
11816 &cur_data.link_report_flags)) {
11817 duplex = "full";
11818 ELINK_DEBUG_P0(sc, "link set to full duplex\n");
11819 } else {
11820 duplex = "half";
11821 ELINK_DEBUG_P0(sc, "link set to half duplex\n");
11822 }
11823
11824 /*
11825 * Handle the FC at the end so that only these flags would be
11826 * possibly set. This way we may easily check if there is no FC
11827 * enabled.
11828 */
11829 if (cur_data.link_report_flags) {
11830 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11831 &cur_data.link_report_flags) &&
11832 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11833 &cur_data.link_report_flags)) {
11834 flow = "ON - receive & transmit";
11835 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11836 &cur_data.link_report_flags) &&
11837 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11838 &cur_data.link_report_flags)) {
11839 flow = "ON - receive";
11840 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11841 &cur_data.link_report_flags) &&
11842 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11843 &cur_data.link_report_flags)) {
11844 flow = "ON - transmit";
11845 } else {
11846 flow = "none"; /* possible? */
11847 }
11848 } else {
11849 flow = "none";
11850 }
11851
11852 if_link_state_change(sc->ifp, LINK_STATE_UP);
11853 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
11854 cur_data.line_speed, duplex, flow);
11855 }
11856 }
11857
11858 static void
bxe_link_report(struct bxe_softc * sc)11859 bxe_link_report(struct bxe_softc *sc)
11860 {
11861 bxe_acquire_phy_lock(sc);
11862 bxe_link_report_locked(sc);
11863 bxe_release_phy_lock(sc);
11864 }
11865
11866 static void
bxe_link_status_update(struct bxe_softc * sc)11867 bxe_link_status_update(struct bxe_softc *sc)
11868 {
11869 if (sc->state != BXE_STATE_OPEN) {
11870 return;
11871 }
11872
11873 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
11874 elink_link_status_update(&sc->link_params, &sc->link_vars);
11875 } else {
11876 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
11877 ELINK_SUPPORTED_10baseT_Full |
11878 ELINK_SUPPORTED_100baseT_Half |
11879 ELINK_SUPPORTED_100baseT_Full |
11880 ELINK_SUPPORTED_1000baseT_Full |
11881 ELINK_SUPPORTED_2500baseX_Full |
11882 ELINK_SUPPORTED_10000baseT_Full |
11883 ELINK_SUPPORTED_TP |
11884 ELINK_SUPPORTED_FIBRE |
11885 ELINK_SUPPORTED_Autoneg |
11886 ELINK_SUPPORTED_Pause |
11887 ELINK_SUPPORTED_Asym_Pause);
11888 sc->port.advertising[0] = sc->port.supported[0];
11889
11890 sc->link_params.sc = sc;
11891 sc->link_params.port = SC_PORT(sc);
11892 sc->link_params.req_duplex[0] = DUPLEX_FULL;
11893 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
11894 sc->link_params.req_line_speed[0] = SPEED_10000;
11895 sc->link_params.speed_cap_mask[0] = 0x7f0000;
11896 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
11897
11898 if (CHIP_REV_IS_FPGA(sc)) {
11899 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
11900 sc->link_vars.line_speed = ELINK_SPEED_1000;
11901 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11902 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
11903 } else {
11904 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
11905 sc->link_vars.line_speed = ELINK_SPEED_10000;
11906 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11907 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
11908 }
11909
11910 sc->link_vars.link_up = 1;
11911
11912 sc->link_vars.duplex = DUPLEX_FULL;
11913 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
11914
11915 if (IS_PF(sc)) {
11916 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0);
11917 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11918 bxe_link_report(sc);
11919 }
11920 }
11921
11922 if (IS_PF(sc)) {
11923 if (sc->link_vars.link_up) {
11924 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11925 } else {
11926 bxe_stats_handle(sc, STATS_EVENT_STOP);
11927 }
11928 bxe_link_report(sc);
11929 } else {
11930 bxe_link_report(sc);
11931 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11932 }
11933 }
11934
11935 static int
bxe_initial_phy_init(struct bxe_softc * sc,int load_mode)11936 bxe_initial_phy_init(struct bxe_softc *sc,
11937 int load_mode)
11938 {
11939 int rc, cfg_idx = bxe_get_link_cfg_idx(sc);
11940 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
11941 struct elink_params *lp = &sc->link_params;
11942
11943 bxe_set_requested_fc(sc);
11944
11945 if (CHIP_REV_IS_SLOW(sc)) {
11946 uint32_t bond = CHIP_BOND_ID(sc);
11947 uint32_t feat = 0;
11948
11949 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
11950 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11951 } else if (bond & 0x4) {
11952 if (CHIP_IS_E3(sc)) {
11953 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
11954 } else {
11955 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11956 }
11957 } else if (bond & 0x8) {
11958 if (CHIP_IS_E3(sc)) {
11959 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
11960 } else {
11961 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
11962 }
11963 }
11964
11965 /* disable EMAC for E3 and above */
11966 if (bond & 0x2) {
11967 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
11968 }
11969
11970 sc->link_params.feature_config_flags |= feat;
11971 }
11972
11973 bxe_acquire_phy_lock(sc);
11974
11975 if (load_mode == LOAD_DIAG) {
11976 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
11977 /* Prefer doing PHY loopback at 10G speed, if possible */
11978 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
11979 if (lp->speed_cap_mask[cfg_idx] &
11980 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
11981 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
11982 } else {
11983 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
11984 }
11985 }
11986 }
11987
11988 if (load_mode == LOAD_LOOPBACK_EXT) {
11989 lp->loopback_mode = ELINK_LOOPBACK_EXT;
11990 }
11991
11992 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
11993
11994 bxe_release_phy_lock(sc);
11995
11996 bxe_calc_fc_adv(sc);
11997
11998 if (sc->link_vars.link_up) {
11999 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12000 bxe_link_report(sc);
12001 }
12002
12003 if (!CHIP_REV_IS_SLOW(sc)) {
12004 bxe_periodic_start(sc);
12005 }
12006
12007 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
12008 return (rc);
12009 }
12010
12011 static u_int
bxe_push_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)12012 bxe_push_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
12013 {
12014 struct ecore_mcast_list_elem *mc_mac = arg;
12015
12016 mc_mac += cnt;
12017 mc_mac->mac = (uint8_t *)LLADDR(sdl);
12018
12019 return (1);
12020 }
12021
12022 static int
bxe_init_mcast_macs_list(struct bxe_softc * sc,struct ecore_mcast_ramrod_params * p)12023 bxe_init_mcast_macs_list(struct bxe_softc *sc,
12024 struct ecore_mcast_ramrod_params *p)
12025 {
12026 if_t ifp = sc->ifp;
12027 int mc_count;
12028 struct ecore_mcast_list_elem *mc_mac;
12029
12030 ECORE_LIST_INIT(&p->mcast_list);
12031 p->mcast_list_len = 0;
12032
12033 /* XXXGL: multicast count may change later */
12034 mc_count = if_llmaddr_count(ifp);
12035
12036 if (!mc_count) {
12037 return (0);
12038 }
12039
12040 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF,
12041 (M_NOWAIT | M_ZERO));
12042 if (!mc_mac) {
12043 BLOGE(sc, "Failed to allocate temp mcast list\n");
12044 return (-1);
12045 }
12046 bzero(mc_mac, (sizeof(*mc_mac) * mc_count));
12047 if_foreach_llmaddr(ifp, bxe_push_maddr, mc_mac);
12048
12049 for (int i = 0; i < mc_count; i ++) {
12050 ECORE_LIST_PUSH_TAIL(&mc_mac[i].link, &p->mcast_list);
12051 BLOGD(sc, DBG_LOAD,
12052 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X and mc_count %d\n",
12053 mc_mac[i].mac[0], mc_mac[i].mac[1], mc_mac[i].mac[2],
12054 mc_mac[i].mac[3], mc_mac[i].mac[4], mc_mac[i].mac[5],
12055 mc_count);
12056 }
12057
12058 p->mcast_list_len = mc_count;
12059
12060 return (0);
12061 }
12062
12063 static void
bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params * p)12064 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p)
12065 {
12066 struct ecore_mcast_list_elem *mc_mac =
12067 ECORE_LIST_FIRST_ENTRY(&p->mcast_list,
12068 struct ecore_mcast_list_elem,
12069 link);
12070
12071 if (mc_mac) {
12072 /* only a single free as all mc_macs are in the same heap array */
12073 free(mc_mac, M_DEVBUF);
12074 }
12075 }
12076 static int
bxe_set_mc_list(struct bxe_softc * sc)12077 bxe_set_mc_list(struct bxe_softc *sc)
12078 {
12079 struct ecore_mcast_ramrod_params rparam = { NULL };
12080 int rc = 0;
12081
12082 rparam.mcast_obj = &sc->mcast_obj;
12083
12084 BXE_MCAST_LOCK(sc);
12085
12086 /* first, clear all configured multicast MACs */
12087 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
12088 if (rc < 0) {
12089 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc);
12090 /* Manual backport parts of FreeBSD upstream r284470. */
12091 BXE_MCAST_UNLOCK(sc);
12092 return (rc);
12093 }
12094
12095 /* configure a new MACs list */
12096 rc = bxe_init_mcast_macs_list(sc, &rparam);
12097 if (rc) {
12098 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc);
12099 BXE_MCAST_UNLOCK(sc);
12100 return (rc);
12101 }
12102
12103 /* Now add the new MACs */
12104 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD);
12105 if (rc < 0) {
12106 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc);
12107 }
12108
12109 bxe_free_mcast_macs_list(&rparam);
12110
12111 BXE_MCAST_UNLOCK(sc);
12112
12113 return (rc);
12114 }
12115
12116 struct bxe_set_addr_ctx {
12117 struct bxe_softc *sc;
12118 unsigned long ramrod_flags;
12119 int rc;
12120 };
12121
12122 static u_int
bxe_set_addr(void * arg,struct sockaddr_dl * sdl,u_int cnt)12123 bxe_set_addr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
12124 {
12125 struct bxe_set_addr_ctx *ctx = arg;
12126 struct ecore_vlan_mac_obj *mac_obj = &ctx->sc->sp_objs->mac_obj;
12127 int rc;
12128
12129 if (ctx->rc < 0)
12130 return (0);
12131
12132 rc = bxe_set_mac_one(ctx->sc, (uint8_t *)LLADDR(sdl), mac_obj, TRUE,
12133 ECORE_UC_LIST_MAC, &ctx->ramrod_flags);
12134
12135 /* do not treat adding same MAC as an error */
12136 if (rc == -EEXIST)
12137 BLOGD(ctx->sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12138 else if (rc < 0) {
12139 BLOGE(ctx->sc, "Failed to schedule ADD operations (%d)\n", rc);
12140 ctx->rc = rc;
12141 }
12142
12143 return (1);
12144 }
12145
12146 static int
bxe_set_uc_list(struct bxe_softc * sc)12147 bxe_set_uc_list(struct bxe_softc *sc)
12148 {
12149 if_t ifp = sc->ifp;
12150 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
12151 struct bxe_set_addr_ctx ctx = { sc, 0, 0 };
12152 int rc;
12153
12154 /* first schedule a cleanup up of old configuration */
12155 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE);
12156 if (rc < 0) {
12157 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc);
12158 return (rc);
12159 }
12160
12161 if_foreach_lladdr(ifp, bxe_set_addr, &ctx);
12162 if (ctx.rc < 0)
12163 return (ctx.rc);
12164
12165 /* Execute the pending commands */
12166 bit_set(&ctx.ramrod_flags, RAMROD_CONT);
12167 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */,
12168 ECORE_UC_LIST_MAC, &ctx.ramrod_flags));
12169 }
12170
12171 static void
bxe_set_rx_mode(struct bxe_softc * sc)12172 bxe_set_rx_mode(struct bxe_softc *sc)
12173 {
12174 if_t ifp = sc->ifp;
12175 uint32_t rx_mode = BXE_RX_MODE_NORMAL;
12176
12177 if (sc->state != BXE_STATE_OPEN) {
12178 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state);
12179 return;
12180 }
12181
12182 BLOGD(sc, DBG_SP, "if_flags(ifp)=0x%x\n", if_getflags(sc->ifp));
12183
12184 if (if_getflags(ifp) & IFF_PROMISC) {
12185 rx_mode = BXE_RX_MODE_PROMISC;
12186 } else if ((if_getflags(ifp) & IFF_ALLMULTI) ||
12187 (if_llmaddr_count(ifp) > BXE_MAX_MULTICAST &&
12188 CHIP_IS_E1(sc))) {
12189 rx_mode = BXE_RX_MODE_ALLMULTI;
12190 } else {
12191 if (IS_PF(sc)) {
12192 /* some multicasts */
12193 if (bxe_set_mc_list(sc) < 0) {
12194 rx_mode = BXE_RX_MODE_ALLMULTI;
12195 }
12196 if (bxe_set_uc_list(sc) < 0) {
12197 rx_mode = BXE_RX_MODE_PROMISC;
12198 }
12199 }
12200 }
12201
12202 sc->rx_mode = rx_mode;
12203
12204 /* schedule the rx_mode command */
12205 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
12206 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n");
12207 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
12208 return;
12209 }
12210
12211 if (IS_PF(sc)) {
12212 bxe_set_storm_rx_mode(sc);
12213 }
12214 }
12215
12216
12217 /* update flags in shmem */
12218 static void
bxe_update_drv_flags(struct bxe_softc * sc,uint32_t flags,uint32_t set)12219 bxe_update_drv_flags(struct bxe_softc *sc,
12220 uint32_t flags,
12221 uint32_t set)
12222 {
12223 uint32_t drv_flags;
12224
12225 if (SHMEM2_HAS(sc, drv_flags)) {
12226 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12227 drv_flags = SHMEM2_RD(sc, drv_flags);
12228
12229 if (set) {
12230 SET_FLAGS(drv_flags, flags);
12231 } else {
12232 RESET_FLAGS(drv_flags, flags);
12233 }
12234
12235 SHMEM2_WR(sc, drv_flags, drv_flags);
12236 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags);
12237
12238 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12239 }
12240 }
12241
12242 /* periodic timer callout routine, only runs when the interface is up */
12243
12244 static void
bxe_periodic_callout_func(void * xsc)12245 bxe_periodic_callout_func(void *xsc)
12246 {
12247 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12248 int i;
12249
12250 if (!BXE_CORE_TRYLOCK(sc)) {
12251 /* just bail and try again next time */
12252
12253 if ((sc->state == BXE_STATE_OPEN) &&
12254 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12255 /* schedule the next periodic callout */
12256 callout_reset(&sc->periodic_callout, hz,
12257 bxe_periodic_callout_func, sc);
12258 }
12259
12260 return;
12261 }
12262
12263 if ((sc->state != BXE_STATE_OPEN) ||
12264 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
12265 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state);
12266 BXE_CORE_UNLOCK(sc);
12267 return;
12268 }
12269
12270
12271 /* Check for TX timeouts on any fastpath. */
12272 FOR_EACH_QUEUE(sc, i) {
12273 if (bxe_watchdog(sc, &sc->fp[i]) != 0) {
12274 /* Ruh-Roh, chip was reset! */
12275 break;
12276 }
12277 }
12278
12279 if (!CHIP_REV_IS_SLOW(sc)) {
12280 /*
12281 * This barrier is needed to ensure the ordering between the writing
12282 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and
12283 * the reading here.
12284 */
12285 mb();
12286 if (sc->port.pmf) {
12287 bxe_acquire_phy_lock(sc);
12288 elink_period_func(&sc->link_params, &sc->link_vars);
12289 bxe_release_phy_lock(sc);
12290 }
12291 }
12292
12293 if (IS_PF(sc) && !(sc->flags & BXE_NO_PULSE)) {
12294 int mb_idx = SC_FW_MB_IDX(sc);
12295 uint32_t drv_pulse;
12296 uint32_t mcp_pulse;
12297
12298 ++sc->fw_drv_pulse_wr_seq;
12299 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
12300
12301 drv_pulse = sc->fw_drv_pulse_wr_seq;
12302 bxe_drv_pulse(sc);
12303
12304 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
12305 MCP_PULSE_SEQ_MASK);
12306
12307 /*
12308 * The delta between driver pulse and mcp response should
12309 * be 1 (before mcp response) or 0 (after mcp response).
12310 */
12311 if ((drv_pulse != mcp_pulse) &&
12312 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
12313 /* someone lost a heartbeat... */
12314 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
12315 drv_pulse, mcp_pulse);
12316 }
12317 }
12318
12319 /* state is BXE_STATE_OPEN */
12320 bxe_stats_handle(sc, STATS_EVENT_UPDATE);
12321
12322 BXE_CORE_UNLOCK(sc);
12323
12324 if ((sc->state == BXE_STATE_OPEN) &&
12325 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12326 /* schedule the next periodic callout */
12327 callout_reset(&sc->periodic_callout, hz,
12328 bxe_periodic_callout_func, sc);
12329 }
12330 }
12331
12332 static void
bxe_periodic_start(struct bxe_softc * sc)12333 bxe_periodic_start(struct bxe_softc *sc)
12334 {
12335 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
12336 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc);
12337 }
12338
12339 static void
bxe_periodic_stop(struct bxe_softc * sc)12340 bxe_periodic_stop(struct bxe_softc *sc)
12341 {
12342 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
12343 callout_drain(&sc->periodic_callout);
12344 }
12345
12346 void
bxe_parity_recover(struct bxe_softc * sc)12347 bxe_parity_recover(struct bxe_softc *sc)
12348 {
12349 uint8_t global = FALSE;
12350 uint32_t error_recovered, error_unrecovered;
12351
12352
12353 if ((sc->recovery_state == BXE_RECOVERY_FAILED) &&
12354 (sc->state == BXE_STATE_ERROR)) {
12355 BLOGE(sc, "RECOVERY failed, "
12356 "stack notified driver is NOT running! "
12357 "Please reboot/power cycle the system.\n");
12358 return;
12359 }
12360
12361 while (1) {
12362 BLOGD(sc, DBG_SP,
12363 "%s sc=%p state=0x%x rec_state=0x%x error_status=%x\n",
12364 __func__, sc, sc->state, sc->recovery_state, sc->error_status);
12365
12366 switch(sc->recovery_state) {
12367
12368 case BXE_RECOVERY_INIT:
12369 bxe_chk_parity_attn(sc, &global, FALSE);
12370
12371 if ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ||
12372 (sc->error_status & BXE_ERR_MCP_ASSERT) ||
12373 (sc->error_status & BXE_ERR_GLOBAL)) {
12374
12375 BXE_CORE_LOCK(sc);
12376 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
12377 bxe_periodic_stop(sc);
12378 }
12379 bxe_nic_unload(sc, UNLOAD_RECOVERY, false);
12380 sc->state = BXE_STATE_ERROR;
12381 sc->recovery_state = BXE_RECOVERY_FAILED;
12382 BLOGE(sc, " No Recovery tried for error 0x%x"
12383 " stack notified driver is NOT running!"
12384 " Please reboot/power cycle the system.\n",
12385 sc->error_status);
12386 BXE_CORE_UNLOCK(sc);
12387 return;
12388 }
12389
12390
12391 /* Try to get a LEADER_LOCK HW lock */
12392 if (bxe_trylock_leader_lock(sc)) {
12393
12394 bxe_set_reset_in_progress(sc);
12395 /*
12396 * Check if there is a global attention and if
12397 * there was a global attention, set the global
12398 * reset bit.
12399 */
12400 if (global) {
12401 bxe_set_reset_global(sc);
12402 }
12403 sc->is_leader = 1;
12404 }
12405
12406 /* If interface has been removed - break */
12407
12408 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
12409 bxe_periodic_stop(sc);
12410 }
12411
12412 BXE_CORE_LOCK(sc);
12413 bxe_nic_unload(sc,UNLOAD_RECOVERY, false);
12414 sc->recovery_state = BXE_RECOVERY_WAIT;
12415 BXE_CORE_UNLOCK(sc);
12416
12417 /*
12418 * Ensure "is_leader", MCP command sequence and
12419 * "recovery_state" update values are seen on other
12420 * CPUs.
12421 */
12422 mb();
12423 break;
12424 case BXE_RECOVERY_WAIT:
12425
12426 if (sc->is_leader) {
12427 int other_engine = SC_PATH(sc) ? 0 : 1;
12428 bool other_load_status =
12429 bxe_get_load_status(sc, other_engine);
12430 bool load_status =
12431 bxe_get_load_status(sc, SC_PATH(sc));
12432 global = bxe_reset_is_global(sc);
12433
12434 /*
12435 * In case of a parity in a global block, let
12436 * the first leader that performs a
12437 * leader_reset() reset the global blocks in
12438 * order to clear global attentions. Otherwise
12439 * the gates will remain closed for that
12440 * engine.
12441 */
12442 if (load_status ||
12443 (global && other_load_status)) {
12444 /*
12445 * Wait until all other functions get
12446 * down.
12447 */
12448 taskqueue_enqueue_timeout(taskqueue_thread,
12449 &sc->sp_err_timeout_task, hz/10);
12450 return;
12451 } else {
12452 /*
12453 * If all other functions got down
12454 * try to bring the chip back to
12455 * normal. In any case it's an exit
12456 * point for a leader.
12457 */
12458 if (bxe_leader_reset(sc)) {
12459 BLOGE(sc, "RECOVERY failed, "
12460 "stack notified driver is NOT running!\n");
12461 sc->recovery_state = BXE_RECOVERY_FAILED;
12462 sc->state = BXE_STATE_ERROR;
12463 mb();
12464 return;
12465 }
12466
12467 /*
12468 * If we are here, means that the
12469 * leader has succeeded and doesn't
12470 * want to be a leader any more. Try
12471 * to continue as a none-leader.
12472 */
12473 break;
12474 }
12475
12476 } else { /* non-leader */
12477 if (!bxe_reset_is_done(sc, SC_PATH(sc))) {
12478 /*
12479 * Try to get a LEADER_LOCK HW lock as
12480 * long as a former leader may have
12481 * been unloaded by the user or
12482 * released a leadership by another
12483 * reason.
12484 */
12485 if (bxe_trylock_leader_lock(sc)) {
12486 /*
12487 * I'm a leader now! Restart a
12488 * switch case.
12489 */
12490 sc->is_leader = 1;
12491 break;
12492 }
12493
12494 taskqueue_enqueue_timeout(taskqueue_thread,
12495 &sc->sp_err_timeout_task, hz/10);
12496 return;
12497
12498 } else {
12499 /*
12500 * If there was a global attention, wait
12501 * for it to be cleared.
12502 */
12503 if (bxe_reset_is_global(sc)) {
12504 taskqueue_enqueue_timeout(taskqueue_thread,
12505 &sc->sp_err_timeout_task, hz/10);
12506 return;
12507 }
12508
12509 error_recovered =
12510 sc->eth_stats.recoverable_error;
12511 error_unrecovered =
12512 sc->eth_stats.unrecoverable_error;
12513 BXE_CORE_LOCK(sc);
12514 sc->recovery_state =
12515 BXE_RECOVERY_NIC_LOADING;
12516 if (bxe_nic_load(sc, LOAD_NORMAL)) {
12517 error_unrecovered++;
12518 sc->recovery_state = BXE_RECOVERY_FAILED;
12519 sc->state = BXE_STATE_ERROR;
12520 BLOGE(sc, "Recovery is NOT successful, "
12521 " state=0x%x recovery_state=0x%x error=%x\n",
12522 sc->state, sc->recovery_state, sc->error_status);
12523 sc->error_status = 0;
12524 } else {
12525 sc->recovery_state =
12526 BXE_RECOVERY_DONE;
12527 error_recovered++;
12528 BLOGI(sc, "Recovery is successful from errors %x,"
12529 " state=0x%x"
12530 " recovery_state=0x%x \n", sc->error_status,
12531 sc->state, sc->recovery_state);
12532 mb();
12533 }
12534 sc->error_status = 0;
12535 BXE_CORE_UNLOCK(sc);
12536 sc->eth_stats.recoverable_error =
12537 error_recovered;
12538 sc->eth_stats.unrecoverable_error =
12539 error_unrecovered;
12540
12541 return;
12542 }
12543 }
12544 default:
12545 return;
12546 }
12547 }
12548 }
12549 void
bxe_handle_error(struct bxe_softc * sc)12550 bxe_handle_error(struct bxe_softc * sc)
12551 {
12552
12553 if(sc->recovery_state == BXE_RECOVERY_WAIT) {
12554 return;
12555 }
12556 if(sc->error_status) {
12557 if (sc->state == BXE_STATE_OPEN) {
12558 bxe_int_disable(sc);
12559 }
12560 if (sc->link_vars.link_up) {
12561 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
12562 }
12563 sc->recovery_state = BXE_RECOVERY_INIT;
12564 BLOGI(sc, "bxe%d: Recovery started errors 0x%x recovery state 0x%x\n",
12565 sc->unit, sc->error_status, sc->recovery_state);
12566 bxe_parity_recover(sc);
12567 }
12568 }
12569
12570 static void
bxe_sp_err_timeout_task(void * arg,int pending)12571 bxe_sp_err_timeout_task(void *arg, int pending)
12572 {
12573
12574 struct bxe_softc *sc = (struct bxe_softc *)arg;
12575
12576 BLOGD(sc, DBG_SP,
12577 "%s state = 0x%x rec state=0x%x error_status=%x\n",
12578 __func__, sc->state, sc->recovery_state, sc->error_status);
12579
12580 if((sc->recovery_state == BXE_RECOVERY_FAILED) &&
12581 (sc->state == BXE_STATE_ERROR)) {
12582 return;
12583 }
12584 /* if can be taken */
12585 if ((sc->error_status) && (sc->trigger_grcdump)) {
12586 bxe_grc_dump(sc);
12587 }
12588 if (sc->recovery_state != BXE_RECOVERY_DONE) {
12589 bxe_handle_error(sc);
12590 bxe_parity_recover(sc);
12591 } else if (sc->error_status) {
12592 bxe_handle_error(sc);
12593 }
12594
12595 return;
12596 }
12597
12598 /* start the controller */
12599 static __noinline int
bxe_nic_load(struct bxe_softc * sc,int load_mode)12600 bxe_nic_load(struct bxe_softc *sc,
12601 int load_mode)
12602 {
12603 uint32_t val;
12604 int load_code = 0;
12605 int i, rc = 0;
12606
12607 BXE_CORE_LOCK_ASSERT(sc);
12608
12609 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n");
12610
12611 sc->state = BXE_STATE_OPENING_WAITING_LOAD;
12612
12613 if (IS_PF(sc)) {
12614 /* must be called before memory allocation and HW init */
12615 bxe_ilt_set_info(sc);
12616 }
12617
12618 sc->last_reported_link_state = LINK_STATE_UNKNOWN;
12619
12620 bxe_set_fp_rx_buf_size(sc);
12621
12622 if (bxe_alloc_fp_buffers(sc) != 0) {
12623 BLOGE(sc, "Failed to allocate fastpath memory\n");
12624 sc->state = BXE_STATE_CLOSED;
12625 rc = ENOMEM;
12626 goto bxe_nic_load_error0;
12627 }
12628
12629 if (bxe_alloc_mem(sc) != 0) {
12630 sc->state = BXE_STATE_CLOSED;
12631 rc = ENOMEM;
12632 goto bxe_nic_load_error0;
12633 }
12634
12635 if (bxe_alloc_fw_stats_mem(sc) != 0) {
12636 sc->state = BXE_STATE_CLOSED;
12637 rc = ENOMEM;
12638 goto bxe_nic_load_error0;
12639 }
12640
12641 if (IS_PF(sc)) {
12642 /* set pf load just before approaching the MCP */
12643 bxe_set_pf_load(sc);
12644
12645 /* if MCP exists send load request and analyze response */
12646 if (!BXE_NOMCP(sc)) {
12647 /* attempt to load pf */
12648 if (bxe_nic_load_request(sc, &load_code) != 0) {
12649 sc->state = BXE_STATE_CLOSED;
12650 rc = ENXIO;
12651 goto bxe_nic_load_error1;
12652 }
12653
12654 /* what did the MCP say? */
12655 if (bxe_nic_load_analyze_req(sc, load_code) != 0) {
12656 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12657 sc->state = BXE_STATE_CLOSED;
12658 rc = ENXIO;
12659 goto bxe_nic_load_error2;
12660 }
12661 } else {
12662 BLOGI(sc, "Device has no MCP!\n");
12663 load_code = bxe_nic_load_no_mcp(sc);
12664 }
12665
12666 /* mark PMF if applicable */
12667 bxe_nic_load_pmf(sc, load_code);
12668
12669 /* Init Function state controlling object */
12670 bxe_init_func_obj(sc);
12671
12672 /* Initialize HW */
12673 if (bxe_init_hw(sc, load_code) != 0) {
12674 BLOGE(sc, "HW init failed\n");
12675 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12676 sc->state = BXE_STATE_CLOSED;
12677 rc = ENXIO;
12678 goto bxe_nic_load_error2;
12679 }
12680 }
12681
12682 /* set ALWAYS_ALIVE bit in shmem */
12683 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
12684 bxe_drv_pulse(sc);
12685 sc->flags |= BXE_NO_PULSE;
12686
12687 /* attach interrupts */
12688 if (bxe_interrupt_attach(sc) != 0) {
12689 sc->state = BXE_STATE_CLOSED;
12690 rc = ENXIO;
12691 goto bxe_nic_load_error2;
12692 }
12693
12694 bxe_nic_init(sc, load_code);
12695
12696 /* Init per-function objects */
12697 if (IS_PF(sc)) {
12698 bxe_init_objs(sc);
12699 // XXX bxe_iov_nic_init(sc);
12700
12701 /* set AFEX default VLAN tag to an invalid value */
12702 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
12703 // XXX bxe_nic_load_afex_dcc(sc, load_code);
12704
12705 sc->state = BXE_STATE_OPENING_WAITING_PORT;
12706 rc = bxe_func_start(sc);
12707 if (rc) {
12708 BLOGE(sc, "Function start failed! rc = %d\n", rc);
12709 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12710 sc->state = BXE_STATE_ERROR;
12711 goto bxe_nic_load_error3;
12712 }
12713
12714 /* send LOAD_DONE command to MCP */
12715 if (!BXE_NOMCP(sc)) {
12716 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12717 if (!load_code) {
12718 BLOGE(sc, "MCP response failure, aborting\n");
12719 sc->state = BXE_STATE_ERROR;
12720 rc = ENXIO;
12721 goto bxe_nic_load_error3;
12722 }
12723 }
12724
12725 rc = bxe_setup_leading(sc);
12726 if (rc) {
12727 BLOGE(sc, "Setup leading failed! rc = %d\n", rc);
12728 sc->state = BXE_STATE_ERROR;
12729 goto bxe_nic_load_error3;
12730 }
12731
12732 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
12733 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE);
12734 if (rc) {
12735 BLOGE(sc, "Queue(%d) setup failed rc = %d\n", i, rc);
12736 sc->state = BXE_STATE_ERROR;
12737 goto bxe_nic_load_error3;
12738 }
12739 }
12740
12741 rc = bxe_init_rss_pf(sc);
12742 if (rc) {
12743 BLOGE(sc, "PF RSS init failed\n");
12744 sc->state = BXE_STATE_ERROR;
12745 goto bxe_nic_load_error3;
12746 }
12747 }
12748 /* XXX VF */
12749
12750 /* now when Clients are configured we are ready to work */
12751 sc->state = BXE_STATE_OPEN;
12752
12753 /* Configure a ucast MAC */
12754 if (IS_PF(sc)) {
12755 rc = bxe_set_eth_mac(sc, TRUE);
12756 }
12757 if (rc) {
12758 BLOGE(sc, "Setting Ethernet MAC failed rc = %d\n", rc);
12759 sc->state = BXE_STATE_ERROR;
12760 goto bxe_nic_load_error3;
12761 }
12762
12763 if (sc->port.pmf) {
12764 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN);
12765 if (rc) {
12766 sc->state = BXE_STATE_ERROR;
12767 goto bxe_nic_load_error3;
12768 }
12769 }
12770
12771 sc->link_params.feature_config_flags &=
12772 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
12773
12774 /* start fast path */
12775
12776 /* Initialize Rx filter */
12777 bxe_set_rx_mode(sc);
12778
12779 /* start the Tx */
12780 switch (/* XXX load_mode */LOAD_OPEN) {
12781 case LOAD_NORMAL:
12782 case LOAD_OPEN:
12783 break;
12784
12785 case LOAD_DIAG:
12786 case LOAD_LOOPBACK_EXT:
12787 sc->state = BXE_STATE_DIAG;
12788 break;
12789
12790 default:
12791 break;
12792 }
12793
12794 if (sc->port.pmf) {
12795 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
12796 } else {
12797 bxe_link_status_update(sc);
12798 }
12799
12800 /* start the periodic timer callout */
12801 bxe_periodic_start(sc);
12802
12803 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
12804 /* mark driver is loaded in shmem2 */
12805 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
12806 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
12807 (val |
12808 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
12809 DRV_FLAGS_CAPABILITIES_LOADED_L2));
12810 }
12811
12812 /* wait for all pending SP commands to complete */
12813 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) {
12814 BLOGE(sc, "Timeout waiting for all SPs to complete!\n");
12815 bxe_periodic_stop(sc);
12816 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE);
12817 return (ENXIO);
12818 }
12819
12820 /* Tell the stack the driver is running! */
12821 if_setdrvflags(sc->ifp, IFF_DRV_RUNNING);
12822
12823 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n");
12824
12825 return (0);
12826
12827 bxe_nic_load_error3:
12828
12829 if (IS_PF(sc)) {
12830 bxe_int_disable_sync(sc, 1);
12831
12832 /* clean out queued objects */
12833 bxe_squeeze_objects(sc);
12834 }
12835
12836 bxe_interrupt_detach(sc);
12837
12838 bxe_nic_load_error2:
12839
12840 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
12841 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
12842 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
12843 }
12844
12845 sc->port.pmf = 0;
12846
12847 bxe_nic_load_error1:
12848
12849 /* clear pf_load status, as it was already set */
12850 if (IS_PF(sc)) {
12851 bxe_clear_pf_load(sc);
12852 }
12853
12854 bxe_nic_load_error0:
12855
12856 bxe_free_fw_stats_mem(sc);
12857 bxe_free_fp_buffers(sc);
12858 bxe_free_mem(sc);
12859
12860 return (rc);
12861 }
12862
12863 static int
bxe_init_locked(struct bxe_softc * sc)12864 bxe_init_locked(struct bxe_softc *sc)
12865 {
12866 int other_engine = SC_PATH(sc) ? 0 : 1;
12867 uint8_t other_load_status, load_status;
12868 uint8_t global = FALSE;
12869 int rc;
12870
12871 BXE_CORE_LOCK_ASSERT(sc);
12872
12873 /* check if the driver is already running */
12874 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
12875 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n");
12876 return (0);
12877 }
12878
12879 if((sc->state == BXE_STATE_ERROR) &&
12880 (sc->recovery_state == BXE_RECOVERY_FAILED)) {
12881 BLOGE(sc, "Initialization not done, "
12882 "as previous recovery failed."
12883 "Reboot/Power-cycle the system\n" );
12884 return (ENXIO);
12885 }
12886
12887
12888 bxe_set_power_state(sc, PCI_PM_D0);
12889
12890 /*
12891 * If parity occurred during the unload, then attentions and/or
12892 * RECOVERY_IN_PROGRES may still be set. If so we want the first function
12893 * loaded on the current engine to complete the recovery. Parity recovery
12894 * is only relevant for PF driver.
12895 */
12896 if (IS_PF(sc)) {
12897 other_load_status = bxe_get_load_status(sc, other_engine);
12898 load_status = bxe_get_load_status(sc, SC_PATH(sc));
12899
12900 if (!bxe_reset_is_done(sc, SC_PATH(sc)) ||
12901 bxe_chk_parity_attn(sc, &global, TRUE)) {
12902 do {
12903 /*
12904 * If there are attentions and they are in global blocks, set
12905 * the GLOBAL_RESET bit regardless whether it will be this
12906 * function that will complete the recovery or not.
12907 */
12908 if (global) {
12909 bxe_set_reset_global(sc);
12910 }
12911
12912 /*
12913 * Only the first function on the current engine should try
12914 * to recover in open. In case of attentions in global blocks
12915 * only the first in the chip should try to recover.
12916 */
12917 if ((!load_status && (!global || !other_load_status)) &&
12918 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) {
12919 BLOGI(sc, "Recovered during init\n");
12920 break;
12921 }
12922
12923 /* recovery has failed... */
12924 bxe_set_power_state(sc, PCI_PM_D3hot);
12925 sc->recovery_state = BXE_RECOVERY_FAILED;
12926
12927 BLOGE(sc, "Recovery flow hasn't properly "
12928 "completed yet, try again later. "
12929 "If you still see this message after a "
12930 "few retries then power cycle is required.\n");
12931
12932 rc = ENXIO;
12933 goto bxe_init_locked_done;
12934 } while (0);
12935 }
12936 }
12937
12938 sc->recovery_state = BXE_RECOVERY_DONE;
12939
12940 rc = bxe_nic_load(sc, LOAD_OPEN);
12941
12942 bxe_init_locked_done:
12943
12944 if (rc) {
12945 /* Tell the stack the driver is NOT running! */
12946 BLOGE(sc, "Initialization failed, "
12947 "stack notified driver is NOT running!\n");
12948 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING);
12949 }
12950
12951 return (rc);
12952 }
12953
12954 static int
bxe_stop_locked(struct bxe_softc * sc)12955 bxe_stop_locked(struct bxe_softc *sc)
12956 {
12957 BXE_CORE_LOCK_ASSERT(sc);
12958 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE));
12959 }
12960
12961 /*
12962 * Handles controller initialization when called from an unlocked routine.
12963 * ifconfig calls this function.
12964 *
12965 * Returns:
12966 * void
12967 */
12968 static void
bxe_init(void * xsc)12969 bxe_init(void *xsc)
12970 {
12971 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12972
12973 BXE_CORE_LOCK(sc);
12974 bxe_init_locked(sc);
12975 BXE_CORE_UNLOCK(sc);
12976 }
12977
12978 static void
bxe_init_ifnet(struct bxe_softc * sc)12979 bxe_init_ifnet(struct bxe_softc *sc)
12980 {
12981 if_t ifp;
12982 int capabilities;
12983
12984 /* ifconfig entrypoint for media type/status reporting */
12985 ifmedia_init(&sc->ifmedia, IFM_IMASK,
12986 bxe_ifmedia_update,
12987 bxe_ifmedia_status);
12988
12989 /* set the default interface values */
12990 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL);
12991 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL);
12992 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO));
12993
12994 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */
12995 BLOGI(sc, "IFMEDIA flags : %x\n", sc->ifmedia.ifm_media);
12996
12997 /* allocate the ifnet structure */
12998 ifp = if_gethandle(IFT_ETHER);
12999
13000 if_setsoftc(ifp, sc);
13001 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
13002 if_setflags(ifp, (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST));
13003 if_setioctlfn(ifp, bxe_ioctl);
13004 if_setstartfn(ifp, bxe_tx_start);
13005 if_setgetcounterfn(ifp, bxe_get_counter);
13006 if_settransmitfn(ifp, bxe_tx_mq_start);
13007 if_setqflushfn(ifp, bxe_mq_flush);
13008 if_setinitfn(ifp, bxe_init);
13009 if_setmtu(ifp, sc->mtu);
13010 if_sethwassist(ifp, (CSUM_IP |
13011 CSUM_TCP |
13012 CSUM_UDP |
13013 CSUM_TSO |
13014 CSUM_TCP_IPV6 |
13015 CSUM_UDP_IPV6));
13016
13017 capabilities =
13018 (IFCAP_VLAN_MTU |
13019 IFCAP_VLAN_HWTAGGING |
13020 IFCAP_VLAN_HWTSO |
13021 IFCAP_VLAN_HWFILTER |
13022 IFCAP_VLAN_HWCSUM |
13023 IFCAP_HWCSUM |
13024 IFCAP_JUMBO_MTU |
13025 IFCAP_LRO |
13026 IFCAP_TSO4 |
13027 IFCAP_TSO6 |
13028 IFCAP_WOL_MAGIC);
13029 if_setcapabilitiesbit(ifp, capabilities, 0); /* XXX */
13030 if_setcapenable(ifp, if_getcapabilities(ifp));
13031 if_setbaudrate(ifp, IF_Gbps(10));
13032 /* XXX */
13033 if_setsendqlen(ifp, sc->tx_ring_size);
13034 if_setsendqready(ifp);
13035 /* XXX */
13036
13037 sc->ifp = ifp;
13038
13039 /* attach to the Ethernet interface list */
13040 ether_ifattach(ifp, sc->link_params.mac_addr);
13041
13042 /* Attach driver debugnet methods. */
13043 DEBUGNET_SET(ifp, bxe);
13044 }
13045
13046 static void
bxe_deallocate_bars(struct bxe_softc * sc)13047 bxe_deallocate_bars(struct bxe_softc *sc)
13048 {
13049 int i;
13050
13051 for (i = 0; i < MAX_BARS; i++) {
13052 if (sc->bar[i].resource != NULL) {
13053 bus_release_resource(sc->dev,
13054 SYS_RES_MEMORY,
13055 sc->bar[i].rid,
13056 sc->bar[i].resource);
13057 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n",
13058 i, PCIR_BAR(i));
13059 }
13060 }
13061 }
13062
13063 static int
bxe_allocate_bars(struct bxe_softc * sc)13064 bxe_allocate_bars(struct bxe_softc *sc)
13065 {
13066 u_int flags;
13067 int i;
13068
13069 memset(sc->bar, 0, sizeof(sc->bar));
13070
13071 for (i = 0; i < MAX_BARS; i++) {
13072
13073 /* memory resources reside at BARs 0, 2, 4 */
13074 /* Run `pciconf -lb` to see mappings */
13075 if ((i != 0) && (i != 2) && (i != 4)) {
13076 continue;
13077 }
13078
13079 sc->bar[i].rid = PCIR_BAR(i);
13080
13081 flags = RF_ACTIVE;
13082 if (i == 0) {
13083 flags |= RF_SHAREABLE;
13084 }
13085
13086 if ((sc->bar[i].resource =
13087 bus_alloc_resource_any(sc->dev,
13088 SYS_RES_MEMORY,
13089 &sc->bar[i].rid,
13090 flags)) == NULL) {
13091 return (0);
13092 }
13093
13094 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource);
13095 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource);
13096 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource);
13097
13098 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %#jx-%#jx (%jd) -> %#jx\n",
13099 i, PCIR_BAR(i),
13100 rman_get_start(sc->bar[i].resource),
13101 rman_get_end(sc->bar[i].resource),
13102 rman_get_size(sc->bar[i].resource),
13103 (uintmax_t)sc->bar[i].kva);
13104 }
13105
13106 return (0);
13107 }
13108
13109 static void
bxe_get_function_num(struct bxe_softc * sc)13110 bxe_get_function_num(struct bxe_softc *sc)
13111 {
13112 uint32_t val = 0;
13113
13114 /*
13115 * Read the ME register to get the function number. The ME register
13116 * holds the relative-function number and absolute-function number. The
13117 * absolute-function number appears only in E2 and above. Before that
13118 * these bits always contained zero, therefore we cannot blindly use them.
13119 */
13120
13121 val = REG_RD(sc, BAR_ME_REGISTER);
13122
13123 sc->pfunc_rel =
13124 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
13125 sc->path_id =
13126 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1;
13127
13128 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13129 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
13130 } else {
13131 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
13132 }
13133
13134 BLOGD(sc, DBG_LOAD,
13135 "Relative function %d, Absolute function %d, Path %d\n",
13136 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
13137 }
13138
13139 static uint32_t
bxe_get_shmem_mf_cfg_base(struct bxe_softc * sc)13140 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc)
13141 {
13142 uint32_t shmem2_size;
13143 uint32_t offset;
13144 uint32_t mf_cfg_offset_value;
13145
13146 /* Non 57712 */
13147 offset = (SHMEM_RD(sc, func_mb) +
13148 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
13149
13150 /* 57712 plus */
13151 if (sc->devinfo.shmem2_base != 0) {
13152 shmem2_size = SHMEM2_RD(sc, size);
13153 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
13154 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
13155 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
13156 offset = mf_cfg_offset_value;
13157 }
13158 }
13159 }
13160
13161 return (offset);
13162 }
13163
13164 static uint32_t
bxe_pcie_capability_read(struct bxe_softc * sc,int reg,int width)13165 bxe_pcie_capability_read(struct bxe_softc *sc,
13166 int reg,
13167 int width)
13168 {
13169 int pcie_reg;
13170
13171 /* ensure PCIe capability is enabled */
13172 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) {
13173 if (pcie_reg != 0) {
13174 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg);
13175 return (pci_read_config(sc->dev, (pcie_reg + reg), width));
13176 }
13177 }
13178
13179 BLOGE(sc, "PCIe capability NOT FOUND!!!\n");
13180
13181 return (0);
13182 }
13183
13184 static uint8_t
bxe_is_pcie_pending(struct bxe_softc * sc)13185 bxe_is_pcie_pending(struct bxe_softc *sc)
13186 {
13187 return (bxe_pcie_capability_read(sc, PCIER_DEVICE_STA, 2) &
13188 PCIEM_STA_TRANSACTION_PND);
13189 }
13190
13191 /*
13192 * Walk the PCI capabiites list for the device to find what features are
13193 * supported. These capabilites may be enabled/disabled by firmware so it's
13194 * best to walk the list rather than make assumptions.
13195 */
13196 static void
bxe_probe_pci_caps(struct bxe_softc * sc)13197 bxe_probe_pci_caps(struct bxe_softc *sc)
13198 {
13199 uint16_t link_status;
13200 int reg;
13201
13202 /* check if PCI Power Management is enabled */
13203 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) {
13204 if (reg != 0) {
13205 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg);
13206
13207 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG;
13208 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg;
13209 }
13210 }
13211
13212 link_status = bxe_pcie_capability_read(sc, PCIER_LINK_STA, 2);
13213
13214 /* handle PCIe 2.0 workarounds for 57710 */
13215 if (CHIP_IS_E1(sc)) {
13216 /* workaround for 57710 errata E4_57710_27462 */
13217 sc->devinfo.pcie_link_speed =
13218 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
13219
13220 /* workaround for 57710 errata E4_57710_27488 */
13221 sc->devinfo.pcie_link_width =
13222 ((link_status & PCIEM_LINK_STA_WIDTH) >> 4);
13223 if (sc->devinfo.pcie_link_speed > 1) {
13224 sc->devinfo.pcie_link_width =
13225 ((link_status & PCIEM_LINK_STA_WIDTH) >> 4) >> 1;
13226 }
13227 } else {
13228 sc->devinfo.pcie_link_speed =
13229 (link_status & PCIEM_LINK_STA_SPEED);
13230 sc->devinfo.pcie_link_width =
13231 ((link_status & PCIEM_LINK_STA_WIDTH) >> 4);
13232 }
13233
13234 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n",
13235 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
13236
13237 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
13238 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg;
13239
13240 /* check if MSI capability is enabled */
13241 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) {
13242 if (reg != 0) {
13243 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg);
13244
13245 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG;
13246 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg;
13247 }
13248 }
13249
13250 /* check if MSI-X capability is enabled */
13251 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) {
13252 if (reg != 0) {
13253 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg);
13254
13255 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
13256 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg;
13257 }
13258 }
13259 }
13260
13261 static int
bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc * sc)13262 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc)
13263 {
13264 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13265 uint32_t val;
13266
13267 /* get the outer vlan if we're in switch-dependent mode */
13268
13269 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13270 mf_info->ext_id = (uint16_t)val;
13271
13272 mf_info->multi_vnics_mode = 1;
13273
13274 if (!VALID_OVLAN(mf_info->ext_id)) {
13275 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id);
13276 return (1);
13277 }
13278
13279 /* get the capabilities */
13280 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13281 FUNC_MF_CFG_PROTOCOL_ISCSI) {
13282 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
13283 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13284 FUNC_MF_CFG_PROTOCOL_FCOE) {
13285 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
13286 } else {
13287 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
13288 }
13289
13290 mf_info->vnics_per_port =
13291 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13292
13293 return (0);
13294 }
13295
13296 static uint32_t
bxe_get_shmem_ext_proto_support_flags(struct bxe_softc * sc)13297 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc)
13298 {
13299 uint32_t retval = 0;
13300 uint32_t val;
13301
13302 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13303
13304 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
13305 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
13306 retval |= MF_PROTO_SUPPORT_ETHERNET;
13307 }
13308 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
13309 retval |= MF_PROTO_SUPPORT_ISCSI;
13310 }
13311 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
13312 retval |= MF_PROTO_SUPPORT_FCOE;
13313 }
13314 }
13315
13316 return (retval);
13317 }
13318
13319 static int
bxe_get_shmem_mf_cfg_info_si(struct bxe_softc * sc)13320 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc)
13321 {
13322 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13323 uint32_t val;
13324
13325 /*
13326 * There is no outer vlan if we're in switch-independent mode.
13327 * If the mac is valid then assume multi-function.
13328 */
13329
13330 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13331
13332 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
13333
13334 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13335
13336 mf_info->vnics_per_port =
13337 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13338
13339 return (0);
13340 }
13341
13342 static int
bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc * sc)13343 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc)
13344 {
13345 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13346 uint32_t e1hov_tag;
13347 uint32_t func_config;
13348 uint32_t niv_config;
13349
13350 mf_info->multi_vnics_mode = 1;
13351
13352 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13353 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13354 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
13355
13356 mf_info->ext_id =
13357 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
13358 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
13359
13360 mf_info->default_vlan =
13361 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
13362 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
13363
13364 mf_info->niv_allowed_priorities =
13365 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
13366 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
13367
13368 mf_info->niv_default_cos =
13369 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
13370 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
13371
13372 mf_info->afex_vlan_mode =
13373 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
13374 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
13375
13376 mf_info->niv_mba_enabled =
13377 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
13378 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
13379
13380 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13381
13382 mf_info->vnics_per_port =
13383 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13384
13385 return (0);
13386 }
13387
13388 static int
bxe_check_valid_mf_cfg(struct bxe_softc * sc)13389 bxe_check_valid_mf_cfg(struct bxe_softc *sc)
13390 {
13391 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13392 uint32_t mf_cfg1;
13393 uint32_t mf_cfg2;
13394 uint32_t ovlan1;
13395 uint32_t ovlan2;
13396 uint8_t i, j;
13397
13398 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n",
13399 SC_PORT(sc));
13400 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n",
13401 mf_info->mf_config[SC_VN(sc)]);
13402 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n",
13403 mf_info->multi_vnics_mode);
13404 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n",
13405 mf_info->vnics_per_port);
13406 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n",
13407 mf_info->ext_id);
13408 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n",
13409 mf_info->min_bw[0], mf_info->min_bw[1],
13410 mf_info->min_bw[2], mf_info->min_bw[3]);
13411 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n",
13412 mf_info->max_bw[0], mf_info->max_bw[1],
13413 mf_info->max_bw[2], mf_info->max_bw[3]);
13414 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n",
13415 sc->mac_addr_str);
13416
13417 /* various MF mode sanity checks... */
13418
13419 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
13420 BLOGE(sc, "Enumerated function %d is marked as hidden\n",
13421 SC_PORT(sc));
13422 return (1);
13423 }
13424
13425 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
13426 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n",
13427 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
13428 return (1);
13429 }
13430
13431 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13432 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
13433 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
13434 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n",
13435 SC_VN(sc), OVLAN(sc));
13436 return (1);
13437 }
13438
13439 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
13440 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n",
13441 mf_info->multi_vnics_mode, OVLAN(sc));
13442 return (1);
13443 }
13444
13445 /*
13446 * Verify all functions are either MF or SF mode. If MF, make sure
13447 * sure that all non-hidden functions have a valid ovlan. If SF,
13448 * make sure that all non-hidden functions have an invalid ovlan.
13449 */
13450 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13451 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13452 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13453 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13454 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) ||
13455 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) {
13456 BLOGE(sc, "mf_mode=SD function %d MF config "
13457 "mismatch, multi_vnics_mode=%d ovlan=%d\n",
13458 i, mf_info->multi_vnics_mode, ovlan1);
13459 return (1);
13460 }
13461 }
13462
13463 /* Verify all funcs on the same port each have a different ovlan. */
13464 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13465 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13466 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13467 /* iterate from the next function on the port to the max func */
13468 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
13469 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config);
13470 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
13471 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13472 VALID_OVLAN(ovlan1) &&
13473 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) &&
13474 VALID_OVLAN(ovlan2) &&
13475 (ovlan1 == ovlan2)) {
13476 BLOGE(sc, "mf_mode=SD functions %d and %d "
13477 "have the same ovlan (%d)\n",
13478 i, j, ovlan1);
13479 return (1);
13480 }
13481 }
13482 }
13483 } /* MULTI_FUNCTION_SD */
13484
13485 return (0);
13486 }
13487
13488 static int
bxe_get_mf_cfg_info(struct bxe_softc * sc)13489 bxe_get_mf_cfg_info(struct bxe_softc *sc)
13490 {
13491 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13492 uint32_t val, mac_upper;
13493 uint8_t i, vnic;
13494
13495 /* initialize mf_info defaults */
13496 mf_info->vnics_per_port = 1;
13497 mf_info->multi_vnics_mode = FALSE;
13498 mf_info->path_has_ovlan = FALSE;
13499 mf_info->mf_mode = SINGLE_FUNCTION;
13500
13501 if (!CHIP_IS_MF_CAP(sc)) {
13502 return (0);
13503 }
13504
13505 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
13506 BLOGE(sc, "Invalid mf_cfg_base!\n");
13507 return (1);
13508 }
13509
13510 /* get the MF mode (switch dependent / independent / single-function) */
13511
13512 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13513
13514 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)
13515 {
13516 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
13517
13518 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13519
13520 /* check for legal upper mac bytes */
13521 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
13522 mf_info->mf_mode = MULTI_FUNCTION_SI;
13523 } else {
13524 BLOGE(sc, "Invalid config for Switch Independent mode\n");
13525 }
13526
13527 break;
13528
13529 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
13530 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
13531
13532 /* get outer vlan configuration */
13533 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13534
13535 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
13536 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
13537 mf_info->mf_mode = MULTI_FUNCTION_SD;
13538 } else {
13539 BLOGE(sc, "Invalid config for Switch Dependent mode\n");
13540 }
13541
13542 break;
13543
13544 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
13545
13546 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
13547 return (0);
13548
13549 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
13550
13551 /*
13552 * Mark MF mode as NIV if MCP version includes NPAR-SD support
13553 * and the MAC address is valid.
13554 */
13555 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13556
13557 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
13558 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
13559 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
13560 } else {
13561 BLOGE(sc, "Invalid config for AFEX mode\n");
13562 }
13563
13564 break;
13565
13566 default:
13567
13568 BLOGE(sc, "Unknown MF mode (0x%08x)\n",
13569 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
13570
13571 return (1);
13572 }
13573
13574 /* set path mf_mode (which could be different than function mf_mode) */
13575 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13576 mf_info->path_has_ovlan = TRUE;
13577 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
13578 /*
13579 * Decide on path multi vnics mode. If we're not in MF mode and in
13580 * 4-port mode, this is good enough to check vnic-0 of the other port
13581 * on the same path
13582 */
13583 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13584 uint8_t other_port = !(PORT_ID(sc) & 1);
13585 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port));
13586
13587 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag);
13588
13589 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0;
13590 }
13591 }
13592
13593 if (mf_info->mf_mode == SINGLE_FUNCTION) {
13594 /* invalid MF config */
13595 if (SC_VN(sc) >= 1) {
13596 BLOGE(sc, "VNIC ID >= 1 in SF mode\n");
13597 return (1);
13598 }
13599
13600 return (0);
13601 }
13602
13603 /* get the MF configuration */
13604 mf_info->mf_config[SC_VN(sc)] =
13605 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13606
13607 switch(mf_info->mf_mode)
13608 {
13609 case MULTI_FUNCTION_SD:
13610
13611 bxe_get_shmem_mf_cfg_info_sd(sc);
13612 break;
13613
13614 case MULTI_FUNCTION_SI:
13615
13616 bxe_get_shmem_mf_cfg_info_si(sc);
13617 break;
13618
13619 case MULTI_FUNCTION_AFEX:
13620
13621 bxe_get_shmem_mf_cfg_info_niv(sc);
13622 break;
13623
13624 default:
13625
13626 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n",
13627 mf_info->mf_mode);
13628 return (1);
13629 }
13630
13631 /* get the congestion management parameters */
13632
13633 vnic = 0;
13634 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13635 /* get min/max bw */
13636 val = MFCFG_RD(sc, func_mf_config[i].config);
13637 mf_info->min_bw[vnic] =
13638 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT);
13639 mf_info->max_bw[vnic] =
13640 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT);
13641 vnic++;
13642 }
13643
13644 return (bxe_check_valid_mf_cfg(sc));
13645 }
13646
13647 static int
bxe_get_shmem_info(struct bxe_softc * sc)13648 bxe_get_shmem_info(struct bxe_softc *sc)
13649 {
13650 int port;
13651 uint32_t mac_hi, mac_lo, val;
13652
13653 port = SC_PORT(sc);
13654 mac_hi = mac_lo = 0;
13655
13656 sc->link_params.sc = sc;
13657 sc->link_params.port = port;
13658
13659 /* get the hardware config info */
13660 sc->devinfo.hw_config =
13661 SHMEM_RD(sc, dev_info.shared_hw_config.config);
13662 sc->devinfo.hw_config2 =
13663 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
13664
13665 sc->link_params.hw_led_mode =
13666 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
13667 SHARED_HW_CFG_LED_MODE_SHIFT);
13668
13669 /* get the port feature config */
13670 sc->port.config =
13671 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
13672
13673 /* get the link params */
13674 sc->link_params.speed_cap_mask[0] =
13675 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
13676 sc->link_params.speed_cap_mask[1] =
13677 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2);
13678
13679 /* get the lane config */
13680 sc->link_params.lane_config =
13681 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
13682
13683 /* get the link config */
13684 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
13685 sc->port.link_config[ELINK_INT_PHY] = val;
13686 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
13687 sc->port.link_config[ELINK_EXT_PHY1] =
13688 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
13689
13690 /* get the override preemphasis flag and enable it or turn it off */
13691 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13692 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
13693 sc->link_params.feature_config_flags |=
13694 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13695 } else {
13696 sc->link_params.feature_config_flags &=
13697 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13698 }
13699
13700 /* get the initial value of the link params */
13701 sc->link_params.multi_phy_config =
13702 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
13703
13704 /* get external phy info */
13705 sc->port.ext_phy_config =
13706 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
13707
13708 /* get the multifunction configuration */
13709 bxe_get_mf_cfg_info(sc);
13710
13711 /* get the mac address */
13712 if (IS_MF(sc)) {
13713 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13714 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
13715 } else {
13716 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
13717 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
13718 }
13719
13720 if ((mac_lo == 0) && (mac_hi == 0)) {
13721 *sc->mac_addr_str = 0;
13722 BLOGE(sc, "No Ethernet address programmed!\n");
13723 } else {
13724 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8);
13725 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi);
13726 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24);
13727 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16);
13728 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8);
13729 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo);
13730 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
13731 "%02x:%02x:%02x:%02x:%02x:%02x",
13732 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1],
13733 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3],
13734 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]);
13735 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str);
13736 }
13737
13738 return (0);
13739 }
13740
13741 static void
bxe_get_tunable_params(struct bxe_softc * sc)13742 bxe_get_tunable_params(struct bxe_softc *sc)
13743 {
13744 /* sanity checks */
13745
13746 if ((bxe_interrupt_mode != INTR_MODE_INTX) &&
13747 (bxe_interrupt_mode != INTR_MODE_MSI) &&
13748 (bxe_interrupt_mode != INTR_MODE_MSIX)) {
13749 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode);
13750 bxe_interrupt_mode = INTR_MODE_MSIX;
13751 }
13752
13753 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) {
13754 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count);
13755 bxe_queue_count = 0;
13756 }
13757
13758 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) {
13759 if (bxe_max_rx_bufs == 0) {
13760 bxe_max_rx_bufs = RX_BD_USABLE;
13761 } else {
13762 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs);
13763 bxe_max_rx_bufs = 2048;
13764 }
13765 }
13766
13767 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) {
13768 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks);
13769 bxe_hc_rx_ticks = 25;
13770 }
13771
13772 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) {
13773 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks);
13774 bxe_hc_tx_ticks = 50;
13775 }
13776
13777 if (bxe_max_aggregation_size == 0) {
13778 bxe_max_aggregation_size = TPA_AGG_SIZE;
13779 }
13780
13781 if (bxe_max_aggregation_size > 0xffff) {
13782 BLOGW(sc, "invalid max_aggregation_size (%d)\n",
13783 bxe_max_aggregation_size);
13784 bxe_max_aggregation_size = TPA_AGG_SIZE;
13785 }
13786
13787 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) {
13788 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs);
13789 bxe_mrrs = -1;
13790 }
13791
13792 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) {
13793 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen);
13794 bxe_autogreeen = 0;
13795 }
13796
13797 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) {
13798 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss);
13799 bxe_udp_rss = 0;
13800 }
13801
13802 /* pull in user settings */
13803
13804 sc->interrupt_mode = bxe_interrupt_mode;
13805 sc->max_rx_bufs = bxe_max_rx_bufs;
13806 sc->hc_rx_ticks = bxe_hc_rx_ticks;
13807 sc->hc_tx_ticks = bxe_hc_tx_ticks;
13808 sc->max_aggregation_size = bxe_max_aggregation_size;
13809 sc->mrrs = bxe_mrrs;
13810 sc->autogreeen = bxe_autogreeen;
13811 sc->udp_rss = bxe_udp_rss;
13812
13813 if (bxe_interrupt_mode == INTR_MODE_INTX) {
13814 sc->num_queues = 1;
13815 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */
13816 sc->num_queues =
13817 min((bxe_queue_count ? bxe_queue_count : mp_ncpus),
13818 MAX_RSS_CHAINS);
13819 if (sc->num_queues > mp_ncpus) {
13820 sc->num_queues = mp_ncpus;
13821 }
13822 }
13823
13824 BLOGD(sc, DBG_LOAD,
13825 "User Config: "
13826 "debug=0x%lx "
13827 "interrupt_mode=%d "
13828 "queue_count=%d "
13829 "hc_rx_ticks=%d "
13830 "hc_tx_ticks=%d "
13831 "rx_budget=%d "
13832 "max_aggregation_size=%d "
13833 "mrrs=%d "
13834 "autogreeen=%d "
13835 "udp_rss=%d\n",
13836 bxe_debug,
13837 sc->interrupt_mode,
13838 sc->num_queues,
13839 sc->hc_rx_ticks,
13840 sc->hc_tx_ticks,
13841 bxe_rx_budget,
13842 sc->max_aggregation_size,
13843 sc->mrrs,
13844 sc->autogreeen,
13845 sc->udp_rss);
13846 }
13847
13848 static int
bxe_media_detect(struct bxe_softc * sc)13849 bxe_media_detect(struct bxe_softc *sc)
13850 {
13851 int port_type;
13852 uint32_t phy_idx = bxe_get_cur_phy_idx(sc);
13853
13854 switch (sc->link_params.phy[phy_idx].media_type) {
13855 case ELINK_ETH_PHY_SFPP_10G_FIBER:
13856 case ELINK_ETH_PHY_XFP_FIBER:
13857 BLOGI(sc, "Found 10Gb Fiber media.\n");
13858 sc->media = IFM_10G_SR;
13859 port_type = PORT_FIBRE;
13860 break;
13861 case ELINK_ETH_PHY_SFP_1G_FIBER:
13862 BLOGI(sc, "Found 1Gb Fiber media.\n");
13863 sc->media = IFM_1000_SX;
13864 port_type = PORT_FIBRE;
13865 break;
13866 case ELINK_ETH_PHY_KR:
13867 case ELINK_ETH_PHY_CX4:
13868 BLOGI(sc, "Found 10GBase-CX4 media.\n");
13869 sc->media = IFM_10G_CX4;
13870 port_type = PORT_FIBRE;
13871 break;
13872 case ELINK_ETH_PHY_DA_TWINAX:
13873 BLOGI(sc, "Found 10Gb Twinax media.\n");
13874 sc->media = IFM_10G_TWINAX;
13875 port_type = PORT_DA;
13876 break;
13877 case ELINK_ETH_PHY_BASE_T:
13878 if (sc->link_params.speed_cap_mask[0] &
13879 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
13880 BLOGI(sc, "Found 10GBase-T media.\n");
13881 sc->media = IFM_10G_T;
13882 port_type = PORT_TP;
13883 } else {
13884 BLOGI(sc, "Found 1000Base-T media.\n");
13885 sc->media = IFM_1000_T;
13886 port_type = PORT_TP;
13887 }
13888 break;
13889 case ELINK_ETH_PHY_NOT_PRESENT:
13890 BLOGI(sc, "Media not present.\n");
13891 sc->media = 0;
13892 port_type = PORT_OTHER;
13893 break;
13894 case ELINK_ETH_PHY_UNSPECIFIED:
13895 default:
13896 BLOGI(sc, "Unknown media!\n");
13897 sc->media = 0;
13898 port_type = PORT_OTHER;
13899 break;
13900 }
13901 return port_type;
13902 }
13903
13904 #define GET_FIELD(value, fname) \
13905 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
13906 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
13907 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
13908
13909 static int
bxe_get_igu_cam_info(struct bxe_softc * sc)13910 bxe_get_igu_cam_info(struct bxe_softc *sc)
13911 {
13912 int pfid = SC_FUNC(sc);
13913 int igu_sb_id;
13914 uint32_t val;
13915 uint8_t fid, igu_sb_cnt = 0;
13916
13917 sc->igu_base_sb = 0xff;
13918
13919 if (CHIP_INT_MODE_IS_BC(sc)) {
13920 int vn = SC_VN(sc);
13921 igu_sb_cnt = sc->igu_sb_cnt;
13922 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
13923 FP_SB_MAX_E1x);
13924 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
13925 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
13926 return (0);
13927 }
13928
13929 /* IGU in normal mode - read CAM */
13930 for (igu_sb_id = 0;
13931 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
13932 igu_sb_id++) {
13933 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
13934 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
13935 continue;
13936 }
13937 fid = IGU_FID(val);
13938 if ((fid & IGU_FID_ENCODE_IS_PF)) {
13939 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
13940 continue;
13941 }
13942 if (IGU_VEC(val) == 0) {
13943 /* default status block */
13944 sc->igu_dsb_id = igu_sb_id;
13945 } else {
13946 if (sc->igu_base_sb == 0xff) {
13947 sc->igu_base_sb = igu_sb_id;
13948 }
13949 igu_sb_cnt++;
13950 }
13951 }
13952 }
13953
13954 /*
13955 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
13956 * that number of CAM entries will not be equal to the value advertised in
13957 * PCI. Driver should use the minimal value of both as the actual status
13958 * block count
13959 */
13960 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
13961
13962 if (igu_sb_cnt == 0) {
13963 BLOGE(sc, "CAM configuration error\n");
13964 return (-1);
13965 }
13966
13967 return (0);
13968 }
13969
13970 /*
13971 * Gather various information from the device config space, the device itself,
13972 * shmem, and the user input.
13973 */
13974 static int
bxe_get_device_info(struct bxe_softc * sc)13975 bxe_get_device_info(struct bxe_softc *sc)
13976 {
13977 uint32_t val;
13978 int rc;
13979
13980 /* Get the data for the device */
13981 sc->devinfo.vendor_id = pci_get_vendor(sc->dev);
13982 sc->devinfo.device_id = pci_get_device(sc->dev);
13983 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev);
13984 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev);
13985
13986 /* get the chip revision (chip metal comes from pci config space) */
13987 sc->devinfo.chip_id =
13988 sc->link_params.chip_id =
13989 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
13990 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
13991 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
13992 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
13993
13994 /* force 57811 according to MISC register */
13995 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
13996 if (CHIP_IS_57810(sc)) {
13997 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
13998 (sc->devinfo.chip_id & 0x0000ffff));
13999 } else if (CHIP_IS_57810_MF(sc)) {
14000 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
14001 (sc->devinfo.chip_id & 0x0000ffff));
14002 }
14003 sc->devinfo.chip_id |= 0x1;
14004 }
14005
14006 BLOGD(sc, DBG_LOAD,
14007 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n",
14008 sc->devinfo.chip_id,
14009 ((sc->devinfo.chip_id >> 16) & 0xffff),
14010 ((sc->devinfo.chip_id >> 12) & 0xf),
14011 ((sc->devinfo.chip_id >> 4) & 0xff),
14012 ((sc->devinfo.chip_id >> 0) & 0xf));
14013
14014 val = (REG_RD(sc, 0x2874) & 0x55);
14015 if ((sc->devinfo.chip_id & 0x1) ||
14016 (CHIP_IS_E1(sc) && val) ||
14017 (CHIP_IS_E1H(sc) && (val == 0x55))) {
14018 sc->flags |= BXE_ONE_PORT_FLAG;
14019 BLOGD(sc, DBG_LOAD, "single port device\n");
14020 }
14021
14022 /* set the doorbell size */
14023 sc->doorbell_size = (1 << BXE_DB_SHIFT);
14024
14025 /* determine whether the device is in 2 port or 4 port mode */
14026 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/
14027 if (CHIP_IS_E2E3(sc)) {
14028 /*
14029 * Read port4mode_en_ovwr[0]:
14030 * If 1, four port mode is in port4mode_en_ovwr[1].
14031 * If 0, four port mode is in port4mode_en[0].
14032 */
14033 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
14034 if (val & 1) {
14035 val = ((val >> 1) & 1);
14036 } else {
14037 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
14038 }
14039
14040 sc->devinfo.chip_port_mode =
14041 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
14042
14043 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2");
14044 }
14045
14046 /* get the function and path info for the device */
14047 bxe_get_function_num(sc);
14048
14049 /* get the shared memory base address */
14050 sc->devinfo.shmem_base =
14051 sc->link_params.shmem_base =
14052 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
14053 sc->devinfo.shmem2_base =
14054 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
14055 MISC_REG_GENERIC_CR_0));
14056
14057 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n",
14058 sc->devinfo.shmem_base, sc->devinfo.shmem2_base);
14059
14060 if (!sc->devinfo.shmem_base) {
14061 /* this should ONLY prevent upcoming shmem reads */
14062 BLOGI(sc, "MCP not active\n");
14063 sc->flags |= BXE_NO_MCP_FLAG;
14064 return (0);
14065 }
14066
14067 /* make sure the shared memory contents are valid */
14068 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
14069 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
14070 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
14071 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val);
14072 return (0);
14073 }
14074 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val);
14075
14076 /* get the bootcode version */
14077 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
14078 snprintf(sc->devinfo.bc_ver_str,
14079 sizeof(sc->devinfo.bc_ver_str),
14080 "%d.%d.%d",
14081 ((sc->devinfo.bc_ver >> 24) & 0xff),
14082 ((sc->devinfo.bc_ver >> 16) & 0xff),
14083 ((sc->devinfo.bc_ver >> 8) & 0xff));
14084 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str);
14085
14086 /* get the bootcode shmem address */
14087 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc);
14088 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base);
14089
14090 /* clean indirect addresses as they're not used */
14091 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
14092 if (IS_PF(sc)) {
14093 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
14094 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
14095 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
14096 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
14097 if (CHIP_IS_E1x(sc)) {
14098 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
14099 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
14100 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
14101 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
14102 }
14103
14104 /*
14105 * Enable internal target-read (in case we are probed after PF
14106 * FLR). Must be done prior to any BAR read access. Only for
14107 * 57712 and up
14108 */
14109 if (!CHIP_IS_E1x(sc)) {
14110 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
14111 }
14112 }
14113
14114 /* get the nvram size */
14115 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
14116 sc->devinfo.flash_size =
14117 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
14118 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size);
14119
14120 /* get PCI capabilites */
14121 bxe_probe_pci_caps(sc);
14122
14123 bxe_set_power_state(sc, PCI_PM_D0);
14124
14125 /* get various configuration parameters from shmem */
14126 bxe_get_shmem_info(sc);
14127
14128 if (sc->devinfo.pcie_msix_cap_reg != 0) {
14129 val = pci_read_config(sc->dev,
14130 (sc->devinfo.pcie_msix_cap_reg +
14131 PCIR_MSIX_CTRL),
14132 2);
14133 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
14134 } else {
14135 sc->igu_sb_cnt = 1;
14136 }
14137
14138 sc->igu_base_addr = BAR_IGU_INTMEM;
14139
14140 /* initialize IGU parameters */
14141 if (CHIP_IS_E1x(sc)) {
14142 sc->devinfo.int_block = INT_BLOCK_HC;
14143 sc->igu_dsb_id = DEF_SB_IGU_ID;
14144 sc->igu_base_sb = 0;
14145 } else {
14146 sc->devinfo.int_block = INT_BLOCK_IGU;
14147
14148 /* do not allow device reset during IGU info preocessing */
14149 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14150
14151 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
14152
14153 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
14154 int tout = 5000;
14155
14156 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n");
14157
14158 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
14159 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
14160 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
14161
14162 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14163 tout--;
14164 DELAY(1000);
14165 }
14166
14167 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14168 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n");
14169 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14170 return (-1);
14171 }
14172 }
14173
14174 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
14175 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n");
14176 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
14177 } else {
14178 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n");
14179 }
14180
14181 rc = bxe_get_igu_cam_info(sc);
14182
14183 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14184
14185 if (rc) {
14186 return (rc);
14187 }
14188 }
14189
14190 /*
14191 * Get base FW non-default (fast path) status block ID. This value is
14192 * used to initialize the fw_sb_id saved on the fp/queue structure to
14193 * determine the id used by the FW.
14194 */
14195 if (CHIP_IS_E1x(sc)) {
14196 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
14197 } else {
14198 /*
14199 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
14200 * the same queue are indicated on the same IGU SB). So we prefer
14201 * FW and IGU SBs to be the same value.
14202 */
14203 sc->base_fw_ndsb = sc->igu_base_sb;
14204 }
14205
14206 BLOGD(sc, DBG_LOAD,
14207 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n",
14208 sc->igu_dsb_id, sc->igu_base_sb,
14209 sc->igu_sb_cnt, sc->base_fw_ndsb);
14210
14211 elink_phy_probe(&sc->link_params);
14212
14213 return (0);
14214 }
14215
14216 static void
bxe_link_settings_supported(struct bxe_softc * sc,uint32_t switch_cfg)14217 bxe_link_settings_supported(struct bxe_softc *sc,
14218 uint32_t switch_cfg)
14219 {
14220 uint32_t cfg_size = 0;
14221 uint32_t idx;
14222 uint8_t port = SC_PORT(sc);
14223
14224 /* aggregation of supported attributes of all external phys */
14225 sc->port.supported[0] = 0;
14226 sc->port.supported[1] = 0;
14227
14228 switch (sc->link_params.num_phys) {
14229 case 1:
14230 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported;
14231 cfg_size = 1;
14232 break;
14233 case 2:
14234 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported;
14235 cfg_size = 1;
14236 break;
14237 case 3:
14238 if (sc->link_params.multi_phy_config &
14239 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
14240 sc->port.supported[1] =
14241 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14242 sc->port.supported[0] =
14243 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14244 } else {
14245 sc->port.supported[0] =
14246 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14247 sc->port.supported[1] =
14248 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14249 }
14250 cfg_size = 2;
14251 break;
14252 }
14253
14254 if (!(sc->port.supported[0] || sc->port.supported[1])) {
14255 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n",
14256 SHMEM_RD(sc,
14257 dev_info.port_hw_config[port].external_phy_config),
14258 SHMEM_RD(sc,
14259 dev_info.port_hw_config[port].external_phy_config2));
14260 return;
14261 }
14262
14263 if (CHIP_IS_E3(sc))
14264 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
14265 else {
14266 switch (switch_cfg) {
14267 case ELINK_SWITCH_CFG_1G:
14268 sc->port.phy_addr =
14269 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
14270 break;
14271 case ELINK_SWITCH_CFG_10G:
14272 sc->port.phy_addr =
14273 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
14274 break;
14275 default:
14276 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n",
14277 sc->port.link_config[0]);
14278 return;
14279 }
14280 }
14281
14282 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr);
14283
14284 /* mask what we support according to speed_cap_mask per configuration */
14285 for (idx = 0; idx < cfg_size; idx++) {
14286 if (!(sc->link_params.speed_cap_mask[idx] &
14287 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
14288 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half;
14289 }
14290
14291 if (!(sc->link_params.speed_cap_mask[idx] &
14292 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
14293 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full;
14294 }
14295
14296 if (!(sc->link_params.speed_cap_mask[idx] &
14297 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
14298 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half;
14299 }
14300
14301 if (!(sc->link_params.speed_cap_mask[idx] &
14302 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
14303 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full;
14304 }
14305
14306 if (!(sc->link_params.speed_cap_mask[idx] &
14307 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
14308 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full;
14309 }
14310
14311 if (!(sc->link_params.speed_cap_mask[idx] &
14312 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
14313 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full;
14314 }
14315
14316 if (!(sc->link_params.speed_cap_mask[idx] &
14317 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
14318 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full;
14319 }
14320
14321 if (!(sc->link_params.speed_cap_mask[idx] &
14322 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
14323 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full;
14324 }
14325 }
14326
14327 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n",
14328 sc->port.supported[0], sc->port.supported[1]);
14329 ELINK_DEBUG_P2(sc, "PHY supported 0=0x%08x 1=0x%08x\n",
14330 sc->port.supported[0], sc->port.supported[1]);
14331 }
14332
14333 static void
bxe_link_settings_requested(struct bxe_softc * sc)14334 bxe_link_settings_requested(struct bxe_softc *sc)
14335 {
14336 uint32_t link_config;
14337 uint32_t idx;
14338 uint32_t cfg_size = 0;
14339
14340 sc->port.advertising[0] = 0;
14341 sc->port.advertising[1] = 0;
14342
14343 switch (sc->link_params.num_phys) {
14344 case 1:
14345 case 2:
14346 cfg_size = 1;
14347 break;
14348 case 3:
14349 cfg_size = 2;
14350 break;
14351 }
14352
14353 for (idx = 0; idx < cfg_size; idx++) {
14354 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
14355 link_config = sc->port.link_config[idx];
14356
14357 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
14358 case PORT_FEATURE_LINK_SPEED_AUTO:
14359 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
14360 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14361 sc->port.advertising[idx] |= sc->port.supported[idx];
14362 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
14363 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
14364 sc->port.advertising[idx] |=
14365 (ELINK_SUPPORTED_100baseT_Half |
14366 ELINK_SUPPORTED_100baseT_Full);
14367 } else {
14368 /* force 10G, no AN */
14369 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14370 sc->port.advertising[idx] |=
14371 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
14372 continue;
14373 }
14374 break;
14375
14376 case PORT_FEATURE_LINK_SPEED_10M_FULL:
14377 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) {
14378 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14379 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full |
14380 ADVERTISED_TP);
14381 } else {
14382 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14383 "speed_cap_mask=0x%08x\n",
14384 link_config, sc->link_params.speed_cap_mask[idx]);
14385 return;
14386 }
14387 break;
14388
14389 case PORT_FEATURE_LINK_SPEED_10M_HALF:
14390 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) {
14391 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14392 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14393 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half |
14394 ADVERTISED_TP);
14395 ELINK_DEBUG_P1(sc, "driver requesting DUPLEX_HALF req_duplex = %x!\n",
14396 sc->link_params.req_duplex[idx]);
14397 } else {
14398 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14399 "speed_cap_mask=0x%08x\n",
14400 link_config, sc->link_params.speed_cap_mask[idx]);
14401 return;
14402 }
14403 break;
14404
14405 case PORT_FEATURE_LINK_SPEED_100M_FULL:
14406 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) {
14407 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14408 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full |
14409 ADVERTISED_TP);
14410 } else {
14411 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14412 "speed_cap_mask=0x%08x\n",
14413 link_config, sc->link_params.speed_cap_mask[idx]);
14414 return;
14415 }
14416 break;
14417
14418 case PORT_FEATURE_LINK_SPEED_100M_HALF:
14419 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) {
14420 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14421 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14422 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half |
14423 ADVERTISED_TP);
14424 } else {
14425 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14426 "speed_cap_mask=0x%08x\n",
14427 link_config, sc->link_params.speed_cap_mask[idx]);
14428 return;
14429 }
14430 break;
14431
14432 case PORT_FEATURE_LINK_SPEED_1G:
14433 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) {
14434 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000;
14435 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full |
14436 ADVERTISED_TP);
14437 } else {
14438 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14439 "speed_cap_mask=0x%08x\n",
14440 link_config, sc->link_params.speed_cap_mask[idx]);
14441 return;
14442 }
14443 break;
14444
14445 case PORT_FEATURE_LINK_SPEED_2_5G:
14446 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) {
14447 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500;
14448 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full |
14449 ADVERTISED_TP);
14450 } else {
14451 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14452 "speed_cap_mask=0x%08x\n",
14453 link_config, sc->link_params.speed_cap_mask[idx]);
14454 return;
14455 }
14456 break;
14457
14458 case PORT_FEATURE_LINK_SPEED_10G_CX4:
14459 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) {
14460 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14461 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full |
14462 ADVERTISED_FIBRE);
14463 } else {
14464 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14465 "speed_cap_mask=0x%08x\n",
14466 link_config, sc->link_params.speed_cap_mask[idx]);
14467 return;
14468 }
14469 break;
14470
14471 case PORT_FEATURE_LINK_SPEED_20G:
14472 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
14473 break;
14474
14475 default:
14476 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14477 "speed_cap_mask=0x%08x\n",
14478 link_config, sc->link_params.speed_cap_mask[idx]);
14479 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14480 sc->port.advertising[idx] = sc->port.supported[idx];
14481 break;
14482 }
14483
14484 sc->link_params.req_flow_ctrl[idx] =
14485 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
14486
14487 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
14488 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
14489 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE;
14490 } else {
14491 bxe_set_requested_fc(sc);
14492 }
14493 }
14494
14495 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d "
14496 "req_flow_ctrl=0x%x advertising=0x%x\n",
14497 sc->link_params.req_line_speed[idx],
14498 sc->link_params.req_duplex[idx],
14499 sc->link_params.req_flow_ctrl[idx],
14500 sc->port.advertising[idx]);
14501 ELINK_DEBUG_P3(sc, "req_line_speed=%d req_duplex=%d "
14502 "advertising=0x%x\n",
14503 sc->link_params.req_line_speed[idx],
14504 sc->link_params.req_duplex[idx],
14505 sc->port.advertising[idx]);
14506 }
14507 }
14508
14509 static void
bxe_get_phy_info(struct bxe_softc * sc)14510 bxe_get_phy_info(struct bxe_softc *sc)
14511 {
14512 uint8_t port = SC_PORT(sc);
14513 uint32_t config = sc->port.config;
14514 uint32_t eee_mode;
14515
14516 /* shmem data already read in bxe_get_shmem_info() */
14517
14518 ELINK_DEBUG_P3(sc, "lane_config=0x%08x speed_cap_mask0=0x%08x "
14519 "link_config0=0x%08x\n",
14520 sc->link_params.lane_config,
14521 sc->link_params.speed_cap_mask[0],
14522 sc->port.link_config[0]);
14523
14524
14525 bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
14526 bxe_link_settings_requested(sc);
14527
14528 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) {
14529 sc->link_params.feature_config_flags |=
14530 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14531 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) {
14532 sc->link_params.feature_config_flags &=
14533 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14534 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) {
14535 sc->link_params.feature_config_flags |=
14536 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14537 }
14538
14539 /* configure link feature according to nvram value */
14540 eee_mode =
14541 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) &
14542 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
14543 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
14544 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
14545 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
14546 ELINK_EEE_MODE_ENABLE_LPI |
14547 ELINK_EEE_MODE_OUTPUT_TIME);
14548 } else {
14549 sc->link_params.eee_mode = 0;
14550 }
14551
14552 /* get the media type */
14553 bxe_media_detect(sc);
14554 ELINK_DEBUG_P1(sc, "detected media type\n", sc->media);
14555 }
14556
14557 static void
bxe_get_params(struct bxe_softc * sc)14558 bxe_get_params(struct bxe_softc *sc)
14559 {
14560 /* get user tunable params */
14561 bxe_get_tunable_params(sc);
14562
14563 /* select the RX and TX ring sizes */
14564 sc->tx_ring_size = TX_BD_USABLE;
14565 sc->rx_ring_size = RX_BD_USABLE;
14566
14567 /* XXX disable WoL */
14568 sc->wol = 0;
14569 }
14570
14571 static void
bxe_set_modes_bitmap(struct bxe_softc * sc)14572 bxe_set_modes_bitmap(struct bxe_softc *sc)
14573 {
14574 uint32_t flags = 0;
14575
14576 if (CHIP_REV_IS_FPGA(sc)) {
14577 SET_FLAGS(flags, MODE_FPGA);
14578 } else if (CHIP_REV_IS_EMUL(sc)) {
14579 SET_FLAGS(flags, MODE_EMUL);
14580 } else {
14581 SET_FLAGS(flags, MODE_ASIC);
14582 }
14583
14584 if (CHIP_IS_MODE_4_PORT(sc)) {
14585 SET_FLAGS(flags, MODE_PORT4);
14586 } else {
14587 SET_FLAGS(flags, MODE_PORT2);
14588 }
14589
14590 if (CHIP_IS_E2(sc)) {
14591 SET_FLAGS(flags, MODE_E2);
14592 } else if (CHIP_IS_E3(sc)) {
14593 SET_FLAGS(flags, MODE_E3);
14594 if (CHIP_REV(sc) == CHIP_REV_Ax) {
14595 SET_FLAGS(flags, MODE_E3_A0);
14596 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ {
14597 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
14598 }
14599 }
14600
14601 if (IS_MF(sc)) {
14602 SET_FLAGS(flags, MODE_MF);
14603 switch (sc->devinfo.mf_info.mf_mode) {
14604 case MULTI_FUNCTION_SD:
14605 SET_FLAGS(flags, MODE_MF_SD);
14606 break;
14607 case MULTI_FUNCTION_SI:
14608 SET_FLAGS(flags, MODE_MF_SI);
14609 break;
14610 case MULTI_FUNCTION_AFEX:
14611 SET_FLAGS(flags, MODE_MF_AFEX);
14612 break;
14613 }
14614 } else {
14615 SET_FLAGS(flags, MODE_SF);
14616 }
14617
14618 #if defined(__LITTLE_ENDIAN)
14619 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
14620 #else /* __BIG_ENDIAN */
14621 SET_FLAGS(flags, MODE_BIG_ENDIAN);
14622 #endif
14623
14624 INIT_MODE_FLAGS(sc) = flags;
14625 }
14626
14627 static int
bxe_alloc_hsi_mem(struct bxe_softc * sc)14628 bxe_alloc_hsi_mem(struct bxe_softc *sc)
14629 {
14630 struct bxe_fastpath *fp;
14631 bus_addr_t busaddr;
14632 int max_agg_queues;
14633 int max_segments;
14634 bus_size_t max_size;
14635 bus_size_t max_seg_size;
14636 char buf[32];
14637 int rc;
14638 int i, j;
14639
14640 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */
14641
14642 /* allocate the parent bus DMA tag */
14643 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */
14644 1, /* alignment */
14645 0, /* boundary limit */
14646 BUS_SPACE_MAXADDR, /* restricted low */
14647 BUS_SPACE_MAXADDR, /* restricted hi */
14648 NULL, /* addr filter() */
14649 NULL, /* addr filter() arg */
14650 BUS_SPACE_MAXSIZE_32BIT, /* max map size */
14651 BUS_SPACE_UNRESTRICTED, /* num discontinuous */
14652 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */
14653 0, /* flags */
14654 NULL, /* lock() */
14655 NULL, /* lock() arg */
14656 &sc->parent_dma_tag); /* returned dma tag */
14657 if (rc != 0) {
14658 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc);
14659 return (1);
14660 }
14661
14662 /************************/
14663 /* DEFAULT STATUS BLOCK */
14664 /************************/
14665
14666 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block),
14667 &sc->def_sb_dma, "default status block") != 0) {
14668 /* XXX */
14669 bus_dma_tag_destroy(sc->parent_dma_tag);
14670 return (1);
14671 }
14672
14673 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
14674
14675 /***************/
14676 /* EVENT QUEUE */
14677 /***************/
14678
14679 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14680 &sc->eq_dma, "event queue") != 0) {
14681 /* XXX */
14682 bxe_dma_free(sc, &sc->def_sb_dma);
14683 sc->def_sb = NULL;
14684 bus_dma_tag_destroy(sc->parent_dma_tag);
14685 return (1);
14686 }
14687
14688 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr;
14689
14690 /*************/
14691 /* SLOW PATH */
14692 /*************/
14693
14694 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath),
14695 &sc->sp_dma, "slow path") != 0) {
14696 /* XXX */
14697 bxe_dma_free(sc, &sc->eq_dma);
14698 sc->eq = NULL;
14699 bxe_dma_free(sc, &sc->def_sb_dma);
14700 sc->def_sb = NULL;
14701 bus_dma_tag_destroy(sc->parent_dma_tag);
14702 return (1);
14703 }
14704
14705 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr;
14706
14707 /*******************/
14708 /* SLOW PATH QUEUE */
14709 /*******************/
14710
14711 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14712 &sc->spq_dma, "slow path queue") != 0) {
14713 /* XXX */
14714 bxe_dma_free(sc, &sc->sp_dma);
14715 sc->sp = NULL;
14716 bxe_dma_free(sc, &sc->eq_dma);
14717 sc->eq = NULL;
14718 bxe_dma_free(sc, &sc->def_sb_dma);
14719 sc->def_sb = NULL;
14720 bus_dma_tag_destroy(sc->parent_dma_tag);
14721 return (1);
14722 }
14723
14724 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
14725
14726 /***************************/
14727 /* FW DECOMPRESSION BUFFER */
14728 /***************************/
14729
14730 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
14731 "fw decompression buffer") != 0) {
14732 /* XXX */
14733 bxe_dma_free(sc, &sc->spq_dma);
14734 sc->spq = NULL;
14735 bxe_dma_free(sc, &sc->sp_dma);
14736 sc->sp = NULL;
14737 bxe_dma_free(sc, &sc->eq_dma);
14738 sc->eq = NULL;
14739 bxe_dma_free(sc, &sc->def_sb_dma);
14740 sc->def_sb = NULL;
14741 bus_dma_tag_destroy(sc->parent_dma_tag);
14742 return (1);
14743 }
14744
14745 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
14746
14747 if ((sc->gz_strm =
14748 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) {
14749 /* XXX */
14750 bxe_dma_free(sc, &sc->gz_buf_dma);
14751 sc->gz_buf = NULL;
14752 bxe_dma_free(sc, &sc->spq_dma);
14753 sc->spq = NULL;
14754 bxe_dma_free(sc, &sc->sp_dma);
14755 sc->sp = NULL;
14756 bxe_dma_free(sc, &sc->eq_dma);
14757 sc->eq = NULL;
14758 bxe_dma_free(sc, &sc->def_sb_dma);
14759 sc->def_sb = NULL;
14760 bus_dma_tag_destroy(sc->parent_dma_tag);
14761 return (1);
14762 }
14763
14764 /*************/
14765 /* FASTPATHS */
14766 /*************/
14767
14768 /* allocate DMA memory for each fastpath structure */
14769 for (i = 0; i < sc->num_queues; i++) {
14770 fp = &sc->fp[i];
14771 fp->sc = sc;
14772 fp->index = i;
14773
14774 /*******************/
14775 /* FP STATUS BLOCK */
14776 /*******************/
14777
14778 snprintf(buf, sizeof(buf), "fp %d status block", i);
14779 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block),
14780 &fp->sb_dma, buf) != 0) {
14781 /* XXX unwind and free previous fastpath allocations */
14782 BLOGE(sc, "Failed to alloc %s\n", buf);
14783 return (1);
14784 } else {
14785 if (CHIP_IS_E2E3(sc)) {
14786 fp->status_block.e2_sb =
14787 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr;
14788 } else {
14789 fp->status_block.e1x_sb =
14790 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr;
14791 }
14792 }
14793
14794 /******************/
14795 /* FP TX BD CHAIN */
14796 /******************/
14797
14798 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i);
14799 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES),
14800 &fp->tx_dma, buf) != 0) {
14801 /* XXX unwind and free previous fastpath allocations */
14802 BLOGE(sc, "Failed to alloc %s\n", buf);
14803 return (1);
14804 } else {
14805 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr;
14806 }
14807
14808 /* link together the tx bd chain pages */
14809 for (j = 1; j <= TX_BD_NUM_PAGES; j++) {
14810 /* index into the tx bd chain array to last entry per page */
14811 struct eth_tx_next_bd *tx_next_bd =
14812 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd;
14813 /* point to the next page and wrap from last page */
14814 busaddr = (fp->tx_dma.paddr +
14815 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES)));
14816 tx_next_bd->addr_hi = htole32(U64_HI(busaddr));
14817 tx_next_bd->addr_lo = htole32(U64_LO(busaddr));
14818 }
14819
14820 /******************/
14821 /* FP RX BD CHAIN */
14822 /******************/
14823
14824 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i);
14825 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES),
14826 &fp->rx_dma, buf) != 0) {
14827 /* XXX unwind and free previous fastpath allocations */
14828 BLOGE(sc, "Failed to alloc %s\n", buf);
14829 return (1);
14830 } else {
14831 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr;
14832 }
14833
14834 /* link together the rx bd chain pages */
14835 for (j = 1; j <= RX_BD_NUM_PAGES; j++) {
14836 /* index into the rx bd chain array to last entry per page */
14837 struct eth_rx_bd *rx_bd =
14838 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2];
14839 /* point to the next page and wrap from last page */
14840 busaddr = (fp->rx_dma.paddr +
14841 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES)));
14842 rx_bd->addr_hi = htole32(U64_HI(busaddr));
14843 rx_bd->addr_lo = htole32(U64_LO(busaddr));
14844 }
14845
14846 /*******************/
14847 /* FP RX RCQ CHAIN */
14848 /*******************/
14849
14850 snprintf(buf, sizeof(buf), "fp %d rcq chain", i);
14851 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES),
14852 &fp->rcq_dma, buf) != 0) {
14853 /* XXX unwind and free previous fastpath allocations */
14854 BLOGE(sc, "Failed to alloc %s\n", buf);
14855 return (1);
14856 } else {
14857 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr;
14858 }
14859
14860 /* link together the rcq chain pages */
14861 for (j = 1; j <= RCQ_NUM_PAGES; j++) {
14862 /* index into the rcq chain array to last entry per page */
14863 struct eth_rx_cqe_next_page *rx_cqe_next =
14864 (struct eth_rx_cqe_next_page *)
14865 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1];
14866 /* point to the next page and wrap from last page */
14867 busaddr = (fp->rcq_dma.paddr +
14868 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES)));
14869 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr));
14870 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr));
14871 }
14872
14873 /*******************/
14874 /* FP RX SGE CHAIN */
14875 /*******************/
14876
14877 snprintf(buf, sizeof(buf), "fp %d sge chain", i);
14878 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES),
14879 &fp->rx_sge_dma, buf) != 0) {
14880 /* XXX unwind and free previous fastpath allocations */
14881 BLOGE(sc, "Failed to alloc %s\n", buf);
14882 return (1);
14883 } else {
14884 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr;
14885 }
14886
14887 /* link together the sge chain pages */
14888 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) {
14889 /* index into the rcq chain array to last entry per page */
14890 struct eth_rx_sge *rx_sge =
14891 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2];
14892 /* point to the next page and wrap from last page */
14893 busaddr = (fp->rx_sge_dma.paddr +
14894 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES)));
14895 rx_sge->addr_hi = htole32(U64_HI(busaddr));
14896 rx_sge->addr_lo = htole32(U64_LO(busaddr));
14897 }
14898
14899 /***********************/
14900 /* FP TX MBUF DMA MAPS */
14901 /***********************/
14902
14903 /* set required sizes before mapping to conserve resources */
14904 if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) {
14905 max_size = BXE_TSO_MAX_SIZE;
14906 max_segments = BXE_TSO_MAX_SEGMENTS;
14907 max_seg_size = BXE_TSO_MAX_SEG_SIZE;
14908 } else {
14909 max_size = (MCLBYTES * BXE_MAX_SEGMENTS);
14910 max_segments = BXE_MAX_SEGMENTS;
14911 max_seg_size = MCLBYTES;
14912 }
14913
14914 /* create a dma tag for the tx mbufs */
14915 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14916 1, /* alignment */
14917 0, /* boundary limit */
14918 BUS_SPACE_MAXADDR, /* restricted low */
14919 BUS_SPACE_MAXADDR, /* restricted hi */
14920 NULL, /* addr filter() */
14921 NULL, /* addr filter() arg */
14922 max_size, /* max map size */
14923 max_segments, /* num discontinuous */
14924 max_seg_size, /* max seg size */
14925 0, /* flags */
14926 NULL, /* lock() */
14927 NULL, /* lock() arg */
14928 &fp->tx_mbuf_tag); /* returned dma tag */
14929 if (rc != 0) {
14930 /* XXX unwind and free previous fastpath allocations */
14931 BLOGE(sc, "Failed to create dma tag for "
14932 "'fp %d tx mbufs' (%d)\n", i, rc);
14933 return (1);
14934 }
14935
14936 /* create dma maps for each of the tx mbuf clusters */
14937 for (j = 0; j < TX_BD_TOTAL; j++) {
14938 if (bus_dmamap_create(fp->tx_mbuf_tag,
14939 BUS_DMA_NOWAIT,
14940 &fp->tx_mbuf_chain[j].m_map)) {
14941 /* XXX unwind and free previous fastpath allocations */
14942 BLOGE(sc, "Failed to create dma map for "
14943 "'fp %d tx mbuf %d' (%d)\n", i, j, rc);
14944 return (1);
14945 }
14946 }
14947
14948 /***********************/
14949 /* FP RX MBUF DMA MAPS */
14950 /***********************/
14951
14952 /* create a dma tag for the rx mbufs */
14953 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14954 1, /* alignment */
14955 0, /* boundary limit */
14956 BUS_SPACE_MAXADDR, /* restricted low */
14957 BUS_SPACE_MAXADDR, /* restricted hi */
14958 NULL, /* addr filter() */
14959 NULL, /* addr filter() arg */
14960 MJUM9BYTES, /* max map size */
14961 1, /* num discontinuous */
14962 MJUM9BYTES, /* max seg size */
14963 0, /* flags */
14964 NULL, /* lock() */
14965 NULL, /* lock() arg */
14966 &fp->rx_mbuf_tag); /* returned dma tag */
14967 if (rc != 0) {
14968 /* XXX unwind and free previous fastpath allocations */
14969 BLOGE(sc, "Failed to create dma tag for "
14970 "'fp %d rx mbufs' (%d)\n", i, rc);
14971 return (1);
14972 }
14973
14974 /* create dma maps for each of the rx mbuf clusters */
14975 for (j = 0; j < RX_BD_TOTAL; j++) {
14976 if (bus_dmamap_create(fp->rx_mbuf_tag,
14977 BUS_DMA_NOWAIT,
14978 &fp->rx_mbuf_chain[j].m_map)) {
14979 /* XXX unwind and free previous fastpath allocations */
14980 BLOGE(sc, "Failed to create dma map for "
14981 "'fp %d rx mbuf %d' (%d)\n", i, j, rc);
14982 return (1);
14983 }
14984 }
14985
14986 /* create dma map for the spare rx mbuf cluster */
14987 if (bus_dmamap_create(fp->rx_mbuf_tag,
14988 BUS_DMA_NOWAIT,
14989 &fp->rx_mbuf_spare_map)) {
14990 /* XXX unwind and free previous fastpath allocations */
14991 BLOGE(sc, "Failed to create dma map for "
14992 "'fp %d spare rx mbuf' (%d)\n", i, rc);
14993 return (1);
14994 }
14995
14996 /***************************/
14997 /* FP RX SGE MBUF DMA MAPS */
14998 /***************************/
14999
15000 /* create a dma tag for the rx sge mbufs */
15001 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
15002 1, /* alignment */
15003 0, /* boundary limit */
15004 BUS_SPACE_MAXADDR, /* restricted low */
15005 BUS_SPACE_MAXADDR, /* restricted hi */
15006 NULL, /* addr filter() */
15007 NULL, /* addr filter() arg */
15008 BCM_PAGE_SIZE, /* max map size */
15009 1, /* num discontinuous */
15010 BCM_PAGE_SIZE, /* max seg size */
15011 0, /* flags */
15012 NULL, /* lock() */
15013 NULL, /* lock() arg */
15014 &fp->rx_sge_mbuf_tag); /* returned dma tag */
15015 if (rc != 0) {
15016 /* XXX unwind and free previous fastpath allocations */
15017 BLOGE(sc, "Failed to create dma tag for "
15018 "'fp %d rx sge mbufs' (%d)\n", i, rc);
15019 return (1);
15020 }
15021
15022 /* create dma maps for the rx sge mbuf clusters */
15023 for (j = 0; j < RX_SGE_TOTAL; j++) {
15024 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
15025 BUS_DMA_NOWAIT,
15026 &fp->rx_sge_mbuf_chain[j].m_map)) {
15027 /* XXX unwind and free previous fastpath allocations */
15028 BLOGE(sc, "Failed to create dma map for "
15029 "'fp %d rx sge mbuf %d' (%d)\n", i, j, rc);
15030 return (1);
15031 }
15032 }
15033
15034 /* create dma map for the spare rx sge mbuf cluster */
15035 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
15036 BUS_DMA_NOWAIT,
15037 &fp->rx_sge_mbuf_spare_map)) {
15038 /* XXX unwind and free previous fastpath allocations */
15039 BLOGE(sc, "Failed to create dma map for "
15040 "'fp %d spare rx sge mbuf' (%d)\n", i, rc);
15041 return (1);
15042 }
15043
15044 /***************************/
15045 /* FP RX TPA MBUF DMA MAPS */
15046 /***************************/
15047
15048 /* create dma maps for the rx tpa mbuf clusters */
15049 max_agg_queues = MAX_AGG_QS(sc);
15050
15051 for (j = 0; j < max_agg_queues; j++) {
15052 if (bus_dmamap_create(fp->rx_mbuf_tag,
15053 BUS_DMA_NOWAIT,
15054 &fp->rx_tpa_info[j].bd.m_map)) {
15055 /* XXX unwind and free previous fastpath allocations */
15056 BLOGE(sc, "Failed to create dma map for "
15057 "'fp %d rx tpa mbuf %d' (%d)\n", i, j, rc);
15058 return (1);
15059 }
15060 }
15061
15062 /* create dma map for the spare rx tpa mbuf cluster */
15063 if (bus_dmamap_create(fp->rx_mbuf_tag,
15064 BUS_DMA_NOWAIT,
15065 &fp->rx_tpa_info_mbuf_spare_map)) {
15066 /* XXX unwind and free previous fastpath allocations */
15067 BLOGE(sc, "Failed to create dma map for "
15068 "'fp %d spare rx tpa mbuf' (%d)\n", i, rc);
15069 return (1);
15070 }
15071
15072 bxe_init_sge_ring_bit_mask(fp);
15073 }
15074
15075 return (0);
15076 }
15077
15078 static void
bxe_free_hsi_mem(struct bxe_softc * sc)15079 bxe_free_hsi_mem(struct bxe_softc *sc)
15080 {
15081 struct bxe_fastpath *fp;
15082 int max_agg_queues;
15083 int i, j;
15084
15085 if (sc->parent_dma_tag == NULL) {
15086 return; /* assume nothing was allocated */
15087 }
15088
15089 for (i = 0; i < sc->num_queues; i++) {
15090 fp = &sc->fp[i];
15091
15092 /*******************/
15093 /* FP STATUS BLOCK */
15094 /*******************/
15095
15096 bxe_dma_free(sc, &fp->sb_dma);
15097 memset(&fp->status_block, 0, sizeof(fp->status_block));
15098
15099 /******************/
15100 /* FP TX BD CHAIN */
15101 /******************/
15102
15103 bxe_dma_free(sc, &fp->tx_dma);
15104 fp->tx_chain = NULL;
15105
15106 /******************/
15107 /* FP RX BD CHAIN */
15108 /******************/
15109
15110 bxe_dma_free(sc, &fp->rx_dma);
15111 fp->rx_chain = NULL;
15112
15113 /*******************/
15114 /* FP RX RCQ CHAIN */
15115 /*******************/
15116
15117 bxe_dma_free(sc, &fp->rcq_dma);
15118 fp->rcq_chain = NULL;
15119
15120 /*******************/
15121 /* FP RX SGE CHAIN */
15122 /*******************/
15123
15124 bxe_dma_free(sc, &fp->rx_sge_dma);
15125 fp->rx_sge_chain = NULL;
15126
15127 /***********************/
15128 /* FP TX MBUF DMA MAPS */
15129 /***********************/
15130
15131 if (fp->tx_mbuf_tag != NULL) {
15132 for (j = 0; j < TX_BD_TOTAL; j++) {
15133 if (fp->tx_mbuf_chain[j].m_map != NULL) {
15134 bus_dmamap_unload(fp->tx_mbuf_tag,
15135 fp->tx_mbuf_chain[j].m_map);
15136 bus_dmamap_destroy(fp->tx_mbuf_tag,
15137 fp->tx_mbuf_chain[j].m_map);
15138 }
15139 }
15140
15141 bus_dma_tag_destroy(fp->tx_mbuf_tag);
15142 fp->tx_mbuf_tag = NULL;
15143 }
15144
15145 /***********************/
15146 /* FP RX MBUF DMA MAPS */
15147 /***********************/
15148
15149 if (fp->rx_mbuf_tag != NULL) {
15150 for (j = 0; j < RX_BD_TOTAL; j++) {
15151 if (fp->rx_mbuf_chain[j].m_map != NULL) {
15152 bus_dmamap_unload(fp->rx_mbuf_tag,
15153 fp->rx_mbuf_chain[j].m_map);
15154 bus_dmamap_destroy(fp->rx_mbuf_tag,
15155 fp->rx_mbuf_chain[j].m_map);
15156 }
15157 }
15158
15159 if (fp->rx_mbuf_spare_map != NULL) {
15160 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
15161 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
15162 }
15163
15164 /***************************/
15165 /* FP RX TPA MBUF DMA MAPS */
15166 /***************************/
15167
15168 max_agg_queues = MAX_AGG_QS(sc);
15169
15170 for (j = 0; j < max_agg_queues; j++) {
15171 if (fp->rx_tpa_info[j].bd.m_map != NULL) {
15172 bus_dmamap_unload(fp->rx_mbuf_tag,
15173 fp->rx_tpa_info[j].bd.m_map);
15174 bus_dmamap_destroy(fp->rx_mbuf_tag,
15175 fp->rx_tpa_info[j].bd.m_map);
15176 }
15177 }
15178
15179 if (fp->rx_tpa_info_mbuf_spare_map != NULL) {
15180 bus_dmamap_unload(fp->rx_mbuf_tag,
15181 fp->rx_tpa_info_mbuf_spare_map);
15182 bus_dmamap_destroy(fp->rx_mbuf_tag,
15183 fp->rx_tpa_info_mbuf_spare_map);
15184 }
15185
15186 bus_dma_tag_destroy(fp->rx_mbuf_tag);
15187 fp->rx_mbuf_tag = NULL;
15188 }
15189
15190 /***************************/
15191 /* FP RX SGE MBUF DMA MAPS */
15192 /***************************/
15193
15194 if (fp->rx_sge_mbuf_tag != NULL) {
15195 for (j = 0; j < RX_SGE_TOTAL; j++) {
15196 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) {
15197 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15198 fp->rx_sge_mbuf_chain[j].m_map);
15199 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15200 fp->rx_sge_mbuf_chain[j].m_map);
15201 }
15202 }
15203
15204 if (fp->rx_sge_mbuf_spare_map != NULL) {
15205 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15206 fp->rx_sge_mbuf_spare_map);
15207 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15208 fp->rx_sge_mbuf_spare_map);
15209 }
15210
15211 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag);
15212 fp->rx_sge_mbuf_tag = NULL;
15213 }
15214 }
15215
15216 /***************************/
15217 /* FW DECOMPRESSION BUFFER */
15218 /***************************/
15219
15220 bxe_dma_free(sc, &sc->gz_buf_dma);
15221 sc->gz_buf = NULL;
15222 free(sc->gz_strm, M_DEVBUF);
15223 sc->gz_strm = NULL;
15224
15225 /*******************/
15226 /* SLOW PATH QUEUE */
15227 /*******************/
15228
15229 bxe_dma_free(sc, &sc->spq_dma);
15230 sc->spq = NULL;
15231
15232 /*************/
15233 /* SLOW PATH */
15234 /*************/
15235
15236 bxe_dma_free(sc, &sc->sp_dma);
15237 sc->sp = NULL;
15238
15239 /***************/
15240 /* EVENT QUEUE */
15241 /***************/
15242
15243 bxe_dma_free(sc, &sc->eq_dma);
15244 sc->eq = NULL;
15245
15246 /************************/
15247 /* DEFAULT STATUS BLOCK */
15248 /************************/
15249
15250 bxe_dma_free(sc, &sc->def_sb_dma);
15251 sc->def_sb = NULL;
15252
15253 bus_dma_tag_destroy(sc->parent_dma_tag);
15254 sc->parent_dma_tag = NULL;
15255 }
15256
15257 /*
15258 * Previous driver DMAE transaction may have occurred when pre-boot stage
15259 * ended and boot began. This would invalidate the addresses of the
15260 * transaction, resulting in was-error bit set in the PCI causing all
15261 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
15262 * the interrupt which detected this from the pglueb and the was-done bit
15263 */
15264 static void
bxe_prev_interrupted_dmae(struct bxe_softc * sc)15265 bxe_prev_interrupted_dmae(struct bxe_softc *sc)
15266 {
15267 uint32_t val;
15268
15269 if (!CHIP_IS_E1x(sc)) {
15270 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
15271 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
15272 BLOGD(sc, DBG_LOAD,
15273 "Clearing 'was-error' bit that was set in pglueb");
15274 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc));
15275 }
15276 }
15277 }
15278
15279 static int
bxe_prev_mcp_done(struct bxe_softc * sc)15280 bxe_prev_mcp_done(struct bxe_softc *sc)
15281 {
15282 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
15283 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
15284 if (!rc) {
15285 BLOGE(sc, "MCP response failure, aborting\n");
15286 return (-1);
15287 }
15288
15289 return (0);
15290 }
15291
15292 static struct bxe_prev_list_node *
bxe_prev_path_get_entry(struct bxe_softc * sc)15293 bxe_prev_path_get_entry(struct bxe_softc *sc)
15294 {
15295 struct bxe_prev_list_node *tmp;
15296
15297 LIST_FOREACH(tmp, &bxe_prev_list, node) {
15298 if ((sc->pcie_bus == tmp->bus) &&
15299 (sc->pcie_device == tmp->slot) &&
15300 (SC_PATH(sc) == tmp->path)) {
15301 return (tmp);
15302 }
15303 }
15304
15305 return (NULL);
15306 }
15307
15308 static uint8_t
bxe_prev_is_path_marked(struct bxe_softc * sc)15309 bxe_prev_is_path_marked(struct bxe_softc *sc)
15310 {
15311 struct bxe_prev_list_node *tmp;
15312 int rc = FALSE;
15313
15314 mtx_lock(&bxe_prev_mtx);
15315
15316 tmp = bxe_prev_path_get_entry(sc);
15317 if (tmp) {
15318 if (tmp->aer) {
15319 BLOGD(sc, DBG_LOAD,
15320 "Path %d/%d/%d was marked by AER\n",
15321 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15322 } else {
15323 rc = TRUE;
15324 BLOGD(sc, DBG_LOAD,
15325 "Path %d/%d/%d was already cleaned from previous drivers\n",
15326 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15327 }
15328 }
15329
15330 mtx_unlock(&bxe_prev_mtx);
15331
15332 return (rc);
15333 }
15334
15335 static int
bxe_prev_mark_path(struct bxe_softc * sc,uint8_t after_undi)15336 bxe_prev_mark_path(struct bxe_softc *sc,
15337 uint8_t after_undi)
15338 {
15339 struct bxe_prev_list_node *tmp;
15340
15341 mtx_lock(&bxe_prev_mtx);
15342
15343 /* Check whether the entry for this path already exists */
15344 tmp = bxe_prev_path_get_entry(sc);
15345 if (tmp) {
15346 if (!tmp->aer) {
15347 BLOGD(sc, DBG_LOAD,
15348 "Re-marking AER in path %d/%d/%d\n",
15349 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15350 } else {
15351 BLOGD(sc, DBG_LOAD,
15352 "Removing AER indication from path %d/%d/%d\n",
15353 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15354 tmp->aer = 0;
15355 }
15356
15357 mtx_unlock(&bxe_prev_mtx);
15358 return (0);
15359 }
15360
15361 mtx_unlock(&bxe_prev_mtx);
15362
15363 /* Create an entry for this path and add it */
15364 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF,
15365 (M_NOWAIT | M_ZERO));
15366 if (!tmp) {
15367 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n");
15368 return (-1);
15369 }
15370
15371 tmp->bus = sc->pcie_bus;
15372 tmp->slot = sc->pcie_device;
15373 tmp->path = SC_PATH(sc);
15374 tmp->aer = 0;
15375 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
15376
15377 mtx_lock(&bxe_prev_mtx);
15378
15379 BLOGD(sc, DBG_LOAD,
15380 "Marked path %d/%d/%d - finished previous unload\n",
15381 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15382 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node);
15383
15384 mtx_unlock(&bxe_prev_mtx);
15385
15386 return (0);
15387 }
15388
15389 static int
bxe_do_flr(struct bxe_softc * sc)15390 bxe_do_flr(struct bxe_softc *sc)
15391 {
15392 int i;
15393
15394 /* only E2 and onwards support FLR */
15395 if (CHIP_IS_E1x(sc)) {
15396 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n");
15397 return (-1);
15398 }
15399
15400 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
15401 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
15402 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n",
15403 sc->devinfo.bc_ver);
15404 return (-1);
15405 }
15406
15407 /* Wait for Transaction Pending bit clean */
15408 for (i = 0; i < 4; i++) {
15409 if (i) {
15410 DELAY(((1 << (i - 1)) * 100) * 1000);
15411 }
15412
15413 if (!bxe_is_pcie_pending(sc)) {
15414 goto clear;
15415 }
15416 }
15417
15418 BLOGE(sc, "PCIE transaction is not cleared, "
15419 "proceeding with reset anyway\n");
15420
15421 clear:
15422
15423 BLOGD(sc, DBG_LOAD, "Initiating FLR\n");
15424 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
15425
15426 return (0);
15427 }
15428
15429 struct bxe_mac_vals {
15430 uint32_t xmac_addr;
15431 uint32_t xmac_val;
15432 uint32_t emac_addr;
15433 uint32_t emac_val;
15434 uint32_t umac_addr;
15435 uint32_t umac_val;
15436 uint32_t bmac_addr;
15437 uint32_t bmac_val[2];
15438 };
15439
15440 static void
bxe_prev_unload_close_mac(struct bxe_softc * sc,struct bxe_mac_vals * vals)15441 bxe_prev_unload_close_mac(struct bxe_softc *sc,
15442 struct bxe_mac_vals *vals)
15443 {
15444 uint32_t val, base_addr, offset, mask, reset_reg;
15445 uint8_t mac_stopped = FALSE;
15446 uint8_t port = SC_PORT(sc);
15447 uint32_t wb_data[2];
15448
15449 /* reset addresses as they also mark which values were changed */
15450 vals->bmac_addr = 0;
15451 vals->umac_addr = 0;
15452 vals->xmac_addr = 0;
15453 vals->emac_addr = 0;
15454
15455 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
15456
15457 if (!CHIP_IS_E3(sc)) {
15458 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
15459 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
15460 if ((mask & reset_reg) && val) {
15461 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n");
15462 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
15463 : NIG_REG_INGRESS_BMAC0_MEM;
15464 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
15465 : BIGMAC_REGISTER_BMAC_CONTROL;
15466
15467 /*
15468 * use rd/wr since we cannot use dmae. This is safe
15469 * since MCP won't access the bus due to the request
15470 * to unload, and no function on the path can be
15471 * loaded at this time.
15472 */
15473 wb_data[0] = REG_RD(sc, base_addr + offset);
15474 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
15475 vals->bmac_addr = base_addr + offset;
15476 vals->bmac_val[0] = wb_data[0];
15477 vals->bmac_val[1] = wb_data[1];
15478 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
15479 REG_WR(sc, vals->bmac_addr, wb_data[0]);
15480 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
15481 }
15482
15483 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n");
15484 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4;
15485 vals->emac_val = REG_RD(sc, vals->emac_addr);
15486 REG_WR(sc, vals->emac_addr, 0);
15487 mac_stopped = TRUE;
15488 } else {
15489 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
15490 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n");
15491 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
15492 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
15493 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1));
15494 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1));
15495 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
15496 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
15497 REG_WR(sc, vals->xmac_addr, 0);
15498 mac_stopped = TRUE;
15499 }
15500
15501 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
15502 if (mask & reset_reg) {
15503 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n");
15504 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
15505 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
15506 vals->umac_val = REG_RD(sc, vals->umac_addr);
15507 REG_WR(sc, vals->umac_addr, 0);
15508 mac_stopped = TRUE;
15509 }
15510 }
15511
15512 if (mac_stopped) {
15513 DELAY(20000);
15514 }
15515 }
15516
15517 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
15518 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff)
15519 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
15520 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
15521
15522 static void
bxe_prev_unload_undi_inc(struct bxe_softc * sc,uint8_t port,uint8_t inc)15523 bxe_prev_unload_undi_inc(struct bxe_softc *sc,
15524 uint8_t port,
15525 uint8_t inc)
15526 {
15527 uint16_t rcq, bd;
15528 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));
15529
15530 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc;
15531 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc;
15532
15533 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd);
15534 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg);
15535
15536 BLOGD(sc, DBG_LOAD,
15537 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
15538 port, bd, rcq);
15539 }
15540
15541 static int
bxe_prev_unload_common(struct bxe_softc * sc)15542 bxe_prev_unload_common(struct bxe_softc *sc)
15543 {
15544 uint32_t reset_reg, tmp_reg = 0, rc;
15545 uint8_t prev_undi = FALSE;
15546 struct bxe_mac_vals mac_vals;
15547 uint32_t timer_count = 1000;
15548 uint32_t prev_brb;
15549
15550 /*
15551 * It is possible a previous function received 'common' answer,
15552 * but hasn't loaded yet, therefore creating a scenario of
15553 * multiple functions receiving 'common' on the same path.
15554 */
15555 BLOGD(sc, DBG_LOAD, "Common unload Flow\n");
15556
15557 memset(&mac_vals, 0, sizeof(mac_vals));
15558
15559 if (bxe_prev_is_path_marked(sc)) {
15560 return (bxe_prev_mcp_done(sc));
15561 }
15562
15563 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
15564
15565 /* Reset should be performed after BRB is emptied */
15566 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
15567 /* Close the MAC Rx to prevent BRB from filling up */
15568 bxe_prev_unload_close_mac(sc, &mac_vals);
15569
15570 /* close LLH filters towards the BRB */
15571 elink_set_rx_filter(&sc->link_params, 0);
15572
15573 /*
15574 * Check if the UNDI driver was previously loaded.
15575 * UNDI driver initializes CID offset for normal bell to 0x7
15576 */
15577 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
15578 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
15579 if (tmp_reg == 0x7) {
15580 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n");
15581 prev_undi = TRUE;
15582 /* clear the UNDI indication */
15583 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
15584 /* clear possible idle check errors */
15585 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
15586 }
15587 }
15588
15589 /* wait until BRB is empty */
15590 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15591 while (timer_count) {
15592 prev_brb = tmp_reg;
15593
15594 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15595 if (!tmp_reg) {
15596 break;
15597 }
15598
15599 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg);
15600
15601 /* reset timer as long as BRB actually gets emptied */
15602 if (prev_brb > tmp_reg) {
15603 timer_count = 1000;
15604 } else {
15605 timer_count--;
15606 }
15607
15608 /* If UNDI resides in memory, manually increment it */
15609 if (prev_undi) {
15610 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
15611 }
15612
15613 DELAY(10);
15614 }
15615
15616 if (!timer_count) {
15617 BLOGE(sc, "Failed to empty BRB\n");
15618 }
15619 }
15620
15621 /* No packets are in the pipeline, path is ready for reset */
15622 bxe_reset_common(sc);
15623
15624 if (mac_vals.xmac_addr) {
15625 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
15626 }
15627 if (mac_vals.umac_addr) {
15628 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
15629 }
15630 if (mac_vals.emac_addr) {
15631 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
15632 }
15633 if (mac_vals.bmac_addr) {
15634 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
15635 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
15636 }
15637
15638 rc = bxe_prev_mark_path(sc, prev_undi);
15639 if (rc) {
15640 bxe_prev_mcp_done(sc);
15641 return (rc);
15642 }
15643
15644 return (bxe_prev_mcp_done(sc));
15645 }
15646
15647 static int
bxe_prev_unload_uncommon(struct bxe_softc * sc)15648 bxe_prev_unload_uncommon(struct bxe_softc *sc)
15649 {
15650 int rc;
15651
15652 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n");
15653
15654 /* Test if previous unload process was already finished for this path */
15655 if (bxe_prev_is_path_marked(sc)) {
15656 return (bxe_prev_mcp_done(sc));
15657 }
15658
15659 BLOGD(sc, DBG_LOAD, "Path is unmarked\n");
15660
15661 /*
15662 * If function has FLR capabilities, and existing FW version matches
15663 * the one required, then FLR will be sufficient to clean any residue
15664 * left by previous driver
15665 */
15666 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
15667 if (!rc) {
15668 /* fw version is good */
15669 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n");
15670 rc = bxe_do_flr(sc);
15671 }
15672
15673 if (!rc) {
15674 /* FLR was performed */
15675 BLOGD(sc, DBG_LOAD, "FLR successful\n");
15676 return (0);
15677 }
15678
15679 BLOGD(sc, DBG_LOAD, "Could not FLR\n");
15680
15681 /* Close the MCP request, return failure*/
15682 rc = bxe_prev_mcp_done(sc);
15683 if (!rc) {
15684 rc = BXE_PREV_WAIT_NEEDED;
15685 }
15686
15687 return (rc);
15688 }
15689
15690 static int
bxe_prev_unload(struct bxe_softc * sc)15691 bxe_prev_unload(struct bxe_softc *sc)
15692 {
15693 int time_counter = 10;
15694 uint32_t fw, hw_lock_reg, hw_lock_val;
15695 uint32_t rc = 0;
15696
15697 /*
15698 * Clear HW from errors which may have resulted from an interrupted
15699 * DMAE transaction.
15700 */
15701 bxe_prev_interrupted_dmae(sc);
15702
15703 /* Release previously held locks */
15704 hw_lock_reg =
15705 (SC_FUNC(sc) <= 5) ?
15706 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
15707 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
15708
15709 hw_lock_val = (REG_RD(sc, hw_lock_reg));
15710 if (hw_lock_val) {
15711 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
15712 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n");
15713 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
15714 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
15715 }
15716 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n");
15717 REG_WR(sc, hw_lock_reg, 0xffffffff);
15718 } else {
15719 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n");
15720 }
15721
15722 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
15723 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n");
15724 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
15725 }
15726
15727 do {
15728 /* Lock MCP using an unload request */
15729 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
15730 if (!fw) {
15731 BLOGE(sc, "MCP response failure, aborting\n");
15732 rc = -1;
15733 break;
15734 }
15735
15736 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
15737 rc = bxe_prev_unload_common(sc);
15738 break;
15739 }
15740
15741 /* non-common reply from MCP night require looping */
15742 rc = bxe_prev_unload_uncommon(sc);
15743 if (rc != BXE_PREV_WAIT_NEEDED) {
15744 break;
15745 }
15746
15747 DELAY(20000);
15748 } while (--time_counter);
15749
15750 if (!time_counter || rc) {
15751 BLOGE(sc, "Failed to unload previous driver!"
15752 " time_counter %d rc %d\n", time_counter, rc);
15753 rc = -1;
15754 }
15755
15756 return (rc);
15757 }
15758
15759 void
bxe_dcbx_set_state(struct bxe_softc * sc,uint8_t dcb_on,uint32_t dcbx_enabled)15760 bxe_dcbx_set_state(struct bxe_softc *sc,
15761 uint8_t dcb_on,
15762 uint32_t dcbx_enabled)
15763 {
15764 if (!CHIP_IS_E1x(sc)) {
15765 sc->dcb_state = dcb_on;
15766 sc->dcbx_enabled = dcbx_enabled;
15767 } else {
15768 sc->dcb_state = FALSE;
15769 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID;
15770 }
15771 BLOGD(sc, DBG_LOAD,
15772 "DCB state [%s:%s]\n",
15773 dcb_on ? "ON" : "OFF",
15774 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" :
15775 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" :
15776 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ?
15777 "on-chip with negotiation" : "invalid");
15778 }
15779
15780 /* must be called after sriov-enable */
15781 static int
bxe_set_qm_cid_count(struct bxe_softc * sc)15782 bxe_set_qm_cid_count(struct bxe_softc *sc)
15783 {
15784 int cid_count = BXE_L2_MAX_CID(sc);
15785
15786 if (IS_SRIOV(sc)) {
15787 cid_count += BXE_VF_CIDS;
15788 }
15789
15790 if (CNIC_SUPPORT(sc)) {
15791 cid_count += CNIC_CID_MAX;
15792 }
15793
15794 return (roundup(cid_count, QM_CID_ROUND));
15795 }
15796
15797 static void
bxe_init_multi_cos(struct bxe_softc * sc)15798 bxe_init_multi_cos(struct bxe_softc *sc)
15799 {
15800 int pri, cos;
15801
15802 uint32_t pri_map = 0; /* XXX change to user config */
15803
15804 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) {
15805 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
15806 if (cos < sc->max_cos) {
15807 sc->prio_to_cos[pri] = cos;
15808 } else {
15809 BLOGW(sc, "Invalid COS %d for priority %d "
15810 "(max COS is %d), setting to 0\n",
15811 cos, pri, (sc->max_cos - 1));
15812 sc->prio_to_cos[pri] = 0;
15813 }
15814 }
15815 }
15816
15817 static int
bxe_sysctl_state(SYSCTL_HANDLER_ARGS)15818 bxe_sysctl_state(SYSCTL_HANDLER_ARGS)
15819 {
15820 struct bxe_softc *sc;
15821 int error, result;
15822
15823 result = 0;
15824 error = sysctl_handle_int(oidp, &result, 0, req);
15825
15826 if (error || !req->newptr) {
15827 return (error);
15828 }
15829
15830 if (result == 1) {
15831 uint32_t temp;
15832 sc = (struct bxe_softc *)arg1;
15833
15834 BLOGI(sc, "... dumping driver state ...\n");
15835 temp = SHMEM2_RD(sc, temperature_in_half_celsius);
15836 BLOGI(sc, "\t Device Temperature = %d Celsius\n", (temp/2));
15837 }
15838
15839 return (error);
15840 }
15841
15842 static int
bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)15843 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)
15844 {
15845 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15846 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats;
15847 uint32_t *offset;
15848 uint64_t value = 0;
15849 int index = (int)arg2;
15850
15851 if (index >= BXE_NUM_ETH_STATS) {
15852 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index);
15853 return (-1);
15854 }
15855
15856 offset = (eth_stats + bxe_eth_stats_arr[index].offset);
15857
15858 switch (bxe_eth_stats_arr[index].size) {
15859 case 4:
15860 value = (uint64_t)*offset;
15861 break;
15862 case 8:
15863 value = HILO_U64(*offset, *(offset + 1));
15864 break;
15865 default:
15866 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n",
15867 index, bxe_eth_stats_arr[index].size);
15868 return (-1);
15869 }
15870
15871 return (sysctl_handle_64(oidp, &value, 0, req));
15872 }
15873
15874 static int
bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)15875 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)
15876 {
15877 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15878 uint32_t *eth_stats;
15879 uint32_t *offset;
15880 uint64_t value = 0;
15881 uint32_t q_stat = (uint32_t)arg2;
15882 uint32_t fp_index = ((q_stat >> 16) & 0xffff);
15883 uint32_t index = (q_stat & 0xffff);
15884
15885 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats;
15886
15887 if (index >= BXE_NUM_ETH_Q_STATS) {
15888 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index);
15889 return (-1);
15890 }
15891
15892 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset);
15893
15894 switch (bxe_eth_q_stats_arr[index].size) {
15895 case 4:
15896 value = (uint64_t)*offset;
15897 break;
15898 case 8:
15899 value = HILO_U64(*offset, *(offset + 1));
15900 break;
15901 default:
15902 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n",
15903 index, bxe_eth_q_stats_arr[index].size);
15904 return (-1);
15905 }
15906
15907 return (sysctl_handle_64(oidp, &value, 0, req));
15908 }
15909
bxe_force_link_reset(struct bxe_softc * sc)15910 static void bxe_force_link_reset(struct bxe_softc *sc)
15911 {
15912
15913 bxe_acquire_phy_lock(sc);
15914 elink_link_reset(&sc->link_params, &sc->link_vars, 1);
15915 bxe_release_phy_lock(sc);
15916 }
15917
15918 static int
bxe_sysctl_pauseparam(SYSCTL_HANDLER_ARGS)15919 bxe_sysctl_pauseparam(SYSCTL_HANDLER_ARGS)
15920 {
15921 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15922 uint32_t cfg_idx = bxe_get_link_cfg_idx(sc);
15923 int rc = 0;
15924 int error;
15925 int result;
15926
15927
15928 error = sysctl_handle_int(oidp, &sc->bxe_pause_param, 0, req);
15929
15930 if (error || !req->newptr) {
15931 return (error);
15932 }
15933 if ((sc->bxe_pause_param < 0) || (sc->bxe_pause_param > 8)) {
15934 BLOGW(sc, "invalid pause param (%d) - use integers between 1 & 8\n",sc->bxe_pause_param);
15935 sc->bxe_pause_param = 8;
15936 }
15937
15938 result = (sc->bxe_pause_param << PORT_FEATURE_FLOW_CONTROL_SHIFT);
15939
15940
15941 if((result & 0x400) && !(sc->port.supported[cfg_idx] & ELINK_SUPPORTED_Autoneg)) {
15942 BLOGW(sc, "Does not support Autoneg pause_param %d\n", sc->bxe_pause_param);
15943 return -EINVAL;
15944 }
15945
15946 if(IS_MF(sc))
15947 return 0;
15948 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_AUTO;
15949 if(result & ELINK_FLOW_CTRL_RX)
15950 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_RX;
15951
15952 if(result & ELINK_FLOW_CTRL_TX)
15953 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_TX;
15954 if(sc->link_params.req_flow_ctrl[cfg_idx] == ELINK_FLOW_CTRL_AUTO)
15955 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_NONE;
15956
15957 if(result & 0x400) {
15958 if (sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG) {
15959 sc->link_params.req_flow_ctrl[cfg_idx] =
15960 ELINK_FLOW_CTRL_AUTO;
15961 }
15962 sc->link_params.req_fc_auto_adv = 0;
15963 if (result & ELINK_FLOW_CTRL_RX)
15964 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_RX;
15965
15966 if (result & ELINK_FLOW_CTRL_TX)
15967 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_TX;
15968 if (!sc->link_params.req_fc_auto_adv)
15969 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_NONE;
15970 }
15971 if (IS_PF(sc)) {
15972 if (sc->link_vars.link_up) {
15973 bxe_stats_handle(sc, STATS_EVENT_STOP);
15974 }
15975 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) {
15976 bxe_force_link_reset(sc);
15977 bxe_acquire_phy_lock(sc);
15978
15979 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
15980
15981 bxe_release_phy_lock(sc);
15982
15983 bxe_calc_fc_adv(sc);
15984 }
15985 }
15986 return rc;
15987 }
15988
15989
15990 static void
bxe_add_sysctls(struct bxe_softc * sc)15991 bxe_add_sysctls(struct bxe_softc *sc)
15992 {
15993 struct sysctl_ctx_list *ctx;
15994 struct sysctl_oid_list *children;
15995 struct sysctl_oid *queue_top, *queue;
15996 struct sysctl_oid_list *queue_top_children, *queue_children;
15997 char queue_num_buf[32];
15998 uint32_t q_stat;
15999 int i, j;
16000
16001 ctx = device_get_sysctl_ctx(sc->dev);
16002 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
16003
16004 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version",
16005 CTLFLAG_RD, BXE_DRIVER_VERSION, 0,
16006 "version");
16007
16008 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d",
16009 BCM_5710_FW_MAJOR_VERSION,
16010 BCM_5710_FW_MINOR_VERSION,
16011 BCM_5710_FW_REVISION_VERSION,
16012 BCM_5710_FW_ENGINEERING_VERSION);
16013
16014 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s",
16015 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" :
16016 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" :
16017 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" :
16018 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" :
16019 "Unknown"));
16020 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics",
16021 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0,
16022 "multifunction vnics per port");
16023
16024 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d",
16025 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" :
16026 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" :
16027 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" :
16028 "???GT/s"),
16029 sc->devinfo.pcie_link_width);
16030
16031 sc->debug = bxe_debug;
16032
16033 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
16034 CTLFLAG_RD, sc->devinfo.bc_ver_str, 0,
16035 "bootcode version");
16036 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
16037 CTLFLAG_RD, sc->fw_ver_str, 0,
16038 "firmware version");
16039 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
16040 CTLFLAG_RD, sc->mf_mode_str, 0,
16041 "multifunction mode");
16042 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
16043 CTLFLAG_RD, sc->mac_addr_str, 0,
16044 "mac address");
16045 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
16046 CTLFLAG_RD, sc->pci_link_str, 0,
16047 "pci link status");
16048 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "debug",
16049 CTLFLAG_RW, &sc->debug,
16050 "debug logging mode");
16051
16052 sc->trigger_grcdump = 0;
16053 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "trigger_grcdump",
16054 CTLFLAG_RW, &sc->trigger_grcdump, 0,
16055 "trigger grcdump should be invoked"
16056 " before collecting grcdump");
16057
16058 sc->grcdump_started = 0;
16059 sc->grcdump_done = 0;
16060 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "grcdump_done",
16061 CTLFLAG_RD, &sc->grcdump_done, 0,
16062 "set by driver when grcdump is done");
16063
16064 sc->rx_budget = bxe_rx_budget;
16065 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget",
16066 CTLFLAG_RW, &sc->rx_budget, 0,
16067 "rx processing budget");
16068
16069 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_param",
16070 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
16071 bxe_sysctl_pauseparam, "IU",
16072 "need pause frames- DEF:0/TX:1/RX:2/BOTH:3/AUTO:4/AUTOTX:5/AUTORX:6/AUTORXTX:7/NONE:8");
16073
16074
16075 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state",
16076 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
16077 bxe_sysctl_state, "IU", "dump driver state");
16078
16079 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
16080 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
16081 bxe_eth_stats_arr[i].string,
16082 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
16083 bxe_sysctl_eth_stat, "LU", bxe_eth_stats_arr[i].string);
16084 }
16085
16086 /* add a new parent node for all queues "dev.bxe.#.queue" */
16087 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue",
16088 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "queue");
16089 queue_top_children = SYSCTL_CHILDREN(queue_top);
16090
16091 for (i = 0; i < sc->num_queues; i++) {
16092 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */
16093 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i);
16094 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO,
16095 queue_num_buf, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "single queue");
16096 queue_children = SYSCTL_CHILDREN(queue);
16097
16098 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) {
16099 q_stat = ((i << 16) | j);
16100 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO,
16101 bxe_eth_q_stats_arr[j].string,
16102 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, q_stat,
16103 bxe_sysctl_eth_q_stat, "LU", bxe_eth_q_stats_arr[j].string);
16104 }
16105 }
16106 }
16107
16108 static int
bxe_alloc_buf_rings(struct bxe_softc * sc)16109 bxe_alloc_buf_rings(struct bxe_softc *sc)
16110 {
16111 int i;
16112 struct bxe_fastpath *fp;
16113
16114 for (i = 0; i < sc->num_queues; i++) {
16115
16116 fp = &sc->fp[i];
16117
16118 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF,
16119 M_NOWAIT, &fp->tx_mtx);
16120 if (fp->tx_br == NULL)
16121 return (-1);
16122 }
16123
16124 return (0);
16125 }
16126
16127 static void
bxe_free_buf_rings(struct bxe_softc * sc)16128 bxe_free_buf_rings(struct bxe_softc *sc)
16129 {
16130 int i;
16131 struct bxe_fastpath *fp;
16132
16133 for (i = 0; i < sc->num_queues; i++) {
16134
16135 fp = &sc->fp[i];
16136
16137 if (fp->tx_br) {
16138 buf_ring_free(fp->tx_br, M_DEVBUF);
16139 fp->tx_br = NULL;
16140 }
16141 }
16142 }
16143
16144 static void
bxe_init_fp_mutexs(struct bxe_softc * sc)16145 bxe_init_fp_mutexs(struct bxe_softc *sc)
16146 {
16147 int i;
16148 struct bxe_fastpath *fp;
16149
16150 for (i = 0; i < sc->num_queues; i++) {
16151
16152 fp = &sc->fp[i];
16153
16154 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
16155 "bxe%d_fp%d_tx_lock", sc->unit, i);
16156 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
16157
16158 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name),
16159 "bxe%d_fp%d_rx_lock", sc->unit, i);
16160 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF);
16161 }
16162 }
16163
16164 static void
bxe_destroy_fp_mutexs(struct bxe_softc * sc)16165 bxe_destroy_fp_mutexs(struct bxe_softc *sc)
16166 {
16167 int i;
16168 struct bxe_fastpath *fp;
16169
16170 for (i = 0; i < sc->num_queues; i++) {
16171
16172 fp = &sc->fp[i];
16173
16174 if (mtx_initialized(&fp->tx_mtx)) {
16175 mtx_destroy(&fp->tx_mtx);
16176 }
16177
16178 if (mtx_initialized(&fp->rx_mtx)) {
16179 mtx_destroy(&fp->rx_mtx);
16180 }
16181 }
16182 }
16183
16184
16185 /*
16186 * Device attach function.
16187 *
16188 * Allocates device resources, performs secondary chip identification, and
16189 * initializes driver instance variables. This function is called from driver
16190 * load after a successful probe.
16191 *
16192 * Returns:
16193 * 0 = Success, >0 = Failure
16194 */
16195 static int
bxe_attach(device_t dev)16196 bxe_attach(device_t dev)
16197 {
16198 struct bxe_softc *sc;
16199
16200 sc = device_get_softc(dev);
16201
16202 BLOGD(sc, DBG_LOAD, "Starting attach...\n");
16203
16204 sc->state = BXE_STATE_CLOSED;
16205
16206 sc->dev = dev;
16207 sc->unit = device_get_unit(dev);
16208
16209 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc);
16210
16211 sc->pcie_bus = pci_get_bus(dev);
16212 sc->pcie_device = pci_get_slot(dev);
16213 sc->pcie_func = pci_get_function(dev);
16214
16215 /* enable bus master capability */
16216 pci_enable_busmaster(dev);
16217
16218 /* get the BARs */
16219 if (bxe_allocate_bars(sc) != 0) {
16220 return (ENXIO);
16221 }
16222
16223 /* initialize the mutexes */
16224 bxe_init_mutexes(sc);
16225
16226 /* prepare the periodic callout */
16227 callout_init(&sc->periodic_callout, 1);
16228
16229 /* prepare the chip taskqueue */
16230 sc->chip_tq_flags = CHIP_TQ_NONE;
16231 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name),
16232 "bxe%d_chip_tq", sc->unit);
16233 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc);
16234 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT,
16235 taskqueue_thread_enqueue,
16236 &sc->chip_tq);
16237 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */
16238 "%s", sc->chip_tq_name);
16239
16240 TIMEOUT_TASK_INIT(taskqueue_thread,
16241 &sc->sp_err_timeout_task, 0, bxe_sp_err_timeout_task, sc);
16242
16243
16244 /* get device info and set params */
16245 if (bxe_get_device_info(sc) != 0) {
16246 BLOGE(sc, "getting device info\n");
16247 bxe_deallocate_bars(sc);
16248 pci_disable_busmaster(dev);
16249 return (ENXIO);
16250 }
16251
16252 /* get final misc params */
16253 bxe_get_params(sc);
16254
16255 /* set the default MTU (changed via ifconfig) */
16256 sc->mtu = ETHERMTU;
16257
16258 bxe_set_modes_bitmap(sc);
16259
16260 /* XXX
16261 * If in AFEX mode and the function is configured for FCoE
16262 * then bail... no L2 allowed.
16263 */
16264
16265 /* get phy settings from shmem and 'and' against admin settings */
16266 bxe_get_phy_info(sc);
16267
16268 /* initialize the FreeBSD ifnet interface */
16269 bxe_init_ifnet(sc);
16270
16271 if (bxe_add_cdev(sc) != 0) {
16272 if (sc->ifp != NULL) {
16273 ether_ifdetach(sc->ifp);
16274 }
16275 ifmedia_removeall(&sc->ifmedia);
16276 bxe_release_mutexes(sc);
16277 bxe_deallocate_bars(sc);
16278 pci_disable_busmaster(dev);
16279 return (ENXIO);
16280 }
16281
16282 /* allocate device interrupts */
16283 if (bxe_interrupt_alloc(sc) != 0) {
16284 bxe_del_cdev(sc);
16285 if (sc->ifp != NULL) {
16286 ether_ifdetach(sc->ifp);
16287 }
16288 ifmedia_removeall(&sc->ifmedia);
16289 bxe_release_mutexes(sc);
16290 bxe_deallocate_bars(sc);
16291 pci_disable_busmaster(dev);
16292 return (ENXIO);
16293 }
16294
16295 bxe_init_fp_mutexs(sc);
16296
16297 if (bxe_alloc_buf_rings(sc) != 0) {
16298 bxe_free_buf_rings(sc);
16299 bxe_interrupt_free(sc);
16300 bxe_del_cdev(sc);
16301 if (sc->ifp != NULL) {
16302 ether_ifdetach(sc->ifp);
16303 }
16304 ifmedia_removeall(&sc->ifmedia);
16305 bxe_release_mutexes(sc);
16306 bxe_deallocate_bars(sc);
16307 pci_disable_busmaster(dev);
16308 return (ENXIO);
16309 }
16310
16311 /* allocate ilt */
16312 if (bxe_alloc_ilt_mem(sc) != 0) {
16313 bxe_free_buf_rings(sc);
16314 bxe_interrupt_free(sc);
16315 bxe_del_cdev(sc);
16316 if (sc->ifp != NULL) {
16317 ether_ifdetach(sc->ifp);
16318 }
16319 ifmedia_removeall(&sc->ifmedia);
16320 bxe_release_mutexes(sc);
16321 bxe_deallocate_bars(sc);
16322 pci_disable_busmaster(dev);
16323 return (ENXIO);
16324 }
16325
16326 /* allocate the host hardware/software hsi structures */
16327 if (bxe_alloc_hsi_mem(sc) != 0) {
16328 bxe_free_ilt_mem(sc);
16329 bxe_free_buf_rings(sc);
16330 bxe_interrupt_free(sc);
16331 bxe_del_cdev(sc);
16332 if (sc->ifp != NULL) {
16333 ether_ifdetach(sc->ifp);
16334 }
16335 ifmedia_removeall(&sc->ifmedia);
16336 bxe_release_mutexes(sc);
16337 bxe_deallocate_bars(sc);
16338 pci_disable_busmaster(dev);
16339 return (ENXIO);
16340 }
16341
16342 /* need to reset chip if UNDI was active */
16343 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
16344 /* init fw_seq */
16345 sc->fw_seq =
16346 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
16347 DRV_MSG_SEQ_NUMBER_MASK);
16348 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq);
16349 bxe_prev_unload(sc);
16350 }
16351
16352 #if 1
16353 /* XXX */
16354 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16355 #else
16356 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) &&
16357 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) &&
16358 SHMEM2_RD(sc, dcbx_lldp_params_offset) &&
16359 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) {
16360 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON);
16361 bxe_dcbx_init_params(sc);
16362 } else {
16363 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16364 }
16365 #endif
16366
16367 /* calculate qm_cid_count */
16368 sc->qm_cid_count = bxe_set_qm_cid_count(sc);
16369 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count);
16370
16371 sc->max_cos = 1;
16372 bxe_init_multi_cos(sc);
16373
16374 bxe_add_sysctls(sc);
16375
16376 return (0);
16377 }
16378
16379 /*
16380 * Device detach function.
16381 *
16382 * Stops the controller, resets the controller, and releases resources.
16383 *
16384 * Returns:
16385 * 0 = Success, >0 = Failure
16386 */
16387 static int
bxe_detach(device_t dev)16388 bxe_detach(device_t dev)
16389 {
16390 struct bxe_softc *sc;
16391 if_t ifp;
16392
16393 sc = device_get_softc(dev);
16394
16395 BLOGD(sc, DBG_LOAD, "Starting detach...\n");
16396
16397 ifp = sc->ifp;
16398 if (ifp != NULL && if_vlantrunkinuse(ifp)) {
16399 BLOGE(sc, "Cannot detach while VLANs are in use.\n");
16400 return(EBUSY);
16401 }
16402
16403 bxe_del_cdev(sc);
16404
16405 /* stop the periodic callout */
16406 bxe_periodic_stop(sc);
16407
16408 /* stop the chip taskqueue */
16409 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE);
16410 if (sc->chip_tq) {
16411 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task);
16412 taskqueue_free(sc->chip_tq);
16413 sc->chip_tq = NULL;
16414 taskqueue_drain_timeout(taskqueue_thread,
16415 &sc->sp_err_timeout_task);
16416 }
16417
16418 /* stop and reset the controller if it was open */
16419 if (sc->state != BXE_STATE_CLOSED) {
16420 BXE_CORE_LOCK(sc);
16421 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE);
16422 sc->state = BXE_STATE_DISABLED;
16423 BXE_CORE_UNLOCK(sc);
16424 }
16425
16426 /* release the network interface */
16427 if (ifp != NULL) {
16428 ether_ifdetach(ifp);
16429 }
16430 ifmedia_removeall(&sc->ifmedia);
16431
16432 /* XXX do the following based on driver state... */
16433
16434 /* free the host hardware/software hsi structures */
16435 bxe_free_hsi_mem(sc);
16436
16437 /* free ilt */
16438 bxe_free_ilt_mem(sc);
16439
16440 bxe_free_buf_rings(sc);
16441
16442 /* release the interrupts */
16443 bxe_interrupt_free(sc);
16444
16445 /* Release the mutexes*/
16446 bxe_destroy_fp_mutexs(sc);
16447 bxe_release_mutexes(sc);
16448
16449
16450 /* Release the PCIe BAR mapped memory */
16451 bxe_deallocate_bars(sc);
16452
16453 /* Release the FreeBSD interface. */
16454 if (sc->ifp != NULL) {
16455 if_free(sc->ifp);
16456 }
16457
16458 pci_disable_busmaster(dev);
16459
16460 return (0);
16461 }
16462
16463 /*
16464 * Device shutdown function.
16465 *
16466 * Stops and resets the controller.
16467 *
16468 * Returns:
16469 * Nothing
16470 */
16471 static int
bxe_shutdown(device_t dev)16472 bxe_shutdown(device_t dev)
16473 {
16474 struct bxe_softc *sc;
16475
16476 sc = device_get_softc(dev);
16477
16478 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n");
16479
16480 /* stop the periodic callout */
16481 bxe_periodic_stop(sc);
16482
16483 if (sc->state != BXE_STATE_CLOSED) {
16484 BXE_CORE_LOCK(sc);
16485 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE);
16486 BXE_CORE_UNLOCK(sc);
16487 }
16488
16489 return (0);
16490 }
16491
16492 void
bxe_igu_ack_sb(struct bxe_softc * sc,uint8_t igu_sb_id,uint8_t segment,uint16_t index,uint8_t op,uint8_t update)16493 bxe_igu_ack_sb(struct bxe_softc *sc,
16494 uint8_t igu_sb_id,
16495 uint8_t segment,
16496 uint16_t index,
16497 uint8_t op,
16498 uint8_t update)
16499 {
16500 uint32_t igu_addr = sc->igu_base_addr;
16501 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
16502 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr);
16503 }
16504
16505 static void
bxe_igu_clear_sb_gen(struct bxe_softc * sc,uint8_t func,uint8_t idu_sb_id,uint8_t is_pf)16506 bxe_igu_clear_sb_gen(struct bxe_softc *sc,
16507 uint8_t func,
16508 uint8_t idu_sb_id,
16509 uint8_t is_pf)
16510 {
16511 uint32_t data, ctl, cnt = 100;
16512 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
16513 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
16514 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
16515 uint32_t sb_bit = 1 << (idu_sb_id%32);
16516 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
16517 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
16518
16519 /* Not supported in BC mode */
16520 if (CHIP_INT_MODE_IS_BC(sc)) {
16521 return;
16522 }
16523
16524 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
16525 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
16526 IGU_REGULAR_CLEANUP_SET |
16527 IGU_REGULAR_BCLEANUP);
16528
16529 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
16530 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
16531 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
16532
16533 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16534 data, igu_addr_data);
16535 REG_WR(sc, igu_addr_data, data);
16536
16537 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16538 BUS_SPACE_BARRIER_WRITE);
16539 mb();
16540
16541 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16542 ctl, igu_addr_ctl);
16543 REG_WR(sc, igu_addr_ctl, ctl);
16544
16545 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16546 BUS_SPACE_BARRIER_WRITE);
16547 mb();
16548
16549 /* wait for clean up to finish */
16550 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16551 DELAY(20000);
16552 }
16553
16554 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
16555 BLOGD(sc, DBG_LOAD,
16556 "Unable to finish IGU cleanup: "
16557 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
16558 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
16559 }
16560 }
16561
16562 static void
bxe_igu_clear_sb(struct bxe_softc * sc,uint8_t idu_sb_id)16563 bxe_igu_clear_sb(struct bxe_softc *sc,
16564 uint8_t idu_sb_id)
16565 {
16566 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
16567 }
16568
16569
16570
16571
16572
16573
16574
16575 /*******************/
16576 /* ECORE CALLBACKS */
16577 /*******************/
16578
16579 static void
bxe_reset_common(struct bxe_softc * sc)16580 bxe_reset_common(struct bxe_softc *sc)
16581 {
16582 uint32_t val = 0x1400;
16583
16584 /* reset_common */
16585 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f);
16586
16587 if (CHIP_IS_E3(sc)) {
16588 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16589 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16590 }
16591
16592 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
16593 }
16594
16595 static void
bxe_common_init_phy(struct bxe_softc * sc)16596 bxe_common_init_phy(struct bxe_softc *sc)
16597 {
16598 uint32_t shmem_base[2];
16599 uint32_t shmem2_base[2];
16600
16601 /* Avoid common init in case MFW supports LFA */
16602 if (SHMEM2_RD(sc, size) >
16603 (uint32_t)offsetof(struct shmem2_region,
16604 lfa_host_addr[SC_PORT(sc)])) {
16605 return;
16606 }
16607
16608 shmem_base[0] = sc->devinfo.shmem_base;
16609 shmem2_base[0] = sc->devinfo.shmem2_base;
16610
16611 if (!CHIP_IS_E1x(sc)) {
16612 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
16613 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
16614 }
16615
16616 bxe_acquire_phy_lock(sc);
16617 elink_common_init_phy(sc, shmem_base, shmem2_base,
16618 sc->devinfo.chip_id, 0);
16619 bxe_release_phy_lock(sc);
16620 }
16621
16622 static void
bxe_pf_disable(struct bxe_softc * sc)16623 bxe_pf_disable(struct bxe_softc *sc)
16624 {
16625 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
16626
16627 val &= ~IGU_PF_CONF_FUNC_EN;
16628
16629 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
16630 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16631 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
16632 }
16633
16634 static void
bxe_init_pxp(struct bxe_softc * sc)16635 bxe_init_pxp(struct bxe_softc *sc)
16636 {
16637 uint16_t devctl;
16638 int r_order, w_order;
16639
16640 devctl = bxe_pcie_capability_read(sc, PCIER_DEVICE_CTL, 2);
16641
16642 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl);
16643
16644 w_order = ((devctl & PCIEM_CTL_MAX_PAYLOAD) >> 5);
16645
16646 if (sc->mrrs == -1) {
16647 r_order = ((devctl & PCIEM_CTL_MAX_READ_REQUEST) >> 12);
16648 } else {
16649 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs);
16650 r_order = sc->mrrs;
16651 }
16652
16653 ecore_init_pxp_arb(sc, r_order, w_order);
16654 }
16655
16656 static uint32_t
bxe_get_pretend_reg(struct bxe_softc * sc)16657 bxe_get_pretend_reg(struct bxe_softc *sc)
16658 {
16659 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
16660 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
16661 return (base + (SC_ABS_FUNC(sc)) * stride);
16662 }
16663
16664 /*
16665 * Called only on E1H or E2.
16666 * When pretending to be PF, the pretend value is the function number 0..7.
16667 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
16668 * combination.
16669 */
16670 static int
bxe_pretend_func(struct bxe_softc * sc,uint16_t pretend_func_val)16671 bxe_pretend_func(struct bxe_softc *sc,
16672 uint16_t pretend_func_val)
16673 {
16674 uint32_t pretend_reg;
16675
16676 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) {
16677 return (-1);
16678 }
16679
16680 /* get my own pretend register */
16681 pretend_reg = bxe_get_pretend_reg(sc);
16682 REG_WR(sc, pretend_reg, pretend_func_val);
16683 REG_RD(sc, pretend_reg);
16684 return (0);
16685 }
16686
16687 static void
bxe_iov_init_dmae(struct bxe_softc * sc)16688 bxe_iov_init_dmae(struct bxe_softc *sc)
16689 {
16690 return;
16691 }
16692
16693 static void
bxe_iov_init_dq(struct bxe_softc * sc)16694 bxe_iov_init_dq(struct bxe_softc *sc)
16695 {
16696 return;
16697 }
16698
16699 /* send a NIG loopback debug packet */
16700 static void
bxe_lb_pckt(struct bxe_softc * sc)16701 bxe_lb_pckt(struct bxe_softc *sc)
16702 {
16703 uint32_t wb_write[3];
16704
16705 /* Ethernet source and destination addresses */
16706 wb_write[0] = 0x55555555;
16707 wb_write[1] = 0x55555555;
16708 wb_write[2] = 0x20; /* SOP */
16709 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16710
16711 /* NON-IP protocol */
16712 wb_write[0] = 0x09000000;
16713 wb_write[1] = 0x55555555;
16714 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
16715 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16716 }
16717
16718 /*
16719 * Some of the internal memories are not directly readable from the driver.
16720 * To test them we send debug packets.
16721 */
16722 static int
bxe_int_mem_test(struct bxe_softc * sc)16723 bxe_int_mem_test(struct bxe_softc *sc)
16724 {
16725 int factor;
16726 int count, i;
16727 uint32_t val = 0;
16728
16729 if (CHIP_REV_IS_FPGA(sc)) {
16730 factor = 120;
16731 } else if (CHIP_REV_IS_EMUL(sc)) {
16732 factor = 200;
16733 } else {
16734 factor = 1;
16735 }
16736
16737 /* disable inputs of parser neighbor blocks */
16738 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16739 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16740 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16741 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16742
16743 /* write 0 to parser credits for CFC search request */
16744 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16745
16746 /* send Ethernet packet */
16747 bxe_lb_pckt(sc);
16748
16749 /* TODO do i reset NIG statistic? */
16750 /* Wait until NIG register shows 1 packet of size 0x10 */
16751 count = 1000 * factor;
16752 while (count) {
16753 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16754 val = *BXE_SP(sc, wb_data[0]);
16755 if (val == 0x10) {
16756 break;
16757 }
16758
16759 DELAY(10000);
16760 count--;
16761 }
16762
16763 if (val != 0x10) {
16764 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16765 return (-1);
16766 }
16767
16768 /* wait until PRS register shows 1 packet */
16769 count = (1000 * factor);
16770 while (count) {
16771 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16772 if (val == 1) {
16773 break;
16774 }
16775
16776 DELAY(10000);
16777 count--;
16778 }
16779
16780 if (val != 0x1) {
16781 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16782 return (-2);
16783 }
16784
16785 /* Reset and init BRB, PRS */
16786 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16787 DELAY(50000);
16788 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16789 DELAY(50000);
16790 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16791 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16792
16793 /* Disable inputs of parser neighbor blocks */
16794 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16795 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16796 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16797 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16798
16799 /* Write 0 to parser credits for CFC search request */
16800 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16801
16802 /* send 10 Ethernet packets */
16803 for (i = 0; i < 10; i++) {
16804 bxe_lb_pckt(sc);
16805 }
16806
16807 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */
16808 count = (1000 * factor);
16809 while (count) {
16810 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16811 val = *BXE_SP(sc, wb_data[0]);
16812 if (val == 0xb0) {
16813 break;
16814 }
16815
16816 DELAY(10000);
16817 count--;
16818 }
16819
16820 if (val != 0xb0) {
16821 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16822 return (-3);
16823 }
16824
16825 /* Wait until PRS register shows 2 packets */
16826 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16827 if (val != 2) {
16828 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16829 }
16830
16831 /* Write 1 to parser credits for CFC search request */
16832 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
16833
16834 /* Wait until PRS register shows 3 packets */
16835 DELAY(10000 * factor);
16836
16837 /* Wait until NIG register shows 1 packet of size 0x10 */
16838 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16839 if (val != 3) {
16840 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16841 }
16842
16843 /* clear NIG EOP FIFO */
16844 for (i = 0; i < 11; i++) {
16845 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
16846 }
16847
16848 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
16849 if (val != 1) {
16850 BLOGE(sc, "clear of NIG failed val=0x%x\n", val);
16851 return (-4);
16852 }
16853
16854 /* Reset and init BRB, PRS, NIG */
16855 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16856 DELAY(50000);
16857 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16858 DELAY(50000);
16859 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16860 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16861 if (!CNIC_SUPPORT(sc)) {
16862 /* set NIC mode */
16863 REG_WR(sc, PRS_REG_NIC_MODE, 1);
16864 }
16865
16866 /* Enable inputs of parser neighbor blocks */
16867 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
16868 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
16869 REG_WR(sc, CFC_REG_DEBUG0, 0x0);
16870 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
16871
16872 return (0);
16873 }
16874
16875 static void
bxe_setup_fan_failure_detection(struct bxe_softc * sc)16876 bxe_setup_fan_failure_detection(struct bxe_softc *sc)
16877 {
16878 int is_required;
16879 uint32_t val;
16880 int port;
16881
16882 is_required = 0;
16883 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
16884 SHARED_HW_CFG_FAN_FAILURE_MASK);
16885
16886 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
16887 is_required = 1;
16888 }
16889 /*
16890 * The fan failure mechanism is usually related to the PHY type since
16891 * the power consumption of the board is affected by the PHY. Currently,
16892 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
16893 */
16894 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
16895 for (port = PORT_0; port < PORT_MAX; port++) {
16896 is_required |= elink_fan_failure_det_req(sc,
16897 sc->devinfo.shmem_base,
16898 sc->devinfo.shmem2_base,
16899 port);
16900 }
16901 }
16902
16903 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required);
16904
16905 if (is_required == 0) {
16906 return;
16907 }
16908
16909 /* Fan failure is indicated by SPIO 5 */
16910 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
16911
16912 /* set to active low mode */
16913 val = REG_RD(sc, MISC_REG_SPIO_INT);
16914 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
16915 REG_WR(sc, MISC_REG_SPIO_INT, val);
16916
16917 /* enable interrupt to signal the IGU */
16918 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
16919 val |= MISC_SPIO_SPIO5;
16920 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
16921 }
16922
16923 static void
bxe_enable_blocks_attention(struct bxe_softc * sc)16924 bxe_enable_blocks_attention(struct bxe_softc *sc)
16925 {
16926 uint32_t val;
16927
16928 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
16929 if (!CHIP_IS_E1x(sc)) {
16930 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
16931 } else {
16932 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
16933 }
16934 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
16935 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
16936 /*
16937 * mask read length error interrupts in brb for parser
16938 * (parsing unit and 'checksum and crc' unit)
16939 * these errors are legal (PU reads fixed length and CAC can cause
16940 * read length error on truncated packets)
16941 */
16942 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
16943 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
16944 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
16945 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
16946 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
16947 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
16948 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
16949 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
16950 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
16951 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
16952 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
16953 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
16954 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
16955 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
16956 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
16957 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
16958 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
16959 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
16960 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
16961
16962 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
16963 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
16964 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
16965 if (!CHIP_IS_E1x(sc)) {
16966 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
16967 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
16968 }
16969 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
16970
16971 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
16972 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
16973 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
16974 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
16975
16976 if (!CHIP_IS_E1x(sc)) {
16977 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
16978 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
16979 }
16980
16981 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
16982 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
16983 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
16984 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
16985 }
16986
16987 /**
16988 * bxe_init_hw_common - initialize the HW at the COMMON phase.
16989 *
16990 * @sc: driver handle
16991 */
16992 static int
bxe_init_hw_common(struct bxe_softc * sc)16993 bxe_init_hw_common(struct bxe_softc *sc)
16994 {
16995 uint8_t abs_func_id;
16996 uint32_t val;
16997
16998 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n",
16999 SC_ABS_FUNC(sc));
17000
17001 /*
17002 * take the RESET lock to protect undi_unload flow from accessing
17003 * registers while we are resetting the chip
17004 */
17005 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
17006
17007 bxe_reset_common(sc);
17008
17009 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
17010
17011 val = 0xfffc;
17012 if (CHIP_IS_E3(sc)) {
17013 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
17014 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
17015 }
17016
17017 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
17018
17019 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
17020
17021 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
17022 BLOGD(sc, DBG_LOAD, "after misc block init\n");
17023
17024 if (!CHIP_IS_E1x(sc)) {
17025 /*
17026 * 4-port mode or 2-port mode we need to turn off master-enable for
17027 * everyone. After that we turn it back on for self. So, we disregard
17028 * multi-function, and always disable all functions on the given path,
17029 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
17030 */
17031 for (abs_func_id = SC_PATH(sc);
17032 abs_func_id < (E2_FUNC_MAX * 2);
17033 abs_func_id += 2) {
17034 if (abs_func_id == SC_ABS_FUNC(sc)) {
17035 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17036 continue;
17037 }
17038
17039 bxe_pretend_func(sc, abs_func_id);
17040
17041 /* clear pf enable */
17042 bxe_pf_disable(sc);
17043
17044 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
17045 }
17046 }
17047
17048 BLOGD(sc, DBG_LOAD, "after pf disable\n");
17049
17050 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
17051
17052 if (CHIP_IS_E1(sc)) {
17053 /*
17054 * enable HW interrupt from PXP on USDM overflow
17055 * bit 16 on INT_MASK_0
17056 */
17057 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
17058 }
17059
17060 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
17061 bxe_init_pxp(sc);
17062
17063 #ifdef __BIG_ENDIAN
17064 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
17065 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
17066 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
17067 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
17068 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
17069 /* make sure this value is 0 */
17070 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
17071
17072 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
17073 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
17074 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
17075 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
17076 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
17077 #endif
17078
17079 ecore_ilt_init_page_size(sc, INITOP_SET);
17080
17081 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
17082 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
17083 }
17084
17085 /* let the HW do it's magic... */
17086 DELAY(100000);
17087
17088 /* finish PXP init */
17089 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
17090 if (val != 1) {
17091 BLOGE(sc, "PXP2 CFG failed PXP2_REG_RQ_CFG_DONE val = 0x%x\n",
17092 val);
17093 return (-1);
17094 }
17095 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
17096 if (val != 1) {
17097 BLOGE(sc, "PXP2 RD_INIT failed val = 0x%x\n", val);
17098 return (-1);
17099 }
17100
17101 BLOGD(sc, DBG_LOAD, "after pxp init\n");
17102
17103 /*
17104 * Timer bug workaround for E2 only. We need to set the entire ILT to have
17105 * entries with value "0" and valid bit on. This needs to be done by the
17106 * first PF that is loaded in a path (i.e. common phase)
17107 */
17108 if (!CHIP_IS_E1x(sc)) {
17109 /*
17110 * In E2 there is a bug in the timers block that can cause function 6 / 7
17111 * (i.e. vnic3) to start even if it is marked as "scan-off".
17112 * This occurs when a different function (func2,3) is being marked
17113 * as "scan-off". Real-life scenario for example: if a driver is being
17114 * load-unloaded while func6,7 are down. This will cause the timer to access
17115 * the ilt, translate to a logical address and send a request to read/write.
17116 * Since the ilt for the function that is down is not valid, this will cause
17117 * a translation error which is unrecoverable.
17118 * The Workaround is intended to make sure that when this happens nothing
17119 * fatal will occur. The workaround:
17120 * 1. First PF driver which loads on a path will:
17121 * a. After taking the chip out of reset, by using pretend,
17122 * it will write "0" to the following registers of
17123 * the other vnics.
17124 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
17125 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
17126 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
17127 * And for itself it will write '1' to
17128 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
17129 * dmae-operations (writing to pram for example.)
17130 * note: can be done for only function 6,7 but cleaner this
17131 * way.
17132 * b. Write zero+valid to the entire ILT.
17133 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
17134 * VNIC3 (of that port). The range allocated will be the
17135 * entire ILT. This is needed to prevent ILT range error.
17136 * 2. Any PF driver load flow:
17137 * a. ILT update with the physical addresses of the allocated
17138 * logical pages.
17139 * b. Wait 20msec. - note that this timeout is needed to make
17140 * sure there are no requests in one of the PXP internal
17141 * queues with "old" ILT addresses.
17142 * c. PF enable in the PGLC.
17143 * d. Clear the was_error of the PF in the PGLC. (could have
17144 * occurred while driver was down)
17145 * e. PF enable in the CFC (WEAK + STRONG)
17146 * f. Timers scan enable
17147 * 3. PF driver unload flow:
17148 * a. Clear the Timers scan_en.
17149 * b. Polling for scan_on=0 for that PF.
17150 * c. Clear the PF enable bit in the PXP.
17151 * d. Clear the PF enable in the CFC (WEAK + STRONG)
17152 * e. Write zero+valid to all ILT entries (The valid bit must
17153 * stay set)
17154 * f. If this is VNIC 3 of a port then also init
17155 * first_timers_ilt_entry to zero and last_timers_ilt_entry
17156 * to the last entry in the ILT.
17157 *
17158 * Notes:
17159 * Currently the PF error in the PGLC is non recoverable.
17160 * In the future the there will be a recovery routine for this error.
17161 * Currently attention is masked.
17162 * Having an MCP lock on the load/unload process does not guarantee that
17163 * there is no Timer disable during Func6/7 enable. This is because the
17164 * Timers scan is currently being cleared by the MCP on FLR.
17165 * Step 2.d can be done only for PF6/7 and the driver can also check if
17166 * there is error before clearing it. But the flow above is simpler and
17167 * more general.
17168 * All ILT entries are written by zero+valid and not just PF6/7
17169 * ILT entries since in the future the ILT entries allocation for
17170 * PF-s might be dynamic.
17171 */
17172 struct ilt_client_info ilt_cli;
17173 struct ecore_ilt ilt;
17174
17175 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
17176 memset(&ilt, 0, sizeof(struct ecore_ilt));
17177
17178 /* initialize dummy TM client */
17179 ilt_cli.start = 0;
17180 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
17181 ilt_cli.client_num = ILT_CLIENT_TM;
17182
17183 /*
17184 * Step 1: set zeroes to all ilt page entries with valid bit on
17185 * Step 2: set the timers first/last ilt entry to point
17186 * to the entire range to prevent ILT range error for 3rd/4th
17187 * vnic (this code assumes existence of the vnic)
17188 *
17189 * both steps performed by call to ecore_ilt_client_init_op()
17190 * with dummy TM client
17191 *
17192 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
17193 * and his brother are split registers
17194 */
17195
17196 bxe_pretend_func(sc, (SC_PATH(sc) + 6));
17197 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
17198 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
17199
17200 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN);
17201 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN);
17202 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
17203 }
17204
17205 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
17206 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
17207
17208 if (!CHIP_IS_E1x(sc)) {
17209 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 :
17210 (CHIP_REV_IS_FPGA(sc) ? 400 : 0);
17211
17212 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
17213 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
17214
17215 /* let the HW do it's magic... */
17216 do {
17217 DELAY(200000);
17218 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
17219 } while (factor-- && (val != 1));
17220
17221 if (val != 1) {
17222 BLOGE(sc, "ATC_INIT failed val = 0x%x\n", val);
17223 return (-1);
17224 }
17225 }
17226
17227 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n");
17228
17229 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
17230
17231 bxe_iov_init_dmae(sc);
17232
17233 /* clean the DMAE memory */
17234 sc->dmae_ready = 1;
17235 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
17236
17237 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
17238
17239 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
17240
17241 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
17242
17243 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
17244
17245 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
17246 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
17247 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
17248 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
17249
17250 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
17251
17252 /* QM queues pointers table */
17253 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
17254
17255 /* soft reset pulse */
17256 REG_WR(sc, QM_REG_SOFT_RESET, 1);
17257 REG_WR(sc, QM_REG_SOFT_RESET, 0);
17258
17259 if (CNIC_SUPPORT(sc))
17260 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
17261
17262 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
17263 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT);
17264 if (!CHIP_REV_IS_SLOW(sc)) {
17265 /* enable hw interrupt from doorbell Q */
17266 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17267 }
17268
17269 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17270
17271 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17272 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
17273
17274 if (!CHIP_IS_E1(sc)) {
17275 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
17276 }
17277
17278 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
17279 if (IS_MF_AFEX(sc)) {
17280 /*
17281 * configure that AFEX and VLAN headers must be
17282 * received in AFEX mode
17283 */
17284 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
17285 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
17286 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
17287 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
17288 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
17289 } else {
17290 /*
17291 * Bit-map indicating which L2 hdrs may appear
17292 * after the basic Ethernet header
17293 */
17294 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
17295 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17296 }
17297 }
17298
17299 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
17300 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
17301 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
17302 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
17303
17304 if (!CHIP_IS_E1x(sc)) {
17305 /* reset VFC memories */
17306 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17307 VFC_MEMORIES_RST_REG_CAM_RST |
17308 VFC_MEMORIES_RST_REG_RAM_RST);
17309 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17310 VFC_MEMORIES_RST_REG_CAM_RST |
17311 VFC_MEMORIES_RST_REG_RAM_RST);
17312
17313 DELAY(20000);
17314 }
17315
17316 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
17317 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
17318 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
17319 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
17320
17321 /* sync semi rtc */
17322 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
17323 0x80000000);
17324 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
17325 0x80000000);
17326
17327 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
17328 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
17329 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
17330
17331 if (!CHIP_IS_E1x(sc)) {
17332 if (IS_MF_AFEX(sc)) {
17333 /*
17334 * configure that AFEX and VLAN headers must be
17335 * sent in AFEX mode
17336 */
17337 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
17338 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
17339 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
17340 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
17341 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
17342 } else {
17343 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
17344 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17345 }
17346 }
17347
17348 REG_WR(sc, SRC_REG_SOFT_RST, 1);
17349
17350 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
17351
17352 if (CNIC_SUPPORT(sc)) {
17353 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
17354 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
17355 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
17356 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
17357 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
17358 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
17359 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
17360 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
17361 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
17362 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
17363 }
17364 REG_WR(sc, SRC_REG_SOFT_RST, 0);
17365
17366 if (sizeof(union cdu_context) != 1024) {
17367 /* we currently assume that a context is 1024 bytes */
17368 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n",
17369 (long)sizeof(union cdu_context));
17370 }
17371
17372 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
17373 val = (4 << 24) + (0 << 12) + 1024;
17374 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
17375
17376 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
17377
17378 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
17379 /* enable context validation interrupt from CFC */
17380 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17381
17382 /* set the thresholds to prevent CFC/CDU race */
17383 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
17384 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
17385
17386 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) {
17387 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
17388 }
17389
17390 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
17391 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
17392
17393 /* Reset PCIE errors for debug */
17394 REG_WR(sc, 0x2814, 0xffffffff);
17395 REG_WR(sc, 0x3820, 0xffffffff);
17396
17397 if (!CHIP_IS_E1x(sc)) {
17398 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
17399 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
17400 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
17401 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
17402 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
17403 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
17404 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
17405 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
17406 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
17407 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
17408 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
17409 }
17410
17411 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
17412
17413 if (!CHIP_IS_E1(sc)) {
17414 /* in E3 this done in per-port section */
17415 if (!CHIP_IS_E3(sc))
17416 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
17417 }
17418
17419 if (CHIP_IS_E1H(sc)) {
17420 /* not applicable for E2 (and above ...) */
17421 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
17422 }
17423
17424 if (CHIP_REV_IS_SLOW(sc)) {
17425 DELAY(200000);
17426 }
17427
17428 /* finish CFC init */
17429 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
17430 if (val != 1) {
17431 BLOGE(sc, "CFC LL_INIT failed val=0x%x\n", val);
17432 return (-1);
17433 }
17434 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
17435 if (val != 1) {
17436 BLOGE(sc, "CFC AC_INIT failed val=0x%x\n", val);
17437 return (-1);
17438 }
17439 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
17440 if (val != 1) {
17441 BLOGE(sc, "CFC CAM_INIT failed val=0x%x\n", val);
17442 return (-1);
17443 }
17444 REG_WR(sc, CFC_REG_DEBUG0, 0);
17445
17446 if (CHIP_IS_E1(sc)) {
17447 /* read NIG statistic to see if this is our first up since powerup */
17448 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
17449 val = *BXE_SP(sc, wb_data[0]);
17450
17451 /* do internal memory self test */
17452 if ((val == 0) && bxe_int_mem_test(sc)) {
17453 BLOGE(sc, "internal mem self test failed val=0x%x\n", val);
17454 return (-1);
17455 }
17456 }
17457
17458 bxe_setup_fan_failure_detection(sc);
17459
17460 /* clear PXP2 attentions */
17461 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
17462
17463 bxe_enable_blocks_attention(sc);
17464
17465 if (!CHIP_REV_IS_SLOW(sc)) {
17466 ecore_enable_blocks_parity(sc);
17467 }
17468
17469 if (!BXE_NOMCP(sc)) {
17470 if (CHIP_IS_E1x(sc)) {
17471 bxe_common_init_phy(sc);
17472 }
17473 }
17474
17475 return (0);
17476 }
17477
17478 /**
17479 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase.
17480 *
17481 * @sc: driver handle
17482 */
17483 static int
bxe_init_hw_common_chip(struct bxe_softc * sc)17484 bxe_init_hw_common_chip(struct bxe_softc *sc)
17485 {
17486 int rc = bxe_init_hw_common(sc);
17487
17488 if (rc) {
17489 BLOGE(sc, "bxe_init_hw_common failed rc=%d\n", rc);
17490 return (rc);
17491 }
17492
17493 /* In E2 2-PORT mode, same ext phy is used for the two paths */
17494 if (!BXE_NOMCP(sc)) {
17495 bxe_common_init_phy(sc);
17496 }
17497
17498 return (0);
17499 }
17500
17501 static int
bxe_init_hw_port(struct bxe_softc * sc)17502 bxe_init_hw_port(struct bxe_softc *sc)
17503 {
17504 int port = SC_PORT(sc);
17505 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
17506 uint32_t low, high;
17507 uint32_t val;
17508
17509 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port);
17510
17511 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
17512
17513 ecore_init_block(sc, BLOCK_MISC, init_phase);
17514 ecore_init_block(sc, BLOCK_PXP, init_phase);
17515 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17516
17517 /*
17518 * Timers bug workaround: disables the pf_master bit in pglue at
17519 * common phase, we need to enable it here before any dmae access are
17520 * attempted. Therefore we manually added the enable-master to the
17521 * port phase (it also happens in the function phase)
17522 */
17523 if (!CHIP_IS_E1x(sc)) {
17524 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17525 }
17526
17527 ecore_init_block(sc, BLOCK_ATC, init_phase);
17528 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17529 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17530 ecore_init_block(sc, BLOCK_QM, init_phase);
17531
17532 ecore_init_block(sc, BLOCK_TCM, init_phase);
17533 ecore_init_block(sc, BLOCK_UCM, init_phase);
17534 ecore_init_block(sc, BLOCK_CCM, init_phase);
17535 ecore_init_block(sc, BLOCK_XCM, init_phase);
17536
17537 /* QM cid (connection) count */
17538 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
17539
17540 if (CNIC_SUPPORT(sc)) {
17541 ecore_init_block(sc, BLOCK_TM, init_phase);
17542 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20);
17543 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
17544 }
17545
17546 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17547
17548 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17549
17550 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) {
17551 if (IS_MF(sc)) {
17552 low = (BXE_ONE_PORT(sc) ? 160 : 246);
17553 } else if (sc->mtu > 4096) {
17554 if (BXE_ONE_PORT(sc)) {
17555 low = 160;
17556 } else {
17557 val = sc->mtu;
17558 /* (24*1024 + val*4)/256 */
17559 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
17560 }
17561 } else {
17562 low = (BXE_ONE_PORT(sc) ? 80 : 160);
17563 }
17564 high = (low + 56); /* 14*1024/256 */
17565 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
17566 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
17567 }
17568
17569 if (CHIP_IS_MODE_4_PORT(sc)) {
17570 REG_WR(sc, SC_PORT(sc) ?
17571 BRB1_REG_MAC_GUARANTIED_1 :
17572 BRB1_REG_MAC_GUARANTIED_0, 40);
17573 }
17574
17575 ecore_init_block(sc, BLOCK_PRS, init_phase);
17576 if (CHIP_IS_E3B0(sc)) {
17577 if (IS_MF_AFEX(sc)) {
17578 /* configure headers for AFEX mode */
17579 REG_WR(sc, SC_PORT(sc) ?
17580 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17581 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
17582 REG_WR(sc, SC_PORT(sc) ?
17583 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
17584 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
17585 REG_WR(sc, SC_PORT(sc) ?
17586 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
17587 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
17588 } else {
17589 /* Ovlan exists only if we are in multi-function +
17590 * switch-dependent mode, in switch-independent there
17591 * is no ovlan headers
17592 */
17593 REG_WR(sc, SC_PORT(sc) ?
17594 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17595 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
17596 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
17597 }
17598 }
17599
17600 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17601 ecore_init_block(sc, BLOCK_CSDM, init_phase);
17602 ecore_init_block(sc, BLOCK_USDM, init_phase);
17603 ecore_init_block(sc, BLOCK_XSDM, init_phase);
17604
17605 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17606 ecore_init_block(sc, BLOCK_USEM, init_phase);
17607 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17608 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17609
17610 ecore_init_block(sc, BLOCK_UPB, init_phase);
17611 ecore_init_block(sc, BLOCK_XPB, init_phase);
17612
17613 ecore_init_block(sc, BLOCK_PBF, init_phase);
17614
17615 if (CHIP_IS_E1x(sc)) {
17616 /* configure PBF to work without PAUSE mtu 9000 */
17617 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
17618
17619 /* update threshold */
17620 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
17621 /* update init credit */
17622 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
17623
17624 /* probe changes */
17625 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1);
17626 DELAY(50);
17627 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0);
17628 }
17629
17630 if (CNIC_SUPPORT(sc)) {
17631 ecore_init_block(sc, BLOCK_SRC, init_phase);
17632 }
17633
17634 ecore_init_block(sc, BLOCK_CDU, init_phase);
17635 ecore_init_block(sc, BLOCK_CFC, init_phase);
17636
17637 if (CHIP_IS_E1(sc)) {
17638 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
17639 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
17640 }
17641 ecore_init_block(sc, BLOCK_HC, init_phase);
17642
17643 ecore_init_block(sc, BLOCK_IGU, init_phase);
17644
17645 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
17646 /* init aeu_mask_attn_func_0/1:
17647 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
17648 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
17649 * bits 4-7 are used for "per vn group attention" */
17650 val = IS_MF(sc) ? 0xF7 : 0x7;
17651 /* Enable DCBX attention for all but E1 */
17652 val |= CHIP_IS_E1(sc) ? 0 : 0x10;
17653 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
17654
17655 ecore_init_block(sc, BLOCK_NIG, init_phase);
17656
17657 if (!CHIP_IS_E1x(sc)) {
17658 /* Bit-map indicating which L2 hdrs may appear after the
17659 * basic Ethernet header
17660 */
17661 if (IS_MF_AFEX(sc)) {
17662 REG_WR(sc, SC_PORT(sc) ?
17663 NIG_REG_P1_HDRS_AFTER_BASIC :
17664 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
17665 } else {
17666 REG_WR(sc, SC_PORT(sc) ?
17667 NIG_REG_P1_HDRS_AFTER_BASIC :
17668 NIG_REG_P0_HDRS_AFTER_BASIC,
17669 IS_MF_SD(sc) ? 7 : 6);
17670 }
17671
17672 if (CHIP_IS_E3(sc)) {
17673 REG_WR(sc, SC_PORT(sc) ?
17674 NIG_REG_LLH1_MF_MODE :
17675 NIG_REG_LLH_MF_MODE, IS_MF(sc));
17676 }
17677 }
17678 if (!CHIP_IS_E3(sc)) {
17679 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
17680 }
17681
17682 if (!CHIP_IS_E1(sc)) {
17683 /* 0x2 disable mf_ov, 0x1 enable */
17684 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
17685 (IS_MF_SD(sc) ? 0x1 : 0x2));
17686
17687 if (!CHIP_IS_E1x(sc)) {
17688 val = 0;
17689 switch (sc->devinfo.mf_info.mf_mode) {
17690 case MULTI_FUNCTION_SD:
17691 val = 1;
17692 break;
17693 case MULTI_FUNCTION_SI:
17694 case MULTI_FUNCTION_AFEX:
17695 val = 2;
17696 break;
17697 }
17698
17699 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
17700 NIG_REG_LLH0_CLS_TYPE), val);
17701 }
17702 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
17703 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
17704 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
17705 }
17706
17707 /* If SPIO5 is set to generate interrupts, enable it for this port */
17708 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17709 if (val & MISC_SPIO_SPIO5) {
17710 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
17711 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
17712 val = REG_RD(sc, reg_addr);
17713 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
17714 REG_WR(sc, reg_addr, val);
17715 }
17716
17717 return (0);
17718 }
17719
17720 static uint32_t
bxe_flr_clnup_reg_poll(struct bxe_softc * sc,uint32_t reg,uint32_t expected,uint32_t poll_count)17721 bxe_flr_clnup_reg_poll(struct bxe_softc *sc,
17722 uint32_t reg,
17723 uint32_t expected,
17724 uint32_t poll_count)
17725 {
17726 uint32_t cur_cnt = poll_count;
17727 uint32_t val;
17728
17729 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
17730 DELAY(FLR_WAIT_INTERVAL);
17731 }
17732
17733 return (val);
17734 }
17735
17736 static int
bxe_flr_clnup_poll_hw_counter(struct bxe_softc * sc,uint32_t reg,char * msg,uint32_t poll_cnt)17737 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc,
17738 uint32_t reg,
17739 char *msg,
17740 uint32_t poll_cnt)
17741 {
17742 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
17743
17744 if (val != 0) {
17745 BLOGE(sc, "%s usage count=%d\n", msg, val);
17746 return (1);
17747 }
17748
17749 return (0);
17750 }
17751
17752 /* Common routines with VF FLR cleanup */
17753 static uint32_t
bxe_flr_clnup_poll_count(struct bxe_softc * sc)17754 bxe_flr_clnup_poll_count(struct bxe_softc *sc)
17755 {
17756 /* adjust polling timeout */
17757 if (CHIP_REV_IS_EMUL(sc)) {
17758 return (FLR_POLL_CNT * 2000);
17759 }
17760
17761 if (CHIP_REV_IS_FPGA(sc)) {
17762 return (FLR_POLL_CNT * 120);
17763 }
17764
17765 return (FLR_POLL_CNT);
17766 }
17767
17768 static int
bxe_poll_hw_usage_counters(struct bxe_softc * sc,uint32_t poll_cnt)17769 bxe_poll_hw_usage_counters(struct bxe_softc *sc,
17770 uint32_t poll_cnt)
17771 {
17772 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
17773 if (bxe_flr_clnup_poll_hw_counter(sc,
17774 CFC_REG_NUM_LCIDS_INSIDE_PF,
17775 "CFC PF usage counter timed out",
17776 poll_cnt)) {
17777 return (1);
17778 }
17779
17780 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
17781 if (bxe_flr_clnup_poll_hw_counter(sc,
17782 DORQ_REG_PF_USAGE_CNT,
17783 "DQ PF usage counter timed out",
17784 poll_cnt)) {
17785 return (1);
17786 }
17787
17788 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
17789 if (bxe_flr_clnup_poll_hw_counter(sc,
17790 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc),
17791 "QM PF usage counter timed out",
17792 poll_cnt)) {
17793 return (1);
17794 }
17795
17796 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
17797 if (bxe_flr_clnup_poll_hw_counter(sc,
17798 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc),
17799 "Timers VNIC usage counter timed out",
17800 poll_cnt)) {
17801 return (1);
17802 }
17803
17804 if (bxe_flr_clnup_poll_hw_counter(sc,
17805 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc),
17806 "Timers NUM_SCANS usage counter timed out",
17807 poll_cnt)) {
17808 return (1);
17809 }
17810
17811 /* Wait DMAE PF usage counter to zero */
17812 if (bxe_flr_clnup_poll_hw_counter(sc,
17813 dmae_reg_go_c[INIT_DMAE_C(sc)],
17814 "DMAE dommand register timed out",
17815 poll_cnt)) {
17816 return (1);
17817 }
17818
17819 return (0);
17820 }
17821
17822 #define OP_GEN_PARAM(param) \
17823 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
17824 #define OP_GEN_TYPE(type) \
17825 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
17826 #define OP_GEN_AGG_VECT(index) \
17827 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
17828
17829 static int
bxe_send_final_clnup(struct bxe_softc * sc,uint8_t clnup_func,uint32_t poll_cnt)17830 bxe_send_final_clnup(struct bxe_softc *sc,
17831 uint8_t clnup_func,
17832 uint32_t poll_cnt)
17833 {
17834 uint32_t op_gen_command = 0;
17835 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
17836 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
17837 int ret = 0;
17838
17839 if (REG_RD(sc, comp_addr)) {
17840 BLOGE(sc, "Cleanup complete was not 0 before sending\n");
17841 return (1);
17842 }
17843
17844 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
17845 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
17846 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
17847 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
17848
17849 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n");
17850 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
17851
17852 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
17853 BLOGE(sc, "FW final cleanup did not succeed\n");
17854 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n",
17855 (REG_RD(sc, comp_addr)));
17856 bxe_panic(sc, ("FLR cleanup failed\n"));
17857 return (1);
17858 }
17859
17860 /* Zero completion for nxt FLR */
17861 REG_WR(sc, comp_addr, 0);
17862
17863 return (ret);
17864 }
17865
17866 static void
bxe_pbf_pN_buf_flushed(struct bxe_softc * sc,struct pbf_pN_buf_regs * regs,uint32_t poll_count)17867 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc,
17868 struct pbf_pN_buf_regs *regs,
17869 uint32_t poll_count)
17870 {
17871 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
17872 uint32_t cur_cnt = poll_count;
17873
17874 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
17875 crd = crd_start = REG_RD(sc, regs->crd);
17876 init_crd = REG_RD(sc, regs->init_crd);
17877
17878 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
17879 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd);
17880 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
17881
17882 while ((crd != init_crd) &&
17883 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) <
17884 (init_crd - crd_start))) {
17885 if (cur_cnt--) {
17886 DELAY(FLR_WAIT_INTERVAL);
17887 crd = REG_RD(sc, regs->crd);
17888 crd_freed = REG_RD(sc, regs->crd_freed);
17889 } else {
17890 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN);
17891 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd);
17892 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed);
17893 break;
17894 }
17895 }
17896
17897 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n",
17898 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17899 }
17900
17901 static void
bxe_pbf_pN_cmd_flushed(struct bxe_softc * sc,struct pbf_pN_cmd_regs * regs,uint32_t poll_count)17902 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc,
17903 struct pbf_pN_cmd_regs *regs,
17904 uint32_t poll_count)
17905 {
17906 uint32_t occup, to_free, freed, freed_start;
17907 uint32_t cur_cnt = poll_count;
17908
17909 occup = to_free = REG_RD(sc, regs->lines_occup);
17910 freed = freed_start = REG_RD(sc, regs->lines_freed);
17911
17912 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17913 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17914
17915 while (occup &&
17916 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) {
17917 if (cur_cnt--) {
17918 DELAY(FLR_WAIT_INTERVAL);
17919 occup = REG_RD(sc, regs->lines_occup);
17920 freed = REG_RD(sc, regs->lines_freed);
17921 } else {
17922 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN);
17923 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17924 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17925 break;
17926 }
17927 }
17928
17929 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n",
17930 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17931 }
17932
17933 static void
bxe_tx_hw_flushed(struct bxe_softc * sc,uint32_t poll_count)17934 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count)
17935 {
17936 struct pbf_pN_cmd_regs cmd_regs[] = {
17937 {0, (CHIP_IS_E3B0(sc)) ?
17938 PBF_REG_TQ_OCCUPANCY_Q0 :
17939 PBF_REG_P0_TQ_OCCUPANCY,
17940 (CHIP_IS_E3B0(sc)) ?
17941 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
17942 PBF_REG_P0_TQ_LINES_FREED_CNT},
17943 {1, (CHIP_IS_E3B0(sc)) ?
17944 PBF_REG_TQ_OCCUPANCY_Q1 :
17945 PBF_REG_P1_TQ_OCCUPANCY,
17946 (CHIP_IS_E3B0(sc)) ?
17947 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
17948 PBF_REG_P1_TQ_LINES_FREED_CNT},
17949 {4, (CHIP_IS_E3B0(sc)) ?
17950 PBF_REG_TQ_OCCUPANCY_LB_Q :
17951 PBF_REG_P4_TQ_OCCUPANCY,
17952 (CHIP_IS_E3B0(sc)) ?
17953 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
17954 PBF_REG_P4_TQ_LINES_FREED_CNT}
17955 };
17956
17957 struct pbf_pN_buf_regs buf_regs[] = {
17958 {0, (CHIP_IS_E3B0(sc)) ?
17959 PBF_REG_INIT_CRD_Q0 :
17960 PBF_REG_P0_INIT_CRD ,
17961 (CHIP_IS_E3B0(sc)) ?
17962 PBF_REG_CREDIT_Q0 :
17963 PBF_REG_P0_CREDIT,
17964 (CHIP_IS_E3B0(sc)) ?
17965 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
17966 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
17967 {1, (CHIP_IS_E3B0(sc)) ?
17968 PBF_REG_INIT_CRD_Q1 :
17969 PBF_REG_P1_INIT_CRD,
17970 (CHIP_IS_E3B0(sc)) ?
17971 PBF_REG_CREDIT_Q1 :
17972 PBF_REG_P1_CREDIT,
17973 (CHIP_IS_E3B0(sc)) ?
17974 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
17975 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
17976 {4, (CHIP_IS_E3B0(sc)) ?
17977 PBF_REG_INIT_CRD_LB_Q :
17978 PBF_REG_P4_INIT_CRD,
17979 (CHIP_IS_E3B0(sc)) ?
17980 PBF_REG_CREDIT_LB_Q :
17981 PBF_REG_P4_CREDIT,
17982 (CHIP_IS_E3B0(sc)) ?
17983 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
17984 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
17985 };
17986
17987 int i;
17988
17989 /* Verify the command queues are flushed P0, P1, P4 */
17990 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
17991 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
17992 }
17993
17994 /* Verify the transmission buffers are flushed P0, P1, P4 */
17995 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
17996 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
17997 }
17998 }
17999
18000 static void
bxe_hw_enable_status(struct bxe_softc * sc)18001 bxe_hw_enable_status(struct bxe_softc *sc)
18002 {
18003 uint32_t val;
18004
18005 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
18006 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
18007
18008 val = REG_RD(sc, PBF_REG_DISABLE_PF);
18009 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val);
18010
18011 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
18012 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
18013
18014 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
18015 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
18016
18017 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
18018 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
18019
18020 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
18021 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
18022
18023 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
18024 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
18025
18026 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
18027 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val);
18028 }
18029
18030 static int
bxe_pf_flr_clnup(struct bxe_softc * sc)18031 bxe_pf_flr_clnup(struct bxe_softc *sc)
18032 {
18033 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc);
18034
18035 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc));
18036
18037 /* Re-enable PF target read access */
18038 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
18039
18040 /* Poll HW usage counters */
18041 BLOGD(sc, DBG_LOAD, "Polling usage counters\n");
18042 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) {
18043 return (-1);
18044 }
18045
18046 /* Zero the igu 'trailing edge' and 'leading edge' */
18047
18048 /* Send the FW cleanup command */
18049 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) {
18050 return (-1);
18051 }
18052
18053 /* ATC cleanup */
18054
18055 /* Verify TX hw is flushed */
18056 bxe_tx_hw_flushed(sc, poll_cnt);
18057
18058 /* Wait 100ms (not adjusted according to platform) */
18059 DELAY(100000);
18060
18061 /* Verify no pending pci transactions */
18062 if (bxe_is_pcie_pending(sc)) {
18063 BLOGE(sc, "PCIE Transactions still pending\n");
18064 }
18065
18066 /* Debug */
18067 bxe_hw_enable_status(sc);
18068
18069 /*
18070 * Master enable - Due to WB DMAE writes performed before this
18071 * register is re-initialized as part of the regular function init
18072 */
18073 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
18074
18075 return (0);
18076 }
18077
18078 static int
bxe_init_hw_func(struct bxe_softc * sc)18079 bxe_init_hw_func(struct bxe_softc *sc)
18080 {
18081 int port = SC_PORT(sc);
18082 int func = SC_FUNC(sc);
18083 int init_phase = PHASE_PF0 + func;
18084 struct ecore_ilt *ilt = sc->ilt;
18085 uint16_t cdu_ilt_start;
18086 uint32_t addr, val;
18087 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
18088 int i, main_mem_width, rc;
18089
18090 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func);
18091
18092 /* FLR cleanup */
18093 if (!CHIP_IS_E1x(sc)) {
18094 rc = bxe_pf_flr_clnup(sc);
18095 if (rc) {
18096 BLOGE(sc, "FLR cleanup failed!\n");
18097 // XXX bxe_fw_dump(sc);
18098 // XXX bxe_idle_chk(sc);
18099 return (rc);
18100 }
18101 }
18102
18103 /* set MSI reconfigure capability */
18104 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18105 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
18106 val = REG_RD(sc, addr);
18107 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
18108 REG_WR(sc, addr, val);
18109 }
18110
18111 ecore_init_block(sc, BLOCK_PXP, init_phase);
18112 ecore_init_block(sc, BLOCK_PXP2, init_phase);
18113
18114 ilt = sc->ilt;
18115 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
18116
18117 for (i = 0; i < L2_ILT_LINES(sc); i++) {
18118 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
18119 ilt->lines[cdu_ilt_start + i].page_mapping =
18120 sc->context[i].vcxt_dma.paddr;
18121 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
18122 }
18123 ecore_ilt_init_op(sc, INITOP_SET);
18124
18125 /* Set NIC mode */
18126 REG_WR(sc, PRS_REG_NIC_MODE, 1);
18127 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n");
18128
18129 if (!CHIP_IS_E1x(sc)) {
18130 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
18131
18132 /* Turn on a single ISR mode in IGU if driver is going to use
18133 * INT#x or MSI
18134 */
18135 if (sc->interrupt_mode != INTR_MODE_MSIX) {
18136 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
18137 }
18138
18139 /*
18140 * Timers workaround bug: function init part.
18141 * Need to wait 20msec after initializing ILT,
18142 * needed to make sure there are no requests in
18143 * one of the PXP internal queues with "old" ILT addresses
18144 */
18145 DELAY(20000);
18146
18147 /*
18148 * Master enable - Due to WB DMAE writes performed before this
18149 * register is re-initialized as part of the regular function
18150 * init
18151 */
18152 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
18153 /* Enable the function in IGU */
18154 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
18155 }
18156
18157 sc->dmae_ready = 1;
18158
18159 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
18160
18161 if (!CHIP_IS_E1x(sc))
18162 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
18163
18164 ecore_init_block(sc, BLOCK_ATC, init_phase);
18165 ecore_init_block(sc, BLOCK_DMAE, init_phase);
18166 ecore_init_block(sc, BLOCK_NIG, init_phase);
18167 ecore_init_block(sc, BLOCK_SRC, init_phase);
18168 ecore_init_block(sc, BLOCK_MISC, init_phase);
18169 ecore_init_block(sc, BLOCK_TCM, init_phase);
18170 ecore_init_block(sc, BLOCK_UCM, init_phase);
18171 ecore_init_block(sc, BLOCK_CCM, init_phase);
18172 ecore_init_block(sc, BLOCK_XCM, init_phase);
18173 ecore_init_block(sc, BLOCK_TSEM, init_phase);
18174 ecore_init_block(sc, BLOCK_USEM, init_phase);
18175 ecore_init_block(sc, BLOCK_CSEM, init_phase);
18176 ecore_init_block(sc, BLOCK_XSEM, init_phase);
18177
18178 if (!CHIP_IS_E1x(sc))
18179 REG_WR(sc, QM_REG_PF_EN, 1);
18180
18181 if (!CHIP_IS_E1x(sc)) {
18182 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18183 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18184 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18185 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18186 }
18187 ecore_init_block(sc, BLOCK_QM, init_phase);
18188
18189 ecore_init_block(sc, BLOCK_TM, init_phase);
18190 ecore_init_block(sc, BLOCK_DORQ, init_phase);
18191
18192 bxe_iov_init_dq(sc);
18193
18194 ecore_init_block(sc, BLOCK_BRB1, init_phase);
18195 ecore_init_block(sc, BLOCK_PRS, init_phase);
18196 ecore_init_block(sc, BLOCK_TSDM, init_phase);
18197 ecore_init_block(sc, BLOCK_CSDM, init_phase);
18198 ecore_init_block(sc, BLOCK_USDM, init_phase);
18199 ecore_init_block(sc, BLOCK_XSDM, init_phase);
18200 ecore_init_block(sc, BLOCK_UPB, init_phase);
18201 ecore_init_block(sc, BLOCK_XPB, init_phase);
18202 ecore_init_block(sc, BLOCK_PBF, init_phase);
18203 if (!CHIP_IS_E1x(sc))
18204 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
18205
18206 ecore_init_block(sc, BLOCK_CDU, init_phase);
18207
18208 ecore_init_block(sc, BLOCK_CFC, init_phase);
18209
18210 if (!CHIP_IS_E1x(sc))
18211 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
18212
18213 if (IS_MF(sc)) {
18214 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
18215 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc));
18216 }
18217
18218 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
18219
18220 /* HC init per function */
18221 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18222 if (CHIP_IS_E1H(sc)) {
18223 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18224
18225 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18226 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18227 }
18228 ecore_init_block(sc, BLOCK_HC, init_phase);
18229
18230 } else {
18231 int num_segs, sb_idx, prod_offset;
18232
18233 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18234
18235 if (!CHIP_IS_E1x(sc)) {
18236 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18237 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18238 }
18239
18240 ecore_init_block(sc, BLOCK_IGU, init_phase);
18241
18242 if (!CHIP_IS_E1x(sc)) {
18243 int dsb_idx = 0;
18244 /**
18245 * Producer memory:
18246 * E2 mode: address 0-135 match to the mapping memory;
18247 * 136 - PF0 default prod; 137 - PF1 default prod;
18248 * 138 - PF2 default prod; 139 - PF3 default prod;
18249 * 140 - PF0 attn prod; 141 - PF1 attn prod;
18250 * 142 - PF2 attn prod; 143 - PF3 attn prod;
18251 * 144-147 reserved.
18252 *
18253 * E1.5 mode - In backward compatible mode;
18254 * for non default SB; each even line in the memory
18255 * holds the U producer and each odd line hold
18256 * the C producer. The first 128 producers are for
18257 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
18258 * producers are for the DSB for each PF.
18259 * Each PF has five segments: (the order inside each
18260 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
18261 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
18262 * 144-147 attn prods;
18263 */
18264 /* non-default-status-blocks */
18265 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18266 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
18267 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
18268 prod_offset = (sc->igu_base_sb + sb_idx) *
18269 num_segs;
18270
18271 for (i = 0; i < num_segs; i++) {
18272 addr = IGU_REG_PROD_CONS_MEMORY +
18273 (prod_offset + i) * 4;
18274 REG_WR(sc, addr, 0);
18275 }
18276 /* send consumer update with value 0 */
18277 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx,
18278 USTORM_ID, 0, IGU_INT_NOP, 1);
18279 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
18280 }
18281
18282 /* default-status-blocks */
18283 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18284 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
18285
18286 if (CHIP_IS_MODE_4_PORT(sc))
18287 dsb_idx = SC_FUNC(sc);
18288 else
18289 dsb_idx = SC_VN(sc);
18290
18291 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
18292 IGU_BC_BASE_DSB_PROD + dsb_idx :
18293 IGU_NORM_BASE_DSB_PROD + dsb_idx);
18294
18295 /*
18296 * igu prods come in chunks of E1HVN_MAX (4) -
18297 * does not matters what is the current chip mode
18298 */
18299 for (i = 0; i < (num_segs * E1HVN_MAX);
18300 i += E1HVN_MAX) {
18301 addr = IGU_REG_PROD_CONS_MEMORY +
18302 (prod_offset + i)*4;
18303 REG_WR(sc, addr, 0);
18304 }
18305 /* send consumer update with 0 */
18306 if (CHIP_INT_MODE_IS_BC(sc)) {
18307 bxe_ack_sb(sc, sc->igu_dsb_id,
18308 USTORM_ID, 0, IGU_INT_NOP, 1);
18309 bxe_ack_sb(sc, sc->igu_dsb_id,
18310 CSTORM_ID, 0, IGU_INT_NOP, 1);
18311 bxe_ack_sb(sc, sc->igu_dsb_id,
18312 XSTORM_ID, 0, IGU_INT_NOP, 1);
18313 bxe_ack_sb(sc, sc->igu_dsb_id,
18314 TSTORM_ID, 0, IGU_INT_NOP, 1);
18315 bxe_ack_sb(sc, sc->igu_dsb_id,
18316 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18317 } else {
18318 bxe_ack_sb(sc, sc->igu_dsb_id,
18319 USTORM_ID, 0, IGU_INT_NOP, 1);
18320 bxe_ack_sb(sc, sc->igu_dsb_id,
18321 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18322 }
18323 bxe_igu_clear_sb(sc, sc->igu_dsb_id);
18324
18325 /* !!! these should become driver const once
18326 rf-tool supports split-68 const */
18327 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
18328 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
18329 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
18330 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
18331 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
18332 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
18333 }
18334 }
18335
18336 /* Reset PCIE errors for debug */
18337 REG_WR(sc, 0x2114, 0xffffffff);
18338 REG_WR(sc, 0x2120, 0xffffffff);
18339
18340 if (CHIP_IS_E1x(sc)) {
18341 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
18342 main_mem_base = HC_REG_MAIN_MEMORY +
18343 SC_PORT(sc) * (main_mem_size * 4);
18344 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
18345 main_mem_width = 8;
18346
18347 val = REG_RD(sc, main_mem_prty_clr);
18348 if (val) {
18349 BLOGD(sc, DBG_LOAD,
18350 "Parity errors in HC block during function init (0x%x)!\n",
18351 val);
18352 }
18353
18354 /* Clear "false" parity errors in MSI-X table */
18355 for (i = main_mem_base;
18356 i < main_mem_base + main_mem_size * 4;
18357 i += main_mem_width) {
18358 bxe_read_dmae(sc, i, main_mem_width / 4);
18359 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data),
18360 i, main_mem_width / 4);
18361 }
18362 /* Clear HC parity attention */
18363 REG_RD(sc, main_mem_prty_clr);
18364 }
18365
18366 #if 1
18367 /* Enable STORMs SP logging */
18368 REG_WR8(sc, BAR_USTRORM_INTMEM +
18369 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18370 REG_WR8(sc, BAR_TSTRORM_INTMEM +
18371 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18372 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18373 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18374 REG_WR8(sc, BAR_XSTRORM_INTMEM +
18375 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18376 #endif
18377
18378 elink_phy_probe(&sc->link_params);
18379
18380 return (0);
18381 }
18382
18383 static void
bxe_link_reset(struct bxe_softc * sc)18384 bxe_link_reset(struct bxe_softc *sc)
18385 {
18386 if (!BXE_NOMCP(sc)) {
18387 bxe_acquire_phy_lock(sc);
18388 elink_lfa_reset(&sc->link_params, &sc->link_vars);
18389 bxe_release_phy_lock(sc);
18390 } else {
18391 if (!CHIP_REV_IS_SLOW(sc)) {
18392 BLOGW(sc, "Bootcode is missing - cannot reset link\n");
18393 }
18394 }
18395 }
18396
18397 static void
bxe_reset_port(struct bxe_softc * sc)18398 bxe_reset_port(struct bxe_softc *sc)
18399 {
18400 int port = SC_PORT(sc);
18401 uint32_t val;
18402
18403 ELINK_DEBUG_P0(sc, "bxe_reset_port called\n");
18404 /* reset physical Link */
18405 bxe_link_reset(sc);
18406
18407 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
18408
18409 /* Do not rcv packets to BRB */
18410 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
18411 /* Do not direct rcv packets that are not for MCP to the BRB */
18412 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
18413 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
18414
18415 /* Configure AEU */
18416 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
18417
18418 DELAY(100000);
18419
18420 /* Check for BRB port occupancy */
18421 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
18422 if (val) {
18423 BLOGD(sc, DBG_LOAD,
18424 "BRB1 is not empty, %d blocks are occupied\n", val);
18425 }
18426
18427 /* TODO: Close Doorbell port? */
18428 }
18429
18430 static void
bxe_ilt_wr(struct bxe_softc * sc,uint32_t index,bus_addr_t addr)18431 bxe_ilt_wr(struct bxe_softc *sc,
18432 uint32_t index,
18433 bus_addr_t addr)
18434 {
18435 int reg;
18436 uint32_t wb_write[2];
18437
18438 if (CHIP_IS_E1(sc)) {
18439 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
18440 } else {
18441 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
18442 }
18443
18444 wb_write[0] = ONCHIP_ADDR1(addr);
18445 wb_write[1] = ONCHIP_ADDR2(addr);
18446 REG_WR_DMAE(sc, reg, wb_write, 2);
18447 }
18448
18449 static void
bxe_clear_func_ilt(struct bxe_softc * sc,uint32_t func)18450 bxe_clear_func_ilt(struct bxe_softc *sc,
18451 uint32_t func)
18452 {
18453 uint32_t i, base = FUNC_ILT_BASE(func);
18454 for (i = base; i < base + ILT_PER_FUNC; i++) {
18455 bxe_ilt_wr(sc, i, 0);
18456 }
18457 }
18458
18459 static void
bxe_reset_func(struct bxe_softc * sc)18460 bxe_reset_func(struct bxe_softc *sc)
18461 {
18462 struct bxe_fastpath *fp;
18463 int port = SC_PORT(sc);
18464 int func = SC_FUNC(sc);
18465 int i;
18466
18467 /* Disable the function in the FW */
18468 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
18469 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
18470 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
18471 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
18472
18473 /* FP SBs */
18474 FOR_EACH_ETH_QUEUE(sc, i) {
18475 fp = &sc->fp[i];
18476 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18477 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
18478 SB_DISABLED);
18479 }
18480
18481 /* SP SB */
18482 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18483 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
18484 SB_DISABLED);
18485
18486 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
18487 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0);
18488 }
18489
18490 /* Configure IGU */
18491 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18492 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18493 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18494 } else {
18495 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18496 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18497 }
18498
18499 if (CNIC_LOADED(sc)) {
18500 /* Disable Timer scan */
18501 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
18502 /*
18503 * Wait for at least 10ms and up to 2 second for the timers
18504 * scan to complete
18505 */
18506 for (i = 0; i < 200; i++) {
18507 DELAY(10000);
18508 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))
18509 break;
18510 }
18511 }
18512
18513 /* Clear ILT */
18514 bxe_clear_func_ilt(sc, func);
18515
18516 /*
18517 * Timers workaround bug for E2: if this is vnic-3,
18518 * we need to set the entire ilt range for this timers.
18519 */
18520 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
18521 struct ilt_client_info ilt_cli;
18522 /* use dummy TM client */
18523 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
18524 ilt_cli.start = 0;
18525 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
18526 ilt_cli.client_num = ILT_CLIENT_TM;
18527
18528 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
18529 }
18530
18531 /* this assumes that reset_port() called before reset_func()*/
18532 if (!CHIP_IS_E1x(sc)) {
18533 bxe_pf_disable(sc);
18534 }
18535
18536 sc->dmae_ready = 0;
18537 }
18538
18539 static int
bxe_gunzip_init(struct bxe_softc * sc)18540 bxe_gunzip_init(struct bxe_softc *sc)
18541 {
18542 return (0);
18543 }
18544
18545 static void
bxe_gunzip_end(struct bxe_softc * sc)18546 bxe_gunzip_end(struct bxe_softc *sc)
18547 {
18548 return;
18549 }
18550
18551 static int
bxe_init_firmware(struct bxe_softc * sc)18552 bxe_init_firmware(struct bxe_softc *sc)
18553 {
18554 if (CHIP_IS_E1(sc)) {
18555 ecore_init_e1_firmware(sc);
18556 sc->iro_array = e1_iro_arr;
18557 } else if (CHIP_IS_E1H(sc)) {
18558 ecore_init_e1h_firmware(sc);
18559 sc->iro_array = e1h_iro_arr;
18560 } else if (!CHIP_IS_E1x(sc)) {
18561 ecore_init_e2_firmware(sc);
18562 sc->iro_array = e2_iro_arr;
18563 } else {
18564 BLOGE(sc, "Unsupported chip revision\n");
18565 return (-1);
18566 }
18567
18568 return (0);
18569 }
18570
18571 static void
bxe_release_firmware(struct bxe_softc * sc)18572 bxe_release_firmware(struct bxe_softc *sc)
18573 {
18574 /* Do nothing */
18575 return;
18576 }
18577
18578 static int
ecore_gunzip(struct bxe_softc * sc,const uint8_t * zbuf,int len)18579 ecore_gunzip(struct bxe_softc *sc,
18580 const uint8_t *zbuf,
18581 int len)
18582 {
18583 /* XXX : Implement... */
18584 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n");
18585 return (FALSE);
18586 }
18587
18588 static void
ecore_reg_wr_ind(struct bxe_softc * sc,uint32_t addr,uint32_t val)18589 ecore_reg_wr_ind(struct bxe_softc *sc,
18590 uint32_t addr,
18591 uint32_t val)
18592 {
18593 bxe_reg_wr_ind(sc, addr, val);
18594 }
18595
18596 static void
ecore_write_dmae_phys_len(struct bxe_softc * sc,bus_addr_t phys_addr,uint32_t addr,uint32_t len)18597 ecore_write_dmae_phys_len(struct bxe_softc *sc,
18598 bus_addr_t phys_addr,
18599 uint32_t addr,
18600 uint32_t len)
18601 {
18602 bxe_write_dmae_phys_len(sc, phys_addr, addr, len);
18603 }
18604
18605 void
ecore_storm_memset_struct(struct bxe_softc * sc,uint32_t addr,size_t size,uint32_t * data)18606 ecore_storm_memset_struct(struct bxe_softc *sc,
18607 uint32_t addr,
18608 size_t size,
18609 uint32_t *data)
18610 {
18611 uint8_t i;
18612 for (i = 0; i < size/4; i++) {
18613 REG_WR(sc, addr + (i * 4), data[i]);
18614 }
18615 }
18616
18617
18618 /*
18619 * character device - ioctl interface definitions
18620 */
18621
18622
18623 #include "bxe_dump.h"
18624 #include "bxe_ioctl.h"
18625 #include <sys/conf.h>
18626
18627 static int bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
18628 struct thread *td);
18629
18630 static struct cdevsw bxe_cdevsw = {
18631 .d_version = D_VERSION,
18632 .d_ioctl = bxe_eioctl,
18633 .d_name = "bxecnic",
18634 };
18635
18636 #define BXE_PATH(sc) (CHIP_IS_E1x(sc) ? 0 : (sc->pcie_func & 1))
18637
18638
18639 #define DUMP_ALL_PRESETS 0x1FFF
18640 #define DUMP_MAX_PRESETS 13
18641 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
18642 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
18643 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
18644 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
18645 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
18646
18647 #define IS_REG_IN_PRESET(presets, idx) \
18648 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
18649
18650
18651 static int
bxe_get_preset_regs_len(struct bxe_softc * sc,uint32_t preset)18652 bxe_get_preset_regs_len(struct bxe_softc *sc, uint32_t preset)
18653 {
18654 if (CHIP_IS_E1(sc))
18655 return dump_num_registers[0][preset-1];
18656 else if (CHIP_IS_E1H(sc))
18657 return dump_num_registers[1][preset-1];
18658 else if (CHIP_IS_E2(sc))
18659 return dump_num_registers[2][preset-1];
18660 else if (CHIP_IS_E3A0(sc))
18661 return dump_num_registers[3][preset-1];
18662 else if (CHIP_IS_E3B0(sc))
18663 return dump_num_registers[4][preset-1];
18664 else
18665 return 0;
18666 }
18667
18668 static int
bxe_get_total_regs_len32(struct bxe_softc * sc)18669 bxe_get_total_regs_len32(struct bxe_softc *sc)
18670 {
18671 uint32_t preset_idx;
18672 int regdump_len32 = 0;
18673
18674
18675 /* Calculate the total preset regs length */
18676 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18677 regdump_len32 += bxe_get_preset_regs_len(sc, preset_idx);
18678 }
18679
18680 return regdump_len32;
18681 }
18682
18683 static const uint32_t *
__bxe_get_page_addr_ar(struct bxe_softc * sc)18684 __bxe_get_page_addr_ar(struct bxe_softc *sc)
18685 {
18686 if (CHIP_IS_E2(sc))
18687 return page_vals_e2;
18688 else if (CHIP_IS_E3(sc))
18689 return page_vals_e3;
18690 else
18691 return NULL;
18692 }
18693
18694 static uint32_t
__bxe_get_page_reg_num(struct bxe_softc * sc)18695 __bxe_get_page_reg_num(struct bxe_softc *sc)
18696 {
18697 if (CHIP_IS_E2(sc))
18698 return PAGE_MODE_VALUES_E2;
18699 else if (CHIP_IS_E3(sc))
18700 return PAGE_MODE_VALUES_E3;
18701 else
18702 return 0;
18703 }
18704
18705 static const uint32_t *
__bxe_get_page_write_ar(struct bxe_softc * sc)18706 __bxe_get_page_write_ar(struct bxe_softc *sc)
18707 {
18708 if (CHIP_IS_E2(sc))
18709 return page_write_regs_e2;
18710 else if (CHIP_IS_E3(sc))
18711 return page_write_regs_e3;
18712 else
18713 return NULL;
18714 }
18715
18716 static uint32_t
__bxe_get_page_write_num(struct bxe_softc * sc)18717 __bxe_get_page_write_num(struct bxe_softc *sc)
18718 {
18719 if (CHIP_IS_E2(sc))
18720 return PAGE_WRITE_REGS_E2;
18721 else if (CHIP_IS_E3(sc))
18722 return PAGE_WRITE_REGS_E3;
18723 else
18724 return 0;
18725 }
18726
18727 static const struct reg_addr *
__bxe_get_page_read_ar(struct bxe_softc * sc)18728 __bxe_get_page_read_ar(struct bxe_softc *sc)
18729 {
18730 if (CHIP_IS_E2(sc))
18731 return page_read_regs_e2;
18732 else if (CHIP_IS_E3(sc))
18733 return page_read_regs_e3;
18734 else
18735 return NULL;
18736 }
18737
18738 static uint32_t
__bxe_get_page_read_num(struct bxe_softc * sc)18739 __bxe_get_page_read_num(struct bxe_softc *sc)
18740 {
18741 if (CHIP_IS_E2(sc))
18742 return PAGE_READ_REGS_E2;
18743 else if (CHIP_IS_E3(sc))
18744 return PAGE_READ_REGS_E3;
18745 else
18746 return 0;
18747 }
18748
18749 static bool
bxe_is_reg_in_chip(struct bxe_softc * sc,const struct reg_addr * reg_info)18750 bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info)
18751 {
18752 if (CHIP_IS_E1(sc))
18753 return IS_E1_REG(reg_info->chips);
18754 else if (CHIP_IS_E1H(sc))
18755 return IS_E1H_REG(reg_info->chips);
18756 else if (CHIP_IS_E2(sc))
18757 return IS_E2_REG(reg_info->chips);
18758 else if (CHIP_IS_E3A0(sc))
18759 return IS_E3A0_REG(reg_info->chips);
18760 else if (CHIP_IS_E3B0(sc))
18761 return IS_E3B0_REG(reg_info->chips);
18762 else
18763 return 0;
18764 }
18765
18766 static bool
bxe_is_wreg_in_chip(struct bxe_softc * sc,const struct wreg_addr * wreg_info)18767 bxe_is_wreg_in_chip(struct bxe_softc *sc, const struct wreg_addr *wreg_info)
18768 {
18769 if (CHIP_IS_E1(sc))
18770 return IS_E1_REG(wreg_info->chips);
18771 else if (CHIP_IS_E1H(sc))
18772 return IS_E1H_REG(wreg_info->chips);
18773 else if (CHIP_IS_E2(sc))
18774 return IS_E2_REG(wreg_info->chips);
18775 else if (CHIP_IS_E3A0(sc))
18776 return IS_E3A0_REG(wreg_info->chips);
18777 else if (CHIP_IS_E3B0(sc))
18778 return IS_E3B0_REG(wreg_info->chips);
18779 else
18780 return 0;
18781 }
18782
18783 /**
18784 * bxe_read_pages_regs - read "paged" registers
18785 *
18786 * @bp device handle
18787 * @p output buffer
18788 *
18789 * Reads "paged" memories: memories that may only be read by first writing to a
18790 * specific address ("write address") and then reading from a specific address
18791 * ("read address"). There may be more than one write address per "page" and
18792 * more than one read address per write address.
18793 */
18794 static void
bxe_read_pages_regs(struct bxe_softc * sc,uint32_t * p,uint32_t preset)18795 bxe_read_pages_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18796 {
18797 uint32_t i, j, k, n;
18798
18799 /* addresses of the paged registers */
18800 const uint32_t *page_addr = __bxe_get_page_addr_ar(sc);
18801 /* number of paged registers */
18802 int num_pages = __bxe_get_page_reg_num(sc);
18803 /* write addresses */
18804 const uint32_t *write_addr = __bxe_get_page_write_ar(sc);
18805 /* number of write addresses */
18806 int write_num = __bxe_get_page_write_num(sc);
18807 /* read addresses info */
18808 const struct reg_addr *read_addr = __bxe_get_page_read_ar(sc);
18809 /* number of read addresses */
18810 int read_num = __bxe_get_page_read_num(sc);
18811 uint32_t addr, size;
18812
18813 for (i = 0; i < num_pages; i++) {
18814 for (j = 0; j < write_num; j++) {
18815 REG_WR(sc, write_addr[j], page_addr[i]);
18816
18817 for (k = 0; k < read_num; k++) {
18818 if (IS_REG_IN_PRESET(read_addr[k].presets, preset)) {
18819 size = read_addr[k].size;
18820 for (n = 0; n < size; n++) {
18821 addr = read_addr[k].addr + n*4;
18822 *p++ = REG_RD(sc, addr);
18823 }
18824 }
18825 }
18826 }
18827 }
18828 return;
18829 }
18830
18831
18832 static int
bxe_get_preset_regs(struct bxe_softc * sc,uint32_t * p,uint32_t preset)18833 bxe_get_preset_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18834 {
18835 uint32_t i, j, addr;
18836 const struct wreg_addr *wreg_addr_p = NULL;
18837
18838 if (CHIP_IS_E1(sc))
18839 wreg_addr_p = &wreg_addr_e1;
18840 else if (CHIP_IS_E1H(sc))
18841 wreg_addr_p = &wreg_addr_e1h;
18842 else if (CHIP_IS_E2(sc))
18843 wreg_addr_p = &wreg_addr_e2;
18844 else if (CHIP_IS_E3A0(sc))
18845 wreg_addr_p = &wreg_addr_e3;
18846 else if (CHIP_IS_E3B0(sc))
18847 wreg_addr_p = &wreg_addr_e3b0;
18848 else
18849 return (-1);
18850
18851 /* Read the idle_chk registers */
18852 for (i = 0; i < IDLE_REGS_COUNT; i++) {
18853 if (bxe_is_reg_in_chip(sc, &idle_reg_addrs[i]) &&
18854 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
18855 for (j = 0; j < idle_reg_addrs[i].size; j++)
18856 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4);
18857 }
18858 }
18859
18860 /* Read the regular registers */
18861 for (i = 0; i < REGS_COUNT; i++) {
18862 if (bxe_is_reg_in_chip(sc, ®_addrs[i]) &&
18863 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
18864 for (j = 0; j < reg_addrs[i].size; j++)
18865 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4);
18866 }
18867 }
18868
18869 /* Read the CAM registers */
18870 if (bxe_is_wreg_in_chip(sc, wreg_addr_p) &&
18871 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
18872 for (i = 0; i < wreg_addr_p->size; i++) {
18873 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4);
18874
18875 /* In case of wreg_addr register, read additional
18876 registers from read_regs array
18877 */
18878 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
18879 addr = *(wreg_addr_p->read_regs);
18880 *p++ = REG_RD(sc, addr + j*4);
18881 }
18882 }
18883 }
18884
18885 /* Paged registers are supported in E2 & E3 only */
18886 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
18887 /* Read "paged" registers */
18888 bxe_read_pages_regs(sc, p, preset);
18889 }
18890
18891 return 0;
18892 }
18893
18894 int
bxe_grc_dump(struct bxe_softc * sc)18895 bxe_grc_dump(struct bxe_softc *sc)
18896 {
18897 int rval = 0;
18898 uint32_t preset_idx;
18899 uint8_t *buf;
18900 uint32_t size;
18901 struct dump_header *d_hdr;
18902 uint32_t i;
18903 uint32_t reg_val;
18904 uint32_t reg_addr;
18905 uint32_t cmd_offset;
18906 struct ecore_ilt *ilt = SC_ILT(sc);
18907 struct bxe_fastpath *fp;
18908 struct ilt_client_info *ilt_cli;
18909 int grc_dump_size;
18910
18911
18912 if (sc->grcdump_done || sc->grcdump_started)
18913 return (rval);
18914
18915 sc->grcdump_started = 1;
18916 BLOGI(sc, "Started collecting grcdump\n");
18917
18918 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
18919 sizeof(struct dump_header);
18920
18921 sc->grc_dump = malloc(grc_dump_size, M_DEVBUF, M_NOWAIT);
18922
18923 if (sc->grc_dump == NULL) {
18924 BLOGW(sc, "Unable to allocate memory for grcdump collection\n");
18925 return(ENOMEM);
18926 }
18927
18928
18929
18930 /* Disable parity attentions as long as following dump may
18931 * cause false alarms by reading never written registers. We
18932 * will re-enable parity attentions right after the dump.
18933 */
18934
18935 /* Disable parity on path 0 */
18936 bxe_pretend_func(sc, 0);
18937
18938 ecore_disable_blocks_parity(sc);
18939
18940 /* Disable parity on path 1 */
18941 bxe_pretend_func(sc, 1);
18942 ecore_disable_blocks_parity(sc);
18943
18944 /* Return to current function */
18945 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
18946
18947 buf = sc->grc_dump;
18948 d_hdr = sc->grc_dump;
18949
18950 d_hdr->header_size = (sizeof(struct dump_header) >> 2) - 1;
18951 d_hdr->version = BNX2X_DUMP_VERSION;
18952 d_hdr->preset = DUMP_ALL_PRESETS;
18953
18954 if (CHIP_IS_E1(sc)) {
18955 d_hdr->dump_meta_data = DUMP_CHIP_E1;
18956 } else if (CHIP_IS_E1H(sc)) {
18957 d_hdr->dump_meta_data = DUMP_CHIP_E1H;
18958 } else if (CHIP_IS_E2(sc)) {
18959 d_hdr->dump_meta_data = DUMP_CHIP_E2 |
18960 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18961 } else if (CHIP_IS_E3A0(sc)) {
18962 d_hdr->dump_meta_data = DUMP_CHIP_E3A0 |
18963 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18964 } else if (CHIP_IS_E3B0(sc)) {
18965 d_hdr->dump_meta_data = DUMP_CHIP_E3B0 |
18966 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18967 }
18968
18969 buf += sizeof(struct dump_header);
18970
18971 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18972
18973 /* Skip presets with IOR */
18974 if ((preset_idx == 2) || (preset_idx == 5) || (preset_idx == 8) ||
18975 (preset_idx == 11))
18976 continue;
18977
18978 rval = bxe_get_preset_regs(sc, (uint32_t *)buf, preset_idx);
18979
18980 if (rval)
18981 break;
18982
18983 size = bxe_get_preset_regs_len(sc, preset_idx) * (sizeof (uint32_t));
18984
18985 buf += size;
18986 }
18987
18988 bxe_pretend_func(sc, 0);
18989 ecore_clear_blocks_parity(sc);
18990 ecore_enable_blocks_parity(sc);
18991
18992 bxe_pretend_func(sc, 1);
18993 ecore_clear_blocks_parity(sc);
18994 ecore_enable_blocks_parity(sc);
18995
18996 /* Return to current function */
18997 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
18998
18999
19000
19001 if(sc->state == BXE_STATE_OPEN) {
19002 if(sc->fw_stats_req != NULL) {
19003 BLOGI(sc, "fw stats start_paddr %#jx end_paddr %#jx vaddr %p size 0x%x\n",
19004 (uintmax_t)sc->fw_stats_req_mapping,
19005 (uintmax_t)sc->fw_stats_data_mapping,
19006 sc->fw_stats_req, (sc->fw_stats_req_size + sc->fw_stats_data_size));
19007 }
19008 if(sc->def_sb != NULL) {
19009 BLOGI(sc, "def_status_block paddr %p vaddr %p size 0x%zx\n",
19010 (void *)sc->def_sb_dma.paddr, sc->def_sb,
19011 sizeof(struct host_sp_status_block));
19012 }
19013 if(sc->eq_dma.vaddr != NULL) {
19014 BLOGI(sc, "event_queue paddr %#jx vaddr %p size 0x%x\n",
19015 (uintmax_t)sc->eq_dma.paddr, sc->eq_dma.vaddr, BCM_PAGE_SIZE);
19016 }
19017 if(sc->sp_dma.vaddr != NULL) {
19018 BLOGI(sc, "slow path paddr %#jx vaddr %p size 0x%zx\n",
19019 (uintmax_t)sc->sp_dma.paddr, sc->sp_dma.vaddr,
19020 sizeof(struct bxe_slowpath));
19021 }
19022 if(sc->spq_dma.vaddr != NULL) {
19023 BLOGI(sc, "slow path queue paddr %#jx vaddr %p size 0x%x\n",
19024 (uintmax_t)sc->spq_dma.paddr, sc->spq_dma.vaddr, BCM_PAGE_SIZE);
19025 }
19026 if(sc->gz_buf_dma.vaddr != NULL) {
19027 BLOGI(sc, "fw_buf paddr %#jx vaddr %p size 0x%x\n",
19028 (uintmax_t)sc->gz_buf_dma.paddr, sc->gz_buf_dma.vaddr,
19029 FW_BUF_SIZE);
19030 }
19031 for (i = 0; i < sc->num_queues; i++) {
19032 fp = &sc->fp[i];
19033 if(fp->sb_dma.vaddr != NULL && fp->tx_dma.vaddr != NULL &&
19034 fp->rx_dma.vaddr != NULL && fp->rcq_dma.vaddr != NULL &&
19035 fp->rx_sge_dma.vaddr != NULL) {
19036
19037 BLOGI(sc, "FP status block fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
19038 (uintmax_t)fp->sb_dma.paddr, fp->sb_dma.vaddr,
19039 sizeof(union bxe_host_hc_status_block));
19040 BLOGI(sc, "TX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
19041 (uintmax_t)fp->tx_dma.paddr, fp->tx_dma.vaddr,
19042 (BCM_PAGE_SIZE * TX_BD_NUM_PAGES));
19043 BLOGI(sc, "RX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
19044 (uintmax_t)fp->rx_dma.paddr, fp->rx_dma.vaddr,
19045 (BCM_PAGE_SIZE * RX_BD_NUM_PAGES));
19046 BLOGI(sc, "RX RCQ CHAIN fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
19047 (uintmax_t)fp->rcq_dma.paddr, fp->rcq_dma.vaddr,
19048 (BCM_PAGE_SIZE * RCQ_NUM_PAGES));
19049 BLOGI(sc, "RX SGE CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
19050 (uintmax_t)fp->rx_sge_dma.paddr, fp->rx_sge_dma.vaddr,
19051 (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES));
19052 }
19053 }
19054 if(ilt != NULL ) {
19055 ilt_cli = &ilt->clients[1];
19056 if(ilt->lines != NULL) {
19057 for (i = ilt_cli->start; i <= ilt_cli->end; i++) {
19058 BLOGI(sc, "ECORE_ILT paddr %#jx vaddr %p size 0x%x\n",
19059 (uintmax_t)(((struct bxe_dma *)((&ilt->lines[i])->page))->paddr),
19060 ((struct bxe_dma *)((&ilt->lines[i])->page))->vaddr, BCM_PAGE_SIZE);
19061 }
19062 }
19063 }
19064
19065
19066 cmd_offset = DMAE_REG_CMD_MEM;
19067 for (i = 0; i < 224; i++) {
19068 reg_addr = (cmd_offset +(i * 4));
19069 reg_val = REG_RD(sc, reg_addr);
19070 BLOGI(sc, "DMAE_REG_CMD_MEM i=%d reg_addr 0x%x reg_val 0x%08x\n",i,
19071 reg_addr, reg_val);
19072 }
19073 }
19074
19075 BLOGI(sc, "Collection of grcdump done\n");
19076 sc->grcdump_done = 1;
19077 return(rval);
19078 }
19079
19080 static int
bxe_add_cdev(struct bxe_softc * sc)19081 bxe_add_cdev(struct bxe_softc *sc)
19082 {
19083 sc->eeprom = malloc(BXE_EEPROM_MAX_DATA_LEN, M_DEVBUF, M_NOWAIT);
19084
19085 if (sc->eeprom == NULL) {
19086 BLOGW(sc, "Unable to alloc for eeprom size buffer\n");
19087 return (-1);
19088 }
19089
19090 sc->ioctl_dev = make_dev(&bxe_cdevsw,
19091 if_getdunit(sc->ifp),
19092 UID_ROOT,
19093 GID_WHEEL,
19094 0600,
19095 "%s",
19096 if_name(sc->ifp));
19097
19098 if (sc->ioctl_dev == NULL) {
19099 free(sc->eeprom, M_DEVBUF);
19100 sc->eeprom = NULL;
19101 return (-1);
19102 }
19103
19104 sc->ioctl_dev->si_drv1 = sc;
19105
19106 return (0);
19107 }
19108
19109 static void
bxe_del_cdev(struct bxe_softc * sc)19110 bxe_del_cdev(struct bxe_softc *sc)
19111 {
19112 if (sc->ioctl_dev != NULL)
19113 destroy_dev(sc->ioctl_dev);
19114
19115 if (sc->eeprom != NULL) {
19116 free(sc->eeprom, M_DEVBUF);
19117 sc->eeprom = NULL;
19118 }
19119 sc->ioctl_dev = NULL;
19120
19121 return;
19122 }
19123
bxe_is_nvram_accessible(struct bxe_softc * sc)19124 static bool bxe_is_nvram_accessible(struct bxe_softc *sc)
19125 {
19126
19127 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0)
19128 return FALSE;
19129
19130 return TRUE;
19131 }
19132
19133
19134 static int
bxe_wr_eeprom(struct bxe_softc * sc,void * data,uint32_t offset,uint32_t len)19135 bxe_wr_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
19136 {
19137 int rval = 0;
19138
19139 if(!bxe_is_nvram_accessible(sc)) {
19140 BLOGW(sc, "Cannot access eeprom when interface is down\n");
19141 return (-EAGAIN);
19142 }
19143 rval = bxe_nvram_write(sc, offset, (uint8_t *)data, len);
19144
19145
19146 return (rval);
19147 }
19148
19149 static int
bxe_rd_eeprom(struct bxe_softc * sc,void * data,uint32_t offset,uint32_t len)19150 bxe_rd_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
19151 {
19152 int rval = 0;
19153
19154 if(!bxe_is_nvram_accessible(sc)) {
19155 BLOGW(sc, "Cannot access eeprom when interface is down\n");
19156 return (-EAGAIN);
19157 }
19158 rval = bxe_nvram_read(sc, offset, (uint8_t *)data, len);
19159
19160 return (rval);
19161 }
19162
19163 static int
bxe_eeprom_rd_wr(struct bxe_softc * sc,bxe_eeprom_t * eeprom)19164 bxe_eeprom_rd_wr(struct bxe_softc *sc, bxe_eeprom_t *eeprom)
19165 {
19166 int rval = 0;
19167
19168 switch (eeprom->eeprom_cmd) {
19169
19170 case BXE_EEPROM_CMD_SET_EEPROM:
19171
19172 rval = copyin(eeprom->eeprom_data, sc->eeprom,
19173 eeprom->eeprom_data_len);
19174
19175 if (rval)
19176 break;
19177
19178 rval = bxe_wr_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
19179 eeprom->eeprom_data_len);
19180 break;
19181
19182 case BXE_EEPROM_CMD_GET_EEPROM:
19183
19184 rval = bxe_rd_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
19185 eeprom->eeprom_data_len);
19186
19187 if (rval) {
19188 break;
19189 }
19190
19191 rval = copyout(sc->eeprom, eeprom->eeprom_data,
19192 eeprom->eeprom_data_len);
19193 break;
19194
19195 default:
19196 rval = EINVAL;
19197 break;
19198 }
19199
19200 if (rval) {
19201 BLOGW(sc, "ioctl cmd %d failed rval %d\n", eeprom->eeprom_cmd, rval);
19202 }
19203
19204 return (rval);
19205 }
19206
19207 static int
bxe_get_settings(struct bxe_softc * sc,bxe_dev_setting_t * dev_p)19208 bxe_get_settings(struct bxe_softc *sc, bxe_dev_setting_t *dev_p)
19209 {
19210 uint32_t ext_phy_config;
19211 int port = SC_PORT(sc);
19212 int cfg_idx = bxe_get_link_cfg_idx(sc);
19213
19214 dev_p->supported = sc->port.supported[cfg_idx] |
19215 (sc->port.supported[cfg_idx ^ 1] &
19216 (ELINK_SUPPORTED_TP | ELINK_SUPPORTED_FIBRE));
19217 dev_p->advertising = sc->port.advertising[cfg_idx];
19218 if(sc->link_params.phy[bxe_get_cur_phy_idx(sc)].media_type ==
19219 ELINK_ETH_PHY_SFP_1G_FIBER) {
19220 dev_p->supported = ~(ELINK_SUPPORTED_10000baseT_Full);
19221 dev_p->advertising &= ~(ADVERTISED_10000baseT_Full);
19222 }
19223 if ((sc->state == BXE_STATE_OPEN) && sc->link_vars.link_up &&
19224 !(sc->flags & BXE_MF_FUNC_DIS)) {
19225 dev_p->duplex = sc->link_vars.duplex;
19226 if (IS_MF(sc) && !BXE_NOMCP(sc))
19227 dev_p->speed = bxe_get_mf_speed(sc);
19228 else
19229 dev_p->speed = sc->link_vars.line_speed;
19230 } else {
19231 dev_p->duplex = DUPLEX_UNKNOWN;
19232 dev_p->speed = SPEED_UNKNOWN;
19233 }
19234
19235 dev_p->port = bxe_media_detect(sc);
19236
19237 ext_phy_config = SHMEM_RD(sc,
19238 dev_info.port_hw_config[port].external_phy_config);
19239 if((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) ==
19240 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
19241 dev_p->phy_address = sc->port.phy_addr;
19242 else if(((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
19243 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
19244 ((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
19245 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
19246 dev_p->phy_address = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
19247 else
19248 dev_p->phy_address = 0;
19249
19250 if(sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG)
19251 dev_p->autoneg = AUTONEG_ENABLE;
19252 else
19253 dev_p->autoneg = AUTONEG_DISABLE;
19254
19255
19256 return 0;
19257 }
19258
19259 static int
bxe_eioctl(struct cdev * dev,u_long cmd,caddr_t data,int fflag,struct thread * td)19260 bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
19261 struct thread *td)
19262 {
19263 struct bxe_softc *sc;
19264 int rval = 0;
19265 bxe_grcdump_t *dump = NULL;
19266 int grc_dump_size;
19267 bxe_drvinfo_t *drv_infop = NULL;
19268 bxe_dev_setting_t *dev_p;
19269 bxe_dev_setting_t dev_set;
19270 bxe_get_regs_t *reg_p;
19271 bxe_reg_rdw_t *reg_rdw_p;
19272 bxe_pcicfg_rdw_t *cfg_rdw_p;
19273 bxe_perm_mac_addr_t *mac_addr_p;
19274
19275
19276 if ((sc = (struct bxe_softc *)dev->si_drv1) == NULL)
19277 return ENXIO;
19278
19279 dump = (bxe_grcdump_t *)data;
19280
19281 switch(cmd) {
19282
19283 case BXE_GRC_DUMP_SIZE:
19284 dump->pci_func = sc->pcie_func;
19285 dump->grcdump_size =
19286 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
19287 sizeof(struct dump_header);
19288 break;
19289
19290 case BXE_GRC_DUMP:
19291
19292 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
19293 sizeof(struct dump_header);
19294 if ((!sc->trigger_grcdump) || (dump->grcdump == NULL) ||
19295 (dump->grcdump_size < grc_dump_size)) {
19296 rval = EINVAL;
19297 break;
19298 }
19299
19300 if((sc->trigger_grcdump) && (!sc->grcdump_done) &&
19301 (!sc->grcdump_started)) {
19302 rval = bxe_grc_dump(sc);
19303 }
19304
19305 if((!rval) && (sc->grcdump_done) && (sc->grcdump_started) &&
19306 (sc->grc_dump != NULL)) {
19307 dump->grcdump_dwords = grc_dump_size >> 2;
19308 rval = copyout(sc->grc_dump, dump->grcdump, grc_dump_size);
19309 free(sc->grc_dump, M_DEVBUF);
19310 sc->grc_dump = NULL;
19311 sc->grcdump_started = 0;
19312 sc->grcdump_done = 0;
19313 }
19314
19315 break;
19316
19317 case BXE_DRV_INFO:
19318 drv_infop = (bxe_drvinfo_t *)data;
19319 snprintf(drv_infop->drv_name, BXE_DRV_NAME_LENGTH, "%s", "bxe");
19320 snprintf(drv_infop->drv_version, BXE_DRV_VERSION_LENGTH, "v:%s",
19321 BXE_DRIVER_VERSION);
19322 snprintf(drv_infop->mfw_version, BXE_MFW_VERSION_LENGTH, "%s",
19323 sc->devinfo.bc_ver_str);
19324 snprintf(drv_infop->stormfw_version, BXE_STORMFW_VERSION_LENGTH,
19325 "%s", sc->fw_ver_str);
19326 drv_infop->eeprom_dump_len = sc->devinfo.flash_size;
19327 drv_infop->reg_dump_len =
19328 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t))
19329 + sizeof(struct dump_header);
19330 snprintf(drv_infop->bus_info, BXE_BUS_INFO_LENGTH, "%d:%d:%d",
19331 sc->pcie_bus, sc->pcie_device, sc->pcie_func);
19332 break;
19333
19334 case BXE_DEV_SETTING:
19335 dev_p = (bxe_dev_setting_t *)data;
19336 bxe_get_settings(sc, &dev_set);
19337 dev_p->supported = dev_set.supported;
19338 dev_p->advertising = dev_set.advertising;
19339 dev_p->speed = dev_set.speed;
19340 dev_p->duplex = dev_set.duplex;
19341 dev_p->port = dev_set.port;
19342 dev_p->phy_address = dev_set.phy_address;
19343 dev_p->autoneg = dev_set.autoneg;
19344
19345 break;
19346
19347 case BXE_GET_REGS:
19348
19349 reg_p = (bxe_get_regs_t *)data;
19350 grc_dump_size = reg_p->reg_buf_len;
19351
19352 if((!sc->grcdump_done) && (!sc->grcdump_started)) {
19353 bxe_grc_dump(sc);
19354 }
19355 if((sc->grcdump_done) && (sc->grcdump_started) &&
19356 (sc->grc_dump != NULL)) {
19357 rval = copyout(sc->grc_dump, reg_p->reg_buf, grc_dump_size);
19358 free(sc->grc_dump, M_DEVBUF);
19359 sc->grc_dump = NULL;
19360 sc->grcdump_started = 0;
19361 sc->grcdump_done = 0;
19362 }
19363
19364 break;
19365
19366 case BXE_RDW_REG:
19367 reg_rdw_p = (bxe_reg_rdw_t *)data;
19368 if((reg_rdw_p->reg_cmd == BXE_READ_REG_CMD) &&
19369 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19370 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id);
19371
19372 if((reg_rdw_p->reg_cmd == BXE_WRITE_REG_CMD) &&
19373 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19374 REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val);
19375
19376 break;
19377
19378 case BXE_RDW_PCICFG:
19379 cfg_rdw_p = (bxe_pcicfg_rdw_t *)data;
19380 if(cfg_rdw_p->cfg_cmd == BXE_READ_PCICFG) {
19381
19382 cfg_rdw_p->cfg_val = pci_read_config(sc->dev, cfg_rdw_p->cfg_id,
19383 cfg_rdw_p->cfg_width);
19384
19385 } else if(cfg_rdw_p->cfg_cmd == BXE_WRITE_PCICFG) {
19386 pci_write_config(sc->dev, cfg_rdw_p->cfg_id, cfg_rdw_p->cfg_val,
19387 cfg_rdw_p->cfg_width);
19388 } else {
19389 BLOGW(sc, "BXE_RDW_PCICFG ioctl wrong cmd passed\n");
19390 }
19391 break;
19392
19393 case BXE_MAC_ADDR:
19394 mac_addr_p = (bxe_perm_mac_addr_t *)data;
19395 snprintf(mac_addr_p->mac_addr_str, sizeof(sc->mac_addr_str), "%s",
19396 sc->mac_addr_str);
19397 break;
19398
19399 case BXE_EEPROM:
19400 rval = bxe_eeprom_rd_wr(sc, (bxe_eeprom_t *)data);
19401 break;
19402
19403
19404 default:
19405 break;
19406 }
19407
19408 return (rval);
19409 }
19410
19411 #ifdef DEBUGNET
19412 static void
bxe_debugnet_init(if_t ifp,int * nrxr,int * ncl,int * clsize)19413 bxe_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
19414 {
19415 struct bxe_softc *sc;
19416
19417 sc = if_getsoftc(ifp);
19418 BXE_CORE_LOCK(sc);
19419 *nrxr = sc->num_queues;
19420 *ncl = DEBUGNET_MAX_IN_FLIGHT;
19421 *clsize = sc->fp[0].mbuf_alloc_size;
19422 BXE_CORE_UNLOCK(sc);
19423 }
19424
19425 static void
bxe_debugnet_event(if_t ifp __unused,enum debugnet_ev event __unused)19426 bxe_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
19427 {
19428 }
19429
19430 static int
bxe_debugnet_transmit(if_t ifp,struct mbuf * m)19431 bxe_debugnet_transmit(if_t ifp, struct mbuf *m)
19432 {
19433 struct bxe_softc *sc;
19434 int error;
19435
19436 sc = if_getsoftc(ifp);
19437 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
19438 IFF_DRV_RUNNING || !sc->link_vars.link_up)
19439 return (ENOENT);
19440
19441 error = bxe_tx_encap(&sc->fp[0], &m);
19442 if (error != 0 && m != NULL)
19443 m_freem(m);
19444 return (error);
19445 }
19446
19447 static int
bxe_debugnet_poll(if_t ifp,int count)19448 bxe_debugnet_poll(if_t ifp, int count)
19449 {
19450 struct bxe_softc *sc;
19451 int i;
19452
19453 sc = if_getsoftc(ifp);
19454 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
19455 !sc->link_vars.link_up)
19456 return (ENOENT);
19457
19458 for (i = 0; i < sc->num_queues; i++)
19459 (void)bxe_rxeof(sc, &sc->fp[i]);
19460 (void)bxe_txeof(sc, &sc->fp[0]);
19461 return (0);
19462 }
19463 #endif /* DEBUGNET */
19464