xref: /illumos-gate/usr/src/uts/common/io/chxge/com/espi.c (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
24  */
25 
26 #include "common.h"
27 #include "regs.h"
28 #include "espi.h"
29 
30 struct peespi {
31 	adapter_t *adapter;
32 	struct espi_intr_counts intr_cnt;
33 	u32 misc_ctrl;
34 	SPINLOCK lock;
35 };
36 
37 #define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \
38 			F_RAMPARITYERR | F_DIP2PARITYERR)
39 #define MON_MASK  (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \
40 			| F_MONITORED_INTERFACE)
41 
42 #define TRICN_CNFG 14
43 #define TRICN_CMD_READ  0x11
44 #define TRICN_CMD_WRITE 0x21
45 #define TRICN_CMD_ATTEMPTS 10
46 
tricn_write(adapter_t * adapter,int bundle_addr,int module_addr,int ch_addr,int reg_offset,u32 wr_data)47 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
48 		       int ch_addr, int reg_offset, u32 wr_data)
49 {
50 	int busy;
51 
52 	t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) |
53 		       V_REGISTER_OFFSET(reg_offset) |
54 		       V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
55 		       V_BUNDLE_ADDR(bundle_addr) |
56 		       V_SPI4_COMMAND(TRICN_CMD_WRITE));
57 	t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
58 
59 	busy = t1_wait_op_done(adapter, A_ESPI_GOSTAT, F_ESPI_CMD_BUSY, 0,
60 			TRICN_CMD_ATTEMPTS, 0);
61 
62 	if (busy)
63 		CH_ERR("%s: TRICN write timed out\n", adapter_name(adapter));
64 
65 	return busy;
66 }
67 
68 #if 0
69 static int tricn_read(adapter_t *adapter, int bundle_addr, int module_addr,
70 		      int ch_addr, int reg_offset, u8 *rd_data)
71 {
72 	int busy, attempts = TRICN_CMD_ATTEMPTS;
73 	u32 status;
74 
75 	t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
76 		       V_REGISTER_OFFSET(reg_offset) |
77 		       V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
78 		       V_BUNDLE_ADDR(bundle_addr) |
79 		       V_SPI4_COMMAND(TRICN_CMD_READ));
80 	t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
81 
82 	do {
83 		status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);
84 		busy = status & F_ESPI_CMD_BUSY;
85 	} while (busy && --attempts);
86 
87 	if (busy)
88 		CH_ERR("%s: TRICN read timed out\n", adapter_name(adapter));
89 	else
90 		*rd_data = G_READ_DATA(status);
91 	return busy;
92 }
93 #endif
94 
tricn_init(adapter_t * adapter)95 static int tricn_init(adapter_t *adapter)
96 {
97 	int i, sme = 1;
98 
99 	if (!(t1_read_reg_4(adapter, A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
100 		CH_ERR("%s: ESPI clock not ready\n", adapter_name(adapter));
101 		return (-1);
102 	 }
103 
104 	t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST);
105 
106 	if (sme) {
107 		(void) tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
108 		(void) tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
109 		(void) tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
110 	}
111 	for (i=1; i<= 8; i++) (void) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
112 	for (i=1; i<= 2; i++) (void) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
113 	for (i=1; i<= 3; i++) (void) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
114 	(void) tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
115 	(void) tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
116 	(void) tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
117 	(void) tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
118 	(void) tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
119 
120 	t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST);
121 
122 	return 0;
123 }
124 
t1_espi_intr_enable(struct peespi * espi)125 void t1_espi_intr_enable(struct peespi *espi)
126 {
127 	u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
128 
129 	/*
130 	 * Cannot enable ESPI interrupts on T1B because HW asserts the
131 	 * interrupt incorrectly, namely the driver gets ESPI interrupts
132 	 * but no data is actually dropped (can verify this reading the ESPI
133 	 * drop registers).  Also, once the ESPI interrupt is asserted it
134 	 * cannot be cleared (HW bug).
135 	 */
136 	enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
137 	t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable);
138 	t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI);
139 }
140 
t1_espi_intr_clear(struct peespi * espi)141 void t1_espi_intr_clear(struct peespi *espi)
142 {
143 	(void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
144 	t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff);
145 	t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI);
146 }
147 
t1_espi_intr_disable(struct peespi * espi)148 void t1_espi_intr_disable(struct peespi *espi)
149 {
150 	u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
151 
152 	t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, 0);
153 	t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI);
154 }
155 
t1_espi_intr_handler(struct peespi * espi)156 int t1_espi_intr_handler(struct peespi *espi)
157 {
158 	u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS);
159 
160 	if (status & F_DIP4ERR)
161 		espi->intr_cnt.DIP4_err++;
162 	if (status & F_RXDROP)
163 		espi->intr_cnt.rx_drops++;
164 	if (status & F_TXDROP)
165 		espi->intr_cnt.tx_drops++;
166 	if (status & F_RXOVERFLOW)
167 		espi->intr_cnt.rx_ovflw++;
168 	if (status & F_RAMPARITYERR)
169 		espi->intr_cnt.parity_err++;
170 	if (status & F_DIP2PARITYERR) {
171 		espi->intr_cnt.DIP2_parity_err++;
172 		(void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
173 	 }
174 
175 	/*
176 	 * For T1B we need to write 1 to clear ESPI interrupts.  For T2+ we
177 	 * write the status as is.
178 	 */
179 	if (status && t1_is_T1B(espi->adapter))
180 		status = 1;
181 	t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, status);
182 	return 0;
183 }
184 
t1_espi_get_intr_counts(struct peespi * espi)185 const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
186 {
187 	return &espi->intr_cnt;
188 }
189 
espi_setup_for_pm3393(adapter_t * adapter)190 static void espi_setup_for_pm3393(adapter_t *adapter)
191 {
192 	u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
193 
194 	t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
195 	t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
196 	t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
197 	t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
198 	t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
199 	t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
200 	t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
201 	t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
202 	t1_write_reg_4(adapter, A_PORT_CONFIG,
203 		       V_RX_NPORTS(1) | V_TX_NPORTS(1));
204 }
205 
espi_setup_for_vsc7321(adapter_t * adapter)206 static void espi_setup_for_vsc7321(adapter_t *adapter)
207 {
208 #ifdef CONFIG_CHELSIO_T1_COUGAR
209 	u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
210 
211         t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
212         t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
213         t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
214 	t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
215         t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
216         t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
217         t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
218  	t1_write_reg_4(adapter, A_PORT_CONFIG,
219 		       V_RX_NPORTS(1) | V_TX_NPORTS(1));
220 #else
221         t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
222         t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f401f4);
223         t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
224 	t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, 0xa00);
225 	t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x1ff);
226 	t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
227         t1_write_reg_4(adapter, A_PORT_CONFIG,
228                        V_RX_NPORTS(4) | V_TX_NPORTS(4));
229 #endif
230 	t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
231 }
232 
233 /*
234  * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug.
235  */
espi_setup_for_ixf1010(adapter_t * adapter,int nports)236 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
237 {
238 	t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
239 	if (nports == 4) {
240 		if (is_T2(adapter)) {
241 			t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
242 				0xf00);
243 			t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
244 				0x3c0);
245 		} else {
246 			t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
247 				0x7ff);
248 			t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
249 				0x1ff);
250 		}
251 	} else {
252 		t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
253 			       0x1fff);
254 		t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
255 			       0x7ff);
256 	}
257 	t1_write_reg_4(adapter, A_PORT_CONFIG,
258 		       V_RX_NPORTS(nports) | V_TX_NPORTS(nports));
259 }
260 
t1_espi_init(struct peespi * espi,int mac_type,int nports)261 int t1_espi_init(struct peespi *espi, int mac_type, int nports)
262 {
263 	u32 status_enable_extra = 0;
264 	adapter_t *adapter = espi->adapter;
265 
266 	/* Disable ESPI training.  MACs that can handle it enable it below. */
267 	t1_write_reg_4(adapter, A_ESPI_TRAIN, 0);
268 
269 	if (is_T2(adapter)) {
270 		t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
271 			       V_OUT_OF_SYNC_COUNT(4) |
272 			       V_DIP2_PARITY_ERR_THRES(3) | V_DIP4_THRES(1));
273         	t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2,
274 			nports == 4 ? 0x200040 : 0x1000080);
275 	} else
276 		t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2, 0x800100);
277 
278 	if (mac_type == CHBT_MAC_PM3393)
279 		espi_setup_for_pm3393(adapter);
280 	else if (mac_type == CHBT_MAC_VSC7321)
281 		espi_setup_for_vsc7321(adapter);
282 	else if (mac_type == CHBT_MAC_IXF1010) {
283 		status_enable_extra = F_INTEL1010MODE;
284 		espi_setup_for_ixf1010(adapter, nports);
285 	} else
286 		return -1;
287 
288 	t1_write_reg_4(adapter, A_ESPI_FIFO_STATUS_ENABLE,
289 		       status_enable_extra | F_RXSTATUSENABLE);
290 
291 	if (is_T2(adapter)) {
292 		(void) tricn_init(adapter);
293 		/*
294 		 * Always position the control at the 1st port egress IN
295 		 * (sop,eop) counter to reduce PIOs for T/N210 workaround.
296 		 */
297 		espi->misc_ctrl = t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL);
298 		espi->misc_ctrl &= ~MON_MASK;
299 		espi->misc_ctrl |= F_MONITORED_DIRECTION;
300 		if (adapter->params.nports == 1)
301 			espi->misc_ctrl |= F_MONITORED_INTERFACE;
302 		t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
303 		SPIN_LOCK_INIT(espi->lock);
304 	}
305 
306 	return 0;
307 }
308 
t1_espi_destroy(struct peespi * espi)309 void t1_espi_destroy(struct peespi *espi)
310 {
311 	if (is_T2(espi->adapter)) {
312 		SPIN_LOCK_DESTROY(espi->lock);
313 	}
314 	t1_os_free((void *)espi, sizeof(*espi));
315 }
316 
t1_espi_create(adapter_t * adapter)317 struct peespi *t1_espi_create(adapter_t *adapter)
318 {
319 	struct peespi *espi = t1_os_malloc_wait_zero(sizeof(*espi));
320 
321 	if (espi)
322 		espi->adapter = adapter;
323 	return espi;
324 }
325 
t1_espi_set_misc_ctrl(adapter_t * adapter,u32 val)326 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
327 {
328 	struct peespi *espi = adapter->espi;
329 
330 	if (!is_T2(adapter))
331 		return;
332 	SPIN_LOCK(espi->lock);
333 	espi->misc_ctrl = (val & ~MON_MASK) |
334 		(espi->misc_ctrl & MON_MASK);
335 	t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
336 	SPIN_UNLOCK(espi->lock);
337 }
338 
t1_espi_get_mon(adapter_t * adapter,u32 addr,u8 wait)339 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
340 {
341 	struct peespi *espi = adapter->espi;
342 	u32 sel;
343 
344 	if (!is_T2(adapter)) return 0;
345 	sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
346 	if (!wait) {
347 		if (!SPIN_TRYLOCK(espi->lock))
348 			return 0;
349         }
350 	else
351 		SPIN_LOCK(espi->lock);
352 	if ((sel != (espi->misc_ctrl & MON_MASK))) {
353 		t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
354 			((espi->misc_ctrl & ~MON_MASK) | sel));
355 		sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
356 		t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
357 			espi->misc_ctrl);
358         }
359 	else
360 		sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
361 	SPIN_UNLOCK(espi->lock);
362 	return sel;
363 }
364 
365 /*
366  * This function is for T204 only.
367  * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in
368  * one shot, since there is no per port counter on the out side.
369  */
370 int
t1_espi_get_mon_t204(adapter_t * adapter,u32 * valp,u8 wait)371 t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
372 {
373 	struct peespi *espi = adapter->espi;
374 	u8 i, nport = (u8)adapter->params.nports;
375 
376 	if (!wait) {
377 		if (!SPIN_TRYLOCK(espi->lock))
378 			return -1;
379 	} else
380 		SPIN_LOCK(espi->lock);
381 	if ((espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION ) {
382 		espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) |
383 			F_MONITORED_DIRECTION;
384 		t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
385 	}
386 	for (i = 0 ; i < nport; i++, valp++) {
387 		if (i) {
388 			t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
389 			(espi->misc_ctrl | V_MONITORED_PORT_NUM(i)));
390 		}
391 		*valp = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
392 	}
393 
394 	t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
395 
396 	SPIN_UNLOCK(espi->lock);
397 	return 0;
398 }
399