1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This contains the functions to handle the descriptors for DesignWare databook
4 * 4.xx.
5 *
6 * Copyright (C) 2015 STMicroelectronics Ltd
7 *
8 * Author: Alexandre Torgue <alexandre.torgue@st.com>
9 */
10
11 #include <linux/stmmac.h>
12 #include "common.h"
13 #include "dwmac4.h"
14 #include "dwmac4_descs.h"
15
dwmac4_wrback_get_tx_status(struct stmmac_extra_stats * x,struct dma_desc * p,void __iomem * ioaddr)16 static int dwmac4_wrback_get_tx_status(struct stmmac_extra_stats *x,
17 struct dma_desc *p,
18 void __iomem *ioaddr)
19 {
20 u32 tdes3 = le32_to_cpu(p->des3);
21 int ret = tx_done;
22
23 /* Get tx owner first */
24 if (unlikely(tdes3 & TDES3_OWN))
25 return tx_dma_own;
26
27 /* Verify tx error by looking at the last segment. */
28 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
29 return tx_not_ls;
30
31 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
32 ret = tx_err;
33
34 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
35 x->tx_jabber++;
36 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
37 x->tx_frame_flushed++;
38 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
39 x->tx_losscarrier++;
40 }
41 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
42 x->tx_carrier++;
43 }
44 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
45 (tdes3 & TDES3_EXCESSIVE_COLLISION)))
46 x->tx_collision +=
47 FIELD_GET(TDES3_COLLISION_COUNT_MASK, tdes3);
48
49 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
50 x->tx_deferred++;
51
52 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) {
53 x->tx_underflow++;
54 ret |= tx_err_bump_tc;
55 }
56
57 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
58 x->tx_ip_header_error++;
59
60 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
61 x->tx_payload_error++;
62 }
63
64 if (unlikely(tdes3 & TDES3_DEFERRED))
65 x->tx_deferred++;
66
67 return ret;
68 }
69
dwmac4_wrback_get_rx_status(struct stmmac_extra_stats * x,struct dma_desc * p)70 static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
71 struct dma_desc *p)
72 {
73 u32 rdes1 = le32_to_cpu(p->des1);
74 u32 rdes2 = le32_to_cpu(p->des2);
75 u32 rdes3 = le32_to_cpu(p->des3);
76 int message_type;
77 int ret = good_frame;
78
79 if (unlikely(rdes3 & RDES3_OWN))
80 return dma_own;
81
82 if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
83 return discard_frame;
84 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
85 return rx_not_ls;
86
87 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
88 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
89 x->rx_length++;
90 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
91 x->rx_gmac_overflow++;
92
93 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
94 x->rx_watchdog++;
95
96 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
97 x->rx_mii++;
98
99 if (unlikely(rdes3 & RDES3_CRC_ERROR))
100 x->rx_crc_errors++;
101
102 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
103 x->dribbling_bit++;
104
105 ret = discard_frame;
106 }
107
108 message_type = FIELD_GET(RDES1_PTP_MSG_TYPE_MASK, rdes1);
109
110 if (rdes1 & RDES1_IP_HDR_ERROR) {
111 x->ip_hdr_err++;
112 ret |= csum_none;
113 }
114 if (rdes1 & RDES1_IP_CSUM_BYPASSED)
115 x->ip_csum_bypassed++;
116 if (rdes1 & RDES1_IPV4_HEADER)
117 x->ipv4_pkt_rcvd++;
118 if (rdes1 & RDES1_IPV6_HEADER)
119 x->ipv6_pkt_rcvd++;
120 if (rdes1 & RDES1_IP_PAYLOAD_ERROR) {
121 x->ip_payload_err++;
122 ret |= csum_none;
123 }
124
125 if (message_type == RDES_EXT_NO_PTP)
126 x->no_ptp_rx_msg_type_ext++;
127 else if (message_type == RDES_EXT_SYNC)
128 x->ptp_rx_msg_type_sync++;
129 else if (message_type == RDES_EXT_FOLLOW_UP)
130 x->ptp_rx_msg_type_follow_up++;
131 else if (message_type == RDES_EXT_DELAY_REQ)
132 x->ptp_rx_msg_type_delay_req++;
133 else if (message_type == RDES_EXT_DELAY_RESP)
134 x->ptp_rx_msg_type_delay_resp++;
135 else if (message_type == RDES_EXT_PDELAY_REQ)
136 x->ptp_rx_msg_type_pdelay_req++;
137 else if (message_type == RDES_EXT_PDELAY_RESP)
138 x->ptp_rx_msg_type_pdelay_resp++;
139 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
140 x->ptp_rx_msg_type_pdelay_follow_up++;
141 else if (message_type == RDES_PTP_ANNOUNCE)
142 x->ptp_rx_msg_type_announce++;
143 else if (message_type == RDES_PTP_MANAGEMENT)
144 x->ptp_rx_msg_type_management++;
145 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
146 x->ptp_rx_msg_pkt_reserved_type++;
147
148 if (rdes1 & RDES1_PTP_PACKET_TYPE)
149 x->ptp_frame_type++;
150 if (rdes1 & RDES1_PTP_VER)
151 x->ptp_ver++;
152 if (rdes1 & RDES1_TIMESTAMP_DROPPED)
153 x->timestamp_dropped++;
154
155 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
156 x->sa_rx_filter_fail++;
157 ret = discard_frame;
158 }
159 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
160 x->da_rx_filter_fail++;
161 ret = discard_frame;
162 }
163
164 if (rdes2 & RDES2_L3_FILTER_MATCH)
165 x->l3_filter_match++;
166 if (rdes2 & RDES2_L4_FILTER_MATCH)
167 x->l4_filter_match++;
168 if (rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
169 x->l3_l4_filter_no_match++;
170
171 return ret;
172 }
173
dwmac4_set_tx_owner(struct dma_desc * p)174 static void dwmac4_set_tx_owner(struct dma_desc *p)
175 {
176 p->des3 |= cpu_to_le32(TDES3_OWN);
177 }
178
dwmac4_set_rx_owner(struct dma_desc * p,int disable_rx_ic)179 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
180 {
181 u32 flags = (RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
182
183 if (!disable_rx_ic)
184 flags |= RDES3_INT_ON_COMPLETION_EN;
185
186 p->des3 |= cpu_to_le32(flags);
187 }
188
dwmac4_wrback_get_rx_vlan_tci(struct dma_desc * p)189 static u16 dwmac4_wrback_get_rx_vlan_tci(struct dma_desc *p)
190 {
191 return (le32_to_cpu(p->des0) & RDES0_VLAN_TAG_MASK);
192 }
193
dwmac4_wrback_get_rx_vlan_valid(struct dma_desc * p)194 static bool dwmac4_wrback_get_rx_vlan_valid(struct dma_desc *p)
195 {
196 return ((le32_to_cpu(p->des3) & RDES3_LAST_DESCRIPTOR) &&
197 (le32_to_cpu(p->des3) & RDES3_RDES0_VALID));
198 }
199
dwmac4_wrback_get_rx_frame_len(struct dma_desc * p,int rx_coe)200 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
201 {
202 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
203 }
204
dwmac4_rd_enable_tx_timestamp(struct dma_desc * p)205 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
206 {
207 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
208 }
209
dwmac4_wrback_get_tx_timestamp_status(struct dma_desc * p)210 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
211 {
212 /* Context type from W/B descriptor must be zero */
213 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
214 return 0;
215
216 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
217 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
218 return 1;
219
220 return 0;
221 }
222
dwmac4_get_timestamp(void * desc,u32 ats,u64 * ts)223 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
224 {
225 struct dma_desc *p = (struct dma_desc *)desc;
226 u64 ns;
227
228 ns = le32_to_cpu(p->des0);
229 /* convert high/sec time stamp value to nanosecond */
230 ns += le32_to_cpu(p->des1) * 1000000000ULL;
231
232 *ts = ns;
233 }
234
dwmac4_rx_check_timestamp(void * desc)235 static int dwmac4_rx_check_timestamp(void *desc)
236 {
237 struct dma_desc *p = (struct dma_desc *)desc;
238 u32 rdes0 = le32_to_cpu(p->des0);
239 u32 rdes1 = le32_to_cpu(p->des1);
240 u32 rdes3 = le32_to_cpu(p->des3);
241 bool own, ctxt;
242 int ret = 1;
243
244 own = rdes3 & RDES3_OWN;
245 ctxt = rdes3 & RDES3_CONTEXT_DESCRIPTOR;
246
247 if (likely(!own && ctxt)) {
248 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
249 /* Corrupted value */
250 ret = -EINVAL;
251 else
252 /* A valid Timestamp is ready to be read */
253 ret = 0;
254 }
255
256 /* Timestamp not ready */
257 return ret;
258 }
259
dwmac4_wrback_get_rx_timestamp_status(void * desc,void * next_desc,u32 ats)260 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
261 u32 ats)
262 {
263 struct dma_desc *p = (struct dma_desc *)desc;
264 int ret = -EINVAL;
265
266 /* Get the status from normal w/b descriptor */
267 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
268 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
269 int i = 0;
270
271 /* Check if timestamp is OK from context descriptor */
272 do {
273 ret = dwmac4_rx_check_timestamp(next_desc);
274 if (ret < 0)
275 goto exit;
276 i++;
277
278 } while ((ret == 1) && (i < 10));
279
280 if (i == 10)
281 ret = -EBUSY;
282 }
283 }
284 exit:
285 if (likely(ret == 0))
286 return 1;
287
288 return 0;
289 }
290
dwmac4_rd_init_rx_desc(struct dma_desc * p,int disable_rx_ic,u8 descriptor_mode,int end,int bfsize)291 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
292 u8 descriptor_mode, int end, int bfsize)
293 {
294 dwmac4_set_rx_owner(p, disable_rx_ic);
295 }
296
dwmac4_rd_init_tx_desc(struct dma_desc * p,u8 descriptor_mode,int end)297 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, u8 descriptor_mode,
298 int end)
299 {
300 p->des0 = 0;
301 p->des1 = 0;
302 p->des2 = 0;
303 p->des3 = 0;
304 }
305
dwmac4_rd_prepare_tx_desc(struct dma_desc * p,int is_fs,int len,bool csum_flag,u8 descriptor_mode,bool tx_own,bool ls,unsigned int tot_pkt_len)306 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
307 bool csum_flag, u8 descriptor_mode,
308 bool tx_own, bool ls,
309 unsigned int tot_pkt_len)
310 {
311 u32 tdes3 = le32_to_cpu(p->des3);
312
313 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
314
315 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
316 if (is_fs)
317 tdes3 |= TDES3_FIRST_DESCRIPTOR;
318 else
319 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
320
321 tdes3 = u32_replace_bits(tdes3, csum_flag ? TX_CIC_FULL : 0,
322 TDES3_CHECKSUM_INSERTION_MASK);
323
324 if (ls)
325 tdes3 |= TDES3_LAST_DESCRIPTOR;
326 else
327 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
328
329 /* Finally set the OWN bit. Later the DMA will start! */
330 if (tx_own)
331 tdes3 |= TDES3_OWN;
332
333 if (is_fs && tx_own)
334 /* When the own bit, for the first frame, has to be set, all
335 * descriptors for the same frame has to be set before, to
336 * avoid race condition.
337 */
338 dma_wmb();
339
340 p->des3 = cpu_to_le32(tdes3);
341 }
342
dwmac4_rd_prepare_tso_tx_desc(struct dma_desc * p,int is_fs,int len1,int len2,bool tx_own,bool ls,unsigned int tcphdrlen,unsigned int tcppayloadlen)343 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
344 int len1, int len2, bool tx_own,
345 bool ls, unsigned int tcphdrlen,
346 unsigned int tcppayloadlen)
347 {
348 u32 tdes3 = le32_to_cpu(p->des3);
349
350 if (len1)
351 p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER1_SIZE_MASK,
352 len1));
353
354 if (len2)
355 p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER2_SIZE_MASK,
356 len2));
357
358 if (is_fs) {
359 tdes3 |= TDES3_FIRST_DESCRIPTOR |
360 TDES3_TCP_SEGMENTATION_ENABLE |
361 FIELD_PREP(TDES3_SLOT_NUMBER_MASK, tcphdrlen) |
362 FIELD_PREP(TDES3_TCP_PKT_PAYLOAD_MASK, tcppayloadlen);
363 } else {
364 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
365 }
366
367 if (ls)
368 tdes3 |= TDES3_LAST_DESCRIPTOR;
369 else
370 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
371
372 /* Finally set the OWN bit. Later the DMA will start! */
373 if (tx_own)
374 tdes3 |= TDES3_OWN;
375
376 if (is_fs && tx_own)
377 /* When the own bit, for the first frame, has to be set, all
378 * descriptors for the same frame has to be set before, to
379 * avoid race condition.
380 */
381 dma_wmb();
382
383 p->des3 = cpu_to_le32(tdes3);
384 }
385
dwmac4_release_tx_desc(struct dma_desc * p,u8 descriptor_mode)386 static void dwmac4_release_tx_desc(struct dma_desc *p, u8 descriptor_mode)
387 {
388 p->des0 = 0;
389 p->des1 = 0;
390 p->des2 = 0;
391 p->des3 = 0;
392 }
393
dwmac4_rd_set_tx_ic(struct dma_desc * p)394 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
395 {
396 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
397 }
398
dwmac4_display_ring(void * head,unsigned int size,bool rx,dma_addr_t dma_rx_phy,unsigned int desc_size)399 static void dwmac4_display_ring(void *head, unsigned int size, bool rx,
400 dma_addr_t dma_rx_phy, unsigned int desc_size)
401 {
402 dma_addr_t dma_addr;
403 int i;
404
405 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
406
407 if (desc_size == sizeof(struct dma_desc)) {
408 struct dma_desc *p = (struct dma_desc *)head;
409
410 for (i = 0; i < size; i++) {
411 dma_addr = dma_rx_phy + i * sizeof(*p);
412 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
413 i, &dma_addr,
414 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
415 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
416 p++;
417 }
418 } else if (desc_size == sizeof(struct dma_extended_desc)) {
419 struct dma_extended_desc *extp = (struct dma_extended_desc *)head;
420
421 for (i = 0; i < size; i++) {
422 dma_addr = dma_rx_phy + i * sizeof(*extp);
423 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
424 i, &dma_addr,
425 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),
426 le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),
427 le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),
428 le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));
429 extp++;
430 }
431 } else if (desc_size == sizeof(struct dma_edesc)) {
432 struct dma_edesc *ep = dma_desc_to_edesc(head);
433
434 for (i = 0; i < size; i++) {
435 dma_addr = dma_rx_phy + i * sizeof(*ep);
436 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
437 i, &dma_addr,
438 le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),
439 le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),
440 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),
441 le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));
442 ep++;
443 }
444 } else {
445 pr_err("unsupported descriptor!");
446 }
447 }
448
dwmac4_set_mss_ctxt(struct dma_desc * p,unsigned int mss)449 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
450 {
451 p->des0 = 0;
452 p->des1 = 0;
453 p->des2 = cpu_to_le32(mss);
454 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
455 }
456
dwmac4_set_addr(struct dma_desc * p,dma_addr_t addr)457 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
458 {
459 p->des0 = cpu_to_le32(lower_32_bits(addr));
460 p->des1 = cpu_to_le32(upper_32_bits(addr));
461 }
462
dwmac4_clear(struct dma_desc * p)463 static void dwmac4_clear(struct dma_desc *p)
464 {
465 p->des0 = 0;
466 p->des1 = 0;
467 p->des2 = 0;
468 p->des3 = 0;
469 }
470
dwmac4_set_sarc(struct dma_desc * p,u32 sarc_type)471 static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
472 {
473 p->des3 |= cpu_to_le32(FIELD_PREP(TDES3_SA_INSERT_CTRL_MASK,
474 sarc_type));
475 }
476
set_16kib_bfsize(int len)477 static int set_16kib_bfsize(int len)
478 {
479 int ret = 0;
480
481 if (unlikely(len > BUF_SIZE_8KiB))
482 ret = BUF_SIZE_16KiB;
483 return ret;
484 }
485
dwmac4_set_vlan_tag(struct dma_desc * p,u16 tag,u16 inner_tag,u32 inner_type)486 static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
487 u32 inner_type)
488 {
489 p->des0 = 0;
490 p->des1 = 0;
491 p->des2 = 0;
492 p->des3 = 0;
493
494 /* Inner VLAN */
495 if (inner_type) {
496 p->des2 = cpu_to_le32(FIELD_PREP(TDES2_IVT_MASK, inner_tag));
497 p->des3 = cpu_to_le32(FIELD_PREP(TDES3_IVTIR_MASK, inner_type) |
498 TDES3_IVLTV);
499 }
500
501 /* Outer VLAN */
502 p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
503 p->des3 |= cpu_to_le32(TDES3_VLTV);
504
505 p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
506 }
507
dwmac4_set_vlan(struct dma_desc * p,u32 type)508 static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
509 {
510 p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_VLAN_TAG_MASK, type));
511 }
512
dwmac4_get_rx_header_len(struct dma_desc * p,unsigned int * len)513 static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
514 {
515 *len = le32_to_cpu(p->des2) & RDES2_HL;
516 }
517
dwmac4_set_sec_addr(struct dma_desc * p,dma_addr_t addr,bool buf2_valid)518 static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)
519 {
520 p->des2 = cpu_to_le32(lower_32_bits(addr));
521 p->des3 = cpu_to_le32(upper_32_bits(addr));
522
523 if (buf2_valid)
524 p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);
525 else
526 p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);
527 }
528
dwmac4_set_tbs(struct dma_edesc * p,u32 sec,u32 nsec)529 static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
530 {
531 p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
532 p->des5 = cpu_to_le32(nsec & TDES5_LT);
533 p->des6 = 0;
534 p->des7 = 0;
535 }
536
537 const struct stmmac_desc_ops dwmac4_desc_ops = {
538 .tx_status = dwmac4_wrback_get_tx_status,
539 .rx_status = dwmac4_wrback_get_rx_status,
540 .set_tx_owner = dwmac4_set_tx_owner,
541 .set_rx_owner = dwmac4_set_rx_owner,
542 .get_rx_vlan_tci = dwmac4_wrback_get_rx_vlan_tci,
543 .get_rx_vlan_valid = dwmac4_wrback_get_rx_vlan_valid,
544 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
545 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
546 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
547 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
548 .get_timestamp = dwmac4_get_timestamp,
549 .set_tx_ic = dwmac4_rd_set_tx_ic,
550 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
551 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
552 .release_tx_desc = dwmac4_release_tx_desc,
553 .init_rx_desc = dwmac4_rd_init_rx_desc,
554 .init_tx_desc = dwmac4_rd_init_tx_desc,
555 .display_ring = dwmac4_display_ring,
556 .set_mss = dwmac4_set_mss_ctxt,
557 .set_addr = dwmac4_set_addr,
558 .clear = dwmac4_clear,
559 .set_sarc = dwmac4_set_sarc,
560 .set_vlan_tag = dwmac4_set_vlan_tag,
561 .set_vlan = dwmac4_set_vlan,
562 .get_rx_header_len = dwmac4_get_rx_header_len,
563 .set_sec_addr = dwmac4_set_sec_addr,
564 .set_tbs = dwmac4_set_tbs,
565 };
566
567 const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
568 .set_16kib_bfsize = set_16kib_bfsize,
569 };
570