1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This contains the functions to handle the descriptors for DesignWare databook
4 * 4.xx.
5 *
6 * Copyright (C) 2015 STMicroelectronics Ltd
7 *
8 * Author: Alexandre Torgue <alexandre.torgue@st.com>
9 */
10
11 #include <linux/stmmac.h>
12 #include "common.h"
13 #include "dwmac4.h"
14 #include "dwmac4_descs.h"
15
dwmac4_wrback_get_tx_status(struct stmmac_extra_stats * x,struct dma_desc * p,void __iomem * ioaddr)16 static int dwmac4_wrback_get_tx_status(struct stmmac_extra_stats *x,
17 struct dma_desc *p,
18 void __iomem *ioaddr)
19 {
20 unsigned int tdes3;
21 int ret = tx_done;
22
23 tdes3 = le32_to_cpu(p->des3);
24
25 /* Get tx owner first */
26 if (unlikely(tdes3 & TDES3_OWN))
27 return tx_dma_own;
28
29 /* Verify tx error by looking at the last segment. */
30 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
31 return tx_not_ls;
32
33 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
34 ret = tx_err;
35
36 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
37 x->tx_jabber++;
38 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
39 x->tx_frame_flushed++;
40 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
41 x->tx_losscarrier++;
42 }
43 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
44 x->tx_carrier++;
45 }
46 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
47 (tdes3 & TDES3_EXCESSIVE_COLLISION)))
48 x->tx_collision +=
49 (tdes3 & TDES3_COLLISION_COUNT_MASK)
50 >> TDES3_COLLISION_COUNT_SHIFT;
51
52 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
53 x->tx_deferred++;
54
55 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) {
56 x->tx_underflow++;
57 ret |= tx_err_bump_tc;
58 }
59
60 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
61 x->tx_ip_header_error++;
62
63 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
64 x->tx_payload_error++;
65 }
66
67 if (unlikely(tdes3 & TDES3_DEFERRED))
68 x->tx_deferred++;
69
70 return ret;
71 }
72
dwmac4_wrback_get_rx_status(struct stmmac_extra_stats * x,struct dma_desc * p)73 static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
74 struct dma_desc *p)
75 {
76 unsigned int rdes1 = le32_to_cpu(p->des1);
77 unsigned int rdes2 = le32_to_cpu(p->des2);
78 unsigned int rdes3 = le32_to_cpu(p->des3);
79 int message_type;
80 int ret = good_frame;
81
82 if (unlikely(rdes3 & RDES3_OWN))
83 return dma_own;
84
85 if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
86 return discard_frame;
87 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
88 return rx_not_ls;
89
90 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
91 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
92 x->rx_length++;
93 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
94 x->rx_gmac_overflow++;
95
96 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
97 x->rx_watchdog++;
98
99 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
100 x->rx_mii++;
101
102 if (unlikely(rdes3 & RDES3_CRC_ERROR))
103 x->rx_crc_errors++;
104
105 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
106 x->dribbling_bit++;
107
108 ret = discard_frame;
109 }
110
111 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
112
113 if (rdes1 & RDES1_IP_HDR_ERROR)
114 x->ip_hdr_err++;
115 if (rdes1 & RDES1_IP_CSUM_BYPASSED)
116 x->ip_csum_bypassed++;
117 if (rdes1 & RDES1_IPV4_HEADER)
118 x->ipv4_pkt_rcvd++;
119 if (rdes1 & RDES1_IPV6_HEADER)
120 x->ipv6_pkt_rcvd++;
121 if (rdes1 & RDES1_IP_PAYLOAD_ERROR)
122 x->ip_payload_err++;
123
124 if (message_type == RDES_EXT_NO_PTP)
125 x->no_ptp_rx_msg_type_ext++;
126 else if (message_type == RDES_EXT_SYNC)
127 x->ptp_rx_msg_type_sync++;
128 else if (message_type == RDES_EXT_FOLLOW_UP)
129 x->ptp_rx_msg_type_follow_up++;
130 else if (message_type == RDES_EXT_DELAY_REQ)
131 x->ptp_rx_msg_type_delay_req++;
132 else if (message_type == RDES_EXT_DELAY_RESP)
133 x->ptp_rx_msg_type_delay_resp++;
134 else if (message_type == RDES_EXT_PDELAY_REQ)
135 x->ptp_rx_msg_type_pdelay_req++;
136 else if (message_type == RDES_EXT_PDELAY_RESP)
137 x->ptp_rx_msg_type_pdelay_resp++;
138 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
139 x->ptp_rx_msg_type_pdelay_follow_up++;
140 else if (message_type == RDES_PTP_ANNOUNCE)
141 x->ptp_rx_msg_type_announce++;
142 else if (message_type == RDES_PTP_MANAGEMENT)
143 x->ptp_rx_msg_type_management++;
144 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
145 x->ptp_rx_msg_pkt_reserved_type++;
146
147 if (rdes1 & RDES1_PTP_PACKET_TYPE)
148 x->ptp_frame_type++;
149 if (rdes1 & RDES1_PTP_VER)
150 x->ptp_ver++;
151 if (rdes1 & RDES1_TIMESTAMP_DROPPED)
152 x->timestamp_dropped++;
153
154 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
155 x->sa_rx_filter_fail++;
156 ret = discard_frame;
157 }
158 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
159 x->da_rx_filter_fail++;
160 ret = discard_frame;
161 }
162
163 if (rdes2 & RDES2_L3_FILTER_MATCH)
164 x->l3_filter_match++;
165 if (rdes2 & RDES2_L4_FILTER_MATCH)
166 x->l4_filter_match++;
167 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
168 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
169 x->l3_l4_filter_no_match++;
170
171 return ret;
172 }
173
dwmac4_rd_get_tx_len(struct dma_desc * p)174 static int dwmac4_rd_get_tx_len(struct dma_desc *p)
175 {
176 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
177 }
178
dwmac4_get_tx_owner(struct dma_desc * p)179 static int dwmac4_get_tx_owner(struct dma_desc *p)
180 {
181 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
182 }
183
dwmac4_set_tx_owner(struct dma_desc * p)184 static void dwmac4_set_tx_owner(struct dma_desc *p)
185 {
186 p->des3 |= cpu_to_le32(TDES3_OWN);
187 }
188
dwmac4_set_rx_owner(struct dma_desc * p,int disable_rx_ic)189 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
190 {
191 u32 flags = (RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
192
193 if (!disable_rx_ic)
194 flags |= RDES3_INT_ON_COMPLETION_EN;
195
196 p->des3 |= cpu_to_le32(flags);
197 }
198
dwmac4_get_tx_ls(struct dma_desc * p)199 static int dwmac4_get_tx_ls(struct dma_desc *p)
200 {
201 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
202 >> TDES3_LAST_DESCRIPTOR_SHIFT;
203 }
204
dwmac4_wrback_get_rx_vlan_tci(struct dma_desc * p)205 static u16 dwmac4_wrback_get_rx_vlan_tci(struct dma_desc *p)
206 {
207 return (le32_to_cpu(p->des0) & RDES0_VLAN_TAG_MASK);
208 }
209
dwmac4_wrback_get_rx_vlan_valid(struct dma_desc * p)210 static bool dwmac4_wrback_get_rx_vlan_valid(struct dma_desc *p)
211 {
212 return ((le32_to_cpu(p->des3) & RDES3_LAST_DESCRIPTOR) &&
213 (le32_to_cpu(p->des3) & RDES3_RDES0_VALID));
214 }
215
dwmac4_wrback_get_rx_frame_len(struct dma_desc * p,int rx_coe)216 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
217 {
218 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
219 }
220
dwmac4_rd_enable_tx_timestamp(struct dma_desc * p)221 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
222 {
223 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
224 }
225
dwmac4_wrback_get_tx_timestamp_status(struct dma_desc * p)226 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
227 {
228 /* Context type from W/B descriptor must be zero */
229 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
230 return 0;
231
232 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
233 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
234 return 1;
235
236 return 0;
237 }
238
dwmac4_get_timestamp(void * desc,u32 ats,u64 * ts)239 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
240 {
241 struct dma_desc *p = (struct dma_desc *)desc;
242 u64 ns;
243
244 ns = le32_to_cpu(p->des0);
245 /* convert high/sec time stamp value to nanosecond */
246 ns += le32_to_cpu(p->des1) * 1000000000ULL;
247
248 *ts = ns;
249 }
250
dwmac4_rx_check_timestamp(void * desc)251 static int dwmac4_rx_check_timestamp(void *desc)
252 {
253 struct dma_desc *p = (struct dma_desc *)desc;
254 unsigned int rdes0 = le32_to_cpu(p->des0);
255 unsigned int rdes1 = le32_to_cpu(p->des1);
256 unsigned int rdes3 = le32_to_cpu(p->des3);
257 u32 own, ctxt;
258 int ret = 1;
259
260 own = rdes3 & RDES3_OWN;
261 ctxt = ((rdes3 & RDES3_CONTEXT_DESCRIPTOR)
262 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
263
264 if (likely(!own && ctxt)) {
265 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
266 /* Corrupted value */
267 ret = -EINVAL;
268 else
269 /* A valid Timestamp is ready to be read */
270 ret = 0;
271 }
272
273 /* Timestamp not ready */
274 return ret;
275 }
276
dwmac4_wrback_get_rx_timestamp_status(void * desc,void * next_desc,u32 ats)277 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
278 u32 ats)
279 {
280 struct dma_desc *p = (struct dma_desc *)desc;
281 int ret = -EINVAL;
282
283 /* Get the status from normal w/b descriptor */
284 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
285 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
286 int i = 0;
287
288 /* Check if timestamp is OK from context descriptor */
289 do {
290 ret = dwmac4_rx_check_timestamp(next_desc);
291 if (ret < 0)
292 goto exit;
293 i++;
294
295 } while ((ret == 1) && (i < 10));
296
297 if (i == 10)
298 ret = -EBUSY;
299 }
300 }
301 exit:
302 if (likely(ret == 0))
303 return 1;
304
305 return 0;
306 }
307
dwmac4_rd_init_rx_desc(struct dma_desc * p,int disable_rx_ic,int mode,int end,int bfsize)308 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
309 int mode, int end, int bfsize)
310 {
311 dwmac4_set_rx_owner(p, disable_rx_ic);
312 }
313
dwmac4_rd_init_tx_desc(struct dma_desc * p,int mode,int end)314 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
315 {
316 p->des0 = 0;
317 p->des1 = 0;
318 p->des2 = 0;
319 p->des3 = 0;
320 }
321
dwmac4_rd_prepare_tx_desc(struct dma_desc * p,int is_fs,int len,bool csum_flag,int mode,bool tx_own,bool ls,unsigned int tot_pkt_len)322 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
323 bool csum_flag, int mode, bool tx_own,
324 bool ls, unsigned int tot_pkt_len)
325 {
326 unsigned int tdes3 = le32_to_cpu(p->des3);
327
328 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
329
330 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
331 if (is_fs)
332 tdes3 |= TDES3_FIRST_DESCRIPTOR;
333 else
334 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
335
336 if (likely(csum_flag))
337 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
338 else
339 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
340
341 if (ls)
342 tdes3 |= TDES3_LAST_DESCRIPTOR;
343 else
344 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
345
346 /* Finally set the OWN bit. Later the DMA will start! */
347 if (tx_own)
348 tdes3 |= TDES3_OWN;
349
350 if (is_fs && tx_own)
351 /* When the own bit, for the first frame, has to be set, all
352 * descriptors for the same frame has to be set before, to
353 * avoid race condition.
354 */
355 dma_wmb();
356
357 p->des3 = cpu_to_le32(tdes3);
358 }
359
dwmac4_rd_prepare_tso_tx_desc(struct dma_desc * p,int is_fs,int len1,int len2,bool tx_own,bool ls,unsigned int tcphdrlen,unsigned int tcppayloadlen)360 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
361 int len1, int len2, bool tx_own,
362 bool ls, unsigned int tcphdrlen,
363 unsigned int tcppayloadlen)
364 {
365 unsigned int tdes3 = le32_to_cpu(p->des3);
366
367 if (len1)
368 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
369
370 if (len2)
371 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
372 & TDES2_BUFFER2_SIZE_MASK);
373
374 if (is_fs) {
375 tdes3 |= TDES3_FIRST_DESCRIPTOR |
376 TDES3_TCP_SEGMENTATION_ENABLE |
377 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
378 TDES3_SLOT_NUMBER_MASK) |
379 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
380 } else {
381 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
382 }
383
384 if (ls)
385 tdes3 |= TDES3_LAST_DESCRIPTOR;
386 else
387 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
388
389 /* Finally set the OWN bit. Later the DMA will start! */
390 if (tx_own)
391 tdes3 |= TDES3_OWN;
392
393 if (is_fs && tx_own)
394 /* When the own bit, for the first frame, has to be set, all
395 * descriptors for the same frame has to be set before, to
396 * avoid race condition.
397 */
398 dma_wmb();
399
400 p->des3 = cpu_to_le32(tdes3);
401 }
402
dwmac4_release_tx_desc(struct dma_desc * p,int mode)403 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
404 {
405 p->des0 = 0;
406 p->des1 = 0;
407 p->des2 = 0;
408 p->des3 = 0;
409 }
410
dwmac4_rd_set_tx_ic(struct dma_desc * p)411 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
412 {
413 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
414 }
415
dwmac4_display_ring(void * head,unsigned int size,bool rx,dma_addr_t dma_rx_phy,unsigned int desc_size)416 static void dwmac4_display_ring(void *head, unsigned int size, bool rx,
417 dma_addr_t dma_rx_phy, unsigned int desc_size)
418 {
419 dma_addr_t dma_addr;
420 int i;
421
422 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
423
424 if (desc_size == sizeof(struct dma_desc)) {
425 struct dma_desc *p = (struct dma_desc *)head;
426
427 for (i = 0; i < size; i++) {
428 dma_addr = dma_rx_phy + i * sizeof(*p);
429 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
430 i, &dma_addr,
431 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
432 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
433 p++;
434 }
435 } else if (desc_size == sizeof(struct dma_extended_desc)) {
436 struct dma_extended_desc *extp = (struct dma_extended_desc *)head;
437
438 for (i = 0; i < size; i++) {
439 dma_addr = dma_rx_phy + i * sizeof(*extp);
440 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
441 i, &dma_addr,
442 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),
443 le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),
444 le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),
445 le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));
446 extp++;
447 }
448 } else if (desc_size == sizeof(struct dma_edesc)) {
449 struct dma_edesc *ep = (struct dma_edesc *)head;
450
451 for (i = 0; i < size; i++) {
452 dma_addr = dma_rx_phy + i * sizeof(*ep);
453 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
454 i, &dma_addr,
455 le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),
456 le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),
457 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),
458 le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));
459 ep++;
460 }
461 } else {
462 pr_err("unsupported descriptor!");
463 }
464 }
465
dwmac4_set_mss_ctxt(struct dma_desc * p,unsigned int mss)466 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
467 {
468 p->des0 = 0;
469 p->des1 = 0;
470 p->des2 = cpu_to_le32(mss);
471 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
472 }
473
dwmac4_set_addr(struct dma_desc * p,dma_addr_t addr)474 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
475 {
476 p->des0 = cpu_to_le32(lower_32_bits(addr));
477 p->des1 = cpu_to_le32(upper_32_bits(addr));
478 }
479
dwmac4_clear(struct dma_desc * p)480 static void dwmac4_clear(struct dma_desc *p)
481 {
482 p->des0 = 0;
483 p->des1 = 0;
484 p->des2 = 0;
485 p->des3 = 0;
486 }
487
dwmac4_set_sarc(struct dma_desc * p,u32 sarc_type)488 static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
489 {
490 sarc_type <<= TDES3_SA_INSERT_CTRL_SHIFT;
491
492 p->des3 |= cpu_to_le32(sarc_type & TDES3_SA_INSERT_CTRL_MASK);
493 }
494
set_16kib_bfsize(int mtu)495 static int set_16kib_bfsize(int mtu)
496 {
497 int ret = 0;
498
499 if (unlikely(mtu >= BUF_SIZE_8KiB))
500 ret = BUF_SIZE_16KiB;
501 return ret;
502 }
503
dwmac4_set_vlan_tag(struct dma_desc * p,u16 tag,u16 inner_tag,u32 inner_type)504 static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
505 u32 inner_type)
506 {
507 p->des0 = 0;
508 p->des1 = 0;
509 p->des2 = 0;
510 p->des3 = 0;
511
512 /* Inner VLAN */
513 if (inner_type) {
514 u32 des = inner_tag << TDES2_IVT_SHIFT;
515
516 des &= TDES2_IVT_MASK;
517 p->des2 = cpu_to_le32(des);
518
519 des = inner_type << TDES3_IVTIR_SHIFT;
520 des &= TDES3_IVTIR_MASK;
521 p->des3 = cpu_to_le32(des | TDES3_IVLTV);
522 }
523
524 /* Outer VLAN */
525 p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
526 p->des3 |= cpu_to_le32(TDES3_VLTV);
527
528 p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
529 }
530
dwmac4_set_vlan(struct dma_desc * p,u32 type)531 static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
532 {
533 type <<= TDES2_VLAN_TAG_SHIFT;
534 p->des2 |= cpu_to_le32(type & TDES2_VLAN_TAG_MASK);
535 }
536
dwmac4_get_rx_header_len(struct dma_desc * p,unsigned int * len)537 static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
538 {
539 *len = le32_to_cpu(p->des2) & RDES2_HL;
540 }
541
dwmac4_set_sec_addr(struct dma_desc * p,dma_addr_t addr,bool buf2_valid)542 static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)
543 {
544 p->des2 = cpu_to_le32(lower_32_bits(addr));
545 p->des3 = cpu_to_le32(upper_32_bits(addr));
546
547 if (buf2_valid)
548 p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);
549 else
550 p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);
551 }
552
dwmac4_set_tbs(struct dma_edesc * p,u32 sec,u32 nsec)553 static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
554 {
555 p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
556 p->des5 = cpu_to_le32(nsec & TDES5_LT);
557 p->des6 = 0;
558 p->des7 = 0;
559 }
560
561 const struct stmmac_desc_ops dwmac4_desc_ops = {
562 .tx_status = dwmac4_wrback_get_tx_status,
563 .rx_status = dwmac4_wrback_get_rx_status,
564 .get_tx_len = dwmac4_rd_get_tx_len,
565 .get_tx_owner = dwmac4_get_tx_owner,
566 .set_tx_owner = dwmac4_set_tx_owner,
567 .set_rx_owner = dwmac4_set_rx_owner,
568 .get_tx_ls = dwmac4_get_tx_ls,
569 .get_rx_vlan_tci = dwmac4_wrback_get_rx_vlan_tci,
570 .get_rx_vlan_valid = dwmac4_wrback_get_rx_vlan_valid,
571 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
572 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
573 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
574 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
575 .get_timestamp = dwmac4_get_timestamp,
576 .set_tx_ic = dwmac4_rd_set_tx_ic,
577 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
578 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
579 .release_tx_desc = dwmac4_release_tx_desc,
580 .init_rx_desc = dwmac4_rd_init_rx_desc,
581 .init_tx_desc = dwmac4_rd_init_tx_desc,
582 .display_ring = dwmac4_display_ring,
583 .set_mss = dwmac4_set_mss_ctxt,
584 .set_addr = dwmac4_set_addr,
585 .clear = dwmac4_clear,
586 .set_sarc = dwmac4_set_sarc,
587 .set_vlan_tag = dwmac4_set_vlan_tag,
588 .set_vlan = dwmac4_set_vlan,
589 .get_rx_header_len = dwmac4_get_rx_header_len,
590 .set_sec_addr = dwmac4_set_sec_addr,
591 .set_tbs = dwmac4_set_tbs,
592 };
593
594 const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
595 .set_16kib_bfsize = set_16kib_bfsize,
596 };
597