1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2025 Chelsio Communications. 5 * Written by: Navdeep Parhar <np@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __T4_ADAPTER_H__ 31 #define __T4_ADAPTER_H__ 32 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/counter.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/seqc.h> 42 #include <sys/sx.h> 43 #include <sys/vmem.h> 44 #include <vm/uma.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <machine/bus.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/taskqueue.h> 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_media.h> 56 #include <net/pfil.h> 57 #include <netinet/in.h> 58 #include <netinet/tcp_lro.h> 59 60 #include "offload.h" 61 #include "t4_ioctl.h" 62 #include "common/t4_msg.h" 63 #include "firmware/t4fw_interface.h" 64 65 #define KTR_CXGBE KTR_SPARE3 66 MALLOC_DECLARE(M_CXGBE); 67 #define CXGBE_UNIMPLEMENTED(s) \ 68 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 69 70 /* 71 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 72 * LIST_HEAD when building iw_cxgbe. 73 */ 74 #define CXGBE_LIST_HEAD(name, type) \ 75 struct name { \ 76 struct type *lh_first; /* first element */ \ 77 } 78 79 #ifndef SYSCTL_ADD_UQUAD 80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 81 #define sysctl_handle_64 sysctl_handle_quad 82 #define CTLTYPE_U64 CTLTYPE_QUAD 83 #endif 84 85 SYSCTL_DECL(_hw_cxgbe); 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 1024, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_SGL_SEGS_VM = 38, 120 TX_SGL_SEGS_VM_TSO = 37, 121 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 122 TX_SGL_SEGS_VXLAN_TSO = 37, 123 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 124 }; 125 126 enum { 127 /* adapter intr_type */ 128 INTR_INTX = (1 << 0), 129 INTR_MSI = (1 << 1), 130 INTR_MSIX = (1 << 2) 131 }; 132 133 enum { 134 XGMAC_MTU = (1 << 0), 135 XGMAC_PROMISC = (1 << 1), 136 XGMAC_ALLMULTI = (1 << 2), 137 XGMAC_VLANEX = (1 << 3), 138 XGMAC_UCADDR = (1 << 4), 139 XGMAC_MCADDRS = (1 << 5), 140 141 XGMAC_ALL = 0xffff 142 }; 143 144 enum { 145 /* flags understood by begin_synchronized_op */ 146 HOLD_LOCK = (1 << 0), 147 SLEEP_OK = (1 << 1), 148 INTR_OK = (1 << 2), 149 150 /* flags understood by end_synchronized_op */ 151 LOCK_HELD = HOLD_LOCK, 152 }; 153 154 enum { 155 /* adapter flags. synch_op or adapter_lock. */ 156 FULL_INIT_DONE = (1 << 0), 157 FW_OK = (1 << 1), 158 CHK_MBOX_ACCESS = (1 << 2), 159 MASTER_PF = (1 << 3), 160 BUF_PACKING_OK = (1 << 6), 161 IS_VF = (1 << 7), 162 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 163 CXGBE_BUSY = (1 << 9), 164 165 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */ 166 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */ 167 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */ 168 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */ 169 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */ 170 171 /* port flags */ 172 HAS_TRACEQ = (1 << 3), 173 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 174 175 /* VI flags */ 176 VI_DETACHING = (1 << 0), 177 VI_INIT_DONE = (1 << 1), 178 /* 1 << 2 is unused, was VI_SYSCTL_CTX */ 179 TX_USES_VM_WR = (1 << 3), 180 VI_SKIP_STATS = (1 << 4), 181 182 /* adapter debug_flags */ 183 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 184 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 185 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 186 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 187 188 /* adapter intr handler flags */ 189 IHF_INTR_CLEAR_ON_INIT = (1 << 0), /* Driver calls t4_intr_clear */ 190 IHF_NO_SHOW = (1 << 1), /* Do not display intr info */ 191 IHF_VERBOSE = (1 << 2), /* Display extra intr info */ 192 IHF_FATAL_IFF_ENABLED = (1 << 3), /* Fatal only if enabled */ 193 IHF_IGNORE_IF_DISABLED = (1 << 4), /* Ignore if disabled */ 194 IHF_CLR_ALL_SET = (1 << 5), /* Clear all set bits */ 195 IHF_CLR_ALL_UNIGNORED = (1 << 6), /* Clear all unignored bits */ 196 IHF_RUN_ALL_ACTIONS = (1 << 7), /* As if all cause are set */ 197 IHF_CLR_DELAYED = (1 << 9), /* Cleared in a delayed call */ 198 }; 199 200 #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING) 201 #define SET_DETACHING(vi) do {(vi)->flags |= VI_DETACHING;} while (0) 202 #define CLR_DETACHING(vi) do {(vi)->flags &= ~VI_DETACHING;} while (0) 203 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 204 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 205 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 206 207 struct vi_info { 208 device_t dev; 209 struct port_info *pi; 210 struct adapter *adapter; 211 212 if_t ifp; 213 struct pfil_head *pfil; 214 215 unsigned long flags; 216 int if_flags; 217 218 uint16_t *rss, *nm_rss; 219 uint16_t viid; /* opaque VI identifier */ 220 uint16_t smt_idx; 221 uint16_t vin; 222 uint8_t vfvld; 223 int16_t xact_addr_filt;/* index of exact MAC address filter */ 224 uint16_t rss_size; /* size of VI's RSS table slice */ 225 uint16_t rss_base; /* start of VI's RSS table slice */ 226 int hashen; 227 228 int nintr; 229 int first_intr; 230 231 /* These need to be int as they are used in sysctl */ 232 int ntxq; /* # of tx queues */ 233 int first_txq; /* index of first tx queue */ 234 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 235 int nrxq; /* # of rx queues */ 236 int first_rxq; /* index of first rx queue */ 237 int nofldtxq; /* # of offload tx queues */ 238 int first_ofld_txq; /* index of first offload tx queue */ 239 int nofldrxq; /* # of offload rx queues */ 240 int first_ofld_rxq; /* index of first offload rx queue */ 241 int nnmtxq; 242 int first_nm_txq; 243 int nnmrxq; 244 int first_nm_rxq; 245 int tmr_idx; 246 int ofld_tmr_idx; 247 int pktc_idx; 248 int ofld_pktc_idx; 249 int qsize_rxq; 250 int qsize_txq; 251 252 struct timeval last_refreshed; 253 struct fw_vi_stats_vf stats; 254 struct mtx tick_mtx; 255 struct callout tick; 256 257 struct sysctl_ctx_list ctx; 258 struct sysctl_oid *rxq_oid; 259 struct sysctl_oid *txq_oid; 260 struct sysctl_oid *nm_rxq_oid; 261 struct sysctl_oid *nm_txq_oid; 262 struct sysctl_oid *ofld_rxq_oid; 263 struct sysctl_oid *ofld_txq_oid; 264 265 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 266 u_int txq_rr; 267 u_int rxq_rr; 268 }; 269 270 struct tx_ch_rl_params { 271 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 272 uint32_t maxrate; 273 }; 274 275 /* CLRL state */ 276 enum clrl_state { 277 CS_UNINITIALIZED = 0, 278 CS_PARAMS_SET, /* sw parameters have been set. */ 279 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 280 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 281 CS_HW_CONFIGURED /* configured in the hardware. */ 282 }; 283 284 /* CLRL flags */ 285 enum { 286 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 287 }; 288 289 struct tx_cl_rl_params { 290 enum clrl_state state; 291 int refcount; 292 uint8_t flags; 293 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 294 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 295 enum fw_sched_params_mode mode; /* aggr or per-flow */ 296 uint32_t maxrate; 297 uint16_t pktsize; 298 uint16_t burstsize; 299 }; 300 301 /* Tx scheduler parameters for a channel/port */ 302 struct tx_sched_params { 303 /* Channel Rate Limiter */ 304 struct tx_ch_rl_params ch_rl; 305 306 /* Class WRR */ 307 /* XXX */ 308 309 /* Class Rate Limiter (including the default pktsize and burstsize). */ 310 int pktsize; 311 int burstsize; 312 struct tx_cl_rl_params cl_rl[]; 313 }; 314 315 struct t4_vf_info { 316 uint8_t mac[ETHER_ADDR_LEN]; 317 uint16_t vlan; 318 bool configured; 319 bool access_vlan; 320 }; 321 322 struct port_info { 323 device_t dev; 324 struct adapter *adapter; 325 326 struct vi_info *vi; 327 int nvi; 328 int up_vis; 329 int uld_vis; 330 bool vxlan_tcam_entry; 331 332 struct tx_sched_params *sched_params; 333 struct t4_vf_info *iov_vfs; 334 uint16_t iov_num_vfs; 335 bool iov_status_supported; 336 337 struct mtx pi_lock; 338 char lockname[16]; 339 unsigned long flags; 340 341 uint8_t hw_port; /* associated hardware port idx */ 342 int8_t mdio_addr; 343 uint8_t port_type; 344 uint8_t mod_type; 345 uint8_t port_id; 346 uint8_t tx_chan; /* tx TP c-channel */ 347 uint8_t rx_chan; /* rx TP c-channel */ 348 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 349 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 350 351 struct link_config link_cfg; 352 struct ifmedia media; 353 354 struct port_stats stats; 355 u_int tnl_cong_drops; 356 u_int tx_parse_error; 357 int fcs_reg; 358 uint64_t fcs_base; 359 360 struct sysctl_ctx_list ctx; 361 }; 362 363 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 364 365 struct cluster_metadata { 366 uma_zone_t zone; 367 caddr_t cl; 368 u_int refcount; 369 }; 370 371 struct fl_sdesc { 372 caddr_t cl; 373 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 374 int16_t moff; /* offset of metadata from cl */ 375 uint8_t zidx; 376 }; 377 378 struct tx_desc { 379 __be64 flit[8]; 380 }; 381 382 struct tx_sdesc { 383 struct mbuf *m; /* m_nextpkt linked chain of frames */ 384 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 385 }; 386 387 388 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 389 struct iq_desc { 390 struct rss_header rss; 391 uint8_t cpl[IQ_PAD]; 392 struct rsp_ctrl rsp; 393 }; 394 #undef IQ_PAD 395 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 396 397 enum { 398 /* iq type */ 399 IQ_OTHER = FW_IQ_IQTYPE_OTHER, 400 IQ_ETH = FW_IQ_IQTYPE_NIC, 401 IQ_OFLD = FW_IQ_IQTYPE_OFLD, 402 403 /* iq flags */ 404 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 405 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 406 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 407 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 408 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 409 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 410 411 /* iq state */ 412 IQS_DISABLED = 0, 413 IQS_BUSY = 1, 414 IQS_IDLE = 2, 415 416 /* netmap related flags */ 417 NM_OFF = 0, 418 NM_ON = 1, 419 NM_BUSY = 2, 420 }; 421 422 enum { 423 CPL_COOKIE_RESERVED = 0, 424 CPL_COOKIE_FILTER, 425 CPL_COOKIE_DDP0, 426 CPL_COOKIE_DDP1, 427 CPL_COOKIE_TOM, 428 CPL_COOKIE_HASHFILTER, 429 CPL_COOKIE_ETHOFLD, 430 CPL_COOKIE_KERN_TLS, 431 432 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 433 }; 434 435 /* 436 * Crypto replies use the low bit in the 64-bit cookie of CPL_FW6_PLD as a 437 * CPL cookie to identify the sender/receiver. 438 */ 439 enum { 440 CPL_FW6_COOKIE_CCR = 0, 441 CPL_FW6_COOKIE_KTLS, 442 443 NUM_CPL_FW6_COOKIES = 2 /* Low bits of cookie value. */ 444 }; 445 446 _Static_assert(powerof2(NUM_CPL_FW6_COOKIES), 447 "NUM_CPL_FW6_COOKIES must be a power of 2"); 448 449 #define CPL_FW6_COOKIE_MASK (NUM_CPL_FW6_COOKIES - 1) 450 451 #define CPL_FW6_PLD_COOKIE(cpl) (be64toh((cpl)->data[1]) & ~CPL_FW6_COOKIE_MASK) 452 453 struct sge_iq; 454 struct rss_header; 455 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 456 struct mbuf *); 457 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 458 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 459 460 /* 461 * Ingress Queue: T4 is producer, driver is consumer. 462 */ 463 struct sge_iq { 464 uint16_t flags; 465 uint8_t qtype; 466 volatile int state; 467 struct adapter *adapter; 468 struct iq_desc *desc; /* KVA of descriptor ring */ 469 int8_t intr_pktc_idx; /* packet count threshold index */ 470 uint8_t gen; /* generation bit */ 471 uint8_t intr_params; /* interrupt holdoff parameters */ 472 int8_t cong_drop; /* congestion drop settings for the queue */ 473 uint16_t qsize; /* size (# of entries) of the queue */ 474 uint16_t sidx; /* index of the entry with the status page */ 475 uint16_t cidx; /* consumer index */ 476 uint16_t cntxt_id; /* SGE context id for the iq */ 477 uint16_t abs_id; /* absolute SGE id for the iq */ 478 int16_t intr_idx; /* interrupt used by the queue */ 479 480 STAILQ_ENTRY(sge_iq) link; 481 482 bus_dma_tag_t desc_tag; 483 bus_dmamap_t desc_map; 484 bus_addr_t ba; /* bus address of descriptor ring */ 485 }; 486 487 enum { 488 /* eq type */ 489 EQ_CTRL = 1, 490 EQ_ETH = 2, 491 EQ_OFLD = 3, 492 493 /* eq flags */ 494 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 495 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 496 EQ_ENABLED = (1 << 3), /* open for business */ 497 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 498 }; 499 500 /* Listed in order of preference. Update t4_sysctls too if you change these */ 501 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 502 503 /* 504 * Egress Queue: driver is producer, T4 is consumer. 505 * 506 * Note: A free list is an egress queue (driver produces the buffers and T4 507 * consumes them) but it's special enough to have its own struct (see sge_fl). 508 */ 509 struct sge_eq { 510 unsigned int flags; /* MUST be first */ 511 unsigned int cntxt_id; /* SGE context id for the eq */ 512 unsigned int abs_id; /* absolute SGE id for the eq */ 513 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 514 uint8_t doorbells; 515 uint8_t port_id; /* port_id of the port associated with the eq */ 516 uint8_t tx_chan; /* tx channel used by the eq */ 517 uint8_t hw_port; /* hw port used by the eq */ 518 struct mtx eq_lock; 519 520 struct tx_desc *desc; /* KVA of descriptor ring */ 521 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 522 u_int udb_qid; /* relative qid within the doorbell page */ 523 uint16_t sidx; /* index of the entry with the status page */ 524 uint16_t cidx; /* consumer idx (desc idx) */ 525 uint16_t pidx; /* producer idx (desc idx) */ 526 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 527 uint16_t dbidx; /* pidx of the most recent doorbell */ 528 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 529 volatile u_int equiq; /* EQUIQ outstanding */ 530 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 531 532 bus_dma_tag_t desc_tag; 533 bus_dmamap_t desc_map; 534 bus_addr_t ba; /* bus address of descriptor ring */ 535 char lockname[16]; 536 }; 537 538 struct rx_buf_info { 539 uma_zone_t zone; /* zone that this cluster comes from */ 540 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 541 * hwsize[hwidx1] = size1. No spare. */ 542 uint16_t size2; /* hwsize[hwidx2] = size2. 543 * spare in cluster = size1 - size2. */ 544 int8_t hwidx1; /* SGE bufsize idx for size1 */ 545 int8_t hwidx2; /* SGE bufsize idx for size2 */ 546 uint8_t type; /* EXT_xxx type of the cluster */ 547 }; 548 549 enum { 550 NUM_MEMWIN = 3, 551 552 MEMWIN0_APERTURE = 2048, 553 MEMWIN0_BASE = 0x1b800, 554 555 MEMWIN1_APERTURE = 32768, 556 MEMWIN1_BASE = 0x28000, 557 558 MEMWIN2_APERTURE_T4 = 65536, 559 MEMWIN2_BASE_T4 = 0x30000, 560 561 MEMWIN2_APERTURE_T5 = 128 * 1024, 562 MEMWIN2_BASE_T5 = 0x60000, 563 }; 564 565 struct memwin { 566 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 567 uint32_t mw_base; /* constant after setup_memwin */ 568 uint32_t mw_aperture; /* ditto */ 569 uint32_t mw_curpos; /* protected by mw_lock */ 570 }; 571 572 enum { 573 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 574 FL_DOOMED = (1 << 1), /* about to be destroyed */ 575 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 576 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 577 }; 578 579 #define FL_RUNNING_LOW(fl) \ 580 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 581 #define FL_NOT_RUNNING_LOW(fl) \ 582 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 583 584 struct sge_fl { 585 struct mtx fl_lock; 586 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 587 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 588 uint16_t zidx; /* refill zone idx */ 589 uint16_t safe_zidx; 590 uint16_t lowat; /* # of buffers <= this means fl needs help */ 591 int flags; 592 uint16_t buf_boundary; 593 594 /* The 16b idx all deal with hw descriptors */ 595 uint16_t dbidx; /* hw pidx after last doorbell */ 596 uint16_t sidx; /* index of status page */ 597 volatile uint16_t hw_cidx; 598 599 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 600 uint32_t cidx; /* consumer index */ 601 uint32_t pidx; /* producer index */ 602 603 uint32_t dbval; 604 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 605 volatile uint32_t *udb; 606 607 uint64_t cl_allocated; /* # of clusters allocated */ 608 uint64_t cl_recycled; /* # of clusters recycled */ 609 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 610 611 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 612 struct mbuf *m0; 613 struct mbuf **pnext; 614 u_int remaining; 615 616 uint16_t qsize; /* # of hw descriptors (status page included) */ 617 uint16_t cntxt_id; /* SGE context id for the freelist */ 618 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 619 bus_dma_tag_t desc_tag; 620 bus_dmamap_t desc_map; 621 char lockname[16]; 622 bus_addr_t ba; /* bus address of descriptor ring */ 623 }; 624 625 struct mp_ring; 626 627 struct txpkts { 628 uint8_t wr_type; /* type 0 or type 1 */ 629 uint8_t npkt; /* # of packets in this work request */ 630 uint8_t len16; /* # of 16B pieces used by this work request */ 631 uint8_t score; 632 uint8_t max_npkt; /* maximum number of packets allowed */ 633 uint16_t plen; /* total payload (sum of all packets) */ 634 635 /* straight from fw_eth_tx_pkts_vm_wr. */ 636 __u8 ethmacdst[6]; 637 __u8 ethmacsrc[6]; 638 __be16 ethtype; 639 __be16 vlantci; 640 641 struct mbuf *mb[15]; 642 }; 643 644 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 645 struct sge_txq { 646 struct sge_eq eq; /* MUST be first */ 647 648 if_t ifp; /* the interface this txq belongs to */ 649 struct mp_ring *r; /* tx software ring */ 650 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 651 struct sglist *gl; 652 __be32 cpl_ctrl0; /* for convenience */ 653 int tc_idx; /* traffic class */ 654 uint64_t last_tx; /* cycle count when eth_tx was last called */ 655 struct txpkts txp; 656 657 struct task tx_reclaim_task; 658 /* stats for common events first */ 659 660 uint64_t txcsum; /* # of times hardware assisted with checksum */ 661 uint64_t tso_wrs; /* # of TSO work requests */ 662 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 663 uint64_t imm_wrs; /* # of work requests with immediate data */ 664 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 665 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 666 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 667 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 668 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 669 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 670 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 671 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 672 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 673 uint64_t vxlan_txcsum; 674 675 uint64_t kern_tls_records; 676 uint64_t kern_tls_short; 677 uint64_t kern_tls_partial; 678 uint64_t kern_tls_full; 679 uint64_t kern_tls_octets; 680 uint64_t kern_tls_waste; 681 uint64_t kern_tls_header; 682 uint64_t kern_tls_fin_short; 683 uint64_t kern_tls_cbc; 684 uint64_t kern_tls_gcm; 685 union { 686 struct { 687 /* T6 only. */ 688 uint64_t kern_tls_options; 689 uint64_t kern_tls_fin; 690 }; 691 struct { 692 /* T7 only. */ 693 uint64_t kern_tls_ghash_received; 694 uint64_t kern_tls_ghash_requested; 695 uint64_t kern_tls_lso; 696 uint64_t kern_tls_partial_ghash; 697 uint64_t kern_tls_splitmode; 698 uint64_t kern_tls_trailer; 699 uint64_t kern_tls_imm_only; 700 uint64_t kern_tls_imm_last16; 701 }; 702 }; 703 704 /* stats for not-that-common events */ 705 706 /* Optional scratch space for constructing work requests. */ 707 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 708 } __aligned(CACHE_LINE_SIZE); 709 710 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 711 struct sge_rxq { 712 struct sge_iq iq; /* MUST be first */ 713 struct sge_fl fl; /* MUST follow iq */ 714 715 if_t ifp; /* the interface this rxq belongs to */ 716 struct lro_ctrl lro; /* LRO state */ 717 718 /* stats for common events first */ 719 720 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 721 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 722 uint64_t vxlan_rxcsum; 723 724 /* stats for not-that-common events */ 725 726 } __aligned(CACHE_LINE_SIZE); 727 728 static inline struct sge_rxq * 729 iq_to_rxq(struct sge_iq *iq) 730 { 731 732 return (__containerof(iq, struct sge_rxq, iq)); 733 } 734 735 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 736 struct sge_ofld_rxq { 737 struct sge_iq iq; /* MUST be first */ 738 struct sge_fl fl; /* MUST follow iq */ 739 counter_u64_t rx_iscsi_ddp_setup_ok; 740 counter_u64_t rx_iscsi_ddp_setup_error; 741 uint64_t rx_iscsi_ddp_pdus; 742 uint64_t rx_iscsi_ddp_octets; 743 uint64_t rx_iscsi_fl_pdus; 744 uint64_t rx_iscsi_fl_octets; 745 uint64_t rx_iscsi_padding_errors; 746 uint64_t rx_iscsi_header_digest_errors; 747 uint64_t rx_iscsi_data_digest_errors; 748 counter_u64_t rx_nvme_ddp_setup_ok; 749 counter_u64_t rx_nvme_ddp_setup_no_stag; 750 counter_u64_t rx_nvme_ddp_setup_error; 751 counter_u64_t rx_nvme_ddp_pdus; 752 counter_u64_t rx_nvme_ddp_octets; 753 counter_u64_t rx_nvme_fl_pdus; 754 counter_u64_t rx_nvme_fl_octets; 755 counter_u64_t rx_nvme_invalid_headers; 756 counter_u64_t rx_nvme_header_digest_errors; 757 counter_u64_t rx_nvme_data_digest_errors; 758 uint64_t rx_aio_ddp_jobs; 759 uint64_t rx_aio_ddp_octets; 760 u_long rx_toe_tls_records; 761 u_long rx_toe_tls_octets; 762 u_long rx_toe_ddp_octets; 763 counter_u64_t ddp_buffer_alloc; 764 counter_u64_t ddp_buffer_reuse; 765 counter_u64_t ddp_buffer_free; 766 } __aligned(CACHE_LINE_SIZE); 767 768 static inline struct sge_ofld_rxq * 769 iq_to_ofld_rxq(struct sge_iq *iq) 770 { 771 772 return (__containerof(iq, struct sge_ofld_rxq, iq)); 773 } 774 775 struct wrqe { 776 STAILQ_ENTRY(wrqe) link; 777 struct sge_wrq *wrq; 778 int wr_len; 779 char wr[] __aligned(16); 780 }; 781 782 struct wrq_cookie { 783 TAILQ_ENTRY(wrq_cookie) link; 784 int ndesc; 785 int pidx; 786 }; 787 788 /* 789 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 790 * are of this type. 791 */ 792 struct sge_wrq { 793 struct sge_eq eq; /* MUST be first */ 794 795 struct adapter *adapter; 796 struct task wrq_tx_task; 797 798 /* Tx desc reserved but WR not "committed" yet. */ 799 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 800 801 /* List of WRs ready to go out as soon as descriptors are available. */ 802 STAILQ_HEAD(, wrqe) wr_list; 803 u_int nwr_pending; 804 u_int ndesc_needed; 805 806 /* stats for common events first */ 807 808 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 809 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 810 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 811 812 /* stats for not-that-common events */ 813 814 /* 815 * Scratch space for work requests that wrap around after reaching the 816 * status page, and some information about the last WR that used it. 817 */ 818 uint16_t ss_pidx; 819 uint16_t ss_len; 820 uint8_t ss[SGE_MAX_WR_LEN]; 821 822 } __aligned(CACHE_LINE_SIZE); 823 824 /* ofld_txq: SGE egress queue + miscellaneous items */ 825 struct sge_ofld_txq { 826 struct sge_wrq wrq; 827 counter_u64_t tx_iscsi_pdus; 828 counter_u64_t tx_iscsi_octets; 829 counter_u64_t tx_iscsi_iso_wrs; 830 counter_u64_t tx_nvme_pdus; 831 counter_u64_t tx_nvme_octets; 832 counter_u64_t tx_nvme_iso_wrs; 833 counter_u64_t tx_aio_jobs; 834 counter_u64_t tx_aio_octets; 835 counter_u64_t tx_toe_tls_records; 836 counter_u64_t tx_toe_tls_octets; 837 } __aligned(CACHE_LINE_SIZE); 838 839 static inline int 840 ofld_txq_group(int val, int mask) 841 { 842 const uint32_t ngroup = 1 << bitcount32(mask); 843 const int mshift = ffs(mask) - 1; 844 const uint32_t gmask = ngroup - 1; 845 846 return (val >> mshift & gmask); 847 } 848 849 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 850 struct sge_nm_rxq { 851 /* Items used by the driver rx ithread are in this cacheline. */ 852 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 853 u_int nid; /* netmap ring # for this queue */ 854 struct vi_info *vi; 855 856 struct iq_desc *iq_desc; 857 uint16_t iq_abs_id; 858 uint16_t iq_cntxt_id; 859 uint16_t iq_cidx; 860 uint16_t iq_sidx; 861 uint8_t iq_gen; 862 uint32_t fl_sidx; 863 864 /* Items used by netmap rxsync are in this cacheline. */ 865 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 866 uint16_t fl_cntxt_id; 867 uint32_t fl_pidx; 868 uint32_t fl_sidx2; /* copy of fl_sidx */ 869 uint32_t fl_db_val; 870 u_int fl_db_saved; 871 u_int fl_db_threshold; /* in descriptors */ 872 u_int fl_hwidx:4; 873 874 /* 875 * fl_cidx is used by both the ithread and rxsync, the rest are not used 876 * in the rx fast path. 877 */ 878 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 879 880 bus_dma_tag_t iq_desc_tag; 881 bus_dmamap_t iq_desc_map; 882 bus_addr_t iq_ba; 883 int intr_idx; 884 885 bus_dma_tag_t fl_desc_tag; 886 bus_dmamap_t fl_desc_map; 887 bus_addr_t fl_ba; 888 }; 889 890 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 891 struct sge_nm_txq { 892 struct tx_desc *desc; 893 uint16_t cidx; 894 uint16_t pidx; 895 uint16_t sidx; 896 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 897 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 898 uint16_t dbidx; /* pidx of the most recent doorbell */ 899 uint8_t doorbells; 900 volatile uint32_t *udb; 901 u_int udb_qid; 902 u_int cntxt_id; 903 __be32 cpl_ctrl0; /* for convenience */ 904 __be32 op_pkd; /* ditto */ 905 u_int nid; /* netmap ring # for this queue */ 906 907 /* infrequently used items after this */ 908 909 bus_dma_tag_t desc_tag; 910 bus_dmamap_t desc_map; 911 bus_addr_t ba; 912 int iqidx; 913 } __aligned(CACHE_LINE_SIZE); 914 915 struct sge { 916 int nctrlq; /* total # of control queues */ 917 int nrxq; /* total # of Ethernet rx queues */ 918 int ntxq; /* total # of Ethernet tx queues */ 919 int nofldrxq; /* total # of TOE rx queues */ 920 int nofldtxq; /* total # of TOE tx queues */ 921 int nnmrxq; /* total # of netmap rx queues */ 922 int nnmtxq; /* total # of netmap tx queues */ 923 int niq; /* total # of ingress queues */ 924 int neq; /* total # of egress queues */ 925 926 struct sge_iq fwq; /* Firmware event queue */ 927 struct sge_wrq *ctrlq; /* Control queues */ 928 struct sge_txq *txq; /* NIC tx queues */ 929 struct sge_rxq *rxq; /* NIC rx queues */ 930 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 931 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 932 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 933 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 934 935 uint16_t iq_start; /* first cntxt_id */ 936 uint16_t iq_base; /* first abs_id */ 937 int eq_start; /* first cntxt_id */ 938 int eq_base; /* first abs_id */ 939 int iqmap_sz; 940 int eqmap_sz; 941 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 942 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 943 944 int8_t safe_zidx; 945 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 946 }; 947 948 struct devnames { 949 const char *nexus_name; 950 const char *ifnet_name; 951 const char *vi_ifnet_name; 952 const char *pf03_drv_name; 953 const char *vf_nexus_name; 954 const char *vf_ifnet_name; 955 }; 956 957 struct clip_entry; 958 959 #define CNT_CAL_INFO 3 960 struct clock_sync { 961 uint64_t hw_cur; 962 uint64_t hw_prev; 963 sbintime_t sbt_cur; 964 sbintime_t sbt_prev; 965 seqc_t gen; 966 }; 967 968 struct adapter { 969 SLIST_ENTRY(adapter) link; 970 device_t dev; 971 struct cdev *cdev; 972 const struct devnames *names; 973 974 /* PCIe register resources */ 975 int regs_rid; 976 struct resource *regs_res; 977 int msix_rid; 978 struct resource *msix_res; 979 bus_size_t mmio_len; 980 int udbs_rid; 981 struct resource *udbs_res; 982 volatile uint8_t *udbs_base; 983 984 unsigned int pf; 985 unsigned int mbox; 986 unsigned int vpd_busy; 987 unsigned int vpd_flag; 988 989 /* Interrupt information */ 990 int intr_type; 991 int intr_count; 992 struct irq { 993 struct resource *res; 994 int rid; 995 void *tag; 996 struct sge_rxq *rxq; 997 struct sge_nm_rxq *nm_rxq; 998 } __aligned(CACHE_LINE_SIZE) *irq; 999 int sge_gts_reg; 1000 int sge_kdoorbell_reg; 1001 1002 bus_dma_tag_t dmat; /* Parent DMA tag */ 1003 1004 struct sge sge; 1005 int lro_timeout; 1006 int sc_do_rxcopy; 1007 1008 int vxlan_port; 1009 u_int vxlan_refcount; 1010 int rawf_base; 1011 int nrawf; 1012 u_int vlan_id; 1013 1014 struct taskqueue *tq[MAX_NPORTS]; /* General purpose taskqueues */ 1015 struct port_info *port[MAX_NPORTS]; 1016 uint8_t chan_map[MAX_NCHAN]; /* tx_chan -> port_id */ 1017 uint8_t port_map[MAX_NPORTS]; /* hw_port -> port_id */ 1018 1019 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 1020 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 1021 u_long clip_mask; 1022 int clip_gen; 1023 struct timeout_task clip_task; 1024 1025 void *tom_softc; /* (struct tom_data *) */ 1026 struct tom_tunables tt; 1027 struct t4_offload_policy *policy; 1028 struct rwlock policy_lock; 1029 1030 void *iwarp_softc; /* (struct c4iw_dev *) */ 1031 struct iw_tunables iwt; 1032 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 1033 void *nvme_ulp_softc; /* (struct nvmf_che_adapter *) */ 1034 struct l2t_data *l2t; /* L2 table */ 1035 struct smt_data *smt; /* Source MAC Table */ 1036 struct tid_info tids; 1037 vmem_t *key_map; 1038 struct tls_tunables tlst; 1039 1040 vmem_t *pbl_arena; 1041 vmem_t *stag_arena; 1042 1043 uint8_t doorbells; 1044 int offload_map; /* port_id's with IFCAP_TOE enabled */ 1045 int bt_map; /* hw_port's that are BASE-T */ 1046 int active_ulds; /* ULDs activated on this adapter */ 1047 int flags; 1048 int debug_flags; 1049 int error_flags; /* Used by error handler and live reset. */ 1050 int intr_flags; /* Used by interrupt setup/handlers. */ 1051 1052 char ifp_lockname[16]; 1053 struct mtx ifp_lock; 1054 if_t ifp; /* tracer ifp */ 1055 struct ifmedia media; 1056 int traceq; /* iq used by all tracers, -1 if none */ 1057 int tracer_valid; /* bitmap of valid tracers */ 1058 int tracer_enabled; /* bitmap of enabled tracers */ 1059 1060 char fw_version[16]; 1061 char tp_version[16]; 1062 char er_version[16]; 1063 char bs_version[16]; 1064 char cfg_file[32]; 1065 u_int cfcsum; 1066 struct adapter_params params; 1067 const struct chip_params *chip_params; 1068 struct t4_virt_res vres; 1069 1070 uint16_t nbmcaps; 1071 uint16_t linkcaps; 1072 uint16_t switchcaps; 1073 uint16_t nvmecaps; 1074 uint16_t niccaps; 1075 uint16_t toecaps; 1076 uint16_t rdmacaps; 1077 uint16_t cryptocaps; 1078 uint16_t iscsicaps; 1079 uint16_t fcoecaps; 1080 1081 struct sysctl_ctx_list ctx; 1082 struct sysctl_oid *ctrlq_oid; 1083 struct sysctl_oid *fwq_oid; 1084 1085 struct mtx sc_lock; 1086 char lockname[16]; 1087 1088 /* Starving free lists */ 1089 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 1090 TAILQ_HEAD(, sge_fl) sfl; 1091 struct callout sfl_callout; 1092 struct callout cal_callout; 1093 struct clock_sync cal_info[CNT_CAL_INFO]; 1094 int cal_current; 1095 int cal_count; 1096 uint32_t cal_gen; 1097 1098 /* 1099 * Driver code that can run when the adapter is suspended must use this 1100 * lock or a synchronized_op and check for HW_OFF_LIMITS before 1101 * accessing hardware. 1102 * 1103 * XXX: could be changed to rwlock. wlock in suspend/resume and for 1104 * indirect register access, rlock everywhere else. 1105 */ 1106 struct mtx reg_lock; 1107 1108 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 1109 1110 struct mtx tc_lock; 1111 struct task tc_task; 1112 1113 struct task fatal_error_task; 1114 struct task reset_task; 1115 const void *reset_thread; 1116 int num_resets; 1117 int incarnation; 1118 1119 const char *last_op; 1120 const void *last_op_thr; 1121 int last_op_flags; 1122 1123 int swintr; 1124 int sensor_resets; 1125 1126 struct callout ktls_tick; 1127 }; 1128 1129 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1130 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1131 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1132 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1133 1134 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1135 KASSERT(IS_BUSY(sc) && \ 1136 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1137 ("%s: operation not synchronized.", __func__)) 1138 1139 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1140 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1141 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1142 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1143 1144 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1145 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1146 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1147 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1148 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1149 1150 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1151 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1152 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1153 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1154 1155 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1156 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1157 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1158 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1159 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1160 1161 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1162 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1163 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1164 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1165 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1166 1167 #define for_each_txq(vi, iter, q) \ 1168 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1169 iter < vi->ntxq; ++iter, ++q) 1170 #define for_each_rxq(vi, iter, q) \ 1171 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1172 iter < vi->nrxq; ++iter, ++q) 1173 #define for_each_ofld_txq(vi, iter, q) \ 1174 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1175 iter < vi->nofldtxq; ++iter, ++q) 1176 #define for_each_ofld_rxq(vi, iter, q) \ 1177 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1178 iter < vi->nofldrxq; ++iter, ++q) 1179 #define for_each_nm_txq(vi, iter, q) \ 1180 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1181 iter < vi->nnmtxq; ++iter, ++q) 1182 #define for_each_nm_rxq(vi, iter, q) \ 1183 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1184 iter < vi->nnmrxq; ++iter, ++q) 1185 #define for_each_vi(_pi, _iter, _vi) \ 1186 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1187 ++(_iter), ++(_vi)) 1188 1189 #define IDXINCR(idx, incr, wrap) do { \ 1190 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1191 } while (0) 1192 #define IDXDIFF(head, tail, wrap) \ 1193 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1194 1195 /* One for errors, one for firmware events */ 1196 #define T4_EXTRA_INTR 2 1197 1198 /* One for firmware events */ 1199 #define T4VF_EXTRA_INTR 1 1200 1201 static inline int 1202 forwarding_intr_to_fwq(struct adapter *sc) 1203 { 1204 1205 return (sc->intr_count == 1); 1206 } 1207 1208 /* Works reliably inside a synch_op or with reg_lock held. */ 1209 static inline bool 1210 hw_off_limits(struct adapter *sc) 1211 { 1212 const int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS; 1213 1214 return (__predict_false(off_limits != 0)); 1215 } 1216 1217 /* Works reliably inside a synch_op or with reg_lock held. */ 1218 static inline bool 1219 hw_all_ok(struct adapter *sc) 1220 { 1221 const int not_ok = atomic_load_int(&sc->error_flags) & 1222 (ADAP_STOPPED | HW_OFF_LIMITS); 1223 1224 return (__predict_true(not_ok == 0)); 1225 } 1226 1227 static inline int 1228 mbuf_nsegs(struct mbuf *m) 1229 { 1230 M_ASSERTPKTHDR(m); 1231 KASSERT(m->m_pkthdr.inner_l5hlen > 0, 1232 ("%s: mbuf %p missing information on # of segments.", __func__, m)); 1233 1234 return (m->m_pkthdr.inner_l5hlen); 1235 } 1236 1237 static inline void 1238 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs) 1239 { 1240 M_ASSERTPKTHDR(m); 1241 m->m_pkthdr.inner_l5hlen = nsegs; 1242 } 1243 1244 /* Internal mbuf flags stored in PH_loc.eight[1]. */ 1245 #define MC_NOMAP 0x01 1246 #define MC_RAW_WR 0x02 1247 #define MC_TLS 0x04 1248 1249 static inline int 1250 mbuf_cflags(struct mbuf *m) 1251 { 1252 M_ASSERTPKTHDR(m); 1253 return (m->m_pkthdr.PH_loc.eight[4]); 1254 } 1255 1256 static inline void 1257 set_mbuf_cflags(struct mbuf *m, uint8_t flags) 1258 { 1259 M_ASSERTPKTHDR(m); 1260 m->m_pkthdr.PH_loc.eight[4] = flags; 1261 } 1262 1263 static inline int 1264 mbuf_len16(struct mbuf *m) 1265 { 1266 int n; 1267 1268 M_ASSERTPKTHDR(m); 1269 n = m->m_pkthdr.PH_loc.eight[0]; 1270 if (!(mbuf_cflags(m) & MC_TLS)) 1271 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16); 1272 1273 return (n); 1274 } 1275 1276 static inline void 1277 set_mbuf_len16(struct mbuf *m, uint8_t len16) 1278 { 1279 M_ASSERTPKTHDR(m); 1280 if (!(mbuf_cflags(m) & MC_TLS)) 1281 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16); 1282 m->m_pkthdr.PH_loc.eight[0] = len16; 1283 } 1284 1285 static inline uint32_t 1286 t4_read_reg(struct adapter *sc, uint32_t reg) 1287 { 1288 if (hw_off_limits(sc)) 1289 MPASS(curthread == sc->reset_thread); 1290 return bus_read_4(sc->regs_res, reg); 1291 } 1292 1293 static inline void 1294 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1295 { 1296 if (hw_off_limits(sc)) 1297 MPASS(curthread == sc->reset_thread); 1298 bus_write_4(sc->regs_res, reg, val); 1299 } 1300 1301 static inline uint64_t 1302 t4_read_reg64(struct adapter *sc, uint32_t reg) 1303 { 1304 if (hw_off_limits(sc)) 1305 MPASS(curthread == sc->reset_thread); 1306 #ifdef __LP64__ 1307 return bus_read_8(sc->regs_res, reg); 1308 #else 1309 return (uint64_t)bus_read_4(sc->regs_res, reg) + 1310 ((uint64_t)bus_read_4(sc->regs_res, reg + 4) << 32); 1311 1312 #endif 1313 } 1314 1315 static inline void 1316 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1317 { 1318 if (hw_off_limits(sc)) 1319 MPASS(curthread == sc->reset_thread); 1320 #ifdef __LP64__ 1321 bus_write_8(sc->regs_res, reg, val); 1322 #else 1323 bus_write_4(sc->regs_res, reg, val); 1324 bus_write_4(sc->regs_res, reg + 4, val>> 32); 1325 #endif 1326 } 1327 1328 static inline void 1329 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1330 { 1331 if (hw_off_limits(sc)) 1332 MPASS(curthread == sc->reset_thread); 1333 *val = pci_read_config(sc->dev, reg, 1); 1334 } 1335 1336 static inline void 1337 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1338 { 1339 if (hw_off_limits(sc)) 1340 MPASS(curthread == sc->reset_thread); 1341 pci_write_config(sc->dev, reg, val, 1); 1342 } 1343 1344 static inline void 1345 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1346 { 1347 1348 if (hw_off_limits(sc)) 1349 MPASS(curthread == sc->reset_thread); 1350 *val = pci_read_config(sc->dev, reg, 2); 1351 } 1352 1353 static inline void 1354 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1355 { 1356 if (hw_off_limits(sc)) 1357 MPASS(curthread == sc->reset_thread); 1358 pci_write_config(sc->dev, reg, val, 2); 1359 } 1360 1361 static inline void 1362 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1363 { 1364 if (hw_off_limits(sc)) 1365 MPASS(curthread == sc->reset_thread); 1366 *val = pci_read_config(sc->dev, reg, 4); 1367 } 1368 1369 static inline void 1370 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1371 { 1372 if (hw_off_limits(sc)) 1373 MPASS(curthread == sc->reset_thread); 1374 pci_write_config(sc->dev, reg, val, 4); 1375 } 1376 1377 static inline struct port_info * 1378 adap2pinfo(struct adapter *sc, int idx) 1379 { 1380 1381 return (sc->port[idx]); 1382 } 1383 1384 static inline void 1385 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1386 { 1387 1388 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1389 } 1390 1391 static inline int 1392 tx_resume_threshold(struct sge_eq *eq) 1393 { 1394 1395 /* not quite the same as qsize / 4, but this will do. */ 1396 return (eq->sidx / 4); 1397 } 1398 1399 static inline int 1400 t4_use_ldst(struct adapter *sc) 1401 { 1402 1403 #ifdef notyet 1404 return (sc->flags & FW_OK || !sc->use_bd); 1405 #else 1406 return (0); 1407 #endif 1408 } 1409 1410 static inline void 1411 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1412 const char *msg, const __be64 *const p, const bool err) 1413 { 1414 1415 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1416 return; 1417 if (p != NULL) { 1418 log(err ? LOG_ERR : LOG_DEBUG, 1419 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1420 "%016llx %016llx %016llx %016llx\n", 1421 device_get_nameunit(sc->dev), mbox, msg, 1422 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1423 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1424 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1425 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1426 } else { 1427 log(err ? LOG_ERR : LOG_DEBUG, 1428 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1429 "%016llx %016llx %016llx %016llx\n", 1430 device_get_nameunit(sc->dev), mbox, msg, 1431 (long long)t4_read_reg64(sc, reg), 1432 (long long)t4_read_reg64(sc, reg + 8), 1433 (long long)t4_read_reg64(sc, reg + 16), 1434 (long long)t4_read_reg64(sc, reg + 24), 1435 (long long)t4_read_reg64(sc, reg + 32), 1436 (long long)t4_read_reg64(sc, reg + 40), 1437 (long long)t4_read_reg64(sc, reg + 48), 1438 (long long)t4_read_reg64(sc, reg + 56)); 1439 } 1440 } 1441 1442 /* t4_main.c */ 1443 extern int t4_ntxq; 1444 extern int t4_nrxq; 1445 extern int t4_intr_types; 1446 extern int t4_tmr_idx; 1447 extern int t4_pktc_idx; 1448 extern unsigned int t4_qsize_rxq; 1449 extern unsigned int t4_qsize_txq; 1450 extern int t4_ddp_rcvbuf_len; 1451 extern unsigned int t4_ddp_rcvbuf_cache; 1452 extern device_method_t cxgbe_methods[]; 1453 1454 int t4_os_find_pci_capability(struct adapter *, int); 1455 void t4_os_portmod_changed(struct port_info *); 1456 void t4_os_link_changed(struct port_info *); 1457 void t4_iterate(void (*)(struct adapter *, void *), void *); 1458 void t4_init_devnames(struct adapter *); 1459 void t4_add_adapter(struct adapter *); 1460 int t4_detach_common(device_t); 1461 int t4_map_bars_0_and_4(struct adapter *); 1462 int t4_map_bar_2(struct adapter *); 1463 int t4_adj_doorbells(struct adapter *); 1464 int t4_setup_intr_handlers(struct adapter *); 1465 void t4_sysctls(struct adapter *); 1466 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1467 void end_synchronized_op(struct adapter *, int); 1468 void begin_vi_detach(struct adapter *, struct vi_info *); 1469 void end_vi_detach(struct adapter *, struct vi_info *); 1470 int update_mac_settings(if_t, int); 1471 int adapter_init(struct adapter *); 1472 int vi_init(struct vi_info *); 1473 void vi_sysctls(struct vi_info *); 1474 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1475 int alloc_atid(struct adapter *, void *); 1476 void *lookup_atid(struct adapter *, int); 1477 void free_atid(struct adapter *, int); 1478 void release_tid(struct adapter *, int, struct sge_wrq *); 1479 int cxgbe_media_change(if_t); 1480 void cxgbe_media_status(if_t, struct ifmediareq *); 1481 void t4_os_cim_err(struct adapter *); 1482 int suspend_adapter(struct adapter *); 1483 int resume_adapter(struct adapter *); 1484 int toe_capability(struct vi_info *, bool); 1485 1486 #ifdef KERN_TLS 1487 /* t6_kern_tls.c */ 1488 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1489 struct m_snd_tag **); 1490 void t6_ktls_modload(void); 1491 void t6_ktls_modunload(void); 1492 int t6_ktls_try(if_t, struct socket *, struct ktls_session *); 1493 int t6_ktls_parse_pkt(struct mbuf *); 1494 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1495 1496 /* t7_kern_tls.c */ 1497 int t7_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1498 struct m_snd_tag **); 1499 void t7_ktls_modload(void); 1500 void t7_ktls_modunload(void); 1501 int t7_ktls_parse_pkt(struct mbuf *); 1502 int t7_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int); 1503 #endif 1504 1505 /* t4_keyctx.c */ 1506 struct auth_hash; 1507 union authctx; 1508 #ifdef KERN_TLS 1509 struct ktls_session; 1510 struct tls_key_req; 1511 struct tls_keyctx; 1512 #endif 1513 1514 void t4_aes_getdeckey(void *, const void *, unsigned int); 1515 void t4_copy_partial_hash(int, union authctx *, void *); 1516 void t4_init_gmac_hash(const char *, int, char *); 1517 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1518 char *); 1519 #ifdef KERN_TLS 1520 u_int t4_tls_key_info_size(const struct ktls_session *); 1521 int t4_tls_proto_ver(const struct ktls_session *); 1522 int t4_tls_cipher_mode(const struct ktls_session *); 1523 int t4_tls_auth_mode(const struct ktls_session *); 1524 int t4_tls_hmac_ctrl(const struct ktls_session *); 1525 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1526 int t4_alloc_tls_keyid(struct adapter *); 1527 void t4_free_tls_keyid(struct adapter *, int); 1528 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1529 struct tls_key_req *); 1530 #endif 1531 1532 #ifdef DEV_NETMAP 1533 /* t4_netmap.c */ 1534 struct sge_nm_rxq; 1535 void cxgbe_nm_attach(struct vi_info *); 1536 void cxgbe_nm_detach(struct vi_info *); 1537 void service_nm_rxq(struct sge_nm_rxq *); 1538 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1539 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1540 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1541 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1542 #endif 1543 1544 /* t4_sge.c */ 1545 void t4_sge_modload(void); 1546 void t4_sge_modunload(void); 1547 uint64_t t4_sge_extfree_refs(void); 1548 void t4_tweak_chip_settings(struct adapter *); 1549 int t4_verify_chip_settings(struct adapter *); 1550 void t4_init_rx_buf_info(struct adapter *); 1551 int t4_create_dma_tag(struct adapter *); 1552 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1553 struct sysctl_oid_list *); 1554 int t4_destroy_dma_tag(struct adapter *); 1555 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1556 bus_addr_t *, void **); 1557 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1558 void *); 1559 void free_fl_buffers(struct adapter *, struct sge_fl *); 1560 int t4_setup_adapter_queues(struct adapter *); 1561 int t4_teardown_adapter_queues(struct adapter *); 1562 int t4_setup_vi_queues(struct vi_info *); 1563 int t4_teardown_vi_queues(struct vi_info *); 1564 void t4_intr_all(void *); 1565 void t4_intr(void *); 1566 #ifdef DEV_NETMAP 1567 void t4_nm_intr(void *); 1568 void t4_vi_intr(void *); 1569 #endif 1570 void t4_intr_err(void *); 1571 void t4_intr_evt(void *); 1572 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1573 void t4_update_fl_bufsize(if_t); 1574 struct mbuf *alloc_wr_mbuf(int, int); 1575 int parse_pkt(struct mbuf **, bool); 1576 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1577 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1578 int t4_sge_set_conm_context(struct adapter *, int, int, int); 1579 void t4_register_an_handler(an_handler_t); 1580 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1581 void t4_register_cpl_handler(int, cpl_handler_t); 1582 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1583 #ifdef RATELIMIT 1584 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1585 #endif 1586 1587 /* t4_tracer.c */ 1588 struct t4_tracer; 1589 void t4_tracer_modload(void); 1590 void t4_tracer_modunload(void); 1591 void t4_tracer_port_detach(struct adapter *); 1592 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1593 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1594 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1595 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1596 1597 /* t4_sched.c */ 1598 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1599 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1600 int t4_init_tx_sched(struct adapter *); 1601 int t4_free_tx_sched(struct adapter *); 1602 void t4_update_tx_sched(struct adapter *); 1603 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1604 void t4_release_cl_rl(struct adapter *, int, int); 1605 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1606 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1607 #ifdef RATELIMIT 1608 void t4_init_etid_table(struct adapter *); 1609 void t4_free_etid_table(struct adapter *); 1610 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1611 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *, 1612 struct m_snd_tag **); 1613 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1614 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *); 1615 #endif 1616 1617 /* t4_filter.c */ 1618 int get_filter_mode(struct adapter *, uint32_t *); 1619 int set_filter_mode(struct adapter *, uint32_t); 1620 int set_filter_mask(struct adapter *, uint32_t); 1621 int get_filter(struct adapter *, struct t4_filter *); 1622 int set_filter(struct adapter *, struct t4_filter *); 1623 int del_filter(struct adapter *, struct t4_filter *); 1624 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1625 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1626 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1627 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1628 void free_hftid_hash(struct tid_info *); 1629 1630 /* t4_tpt.c */ 1631 #define T4_STAG_UNSET 0xffffffff 1632 #define T4_WRITE_MEM_DMA_LEN \ 1633 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_sgl), 16) 1634 #define T4_ULPTX_MIN_IO 32 1635 #define T4_MAX_INLINE_SIZE 96 1636 #define T4_WRITE_MEM_INLINE_LEN(len) \ 1637 roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_idata) + \ 1638 roundup((len), T4_ULPTX_MIN_IO), 16) 1639 1640 uint32_t t4_pblpool_alloc(struct adapter *, int); 1641 void t4_pblpool_free(struct adapter *, uint32_t, int); 1642 uint32_t t4_stag_alloc(struct adapter *, int); 1643 void t4_stag_free(struct adapter *, uint32_t, int); 1644 void t4_init_tpt(struct adapter *); 1645 void t4_free_tpt(struct adapter *); 1646 void t4_write_mem_dma_wr(struct adapter *, void *, int, int, uint32_t, 1647 uint32_t, vm_paddr_t, uint64_t); 1648 void t4_write_mem_inline_wr(struct adapter *, void *, int, int, uint32_t, 1649 uint32_t, void *, uint64_t); 1650 1651 static inline struct wrqe * 1652 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1653 { 1654 int len = offsetof(struct wrqe, wr) + wr_len; 1655 struct wrqe *wr; 1656 1657 wr = malloc(len, M_CXGBE, M_NOWAIT); 1658 if (__predict_false(wr == NULL)) 1659 return (NULL); 1660 wr->wr_len = wr_len; 1661 wr->wrq = wrq; 1662 return (wr); 1663 } 1664 1665 static inline void * 1666 wrtod(struct wrqe *wr) 1667 { 1668 return (&wr->wr[0]); 1669 } 1670 1671 static inline void 1672 free_wrqe(struct wrqe *wr) 1673 { 1674 free(wr, M_CXGBE); 1675 } 1676 1677 static inline void 1678 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1679 { 1680 struct sge_wrq *wrq = wr->wrq; 1681 1682 TXQ_LOCK(wrq); 1683 if (__predict_true(wrq->eq.flags & EQ_HW_ALLOCATED)) 1684 t4_wrq_tx_locked(sc, wrq, wr); 1685 else 1686 free(wr, M_CXGBE); 1687 TXQ_UNLOCK(wrq); 1688 } 1689 1690 static inline int 1691 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1692 int len) 1693 { 1694 1695 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1696 } 1697 1698 static inline int 1699 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1700 const uint32_t *val, int len) 1701 { 1702 1703 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1704 } 1705 1706 /* Number of len16 -> number of descriptors */ 1707 static inline int 1708 tx_len16_to_desc(int len16) 1709 { 1710 1711 return (howmany(len16, EQ_ESIZE / 16)); 1712 } 1713 #endif 1714