xref: /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /*
2  * Copyright (c) 2010 Broadcom Corporation
3  * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
12  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
14  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
15  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 
20 #include <linux/pci_ids.h>
21 #include <linux/if_ether.h>
22 #include <net/cfg80211.h>
23 #include <net/mac80211.h>
24 #include <brcm_hw_ids.h>
25 #include <aiutils.h>
26 #include <chipcommon.h>
27 #include "rate.h"
28 #include "scb.h"
29 #include "phy/phy_hal.h"
30 #include "channel.h"
31 #include "antsel.h"
32 #include "stf.h"
33 #include "ampdu.h"
34 #include "mac80211_if.h"
35 #include "ucode_loader.h"
36 #include "main.h"
37 #include "soc.h"
38 #include "dma.h"
39 #include "debug.h"
40 #include "brcms_trace_events.h"
41 
42 /* watchdog timer, in unit of ms */
43 #define TIMER_INTERVAL_WATCHDOG		1000
44 /* radio monitor timer, in unit of ms */
45 #define TIMER_INTERVAL_RADIOCHK		800
46 
47 /* beacon interval, in unit of 1024TU */
48 #define BEACON_INTERVAL_DEFAULT		100
49 
50 /* n-mode support capability */
51 /* 2x2 includes both 1x1 & 2x2 devices
52  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
53  * control it independently
54  */
55 #define WL_11N_2x2			1
56 #define WL_11N_3x3			3
57 #define WL_11N_4x4			4
58 
59 #define EDCF_ACI_MASK			0x60
60 #define EDCF_ACI_SHIFT			5
61 #define EDCF_ECWMIN_MASK		0x0f
62 #define EDCF_ECWMAX_SHIFT		4
63 #define EDCF_AIFSN_MASK			0x0f
64 #define EDCF_AIFSN_MAX			15
65 #define EDCF_ECWMAX_MASK		0xf0
66 
67 #define EDCF_AC_BE_TXOP_STA		0x0000
68 #define EDCF_AC_BK_TXOP_STA		0x0000
69 #define EDCF_AC_VO_ACI_STA		0x62
70 #define EDCF_AC_VO_ECW_STA		0x32
71 #define EDCF_AC_VI_ACI_STA		0x42
72 #define EDCF_AC_VI_ECW_STA		0x43
73 #define EDCF_AC_BK_ECW_STA		0xA4
74 #define EDCF_AC_VI_TXOP_STA		0x005e
75 #define EDCF_AC_VO_TXOP_STA		0x002f
76 #define EDCF_AC_BE_ACI_STA		0x03
77 #define EDCF_AC_BE_ECW_STA		0xA4
78 #define EDCF_AC_BK_ACI_STA		0x27
79 #define EDCF_AC_VO_TXOP_AP		0x002f
80 
81 #define EDCF_TXOP2USEC(txop)		((txop) << 5)
82 #define EDCF_ECW2CW(exp)		((1 << (exp)) - 1)
83 
84 #define APHY_SYMBOL_TIME		4
85 #define APHY_PREAMBLE_TIME		16
86 #define APHY_SIGNAL_TIME		4
87 #define APHY_SIFS_TIME			16
88 #define APHY_SERVICE_NBITS		16
89 #define APHY_TAIL_NBITS			6
90 #define BPHY_SIFS_TIME			10
91 #define BPHY_PLCP_SHORT_TIME		96
92 
93 #define PREN_PREAMBLE			24
94 #define PREN_MM_EXT			12
95 #define PREN_PREAMBLE_EXT		4
96 
97 #define DOT11_MAC_HDR_LEN		24
98 #define DOT11_ACK_LEN			10
99 #define DOT11_BA_LEN			4
100 #define DOT11_OFDM_SIGNAL_EXTENSION	6
101 #define DOT11_MIN_FRAG_LEN		256
102 #define DOT11_RTS_LEN			16
103 #define DOT11_CTS_LEN			10
104 #define DOT11_BA_BITMAP_LEN		128
105 #define DOT11_MAXNUMFRAGS		16
106 #define DOT11_MAX_FRAG_LEN		2346
107 
108 #define BPHY_PLCP_TIME			192
109 #define RIFS_11N_TIME			2
110 
111 /* length of the BCN template area */
112 #define BCN_TMPL_LEN			512
113 
114 /* brcms_bss_info flag bit values */
115 #define BRCMS_BSS_HT			0x0020	/* BSS is HT (MIMO) capable */
116 
117 /* chip rx buffer offset */
118 #define BRCMS_HWRXOFF			38
119 
120 /* rfdisable delay timer 500 ms, runs of ALP clock */
121 #define RFDISABLE_DEFAULT		10000000
122 
123 #define BRCMS_TEMPSENSE_PERIOD		10	/* 10 second timeout */
124 
125 /* synthpu_dly times in us */
126 #define SYNTHPU_DLY_APHY_US		3700
127 #define SYNTHPU_DLY_BPHY_US		1050
128 #define SYNTHPU_DLY_NPHY_US		2048
129 #define SYNTHPU_DLY_LPPHY_US		300
130 
131 #define ANTCNT				10	/* vanilla M_MAX_ANTCNT val */
132 
133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
134 #define EDCF_SHORT_S			0
135 #define EDCF_SFB_S			4
136 #define EDCF_LONG_S			8
137 #define EDCF_LFB_S			12
138 #define EDCF_SHORT_M			BITFIELD_MASK(4)
139 #define EDCF_SFB_M			BITFIELD_MASK(4)
140 #define EDCF_LONG_M			BITFIELD_MASK(4)
141 #define EDCF_LFB_M			BITFIELD_MASK(4)
142 
143 #define RETRY_SHORT_DEF			7	/* Default Short retry Limit */
144 #define RETRY_SHORT_MAX			255	/* Maximum Short retry Limit */
145 #define RETRY_LONG_DEF			4	/* Default Long retry count */
146 #define RETRY_SHORT_FB			3	/* Short count for fb rate */
147 #define RETRY_LONG_FB			2	/* Long count for fb rate */
148 
149 #define APHY_CWMIN			15
150 #define PHY_CWMAX			1023
151 
152 #define EDCF_AIFSN_MIN			1
153 
154 #define FRAGNUM_MASK			0xF
155 
156 #define APHY_SLOT_TIME			9
157 #define BPHY_SLOT_TIME			20
158 
159 #define WL_SPURAVOID_OFF		0
160 #define WL_SPURAVOID_ON1		1
161 #define WL_SPURAVOID_ON2		2
162 
163 /* invalid core flags, use the saved coreflags */
164 #define BRCMS_USE_COREFLAGS		0xffffffff
165 
166 /* values for PLCPHdr_override */
167 #define BRCMS_PLCP_AUTO			-1
168 #define BRCMS_PLCP_SHORT		0
169 #define BRCMS_PLCP_LONG			1
170 
171 /* values for g_protection_override and n_protection_override */
172 #define BRCMS_PROTECTION_AUTO		-1
173 #define BRCMS_PROTECTION_OFF		0
174 #define BRCMS_PROTECTION_ON		1
175 #define BRCMS_PROTECTION_MMHDR_ONLY	2
176 #define BRCMS_PROTECTION_CTS_ONLY	3
177 
178 /* values for g_protection_control and n_protection_control */
179 #define BRCMS_PROTECTION_CTL_OFF	0
180 #define BRCMS_PROTECTION_CTL_LOCAL	1
181 #define BRCMS_PROTECTION_CTL_OVERLAP	2
182 
183 /* values for n_protection */
184 #define BRCMS_N_PROTECTION_OFF		0
185 #define BRCMS_N_PROTECTION_OPTIONAL	1
186 #define BRCMS_N_PROTECTION_20IN40	2
187 #define BRCMS_N_PROTECTION_MIXEDMODE	3
188 
189 /* values for band specific 40MHz capabilities */
190 #define BRCMS_N_BW_20ALL		0
191 #define BRCMS_N_BW_40ALL		1
192 #define BRCMS_N_BW_20IN2G_40IN5G	2
193 
194 /* bitflags for SGI support (sgi_rx iovar) */
195 #define BRCMS_N_SGI_20			0x01
196 #define BRCMS_N_SGI_40			0x02
197 
198 /* defines used by the nrate iovar */
199 /* MSC in use,indicates b0-6 holds an mcs */
200 #define NRATE_MCS_INUSE			0x00000080
201 /* rate/mcs value */
202 #define NRATE_RATE_MASK			0x0000007f
203 /* stf mode mask: siso, cdd, stbc, sdm */
204 #define NRATE_STF_MASK			0x0000ff00
205 /* stf mode shift */
206 #define NRATE_STF_SHIFT			8
207 /* bit indicate to override mcs only */
208 #define NRATE_OVERRIDE_MCS_ONLY		0x40000000
209 #define NRATE_SGI_MASK			0x00800000	/* sgi mode */
210 #define NRATE_SGI_SHIFT			23		/* sgi mode */
211 #define NRATE_LDPC_CODING		0x00400000	/* adv coding in use */
212 #define NRATE_LDPC_SHIFT		22		/* ldpc shift */
213 
214 #define NRATE_STF_SISO			0		/* stf mode SISO */
215 #define NRATE_STF_CDD			1		/* stf mode CDD */
216 #define NRATE_STF_STBC			2		/* stf mode STBC */
217 #define NRATE_STF_SDM			3		/* stf mode SDM */
218 
219 #define MAX_DMA_SEGS			4
220 
221 /* # of entries in Tx FIFO */
222 #define NTXD				64
223 /* Max # of entries in Rx FIFO based on 4kb page size */
224 #define NRXD				256
225 
226 /* Amount of headroom to leave in Tx FIFO */
227 #define TX_HEADROOM			4
228 
229 /* try to keep this # rbufs posted to the chip */
230 #define NRXBUFPOST			32
231 
232 /* max # frames to process in brcms_c_recv() */
233 #define RXBND				8
234 /* max # tx status to process in wlc_txstatus() */
235 #define TXSBND				8
236 
237 /*
238  * The following table lists the buffer memory allocated to xmt fifos in HW.
239  * the size is in units of 256bytes(one block), total size is HW dependent
240  * ucode has default fifo partition, sw can overwrite if necessary
241  *
242  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
243  * the twiki is updated before making changes.
244  */
245 
246 /* Starting corerev for the fifo size table */
247 #define XMTFIFOTBL_STARTREV	17
248 
249 struct d11init {
250 	__le16 addr;
251 	__le16 size;
252 	__le32 value;
253 };
254 
255 struct edcf_acparam {
256 	u8 ACI;
257 	u8 ECW;
258 	u16 TXOP;
259 } __packed;
260 
261 /* debug/trace */
262 uint brcm_msg_level;
263 
264 /* TX FIFO number to WME/802.1E Access Category */
265 static const u8 wme_fifo2ac[] = {
266 	IEEE80211_AC_BK,
267 	IEEE80211_AC_BE,
268 	IEEE80211_AC_VI,
269 	IEEE80211_AC_VO,
270 	IEEE80211_AC_BE,
271 	IEEE80211_AC_BE
272 };
273 
274 /* ieee80211 Access Category to TX FIFO number */
275 static const u8 wme_ac2fifo[] = {
276 	TX_AC_VO_FIFO,
277 	TX_AC_VI_FIFO,
278 	TX_AC_BE_FIFO,
279 	TX_AC_BK_FIFO
280 };
281 
282 static const u16 xmtfifo_sz[][NFIFO] = {
283 	/* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
284 	{20, 192, 192, 21, 17, 5},
285 	/* corerev 18: */
286 	{0, 0, 0, 0, 0, 0},
287 	/* corerev 19: */
288 	{0, 0, 0, 0, 0, 0},
289 	/* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
290 	{20, 192, 192, 21, 17, 5},
291 	/* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
292 	{9, 58, 22, 14, 14, 5},
293 	/* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
294 	{20, 192, 192, 21, 17, 5},
295 	/* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
296 	{20, 192, 192, 21, 17, 5},
297 	/* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
298 	{9, 58, 22, 14, 14, 5},
299 	/* corerev 25: */
300 	{0, 0, 0, 0, 0, 0},
301 	/* corerev 26: */
302 	{0, 0, 0, 0, 0, 0},
303 	/* corerev 27: */
304 	{0, 0, 0, 0, 0, 0},
305 	/* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
306 	{9, 58, 22, 14, 14, 5},
307 };
308 
309 #ifdef DEBUG
310 static const char * const fifo_names[] = {
311 	"AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
312 #else
313 static const char fifo_names[6][1];
314 #endif
315 
316 #ifdef DEBUG
317 /* pointer to most recently allocated wl/wlc */
318 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
319 #endif
320 
321 /* Mapping of ieee80211 AC numbers to tx fifos */
322 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
323 	[IEEE80211_AC_VO]	= TX_AC_VO_FIFO,
324 	[IEEE80211_AC_VI]	= TX_AC_VI_FIFO,
325 	[IEEE80211_AC_BE]	= TX_AC_BE_FIFO,
326 	[IEEE80211_AC_BK]	= TX_AC_BK_FIFO,
327 };
328 
329 /* Mapping of tx fifos to ieee80211 AC numbers */
330 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
331 	[TX_AC_BK_FIFO]	= IEEE80211_AC_BK,
332 	[TX_AC_BE_FIFO]	= IEEE80211_AC_BE,
333 	[TX_AC_VI_FIFO]	= IEEE80211_AC_VI,
334 	[TX_AC_VO_FIFO]	= IEEE80211_AC_VO,
335 };
336 
brcms_ac_to_fifo(u8 ac)337 static u8 brcms_ac_to_fifo(u8 ac)
338 {
339 	if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
340 		return TX_AC_BE_FIFO;
341 	return ac_to_fifo_mapping[ac];
342 }
343 
brcms_fifo_to_ac(u8 fifo)344 static u8 brcms_fifo_to_ac(u8 fifo)
345 {
346 	if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
347 		return IEEE80211_AC_BE;
348 	return fifo_to_ac_mapping[fifo];
349 }
350 
351 /* Find basic rate for a given rate */
brcms_basic_rate(struct brcms_c_info * wlc,u32 rspec)352 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
353 {
354 	if (is_mcs_rate(rspec))
355 		return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
356 		       .leg_ofdm];
357 	return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
358 }
359 
frametype(u32 rspec,u8 mimoframe)360 static u16 frametype(u32 rspec, u8 mimoframe)
361 {
362 	if (is_mcs_rate(rspec))
363 		return mimoframe;
364 	return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
365 }
366 
367 /* currently the best mechanism for determining SIFS is the band in use */
get_sifs(struct brcms_band * band)368 static u16 get_sifs(struct brcms_band *band)
369 {
370 	return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
371 				 BPHY_SIFS_TIME;
372 }
373 
374 /*
375  * Detect Card removed.
376  * Even checking an sbconfig register read will not false trigger when the core
377  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
378  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
379  * reg with fixed 0/1 pattern (some platforms return all 0).
380  * If clocks are present, call the sb routine which will figure out if the
381  * device is removed.
382  */
brcms_deviceremoved(struct brcms_c_info * wlc)383 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
384 {
385 	u32 macctrl;
386 
387 	if (!wlc->hw->clk)
388 		return ai_deviceremoved(wlc->hw->sih);
389 	macctrl = bcma_read32(wlc->hw->d11core,
390 			      D11REGOFFS(maccontrol));
391 	return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
392 }
393 
394 /* sum the individual fifo tx pending packet counts */
brcms_txpktpendtot(struct brcms_c_info * wlc)395 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
396 {
397 	int i;
398 	int pending = 0;
399 
400 	for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
401 		if (wlc->hw->di[i])
402 			pending += dma_txpending(wlc->hw->di[i]);
403 	return pending;
404 }
405 
brcms_is_mband_unlocked(struct brcms_c_info * wlc)406 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
407 {
408 	return wlc->pub->_nbands > 1 && !wlc->bandlocked;
409 }
410 
brcms_chspec_bw(u16 chanspec)411 static int brcms_chspec_bw(u16 chanspec)
412 {
413 	if (CHSPEC_IS40(chanspec))
414 		return BRCMS_40_MHZ;
415 	if (CHSPEC_IS20(chanspec))
416 		return BRCMS_20_MHZ;
417 
418 	return BRCMS_10_MHZ;
419 }
420 
brcms_c_bsscfg_mfree(struct brcms_bss_cfg * cfg)421 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
422 {
423 	if (cfg == NULL)
424 		return;
425 
426 	kfree(cfg->current_bss);
427 	kfree(cfg);
428 }
429 
brcms_c_detach_mfree(struct brcms_c_info * wlc)430 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
431 {
432 	if (wlc == NULL)
433 		return;
434 
435 	brcms_c_bsscfg_mfree(wlc->bsscfg);
436 	kfree(wlc->pub);
437 	kfree(wlc->modulecb);
438 	kfree(wlc->default_bss);
439 	kfree(wlc->protection);
440 	kfree(wlc->stf);
441 	kfree(wlc->bandstate[0]);
442 	if (wlc->corestate)
443 		kfree(wlc->corestate->macstat_snapshot);
444 	kfree(wlc->corestate);
445 	if (wlc->hw)
446 		kfree(wlc->hw->bandstate[0]);
447 	kfree(wlc->hw);
448 	if (wlc->beacon)
449 		dev_kfree_skb_any(wlc->beacon);
450 	if (wlc->probe_resp)
451 		dev_kfree_skb_any(wlc->probe_resp);
452 
453 	kfree(wlc);
454 }
455 
brcms_c_bsscfg_malloc(uint unit)456 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
457 {
458 	struct brcms_bss_cfg *cfg;
459 
460 	cfg = kzalloc(sizeof(*cfg), GFP_ATOMIC);
461 	if (cfg == NULL)
462 		goto fail;
463 
464 	cfg->current_bss = kzalloc(sizeof(*cfg->current_bss), GFP_ATOMIC);
465 	if (cfg->current_bss == NULL)
466 		goto fail;
467 
468 	return cfg;
469 
470  fail:
471 	brcms_c_bsscfg_mfree(cfg);
472 	return NULL;
473 }
474 
475 static struct brcms_c_info *
brcms_c_attach_malloc(uint unit,uint * err,uint devid)476 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
477 {
478 	struct brcms_c_info *wlc;
479 
480 	wlc = kzalloc(sizeof(*wlc), GFP_ATOMIC);
481 	if (wlc == NULL) {
482 		*err = 1002;
483 		goto fail;
484 	}
485 
486 	/* allocate struct brcms_c_pub state structure */
487 	wlc->pub = kzalloc(sizeof(*wlc->pub), GFP_ATOMIC);
488 	if (wlc->pub == NULL) {
489 		*err = 1003;
490 		goto fail;
491 	}
492 	wlc->pub->wlc = wlc;
493 
494 	/* allocate struct brcms_hardware state structure */
495 
496 	wlc->hw = kzalloc(sizeof(*wlc->hw), GFP_ATOMIC);
497 	if (wlc->hw == NULL) {
498 		*err = 1005;
499 		goto fail;
500 	}
501 	wlc->hw->wlc = wlc;
502 
503 	wlc->hw->bandstate[0] =
504 		kcalloc(MAXBANDS, sizeof(struct brcms_hw_band), GFP_ATOMIC);
505 	if (wlc->hw->bandstate[0] == NULL) {
506 		*err = 1006;
507 		goto fail;
508 	} else {
509 		int i;
510 
511 		for (i = 1; i < MAXBANDS; i++)
512 			wlc->hw->bandstate[i] = (struct brcms_hw_band *)
513 			    ((unsigned long)wlc->hw->bandstate[0] +
514 			     (sizeof(struct brcms_hw_band) * i));
515 	}
516 
517 	wlc->modulecb =
518 		kcalloc(BRCMS_MAXMODULES, sizeof(struct modulecb),
519 			GFP_ATOMIC);
520 	if (wlc->modulecb == NULL) {
521 		*err = 1009;
522 		goto fail;
523 	}
524 
525 	wlc->default_bss = kzalloc(sizeof(*wlc->default_bss), GFP_ATOMIC);
526 	if (wlc->default_bss == NULL) {
527 		*err = 1010;
528 		goto fail;
529 	}
530 
531 	wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
532 	if (wlc->bsscfg == NULL) {
533 		*err = 1011;
534 		goto fail;
535 	}
536 
537 	wlc->protection = kzalloc(sizeof(*wlc->protection), GFP_ATOMIC);
538 	if (wlc->protection == NULL) {
539 		*err = 1016;
540 		goto fail;
541 	}
542 
543 	wlc->stf = kzalloc(sizeof(*wlc->stf), GFP_ATOMIC);
544 	if (wlc->stf == NULL) {
545 		*err = 1017;
546 		goto fail;
547 	}
548 
549 	wlc->bandstate[0] =
550 		kcalloc(MAXBANDS, sizeof(*wlc->bandstate[0]), GFP_ATOMIC);
551 	if (wlc->bandstate[0] == NULL) {
552 		*err = 1025;
553 		goto fail;
554 	} else {
555 		int i;
556 
557 		for (i = 1; i < MAXBANDS; i++)
558 			wlc->bandstate[i] = (struct brcms_band *)
559 				((unsigned long)wlc->bandstate[0]
560 				+ (sizeof(struct brcms_band)*i));
561 	}
562 
563 	wlc->corestate = kzalloc(sizeof(*wlc->corestate), GFP_ATOMIC);
564 	if (wlc->corestate == NULL) {
565 		*err = 1026;
566 		goto fail;
567 	}
568 
569 	wlc->corestate->macstat_snapshot =
570 		kzalloc(sizeof(*wlc->corestate->macstat_snapshot), GFP_ATOMIC);
571 	if (wlc->corestate->macstat_snapshot == NULL) {
572 		*err = 1027;
573 		goto fail;
574 	}
575 
576 	return wlc;
577 
578  fail:
579 	brcms_c_detach_mfree(wlc);
580 	return NULL;
581 }
582 
583 /*
584  * Update the slot timing for standard 11b/g (20us slots)
585  * or shortslot 11g (9us slots)
586  * The PSM needs to be suspended for this call.
587  */
brcms_b_update_slot_timing(struct brcms_hardware * wlc_hw,bool shortslot)588 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
589 					bool shortslot)
590 {
591 	struct bcma_device *core = wlc_hw->d11core;
592 
593 	if (shortslot) {
594 		/* 11g short slot: 11a timing */
595 		bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
596 		brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
597 	} else {
598 		/* 11g long slot: 11b timing */
599 		bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
600 		brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
601 	}
602 }
603 
604 /*
605  * calculate frame duration of a given rate and length, return
606  * time in usec unit
607  */
brcms_c_calc_frame_time(struct brcms_c_info * wlc,u32 ratespec,u8 preamble_type,uint mac_len)608 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
609 				    u8 preamble_type, uint mac_len)
610 {
611 	uint nsyms, dur = 0, Ndps, kNdps;
612 	uint rate = rspec2rate(ratespec);
613 
614 	if (rate == 0) {
615 		brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
616 			  wlc->pub->unit);
617 		rate = BRCM_RATE_1M;
618 	}
619 
620 	if (is_mcs_rate(ratespec)) {
621 		uint mcs = ratespec & RSPEC_RATE_MASK;
622 		int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
623 
624 		dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
625 		if (preamble_type == BRCMS_MM_PREAMBLE)
626 			dur += PREN_MM_EXT;
627 		/* 1000Ndbps = kbps * 4 */
628 		kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
629 				   rspec_issgi(ratespec)) * 4;
630 
631 		if (rspec_stc(ratespec) == 0)
632 			nsyms =
633 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
634 				  APHY_TAIL_NBITS) * 1000, kNdps);
635 		else
636 			/* STBC needs to have even number of symbols */
637 			nsyms =
638 			    2 *
639 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
640 				  APHY_TAIL_NBITS) * 1000, 2 * kNdps);
641 
642 		dur += APHY_SYMBOL_TIME * nsyms;
643 		if (wlc->band->bandtype == BRCM_BAND_2G)
644 			dur += DOT11_OFDM_SIGNAL_EXTENSION;
645 	} else if (is_ofdm_rate(rate)) {
646 		dur = APHY_PREAMBLE_TIME;
647 		dur += APHY_SIGNAL_TIME;
648 		/* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
649 		Ndps = rate * 2;
650 		/* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
651 		nsyms =
652 		    CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
653 			 Ndps);
654 		dur += APHY_SYMBOL_TIME * nsyms;
655 		if (wlc->band->bandtype == BRCM_BAND_2G)
656 			dur += DOT11_OFDM_SIGNAL_EXTENSION;
657 	} else {
658 		/*
659 		 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
660 		 * will divide out
661 		 */
662 		mac_len = mac_len * 8 * 2;
663 		/* calc ceiling of bits/rate = microseconds of air time */
664 		dur = (mac_len + rate - 1) / rate;
665 		if (preamble_type & BRCMS_SHORT_PREAMBLE)
666 			dur += BPHY_PLCP_SHORT_TIME;
667 		else
668 			dur += BPHY_PLCP_TIME;
669 	}
670 	return dur;
671 }
672 
brcms_c_write_inits(struct brcms_hardware * wlc_hw,const struct d11init * inits)673 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
674 				const struct d11init *inits)
675 {
676 	struct bcma_device *core = wlc_hw->d11core;
677 	int i;
678 	uint offset;
679 	u16 size;
680 	u32 value;
681 
682 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
683 
684 	for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
685 		size = le16_to_cpu(inits[i].size);
686 		offset = le16_to_cpu(inits[i].addr);
687 		value = le32_to_cpu(inits[i].value);
688 		if (size == 2)
689 			bcma_write16(core, offset, value);
690 		else if (size == 4)
691 			bcma_write32(core, offset, value);
692 		else
693 			break;
694 	}
695 }
696 
brcms_c_write_mhf(struct brcms_hardware * wlc_hw,u16 * mhfs)697 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
698 {
699 	u8 idx;
700 	static const u16 addr[] = {
701 		M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
702 		M_HOST_FLAGS5
703 	};
704 
705 	for (idx = 0; idx < MHFMAX; idx++)
706 		brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
707 }
708 
brcms_c_ucode_bsinit(struct brcms_hardware * wlc_hw)709 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
710 {
711 	struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
712 
713 	/* init microcode host flags */
714 	brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
715 
716 	/* do band-specific ucode IHR, SHM, and SCR inits */
717 	if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
718 		if (BRCMS_ISNPHY(wlc_hw->band))
719 			brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
720 		else
721 			brcms_err(wlc_hw->d11core,
722 				  "%s: wl%d: unsupported phy in corerev %d\n",
723 				  __func__, wlc_hw->unit,
724 				  wlc_hw->corerev);
725 	} else {
726 		if (D11REV_IS(wlc_hw->corerev, 24)) {
727 			if (BRCMS_ISLCNPHY(wlc_hw->band))
728 				brcms_c_write_inits(wlc_hw,
729 						    ucode->d11lcn0bsinitvals24);
730 			else
731 				brcms_err(wlc_hw->d11core,
732 					  "%s: wl%d: unsupported phy in core rev %d\n",
733 					  __func__, wlc_hw->unit,
734 					  wlc_hw->corerev);
735 		} else {
736 			brcms_err(wlc_hw->d11core,
737 				  "%s: wl%d: unsupported corerev %d\n",
738 				  __func__, wlc_hw->unit, wlc_hw->corerev);
739 		}
740 	}
741 }
742 
brcms_b_core_ioctl(struct brcms_hardware * wlc_hw,u32 m,u32 v)743 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
744 {
745 	struct bcma_device *core = wlc_hw->d11core;
746 	u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
747 
748 	bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
749 }
750 
brcms_b_core_phy_clk(struct brcms_hardware * wlc_hw,bool clk)751 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
752 {
753 	brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
754 
755 	wlc_hw->phyclk = clk;
756 
757 	if (OFF == clk) {	/* clear gmode bit, put phy into reset */
758 
759 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
760 				   (SICF_PRST | SICF_FGC));
761 		udelay(1);
762 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
763 		udelay(1);
764 
765 	} else {		/* take phy out of reset */
766 
767 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
768 		udelay(1);
769 		brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
770 		udelay(1);
771 
772 	}
773 }
774 
775 /* low-level band switch utility routine */
brcms_c_setxband(struct brcms_hardware * wlc_hw,uint bandunit)776 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
777 {
778 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
779 			   bandunit);
780 
781 	wlc_hw->band = wlc_hw->bandstate[bandunit];
782 
783 	/*
784 	 * BMAC_NOTE:
785 	 *   until we eliminate need for wlc->band refs in low level code
786 	 */
787 	wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
788 
789 	/* set gmode core flag */
790 	if (wlc_hw->sbclk && !wlc_hw->noreset) {
791 		u32 gmode = 0;
792 
793 		if (bandunit == 0)
794 			gmode = SICF_GMODE;
795 
796 		brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
797 	}
798 }
799 
800 /* switch to new band but leave it inactive */
brcms_c_setband_inact(struct brcms_c_info * wlc,uint bandunit)801 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
802 {
803 	struct brcms_hardware *wlc_hw = wlc->hw;
804 	u32 macintmask;
805 	u32 macctrl;
806 
807 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
808 	macctrl = bcma_read32(wlc_hw->d11core,
809 			      D11REGOFFS(maccontrol));
810 	WARN_ON((macctrl & MCTL_EN_MAC) != 0);
811 
812 	/* disable interrupts */
813 	macintmask = brcms_intrsoff(wlc->wl);
814 
815 	/* radio off */
816 	wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
817 
818 	brcms_b_core_phy_clk(wlc_hw, OFF);
819 
820 	brcms_c_setxband(wlc_hw, bandunit);
821 
822 	return macintmask;
823 }
824 
825 /* process an individual struct tx_status */
826 static bool
brcms_c_dotxstatus(struct brcms_c_info * wlc,struct tx_status * txs)827 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
828 {
829 	struct sk_buff *p = NULL;
830 	uint queue = NFIFO;
831 	struct dma_pub *dma = NULL;
832 	struct d11txh *txh = NULL;
833 	struct scb *scb = NULL;
834 	int tx_frame_count;
835 	uint supr_status;
836 	bool lastframe;
837 	struct ieee80211_hdr *h;
838 	struct ieee80211_tx_info *tx_info;
839 	struct ieee80211_tx_rate *txrate;
840 	int i;
841 	bool fatal = true;
842 
843 	trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
844 			     txs->frameid, txs->status, txs->lasttxtime,
845 			     txs->sequence, txs->phyerr, txs->ackphyrxsh);
846 
847 	/* discard intermediate indications for ucode with one legitimate case:
848 	 *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
849 	 *   but the subsequent tx of DATA failed. so it will start rts/cts
850 	 *   from the beginning (resetting the rts transmission count)
851 	 */
852 	if (!(txs->status & TX_STATUS_AMPDU)
853 	    && (txs->status & TX_STATUS_INTERMEDIATE)) {
854 		brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
855 		fatal = false;
856 		goto out;
857 	}
858 
859 	queue = txs->frameid & TXFID_QUEUE_MASK;
860 	if (queue >= NFIFO) {
861 		brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
862 		goto out;
863 	}
864 
865 	dma = wlc->hw->di[queue];
866 
867 	p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
868 	if (p == NULL) {
869 		brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
870 		goto out;
871 	}
872 
873 	txh = (struct d11txh *) (p->data);
874 
875 	if (txs->phyerr)
876 		brcms_dbg_tx(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
877 			     txs->phyerr, txh->MainRates);
878 
879 	if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
880 		brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
881 		goto out;
882 	}
883 	tx_info = IEEE80211_SKB_CB(p);
884 	h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
885 
886 	if (tx_info->rate_driver_data[0])
887 		scb = &wlc->pri_scb;
888 
889 	if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
890 		brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
891 		fatal = false;
892 		goto out;
893 	}
894 
895 	/*
896 	 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
897 	 * frames; this traces them for the rest.
898 	 */
899 	trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
900 
901 	supr_status = txs->status & TX_STATUS_SUPR_MASK;
902 	if (supr_status == TX_STATUS_SUPR_BADCH) {
903 		unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
904 		brcms_dbg_tx(wlc->hw->d11core,
905 			     "Pkt tx suppressed, dest chan %u, current %d\n",
906 			     (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
907 			     CHSPEC_CHANNEL(wlc->default_bss->chanspec));
908 	}
909 
910 	tx_frame_count =
911 	    (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
912 
913 	lastframe = !ieee80211_has_morefrags(h->frame_control);
914 
915 	if (!lastframe) {
916 		brcms_err(wlc->hw->d11core, "Not last frame!\n");
917 	} else {
918 		/*
919 		 * Set information to be consumed by Minstrel ht.
920 		 *
921 		 * The "fallback limit" is the number of tx attempts a given
922 		 * MPDU is sent at the "primary" rate. Tx attempts beyond that
923 		 * limit are sent at the "secondary" rate.
924 		 * A 'short frame' does not exceed RTS treshold.
925 		 */
926 		u16 sfbl,	/* Short Frame Rate Fallback Limit */
927 		    lfbl,	/* Long Frame Rate Fallback Limit */
928 		    fbl;
929 
930 		if (queue < IEEE80211_NUM_ACS) {
931 			sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
932 				      EDCF_SFB);
933 			lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
934 				      EDCF_LFB);
935 		} else {
936 			sfbl = wlc->SFBL;
937 			lfbl = wlc->LFBL;
938 		}
939 
940 		txrate = tx_info->status.rates;
941 		if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
942 			fbl = lfbl;
943 		else
944 			fbl = sfbl;
945 
946 		ieee80211_tx_info_clear_status(tx_info);
947 
948 		if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
949 			/*
950 			 * rate selection requested a fallback rate
951 			 * and we used it
952 			 */
953 			txrate[0].count = fbl;
954 			txrate[1].count = tx_frame_count - fbl;
955 		} else {
956 			/*
957 			 * rate selection did not request fallback rate, or
958 			 * we didn't need it
959 			 */
960 			txrate[0].count = tx_frame_count;
961 			/*
962 			 * rc80211_minstrel.c:minstrel_tx_status() expects
963 			 * unused rates to be marked with idx = -1
964 			 */
965 			txrate[1].idx = -1;
966 			txrate[1].count = 0;
967 		}
968 
969 		/* clear the rest of the rates */
970 		for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
971 			txrate[i].idx = -1;
972 			txrate[i].count = 0;
973 		}
974 
975 		if (txs->status & TX_STATUS_ACK_RCV)
976 			tx_info->flags |= IEEE80211_TX_STAT_ACK;
977 	}
978 
979 	if (lastframe) {
980 		/* remove PLCP & Broadcom tx descriptor header */
981 		skb_pull(p, D11_PHY_HDR_LEN);
982 		skb_pull(p, D11_TXH_LEN);
983 		ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
984 	} else {
985 		brcms_err(wlc->hw->d11core,
986 			  "%s: Not last frame => not calling tx_status\n",
987 			  __func__);
988 	}
989 
990 	fatal = false;
991 
992  out:
993 	if (fatal) {
994 		if (txh)
995 			trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
996 					   sizeof(*txh));
997 		brcmu_pkt_buf_free_skb(p);
998 	}
999 
1000 	if (dma && queue < NFIFO) {
1001 		u16 ac_queue = brcms_fifo_to_ac(queue);
1002 		if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1003 		    ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1004 			ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1005 		dma_kick_tx(dma);
1006 	}
1007 
1008 	return fatal;
1009 }
1010 
1011 /* process tx completion events in BMAC
1012  * Return true if more tx status need to be processed. false otherwise.
1013  */
1014 static bool
brcms_b_txstatus(struct brcms_hardware * wlc_hw,bool bound,bool * fatal)1015 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1016 {
1017 	struct bcma_device *core;
1018 	struct tx_status txstatus, *txs;
1019 	u32 s1, s2;
1020 	uint n = 0;
1021 	/*
1022 	 * Param 'max_tx_num' indicates max. # tx status to process before
1023 	 * break out.
1024 	 */
1025 	uint max_tx_num = bound ? TXSBND : -1;
1026 
1027 	txs = &txstatus;
1028 	core = wlc_hw->d11core;
1029 	*fatal = false;
1030 
1031 	while (n < max_tx_num) {
1032 		s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1033 		if (s1 == 0xffffffff) {
1034 			brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1035 				  __func__);
1036 			*fatal = true;
1037 			return false;
1038 		}
1039 		/* only process when valid */
1040 		if (!(s1 & TXS_V))
1041 			break;
1042 
1043 		s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1044 		txs->status = s1 & TXS_STATUS_MASK;
1045 		txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1046 		txs->sequence = s2 & TXS_SEQ_MASK;
1047 		txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1048 		txs->lasttxtime = 0;
1049 
1050 		*fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1051 		if (*fatal)
1052 			return false;
1053 		n++;
1054 	}
1055 
1056 	return n >= max_tx_num;
1057 }
1058 
brcms_c_tbtt(struct brcms_c_info * wlc)1059 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1060 {
1061 	if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
1062 		/*
1063 		 * DirFrmQ is now valid...defer setting until end
1064 		 * of ATIM window
1065 		 */
1066 		wlc->qvalid |= MCMD_DIRFRMQVAL;
1067 }
1068 
1069 /* set initial host flags value */
1070 static void
brcms_c_mhfdef(struct brcms_c_info * wlc,u16 * mhfs,u16 mhf2_init)1071 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1072 {
1073 	struct brcms_hardware *wlc_hw = wlc->hw;
1074 
1075 	memset(mhfs, 0, MHFMAX * sizeof(u16));
1076 
1077 	mhfs[MHF2] |= mhf2_init;
1078 
1079 	/* prohibit use of slowclock on multifunction boards */
1080 	if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1081 		mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1082 
1083 	if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1084 		mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1085 		mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1086 	}
1087 }
1088 
1089 static uint
dmareg(uint direction,uint fifonum)1090 dmareg(uint direction, uint fifonum)
1091 {
1092 	if (direction == DMA_TX)
1093 		return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1094 	return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1095 }
1096 
brcms_b_attach_dmapio(struct brcms_c_info * wlc,uint j,bool wme)1097 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1098 {
1099 	uint i;
1100 	char name[8];
1101 	/*
1102 	 * ucode host flag 2 needed for pio mode, independent of band and fifo
1103 	 */
1104 	u16 pio_mhf2 = 0;
1105 	struct brcms_hardware *wlc_hw = wlc->hw;
1106 	uint unit = wlc_hw->unit;
1107 
1108 	/* name and offsets for dma_attach */
1109 	snprintf(name, sizeof(name), "wl%d", unit);
1110 
1111 	if (wlc_hw->di[0] == NULL) {	/* Init FIFOs */
1112 		int dma_attach_err = 0;
1113 
1114 		/*
1115 		 * FIFO 0
1116 		 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1117 		 * RX: RX_FIFO (RX data packets)
1118 		 */
1119 		wlc_hw->di[0] = dma_attach(name, wlc,
1120 					   (wme ? dmareg(DMA_TX, 0) : 0),
1121 					   dmareg(DMA_RX, 0),
1122 					   (wme ? NTXD : 0), NRXD,
1123 					   RXBUFSZ, -1, NRXBUFPOST,
1124 					   BRCMS_HWRXOFF);
1125 		dma_attach_err |= (NULL == wlc_hw->di[0]);
1126 
1127 		/*
1128 		 * FIFO 1
1129 		 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1130 		 *   (legacy) TX_DATA_FIFO (TX data packets)
1131 		 * RX: UNUSED
1132 		 */
1133 		wlc_hw->di[1] = dma_attach(name, wlc,
1134 					   dmareg(DMA_TX, 1), 0,
1135 					   NTXD, 0, 0, -1, 0, 0);
1136 		dma_attach_err |= (NULL == wlc_hw->di[1]);
1137 
1138 		/*
1139 		 * FIFO 2
1140 		 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1141 		 * RX: UNUSED
1142 		 */
1143 		wlc_hw->di[2] = dma_attach(name, wlc,
1144 					   dmareg(DMA_TX, 2), 0,
1145 					   NTXD, 0, 0, -1, 0, 0);
1146 		dma_attach_err |= (NULL == wlc_hw->di[2]);
1147 		/*
1148 		 * FIFO 3
1149 		 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1150 		 *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1151 		 */
1152 		wlc_hw->di[3] = dma_attach(name, wlc,
1153 					   dmareg(DMA_TX, 3),
1154 					   0, NTXD, 0, 0, -1,
1155 					   0, 0);
1156 		dma_attach_err |= (NULL == wlc_hw->di[3]);
1157 /* Cleaner to leave this as if with AP defined */
1158 
1159 		if (dma_attach_err) {
1160 			brcms_err(wlc_hw->d11core,
1161 				  "wl%d: wlc_attach: dma_attach failed\n",
1162 				  unit);
1163 			return false;
1164 		}
1165 
1166 		/* get pointer to dma engine tx flow control variable */
1167 		for (i = 0; i < NFIFO; i++)
1168 			if (wlc_hw->di[i])
1169 				wlc_hw->txavail[i] =
1170 				    (uint *) dma_getvar(wlc_hw->di[i],
1171 							"&txavail");
1172 	}
1173 
1174 	/* initial ucode host flags */
1175 	brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1176 
1177 	return true;
1178 }
1179 
brcms_b_detach_dmapio(struct brcms_hardware * wlc_hw)1180 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1181 {
1182 	uint j;
1183 
1184 	for (j = 0; j < NFIFO; j++) {
1185 		if (wlc_hw->di[j]) {
1186 			dma_detach(wlc_hw->di[j]);
1187 			wlc_hw->di[j] = NULL;
1188 		}
1189 	}
1190 }
1191 
1192 /*
1193  * Initialize brcms_c_info default values ...
1194  * may get overrides later in this function
1195  *  BMAC_NOTES, move low out and resolve the dangling ones
1196  */
brcms_b_info_init(struct brcms_hardware * wlc_hw)1197 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1198 {
1199 	struct brcms_c_info *wlc = wlc_hw->wlc;
1200 
1201 	/* set default sw macintmask value */
1202 	wlc->defmacintmask = DEF_MACINTMASK;
1203 
1204 	/* various 802.11g modes */
1205 	wlc_hw->shortslot = false;
1206 
1207 	wlc_hw->SFBL = RETRY_SHORT_FB;
1208 	wlc_hw->LFBL = RETRY_LONG_FB;
1209 
1210 	/* default mac retry limits */
1211 	wlc_hw->SRL = RETRY_SHORT_DEF;
1212 	wlc_hw->LRL = RETRY_LONG_DEF;
1213 	wlc_hw->chanspec = ch20mhz_chspec(1);
1214 }
1215 
brcms_b_wait_for_wake(struct brcms_hardware * wlc_hw)1216 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1217 {
1218 	/* delay before first read of ucode state */
1219 	udelay(40);
1220 
1221 	/* wait until ucode is no longer asleep */
1222 	SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1223 		  DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1224 }
1225 
1226 /* control chip clock to save power, enable dynamic clock or force fast clock */
brcms_b_clkctl_clk(struct brcms_hardware * wlc_hw,enum bcma_clkmode mode)1227 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1228 {
1229 	if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1230 		/* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1231 		 * on backplane, but mac core will still run on ALP(not HT) when
1232 		 * it enters powersave mode, which means the FCA bit may not be
1233 		 * set. Should wakeup mac if driver wants it to run on HT.
1234 		 */
1235 
1236 		if (wlc_hw->clk) {
1237 			if (mode == BCMA_CLKMODE_FAST) {
1238 				bcma_set32(wlc_hw->d11core,
1239 					   D11REGOFFS(clk_ctl_st),
1240 					   CCS_FORCEHT);
1241 
1242 				udelay(64);
1243 
1244 				SPINWAIT(
1245 				    ((bcma_read32(wlc_hw->d11core,
1246 				      D11REGOFFS(clk_ctl_st)) &
1247 				      CCS_HTAVAIL) == 0),
1248 				      PMU_MAX_TRANSITION_DLY);
1249 				WARN_ON(!(bcma_read32(wlc_hw->d11core,
1250 					D11REGOFFS(clk_ctl_st)) &
1251 					CCS_HTAVAIL));
1252 			} else {
1253 				if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1254 				    (bcma_read32(wlc_hw->d11core,
1255 					D11REGOFFS(clk_ctl_st)) &
1256 					(CCS_FORCEHT | CCS_HTAREQ)))
1257 					SPINWAIT(
1258 					    ((bcma_read32(wlc_hw->d11core,
1259 					      offsetof(struct d11regs,
1260 						       clk_ctl_st)) &
1261 					      CCS_HTAVAIL) == 0),
1262 					      PMU_MAX_TRANSITION_DLY);
1263 				bcma_mask32(wlc_hw->d11core,
1264 					D11REGOFFS(clk_ctl_st),
1265 					~CCS_FORCEHT);
1266 			}
1267 		}
1268 		wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1269 	} else {
1270 
1271 		/* old chips w/o PMU, force HT through cc,
1272 		 * then use FCA to verify mac is running fast clock
1273 		 */
1274 
1275 		wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1276 
1277 		/* check fast clock is available (if core is not in reset) */
1278 		if (wlc_hw->forcefastclk && wlc_hw->clk)
1279 			WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1280 				  SISF_FCLKA));
1281 
1282 		/*
1283 		 * keep the ucode wake bit on if forcefastclk is on since we
1284 		 * do not want ucode to put us back to slow clock when it dozes
1285 		 * for PM mode. Code below matches the wake override bit with
1286 		 * current forcefastclk state. Only setting bit in wake_override
1287 		 * instead of waking ucode immediately since old code had this
1288 		 * behavior. Older code set wlc->forcefastclk but only had the
1289 		 * wake happen if the wakup_ucode work (protected by an up
1290 		 * check) was executed just below.
1291 		 */
1292 		if (wlc_hw->forcefastclk)
1293 			mboolset(wlc_hw->wake_override,
1294 				 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1295 		else
1296 			mboolclr(wlc_hw->wake_override,
1297 				 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1298 	}
1299 }
1300 
1301 /* set or clear ucode host flag bits
1302  * it has an optimization for no-change write
1303  * it only writes through shared memory when the core has clock;
1304  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1305  *
1306  *
1307  * bands values are: BRCM_BAND_AUTO <--- Current band only
1308  *                   BRCM_BAND_5G   <--- 5G band only
1309  *                   BRCM_BAND_2G   <--- 2G band only
1310  *                   BRCM_BAND_ALL  <--- All bands
1311  */
1312 void
brcms_b_mhf(struct brcms_hardware * wlc_hw,u8 idx,u16 mask,u16 val,int bands)1313 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1314 	     int bands)
1315 {
1316 	u16 save;
1317 	u16 addr[MHFMAX] = {
1318 		M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1319 		M_HOST_FLAGS5
1320 	};
1321 	struct brcms_hw_band *band;
1322 
1323 	if ((val & ~mask) || idx >= MHFMAX)
1324 		return; /* error condition */
1325 
1326 	switch (bands) {
1327 		/* Current band only or all bands,
1328 		 * then set the band to current band
1329 		 */
1330 	case BRCM_BAND_AUTO:
1331 	case BRCM_BAND_ALL:
1332 		band = wlc_hw->band;
1333 		break;
1334 	case BRCM_BAND_5G:
1335 		band = wlc_hw->bandstate[BAND_5G_INDEX];
1336 		break;
1337 	case BRCM_BAND_2G:
1338 		band = wlc_hw->bandstate[BAND_2G_INDEX];
1339 		break;
1340 	default:
1341 		band = NULL;	/* error condition */
1342 	}
1343 
1344 	if (band) {
1345 		save = band->mhfs[idx];
1346 		band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1347 
1348 		/* optimization: only write through if changed, and
1349 		 * changed band is the current band
1350 		 */
1351 		if (wlc_hw->clk && (band->mhfs[idx] != save)
1352 		    && (band == wlc_hw->band))
1353 			brcms_b_write_shm(wlc_hw, addr[idx],
1354 					   (u16) band->mhfs[idx]);
1355 	}
1356 
1357 	if (bands == BRCM_BAND_ALL) {
1358 		wlc_hw->bandstate[0]->mhfs[idx] =
1359 		    (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1360 		wlc_hw->bandstate[1]->mhfs[idx] =
1361 		    (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1362 	}
1363 }
1364 
1365 /* set the maccontrol register to desired reset state and
1366  * initialize the sw cache of the register
1367  */
brcms_c_mctrl_reset(struct brcms_hardware * wlc_hw)1368 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1369 {
1370 	/* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1371 	wlc_hw->maccontrol = 0;
1372 	wlc_hw->suspended_fifos = 0;
1373 	wlc_hw->wake_override = 0;
1374 	wlc_hw->mute_override = 0;
1375 	brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1376 }
1377 
1378 /*
1379  * write the software state of maccontrol and
1380  * overrides to the maccontrol register
1381  */
brcms_c_mctrl_write(struct brcms_hardware * wlc_hw)1382 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1383 {
1384 	u32 maccontrol = wlc_hw->maccontrol;
1385 
1386 	/* OR in the wake bit if overridden */
1387 	if (wlc_hw->wake_override)
1388 		maccontrol |= MCTL_WAKE;
1389 
1390 	/* set AP and INFRA bits for mute if needed */
1391 	if (wlc_hw->mute_override) {
1392 		maccontrol &= ~(MCTL_AP);
1393 		maccontrol |= MCTL_INFRA;
1394 	}
1395 
1396 	bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1397 		     maccontrol);
1398 }
1399 
1400 /* set or clear maccontrol bits */
brcms_b_mctrl(struct brcms_hardware * wlc_hw,u32 mask,u32 val)1401 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1402 {
1403 	u32 maccontrol;
1404 	u32 new_maccontrol;
1405 
1406 	if (val & ~mask)
1407 		return; /* error condition */
1408 	maccontrol = wlc_hw->maccontrol;
1409 	new_maccontrol = (maccontrol & ~mask) | val;
1410 
1411 	/* if the new maccontrol value is the same as the old, nothing to do */
1412 	if (new_maccontrol == maccontrol)
1413 		return;
1414 
1415 	/* something changed, cache the new value */
1416 	wlc_hw->maccontrol = new_maccontrol;
1417 
1418 	/* write the new values with overrides applied */
1419 	brcms_c_mctrl_write(wlc_hw);
1420 }
1421 
brcms_c_ucode_wake_override_set(struct brcms_hardware * wlc_hw,u32 override_bit)1422 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1423 				 u32 override_bit)
1424 {
1425 	if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1426 		mboolset(wlc_hw->wake_override, override_bit);
1427 		return;
1428 	}
1429 
1430 	mboolset(wlc_hw->wake_override, override_bit);
1431 
1432 	brcms_c_mctrl_write(wlc_hw);
1433 	brcms_b_wait_for_wake(wlc_hw);
1434 }
1435 
brcms_c_ucode_wake_override_clear(struct brcms_hardware * wlc_hw,u32 override_bit)1436 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1437 				   u32 override_bit)
1438 {
1439 	mboolclr(wlc_hw->wake_override, override_bit);
1440 
1441 	if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1442 		return;
1443 
1444 	brcms_c_mctrl_write(wlc_hw);
1445 }
1446 
1447 /* When driver needs ucode to stop beaconing, it has to make sure that
1448  * MCTL_AP is clear and MCTL_INFRA is set
1449  * Mode           MCTL_AP        MCTL_INFRA
1450  * AP                1              1
1451  * STA               0              1 <--- This will ensure no beacons
1452  * IBSS              0              0
1453  */
brcms_c_ucode_mute_override_set(struct brcms_hardware * wlc_hw)1454 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1455 {
1456 	wlc_hw->mute_override = 1;
1457 
1458 	/* if maccontrol already has AP == 0 and INFRA == 1 without this
1459 	 * override, then there is no change to write
1460 	 */
1461 	if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1462 		return;
1463 
1464 	brcms_c_mctrl_write(wlc_hw);
1465 }
1466 
1467 /* Clear the override on AP and INFRA bits */
brcms_c_ucode_mute_override_clear(struct brcms_hardware * wlc_hw)1468 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1469 {
1470 	if (wlc_hw->mute_override == 0)
1471 		return;
1472 
1473 	wlc_hw->mute_override = 0;
1474 
1475 	/* if maccontrol already has AP == 0 and INFRA == 1 without this
1476 	 * override, then there is no change to write
1477 	 */
1478 	if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1479 		return;
1480 
1481 	brcms_c_mctrl_write(wlc_hw);
1482 }
1483 
1484 /*
1485  * Write a MAC address to the given match reg offset in the RXE match engine.
1486  */
1487 static void
brcms_b_set_addrmatch(struct brcms_hardware * wlc_hw,int match_reg_offset,const u8 * addr)1488 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1489 		       const u8 *addr)
1490 {
1491 	struct bcma_device *core = wlc_hw->d11core;
1492 	u16 mac_l;
1493 	u16 mac_m;
1494 	u16 mac_h;
1495 
1496 	brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1497 
1498 	mac_l = addr[0] | (addr[1] << 8);
1499 	mac_m = addr[2] | (addr[3] << 8);
1500 	mac_h = addr[4] | (addr[5] << 8);
1501 
1502 	/* enter the MAC addr into the RXE match registers */
1503 	bcma_write16(core, D11REGOFFS(rcm_ctl),
1504 		     RCM_INC_DATA | match_reg_offset);
1505 	bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1506 	bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1507 	bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1508 }
1509 
1510 void
brcms_b_write_template_ram(struct brcms_hardware * wlc_hw,int offset,int len,void * buf)1511 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1512 			    void *buf)
1513 {
1514 	struct bcma_device *core = wlc_hw->d11core;
1515 	u32 word;
1516 	__le32 word_le;
1517 	__be32 word_be;
1518 	bool be_bit;
1519 	brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1520 
1521 	bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1522 
1523 	/* if MCTL_BIGEND bit set in mac control register,
1524 	 * the chip swaps data in fifo, as well as data in
1525 	 * template ram
1526 	 */
1527 	be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1528 
1529 	while (len > 0) {
1530 		memcpy(&word, buf, sizeof(u32));
1531 
1532 		if (be_bit) {
1533 			word_be = cpu_to_be32(word);
1534 			word = *(u32 *)&word_be;
1535 		} else {
1536 			word_le = cpu_to_le32(word);
1537 			word = *(u32 *)&word_le;
1538 		}
1539 
1540 		bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1541 
1542 		buf = (u8 *) buf + sizeof(u32);
1543 		len -= sizeof(u32);
1544 	}
1545 }
1546 
brcms_b_set_cwmin(struct brcms_hardware * wlc_hw,u16 newmin)1547 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1548 {
1549 	wlc_hw->band->CWmin = newmin;
1550 
1551 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1552 		     OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1553 	(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1554 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1555 }
1556 
brcms_b_set_cwmax(struct brcms_hardware * wlc_hw,u16 newmax)1557 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1558 {
1559 	wlc_hw->band->CWmax = newmax;
1560 
1561 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1562 		     OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1563 	(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1564 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1565 }
1566 
brcms_b_bw_set(struct brcms_hardware * wlc_hw,u16 bw)1567 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1568 {
1569 	bool fastclk;
1570 
1571 	/* request FAST clock if not on */
1572 	fastclk = wlc_hw->forcefastclk;
1573 	if (!fastclk)
1574 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1575 
1576 	wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1577 
1578 	brcms_b_phy_reset(wlc_hw);
1579 	wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1580 
1581 	/* restore the clk */
1582 	if (!fastclk)
1583 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1584 }
1585 
brcms_b_upd_synthpu(struct brcms_hardware * wlc_hw)1586 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1587 {
1588 	u16 v;
1589 	struct brcms_c_info *wlc = wlc_hw->wlc;
1590 	/* update SYNTHPU_DLY */
1591 
1592 	if (BRCMS_ISLCNPHY(wlc->band))
1593 		v = SYNTHPU_DLY_LPPHY_US;
1594 	else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1595 		v = SYNTHPU_DLY_NPHY_US;
1596 	else
1597 		v = SYNTHPU_DLY_BPHY_US;
1598 
1599 	brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1600 }
1601 
brcms_c_ucode_txant_set(struct brcms_hardware * wlc_hw)1602 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1603 {
1604 	u16 phyctl;
1605 	u16 phytxant = wlc_hw->bmac_phytxant;
1606 	u16 mask = PHY_TXC_ANT_MASK;
1607 
1608 	/* set the Probe Response frame phy control word */
1609 	phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1610 	phyctl = (phyctl & ~mask) | phytxant;
1611 	brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1612 
1613 	/* set the Response (ACK/CTS) frame phy control word */
1614 	phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1615 	phyctl = (phyctl & ~mask) | phytxant;
1616 	brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1617 }
1618 
brcms_b_ofdm_ratetable_offset(struct brcms_hardware * wlc_hw,u8 rate)1619 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1620 					 u8 rate)
1621 {
1622 	uint i;
1623 	u8 plcp_rate = 0;
1624 	struct plcp_signal_rate_lookup {
1625 		u8 rate;
1626 		u8 signal_rate;
1627 	};
1628 	/* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1629 	const struct plcp_signal_rate_lookup rate_lookup[] = {
1630 		{BRCM_RATE_6M, 0xB},
1631 		{BRCM_RATE_9M, 0xF},
1632 		{BRCM_RATE_12M, 0xA},
1633 		{BRCM_RATE_18M, 0xE},
1634 		{BRCM_RATE_24M, 0x9},
1635 		{BRCM_RATE_36M, 0xD},
1636 		{BRCM_RATE_48M, 0x8},
1637 		{BRCM_RATE_54M, 0xC}
1638 	};
1639 
1640 	for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1641 		if (rate == rate_lookup[i].rate) {
1642 			plcp_rate = rate_lookup[i].signal_rate;
1643 			break;
1644 		}
1645 	}
1646 
1647 	/* Find the SHM pointer to the rate table entry by looking in the
1648 	 * Direct-map Table
1649 	 */
1650 	return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1651 }
1652 
brcms_upd_ofdm_pctl1_table(struct brcms_hardware * wlc_hw)1653 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1654 {
1655 	u8 rate;
1656 	u8 rates[8] = {
1657 		BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1658 		BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1659 	};
1660 	u16 entry_ptr;
1661 	u16 pctl1;
1662 	uint i;
1663 
1664 	if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1665 		return;
1666 
1667 	/* walk the phy rate table and update the entries */
1668 	for (i = 0; i < ARRAY_SIZE(rates); i++) {
1669 		rate = rates[i];
1670 
1671 		entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1672 
1673 		/* read the SHM Rate Table entry OFDM PCTL1 values */
1674 		pctl1 =
1675 		    brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1676 
1677 		/* modify the value */
1678 		pctl1 &= ~PHY_TXC1_MODE_MASK;
1679 		pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1680 
1681 		/* Update the SHM Rate Table entry OFDM PCTL1 values */
1682 		brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1683 				   pctl1);
1684 	}
1685 }
1686 
1687 /* band-specific init */
brcms_b_bsinit(struct brcms_c_info * wlc,u16 chanspec)1688 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1689 {
1690 	struct brcms_hardware *wlc_hw = wlc->hw;
1691 
1692 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1693 			   wlc_hw->band->bandunit);
1694 
1695 	brcms_c_ucode_bsinit(wlc_hw);
1696 
1697 	wlc_phy_init(wlc_hw->band->pi, chanspec);
1698 
1699 	brcms_c_ucode_txant_set(wlc_hw);
1700 
1701 	/*
1702 	 * cwmin is band-specific, update hardware
1703 	 * with value for current band
1704 	 */
1705 	brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1706 	brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1707 
1708 	brcms_b_update_slot_timing(wlc_hw,
1709 				   wlc_hw->band->bandtype == BRCM_BAND_5G ?
1710 				   true : wlc_hw->shortslot);
1711 
1712 	/* write phytype and phyvers */
1713 	brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1714 	brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1715 
1716 	/*
1717 	 * initialize the txphyctl1 rate table since
1718 	 * shmem is shared between bands
1719 	 */
1720 	brcms_upd_ofdm_pctl1_table(wlc_hw);
1721 
1722 	brcms_b_upd_synthpu(wlc_hw);
1723 }
1724 
1725 /* Perform a soft reset of the PHY PLL */
brcms_b_core_phypll_reset(struct brcms_hardware * wlc_hw)1726 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1727 {
1728 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1729 		  ~0, 0);
1730 	udelay(1);
1731 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1732 		  0x4, 0);
1733 	udelay(1);
1734 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1735 		  0x4, 4);
1736 	udelay(1);
1737 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1738 		  0x4, 0);
1739 	udelay(1);
1740 }
1741 
1742 /* light way to turn on phy clock without reset for NPHY only
1743  *  refer to brcms_b_core_phy_clk for full version
1744  */
brcms_b_phyclk_fgc(struct brcms_hardware * wlc_hw,bool clk)1745 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1746 {
1747 	/* support(necessary for NPHY and HYPHY) only */
1748 	if (!BRCMS_ISNPHY(wlc_hw->band))
1749 		return;
1750 
1751 	if (ON == clk)
1752 		brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1753 	else
1754 		brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1755 
1756 }
1757 
brcms_b_macphyclk_set(struct brcms_hardware * wlc_hw,bool clk)1758 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1759 {
1760 	if (ON == clk)
1761 		brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1762 	else
1763 		brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1764 }
1765 
brcms_b_phy_reset(struct brcms_hardware * wlc_hw)1766 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1767 {
1768 	struct brcms_phy_pub *pih = wlc_hw->band->pi;
1769 	u32 phy_bw_clkbits;
1770 
1771 	brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1772 
1773 	if (pih == NULL)
1774 		return;
1775 
1776 	phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1777 
1778 	/* Specific reset sequence required for NPHY rev 3 and 4 */
1779 	if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1780 	    NREV_LE(wlc_hw->band->phyrev, 4)) {
1781 		/* Set the PHY bandwidth */
1782 		brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1783 
1784 		udelay(1);
1785 
1786 		/* Perform a soft reset of the PHY PLL */
1787 		brcms_b_core_phypll_reset(wlc_hw);
1788 
1789 		/* reset the PHY */
1790 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1791 				   (SICF_PRST | SICF_PCLKE));
1792 	} else {
1793 		brcms_b_core_ioctl(wlc_hw,
1794 				   (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1795 				   (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1796 	}
1797 
1798 	udelay(2);
1799 	brcms_b_core_phy_clk(wlc_hw, ON);
1800 
1801 	wlc_phy_anacore(pih, ON);
1802 }
1803 
1804 /* switch to and initialize new band */
brcms_b_setband(struct brcms_hardware * wlc_hw,uint bandunit,u16 chanspec)1805 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1806 			    u16 chanspec) {
1807 	struct brcms_c_info *wlc = wlc_hw->wlc;
1808 	u32 macintmask;
1809 
1810 	/* Enable the d11 core before accessing it */
1811 	if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1812 		bcma_core_enable(wlc_hw->d11core, 0);
1813 		brcms_c_mctrl_reset(wlc_hw);
1814 	}
1815 
1816 	macintmask = brcms_c_setband_inact(wlc, bandunit);
1817 
1818 	if (!wlc_hw->up)
1819 		return;
1820 
1821 	brcms_b_core_phy_clk(wlc_hw, ON);
1822 
1823 	/* band-specific initializations */
1824 	brcms_b_bsinit(wlc, chanspec);
1825 
1826 	/*
1827 	 * If there are any pending software interrupt bits,
1828 	 * then replace these with a harmless nonzero value
1829 	 * so brcms_c_dpc() will re-enable interrupts when done.
1830 	 */
1831 	if (wlc->macintstatus)
1832 		wlc->macintstatus = MI_DMAINT;
1833 
1834 	/* restore macintmask */
1835 	brcms_intrsrestore(wlc->wl, macintmask);
1836 
1837 	/* ucode should still be suspended.. */
1838 	WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1839 		 MCTL_EN_MAC) != 0);
1840 }
1841 
brcms_c_isgoodchip(struct brcms_hardware * wlc_hw)1842 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1843 {
1844 
1845 	/* reject unsupported corerev */
1846 	if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1847 		wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1848 			  wlc_hw->corerev);
1849 		return false;
1850 	}
1851 
1852 	return true;
1853 }
1854 
1855 /* Validate some board info parameters */
brcms_c_validboardtype(struct brcms_hardware * wlc_hw)1856 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1857 {
1858 	uint boardrev = wlc_hw->boardrev;
1859 
1860 	/* 4 bits each for board type, major, minor, and tiny version */
1861 	uint brt = (boardrev & 0xf000) >> 12;
1862 	uint b0 = (boardrev & 0xf00) >> 8;
1863 	uint b1 = (boardrev & 0xf0) >> 4;
1864 	uint b2 = boardrev & 0xf;
1865 
1866 	/* voards from other vendors are always considered valid */
1867 	if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1868 		return true;
1869 
1870 	/* do some boardrev sanity checks when boardvendor is Broadcom */
1871 	if (boardrev == 0)
1872 		return false;
1873 
1874 	if (boardrev <= 0xff)
1875 		return true;
1876 
1877 	if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1878 		|| (b2 > 9))
1879 		return false;
1880 
1881 	return true;
1882 }
1883 
brcms_c_get_macaddr(struct brcms_hardware * wlc_hw,u8 etheraddr[ETH_ALEN])1884 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1885 {
1886 	struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1887 
1888 	/* If macaddr exists, use it (Sromrev4, CIS, ...). */
1889 	if (!is_zero_ether_addr(sprom->il0mac)) {
1890 		memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
1891 		return;
1892 	}
1893 
1894 	if (wlc_hw->_nbands > 1)
1895 		memcpy(etheraddr, sprom->et1mac, ETH_ALEN);
1896 	else
1897 		memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
1898 }
1899 
1900 /* power both the pll and external oscillator on/off */
brcms_b_xtal(struct brcms_hardware * wlc_hw,bool want)1901 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1902 {
1903 	brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1904 
1905 	/*
1906 	 * dont power down if plldown is false or
1907 	 * we must poll hw radio disable
1908 	 */
1909 	if (!want && wlc_hw->pllreq)
1910 		return;
1911 
1912 	wlc_hw->sbclk = want;
1913 	if (!wlc_hw->sbclk) {
1914 		wlc_hw->clk = false;
1915 		if (wlc_hw->band && wlc_hw->band->pi)
1916 			wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1917 	}
1918 }
1919 
1920 /*
1921  * Return true if radio is disabled, otherwise false.
1922  * hw radio disable signal is an external pin, users activate it asynchronously
1923  * this function could be called when driver is down and w/o clock
1924  * it operates on different registers depending on corerev and boardflag.
1925  */
brcms_b_radio_read_hwdisabled(struct brcms_hardware * wlc_hw)1926 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1927 {
1928 	bool v, clk, xtal;
1929 	u32 flags = 0;
1930 
1931 	xtal = wlc_hw->sbclk;
1932 	if (!xtal)
1933 		brcms_b_xtal(wlc_hw, ON);
1934 
1935 	/* may need to take core out of reset first */
1936 	clk = wlc_hw->clk;
1937 	if (!clk) {
1938 		/*
1939 		 * mac no longer enables phyclk automatically when driver
1940 		 * accesses phyreg throughput mac. This can be skipped since
1941 		 * only mac reg is accessed below
1942 		 */
1943 		if (D11REV_GE(wlc_hw->corerev, 18))
1944 			flags |= SICF_PCLKE;
1945 
1946 		/*
1947 		 * TODO: test suspend/resume
1948 		 *
1949 		 * AI chip doesn't restore bar0win2 on
1950 		 * hibernation/resume, need sw fixup
1951 		 */
1952 
1953 		bcma_core_enable(wlc_hw->d11core, flags);
1954 		brcms_c_mctrl_reset(wlc_hw);
1955 	}
1956 
1957 	v = ((bcma_read32(wlc_hw->d11core,
1958 			  D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1959 
1960 	/* put core back into reset */
1961 	if (!clk)
1962 		bcma_core_disable(wlc_hw->d11core, 0);
1963 
1964 	if (!xtal)
1965 		brcms_b_xtal(wlc_hw, OFF);
1966 
1967 	return v;
1968 }
1969 
wlc_dma_rxreset(struct brcms_hardware * wlc_hw,uint fifo)1970 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1971 {
1972 	struct dma_pub *di = wlc_hw->di[fifo];
1973 	return dma_rxreset(di);
1974 }
1975 
1976 /* d11 core reset
1977  *   ensure fask clock during reset
1978  *   reset dma
1979  *   reset d11(out of reset)
1980  *   reset phy(out of reset)
1981  *   clear software macintstatus for fresh new start
1982  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1983  */
brcms_b_corereset(struct brcms_hardware * wlc_hw,u32 flags)1984 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1985 {
1986 	uint i;
1987 	bool fastclk;
1988 
1989 	if (flags == BRCMS_USE_COREFLAGS)
1990 		flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
1991 
1992 	brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
1993 
1994 	/* request FAST clock if not on  */
1995 	fastclk = wlc_hw->forcefastclk;
1996 	if (!fastclk)
1997 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1998 
1999 	/* reset the dma engines except first time thru */
2000 	if (bcma_core_is_enabled(wlc_hw->d11core)) {
2001 		for (i = 0; i < NFIFO; i++)
2002 			if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2003 				brcms_err(wlc_hw->d11core, "wl%d: %s: "
2004 					  "dma_txreset[%d]: cannot stop dma\n",
2005 					   wlc_hw->unit, __func__, i);
2006 
2007 		if ((wlc_hw->di[RX_FIFO])
2008 		    && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2009 			brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2010 				  "[%d]: cannot stop dma\n",
2011 				  wlc_hw->unit, __func__, RX_FIFO);
2012 	}
2013 	/* if noreset, just stop the psm and return */
2014 	if (wlc_hw->noreset) {
2015 		wlc_hw->wlc->macintstatus = 0;	/* skip wl_dpc after down */
2016 		brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2017 		return;
2018 	}
2019 
2020 	/*
2021 	 * mac no longer enables phyclk automatically when driver accesses
2022 	 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2023 	 * band->pi is invalid. need to enable PHY CLK
2024 	 */
2025 	if (D11REV_GE(wlc_hw->corerev, 18))
2026 		flags |= SICF_PCLKE;
2027 
2028 	/*
2029 	 * reset the core
2030 	 * In chips with PMU, the fastclk request goes through d11 core
2031 	 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2032 	 *
2033 	 * This adds some delay and we can optimize it by also requesting
2034 	 * fastclk through chipcommon during this period if necessary. But
2035 	 * that has to work coordinate with other driver like mips/arm since
2036 	 * they may touch chipcommon as well.
2037 	 */
2038 	wlc_hw->clk = false;
2039 	bcma_core_enable(wlc_hw->d11core, flags);
2040 	wlc_hw->clk = true;
2041 	if (wlc_hw->band && wlc_hw->band->pi)
2042 		wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2043 
2044 	brcms_c_mctrl_reset(wlc_hw);
2045 
2046 	if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2047 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2048 
2049 	brcms_b_phy_reset(wlc_hw);
2050 
2051 	/* turn on PHY_PLL */
2052 	brcms_b_core_phypll_ctl(wlc_hw, true);
2053 
2054 	/* clear sw intstatus */
2055 	wlc_hw->wlc->macintstatus = 0;
2056 
2057 	/* restore the clk setting */
2058 	if (!fastclk)
2059 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2060 }
2061 
2062 /* txfifo sizes needs to be modified(increased) since the newer cores
2063  * have more memory.
2064  */
brcms_b_corerev_fifofixup(struct brcms_hardware * wlc_hw)2065 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2066 {
2067 	struct bcma_device *core = wlc_hw->d11core;
2068 	u16 fifo_nu;
2069 	u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2070 	u16 txfifo_def, txfifo_def1;
2071 	u16 txfifo_cmd;
2072 
2073 	/* tx fifos start at TXFIFO_START_BLK from the Base address */
2074 	txfifo_startblk = TXFIFO_START_BLK;
2075 
2076 	/* sequence of operations:  reset fifo, set fifo size, reset fifo */
2077 	for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2078 
2079 		txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2080 		txfifo_def = (txfifo_startblk & 0xff) |
2081 		    (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2082 		txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2083 		    ((((txfifo_endblk -
2084 			1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2085 		txfifo_cmd =
2086 		    TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2087 
2088 		bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2089 		bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2090 		bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2091 
2092 		bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2093 
2094 		txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2095 	}
2096 	/*
2097 	 * need to propagate to shm location to be in sync since ucode/hw won't
2098 	 * do this
2099 	 */
2100 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2101 			   wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2102 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2103 			   wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2104 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2105 			   ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2106 			    xmtfifo_sz[TX_AC_BK_FIFO]));
2107 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2108 			   ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2109 			    xmtfifo_sz[TX_BCMC_FIFO]));
2110 }
2111 
2112 /* This function is used for changing the tsf frac register
2113  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2114  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2115  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2116  * HTPHY Formula is 2^26/freq(MHz) e.g.
2117  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2118  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2119  * For spuron: 123MHz -> 2^26/123    = 545600.5
2120  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2121  * For spur off: 120MHz -> 2^26/120    = 559240.5
2122  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2123  */
2124 
brcms_b_switch_macfreq(struct brcms_hardware * wlc_hw,u8 spurmode)2125 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2126 {
2127 	struct bcma_device *core = wlc_hw->d11core;
2128 
2129 	if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2130 	    (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2131 		if (spurmode == WL_SPURAVOID_ON2) {	/* 126Mhz */
2132 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2133 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2134 		} else if (spurmode == WL_SPURAVOID_ON1) {	/* 123Mhz */
2135 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2136 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2137 		} else {	/* 120Mhz */
2138 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2139 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2140 		}
2141 	} else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2142 		if (spurmode == WL_SPURAVOID_ON1) {	/* 82Mhz */
2143 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2144 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2145 		} else {	/* 80Mhz */
2146 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2147 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2148 		}
2149 	}
2150 }
2151 
brcms_c_start_station(struct brcms_c_info * wlc,u8 * addr)2152 void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr)
2153 {
2154 	memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2155 	wlc->bsscfg->type = BRCMS_TYPE_STATION;
2156 }
2157 
brcms_c_start_ap(struct brcms_c_info * wlc,u8 * addr,const u8 * bssid,u8 * ssid,size_t ssid_len)2158 void brcms_c_start_ap(struct brcms_c_info *wlc, u8 *addr, const u8 *bssid,
2159 		      u8 *ssid, size_t ssid_len)
2160 {
2161 	brcms_c_set_ssid(wlc, ssid, ssid_len);
2162 
2163 	memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2164 	memcpy(wlc->bsscfg->BSSID, bssid, sizeof(wlc->bsscfg->BSSID));
2165 	wlc->bsscfg->type = BRCMS_TYPE_AP;
2166 
2167 	brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, MCTL_AP | MCTL_INFRA);
2168 }
2169 
brcms_c_start_adhoc(struct brcms_c_info * wlc,u8 * addr)2170 void brcms_c_start_adhoc(struct brcms_c_info *wlc, u8 *addr)
2171 {
2172 	memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2173 	wlc->bsscfg->type = BRCMS_TYPE_ADHOC;
2174 
2175 	brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, 0);
2176 }
2177 
2178 /* Initialize GPIOs that are controlled by D11 core */
brcms_c_gpio_init(struct brcms_c_info * wlc)2179 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2180 {
2181 	struct brcms_hardware *wlc_hw = wlc->hw;
2182 	u32 gc, gm;
2183 
2184 	/* use GPIO select 0 to get all gpio signals from the gpio out reg */
2185 	brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2186 
2187 	/*
2188 	 * Common GPIO setup:
2189 	 *      G0 = LED 0 = WLAN Activity
2190 	 *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2191 	 *      G2 = LED 2 = WLAN 5 GHz Radio State
2192 	 *      G4 = radio disable input (HI enabled, LO disabled)
2193 	 */
2194 
2195 	gc = gm = 0;
2196 
2197 	/* Allocate GPIOs for mimo antenna diversity feature */
2198 	if (wlc_hw->antsel_type == ANTSEL_2x3) {
2199 		/* Enable antenna diversity, use 2x3 mode */
2200 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2201 			     MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2202 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2203 			     MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2204 
2205 		/* init superswitch control */
2206 		wlc_phy_antsel_init(wlc_hw->band->pi, false);
2207 
2208 	} else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2209 		gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2210 		/*
2211 		 * The board itself is powered by these GPIOs
2212 		 * (when not sending pattern) so set them high
2213 		 */
2214 		bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2215 			   (BOARD_GPIO_12 | BOARD_GPIO_13));
2216 		bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2217 			   (BOARD_GPIO_12 | BOARD_GPIO_13));
2218 
2219 		/* Enable antenna diversity, use 2x4 mode */
2220 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2221 			     MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2222 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2223 			     BRCM_BAND_ALL);
2224 
2225 		/* Configure the desired clock to be 4Mhz */
2226 		brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2227 				   ANTSEL_CLKDIV_4MHZ);
2228 	}
2229 
2230 	/*
2231 	 * gpio 9 controls the PA. ucode is responsible
2232 	 * for wiggling out and oe
2233 	 */
2234 	if (wlc_hw->boardflags & BFL_PACTRL)
2235 		gm |= gc |= BOARD_GPIO_PACTRL;
2236 
2237 	/* apply to gpiocontrol register */
2238 	bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2239 }
2240 
brcms_ucode_write(struct brcms_hardware * wlc_hw,const __le32 ucode[],const size_t nbytes)2241 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2242 			      const __le32 ucode[], const size_t nbytes)
2243 {
2244 	struct bcma_device *core = wlc_hw->d11core;
2245 	uint i;
2246 	uint count;
2247 
2248 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2249 
2250 	count = (nbytes / sizeof(u32));
2251 
2252 	bcma_write32(core, D11REGOFFS(objaddr),
2253 		     OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2254 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2255 	for (i = 0; i < count; i++)
2256 		bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2257 
2258 }
2259 
brcms_ucode_download(struct brcms_hardware * wlc_hw)2260 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2261 {
2262 	struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2263 
2264 	if (wlc_hw->ucode_loaded)
2265 		return;
2266 
2267 	if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2268 		if (BRCMS_ISNPHY(wlc_hw->band)) {
2269 			brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2270 					  ucode->bcm43xx_16_mimosz);
2271 			wlc_hw->ucode_loaded = true;
2272 		} else
2273 			brcms_err(wlc_hw->d11core,
2274 				  "%s: wl%d: unsupported phy in corerev %d\n",
2275 				  __func__, wlc_hw->unit, wlc_hw->corerev);
2276 	} else if (D11REV_IS(wlc_hw->corerev, 24)) {
2277 		if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2278 			brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2279 					  ucode->bcm43xx_24_lcnsz);
2280 			wlc_hw->ucode_loaded = true;
2281 		} else {
2282 			brcms_err(wlc_hw->d11core,
2283 				  "%s: wl%d: unsupported phy in corerev %d\n",
2284 				  __func__, wlc_hw->unit, wlc_hw->corerev);
2285 		}
2286 	}
2287 }
2288 
brcms_b_txant_set(struct brcms_hardware * wlc_hw,u16 phytxant)2289 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2290 {
2291 	/* update sw state */
2292 	wlc_hw->bmac_phytxant = phytxant;
2293 
2294 	/* push to ucode if up */
2295 	if (!wlc_hw->up)
2296 		return;
2297 	brcms_c_ucode_txant_set(wlc_hw);
2298 
2299 }
2300 
brcms_b_get_txant(struct brcms_hardware * wlc_hw)2301 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2302 {
2303 	return (u16) wlc_hw->wlc->stf->txant;
2304 }
2305 
brcms_b_antsel_type_set(struct brcms_hardware * wlc_hw,u8 antsel_type)2306 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2307 {
2308 	wlc_hw->antsel_type = antsel_type;
2309 
2310 	/* Update the antsel type for phy module to use */
2311 	wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2312 }
2313 
brcms_b_fifoerrors(struct brcms_hardware * wlc_hw)2314 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2315 {
2316 	bool fatal = false;
2317 	uint unit;
2318 	uint intstatus, idx;
2319 	struct bcma_device *core = wlc_hw->d11core;
2320 
2321 	unit = wlc_hw->unit;
2322 
2323 	for (idx = 0; idx < NFIFO; idx++) {
2324 		/* read intstatus register and ignore any non-error bits */
2325 		intstatus =
2326 			bcma_read32(core,
2327 				    D11REGOFFS(intctrlregs[idx].intstatus)) &
2328 			I_ERRORS;
2329 		if (!intstatus)
2330 			continue;
2331 
2332 		brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2333 			      unit, idx, intstatus);
2334 
2335 		if (intstatus & I_RO) {
2336 			brcms_err(core, "wl%d: fifo %d: receive fifo "
2337 				  "overflow\n", unit, idx);
2338 			fatal = true;
2339 		}
2340 
2341 		if (intstatus & I_PC) {
2342 			brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2343 				  unit, idx);
2344 			fatal = true;
2345 		}
2346 
2347 		if (intstatus & I_PD) {
2348 			brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2349 				  idx);
2350 			fatal = true;
2351 		}
2352 
2353 		if (intstatus & I_DE) {
2354 			brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2355 				  "error\n", unit, idx);
2356 			fatal = true;
2357 		}
2358 
2359 		if (intstatus & I_RU)
2360 			brcms_err(core, "wl%d: fifo %d: receive descriptor "
2361 				  "underflow\n", idx, unit);
2362 
2363 		if (intstatus & I_XU) {
2364 			brcms_err(core, "wl%d: fifo %d: transmit fifo "
2365 				  "underflow\n", idx, unit);
2366 			fatal = true;
2367 		}
2368 
2369 		if (fatal) {
2370 			brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2371 			break;
2372 		} else
2373 			bcma_write32(core,
2374 				     D11REGOFFS(intctrlregs[idx].intstatus),
2375 				     intstatus);
2376 	}
2377 }
2378 
brcms_c_intrson(struct brcms_c_info * wlc)2379 void brcms_c_intrson(struct brcms_c_info *wlc)
2380 {
2381 	struct brcms_hardware *wlc_hw = wlc->hw;
2382 	wlc->macintmask = wlc->defmacintmask;
2383 	bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2384 }
2385 
brcms_c_intrsoff(struct brcms_c_info * wlc)2386 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2387 {
2388 	struct brcms_hardware *wlc_hw = wlc->hw;
2389 	u32 macintmask;
2390 
2391 	if (!wlc_hw->clk)
2392 		return 0;
2393 
2394 	macintmask = wlc->macintmask;	/* isr can still happen */
2395 
2396 	bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2397 	(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2398 	udelay(1);		/* ensure int line is no longer driven */
2399 	wlc->macintmask = 0;
2400 
2401 	/* return previous macintmask; resolve race between us and our isr */
2402 	return wlc->macintstatus ? 0 : macintmask;
2403 }
2404 
brcms_c_intrsrestore(struct brcms_c_info * wlc,u32 macintmask)2405 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2406 {
2407 	struct brcms_hardware *wlc_hw = wlc->hw;
2408 	if (!wlc_hw->clk)
2409 		return;
2410 
2411 	wlc->macintmask = macintmask;
2412 	bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2413 }
2414 
2415 /* assumes that the d11 MAC is enabled */
brcms_b_tx_fifo_suspend(struct brcms_hardware * wlc_hw,uint tx_fifo)2416 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2417 				    uint tx_fifo)
2418 {
2419 	u8 fifo = 1 << tx_fifo;
2420 
2421 	/* Two clients of this code, 11h Quiet period and scanning. */
2422 
2423 	/* only suspend if not already suspended */
2424 	if ((wlc_hw->suspended_fifos & fifo) == fifo)
2425 		return;
2426 
2427 	/* force the core awake only if not already */
2428 	if (wlc_hw->suspended_fifos == 0)
2429 		brcms_c_ucode_wake_override_set(wlc_hw,
2430 						BRCMS_WAKE_OVERRIDE_TXFIFO);
2431 
2432 	wlc_hw->suspended_fifos |= fifo;
2433 
2434 	if (wlc_hw->di[tx_fifo]) {
2435 		/*
2436 		 * Suspending AMPDU transmissions in the middle can cause
2437 		 * underflow which may result in mismatch between ucode and
2438 		 * driver so suspend the mac before suspending the FIFO
2439 		 */
2440 		if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2441 			brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2442 
2443 		dma_txsuspend(wlc_hw->di[tx_fifo]);
2444 
2445 		if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2446 			brcms_c_enable_mac(wlc_hw->wlc);
2447 	}
2448 }
2449 
brcms_b_tx_fifo_resume(struct brcms_hardware * wlc_hw,uint tx_fifo)2450 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2451 				   uint tx_fifo)
2452 {
2453 	/* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2454 	 * but need to be done here for PIO otherwise the watchdog will catch
2455 	 * the inconsistency and fire
2456 	 */
2457 	/* Two clients of this code, 11h Quiet period and scanning. */
2458 	if (wlc_hw->di[tx_fifo])
2459 		dma_txresume(wlc_hw->di[tx_fifo]);
2460 
2461 	/* allow core to sleep again */
2462 	if (wlc_hw->suspended_fifos == 0)
2463 		return;
2464 	else {
2465 		wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2466 		if (wlc_hw->suspended_fifos == 0)
2467 			brcms_c_ucode_wake_override_clear(wlc_hw,
2468 						BRCMS_WAKE_OVERRIDE_TXFIFO);
2469 	}
2470 }
2471 
2472 /* precondition: requires the mac core to be enabled */
brcms_b_mute(struct brcms_hardware * wlc_hw,bool mute_tx)2473 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2474 {
2475 	static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2476 	u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2477 
2478 	if (mute_tx) {
2479 		/* suspend tx fifos */
2480 		brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2481 		brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2482 		brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2483 		brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2484 
2485 		/* zero the address match register so we do not send ACKs */
2486 		brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2487 	} else {
2488 		/* resume tx fifos */
2489 		brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2490 		brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2491 		brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2492 		brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2493 
2494 		/* Restore address */
2495 		brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2496 	}
2497 
2498 	wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2499 
2500 	if (mute_tx)
2501 		brcms_c_ucode_mute_override_set(wlc_hw);
2502 	else
2503 		brcms_c_ucode_mute_override_clear(wlc_hw);
2504 }
2505 
2506 void
brcms_c_mute(struct brcms_c_info * wlc,bool mute_tx)2507 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2508 {
2509 	brcms_b_mute(wlc->hw, mute_tx);
2510 }
2511 
2512 /*
2513  * Read and clear macintmask and macintstatus and intstatus registers.
2514  * This routine should be called with interrupts off
2515  * Return:
2516  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2517  *   0 if the interrupt is not for us, or we are in some special cases;
2518  *   device interrupt status bits otherwise.
2519  */
wlc_intstatus(struct brcms_c_info * wlc,bool in_isr)2520 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2521 {
2522 	struct brcms_hardware *wlc_hw = wlc->hw;
2523 	struct bcma_device *core = wlc_hw->d11core;
2524 	u32 macintstatus, mask;
2525 
2526 	/* macintstatus includes a DMA interrupt summary bit */
2527 	macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2528 	mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2529 
2530 	trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2531 
2532 	/* detect cardbus removed, in power down(suspend) and in reset */
2533 	if (brcms_deviceremoved(wlc))
2534 		return -1;
2535 
2536 	/* brcms_deviceremoved() succeeds even when the core is still resetting,
2537 	 * handle that case here.
2538 	 */
2539 	if (macintstatus == 0xffffffff)
2540 		return 0;
2541 
2542 	/* defer unsolicited interrupts */
2543 	macintstatus &= mask;
2544 
2545 	/* if not for us */
2546 	if (macintstatus == 0)
2547 		return 0;
2548 
2549 	/* turn off the interrupts */
2550 	bcma_write32(core, D11REGOFFS(macintmask), 0);
2551 	(void)bcma_read32(core, D11REGOFFS(macintmask));
2552 	wlc->macintmask = 0;
2553 
2554 	/* clear device interrupts */
2555 	bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2556 
2557 	/* MI_DMAINT is indication of non-zero intstatus */
2558 	if (macintstatus & MI_DMAINT)
2559 		/*
2560 		 * only fifo interrupt enabled is I_RI in
2561 		 * RX_FIFO. If MI_DMAINT is set, assume it
2562 		 * is set and clear the interrupt.
2563 		 */
2564 		bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2565 			     DEF_RXINTMASK);
2566 
2567 	return macintstatus;
2568 }
2569 
2570 /* Update wlc->macintstatus and wlc->intstatus[]. */
2571 /* Return true if they are updated successfully. false otherwise */
brcms_c_intrsupd(struct brcms_c_info * wlc)2572 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2573 {
2574 	u32 macintstatus;
2575 
2576 	/* read and clear macintstatus and intstatus registers */
2577 	macintstatus = wlc_intstatus(wlc, false);
2578 
2579 	/* device is removed */
2580 	if (macintstatus == 0xffffffff)
2581 		return false;
2582 
2583 	/* update interrupt status in software */
2584 	wlc->macintstatus |= macintstatus;
2585 
2586 	return true;
2587 }
2588 
2589 /*
2590  * First-level interrupt processing.
2591  * Return true if this was our interrupt
2592  * and if further brcms_c_dpc() processing is required,
2593  * false otherwise.
2594  */
brcms_c_isr(struct brcms_c_info * wlc)2595 bool brcms_c_isr(struct brcms_c_info *wlc)
2596 {
2597 	struct brcms_hardware *wlc_hw = wlc->hw;
2598 	u32 macintstatus;
2599 
2600 	if (!wlc_hw->up || !wlc->macintmask)
2601 		return false;
2602 
2603 	/* read and clear macintstatus and intstatus registers */
2604 	macintstatus = wlc_intstatus(wlc, true);
2605 
2606 	if (macintstatus == 0xffffffff) {
2607 		brcms_err(wlc_hw->d11core,
2608 			  "DEVICEREMOVED detected in the ISR code path\n");
2609 		return false;
2610 	}
2611 
2612 	/* it is not for us */
2613 	if (macintstatus == 0)
2614 		return false;
2615 
2616 	/* save interrupt status bits */
2617 	wlc->macintstatus = macintstatus;
2618 
2619 	return true;
2620 
2621 }
2622 
brcms_c_suspend_mac_and_wait(struct brcms_c_info * wlc)2623 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2624 {
2625 	struct brcms_hardware *wlc_hw = wlc->hw;
2626 	struct bcma_device *core = wlc_hw->d11core;
2627 	u32 mc, mi;
2628 
2629 	brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2630 			   wlc_hw->band->bandunit);
2631 
2632 	/*
2633 	 * Track overlapping suspend requests
2634 	 */
2635 	wlc_hw->mac_suspend_depth++;
2636 	if (wlc_hw->mac_suspend_depth > 1)
2637 		return;
2638 
2639 	/* force the core awake */
2640 	brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2641 
2642 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2643 
2644 	if (mc == 0xffffffff) {
2645 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2646 			  __func__);
2647 		brcms_down(wlc->wl);
2648 		return;
2649 	}
2650 	WARN_ON(mc & MCTL_PSM_JMP_0);
2651 	WARN_ON(!(mc & MCTL_PSM_RUN));
2652 	WARN_ON(!(mc & MCTL_EN_MAC));
2653 
2654 	mi = bcma_read32(core, D11REGOFFS(macintstatus));
2655 	if (mi == 0xffffffff) {
2656 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2657 			  __func__);
2658 		brcms_down(wlc->wl);
2659 		return;
2660 	}
2661 	WARN_ON(mi & MI_MACSSPNDD);
2662 
2663 	brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2664 
2665 	SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2666 		 BRCMS_MAX_MAC_SUSPEND);
2667 
2668 	if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2669 		brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2670 			  " and MI_MACSSPNDD is still not on.\n",
2671 			  wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2672 		brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2673 			  "psm_brc 0x%04x\n", wlc_hw->unit,
2674 			  bcma_read32(core, D11REGOFFS(psmdebug)),
2675 			  bcma_read32(core, D11REGOFFS(phydebug)),
2676 			  bcma_read16(core, D11REGOFFS(psm_brc)));
2677 	}
2678 
2679 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2680 	if (mc == 0xffffffff) {
2681 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2682 			  __func__);
2683 		brcms_down(wlc->wl);
2684 		return;
2685 	}
2686 	WARN_ON(mc & MCTL_PSM_JMP_0);
2687 	WARN_ON(!(mc & MCTL_PSM_RUN));
2688 	WARN_ON(mc & MCTL_EN_MAC);
2689 }
2690 
brcms_c_enable_mac(struct brcms_c_info * wlc)2691 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2692 {
2693 	struct brcms_hardware *wlc_hw = wlc->hw;
2694 	struct bcma_device *core = wlc_hw->d11core;
2695 	u32 mc, mi;
2696 
2697 	brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2698 			   wlc->band->bandunit);
2699 
2700 	/*
2701 	 * Track overlapping suspend requests
2702 	 */
2703 	wlc_hw->mac_suspend_depth--;
2704 	if (wlc_hw->mac_suspend_depth > 0)
2705 		return;
2706 
2707 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2708 	WARN_ON(mc & MCTL_PSM_JMP_0);
2709 	WARN_ON(mc & MCTL_EN_MAC);
2710 	WARN_ON(!(mc & MCTL_PSM_RUN));
2711 
2712 	brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2713 	bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2714 
2715 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2716 	WARN_ON(mc & MCTL_PSM_JMP_0);
2717 	WARN_ON(!(mc & MCTL_EN_MAC));
2718 	WARN_ON(!(mc & MCTL_PSM_RUN));
2719 
2720 	mi = bcma_read32(core, D11REGOFFS(macintstatus));
2721 	WARN_ON(mi & MI_MACSSPNDD);
2722 
2723 	brcms_c_ucode_wake_override_clear(wlc_hw,
2724 					  BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2725 }
2726 
brcms_b_band_stf_ss_set(struct brcms_hardware * wlc_hw,u8 stf_mode)2727 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2728 {
2729 	wlc_hw->hw_stf_ss_opmode = stf_mode;
2730 
2731 	if (wlc_hw->clk)
2732 		brcms_upd_ofdm_pctl1_table(wlc_hw);
2733 }
2734 
brcms_b_validate_chip_access(struct brcms_hardware * wlc_hw)2735 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2736 {
2737 	struct bcma_device *core = wlc_hw->d11core;
2738 	u32 w, val;
2739 	struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2740 
2741 	/* Validate dchip register access */
2742 
2743 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2744 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2745 	w = bcma_read32(core, D11REGOFFS(objdata));
2746 
2747 	/* Can we write and read back a 32bit register? */
2748 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2749 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2750 	bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2751 
2752 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2753 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2754 	val = bcma_read32(core, D11REGOFFS(objdata));
2755 	if (val != (u32) 0xaa5555aa) {
2756 		wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2757 			  "expected 0xaa5555aa\n", wlc_hw->unit, val);
2758 		return false;
2759 	}
2760 
2761 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2762 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2763 	bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2764 
2765 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2766 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2767 	val = bcma_read32(core, D11REGOFFS(objdata));
2768 	if (val != (u32) 0x55aaaa55) {
2769 		wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2770 			  "expected 0x55aaaa55\n", wlc_hw->unit, val);
2771 		return false;
2772 	}
2773 
2774 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2775 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2776 	bcma_write32(core, D11REGOFFS(objdata), w);
2777 
2778 	/* clear CFPStart */
2779 	bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2780 
2781 	w = bcma_read32(core, D11REGOFFS(maccontrol));
2782 	if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2783 	    (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2784 		wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2785 			  "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2786 			  (MCTL_IHR_EN | MCTL_WAKE),
2787 			  (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2788 		return false;
2789 	}
2790 
2791 	return true;
2792 }
2793 
2794 #define PHYPLL_WAIT_US	100000
2795 
brcms_b_core_phypll_ctl(struct brcms_hardware * wlc_hw,bool on)2796 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2797 {
2798 	struct bcma_device *core = wlc_hw->d11core;
2799 	u32 tmp;
2800 
2801 	brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2802 
2803 	tmp = 0;
2804 
2805 	if (on) {
2806 		if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2807 			bcma_set32(core, D11REGOFFS(clk_ctl_st),
2808 				   CCS_ERSRC_REQ_HT |
2809 				   CCS_ERSRC_REQ_D11PLL |
2810 				   CCS_ERSRC_REQ_PHYPLL);
2811 			SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2812 				  CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2813 				 PHYPLL_WAIT_US);
2814 
2815 			tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2816 			if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2817 				brcms_err(core, "%s: turn on PHY PLL failed\n",
2818 					  __func__);
2819 		} else {
2820 			bcma_set32(core, D11REGOFFS(clk_ctl_st),
2821 				   tmp | CCS_ERSRC_REQ_D11PLL |
2822 				   CCS_ERSRC_REQ_PHYPLL);
2823 			SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2824 				  (CCS_ERSRC_AVAIL_D11PLL |
2825 				   CCS_ERSRC_AVAIL_PHYPLL)) !=
2826 				 (CCS_ERSRC_AVAIL_D11PLL |
2827 				  CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2828 
2829 			tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2830 			if ((tmp &
2831 			     (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2832 			    !=
2833 			    (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2834 				brcms_err(core, "%s: turn on PHY PLL failed\n",
2835 					  __func__);
2836 		}
2837 	} else {
2838 		/*
2839 		 * Since the PLL may be shared, other cores can still
2840 		 * be requesting it; so we'll deassert the request but
2841 		 * not wait for status to comply.
2842 		 */
2843 		bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2844 			    ~CCS_ERSRC_REQ_PHYPLL);
2845 		(void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2846 	}
2847 }
2848 
brcms_c_coredisable(struct brcms_hardware * wlc_hw)2849 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2850 {
2851 	bool dev_gone;
2852 
2853 	brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2854 
2855 	dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2856 
2857 	if (dev_gone)
2858 		return;
2859 
2860 	if (wlc_hw->noreset)
2861 		return;
2862 
2863 	/* radio off */
2864 	wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2865 
2866 	/* turn off analog core */
2867 	wlc_phy_anacore(wlc_hw->band->pi, OFF);
2868 
2869 	/* turn off PHYPLL to save power */
2870 	brcms_b_core_phypll_ctl(wlc_hw, false);
2871 
2872 	wlc_hw->clk = false;
2873 	bcma_core_disable(wlc_hw->d11core, 0);
2874 	wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2875 }
2876 
brcms_c_flushqueues(struct brcms_c_info * wlc)2877 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2878 {
2879 	struct brcms_hardware *wlc_hw = wlc->hw;
2880 	uint i;
2881 
2882 	/* free any posted tx packets */
2883 	for (i = 0; i < NFIFO; i++) {
2884 		if (wlc_hw->di[i]) {
2885 			dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2886 			if (i < TX_BCMC_FIFO)
2887 				ieee80211_wake_queue(wlc->pub->ieee_hw,
2888 						     brcms_fifo_to_ac(i));
2889 		}
2890 	}
2891 
2892 	/* free any posted rx packets */
2893 	dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2894 }
2895 
2896 static u16
brcms_b_read_objmem(struct brcms_hardware * wlc_hw,uint offset,u32 sel)2897 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2898 {
2899 	struct bcma_device *core = wlc_hw->d11core;
2900 	u16 objoff = D11REGOFFS(objdata);
2901 
2902 	bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2903 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2904 	if (offset & 2)
2905 		objoff += 2;
2906 
2907 	return bcma_read16(core, objoff);
2908 }
2909 
2910 static void
brcms_b_write_objmem(struct brcms_hardware * wlc_hw,uint offset,u16 v,u32 sel)2911 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2912 		     u32 sel)
2913 {
2914 	struct bcma_device *core = wlc_hw->d11core;
2915 	u16 objoff = D11REGOFFS(objdata);
2916 
2917 	bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2918 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2919 	if (offset & 2)
2920 		objoff += 2;
2921 
2922 	bcma_wflush16(core, objoff, v);
2923 }
2924 
2925 /*
2926  * Read a single u16 from shared memory.
2927  * SHM 'offset' needs to be an even address
2928  */
brcms_b_read_shm(struct brcms_hardware * wlc_hw,uint offset)2929 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2930 {
2931 	return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2932 }
2933 
2934 /*
2935  * Write a single u16 to shared memory.
2936  * SHM 'offset' needs to be an even address
2937  */
brcms_b_write_shm(struct brcms_hardware * wlc_hw,uint offset,u16 v)2938 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2939 {
2940 	brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2941 }
2942 
2943 /*
2944  * Copy a buffer to shared memory of specified type .
2945  * SHM 'offset' needs to be an even address and
2946  * Buffer length 'len' must be an even number of bytes
2947  * 'sel' selects the type of memory
2948  */
2949 void
brcms_b_copyto_objmem(struct brcms_hardware * wlc_hw,uint offset,const void * buf,int len,u32 sel)2950 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2951 		      const void *buf, int len, u32 sel)
2952 {
2953 	u16 v;
2954 	const u8 *p = (const u8 *)buf;
2955 	int i;
2956 
2957 	if (len <= 0 || (offset & 1) || (len & 1))
2958 		return;
2959 
2960 	for (i = 0; i < len; i += 2) {
2961 		v = p[i] | (p[i + 1] << 8);
2962 		brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2963 	}
2964 }
2965 
2966 /*
2967  * Copy a piece of shared memory of specified type to a buffer .
2968  * SHM 'offset' needs to be an even address and
2969  * Buffer length 'len' must be an even number of bytes
2970  * 'sel' selects the type of memory
2971  */
2972 void
brcms_b_copyfrom_objmem(struct brcms_hardware * wlc_hw,uint offset,void * buf,int len,u32 sel)2973 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2974 			 int len, u32 sel)
2975 {
2976 	u16 v;
2977 	u8 *p = (u8 *) buf;
2978 	int i;
2979 
2980 	if (len <= 0 || (offset & 1) || (len & 1))
2981 		return;
2982 
2983 	for (i = 0; i < len; i += 2) {
2984 		v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2985 		p[i] = v & 0xFF;
2986 		p[i + 1] = (v >> 8) & 0xFF;
2987 	}
2988 }
2989 
2990 /* Copy a buffer to shared memory.
2991  * SHM 'offset' needs to be an even address and
2992  * Buffer length 'len' must be an even number of bytes
2993  */
brcms_c_copyto_shm(struct brcms_c_info * wlc,uint offset,const void * buf,int len)2994 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2995 			const void *buf, int len)
2996 {
2997 	brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2998 }
2999 
brcms_b_retrylimit_upd(struct brcms_hardware * wlc_hw,u16 SRL,u16 LRL)3000 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3001 				   u16 SRL, u16 LRL)
3002 {
3003 	wlc_hw->SRL = SRL;
3004 	wlc_hw->LRL = LRL;
3005 
3006 	/* write retry limit to SCR, shouldn't need to suspend */
3007 	if (wlc_hw->up) {
3008 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3009 			     OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3010 		(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3011 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3012 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3013 			     OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3014 		(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3015 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3016 	}
3017 }
3018 
brcms_b_pllreq(struct brcms_hardware * wlc_hw,bool set,u32 req_bit)3019 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3020 {
3021 	if (set) {
3022 		if (mboolisset(wlc_hw->pllreq, req_bit))
3023 			return;
3024 
3025 		mboolset(wlc_hw->pllreq, req_bit);
3026 
3027 		if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3028 			if (!wlc_hw->sbclk)
3029 				brcms_b_xtal(wlc_hw, ON);
3030 		}
3031 	} else {
3032 		if (!mboolisset(wlc_hw->pllreq, req_bit))
3033 			return;
3034 
3035 		mboolclr(wlc_hw->pllreq, req_bit);
3036 
3037 		if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3038 			if (wlc_hw->sbclk)
3039 				brcms_b_xtal(wlc_hw, OFF);
3040 		}
3041 	}
3042 }
3043 
brcms_b_antsel_set(struct brcms_hardware * wlc_hw,u32 antsel_avail)3044 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3045 {
3046 	wlc_hw->antsel_avail = antsel_avail;
3047 }
3048 
3049 /*
3050  * conditions under which the PM bit should be set in outgoing frames
3051  * and STAY_AWAKE is meaningful
3052  */
brcms_c_ps_allowed(struct brcms_c_info * wlc)3053 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3054 {
3055 	/* not supporting PS so always return false for now */
3056 	return false;
3057 }
3058 
brcms_c_statsupd(struct brcms_c_info * wlc)3059 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3060 {
3061 	int i;
3062 	struct macstat *macstats;
3063 #ifdef DEBUG
3064 	u16 delta;
3065 	u16 rxf0ovfl;
3066 	u16 txfunfl[NFIFO];
3067 #endif				/* DEBUG */
3068 
3069 	/* if driver down, make no sense to update stats */
3070 	if (!wlc->pub->up)
3071 		return;
3072 
3073 	macstats = wlc->core->macstat_snapshot;
3074 
3075 #ifdef DEBUG
3076 	/* save last rx fifo 0 overflow count */
3077 	rxf0ovfl = macstats->rxf0ovfl;
3078 
3079 	/* save last tx fifo  underflow count */
3080 	for (i = 0; i < NFIFO; i++)
3081 		txfunfl[i] = macstats->txfunfl[i];
3082 #endif				/* DEBUG */
3083 
3084 	/* Read mac stats from contiguous shared memory */
3085 	brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, macstats,
3086 				sizeof(*macstats), OBJADDR_SHM_SEL);
3087 
3088 #ifdef DEBUG
3089 	/* check for rx fifo 0 overflow */
3090 	delta = (u16)(macstats->rxf0ovfl - rxf0ovfl);
3091 	if (delta)
3092 		brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3093 			  wlc->pub->unit, delta);
3094 
3095 	/* check for tx fifo underflows */
3096 	for (i = 0; i < NFIFO; i++) {
3097 		delta = macstats->txfunfl[i] - txfunfl[i];
3098 		if (delta)
3099 			brcms_err(wlc->hw->d11core,
3100 				  "wl%d: %u tx fifo %d underflows!\n",
3101 				  wlc->pub->unit, delta, i);
3102 	}
3103 #endif				/* DEBUG */
3104 
3105 	/* merge counters from dma module */
3106 	for (i = 0; i < NFIFO; i++) {
3107 		if (wlc->hw->di[i])
3108 			dma_counterreset(wlc->hw->di[i]);
3109 	}
3110 }
3111 
brcms_b_reset(struct brcms_hardware * wlc_hw)3112 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3113 {
3114 	/* reset the core */
3115 	if (!brcms_deviceremoved(wlc_hw->wlc))
3116 		brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3117 
3118 	/* purge the dma rings */
3119 	brcms_c_flushqueues(wlc_hw->wlc);
3120 }
3121 
brcms_c_reset(struct brcms_c_info * wlc)3122 void brcms_c_reset(struct brcms_c_info *wlc)
3123 {
3124 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3125 
3126 	/* slurp up hw mac counters before core reset */
3127 	brcms_c_statsupd(wlc);
3128 
3129 	/* reset our snapshot of macstat counters */
3130 	memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3131 
3132 	brcms_b_reset(wlc->hw);
3133 }
3134 
brcms_c_init_scb(struct scb * scb)3135 void brcms_c_init_scb(struct scb *scb)
3136 {
3137 	int i;
3138 
3139 	memset(scb, 0, sizeof(struct scb));
3140 	scb->flags = SCB_WMECAP | SCB_HTCAP;
3141 	for (i = 0; i < NUMPRIO; i++) {
3142 		scb->seqnum[i] = 0;
3143 	}
3144 
3145 	scb->magic = SCB_MAGIC;
3146 }
3147 
3148 /* d11 core init
3149  *   reset PSM
3150  *   download ucode/PCM
3151  *   let ucode run to suspended
3152  *   download ucode inits
3153  *   config other core registers
3154  *   init dma
3155  */
brcms_b_coreinit(struct brcms_c_info * wlc)3156 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3157 {
3158 	struct brcms_hardware *wlc_hw = wlc->hw;
3159 	struct bcma_device *core = wlc_hw->d11core;
3160 	u32 bcnint_us;
3161 	uint i = 0;
3162 	bool fifosz_fixup = false;
3163 	int err = 0;
3164 	u16 buf[NFIFO];
3165 	struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3166 
3167 	brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3168 
3169 	/* reset PSM */
3170 	brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3171 
3172 	brcms_ucode_download(wlc_hw);
3173 	/*
3174 	 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3175 	 */
3176 	fifosz_fixup = true;
3177 
3178 	/* let the PSM run to the suspended state, set mode to BSS STA */
3179 	bcma_write32(core, D11REGOFFS(macintstatus), -1);
3180 	brcms_b_mctrl(wlc_hw, ~0,
3181 		       (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3182 
3183 	/* wait for ucode to self-suspend after auto-init */
3184 	SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3185 		   MI_MACSSPNDD) == 0), 1000 * 1000);
3186 	if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3187 		brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3188 			  "suspend!\n", wlc_hw->unit);
3189 
3190 	brcms_c_gpio_init(wlc);
3191 
3192 	bcma_aread32(core, BCMA_IOST);
3193 
3194 	if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3195 		if (BRCMS_ISNPHY(wlc_hw->band))
3196 			brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3197 		else
3198 			brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3199 				  " %d\n", __func__, wlc_hw->unit,
3200 				  wlc_hw->corerev);
3201 	} else if (D11REV_IS(wlc_hw->corerev, 24)) {
3202 		if (BRCMS_ISLCNPHY(wlc_hw->band))
3203 			brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3204 		else
3205 			brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3206 				  " %d\n", __func__, wlc_hw->unit,
3207 				  wlc_hw->corerev);
3208 	} else {
3209 		brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3210 			  __func__, wlc_hw->unit, wlc_hw->corerev);
3211 	}
3212 
3213 	/* For old ucode, txfifo sizes needs to be modified(increased) */
3214 	if (fifosz_fixup)
3215 		brcms_b_corerev_fifofixup(wlc_hw);
3216 
3217 	/* check txfifo allocations match between ucode and driver */
3218 	buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3219 	if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3220 		i = TX_AC_BE_FIFO;
3221 		err = -1;
3222 	}
3223 	buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3224 	if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3225 		i = TX_AC_VI_FIFO;
3226 		err = -1;
3227 	}
3228 	buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3229 	buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3230 	buf[TX_AC_BK_FIFO] &= 0xff;
3231 	if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3232 		i = TX_AC_BK_FIFO;
3233 		err = -1;
3234 	}
3235 	if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3236 		i = TX_AC_VO_FIFO;
3237 		err = -1;
3238 	}
3239 	buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3240 	buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3241 	buf[TX_BCMC_FIFO] &= 0xff;
3242 	if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3243 		i = TX_BCMC_FIFO;
3244 		err = -1;
3245 	}
3246 	if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3247 		i = TX_ATIM_FIFO;
3248 		err = -1;
3249 	}
3250 	if (err != 0)
3251 		brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3252 			  " driver size %d index %d\n", buf[i],
3253 			  wlc_hw->xmtfifo_sz[i], i);
3254 
3255 	/* make sure we can still talk to the mac */
3256 	WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3257 
3258 	/* band-specific inits done by wlc_bsinit() */
3259 
3260 	/* Set up frame burst size and antenna swap threshold init values */
3261 	brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3262 	brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3263 
3264 	/* enable one rx interrupt per received frame */
3265 	bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3266 
3267 	/* set the station mode (BSS STA) */
3268 	brcms_b_mctrl(wlc_hw,
3269 		       (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3270 		       (MCTL_INFRA | MCTL_DISCARD_PMQ));
3271 
3272 	/* set up Beacon interval */
3273 	bcnint_us = 0x8000 << 10;
3274 	bcma_write32(core, D11REGOFFS(tsf_cfprep),
3275 		     (bcnint_us << CFPREP_CBI_SHIFT));
3276 	bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3277 	bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3278 
3279 	/* write interrupt mask */
3280 	bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3281 		     DEF_RXINTMASK);
3282 
3283 	/* allow the MAC to control the PHY clock (dynamic on/off) */
3284 	brcms_b_macphyclk_set(wlc_hw, ON);
3285 
3286 	/* program dynamic clock control fast powerup delay register */
3287 	wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3288 	bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3289 
3290 	/* tell the ucode the corerev */
3291 	brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3292 
3293 	/* tell the ucode MAC capabilities */
3294 	brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3295 			   (u16) (wlc_hw->machwcap & 0xffff));
3296 	brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3297 			   (u16) ((wlc_hw->
3298 				      machwcap >> 16) & 0xffff));
3299 
3300 	/* write retry limits to SCR, this done after PSM init */
3301 	bcma_write32(core, D11REGOFFS(objaddr),
3302 		     OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3303 	(void)bcma_read32(core, D11REGOFFS(objaddr));
3304 	bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3305 	bcma_write32(core, D11REGOFFS(objaddr),
3306 		     OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3307 	(void)bcma_read32(core, D11REGOFFS(objaddr));
3308 	bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3309 
3310 	/* write rate fallback retry limits */
3311 	brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3312 	brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3313 
3314 	bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3315 	bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3316 
3317 	/* init the tx dma engines */
3318 	for (i = 0; i < NFIFO; i++) {
3319 		if (wlc_hw->di[i])
3320 			dma_txinit(wlc_hw->di[i]);
3321 	}
3322 
3323 	/* init the rx dma engine(s) and post receive buffers */
3324 	dma_rxinit(wlc_hw->di[RX_FIFO]);
3325 	dma_rxfill(wlc_hw->di[RX_FIFO]);
3326 }
3327 
brcms_b_init(struct brcms_hardware * wlc_hw,u16 chanspec)3328 static void brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec)
3329 {
3330 	u32 macintmask;
3331 	bool fastclk;
3332 	struct brcms_c_info *wlc = wlc_hw->wlc;
3333 
3334 	/* request FAST clock if not on */
3335 	fastclk = wlc_hw->forcefastclk;
3336 	if (!fastclk)
3337 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3338 
3339 	/* disable interrupts */
3340 	macintmask = brcms_intrsoff(wlc->wl);
3341 
3342 	/* set up the specified band and chanspec */
3343 	brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3344 	wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3345 
3346 	/* do one-time phy inits and calibration */
3347 	wlc_phy_cal_init(wlc_hw->band->pi);
3348 
3349 	/* core-specific initialization */
3350 	brcms_b_coreinit(wlc);
3351 
3352 	/* band-specific inits */
3353 	brcms_b_bsinit(wlc, chanspec);
3354 
3355 	/* restore macintmask */
3356 	brcms_intrsrestore(wlc->wl, macintmask);
3357 
3358 	/* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3359 	 * is suspended and brcms_c_enable_mac() will clear this override bit.
3360 	 */
3361 	mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3362 
3363 	/*
3364 	 * initialize mac_suspend_depth to 1 to match ucode
3365 	 * initial suspended state
3366 	 */
3367 	wlc_hw->mac_suspend_depth = 1;
3368 
3369 	/* restore the clk */
3370 	if (!fastclk)
3371 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3372 }
3373 
brcms_c_set_phy_chanspec(struct brcms_c_info * wlc,u16 chanspec)3374 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3375 				     u16 chanspec)
3376 {
3377 	/* Save our copy of the chanspec */
3378 	wlc->chanspec = chanspec;
3379 
3380 	/* Set the chanspec and power limits for this locale */
3381 	brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3382 
3383 	if (wlc->stf->ss_algosel_auto)
3384 		brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3385 					    chanspec);
3386 
3387 	brcms_c_stf_ss_update(wlc, wlc->band);
3388 }
3389 
3390 static void
brcms_default_rateset(struct brcms_c_info * wlc,struct brcms_c_rateset * rs)3391 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3392 {
3393 	brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3394 		wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3395 		(bool) (wlc->pub->_n_enab & SUPPORT_11N),
3396 		brcms_chspec_bw(wlc->default_bss->chanspec),
3397 		wlc->stf->txstreams);
3398 }
3399 
3400 /* derive wlc->band->basic_rate[] table from 'rateset' */
brcms_c_rate_lookup_init(struct brcms_c_info * wlc,struct brcms_c_rateset * rateset)3401 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3402 			      struct brcms_c_rateset *rateset)
3403 {
3404 	u8 rate;
3405 	u8 mandatory;
3406 	u8 cck_basic = 0;
3407 	u8 ofdm_basic = 0;
3408 	u8 *br = wlc->band->basic_rate;
3409 	uint i;
3410 
3411 	/* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3412 	memset(br, 0, BRCM_MAXRATE + 1);
3413 
3414 	/* For each basic rate in the rates list, make an entry in the
3415 	 * best basic lookup.
3416 	 */
3417 	for (i = 0; i < rateset->count; i++) {
3418 		/* only make an entry for a basic rate */
3419 		if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3420 			continue;
3421 
3422 		/* mask off basic bit */
3423 		rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3424 
3425 		if (rate > BRCM_MAXRATE) {
3426 			brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3427 				  "invalid rate 0x%X in rate set\n",
3428 				  rateset->rates[i]);
3429 			continue;
3430 		}
3431 
3432 		br[rate] = rate;
3433 	}
3434 
3435 	/* The rate lookup table now has non-zero entries for each
3436 	 * basic rate, equal to the basic rate: br[basicN] = basicN
3437 	 *
3438 	 * To look up the best basic rate corresponding to any
3439 	 * particular rate, code can use the basic_rate table
3440 	 * like this
3441 	 *
3442 	 * basic_rate = wlc->band->basic_rate[tx_rate]
3443 	 *
3444 	 * Make sure there is a best basic rate entry for
3445 	 * every rate by walking up the table from low rates
3446 	 * to high, filling in holes in the lookup table
3447 	 */
3448 
3449 	for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3450 		rate = wlc->band->hw_rateset.rates[i];
3451 
3452 		if (br[rate] != 0) {
3453 			/* This rate is a basic rate.
3454 			 * Keep track of the best basic rate so far by
3455 			 * modulation type.
3456 			 */
3457 			if (is_ofdm_rate(rate))
3458 				ofdm_basic = rate;
3459 			else
3460 				cck_basic = rate;
3461 
3462 			continue;
3463 		}
3464 
3465 		/* This rate is not a basic rate so figure out the
3466 		 * best basic rate less than this rate and fill in
3467 		 * the hole in the table
3468 		 */
3469 
3470 		br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3471 
3472 		if (br[rate] != 0)
3473 			continue;
3474 
3475 		if (is_ofdm_rate(rate)) {
3476 			/*
3477 			 * In 11g and 11a, the OFDM mandatory rates
3478 			 * are 6, 12, and 24 Mbps
3479 			 */
3480 			if (rate >= BRCM_RATE_24M)
3481 				mandatory = BRCM_RATE_24M;
3482 			else if (rate >= BRCM_RATE_12M)
3483 				mandatory = BRCM_RATE_12M;
3484 			else
3485 				mandatory = BRCM_RATE_6M;
3486 		} else {
3487 			/* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3488 			mandatory = rate;
3489 		}
3490 
3491 		br[rate] = mandatory;
3492 	}
3493 }
3494 
brcms_c_bandinit_ordered(struct brcms_c_info * wlc,u16 chanspec)3495 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3496 				     u16 chanspec)
3497 {
3498 	struct brcms_c_rateset default_rateset;
3499 	uint parkband;
3500 	uint i, band_order[2];
3501 
3502 	/*
3503 	 * We might have been bandlocked during down and the chip
3504 	 * power-cycled (hibernate). Figure out the right band to park on
3505 	 */
3506 	if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3507 		/* updated in brcms_c_bandlock() */
3508 		parkband = wlc->band->bandunit;
3509 		band_order[0] = band_order[1] = parkband;
3510 	} else {
3511 		/* park on the band of the specified chanspec */
3512 		parkband = chspec_bandunit(chanspec);
3513 
3514 		/* order so that parkband initialize last */
3515 		band_order[0] = parkband ^ 1;
3516 		band_order[1] = parkband;
3517 	}
3518 
3519 	/* make each band operational, software state init */
3520 	for (i = 0; i < wlc->pub->_nbands; i++) {
3521 		uint j = band_order[i];
3522 
3523 		wlc->band = wlc->bandstate[j];
3524 
3525 		brcms_default_rateset(wlc, &default_rateset);
3526 
3527 		/* fill in hw_rate */
3528 		brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3529 				   false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3530 				   (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3531 
3532 		/* init basic rate lookup */
3533 		brcms_c_rate_lookup_init(wlc, &default_rateset);
3534 	}
3535 
3536 	/* sync up phy/radio chanspec */
3537 	brcms_c_set_phy_chanspec(wlc, chanspec);
3538 }
3539 
3540 /*
3541  * Set or clear filtering related maccontrol bits based on
3542  * specified filter flags
3543  */
brcms_c_mac_promisc(struct brcms_c_info * wlc,uint filter_flags)3544 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3545 {
3546 	u32 promisc_bits = 0;
3547 
3548 	wlc->filter_flags = filter_flags;
3549 
3550 	if (filter_flags & FIF_OTHER_BSS)
3551 		promisc_bits |= MCTL_PROMISC;
3552 
3553 	if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3554 		promisc_bits |= MCTL_BCNS_PROMISC;
3555 
3556 	if (filter_flags & FIF_FCSFAIL)
3557 		promisc_bits |= MCTL_KEEPBADFCS;
3558 
3559 	if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3560 		promisc_bits |= MCTL_KEEPCONTROL;
3561 
3562 	brcms_b_mctrl(wlc->hw,
3563 		MCTL_PROMISC | MCTL_BCNS_PROMISC |
3564 		MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3565 		promisc_bits);
3566 }
3567 
3568 /*
3569  * ucode, hwmac update
3570  *    Channel dependent updates for ucode and hw
3571  */
brcms_c_ucode_mac_upd(struct brcms_c_info * wlc)3572 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3573 {
3574 	/* enable or disable any active IBSSs depending on whether or not
3575 	 * we are on the home channel
3576 	 */
3577 	if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3578 		if (wlc->pub->associated) {
3579 			/*
3580 			 * BMAC_NOTE: This is something that should be fixed
3581 			 * in ucode inits. I think that the ucode inits set
3582 			 * up the bcn templates and shm values with a bogus
3583 			 * beacon. This should not be done in the inits. If
3584 			 * ucode needs to set up a beacon for testing, the
3585 			 * test routines should write it down, not expect the
3586 			 * inits to populate a bogus beacon.
3587 			 */
3588 			if (BRCMS_PHY_11N_CAP(wlc->band))
3589 				brcms_b_write_shm(wlc->hw,
3590 						M_BCN_TXTSF_OFFSET, 0);
3591 		}
3592 	} else {
3593 		/* disable an active IBSS if we are not on the home channel */
3594 	}
3595 }
3596 
brcms_c_write_rate_shm(struct brcms_c_info * wlc,u8 rate,u8 basic_rate)3597 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3598 				   u8 basic_rate)
3599 {
3600 	u8 phy_rate, index;
3601 	u8 basic_phy_rate, basic_index;
3602 	u16 dir_table, basic_table;
3603 	u16 basic_ptr;
3604 
3605 	/* Shared memory address for the table we are reading */
3606 	dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3607 
3608 	/* Shared memory address for the table we are writing */
3609 	basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3610 
3611 	/*
3612 	 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3613 	 * the index into the rate table.
3614 	 */
3615 	phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3616 	basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3617 	index = phy_rate & 0xf;
3618 	basic_index = basic_phy_rate & 0xf;
3619 
3620 	/* Find the SHM pointer to the ACK rate entry by looking in the
3621 	 * Direct-map Table
3622 	 */
3623 	basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3624 
3625 	/* Update the SHM BSS-basic-rate-set mapping table with the pointer
3626 	 * to the correct basic rate for the given incoming rate
3627 	 */
3628 	brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3629 }
3630 
3631 static const struct brcms_c_rateset *
brcms_c_rateset_get_hwrs(struct brcms_c_info * wlc)3632 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3633 {
3634 	const struct brcms_c_rateset *rs_dflt;
3635 
3636 	if (BRCMS_PHY_11N_CAP(wlc->band)) {
3637 		if (wlc->band->bandtype == BRCM_BAND_5G)
3638 			rs_dflt = &ofdm_mimo_rates;
3639 		else
3640 			rs_dflt = &cck_ofdm_mimo_rates;
3641 	} else if (wlc->band->gmode)
3642 		rs_dflt = &cck_ofdm_rates;
3643 	else
3644 		rs_dflt = &cck_rates;
3645 
3646 	return rs_dflt;
3647 }
3648 
brcms_c_set_ratetable(struct brcms_c_info * wlc)3649 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3650 {
3651 	const struct brcms_c_rateset *rs_dflt;
3652 	struct brcms_c_rateset rs;
3653 	u8 rate, basic_rate;
3654 	uint i;
3655 
3656 	rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3657 
3658 	brcms_c_rateset_copy(rs_dflt, &rs);
3659 	brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3660 
3661 	/* walk the phy rate table and update SHM basic rate lookup table */
3662 	for (i = 0; i < rs.count; i++) {
3663 		rate = rs.rates[i] & BRCMS_RATE_MASK;
3664 
3665 		/* for a given rate brcms_basic_rate returns the rate at
3666 		 * which a response ACK/CTS should be sent.
3667 		 */
3668 		basic_rate = brcms_basic_rate(wlc, rate);
3669 		if (basic_rate == 0)
3670 			/* This should only happen if we are using a
3671 			 * restricted rateset.
3672 			 */
3673 			basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3674 
3675 		brcms_c_write_rate_shm(wlc, rate, basic_rate);
3676 	}
3677 }
3678 
3679 /* band-specific init */
brcms_c_bsinit(struct brcms_c_info * wlc)3680 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3681 {
3682 	brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3683 		       wlc->pub->unit, wlc->band->bandunit);
3684 
3685 	/* write ucode ACK/CTS rate table */
3686 	brcms_c_set_ratetable(wlc);
3687 
3688 	/* update some band specific mac configuration */
3689 	brcms_c_ucode_mac_upd(wlc);
3690 
3691 	/* init antenna selection */
3692 	brcms_c_antsel_init(wlc->asi);
3693 
3694 }
3695 
3696 /* formula:  IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3697 static int
brcms_c_duty_cycle_set(struct brcms_c_info * wlc,int duty_cycle,bool isOFDM,bool writeToShm)3698 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3699 		   bool writeToShm)
3700 {
3701 	int idle_busy_ratio_x_16 = 0;
3702 	uint offset =
3703 	    isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3704 	    M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3705 	if (duty_cycle > 100 || duty_cycle < 0) {
3706 		brcms_err(wlc->hw->d11core,
3707 			  "wl%d:  duty cycle value off limit\n",
3708 			  wlc->pub->unit);
3709 		return -EINVAL;
3710 	}
3711 	if (duty_cycle)
3712 		idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3713 	/* Only write to shared memory  when wl is up */
3714 	if (writeToShm)
3715 		brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3716 
3717 	if (isOFDM)
3718 		wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3719 	else
3720 		wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3721 
3722 	return 0;
3723 }
3724 
3725 /* push sw hps and wake state through hardware */
brcms_c_set_ps_ctrl(struct brcms_c_info * wlc)3726 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3727 {
3728 	u32 v1, v2;
3729 	bool hps;
3730 	bool awake_before;
3731 
3732 	hps = brcms_c_ps_allowed(wlc);
3733 
3734 	brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3735 			   hps);
3736 
3737 	v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3738 	v2 = MCTL_WAKE;
3739 	if (hps)
3740 		v2 |= MCTL_HPS;
3741 
3742 	brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3743 
3744 	awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3745 
3746 	if (!awake_before)
3747 		brcms_b_wait_for_wake(wlc->hw);
3748 }
3749 
3750 /*
3751  * Write this BSS config's MAC address to core.
3752  * Updates RXE match engine.
3753  */
brcms_c_set_mac(struct brcms_bss_cfg * bsscfg)3754 static void brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3755 {
3756 	struct brcms_c_info *wlc = bsscfg->wlc;
3757 
3758 	/* enter the MAC addr into the RXE match registers */
3759 	brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, wlc->pub->cur_etheraddr);
3760 
3761 	brcms_c_ampdu_macaddr_upd(wlc);
3762 }
3763 
3764 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3765  * Updates RXE match engine.
3766  */
brcms_c_set_bssid(struct brcms_bss_cfg * bsscfg)3767 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3768 {
3769 	/* we need to update BSSID in RXE match registers */
3770 	brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3771 }
3772 
brcms_c_set_ssid(struct brcms_c_info * wlc,u8 * ssid,size_t ssid_len)3773 void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid, size_t ssid_len)
3774 {
3775 	u8 len = min_t(u8, sizeof(wlc->bsscfg->SSID), ssid_len);
3776 	memset(wlc->bsscfg->SSID, 0, sizeof(wlc->bsscfg->SSID));
3777 
3778 	memcpy(wlc->bsscfg->SSID, ssid, len);
3779 	wlc->bsscfg->SSID_len = len;
3780 }
3781 
brcms_b_set_shortslot(struct brcms_hardware * wlc_hw,bool shortslot)3782 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3783 {
3784 	wlc_hw->shortslot = shortslot;
3785 
3786 	if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3787 		brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3788 		brcms_b_update_slot_timing(wlc_hw, shortslot);
3789 		brcms_c_enable_mac(wlc_hw->wlc);
3790 	}
3791 }
3792 
3793 /*
3794  * Suspend the MAC and update the slot timing
3795  * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3796  */
brcms_c_switch_shortslot(struct brcms_c_info * wlc,bool shortslot)3797 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3798 {
3799 	/* use the override if it is set */
3800 	if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3801 		shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3802 
3803 	if (wlc->shortslot == shortslot)
3804 		return;
3805 
3806 	wlc->shortslot = shortslot;
3807 
3808 	brcms_b_set_shortslot(wlc->hw, shortslot);
3809 }
3810 
brcms_c_set_home_chanspec(struct brcms_c_info * wlc,u16 chanspec)3811 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3812 {
3813 	if (wlc->home_chanspec != chanspec) {
3814 		wlc->home_chanspec = chanspec;
3815 
3816 		if (wlc->pub->associated)
3817 			wlc->bsscfg->current_bss->chanspec = chanspec;
3818 	}
3819 }
3820 
3821 void
brcms_b_set_chanspec(struct brcms_hardware * wlc_hw,u16 chanspec,bool mute_tx,struct txpwr_limits * txpwr)3822 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3823 		      bool mute_tx, struct txpwr_limits *txpwr)
3824 {
3825 	uint bandunit;
3826 
3827 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3828 			   chanspec);
3829 
3830 	wlc_hw->chanspec = chanspec;
3831 
3832 	/* Switch bands if necessary */
3833 	if (wlc_hw->_nbands > 1) {
3834 		bandunit = chspec_bandunit(chanspec);
3835 		if (wlc_hw->band->bandunit != bandunit) {
3836 			/* brcms_b_setband disables other bandunit,
3837 			 *  use light band switch if not up yet
3838 			 */
3839 			if (wlc_hw->up) {
3840 				wlc_phy_chanspec_radio_set(wlc_hw->
3841 							   bandstate[bandunit]->
3842 							   pi, chanspec);
3843 				brcms_b_setband(wlc_hw, bandunit, chanspec);
3844 			} else {
3845 				brcms_c_setxband(wlc_hw, bandunit);
3846 			}
3847 		}
3848 	}
3849 
3850 	wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3851 
3852 	if (!wlc_hw->up) {
3853 		if (wlc_hw->clk)
3854 			wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3855 						  chanspec);
3856 		wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3857 	} else {
3858 		wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3859 		wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3860 
3861 		/* Update muting of the channel */
3862 		brcms_b_mute(wlc_hw, mute_tx);
3863 	}
3864 }
3865 
3866 /* switch to and initialize new band */
brcms_c_setband(struct brcms_c_info * wlc,uint bandunit)3867 static void brcms_c_setband(struct brcms_c_info *wlc,
3868 					   uint bandunit)
3869 {
3870 	wlc->band = wlc->bandstate[bandunit];
3871 
3872 	if (!wlc->pub->up)
3873 		return;
3874 
3875 	/* wait for at least one beacon before entering sleeping state */
3876 	brcms_c_set_ps_ctrl(wlc);
3877 
3878 	/* band-specific initializations */
3879 	brcms_c_bsinit(wlc);
3880 }
3881 
brcms_c_set_chanspec(struct brcms_c_info * wlc,u16 chanspec)3882 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3883 {
3884 	uint bandunit;
3885 	u16 old_chanspec = wlc->chanspec;
3886 
3887 	if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3888 		brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3889 			  wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3890 		return;
3891 	}
3892 
3893 	/* Switch bands if necessary */
3894 	if (wlc->pub->_nbands > 1) {
3895 		bandunit = chspec_bandunit(chanspec);
3896 		if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3897 			if (wlc->bandlocked) {
3898 				brcms_err(wlc->hw->d11core,
3899 					  "wl%d: %s: chspec %d band is locked!\n",
3900 					  wlc->pub->unit, __func__,
3901 					  CHSPEC_CHANNEL(chanspec));
3902 				return;
3903 			}
3904 			/*
3905 			 * should the setband call come after the
3906 			 * brcms_b_chanspec() ? if the setband updates
3907 			 * (brcms_c_bsinit) use low level calls to inspect and
3908 			 * set state, the state inspected may be from the wrong
3909 			 * band, or the following brcms_b_set_chanspec() may
3910 			 * undo the work.
3911 			 */
3912 			brcms_c_setband(wlc, bandunit);
3913 		}
3914 	}
3915 
3916 	/* sync up phy/radio chanspec */
3917 	brcms_c_set_phy_chanspec(wlc, chanspec);
3918 
3919 	/* init antenna selection */
3920 	if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3921 		brcms_c_antsel_init(wlc->asi);
3922 
3923 		/* Fix the hardware rateset based on bw.
3924 		 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3925 		 */
3926 		brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3927 			wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3928 	}
3929 
3930 	/* update some mac configuration since chanspec changed */
3931 	brcms_c_ucode_mac_upd(wlc);
3932 }
3933 
3934 /*
3935  * This function changes the phytxctl for beacon based on current
3936  * beacon ratespec AND txant setting as per this table:
3937  *  ratespec     CCK		ant = wlc->stf->txant
3938  *		OFDM		ant = 3
3939  */
brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info * wlc,u32 bcn_rspec)3940 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3941 				       u32 bcn_rspec)
3942 {
3943 	u16 phyctl;
3944 	u16 phytxant = wlc->stf->phytxant;
3945 	u16 mask = PHY_TXC_ANT_MASK;
3946 
3947 	/* for non-siso rates or default setting, use the available chains */
3948 	if (BRCMS_PHY_11N_CAP(wlc->band))
3949 		phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3950 
3951 	phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3952 	phyctl = (phyctl & ~mask) | phytxant;
3953 	brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3954 }
3955 
3956 /*
3957  * centralized protection config change function to simplify debugging, no
3958  * consistency checking this should be called only on changes to avoid overhead
3959  * in periodic function
3960  */
brcms_c_protection_upd(struct brcms_c_info * wlc,uint idx,int val)3961 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3962 {
3963 	/*
3964 	 * Cannot use brcms_dbg_* here because this function is called
3965 	 * before wlc is sufficiently initialized.
3966 	 */
3967 	BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3968 
3969 	switch (idx) {
3970 	case BRCMS_PROT_G_SPEC:
3971 		wlc->protection->_g = (bool) val;
3972 		break;
3973 	case BRCMS_PROT_G_OVR:
3974 		wlc->protection->g_override = (s8) val;
3975 		break;
3976 	case BRCMS_PROT_G_USER:
3977 		wlc->protection->gmode_user = (u8) val;
3978 		break;
3979 	case BRCMS_PROT_OVERLAP:
3980 		wlc->protection->overlap = (s8) val;
3981 		break;
3982 	case BRCMS_PROT_N_USER:
3983 		wlc->protection->nmode_user = (s8) val;
3984 		break;
3985 	case BRCMS_PROT_N_CFG:
3986 		wlc->protection->n_cfg = (s8) val;
3987 		break;
3988 	case BRCMS_PROT_N_CFG_OVR:
3989 		wlc->protection->n_cfg_override = (s8) val;
3990 		break;
3991 	case BRCMS_PROT_N_NONGF:
3992 		wlc->protection->nongf = (bool) val;
3993 		break;
3994 	case BRCMS_PROT_N_NONGF_OVR:
3995 		wlc->protection->nongf_override = (s8) val;
3996 		break;
3997 	case BRCMS_PROT_N_PAM_OVR:
3998 		wlc->protection->n_pam_override = (s8) val;
3999 		break;
4000 	case BRCMS_PROT_N_OBSS:
4001 		wlc->protection->n_obss = (bool) val;
4002 		break;
4003 
4004 	default:
4005 		break;
4006 	}
4007 
4008 }
4009 
brcms_c_ht_update_sgi_rx(struct brcms_c_info * wlc,int val)4010 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4011 {
4012 	if (wlc->pub->up) {
4013 		brcms_c_update_beacon(wlc);
4014 		brcms_c_update_probe_resp(wlc, true);
4015 	}
4016 }
4017 
brcms_c_ht_update_ldpc(struct brcms_c_info * wlc,s8 val)4018 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4019 {
4020 	wlc->stf->ldpc = val;
4021 
4022 	if (wlc->pub->up) {
4023 		brcms_c_update_beacon(wlc);
4024 		brcms_c_update_probe_resp(wlc, true);
4025 		wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4026 	}
4027 }
4028 
brcms_c_wme_setparams(struct brcms_c_info * wlc,u16 aci,const struct ieee80211_tx_queue_params * params,bool suspend)4029 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4030 		       const struct ieee80211_tx_queue_params *params,
4031 		       bool suspend)
4032 {
4033 	int i;
4034 	struct shm_acparams acp_shm;
4035 	u16 *shm_entry;
4036 
4037 	/* Only apply params if the core is out of reset and has clocks */
4038 	if (!wlc->clk) {
4039 		brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4040 			  wlc->pub->unit, __func__);
4041 		return;
4042 	}
4043 
4044 	memset(&acp_shm, 0, sizeof(struct shm_acparams));
4045 	/* fill in shm ac params struct */
4046 	acp_shm.txop = params->txop;
4047 	/* convert from units of 32us to us for ucode */
4048 	wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4049 	    EDCF_TXOP2USEC(acp_shm.txop);
4050 	acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4051 
4052 	if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4053 	    && acp_shm.aifs < EDCF_AIFSN_MAX)
4054 		acp_shm.aifs++;
4055 
4056 	if (acp_shm.aifs < EDCF_AIFSN_MIN
4057 	    || acp_shm.aifs > EDCF_AIFSN_MAX) {
4058 		brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4059 			  "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4060 	} else {
4061 		acp_shm.cwmin = params->cw_min;
4062 		acp_shm.cwmax = params->cw_max;
4063 		acp_shm.cwcur = acp_shm.cwmin;
4064 		acp_shm.bslots =
4065 			bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4066 			acp_shm.cwcur;
4067 		acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4068 		/* Indicate the new params to the ucode */
4069 		acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4070 						  wme_ac2fifo[aci] *
4071 						  M_EDCF_QLEN +
4072 						  M_EDCF_STATUS_OFF));
4073 		acp_shm.status |= WME_STATUS_NEWAC;
4074 
4075 		/* Fill in shm acparam table */
4076 		shm_entry = (u16 *) &acp_shm;
4077 		for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4078 			brcms_b_write_shm(wlc->hw,
4079 					  M_EDCF_QINFO +
4080 					  wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4081 					  *shm_entry++);
4082 	}
4083 
4084 	if (suspend)
4085 		brcms_c_suspend_mac_and_wait(wlc);
4086 
4087 	brcms_c_update_beacon(wlc);
4088 	brcms_c_update_probe_resp(wlc, false);
4089 
4090 	if (suspend)
4091 		brcms_c_enable_mac(wlc);
4092 }
4093 
brcms_c_edcf_setparams(struct brcms_c_info * wlc,bool suspend)4094 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4095 {
4096 	u16 aci;
4097 	int i_ac;
4098 	struct ieee80211_tx_queue_params txq_pars;
4099 	static const struct edcf_acparam default_edcf_acparams[] = {
4100 		 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4101 		 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4102 		 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4103 		 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4104 	}; /* ucode needs these parameters during its initialization */
4105 	const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4106 
4107 	for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4108 		/* find out which ac this set of params applies to */
4109 		aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4110 
4111 		/* fill in shm ac params struct */
4112 		txq_pars.txop = edcf_acp->TXOP;
4113 		txq_pars.aifs = edcf_acp->ACI;
4114 
4115 		/* CWmin = 2^(ECWmin) - 1 */
4116 		txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4117 		/* CWmax = 2^(ECWmax) - 1 */
4118 		txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4119 					    >> EDCF_ECWMAX_SHIFT);
4120 		brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4121 	}
4122 
4123 	if (suspend) {
4124 		brcms_c_suspend_mac_and_wait(wlc);
4125 		brcms_c_enable_mac(wlc);
4126 	}
4127 }
4128 
brcms_c_radio_monitor_start(struct brcms_c_info * wlc)4129 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4130 {
4131 	/* Don't start the timer if HWRADIO feature is disabled */
4132 	if (wlc->radio_monitor)
4133 		return;
4134 
4135 	wlc->radio_monitor = true;
4136 	brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4137 	brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4138 }
4139 
brcms_c_radio_monitor_stop(struct brcms_c_info * wlc)4140 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4141 {
4142 	if (!wlc->radio_monitor)
4143 		return true;
4144 
4145 	wlc->radio_monitor = false;
4146 	brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4147 	return brcms_del_timer(wlc->radio_timer);
4148 }
4149 
4150 /* read hwdisable state and propagate to wlc flag */
brcms_c_radio_hwdisable_upd(struct brcms_c_info * wlc)4151 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4152 {
4153 	if (wlc->pub->hw_off)
4154 		return;
4155 
4156 	if (brcms_b_radio_read_hwdisabled(wlc->hw))
4157 		mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4158 	else
4159 		mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4160 }
4161 
4162 /* update hwradio status and return it */
brcms_c_check_radio_disabled(struct brcms_c_info * wlc)4163 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4164 {
4165 	brcms_c_radio_hwdisable_upd(wlc);
4166 
4167 	return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4168 			true : false;
4169 }
4170 
4171 /* periodical query hw radio button while driver is "down" */
brcms_c_radio_timer(void * arg)4172 static void brcms_c_radio_timer(void *arg)
4173 {
4174 	struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4175 
4176 	if (brcms_deviceremoved(wlc)) {
4177 		brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4178 			  wlc->pub->unit, __func__);
4179 		brcms_down(wlc->wl);
4180 		return;
4181 	}
4182 
4183 	brcms_c_radio_hwdisable_upd(wlc);
4184 }
4185 
4186 /* common low-level watchdog code */
brcms_b_watchdog(struct brcms_c_info * wlc)4187 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4188 {
4189 	struct brcms_hardware *wlc_hw = wlc->hw;
4190 
4191 	if (!wlc_hw->up)
4192 		return;
4193 
4194 	/* increment second count */
4195 	wlc_hw->now++;
4196 
4197 	/* Check for FIFO error interrupts */
4198 	brcms_b_fifoerrors(wlc_hw);
4199 
4200 	/* make sure RX dma has buffers */
4201 	dma_rxfill(wlc->hw->di[RX_FIFO]);
4202 
4203 	wlc_phy_watchdog(wlc_hw->band->pi);
4204 }
4205 
4206 /* common watchdog code */
brcms_c_watchdog(struct brcms_c_info * wlc)4207 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4208 {
4209 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4210 
4211 	if (!wlc->pub->up)
4212 		return;
4213 
4214 	if (brcms_deviceremoved(wlc)) {
4215 		brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4216 			  wlc->pub->unit, __func__);
4217 		brcms_down(wlc->wl);
4218 		return;
4219 	}
4220 
4221 	/* increment second count */
4222 	wlc->pub->now++;
4223 
4224 	brcms_c_radio_hwdisable_upd(wlc);
4225 	/* if radio is disable, driver may be down, quit here */
4226 	if (wlc->pub->radio_disabled)
4227 		return;
4228 
4229 	brcms_b_watchdog(wlc);
4230 
4231 	/*
4232 	 * occasionally sample mac stat counters to
4233 	 * detect 16-bit counter wrap
4234 	 */
4235 	if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4236 		brcms_c_statsupd(wlc);
4237 
4238 	if (BRCMS_ISNPHY(wlc->band) &&
4239 	    ((wlc->pub->now - wlc->tempsense_lasttime) >=
4240 	     BRCMS_TEMPSENSE_PERIOD)) {
4241 		wlc->tempsense_lasttime = wlc->pub->now;
4242 		brcms_c_tempsense_upd(wlc);
4243 	}
4244 }
4245 
brcms_c_watchdog_by_timer(void * arg)4246 static void brcms_c_watchdog_by_timer(void *arg)
4247 {
4248 	struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4249 
4250 	brcms_c_watchdog(wlc);
4251 }
4252 
brcms_c_timers_init(struct brcms_c_info * wlc,int unit)4253 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4254 {
4255 	wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4256 		wlc, "watchdog");
4257 	if (!wlc->wdtimer) {
4258 		wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for wdtimer "
4259 			  "failed\n", unit);
4260 		goto fail;
4261 	}
4262 
4263 	wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4264 		wlc, "radio");
4265 	if (!wlc->radio_timer) {
4266 		wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for radio_timer "
4267 			  "failed\n", unit);
4268 		goto fail;
4269 	}
4270 
4271 	return true;
4272 
4273  fail:
4274 	return false;
4275 }
4276 
4277 /*
4278  * Initialize brcms_c_info default values ...
4279  * may get overrides later in this function
4280  */
brcms_c_info_init(struct brcms_c_info * wlc,int unit)4281 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4282 {
4283 	int i;
4284 
4285 	/* Save our copy of the chanspec */
4286 	wlc->chanspec = ch20mhz_chspec(1);
4287 
4288 	/* various 802.11g modes */
4289 	wlc->shortslot = false;
4290 	wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4291 
4292 	brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4293 	brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4294 
4295 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4296 			       BRCMS_PROTECTION_AUTO);
4297 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4298 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4299 			       BRCMS_PROTECTION_AUTO);
4300 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4301 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4302 
4303 	brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4304 			       BRCMS_PROTECTION_CTL_OVERLAP);
4305 
4306 	/* 802.11g draft 4.0 NonERP elt advertisement */
4307 	wlc->include_legacy_erp = true;
4308 
4309 	wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4310 	wlc->stf->txant = ANT_TX_DEF;
4311 
4312 	wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4313 
4314 	wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4315 	for (i = 0; i < NFIFO; i++)
4316 		wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4317 	wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4318 
4319 	/* default rate fallback retry limits */
4320 	wlc->SFBL = RETRY_SHORT_FB;
4321 	wlc->LFBL = RETRY_LONG_FB;
4322 
4323 	/* default mac retry limits */
4324 	wlc->SRL = RETRY_SHORT_DEF;
4325 	wlc->LRL = RETRY_LONG_DEF;
4326 
4327 	/* WME QoS mode is Auto by default */
4328 	wlc->pub->_ampdu = AMPDU_AGG_HOST;
4329 }
4330 
brcms_c_attach_module(struct brcms_c_info * wlc)4331 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4332 {
4333 	uint err = 0;
4334 	uint unit;
4335 	unit = wlc->pub->unit;
4336 
4337 	wlc->asi = brcms_c_antsel_attach(wlc);
4338 	if (wlc->asi == NULL) {
4339 		wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4340 			  "failed\n", unit);
4341 		err = 44;
4342 		goto fail;
4343 	}
4344 
4345 	wlc->ampdu = brcms_c_ampdu_attach(wlc);
4346 	if (wlc->ampdu == NULL) {
4347 		wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4348 			  "failed\n", unit);
4349 		err = 50;
4350 		goto fail;
4351 	}
4352 
4353 	if ((brcms_c_stf_attach(wlc) != 0)) {
4354 		wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4355 			  "failed\n", unit);
4356 		err = 68;
4357 		goto fail;
4358 	}
4359  fail:
4360 	return err;
4361 }
4362 
brcms_c_pub(struct brcms_c_info * wlc)4363 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4364 {
4365 	return wlc->pub;
4366 }
4367 
4368 /* low level attach
4369  *    run backplane attach, init nvram
4370  *    run phy attach
4371  *    initialize software state for each core and band
4372  *    put the whole chip in reset(driver down state), no clock
4373  */
brcms_b_attach(struct brcms_c_info * wlc,struct bcma_device * core,uint unit,bool piomode)4374 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4375 			  uint unit, bool piomode)
4376 {
4377 	struct brcms_hardware *wlc_hw;
4378 	uint err = 0;
4379 	uint j;
4380 	bool wme = false;
4381 	struct shared_phy_params sha_params;
4382 	struct wiphy *wiphy = wlc->wiphy;
4383 	struct pci_dev *pcidev = core->bus->host_pci;
4384 	struct ssb_sprom *sprom = &core->bus->sprom;
4385 
4386 	if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4387 		brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4388 			       pcidev->vendor,
4389 			       pcidev->device);
4390 	else
4391 		brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4392 			       core->bus->boardinfo.vendor,
4393 			       core->bus->boardinfo.type);
4394 
4395 	wme = true;
4396 
4397 	wlc_hw = wlc->hw;
4398 	wlc_hw->wlc = wlc;
4399 	wlc_hw->unit = unit;
4400 	wlc_hw->band = wlc_hw->bandstate[0];
4401 	wlc_hw->_piomode = piomode;
4402 
4403 	/* populate struct brcms_hardware with default values  */
4404 	brcms_b_info_init(wlc_hw);
4405 
4406 	/*
4407 	 * Do the hardware portion of the attach. Also initialize software
4408 	 * state that depends on the particular hardware we are running.
4409 	 */
4410 	wlc_hw->sih = ai_attach(core->bus);
4411 	if (wlc_hw->sih == NULL) {
4412 		wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4413 			  unit);
4414 		err = 11;
4415 		goto fail;
4416 	}
4417 
4418 	/* verify again the device is supported */
4419 	if (!brcms_c_chipmatch(core)) {
4420 		wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4421 			 unit);
4422 		err = 12;
4423 		goto fail;
4424 	}
4425 
4426 	if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4427 		wlc_hw->vendorid = pcidev->vendor;
4428 		wlc_hw->deviceid = pcidev->device;
4429 	} else {
4430 		wlc_hw->vendorid = core->bus->boardinfo.vendor;
4431 		wlc_hw->deviceid = core->bus->boardinfo.type;
4432 	}
4433 
4434 	wlc_hw->d11core = core;
4435 	wlc_hw->corerev = core->id.rev;
4436 
4437 	/* validate chip, chiprev and corerev */
4438 	if (!brcms_c_isgoodchip(wlc_hw)) {
4439 		err = 13;
4440 		goto fail;
4441 	}
4442 
4443 	/* initialize power control registers */
4444 	ai_clkctl_init(wlc_hw->sih);
4445 
4446 	/* request fastclock and force fastclock for the rest of attach
4447 	 * bring the d11 core out of reset.
4448 	 *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4449 	 *   is still false; But it will be called again inside wlc_corereset,
4450 	 *   after d11 is out of reset.
4451 	 */
4452 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4453 	brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4454 
4455 	if (!brcms_b_validate_chip_access(wlc_hw)) {
4456 		wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4457 			"failed\n", unit);
4458 		err = 14;
4459 		goto fail;
4460 	}
4461 
4462 	/* get the board rev, used just below */
4463 	j = sprom->board_rev;
4464 	/* promote srom boardrev of 0xFF to 1 */
4465 	if (j == BOARDREV_PROMOTABLE)
4466 		j = BOARDREV_PROMOTED;
4467 	wlc_hw->boardrev = (u16) j;
4468 	if (!brcms_c_validboardtype(wlc_hw)) {
4469 		wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4470 			  "board type (0x%x)" " or revision level (0x%x)\n",
4471 			  unit, ai_get_boardtype(wlc_hw->sih),
4472 			  wlc_hw->boardrev);
4473 		err = 15;
4474 		goto fail;
4475 	}
4476 	wlc_hw->sromrev = sprom->revision;
4477 	wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4478 	wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4479 
4480 	if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4481 		brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4482 
4483 	/* check device id(srom, nvram etc.) to set bands */
4484 	if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4485 	    wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4486 	    wlc_hw->deviceid == BCM43224_CHIP_ID)
4487 		/* Dualband boards */
4488 		wlc_hw->_nbands = 2;
4489 	else
4490 		wlc_hw->_nbands = 1;
4491 
4492 	if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4493 		wlc_hw->_nbands = 1;
4494 
4495 	/* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4496 	 * unconditionally does the init of these values
4497 	 */
4498 	wlc->vendorid = wlc_hw->vendorid;
4499 	wlc->deviceid = wlc_hw->deviceid;
4500 	wlc->pub->sih = wlc_hw->sih;
4501 	wlc->pub->corerev = wlc_hw->corerev;
4502 	wlc->pub->sromrev = wlc_hw->sromrev;
4503 	wlc->pub->boardrev = wlc_hw->boardrev;
4504 	wlc->pub->boardflags = wlc_hw->boardflags;
4505 	wlc->pub->boardflags2 = wlc_hw->boardflags2;
4506 	wlc->pub->_nbands = wlc_hw->_nbands;
4507 
4508 	wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4509 
4510 	if (wlc_hw->physhim == NULL) {
4511 		wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4512 			"failed\n", unit);
4513 		err = 25;
4514 		goto fail;
4515 	}
4516 
4517 	/* pass all the parameters to wlc_phy_shared_attach in one struct */
4518 	sha_params.sih = wlc_hw->sih;
4519 	sha_params.physhim = wlc_hw->physhim;
4520 	sha_params.unit = unit;
4521 	sha_params.corerev = wlc_hw->corerev;
4522 	sha_params.vid = wlc_hw->vendorid;
4523 	sha_params.did = wlc_hw->deviceid;
4524 	sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4525 	sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4526 	sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4527 	sha_params.sromrev = wlc_hw->sromrev;
4528 	sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4529 	sha_params.boardrev = wlc_hw->boardrev;
4530 	sha_params.boardflags = wlc_hw->boardflags;
4531 	sha_params.boardflags2 = wlc_hw->boardflags2;
4532 
4533 	/* alloc and save pointer to shared phy state area */
4534 	wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4535 	if (!wlc_hw->phy_sh) {
4536 		err = 16;
4537 		goto fail;
4538 	}
4539 
4540 	/* initialize software state for each core and band */
4541 	for (j = 0; j < wlc_hw->_nbands; j++) {
4542 		/*
4543 		 * band0 is always 2.4Ghz
4544 		 * band1, if present, is 5Ghz
4545 		 */
4546 
4547 		brcms_c_setxband(wlc_hw, j);
4548 
4549 		wlc_hw->band->bandunit = j;
4550 		wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4551 		wlc->band->bandunit = j;
4552 		wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4553 		wlc->core->coreidx = core->core_index;
4554 
4555 		wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4556 		wlc_hw->machwcap_backup = wlc_hw->machwcap;
4557 
4558 		/* init tx fifo size */
4559 		WARN_ON(wlc_hw->corerev < XMTFIFOTBL_STARTREV ||
4560 			(wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4561 				ARRAY_SIZE(xmtfifo_sz));
4562 		wlc_hw->xmtfifo_sz =
4563 		    xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4564 		WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4565 
4566 		/* Get a phy for this band */
4567 		wlc_hw->band->pi =
4568 			wlc_phy_attach(wlc_hw->phy_sh, core,
4569 				       wlc_hw->band->bandtype,
4570 				       wlc->wiphy);
4571 		if (wlc_hw->band->pi == NULL) {
4572 			wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4573 				  "attach failed\n", unit);
4574 			err = 17;
4575 			goto fail;
4576 		}
4577 
4578 		wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4579 
4580 		wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4581 				       &wlc_hw->band->phyrev,
4582 				       &wlc_hw->band->radioid,
4583 				       &wlc_hw->band->radiorev);
4584 		wlc_hw->band->abgphy_encore =
4585 		    wlc_phy_get_encore(wlc_hw->band->pi);
4586 		wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4587 		wlc_hw->band->core_flags =
4588 		    wlc_phy_get_coreflags(wlc_hw->band->pi);
4589 
4590 		/* verify good phy_type & supported phy revision */
4591 		if (BRCMS_ISNPHY(wlc_hw->band)) {
4592 			if (NCONF_HAS(wlc_hw->band->phyrev))
4593 				goto good_phy;
4594 			else
4595 				goto bad_phy;
4596 		} else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4597 			if (LCNCONF_HAS(wlc_hw->band->phyrev))
4598 				goto good_phy;
4599 			else
4600 				goto bad_phy;
4601 		} else {
4602  bad_phy:
4603 			wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4604 				  "phy type/rev (%d/%d)\n", unit,
4605 				  wlc_hw->band->phytype, wlc_hw->band->phyrev);
4606 			err = 18;
4607 			goto fail;
4608 		}
4609 
4610  good_phy:
4611 		/*
4612 		 * BMAC_NOTE: wlc->band->pi should not be set below and should
4613 		 * be done in the high level attach. However we can not make
4614 		 * that change until all low level access is changed to
4615 		 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4616 		 * keeping wlc_hw->band->pi as well for incremental update of
4617 		 * low level fns, and cut over low only init when all fns
4618 		 * updated.
4619 		 */
4620 		wlc->band->pi = wlc_hw->band->pi;
4621 		wlc->band->phytype = wlc_hw->band->phytype;
4622 		wlc->band->phyrev = wlc_hw->band->phyrev;
4623 		wlc->band->radioid = wlc_hw->band->radioid;
4624 		wlc->band->radiorev = wlc_hw->band->radiorev;
4625 		brcms_dbg_info(core, "wl%d: phy %u/%u radio %x/%u\n", unit,
4626 			       wlc->band->phytype, wlc->band->phyrev,
4627 			       wlc->band->radioid, wlc->band->radiorev);
4628 		/* default contention windows size limits */
4629 		wlc_hw->band->CWmin = APHY_CWMIN;
4630 		wlc_hw->band->CWmax = PHY_CWMAX;
4631 
4632 		if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4633 			err = 19;
4634 			goto fail;
4635 		}
4636 	}
4637 
4638 	/* disable core to match driver "down" state */
4639 	brcms_c_coredisable(wlc_hw);
4640 
4641 	/* Match driver "down" state */
4642 	bcma_host_pci_down(wlc_hw->d11core->bus);
4643 
4644 	/* turn off pll and xtal to match driver "down" state */
4645 	brcms_b_xtal(wlc_hw, OFF);
4646 
4647 	/* *******************************************************************
4648 	 * The hardware is in the DOWN state at this point. D11 core
4649 	 * or cores are in reset with clocks off, and the board PLLs
4650 	 * are off if possible.
4651 	 *
4652 	 * Beyond this point, wlc->sbclk == false and chip registers
4653 	 * should not be touched.
4654 	 *********************************************************************
4655 	 */
4656 
4657 	/* init etheraddr state variables */
4658 	brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4659 
4660 	if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4661 	    is_zero_ether_addr(wlc_hw->etheraddr)) {
4662 		wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4663 			  unit);
4664 		err = 22;
4665 		goto fail;
4666 	}
4667 
4668 	brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4669 		       wlc_hw->deviceid, wlc_hw->_nbands,
4670 		       ai_get_boardtype(wlc_hw->sih));
4671 
4672 	return err;
4673 
4674  fail:
4675 	wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4676 		  err);
4677 	return err;
4678 }
4679 
brcms_c_attach_stf_ant_init(struct brcms_c_info * wlc)4680 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4681 {
4682 	int aa;
4683 	uint unit;
4684 	int bandtype;
4685 	struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4686 
4687 	unit = wlc->pub->unit;
4688 	bandtype = wlc->band->bandtype;
4689 
4690 	/* get antennas available */
4691 	if (bandtype == BRCM_BAND_5G)
4692 		aa = sprom->ant_available_a;
4693 	else
4694 		aa = sprom->ant_available_bg;
4695 
4696 	if ((aa < 1) || (aa > 15)) {
4697 		wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4698 			  " srom (0x%x), using 3\n", unit, __func__, aa);
4699 		aa = 3;
4700 	}
4701 
4702 	/* reset the defaults if we have a single antenna */
4703 	if (aa == 1) {
4704 		wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4705 		wlc->stf->txant = ANT_TX_FORCE_0;
4706 	} else if (aa == 2) {
4707 		wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4708 		wlc->stf->txant = ANT_TX_FORCE_1;
4709 	} else {
4710 	}
4711 
4712 	/* Compute Antenna Gain */
4713 	if (bandtype == BRCM_BAND_5G)
4714 		wlc->band->antgain = sprom->antenna_gain.a1;
4715 	else
4716 		wlc->band->antgain = sprom->antenna_gain.a0;
4717 
4718 	return true;
4719 }
4720 
brcms_c_bss_default_init(struct brcms_c_info * wlc)4721 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4722 {
4723 	u16 chanspec;
4724 	struct brcms_band *band;
4725 	struct brcms_bss_info *bi = wlc->default_bss;
4726 
4727 	/* init default and target BSS with some sane initial values */
4728 	memset(bi, 0, sizeof(*bi));
4729 	bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4730 
4731 	/* fill the default channel as the first valid channel
4732 	 * starting from the 2G channels
4733 	 */
4734 	chanspec = ch20mhz_chspec(1);
4735 	wlc->home_chanspec = bi->chanspec = chanspec;
4736 
4737 	/* find the band of our default channel */
4738 	band = wlc->band;
4739 	if (wlc->pub->_nbands > 1 &&
4740 	    band->bandunit != chspec_bandunit(chanspec))
4741 		band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4742 
4743 	/* init bss rates to the band specific default rate set */
4744 	brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4745 		band->bandtype, false, BRCMS_RATE_MASK_FULL,
4746 		(bool) (wlc->pub->_n_enab & SUPPORT_11N),
4747 		brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4748 
4749 	if (wlc->pub->_n_enab & SUPPORT_11N)
4750 		bi->flags |= BRCMS_BSS_HT;
4751 }
4752 
brcms_c_update_mimo_band_bwcap(struct brcms_c_info * wlc,u8 bwcap)4753 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4754 {
4755 	uint i;
4756 	struct brcms_band *band;
4757 
4758 	for (i = 0; i < wlc->pub->_nbands; i++) {
4759 		band = wlc->bandstate[i];
4760 		if (band->bandtype == BRCM_BAND_5G) {
4761 			if ((bwcap == BRCMS_N_BW_40ALL)
4762 			    || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4763 				band->mimo_cap_40 = true;
4764 			else
4765 				band->mimo_cap_40 = false;
4766 		} else {
4767 			if (bwcap == BRCMS_N_BW_40ALL)
4768 				band->mimo_cap_40 = true;
4769 			else
4770 				band->mimo_cap_40 = false;
4771 		}
4772 	}
4773 }
4774 
brcms_c_timers_deinit(struct brcms_c_info * wlc)4775 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4776 {
4777 	/* free timer state */
4778 	if (wlc->wdtimer) {
4779 		brcms_free_timer(wlc->wdtimer);
4780 		wlc->wdtimer = NULL;
4781 	}
4782 	if (wlc->radio_timer) {
4783 		brcms_free_timer(wlc->radio_timer);
4784 		wlc->radio_timer = NULL;
4785 	}
4786 }
4787 
brcms_c_detach_module(struct brcms_c_info * wlc)4788 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4789 {
4790 	if (wlc->asi) {
4791 		brcms_c_antsel_detach(wlc->asi);
4792 		wlc->asi = NULL;
4793 	}
4794 
4795 	if (wlc->ampdu) {
4796 		brcms_c_ampdu_detach(wlc->ampdu);
4797 		wlc->ampdu = NULL;
4798 	}
4799 
4800 	brcms_c_stf_detach(wlc);
4801 }
4802 
4803 /*
4804  * low level detach
4805  */
brcms_b_detach(struct brcms_c_info * wlc)4806 static void brcms_b_detach(struct brcms_c_info *wlc)
4807 {
4808 	uint i;
4809 	struct brcms_hw_band *band;
4810 	struct brcms_hardware *wlc_hw = wlc->hw;
4811 
4812 	brcms_b_detach_dmapio(wlc_hw);
4813 
4814 	band = wlc_hw->band;
4815 	for (i = 0; i < wlc_hw->_nbands; i++) {
4816 		if (band->pi) {
4817 			/* Detach this band's phy */
4818 			wlc_phy_detach(band->pi);
4819 			band->pi = NULL;
4820 		}
4821 		band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4822 	}
4823 
4824 	/* Free shared phy state */
4825 	kfree(wlc_hw->phy_sh);
4826 
4827 	wlc_phy_shim_detach(wlc_hw->physhim);
4828 
4829 	if (wlc_hw->sih) {
4830 		ai_detach(wlc_hw->sih);
4831 		wlc_hw->sih = NULL;
4832 	}
4833 }
4834 
4835 /*
4836  * Return a count of the number of driver callbacks still pending.
4837  *
4838  * General policy is that brcms_c_detach can only dealloc/free software states.
4839  * It can NOT touch hardware registers since the d11core may be in reset and
4840  * clock may not be available.
4841  * One exception is sb register access, which is possible if crystal is turned
4842  * on after "down" state, driver should avoid software timer with the exception
4843  * of radio_monitor.
4844  */
brcms_c_detach(struct brcms_c_info * wlc)4845 uint brcms_c_detach(struct brcms_c_info *wlc)
4846 {
4847 	uint callbacks;
4848 
4849 	if (wlc == NULL)
4850 		return 0;
4851 
4852 	brcms_b_detach(wlc);
4853 
4854 	/* delete software timers */
4855 	callbacks = 0;
4856 	if (!brcms_c_radio_monitor_stop(wlc))
4857 		callbacks++;
4858 
4859 	brcms_c_channel_mgr_detach(wlc->cmi);
4860 
4861 	brcms_c_timers_deinit(wlc);
4862 
4863 	brcms_c_detach_module(wlc);
4864 
4865 	brcms_c_detach_mfree(wlc);
4866 	return callbacks;
4867 }
4868 
4869 /* update state that depends on the current value of "ap" */
brcms_c_ap_upd(struct brcms_c_info * wlc)4870 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4871 {
4872 	/* STA-BSS; short capable */
4873 	wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4874 }
4875 
4876 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
brcms_b_hw_up(struct brcms_hardware * wlc_hw)4877 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4878 {
4879 	if (wlc_hw->wlc->pub->hw_up)
4880 		return;
4881 
4882 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4883 
4884 	/*
4885 	 * Enable pll and xtal, initialize the power control registers,
4886 	 * and force fastclock for the remainder of brcms_c_up().
4887 	 */
4888 	brcms_b_xtal(wlc_hw, ON);
4889 	ai_clkctl_init(wlc_hw->sih);
4890 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4891 
4892 	/*
4893 	 * TODO: test suspend/resume
4894 	 *
4895 	 * AI chip doesn't restore bar0win2 on
4896 	 * hibernation/resume, need sw fixup
4897 	 */
4898 
4899 	/*
4900 	 * Inform phy that a POR reset has occurred so
4901 	 * it does a complete phy init
4902 	 */
4903 	wlc_phy_por_inform(wlc_hw->band->pi);
4904 
4905 	wlc_hw->ucode_loaded = false;
4906 	wlc_hw->wlc->pub->hw_up = true;
4907 
4908 	if ((wlc_hw->boardflags & BFL_FEM)
4909 	    && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4910 		if (!
4911 		    (wlc_hw->boardrev >= 0x1250
4912 		     && (wlc_hw->boardflags & BFL_FEM_BT)))
4913 			ai_epa_4313war(wlc_hw->sih);
4914 	}
4915 }
4916 
brcms_b_up_prep(struct brcms_hardware * wlc_hw)4917 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4918 {
4919 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4920 
4921 	/*
4922 	 * Enable pll and xtal, initialize the power control registers,
4923 	 * and force fastclock for the remainder of brcms_c_up().
4924 	 */
4925 	brcms_b_xtal(wlc_hw, ON);
4926 	ai_clkctl_init(wlc_hw->sih);
4927 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4928 
4929 	/*
4930 	 * Configure pci/pcmcia here instead of in brcms_c_attach()
4931 	 * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
4932 	 */
4933 	bcma_host_pci_irq_ctl(wlc_hw->d11core->bus, wlc_hw->d11core,
4934 			      true);
4935 
4936 	/*
4937 	 * Need to read the hwradio status here to cover the case where the
4938 	 * system is loaded with the hw radio disabled. We do not want to
4939 	 * bring the driver up in this case.
4940 	 */
4941 	if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4942 		/* put SB PCI in down state again */
4943 		bcma_host_pci_down(wlc_hw->d11core->bus);
4944 		brcms_b_xtal(wlc_hw, OFF);
4945 		return -ENOMEDIUM;
4946 	}
4947 
4948 	bcma_host_pci_up(wlc_hw->d11core->bus);
4949 
4950 	/* reset the d11 core */
4951 	brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4952 
4953 	return 0;
4954 }
4955 
brcms_b_up_finish(struct brcms_hardware * wlc_hw)4956 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
4957 {
4958 	wlc_hw->up = true;
4959 	wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
4960 
4961 	/* FULLY enable dynamic power control and d11 core interrupt */
4962 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
4963 	brcms_intrson(wlc_hw->wlc->wl);
4964 	return 0;
4965 }
4966 
4967 /*
4968  * Write WME tunable parameters for retransmit/max rate
4969  * from wlc struct to ucode
4970  */
brcms_c_wme_retries_write(struct brcms_c_info * wlc)4971 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
4972 {
4973 	int ac;
4974 
4975 	/* Need clock to do this */
4976 	if (!wlc->clk)
4977 		return;
4978 
4979 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
4980 		brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
4981 				  wlc->wme_retries[ac]);
4982 }
4983 
4984 /* make interface operational */
brcms_c_up(struct brcms_c_info * wlc)4985 int brcms_c_up(struct brcms_c_info *wlc)
4986 {
4987 	struct ieee80211_channel *ch;
4988 
4989 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4990 
4991 	/* HW is turned off so don't try to access it */
4992 	if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
4993 		return -ENOMEDIUM;
4994 
4995 	if (!wlc->pub->hw_up) {
4996 		brcms_b_hw_up(wlc->hw);
4997 		wlc->pub->hw_up = true;
4998 	}
4999 
5000 	if ((wlc->pub->boardflags & BFL_FEM)
5001 	    && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5002 		if (wlc->pub->boardrev >= 0x1250
5003 		    && (wlc->pub->boardflags & BFL_FEM_BT))
5004 			brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5005 				MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5006 		else
5007 			brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5008 				    MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5009 	}
5010 
5011 	/*
5012 	 * Need to read the hwradio status here to cover the case where the
5013 	 * system is loaded with the hw radio disabled. We do not want to bring
5014 	 * the driver up in this case. If radio is disabled, abort up, lower
5015 	 * power, start radio timer and return 0(for NDIS) don't call
5016 	 * radio_update to avoid looping brcms_c_up.
5017 	 *
5018 	 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5019 	 */
5020 	if (!wlc->pub->radio_disabled) {
5021 		int status = brcms_b_up_prep(wlc->hw);
5022 		if (status == -ENOMEDIUM) {
5023 			if (!mboolisset
5024 			    (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5025 				struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5026 				mboolset(wlc->pub->radio_disabled,
5027 					 WL_RADIO_HW_DISABLE);
5028 				if (bsscfg->type == BRCMS_TYPE_STATION ||
5029 				    bsscfg->type == BRCMS_TYPE_ADHOC)
5030 					brcms_err(wlc->hw->d11core,
5031 						  "wl%d: up: rfdisable -> "
5032 						  "bsscfg_disable()\n",
5033 						   wlc->pub->unit);
5034 			}
5035 		}
5036 	}
5037 
5038 	if (wlc->pub->radio_disabled) {
5039 		brcms_c_radio_monitor_start(wlc);
5040 		return 0;
5041 	}
5042 
5043 	/* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5044 	wlc->clk = true;
5045 
5046 	brcms_c_radio_monitor_stop(wlc);
5047 
5048 	/* Set EDCF hostflags */
5049 	brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5050 
5051 	brcms_init(wlc->wl);
5052 	wlc->pub->up = true;
5053 
5054 	if (wlc->bandinit_pending) {
5055 		ch = wlc->pub->ieee_hw->conf.chandef.chan;
5056 		brcms_c_suspend_mac_and_wait(wlc);
5057 		brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5058 		wlc->bandinit_pending = false;
5059 		brcms_c_enable_mac(wlc);
5060 	}
5061 
5062 	brcms_b_up_finish(wlc->hw);
5063 
5064 	/* Program the TX wme params with the current settings */
5065 	brcms_c_wme_retries_write(wlc);
5066 
5067 	/* start one second watchdog timer */
5068 	brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5069 	wlc->WDarmed = true;
5070 
5071 	/* ensure antenna config is up to date */
5072 	brcms_c_stf_phy_txant_upd(wlc);
5073 	/* ensure LDPC config is in sync */
5074 	brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5075 
5076 	return 0;
5077 }
5078 
brcms_b_bmac_down_prep(struct brcms_hardware * wlc_hw)5079 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5080 {
5081 	bool dev_gone;
5082 	uint callbacks = 0;
5083 
5084 	if (!wlc_hw->up)
5085 		return callbacks;
5086 
5087 	dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5088 
5089 	/* disable interrupts */
5090 	if (dev_gone)
5091 		wlc_hw->wlc->macintmask = 0;
5092 	else {
5093 		/* now disable interrupts */
5094 		brcms_intrsoff(wlc_hw->wlc->wl);
5095 
5096 		/* ensure we're running on the pll clock again */
5097 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5098 	}
5099 	/* down phy at the last of this stage */
5100 	callbacks += wlc_phy_down(wlc_hw->band->pi);
5101 
5102 	return callbacks;
5103 }
5104 
brcms_b_down_finish(struct brcms_hardware * wlc_hw)5105 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5106 {
5107 	uint callbacks = 0;
5108 	bool dev_gone;
5109 
5110 	if (!wlc_hw->up)
5111 		return callbacks;
5112 
5113 	wlc_hw->up = false;
5114 	wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5115 
5116 	dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5117 
5118 	if (dev_gone) {
5119 		wlc_hw->sbclk = false;
5120 		wlc_hw->clk = false;
5121 		wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5122 
5123 		/* reclaim any posted packets */
5124 		brcms_c_flushqueues(wlc_hw->wlc);
5125 	} else {
5126 
5127 		/* Reset and disable the core */
5128 		if (bcma_core_is_enabled(wlc_hw->d11core)) {
5129 			if (bcma_read32(wlc_hw->d11core,
5130 					D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5131 				brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5132 			callbacks += brcms_reset(wlc_hw->wlc->wl);
5133 			brcms_c_coredisable(wlc_hw);
5134 		}
5135 
5136 		/* turn off primary xtal and pll */
5137 		if (!wlc_hw->noreset) {
5138 			bcma_host_pci_down(wlc_hw->d11core->bus);
5139 			brcms_b_xtal(wlc_hw, OFF);
5140 		}
5141 	}
5142 
5143 	return callbacks;
5144 }
5145 
5146 /*
5147  * Mark the interface nonoperational, stop the software mechanisms,
5148  * disable the hardware, free any transient buffer state.
5149  * Return a count of the number of driver callbacks still pending.
5150  */
brcms_c_down(struct brcms_c_info * wlc)5151 uint brcms_c_down(struct brcms_c_info *wlc)
5152 {
5153 
5154 	uint callbacks = 0;
5155 	int i;
5156 
5157 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5158 
5159 	/* check if we are already in the going down path */
5160 	if (wlc->going_down) {
5161 		brcms_err(wlc->hw->d11core,
5162 			  "wl%d: %s: Driver going down so return\n",
5163 			  wlc->pub->unit, __func__);
5164 		return 0;
5165 	}
5166 	if (!wlc->pub->up)
5167 		return callbacks;
5168 
5169 	wlc->going_down = true;
5170 
5171 	callbacks += brcms_b_bmac_down_prep(wlc->hw);
5172 
5173 	brcms_deviceremoved(wlc);
5174 
5175 	/* Call any registered down handlers */
5176 	for (i = 0; i < BRCMS_MAXMODULES; i++) {
5177 		if (wlc->modulecb[i].down_fn)
5178 			callbacks +=
5179 			    wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5180 	}
5181 
5182 	/* cancel the watchdog timer */
5183 	if (wlc->WDarmed) {
5184 		if (!brcms_del_timer(wlc->wdtimer))
5185 			callbacks++;
5186 		wlc->WDarmed = false;
5187 	}
5188 
5189 	wlc->pub->up = false;
5190 
5191 	wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5192 
5193 	callbacks += brcms_b_down_finish(wlc->hw);
5194 
5195 	/* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5196 	wlc->clk = false;
5197 
5198 	wlc->going_down = false;
5199 	return callbacks;
5200 }
5201 
5202 /* Set the current gmode configuration */
brcms_c_set_gmode(struct brcms_c_info * wlc,u8 gmode,bool config)5203 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5204 {
5205 	int ret = 0;
5206 	uint i;
5207 	struct brcms_c_rateset rs;
5208 	/* Default to 54g Auto */
5209 	/* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5210 	s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5211 	bool ofdm_basic = false;	/* Make 6, 12, and 24 basic rates */
5212 	struct brcms_band *band;
5213 
5214 	/* if N-support is enabled, allow Gmode set as long as requested
5215 	 * Gmode is not GMODE_LEGACY_B
5216 	 */
5217 	if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5218 		return -ENOTSUPP;
5219 
5220 	/* verify that we are dealing with 2G band and grab the band pointer */
5221 	if (wlc->band->bandtype == BRCM_BAND_2G)
5222 		band = wlc->band;
5223 	else if ((wlc->pub->_nbands > 1) &&
5224 		 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5225 		band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5226 	else
5227 		return -EINVAL;
5228 
5229 	/* update configuration value */
5230 	if (config)
5231 		brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5232 
5233 	/* Clear rateset override */
5234 	memset(&rs, 0, sizeof(rs));
5235 
5236 	switch (gmode) {
5237 	case GMODE_LEGACY_B:
5238 		shortslot = BRCMS_SHORTSLOT_OFF;
5239 		brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5240 
5241 		break;
5242 
5243 	case GMODE_LRS:
5244 		break;
5245 
5246 	case GMODE_AUTO:
5247 		/* Accept defaults */
5248 		break;
5249 
5250 	case GMODE_ONLY:
5251 		ofdm_basic = true;
5252 		break;
5253 
5254 	case GMODE_PERFORMANCE:
5255 		shortslot = BRCMS_SHORTSLOT_ON;
5256 		ofdm_basic = true;
5257 		break;
5258 
5259 	default:
5260 		/* Error */
5261 		brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5262 			  wlc->pub->unit, __func__, gmode);
5263 		return -ENOTSUPP;
5264 	}
5265 
5266 	band->gmode = gmode;
5267 
5268 	wlc->shortslot_override = shortslot;
5269 
5270 	/* Use the default 11g rateset */
5271 	if (!rs.count)
5272 		brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5273 
5274 	if (ofdm_basic) {
5275 		for (i = 0; i < rs.count; i++) {
5276 			if (rs.rates[i] == BRCM_RATE_6M
5277 			    || rs.rates[i] == BRCM_RATE_12M
5278 			    || rs.rates[i] == BRCM_RATE_24M)
5279 				rs.rates[i] |= BRCMS_RATE_FLAG;
5280 		}
5281 	}
5282 
5283 	/* Set default bss rateset */
5284 	wlc->default_bss->rateset.count = rs.count;
5285 	memcpy(wlc->default_bss->rateset.rates, rs.rates,
5286 	       sizeof(wlc->default_bss->rateset.rates));
5287 
5288 	return ret;
5289 }
5290 
brcms_c_set_nmode(struct brcms_c_info * wlc)5291 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5292 {
5293 	uint i;
5294 	s32 nmode = AUTO;
5295 
5296 	if (wlc->stf->txstreams == WL_11N_3x3)
5297 		nmode = WL_11N_3x3;
5298 	else
5299 		nmode = WL_11N_2x2;
5300 
5301 	/* force GMODE_AUTO if NMODE is ON */
5302 	brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5303 	if (nmode == WL_11N_3x3)
5304 		wlc->pub->_n_enab = SUPPORT_HT;
5305 	else
5306 		wlc->pub->_n_enab = SUPPORT_11N;
5307 	wlc->default_bss->flags |= BRCMS_BSS_HT;
5308 	/* add the mcs rates to the default and hw ratesets */
5309 	brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5310 			      wlc->stf->txstreams);
5311 	for (i = 0; i < wlc->pub->_nbands; i++)
5312 		memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5313 		       wlc->default_bss->rateset.mcs, MCSSET_LEN);
5314 
5315 	return 0;
5316 }
5317 
5318 static int
brcms_c_set_internal_rateset(struct brcms_c_info * wlc,struct brcms_c_rateset * rs_arg)5319 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5320 			     struct brcms_c_rateset *rs_arg)
5321 {
5322 	struct brcms_c_rateset rs, new;
5323 	uint bandunit;
5324 
5325 	memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5326 
5327 	/* check for bad count value */
5328 	if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5329 		return -EINVAL;
5330 
5331 	/* try the current band */
5332 	bandunit = wlc->band->bandunit;
5333 	memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5334 	if (brcms_c_rate_hwrs_filter_sort_validate
5335 	    (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5336 	     wlc->stf->txstreams))
5337 		goto good;
5338 
5339 	/* try the other band */
5340 	if (brcms_is_mband_unlocked(wlc)) {
5341 		bandunit = OTHERBANDUNIT(wlc);
5342 		memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5343 		if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5344 						       &wlc->
5345 						       bandstate[bandunit]->
5346 						       hw_rateset, true,
5347 						       wlc->stf->txstreams))
5348 			goto good;
5349 	}
5350 
5351 	return -EBADE;
5352 
5353  good:
5354 	/* apply new rateset */
5355 	memcpy(&wlc->default_bss->rateset, &new,
5356 	       sizeof(struct brcms_c_rateset));
5357 	memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5358 	       sizeof(struct brcms_c_rateset));
5359 	return 0;
5360 }
5361 
brcms_c_ofdm_rateset_war(struct brcms_c_info * wlc)5362 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5363 {
5364 	wlc_phy_ofdm_rateset_war(wlc->band->pi, false);
5365 }
5366 
brcms_c_set_channel(struct brcms_c_info * wlc,u16 channel)5367 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5368 {
5369 	u16 chspec = ch20mhz_chspec(channel);
5370 
5371 	if (channel > MAXCHANNEL)
5372 		return -EINVAL;
5373 
5374 	if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5375 		return -EINVAL;
5376 
5377 
5378 	if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5379 		if (wlc->band->bandunit != chspec_bandunit(chspec))
5380 			wlc->bandinit_pending = true;
5381 		else
5382 			wlc->bandinit_pending = false;
5383 	}
5384 
5385 	wlc->default_bss->chanspec = chspec;
5386 	/* brcms_c_BSSinit() will sanitize the rateset before
5387 	 * using it.. */
5388 	if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5389 		brcms_c_set_home_chanspec(wlc, chspec);
5390 		brcms_c_suspend_mac_and_wait(wlc);
5391 		brcms_c_set_chanspec(wlc, chspec);
5392 		brcms_c_enable_mac(wlc);
5393 	}
5394 	return 0;
5395 }
5396 
brcms_c_set_rate_limit(struct brcms_c_info * wlc,u16 srl,u16 lrl)5397 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5398 {
5399 	int ac;
5400 
5401 	if (srl < 1 || srl > RETRY_SHORT_MAX ||
5402 	    lrl < 1 || lrl > RETRY_SHORT_MAX)
5403 		return -EINVAL;
5404 
5405 	wlc->SRL = srl;
5406 	wlc->LRL = lrl;
5407 
5408 	brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5409 
5410 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5411 		wlc->wme_retries[ac] =	SFIELD(wlc->wme_retries[ac],
5412 					       EDCF_SHORT,  wlc->SRL);
5413 		wlc->wme_retries[ac] =	SFIELD(wlc->wme_retries[ac],
5414 					       EDCF_LONG, wlc->LRL);
5415 	}
5416 	brcms_c_wme_retries_write(wlc);
5417 
5418 	return 0;
5419 }
5420 
brcms_c_get_current_rateset(struct brcms_c_info * wlc,struct brcm_rateset * currs)5421 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5422 				 struct brcm_rateset *currs)
5423 {
5424 	struct brcms_c_rateset *rs;
5425 
5426 	if (wlc->pub->associated)
5427 		rs = &wlc->bsscfg->current_bss->rateset;
5428 	else
5429 		rs = &wlc->default_bss->rateset;
5430 
5431 	/* Copy only legacy rateset section */
5432 	currs->count = rs->count;
5433 	memcpy(&currs->rates, &rs->rates, rs->count);
5434 }
5435 
brcms_c_set_rateset(struct brcms_c_info * wlc,struct brcm_rateset * rs)5436 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5437 {
5438 	struct brcms_c_rateset internal_rs;
5439 	int bcmerror;
5440 
5441 	if (rs->count > BRCMS_NUMRATES)
5442 		return -ENOBUFS;
5443 
5444 	memset(&internal_rs, 0, sizeof(internal_rs));
5445 
5446 	/* Copy only legacy rateset section */
5447 	internal_rs.count = rs->count;
5448 	memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5449 
5450 	/* merge rateset coming in with the current mcsset */
5451 	if (wlc->pub->_n_enab & SUPPORT_11N) {
5452 		struct brcms_bss_info *mcsset_bss;
5453 		if (wlc->pub->associated)
5454 			mcsset_bss = wlc->bsscfg->current_bss;
5455 		else
5456 			mcsset_bss = wlc->default_bss;
5457 		memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5458 		       MCSSET_LEN);
5459 	}
5460 
5461 	bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5462 	if (!bcmerror)
5463 		brcms_c_ofdm_rateset_war(wlc);
5464 
5465 	return bcmerror;
5466 }
5467 
brcms_c_time_lock(struct brcms_c_info * wlc)5468 static void brcms_c_time_lock(struct brcms_c_info *wlc)
5469 {
5470 	bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD);
5471 	/* Commit the write */
5472 	bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5473 }
5474 
brcms_c_time_unlock(struct brcms_c_info * wlc)5475 static void brcms_c_time_unlock(struct brcms_c_info *wlc)
5476 {
5477 	bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD);
5478 	/* Commit the write */
5479 	bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5480 }
5481 
brcms_c_set_beacon_period(struct brcms_c_info * wlc,u16 period)5482 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5483 {
5484 	u32 bcnint_us;
5485 
5486 	if (period == 0)
5487 		return -EINVAL;
5488 
5489 	wlc->default_bss->beacon_period = period;
5490 
5491 	bcnint_us = period << 10;
5492 	brcms_c_time_lock(wlc);
5493 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfprep),
5494 		     (bcnint_us << CFPREP_CBI_SHIFT));
5495 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfpstart), bcnint_us);
5496 	brcms_c_time_unlock(wlc);
5497 
5498 	return 0;
5499 }
5500 
brcms_c_get_phy_type(struct brcms_c_info * wlc,int phyidx)5501 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5502 {
5503 	return wlc->band->phytype;
5504 }
5505 
brcms_c_set_shortslot_override(struct brcms_c_info * wlc,s8 sslot_override)5506 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5507 {
5508 	wlc->shortslot_override = sslot_override;
5509 
5510 	/*
5511 	 * shortslot is an 11g feature, so no more work if we are
5512 	 * currently on the 5G band
5513 	 */
5514 	if (wlc->band->bandtype == BRCM_BAND_5G)
5515 		return;
5516 
5517 	if (wlc->pub->up && wlc->pub->associated) {
5518 		/* let watchdog or beacon processing update shortslot */
5519 	} else if (wlc->pub->up) {
5520 		/* unassociated shortslot is off */
5521 		brcms_c_switch_shortslot(wlc, false);
5522 	} else {
5523 		/* driver is down, so just update the brcms_c_info
5524 		 * value */
5525 		if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5526 			wlc->shortslot = false;
5527 		else
5528 			wlc->shortslot =
5529 			    (wlc->shortslot_override ==
5530 			     BRCMS_SHORTSLOT_ON);
5531 	}
5532 }
5533 
5534 /*
5535  * register watchdog and down handlers.
5536  */
brcms_c_module_register(struct brcms_pub * pub,const char * name,struct brcms_info * hdl,int (* d_fn)(void * handle))5537 int brcms_c_module_register(struct brcms_pub *pub,
5538 			    const char *name, struct brcms_info *hdl,
5539 			    int (*d_fn)(void *handle))
5540 {
5541 	struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5542 	int i;
5543 
5544 	/* find an empty entry and just add, no duplication check! */
5545 	for (i = 0; i < BRCMS_MAXMODULES; i++) {
5546 		if (wlc->modulecb[i].name[0] == '\0') {
5547 			strscpy(wlc->modulecb[i].name, name,
5548 				sizeof(wlc->modulecb[i].name));
5549 			wlc->modulecb[i].hdl = hdl;
5550 			wlc->modulecb[i].down_fn = d_fn;
5551 			return 0;
5552 		}
5553 	}
5554 
5555 	return -ENOSR;
5556 }
5557 
5558 /* unregister module callbacks */
brcms_c_module_unregister(struct brcms_pub * pub,const char * name,struct brcms_info * hdl)5559 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5560 			      struct brcms_info *hdl)
5561 {
5562 	struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5563 	int i;
5564 
5565 	if (wlc == NULL)
5566 		return -ENODATA;
5567 
5568 	for (i = 0; i < BRCMS_MAXMODULES; i++) {
5569 		if (!strcmp(wlc->modulecb[i].name, name) &&
5570 		    (wlc->modulecb[i].hdl == hdl)) {
5571 			memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
5572 			return 0;
5573 		}
5574 	}
5575 
5576 	/* table not found! */
5577 	return -ENODATA;
5578 }
5579 
brcms_c_chipmatch_pci(struct bcma_device * core)5580 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5581 {
5582 	struct pci_dev *pcidev = core->bus->host_pci;
5583 	u16 vendor = pcidev->vendor;
5584 	u16 device = pcidev->device;
5585 
5586 	if (vendor != PCI_VENDOR_ID_BROADCOM) {
5587 		pr_err("unknown vendor id %04x\n", vendor);
5588 		return false;
5589 	}
5590 
5591 	if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5592 		return true;
5593 	if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5594 		return true;
5595 	if (device == BCM4313_D11N2G_ID || device == BCM4313_CHIP_ID)
5596 		return true;
5597 	if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5598 		return true;
5599 
5600 	pr_err("unknown device id %04x\n", device);
5601 	return false;
5602 }
5603 
brcms_c_chipmatch_soc(struct bcma_device * core)5604 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5605 {
5606 	struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5607 
5608 	if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5609 		return true;
5610 
5611 	pr_err("unknown chip id %04x\n", chipinfo->id);
5612 	return false;
5613 }
5614 
brcms_c_chipmatch(struct bcma_device * core)5615 bool brcms_c_chipmatch(struct bcma_device *core)
5616 {
5617 	switch (core->bus->hosttype) {
5618 	case BCMA_HOSTTYPE_PCI:
5619 		return brcms_c_chipmatch_pci(core);
5620 	case BCMA_HOSTTYPE_SOC:
5621 		return brcms_c_chipmatch_soc(core);
5622 	default:
5623 		pr_err("unknown host type: %i\n", core->bus->hosttype);
5624 		return false;
5625 	}
5626 }
5627 
brcms_b_rate_shm_offset(struct brcms_hardware * wlc_hw,u8 rate)5628 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5629 {
5630 	u16 table_ptr;
5631 	u8 phy_rate, index;
5632 
5633 	/* get the phy specific rate encoding for the PLCP SIGNAL field */
5634 	if (is_ofdm_rate(rate))
5635 		table_ptr = M_RT_DIRMAP_A;
5636 	else
5637 		table_ptr = M_RT_DIRMAP_B;
5638 
5639 	/* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5640 	 * the index into the rate table.
5641 	 */
5642 	phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5643 	index = phy_rate & 0xf;
5644 
5645 	/* Find the SHM pointer to the rate table entry by looking in the
5646 	 * Direct-map Table
5647 	 */
5648 	return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5649 }
5650 
5651 /*
5652  * bcmc_fid_generate:
5653  * Generate frame ID for a BCMC packet.  The frag field is not used
5654  * for MC frames so is used as part of the sequence number.
5655  */
5656 static inline u16
bcmc_fid_generate(struct brcms_c_info * wlc,struct brcms_bss_cfg * bsscfg,struct d11txh * txh)5657 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5658 		  struct d11txh *txh)
5659 {
5660 	u16 frameid;
5661 
5662 	frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5663 						  TXFID_QUEUE_MASK);
5664 	frameid |=
5665 	    (((wlc->
5666 	       mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5667 	    TX_BCMC_FIFO;
5668 
5669 	return frameid;
5670 }
5671 
5672 static uint
brcms_c_calc_ack_time(struct brcms_c_info * wlc,u32 rspec,u8 preamble_type)5673 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5674 		      u8 preamble_type)
5675 {
5676 	uint dur = 0;
5677 
5678 	/*
5679 	 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5680 	 * is less than or equal to the rate of the immediately previous
5681 	 * frame in the FES
5682 	 */
5683 	rspec = brcms_basic_rate(wlc, rspec);
5684 	/* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5685 	dur =
5686 	    brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5687 				(DOT11_ACK_LEN + FCS_LEN));
5688 	return dur;
5689 }
5690 
5691 static uint
brcms_c_calc_cts_time(struct brcms_c_info * wlc,u32 rspec,u8 preamble_type)5692 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5693 		      u8 preamble_type)
5694 {
5695 	return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5696 }
5697 
5698 static uint
brcms_c_calc_ba_time(struct brcms_c_info * wlc,u32 rspec,u8 preamble_type)5699 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5700 		     u8 preamble_type)
5701 {
5702 	/*
5703 	 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5704 	 * is less than or equal to the rate of the immediately previous
5705 	 * frame in the FES
5706 	 */
5707 	rspec = brcms_basic_rate(wlc, rspec);
5708 	/* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5709 	return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5710 				   (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5711 				    FCS_LEN));
5712 }
5713 
5714 /* brcms_c_compute_frame_dur()
5715  *
5716  * Calculate the 802.11 MAC header DUR field for MPDU
5717  * DUR for a single frame = 1 SIFS + 1 ACK
5718  * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5719  *
5720  * rate			MPDU rate in unit of 500kbps
5721  * next_frag_len	next MPDU length in bytes
5722  * preamble_type	use short/GF or long/MM PLCP header
5723  */
5724 static u16
brcms_c_compute_frame_dur(struct brcms_c_info * wlc,u32 rate,u8 preamble_type,uint next_frag_len)5725 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5726 		      u8 preamble_type, uint next_frag_len)
5727 {
5728 	u16 dur, sifs;
5729 
5730 	sifs = get_sifs(wlc->band);
5731 
5732 	dur = sifs;
5733 	dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5734 
5735 	if (next_frag_len) {
5736 		/* Double the current DUR to get 2 SIFS + 2 ACKs */
5737 		dur *= 2;
5738 		/* add another SIFS and the frag time */
5739 		dur += sifs;
5740 		dur +=
5741 		    (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5742 						 next_frag_len);
5743 	}
5744 	return dur;
5745 }
5746 
5747 /* The opposite of brcms_c_calc_frame_time */
5748 static uint
brcms_c_calc_frame_len(struct brcms_c_info * wlc,u32 ratespec,u8 preamble_type,uint dur)5749 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5750 		   u8 preamble_type, uint dur)
5751 {
5752 	uint nsyms, mac_len, Ndps, kNdps;
5753 	uint rate = rspec2rate(ratespec);
5754 
5755 	if (is_mcs_rate(ratespec)) {
5756 		uint mcs = ratespec & RSPEC_RATE_MASK;
5757 		int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5758 		dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5759 		/* payload calculation matches that of regular ofdm */
5760 		if (wlc->band->bandtype == BRCM_BAND_2G)
5761 			dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5762 		/* kNdbps = kbps * 4 */
5763 		kNdps =	mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5764 				   rspec_issgi(ratespec)) * 4;
5765 		nsyms = dur / APHY_SYMBOL_TIME;
5766 		mac_len =
5767 		    ((nsyms * kNdps) -
5768 		     ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5769 	} else if (is_ofdm_rate(ratespec)) {
5770 		dur -= APHY_PREAMBLE_TIME;
5771 		dur -= APHY_SIGNAL_TIME;
5772 		/* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5773 		Ndps = rate * 2;
5774 		nsyms = dur / APHY_SYMBOL_TIME;
5775 		mac_len =
5776 		    ((nsyms * Ndps) -
5777 		     (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5778 	} else {
5779 		if (preamble_type & BRCMS_SHORT_PREAMBLE)
5780 			dur -= BPHY_PLCP_SHORT_TIME;
5781 		else
5782 			dur -= BPHY_PLCP_TIME;
5783 		mac_len = dur * rate;
5784 		/* divide out factor of 2 in rate (1/2 mbps) */
5785 		mac_len = mac_len / 8 / 2;
5786 	}
5787 	return mac_len;
5788 }
5789 
5790 /*
5791  * Return true if the specified rate is supported by the specified band.
5792  * BRCM_BAND_AUTO indicates the current band.
5793  */
brcms_c_valid_rate(struct brcms_c_info * wlc,u32 rspec,int band,bool verbose)5794 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5795 		    bool verbose)
5796 {
5797 	struct brcms_c_rateset *hw_rateset;
5798 	uint i;
5799 
5800 	if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5801 		hw_rateset = &wlc->band->hw_rateset;
5802 	else if (wlc->pub->_nbands > 1)
5803 		hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5804 	else
5805 		/* other band specified and we are a single band device */
5806 		return false;
5807 
5808 	/* check if this is a mimo rate */
5809 	if (is_mcs_rate(rspec)) {
5810 		if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5811 			goto error;
5812 
5813 		return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5814 	}
5815 
5816 	for (i = 0; i < hw_rateset->count; i++)
5817 		if (hw_rateset->rates[i] == rspec2rate(rspec))
5818 			return true;
5819  error:
5820 	if (verbose)
5821 		brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5822 			  "not in hw_rateset\n", wlc->pub->unit, rspec);
5823 
5824 	return false;
5825 }
5826 
5827 static u32
mac80211_wlc_set_nrate(struct brcms_c_info * wlc,struct brcms_band * cur_band,u32 int_val)5828 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5829 		       u32 int_val)
5830 {
5831 	struct bcma_device *core = wlc->hw->d11core;
5832 	u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5833 	u8 rate = int_val & NRATE_RATE_MASK;
5834 	u32 rspec;
5835 	bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5836 	bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5837 	bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5838 				  == NRATE_OVERRIDE_MCS_ONLY);
5839 
5840 	if (!ismcs)
5841 		return (u32) rate;
5842 
5843 	/* validate the combination of rate/mcs/stf is allowed */
5844 	if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5845 		/* mcs only allowed when nmode */
5846 		if (stf > PHY_TXC1_MODE_SDM) {
5847 			brcms_err(core, "wl%d: %s: Invalid stf\n",
5848 				  wlc->pub->unit, __func__);
5849 			goto done;
5850 		}
5851 
5852 		/* mcs 32 is a special case, DUP mode 40 only */
5853 		if (rate == 32) {
5854 			if (!CHSPEC_IS40(wlc->home_chanspec) ||
5855 			    ((stf != PHY_TXC1_MODE_SISO)
5856 			     && (stf != PHY_TXC1_MODE_CDD))) {
5857 				brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5858 					  wlc->pub->unit, __func__);
5859 				goto done;
5860 			}
5861 			/* mcs > 7 must use stf SDM */
5862 		} else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5863 			/* mcs > 7 must use stf SDM */
5864 			if (stf != PHY_TXC1_MODE_SDM) {
5865 				brcms_dbg_mac80211(core, "wl%d: enabling "
5866 						   "SDM mode for mcs %d\n",
5867 						   wlc->pub->unit, rate);
5868 				stf = PHY_TXC1_MODE_SDM;
5869 			}
5870 		} else {
5871 			/*
5872 			 * MCS 0-7 may use SISO, CDD, and for
5873 			 * phy_rev >= 3 STBC
5874 			 */
5875 			if ((stf > PHY_TXC1_MODE_STBC) ||
5876 			    (!BRCMS_STBC_CAP_PHY(wlc)
5877 			     && (stf == PHY_TXC1_MODE_STBC))) {
5878 				brcms_err(core, "wl%d: %s: Invalid STBC\n",
5879 					  wlc->pub->unit, __func__);
5880 				goto done;
5881 			}
5882 		}
5883 	} else if (is_ofdm_rate(rate)) {
5884 		if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5885 			brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5886 				  wlc->pub->unit, __func__);
5887 			goto done;
5888 		}
5889 	} else if (is_cck_rate(rate)) {
5890 		if ((cur_band->bandtype != BRCM_BAND_2G)
5891 		    || (stf != PHY_TXC1_MODE_SISO)) {
5892 			brcms_err(core, "wl%d: %s: Invalid CCK\n",
5893 				  wlc->pub->unit, __func__);
5894 			goto done;
5895 		}
5896 	} else {
5897 		brcms_err(core, "wl%d: %s: Unknown rate type\n",
5898 			  wlc->pub->unit, __func__);
5899 		goto done;
5900 	}
5901 	/* make sure multiple antennae are available for non-siso rates */
5902 	if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5903 		brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5904 			  "request\n", wlc->pub->unit, __func__);
5905 		goto done;
5906 	}
5907 
5908 	rspec = rate;
5909 	if (ismcs) {
5910 		rspec |= RSPEC_MIMORATE;
5911 		/* For STBC populate the STC field of the ratespec */
5912 		if (stf == PHY_TXC1_MODE_STBC) {
5913 			u8 stc;
5914 			stc = 1;	/* Nss for single stream is always 1 */
5915 			rspec |= (stc << RSPEC_STC_SHIFT);
5916 		}
5917 	}
5918 
5919 	rspec |= (stf << RSPEC_STF_SHIFT);
5920 
5921 	if (override_mcs_only)
5922 		rspec |= RSPEC_OVERRIDE_MCS_ONLY;
5923 
5924 	if (issgi)
5925 		rspec |= RSPEC_SHORT_GI;
5926 
5927 	if ((rate != 0)
5928 	    && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
5929 		return rate;
5930 
5931 	return rspec;
5932 done:
5933 	return rate;
5934 }
5935 
5936 /*
5937  * Compute PLCP, but only requires actual rate and length of pkt.
5938  * Rate is given in the driver standard multiple of 500 kbps.
5939  * le is set for 11 Mbps rate if necessary.
5940  * Broken out for PRQ.
5941  */
5942 
brcms_c_cck_plcp_set(struct brcms_c_info * wlc,int rate_500,uint length,u8 * plcp)5943 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
5944 			     uint length, u8 *plcp)
5945 {
5946 	u16 usec = 0;
5947 	u8 le = 0;
5948 
5949 	switch (rate_500) {
5950 	case BRCM_RATE_1M:
5951 		usec = length << 3;
5952 		break;
5953 	case BRCM_RATE_2M:
5954 		usec = length << 2;
5955 		break;
5956 	case BRCM_RATE_5M5:
5957 		usec = (length << 4) / 11;
5958 		if ((length << 4) - (usec * 11) > 0)
5959 			usec++;
5960 		break;
5961 	case BRCM_RATE_11M:
5962 		usec = (length << 3) / 11;
5963 		if ((length << 3) - (usec * 11) > 0) {
5964 			usec++;
5965 			if ((usec * 11) - (length << 3) >= 8)
5966 				le = D11B_PLCP_SIGNAL_LE;
5967 		}
5968 		break;
5969 
5970 	default:
5971 		brcms_err(wlc->hw->d11core,
5972 			  "brcms_c_cck_plcp_set: unsupported rate %d\n",
5973 			  rate_500);
5974 		rate_500 = BRCM_RATE_1M;
5975 		usec = length << 3;
5976 		break;
5977 	}
5978 	/* PLCP signal byte */
5979 	plcp[0] = rate_500 * 5;	/* r (500kbps) * 5 == r (100kbps) */
5980 	/* PLCP service byte */
5981 	plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
5982 	/* PLCP length u16, little endian */
5983 	plcp[2] = usec & 0xff;
5984 	plcp[3] = (usec >> 8) & 0xff;
5985 	/* PLCP CRC16 */
5986 	plcp[4] = 0;
5987 	plcp[5] = 0;
5988 }
5989 
5990 /* Rate: 802.11 rate code, length: PSDU length in octets */
brcms_c_compute_mimo_plcp(u32 rspec,uint length,u8 * plcp)5991 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
5992 {
5993 	u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
5994 	plcp[0] = mcs;
5995 	if (rspec_is40mhz(rspec) || (mcs == 32))
5996 		plcp[0] |= MIMO_PLCP_40MHZ;
5997 	BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
5998 	plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
5999 	plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6000 	plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6001 	plcp[5] = 0;
6002 }
6003 
6004 /* Rate: 802.11 rate code, length: PSDU length in octets */
6005 static void
brcms_c_compute_ofdm_plcp(u32 rspec,u32 length,u8 * plcp)6006 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6007 {
6008 	u8 rate_signal;
6009 	u32 tmp = 0;
6010 	int rate = rspec2rate(rspec);
6011 
6012 	/*
6013 	 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6014 	 * transmitted first
6015 	 */
6016 	rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6017 	memset(plcp, 0, D11_PHY_HDR_LEN);
6018 	D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6019 
6020 	tmp = (length & 0xfff) << 5;
6021 	plcp[2] |= (tmp >> 16) & 0xff;
6022 	plcp[1] |= (tmp >> 8) & 0xff;
6023 	plcp[0] |= tmp & 0xff;
6024 }
6025 
6026 /* Rate: 802.11 rate code, length: PSDU length in octets */
brcms_c_compute_cck_plcp(struct brcms_c_info * wlc,u32 rspec,uint length,u8 * plcp)6027 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6028 				 uint length, u8 *plcp)
6029 {
6030 	int rate = rspec2rate(rspec);
6031 
6032 	brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6033 }
6034 
6035 static void
brcms_c_compute_plcp(struct brcms_c_info * wlc,u32 rspec,uint length,u8 * plcp)6036 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6037 		     uint length, u8 *plcp)
6038 {
6039 	if (is_mcs_rate(rspec))
6040 		brcms_c_compute_mimo_plcp(rspec, length, plcp);
6041 	else if (is_ofdm_rate(rspec))
6042 		brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6043 	else
6044 		brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6045 }
6046 
6047 /* brcms_c_compute_rtscts_dur()
6048  *
6049  * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6050  * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6051  * DUR for CTS-TO-SELF w/ frame    = 2 SIFS         + next frame time + 1 ACK
6052  *
6053  * cts			cts-to-self or rts/cts
6054  * rts_rate		rts or cts rate in unit of 500kbps
6055  * rate			next MPDU rate in unit of 500kbps
6056  * frame_len		next MPDU frame length in bytes
6057  */
6058 u16
brcms_c_compute_rtscts_dur(struct brcms_c_info * wlc,bool cts_only,u32 rts_rate,u32 frame_rate,u8 rts_preamble_type,u8 frame_preamble_type,uint frame_len,bool ba)6059 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6060 			   u32 rts_rate,
6061 			   u32 frame_rate, u8 rts_preamble_type,
6062 			   u8 frame_preamble_type, uint frame_len, bool ba)
6063 {
6064 	u16 dur, sifs;
6065 
6066 	sifs = get_sifs(wlc->band);
6067 
6068 	if (!cts_only) {
6069 		/* RTS/CTS */
6070 		dur = 3 * sifs;
6071 		dur +=
6072 		    (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6073 					       rts_preamble_type);
6074 	} else {
6075 		/* CTS-TO-SELF */
6076 		dur = 2 * sifs;
6077 	}
6078 
6079 	dur +=
6080 	    (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6081 					 frame_len);
6082 	if (ba)
6083 		dur +=
6084 		    (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6085 					      BRCMS_SHORT_PREAMBLE);
6086 	else
6087 		dur +=
6088 		    (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6089 					       frame_preamble_type);
6090 	return dur;
6091 }
6092 
brcms_c_phytxctl1_calc(struct brcms_c_info * wlc,u32 rspec)6093 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6094 {
6095 	u16 phyctl1 = 0;
6096 	u16 bw;
6097 
6098 	if (BRCMS_ISLCNPHY(wlc->band)) {
6099 		bw = PHY_TXC1_BW_20MHZ;
6100 	} else {
6101 		bw = rspec_get_bw(rspec);
6102 		/* 10Mhz is not supported yet */
6103 		if (bw < PHY_TXC1_BW_20MHZ) {
6104 			brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6105 				  "not supported yet, set to 20L\n", bw);
6106 			bw = PHY_TXC1_BW_20MHZ;
6107 		}
6108 	}
6109 
6110 	if (is_mcs_rate(rspec)) {
6111 		uint mcs = rspec & RSPEC_RATE_MASK;
6112 
6113 		/* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6114 		phyctl1 = rspec_phytxbyte2(rspec);
6115 		/* set the upper byte of phyctl1 */
6116 		phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6117 	} else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6118 		   && !BRCMS_ISSSLPNPHY(wlc->band)) {
6119 		/*
6120 		 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6121 		 * Data Rate. Eventually MIMOPHY would also be converted to
6122 		 * this format
6123 		 */
6124 		/* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6125 		phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6126 	} else {		/* legacy OFDM/CCK */
6127 		s16 phycfg;
6128 		/* get the phyctl byte from rate phycfg table */
6129 		phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6130 		if (phycfg == -1) {
6131 			brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6132 				  "legacy OFDM/CCK rate\n");
6133 			phycfg = 0;
6134 		}
6135 		/* set the upper byte of phyctl1 */
6136 		phyctl1 =
6137 		    (bw | (phycfg << 8) |
6138 		     (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6139 	}
6140 	return phyctl1;
6141 }
6142 
6143 /*
6144  * Add struct d11txh, struct cck_phy_hdr.
6145  *
6146  * 'p' data must start with 802.11 MAC header
6147  * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6148  *
6149  * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6150  *
6151  */
6152 static u16
brcms_c_d11hdrs_mac80211(struct brcms_c_info * wlc,struct ieee80211_hw * hw,struct sk_buff * p,struct scb * scb,uint frag,uint nfrags,uint queue,uint next_frag_len)6153 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6154 		     struct sk_buff *p, struct scb *scb, uint frag,
6155 		     uint nfrags, uint queue, uint next_frag_len)
6156 {
6157 	struct ieee80211_hdr *h;
6158 	struct d11txh *txh;
6159 	u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6160 	int len, phylen, rts_phylen;
6161 	u16 mch, phyctl, xfts, mainrates;
6162 	u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6163 	u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6164 	u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6165 	bool use_rts = false;
6166 	bool use_cts = false;
6167 	bool use_rifs = false;
6168 	u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6169 	u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6170 	u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6171 	struct ieee80211_rts *rts = NULL;
6172 	bool qos;
6173 	uint ac;
6174 	bool hwtkmic = false;
6175 	u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6176 #define ANTCFG_NONE 0xFF
6177 	u8 antcfg = ANTCFG_NONE;
6178 	u8 fbantcfg = ANTCFG_NONE;
6179 	uint phyctl1_stf = 0;
6180 	u16 durid = 0;
6181 	struct ieee80211_tx_rate *txrate[2];
6182 	int k;
6183 	struct ieee80211_tx_info *tx_info;
6184 	bool is_mcs;
6185 	u16 mimo_txbw;
6186 	u8 mimo_preamble_type;
6187 
6188 	/* locate 802.11 MAC header */
6189 	h = (struct ieee80211_hdr *)(p->data);
6190 	qos = ieee80211_is_data_qos(h->frame_control);
6191 
6192 	/* compute length of frame in bytes for use in PLCP computations */
6193 	len = p->len;
6194 	phylen = len + FCS_LEN;
6195 
6196 	/* Get tx_info */
6197 	tx_info = IEEE80211_SKB_CB(p);
6198 
6199 	/* add PLCP */
6200 	plcp = skb_push(p, D11_PHY_HDR_LEN);
6201 
6202 	/* add Broadcom tx descriptor header */
6203 	txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6204 	memset(txh, 0, D11_TXH_LEN);
6205 
6206 	/* setup frameid */
6207 	if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6208 		/* non-AP STA should never use BCMC queue */
6209 		if (queue == TX_BCMC_FIFO) {
6210 			brcms_err(wlc->hw->d11core,
6211 				  "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6212 				  wlc->pub->unit, __func__);
6213 			frameid = bcmc_fid_generate(wlc, NULL, txh);
6214 		} else {
6215 			/* Increment the counter for first fragment */
6216 			if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6217 				scb->seqnum[p->priority]++;
6218 
6219 			/* extract fragment number from frame first */
6220 			seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6221 			seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6222 			h->seq_ctrl = cpu_to_le16(seq);
6223 
6224 			frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6225 			    (queue & TXFID_QUEUE_MASK);
6226 		}
6227 	}
6228 	frameid |= queue & TXFID_QUEUE_MASK;
6229 
6230 	/* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6231 	if (ieee80211_is_beacon(h->frame_control))
6232 		mcl |= TXC_IGNOREPMQ;
6233 
6234 	txrate[0] = tx_info->control.rates;
6235 	txrate[1] = txrate[0] + 1;
6236 
6237 	/*
6238 	 * if rate control algorithm didn't give us a fallback
6239 	 * rate, use the primary rate
6240 	 */
6241 	if (txrate[1]->idx < 0)
6242 		txrate[1] = txrate[0];
6243 
6244 	for (k = 0; k < hw->max_rates; k++) {
6245 		is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6246 		if (!is_mcs) {
6247 			if ((txrate[k]->idx >= 0)
6248 			    && (txrate[k]->idx <
6249 				hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6250 				rspec[k] =
6251 				    hw->wiphy->bands[tx_info->band]->
6252 				    bitrates[txrate[k]->idx].hw_value;
6253 			} else {
6254 				rspec[k] = BRCM_RATE_1M;
6255 			}
6256 		} else {
6257 			rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6258 					NRATE_MCS_INUSE | txrate[k]->idx);
6259 		}
6260 
6261 		/*
6262 		 * Currently only support same setting for primay and
6263 		 * fallback rates. Unify flags for each rate into a
6264 		 * single value for the frame
6265 		 */
6266 		use_rts |=
6267 		    txrate[k]->
6268 		    flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6269 		use_cts |=
6270 		    txrate[k]->
6271 		    flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6272 
6273 
6274 		/*
6275 		 * (1) RATE:
6276 		 *   determine and validate primary rate
6277 		 *   and fallback rates
6278 		 */
6279 		if (!rspec_active(rspec[k])) {
6280 			rspec[k] = BRCM_RATE_1M;
6281 		} else {
6282 			if (!is_multicast_ether_addr(h->addr1)) {
6283 				/* set tx antenna config */
6284 				brcms_c_antsel_antcfg_get(wlc->asi, false,
6285 					false, 0, 0, &antcfg, &fbantcfg);
6286 			}
6287 		}
6288 	}
6289 
6290 	phyctl1_stf = wlc->stf->ss_opmode;
6291 
6292 	if (wlc->pub->_n_enab & SUPPORT_11N) {
6293 		for (k = 0; k < hw->max_rates; k++) {
6294 			/*
6295 			 * apply siso/cdd to single stream mcs's or ofdm
6296 			 * if rspec is auto selected
6297 			 */
6298 			if (((is_mcs_rate(rspec[k]) &&
6299 			      is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6300 			     is_ofdm_rate(rspec[k]))
6301 			    && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6302 				|| !(rspec[k] & RSPEC_OVERRIDE))) {
6303 				rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6304 
6305 				/* For SISO MCS use STBC if possible */
6306 				if (is_mcs_rate(rspec[k])
6307 				    && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6308 					u8 stc;
6309 
6310 					/* Nss for single stream is always 1 */
6311 					stc = 1;
6312 					rspec[k] |= (PHY_TXC1_MODE_STBC <<
6313 							RSPEC_STF_SHIFT) |
6314 						    (stc << RSPEC_STC_SHIFT);
6315 				} else
6316 					rspec[k] |=
6317 					    (phyctl1_stf << RSPEC_STF_SHIFT);
6318 			}
6319 
6320 			/*
6321 			 * Is the phy configured to use 40MHZ frames? If
6322 			 * so then pick the desired txbw
6323 			 */
6324 			if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6325 				/* default txbw is 20in40 SB */
6326 				mimo_ctlchbw = mimo_txbw =
6327 				   CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6328 								 wlc->band->pi))
6329 				   ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6330 
6331 				if (is_mcs_rate(rspec[k])) {
6332 					/* mcs 32 must be 40b/w DUP */
6333 					if ((rspec[k] & RSPEC_RATE_MASK)
6334 					    == 32) {
6335 						mimo_txbw =
6336 						    PHY_TXC1_BW_40MHZ_DUP;
6337 						/* use override */
6338 					} else if (wlc->mimo_40txbw != AUTO)
6339 						mimo_txbw = wlc->mimo_40txbw;
6340 					/* else check if dst is using 40 Mhz */
6341 					else if (scb->flags & SCB_IS40)
6342 						mimo_txbw = PHY_TXC1_BW_40MHZ;
6343 				} else if (is_ofdm_rate(rspec[k])) {
6344 					if (wlc->ofdm_40txbw != AUTO)
6345 						mimo_txbw = wlc->ofdm_40txbw;
6346 				} else if (wlc->cck_40txbw != AUTO) {
6347 					mimo_txbw = wlc->cck_40txbw;
6348 				}
6349 			} else {
6350 				/*
6351 				 * mcs32 is 40 b/w only.
6352 				 * This is possible for probe packets on
6353 				 * a STA during SCAN
6354 				 */
6355 				if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6356 					/* mcs 0 */
6357 					rspec[k] = RSPEC_MIMORATE;
6358 
6359 				mimo_txbw = PHY_TXC1_BW_20MHZ;
6360 			}
6361 
6362 			/* Set channel width */
6363 			rspec[k] &= ~RSPEC_BW_MASK;
6364 			if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6365 				rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6366 			else
6367 				rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6368 
6369 			/* Disable short GI, not supported yet */
6370 			rspec[k] &= ~RSPEC_SHORT_GI;
6371 
6372 			mimo_preamble_type = BRCMS_MM_PREAMBLE;
6373 			if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6374 				mimo_preamble_type = BRCMS_GF_PREAMBLE;
6375 
6376 			if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6377 			    && (!is_mcs_rate(rspec[k]))) {
6378 				brcms_warn(wlc->hw->d11core,
6379 					   "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n",
6380 					   wlc->pub->unit, __func__);
6381 			}
6382 
6383 			if (is_mcs_rate(rspec[k])) {
6384 				preamble_type[k] = mimo_preamble_type;
6385 
6386 				/*
6387 				 * if SGI is selected, then forced mm
6388 				 * for single stream
6389 				 */
6390 				if ((rspec[k] & RSPEC_SHORT_GI)
6391 				    && is_single_stream(rspec[k] &
6392 							RSPEC_RATE_MASK))
6393 					preamble_type[k] = BRCMS_MM_PREAMBLE;
6394 			}
6395 
6396 			/* should be better conditionalized */
6397 			if (!is_mcs_rate(rspec[0])
6398 			    && (tx_info->control.rates[0].
6399 				flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6400 				preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6401 		}
6402 	} else {
6403 		for (k = 0; k < hw->max_rates; k++) {
6404 			/* Set ctrlchbw as 20Mhz */
6405 			rspec[k] &= ~RSPEC_BW_MASK;
6406 			rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6407 
6408 			/* for nphy, stf of ofdm frames must follow policies */
6409 			if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6410 				rspec[k] &= ~RSPEC_STF_MASK;
6411 				rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6412 			}
6413 		}
6414 	}
6415 
6416 	/* Reset these for use with AMPDU's */
6417 	txrate[0]->count = 0;
6418 	txrate[1]->count = 0;
6419 
6420 	/* (2) PROTECTION, may change rspec */
6421 	if ((ieee80211_is_data(h->frame_control) ||
6422 	    ieee80211_is_mgmt(h->frame_control)) &&
6423 	    (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6424 		use_rts = true;
6425 
6426 	/* (3) PLCP: determine PLCP header and MAC duration,
6427 	 * fill struct d11txh */
6428 	brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6429 	brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6430 	memcpy(&txh->FragPLCPFallback,
6431 	       plcp_fallback, sizeof(txh->FragPLCPFallback));
6432 
6433 	/* Length field now put in CCK FBR CRC field */
6434 	if (is_cck_rate(rspec[1])) {
6435 		txh->FragPLCPFallback[4] = phylen & 0xff;
6436 		txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6437 	}
6438 
6439 	/* MIMO-RATE: need validation ?? */
6440 	mainrates = is_ofdm_rate(rspec[0]) ?
6441 			D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6442 			plcp[0];
6443 
6444 	/* DUR field for main rate */
6445 	if (!ieee80211_is_pspoll(h->frame_control) &&
6446 	    !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6447 		durid =
6448 		    brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6449 					  next_frag_len);
6450 		h->duration_id = cpu_to_le16(durid);
6451 	} else if (use_rifs) {
6452 		/* NAV protect to end of next max packet size */
6453 		durid =
6454 		    (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6455 						 preamble_type[0],
6456 						 DOT11_MAX_FRAG_LEN);
6457 		durid += RIFS_11N_TIME;
6458 		h->duration_id = cpu_to_le16(durid);
6459 	}
6460 
6461 	/* DUR field for fallback rate */
6462 	if (ieee80211_is_pspoll(h->frame_control))
6463 		txh->FragDurFallback = h->duration_id;
6464 	else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6465 		txh->FragDurFallback = 0;
6466 	else {
6467 		durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6468 					      preamble_type[1], next_frag_len);
6469 		txh->FragDurFallback = cpu_to_le16(durid);
6470 	}
6471 
6472 	/* (4) MAC-HDR: MacTxControlLow */
6473 	if (frag == 0)
6474 		mcl |= TXC_STARTMSDU;
6475 
6476 	if (!is_multicast_ether_addr(h->addr1))
6477 		mcl |= TXC_IMMEDACK;
6478 
6479 	if (wlc->band->bandtype == BRCM_BAND_5G)
6480 		mcl |= TXC_FREQBAND_5G;
6481 
6482 	if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6483 		mcl |= TXC_BW_40;
6484 
6485 	/* set AMIC bit if using hardware TKIP MIC */
6486 	if (hwtkmic)
6487 		mcl |= TXC_AMIC;
6488 
6489 	txh->MacTxControlLow = cpu_to_le16(mcl);
6490 
6491 	/* MacTxControlHigh */
6492 	mch = 0;
6493 
6494 	/* Set fallback rate preamble type */
6495 	if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6496 	    (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6497 		if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6498 			mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6499 	}
6500 
6501 	/* MacFrameControl */
6502 	memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6503 	txh->TxFesTimeNormal = cpu_to_le16(0);
6504 
6505 	txh->TxFesTimeFallback = cpu_to_le16(0);
6506 
6507 	/* TxFrameRA */
6508 	memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6509 
6510 	/* TxFrameID */
6511 	txh->TxFrameID = cpu_to_le16(frameid);
6512 
6513 	/*
6514 	 * TxStatus, Note the case of recreating the first frag of a suppressed
6515 	 * frame then we may need to reset the retry cnt's via the status reg
6516 	 */
6517 	txh->TxStatus = cpu_to_le16(status);
6518 
6519 	/*
6520 	 * extra fields for ucode AMPDU aggregation, the new fields are added to
6521 	 * the END of previous structure so that it's compatible in driver.
6522 	 */
6523 	txh->MaxNMpdus = cpu_to_le16(0);
6524 	txh->MaxABytes_MRT = cpu_to_le16(0);
6525 	txh->MaxABytes_FBR = cpu_to_le16(0);
6526 	txh->MinMBytes = cpu_to_le16(0);
6527 
6528 	/* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6529 	 * furnish struct d11txh */
6530 	/* RTS PLCP header and RTS frame */
6531 	if (use_rts || use_cts) {
6532 		if (use_rts && use_cts)
6533 			use_cts = false;
6534 
6535 		for (k = 0; k < 2; k++) {
6536 			rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6537 							      false,
6538 							      mimo_ctlchbw);
6539 		}
6540 
6541 		if (!is_ofdm_rate(rts_rspec[0]) &&
6542 		    !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6543 		      (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6544 			rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6545 			mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6546 		}
6547 
6548 		if (!is_ofdm_rate(rts_rspec[1]) &&
6549 		    !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6550 		      (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6551 			rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6552 			mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6553 		}
6554 
6555 		/* RTS/CTS additions to MacTxControlLow */
6556 		if (use_cts) {
6557 			txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6558 		} else {
6559 			txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6560 			txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6561 		}
6562 
6563 		/* RTS PLCP header */
6564 		rts_plcp = txh->RTSPhyHeader;
6565 		if (use_cts)
6566 			rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6567 		else
6568 			rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6569 
6570 		brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6571 
6572 		/* fallback rate version of RTS PLCP header */
6573 		brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6574 				 rts_plcp_fallback);
6575 		memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6576 		       sizeof(txh->RTSPLCPFallback));
6577 
6578 		/* RTS frame fields... */
6579 		rts = (struct ieee80211_rts *)&txh->rts_frame;
6580 
6581 		durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6582 					       rspec[0], rts_preamble_type[0],
6583 					       preamble_type[0], phylen, false);
6584 		rts->duration = cpu_to_le16(durid);
6585 		/* fallback rate version of RTS DUR field */
6586 		durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6587 					       rts_rspec[1], rspec[1],
6588 					       rts_preamble_type[1],
6589 					       preamble_type[1], phylen, false);
6590 		txh->RTSDurFallback = cpu_to_le16(durid);
6591 
6592 		if (use_cts) {
6593 			rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6594 							 IEEE80211_STYPE_CTS);
6595 
6596 			memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6597 		} else {
6598 			rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6599 							 IEEE80211_STYPE_RTS);
6600 
6601 			memcpy(&rts->ra, &h->addr1, ETH_ALEN);
6602 			memcpy(&rts->ta, &h->addr2, ETH_ALEN);
6603 		}
6604 
6605 		/* mainrate
6606 		 *    low 8 bits: main frag rate/mcs,
6607 		 *    high 8 bits: rts/cts rate/mcs
6608 		 */
6609 		mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6610 				D11A_PHY_HDR_GRATE(
6611 					(struct ofdm_phy_hdr *) rts_plcp) :
6612 				rts_plcp[0]) << 8;
6613 	} else {
6614 		memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6615 		memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts));
6616 		memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback));
6617 		txh->RTSDurFallback = 0;
6618 	}
6619 
6620 #ifdef SUPPORT_40MHZ
6621 	/* add null delimiter count */
6622 	if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6623 		txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6624 		   brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6625 
6626 #endif
6627 
6628 	/*
6629 	 * Now that RTS/RTS FB preamble types are updated, write
6630 	 * the final value
6631 	 */
6632 	txh->MacTxControlHigh = cpu_to_le16(mch);
6633 
6634 	/*
6635 	 * MainRates (both the rts and frag plcp rates have
6636 	 * been calculated now)
6637 	 */
6638 	txh->MainRates = cpu_to_le16(mainrates);
6639 
6640 	/* XtraFrameTypes */
6641 	xfts = frametype(rspec[1], wlc->mimoft);
6642 	xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6643 	xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6644 	xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6645 							     XFTS_CHANNEL_SHIFT;
6646 	txh->XtraFrameTypes = cpu_to_le16(xfts);
6647 
6648 	/* PhyTxControlWord */
6649 	phyctl = frametype(rspec[0], wlc->mimoft);
6650 	if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6651 	    (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6652 		if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6653 			phyctl |= PHY_TXC_SHORT_HDR;
6654 	}
6655 
6656 	/* phytxant is properly bit shifted */
6657 	phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6658 	txh->PhyTxControlWord = cpu_to_le16(phyctl);
6659 
6660 	/* PhyTxControlWord_1 */
6661 	if (BRCMS_PHY_11N_CAP(wlc->band)) {
6662 		u16 phyctl1 = 0;
6663 
6664 		phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6665 		txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6666 		phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6667 		txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6668 
6669 		if (use_rts || use_cts) {
6670 			phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6671 			txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6672 			phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6673 			txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6674 		}
6675 
6676 		/*
6677 		 * For mcs frames, if mixedmode(overloaded with long preamble)
6678 		 * is going to be set, fill in non-zero MModeLen and/or
6679 		 * MModeFbrLen it will be unnecessary if they are separated
6680 		 */
6681 		if (is_mcs_rate(rspec[0]) &&
6682 		    (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6683 			u16 mmodelen =
6684 			    brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6685 			txh->MModeLen = cpu_to_le16(mmodelen);
6686 		}
6687 
6688 		if (is_mcs_rate(rspec[1]) &&
6689 		    (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6690 			u16 mmodefbrlen =
6691 			    brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6692 			txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6693 		}
6694 	}
6695 
6696 	ac = skb_get_queue_mapping(p);
6697 	if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6698 		uint frag_dur, dur, dur_fallback;
6699 
6700 		/* WME: Update TXOP threshold */
6701 		if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6702 			frag_dur =
6703 			    brcms_c_calc_frame_time(wlc, rspec[0],
6704 					preamble_type[0], phylen);
6705 
6706 			if (rts) {
6707 				/* 1 RTS or CTS-to-self frame */
6708 				dur =
6709 				    brcms_c_calc_cts_time(wlc, rts_rspec[0],
6710 						      rts_preamble_type[0]);
6711 				dur_fallback =
6712 				    brcms_c_calc_cts_time(wlc, rts_rspec[1],
6713 						      rts_preamble_type[1]);
6714 				/* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6715 				dur += le16_to_cpu(rts->duration);
6716 				dur_fallback +=
6717 					le16_to_cpu(txh->RTSDurFallback);
6718 			} else if (use_rifs) {
6719 				dur = frag_dur;
6720 				dur_fallback = 0;
6721 			} else {
6722 				/* frame + SIFS + ACK */
6723 				dur = frag_dur;
6724 				dur +=
6725 				    brcms_c_compute_frame_dur(wlc, rspec[0],
6726 							  preamble_type[0], 0);
6727 
6728 				dur_fallback =
6729 				    brcms_c_calc_frame_time(wlc, rspec[1],
6730 							preamble_type[1],
6731 							phylen);
6732 				dur_fallback +=
6733 				    brcms_c_compute_frame_dur(wlc, rspec[1],
6734 							  preamble_type[1], 0);
6735 			}
6736 			/* NEED to set TxFesTimeNormal (hard) */
6737 			txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6738 			/*
6739 			 * NEED to set fallback rate version of
6740 			 * TxFesTimeNormal (hard)
6741 			 */
6742 			txh->TxFesTimeFallback =
6743 				cpu_to_le16((u16) dur_fallback);
6744 
6745 			/*
6746 			 * update txop byte threshold (txop minus intraframe
6747 			 * overhead)
6748 			 */
6749 			if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6750 				uint newfragthresh;
6751 
6752 				newfragthresh =
6753 				    brcms_c_calc_frame_len(wlc,
6754 					rspec[0], preamble_type[0],
6755 					(wlc->edcf_txop[ac] -
6756 						(dur - frag_dur)));
6757 				/* range bound the fragthreshold */
6758 				if (newfragthresh < DOT11_MIN_FRAG_LEN)
6759 					newfragthresh =
6760 					    DOT11_MIN_FRAG_LEN;
6761 				else if (newfragthresh >
6762 					 wlc->usr_fragthresh)
6763 					newfragthresh =
6764 					    wlc->usr_fragthresh;
6765 				/* update the fragthresh and do txc update */
6766 				if (wlc->fragthresh[queue] !=
6767 				    (u16) newfragthresh)
6768 					wlc->fragthresh[queue] =
6769 					    (u16) newfragthresh;
6770 			} else {
6771 				brcms_warn(wlc->hw->d11core,
6772 					   "wl%d: %s txop invalid for rate %d\n",
6773 					   wlc->pub->unit, fifo_names[queue],
6774 					   rspec2rate(rspec[0]));
6775 			}
6776 
6777 			if (dur > wlc->edcf_txop[ac])
6778 				brcms_warn(wlc->hw->d11core,
6779 					   "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
6780 					   wlc->pub->unit, __func__,
6781 					   fifo_names[queue],
6782 					   phylen, wlc->fragthresh[queue],
6783 					   dur, wlc->edcf_txop[ac]);
6784 		}
6785 	}
6786 
6787 	return 0;
6788 }
6789 
brcms_c_tx(struct brcms_c_info * wlc,struct sk_buff * skb)6790 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6791 {
6792 	struct dma_pub *dma;
6793 	int fifo, ret = -ENOSPC;
6794 	struct d11txh *txh;
6795 	u16 frameid = INVALIDFID;
6796 
6797 	fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6798 	dma = wlc->hw->di[fifo];
6799 	txh = (struct d11txh *)(skb->data);
6800 
6801 	if (dma->txavail == 0) {
6802 		/*
6803 		 * We sometimes get a frame from mac80211 after stopping
6804 		 * the queues. This only ever seems to be a single frame
6805 		 * and is seems likely to be a race. TX_HEADROOM should
6806 		 * ensure that we have enough space to handle these stray
6807 		 * packets, so warn if there isn't. If we're out of space
6808 		 * in the tx ring and the tx queue isn't stopped then
6809 		 * we've really got a bug; warn loudly if that happens.
6810 		 */
6811 		brcms_warn(wlc->hw->d11core,
6812 			   "Received frame for tx with no space in DMA ring\n");
6813 		WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6814 						 skb_get_queue_mapping(skb)));
6815 		return -ENOSPC;
6816 	}
6817 
6818 	/* When a BC/MC frame is being committed to the BCMC fifo
6819 	 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6820 	 */
6821 	if (fifo == TX_BCMC_FIFO)
6822 		frameid = le16_to_cpu(txh->TxFrameID);
6823 
6824 	/* Commit BCMC sequence number in the SHM frame ID location */
6825 	if (frameid != INVALIDFID) {
6826 		/*
6827 		 * To inform the ucode of the last mcast frame posted
6828 		 * so that it can clear moredata bit
6829 		 */
6830 		brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6831 	}
6832 
6833 	ret = brcms_c_txfifo(wlc, fifo, skb);
6834 	/*
6835 	 * The only reason for brcms_c_txfifo to fail is because
6836 	 * there weren't any DMA descriptors, but we've already
6837 	 * checked for that. So if it does fail yell loudly.
6838 	 */
6839 	WARN_ON_ONCE(ret);
6840 
6841 	return ret;
6842 }
6843 
brcms_c_sendpkt_mac80211(struct brcms_c_info * wlc,struct sk_buff * sdu,struct ieee80211_hw * hw)6844 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6845 			      struct ieee80211_hw *hw)
6846 {
6847 	uint fifo;
6848 	struct scb *scb = &wlc->pri_scb;
6849 
6850 	fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6851 	brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6852 	if (!brcms_c_tx(wlc, sdu))
6853 		return true;
6854 
6855 	/* packet discarded */
6856 	dev_kfree_skb_any(sdu);
6857 	return false;
6858 }
6859 
6860 int
brcms_c_txfifo(struct brcms_c_info * wlc,uint fifo,struct sk_buff * p)6861 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6862 {
6863 	struct dma_pub *dma = wlc->hw->di[fifo];
6864 	int ret;
6865 	u16 queue;
6866 
6867 	ret = dma_txfast(wlc, dma, p);
6868 	if (ret	< 0)
6869 		wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6870 
6871 	/*
6872 	 * Stop queue if DMA ring is full. Reserve some free descriptors,
6873 	 * as we sometimes receive a frame from mac80211 after the queues
6874 	 * are stopped.
6875 	 */
6876 	queue = skb_get_queue_mapping(p);
6877 	if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
6878 	    !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
6879 		ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
6880 
6881 	return ret;
6882 }
6883 
6884 u32
brcms_c_rspec_to_rts_rspec(struct brcms_c_info * wlc,u32 rspec,bool use_rspec,u16 mimo_ctlchbw)6885 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
6886 			   bool use_rspec, u16 mimo_ctlchbw)
6887 {
6888 	u32 rts_rspec = 0;
6889 
6890 	if (use_rspec)
6891 		/* use frame rate as rts rate */
6892 		rts_rspec = rspec;
6893 	else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
6894 		/* Use 11Mbps as the g protection RTS target rate and fallback.
6895 		 * Use the brcms_basic_rate() lookup to find the best basic rate
6896 		 * under the target in case 11 Mbps is not Basic.
6897 		 * 6 and 9 Mbps are not usually selected by rate selection, but
6898 		 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6899 		 * is more robust.
6900 		 */
6901 		rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
6902 	else
6903 		/* calculate RTS rate and fallback rate based on the frame rate
6904 		 * RTS must be sent at a basic rate since it is a
6905 		 * control frame, sec 9.6 of 802.11 spec
6906 		 */
6907 		rts_rspec = brcms_basic_rate(wlc, rspec);
6908 
6909 	if (BRCMS_PHY_11N_CAP(wlc->band)) {
6910 		/* set rts txbw to correct side band */
6911 		rts_rspec &= ~RSPEC_BW_MASK;
6912 
6913 		/*
6914 		 * if rspec/rspec_fallback is 40MHz, then send RTS on both
6915 		 * 20MHz channel (DUP), otherwise send RTS on control channel
6916 		 */
6917 		if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
6918 			rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
6919 		else
6920 			rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6921 
6922 		/* pick siso/cdd as default for ofdm */
6923 		if (is_ofdm_rate(rts_rspec)) {
6924 			rts_rspec &= ~RSPEC_STF_MASK;
6925 			rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
6926 		}
6927 	}
6928 	return rts_rspec;
6929 }
6930 
6931 /* Update beacon listen interval in shared memory */
brcms_c_bcn_li_upd(struct brcms_c_info * wlc)6932 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
6933 {
6934 	/* wake up every DTIM is the default */
6935 	if (wlc->bcn_li_dtim == 1)
6936 		brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
6937 	else
6938 		brcms_b_write_shm(wlc->hw, M_BCN_LI,
6939 			      (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
6940 }
6941 
6942 static void
brcms_b_read_tsf(struct brcms_hardware * wlc_hw,u32 * tsf_l_ptr,u32 * tsf_h_ptr)6943 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
6944 		  u32 *tsf_h_ptr)
6945 {
6946 	struct bcma_device *core = wlc_hw->d11core;
6947 
6948 	/* read the tsf timer low, then high to get an atomic read */
6949 	*tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
6950 	*tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
6951 }
6952 
6953 /*
6954  * recover 64bit TSF value from the 16bit TSF value in the rx header
6955  * given the assumption that the TSF passed in header is within 65ms
6956  * of the current tsf.
6957  *
6958  * 6       5       4       4       3       2       1
6959  * 3.......6.......8.......0.......2.......4.......6.......8......0
6960  * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
6961  *
6962  * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
6963  * tsf_l is filled in by brcms_b_recv, which is done earlier in the
6964  * receive call sequence after rx interrupt. Only the higher 16 bits
6965  * are used. Finally, the tsf_h is read from the tsf register.
6966  */
brcms_c_recover_tsf64(struct brcms_c_info * wlc,struct d11rxhdr * rxh)6967 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
6968 				 struct d11rxhdr *rxh)
6969 {
6970 	u32 tsf_h, tsf_l;
6971 	u16 rx_tsf_0_15, rx_tsf_16_31;
6972 
6973 	brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
6974 
6975 	rx_tsf_16_31 = (u16)(tsf_l >> 16);
6976 	rx_tsf_0_15 = rxh->RxTSFTime;
6977 
6978 	/*
6979 	 * a greater tsf time indicates the low 16 bits of
6980 	 * tsf_l wrapped, so decrement the high 16 bits.
6981 	 */
6982 	if ((u16)tsf_l < rx_tsf_0_15) {
6983 		rx_tsf_16_31 -= 1;
6984 		if (rx_tsf_16_31 == 0xffff)
6985 			tsf_h -= 1;
6986 	}
6987 
6988 	return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
6989 }
6990 
6991 static void
prep_mac80211_status(struct brcms_c_info * wlc,struct d11rxhdr * rxh,struct sk_buff * p,struct ieee80211_rx_status * rx_status)6992 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
6993 		     struct sk_buff *p,
6994 		     struct ieee80211_rx_status *rx_status)
6995 {
6996 	int channel;
6997 	u32 rspec;
6998 	unsigned char *plcp;
6999 
7000 	/* fill in TSF and flag its presence */
7001 	rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7002 	rx_status->flag |= RX_FLAG_MACTIME_START;
7003 
7004 	channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7005 
7006 	rx_status->band =
7007 		channel > 14 ? NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
7008 	rx_status->freq =
7009 		ieee80211_channel_to_frequency(channel, rx_status->band);
7010 
7011 	rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7012 
7013 	/* noise */
7014 	/* qual */
7015 	rx_status->antenna =
7016 		(rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7017 
7018 	plcp = p->data;
7019 
7020 	rspec = brcms_c_compute_rspec(rxh, plcp);
7021 	if (is_mcs_rate(rspec)) {
7022 		rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7023 		rx_status->encoding = RX_ENC_HT;
7024 		if (rspec_is40mhz(rspec))
7025 			rx_status->bw = RATE_INFO_BW_40;
7026 	} else {
7027 		switch (rspec2rate(rspec)) {
7028 		case BRCM_RATE_1M:
7029 			rx_status->rate_idx = 0;
7030 			break;
7031 		case BRCM_RATE_2M:
7032 			rx_status->rate_idx = 1;
7033 			break;
7034 		case BRCM_RATE_5M5:
7035 			rx_status->rate_idx = 2;
7036 			break;
7037 		case BRCM_RATE_11M:
7038 			rx_status->rate_idx = 3;
7039 			break;
7040 		case BRCM_RATE_6M:
7041 			rx_status->rate_idx = 4;
7042 			break;
7043 		case BRCM_RATE_9M:
7044 			rx_status->rate_idx = 5;
7045 			break;
7046 		case BRCM_RATE_12M:
7047 			rx_status->rate_idx = 6;
7048 			break;
7049 		case BRCM_RATE_18M:
7050 			rx_status->rate_idx = 7;
7051 			break;
7052 		case BRCM_RATE_24M:
7053 			rx_status->rate_idx = 8;
7054 			break;
7055 		case BRCM_RATE_36M:
7056 			rx_status->rate_idx = 9;
7057 			break;
7058 		case BRCM_RATE_48M:
7059 			rx_status->rate_idx = 10;
7060 			break;
7061 		case BRCM_RATE_54M:
7062 			rx_status->rate_idx = 11;
7063 			break;
7064 		default:
7065 			brcms_err(wlc->hw->d11core,
7066 				  "%s: Unknown rate\n", __func__);
7067 		}
7068 
7069 		/*
7070 		 * For 5GHz, we should decrease the index as it is
7071 		 * a subset of the 2.4G rates. See bitrates field
7072 		 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7073 		 */
7074 		if (rx_status->band == NL80211_BAND_5GHZ)
7075 			rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7076 
7077 		/* Determine short preamble and rate_idx */
7078 		if (is_cck_rate(rspec)) {
7079 			if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7080 				rx_status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
7081 		} else if (is_ofdm_rate(rspec)) {
7082 			rx_status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
7083 		} else {
7084 			brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7085 				  __func__);
7086 		}
7087 	}
7088 
7089 	if (plcp3_issgi(plcp[3]))
7090 		rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
7091 
7092 	if (rxh->RxStatus1 & RXS_DECERR) {
7093 		rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7094 		brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_PLCP_CRC\n",
7095 			  __func__);
7096 	}
7097 	if (rxh->RxStatus1 & RXS_FCSERR) {
7098 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7099 		brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_FCS_CRC\n",
7100 			  __func__);
7101 	}
7102 }
7103 
7104 static void
brcms_c_recvctl(struct brcms_c_info * wlc,struct d11rxhdr * rxh,struct sk_buff * p)7105 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7106 		struct sk_buff *p)
7107 {
7108 	int len_mpdu;
7109 	struct ieee80211_rx_status rx_status;
7110 	struct ieee80211_hdr *hdr;
7111 
7112 	memset(&rx_status, 0, sizeof(rx_status));
7113 	prep_mac80211_status(wlc, rxh, p, &rx_status);
7114 
7115 	/* mac header+body length, exclude CRC and plcp header */
7116 	len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7117 	skb_pull(p, D11_PHY_HDR_LEN);
7118 	__skb_trim(p, len_mpdu);
7119 
7120 	/* unmute transmit */
7121 	if (wlc->hw->suspended_fifos) {
7122 		hdr = (struct ieee80211_hdr *)p->data;
7123 		if (ieee80211_is_beacon(hdr->frame_control))
7124 			brcms_b_mute(wlc->hw, false);
7125 	}
7126 
7127 	memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7128 	ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7129 }
7130 
7131 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7132  * number of bytes goes in the length field
7133  *
7134  * Formula given by HT PHY Spec v 1.13
7135  *   len = 3(nsyms + nstream + 3) - 3
7136  */
7137 u16
brcms_c_calc_lsig_len(struct brcms_c_info * wlc,u32 ratespec,uint mac_len)7138 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7139 		      uint mac_len)
7140 {
7141 	uint nsyms, len = 0, kNdps;
7142 
7143 	if (is_mcs_rate(ratespec)) {
7144 		uint mcs = ratespec & RSPEC_RATE_MASK;
7145 		int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7146 				  rspec_stc(ratespec);
7147 
7148 		/*
7149 		 * the payload duration calculation matches that
7150 		 * of regular ofdm
7151 		 */
7152 		/* 1000Ndbps = kbps * 4 */
7153 		kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7154 				   rspec_issgi(ratespec)) * 4;
7155 
7156 		if (rspec_stc(ratespec) == 0)
7157 			nsyms =
7158 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7159 				  APHY_TAIL_NBITS) * 1000, kNdps);
7160 		else
7161 			/* STBC needs to have even number of symbols */
7162 			nsyms =
7163 			    2 *
7164 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7165 				  APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7166 
7167 		/* (+3) account for HT-SIG(2) and HT-STF(1) */
7168 		nsyms += (tot_streams + 3);
7169 		/*
7170 		 * 3 bytes/symbol @ legacy 6Mbps rate
7171 		 * (-3) excluding service bits and tail bits
7172 		 */
7173 		len = (3 * nsyms) - 3;
7174 	}
7175 
7176 	return (u16) len;
7177 }
7178 
7179 static void
brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info * wlc,uint frame_len)7180 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7181 {
7182 	const struct brcms_c_rateset *rs_dflt;
7183 	struct brcms_c_rateset rs;
7184 	u8 rate;
7185 	u16 entry_ptr;
7186 	u8 plcp[D11_PHY_HDR_LEN];
7187 	u16 dur, sifs;
7188 	uint i;
7189 
7190 	sifs = get_sifs(wlc->band);
7191 
7192 	rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7193 
7194 	brcms_c_rateset_copy(rs_dflt, &rs);
7195 	brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7196 
7197 	/*
7198 	 * walk the phy rate table and update MAC core SHM
7199 	 * basic rate table entries
7200 	 */
7201 	for (i = 0; i < rs.count; i++) {
7202 		rate = rs.rates[i] & BRCMS_RATE_MASK;
7203 
7204 		entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7205 
7206 		/* Calculate the Probe Response PLCP for the given rate */
7207 		brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7208 
7209 		/*
7210 		 * Calculate the duration of the Probe Response
7211 		 * frame plus SIFS for the MAC
7212 		 */
7213 		dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7214 						BRCMS_LONG_PREAMBLE, frame_len);
7215 		dur += sifs;
7216 
7217 		/* Update the SHM Rate Table entry Probe Response values */
7218 		brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7219 			      (u16) (plcp[0] + (plcp[1] << 8)));
7220 		brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7221 			      (u16) (plcp[2] + (plcp[3] << 8)));
7222 		brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7223 	}
7224 }
7225 
brcms_c_get_header_len(void)7226 int brcms_c_get_header_len(void)
7227 {
7228 	return TXOFF;
7229 }
7230 
brcms_c_beacon_write(struct brcms_c_info * wlc,struct sk_buff * beacon,u16 tim_offset,u16 dtim_period,bool bcn0,bool bcn1)7231 static void brcms_c_beacon_write(struct brcms_c_info *wlc,
7232 				 struct sk_buff *beacon, u16 tim_offset,
7233 				 u16 dtim_period, bool bcn0, bool bcn1)
7234 {
7235 	size_t len;
7236 	struct ieee80211_tx_info *tx_info;
7237 	struct brcms_hardware *wlc_hw = wlc->hw;
7238 	struct ieee80211_hw *ieee_hw = brcms_c_pub(wlc)->ieee_hw;
7239 
7240 	/* Get tx_info */
7241 	tx_info = IEEE80211_SKB_CB(beacon);
7242 
7243 	len = min_t(size_t, beacon->len, BCN_TMPL_LEN);
7244 	wlc->bcn_rspec = ieee80211_get_tx_rate(ieee_hw, tx_info)->hw_value;
7245 
7246 	brcms_c_compute_plcp(wlc, wlc->bcn_rspec,
7247 			     len + FCS_LEN - D11_PHY_HDR_LEN, beacon->data);
7248 
7249 	/* "Regular" and 16 MBSS but not for 4 MBSS */
7250 	/* Update the phytxctl for the beacon based on the rspec */
7251 	brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec);
7252 
7253 	if (bcn0) {
7254 		/* write the probe response into the template region */
7255 		brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE,
7256 					    (len + 3) & ~3, beacon->data);
7257 
7258 		/* write beacon length to SCR */
7259 		brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
7260 	}
7261 	if (bcn1) {
7262 		/* write the probe response into the template region */
7263 		brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE,
7264 					    (len + 3) & ~3, beacon->data);
7265 
7266 		/* write beacon length to SCR */
7267 		brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
7268 	}
7269 
7270 	if (tim_offset != 0) {
7271 		brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7272 				  tim_offset + D11B_PHY_HDR_LEN);
7273 		brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, dtim_period);
7274 	} else {
7275 		brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7276 				  len + D11B_PHY_HDR_LEN);
7277 		brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, 0);
7278 	}
7279 }
7280 
brcms_c_update_beacon_hw(struct brcms_c_info * wlc,struct sk_buff * beacon,u16 tim_offset,u16 dtim_period)7281 static void brcms_c_update_beacon_hw(struct brcms_c_info *wlc,
7282 				     struct sk_buff *beacon, u16 tim_offset,
7283 				     u16 dtim_period)
7284 {
7285 	struct brcms_hardware *wlc_hw = wlc->hw;
7286 	struct bcma_device *core = wlc_hw->d11core;
7287 
7288 	/* Hardware beaconing for this config */
7289 	u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
7290 
7291 	/* Check if both templates are in use, if so sched. an interrupt
7292 	 *      that will call back into this routine
7293 	 */
7294 	if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid)
7295 		/* clear any previous status */
7296 		bcma_write32(core, D11REGOFFS(macintstatus), MI_BCNTPL);
7297 
7298 	if (wlc->beacon_template_virgin) {
7299 		wlc->beacon_template_virgin = false;
7300 		brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7301 				     true);
7302 		/* mark beacon0 valid */
7303 		bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7304 		return;
7305 	}
7306 
7307 	/* Check that after scheduling the interrupt both of the
7308 	 *      templates are still busy. if not clear the int. & remask
7309 	 */
7310 	if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid) {
7311 		wlc->defmacintmask |= MI_BCNTPL;
7312 		return;
7313 	}
7314 
7315 	if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN0VLD)) {
7316 		brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7317 				     false);
7318 		/* mark beacon0 valid */
7319 		bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7320 		return;
7321 	}
7322 	if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN1VLD)) {
7323 		brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period,
7324 				     false, true);
7325 		/* mark beacon0 valid */
7326 		bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN1VLD);
7327 	}
7328 }
7329 
7330 /*
7331  * Update all beacons for the system.
7332  */
brcms_c_update_beacon(struct brcms_c_info * wlc)7333 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7334 {
7335 	struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7336 
7337 	if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7338 			     bsscfg->type == BRCMS_TYPE_ADHOC)) {
7339 		/* Clear the soft intmask */
7340 		wlc->defmacintmask &= ~MI_BCNTPL;
7341 		if (!wlc->beacon)
7342 			return;
7343 		brcms_c_update_beacon_hw(wlc, wlc->beacon,
7344 					 wlc->beacon_tim_offset,
7345 					 wlc->beacon_dtim_period);
7346 	}
7347 }
7348 
brcms_c_set_new_beacon(struct brcms_c_info * wlc,struct sk_buff * beacon,u16 tim_offset,u16 dtim_period)7349 void brcms_c_set_new_beacon(struct brcms_c_info *wlc, struct sk_buff *beacon,
7350 			    u16 tim_offset, u16 dtim_period)
7351 {
7352 	if (!beacon)
7353 		return;
7354 	if (wlc->beacon)
7355 		dev_kfree_skb_any(wlc->beacon);
7356 	wlc->beacon = beacon;
7357 
7358 	/* add PLCP */
7359 	skb_push(wlc->beacon, D11_PHY_HDR_LEN);
7360 	wlc->beacon_tim_offset = tim_offset;
7361 	wlc->beacon_dtim_period = dtim_period;
7362 	brcms_c_update_beacon(wlc);
7363 }
7364 
brcms_c_set_new_probe_resp(struct brcms_c_info * wlc,struct sk_buff * probe_resp)7365 void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc,
7366 				struct sk_buff *probe_resp)
7367 {
7368 	if (!probe_resp)
7369 		return;
7370 	if (wlc->probe_resp)
7371 		dev_kfree_skb_any(wlc->probe_resp);
7372 	wlc->probe_resp = probe_resp;
7373 
7374 	/* add PLCP */
7375 	skb_push(wlc->probe_resp, D11_PHY_HDR_LEN);
7376 	brcms_c_update_probe_resp(wlc, false);
7377 }
7378 
brcms_c_enable_probe_resp(struct brcms_c_info * wlc,bool enable)7379 void brcms_c_enable_probe_resp(struct brcms_c_info *wlc, bool enable)
7380 {
7381 	/*
7382 	 * prevent ucode from sending probe responses by setting the timeout
7383 	 * to 1, it can not send it in that time frame.
7384 	 */
7385 	wlc->prb_resp_timeout = enable ? BRCMS_PRB_RESP_TIMEOUT : 1;
7386 	brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7387 	/* TODO: if (enable) => also deactivate receiving of probe request */
7388 }
7389 
7390 /* Write ssid into shared memory */
7391 static void
brcms_c_shm_ssid_upd(struct brcms_c_info * wlc,struct brcms_bss_cfg * cfg)7392 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7393 {
7394 	u8 *ssidptr = cfg->SSID;
7395 	u16 base = M_SSID;
7396 	u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7397 
7398 	/* padding the ssid with zero and copy it into shm */
7399 	memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7400 	memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7401 
7402 	brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7403 	brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7404 }
7405 
7406 static void
brcms_c_bss_update_probe_resp(struct brcms_c_info * wlc,struct brcms_bss_cfg * cfg,struct sk_buff * probe_resp,bool suspend)7407 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7408 			      struct brcms_bss_cfg *cfg,
7409 			      struct sk_buff *probe_resp,
7410 			      bool suspend)
7411 {
7412 	int len;
7413 
7414 	len = min_t(size_t, probe_resp->len, BCN_TMPL_LEN);
7415 
7416 	if (suspend)
7417 		brcms_c_suspend_mac_and_wait(wlc);
7418 
7419 	/* write the probe response into the template region */
7420 	brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7421 				    (len + 3) & ~3, probe_resp->data);
7422 
7423 	/* write the length of the probe response frame (+PLCP/-FCS) */
7424 	brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7425 
7426 	/* write the SSID and SSID length */
7427 	brcms_c_shm_ssid_upd(wlc, cfg);
7428 
7429 	/*
7430 	 * Write PLCP headers and durations for probe response frames
7431 	 * at all rates. Use the actual frame length covered by the
7432 	 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7433 	 * by subtracting the PLCP len and adding the FCS.
7434 	 */
7435 	brcms_c_mod_prb_rsp_rate_table(wlc,
7436 				      (u16)len + FCS_LEN - D11_PHY_HDR_LEN);
7437 
7438 	if (suspend)
7439 		brcms_c_enable_mac(wlc);
7440 }
7441 
brcms_c_update_probe_resp(struct brcms_c_info * wlc,bool suspend)7442 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7443 {
7444 	struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7445 
7446 	/* update AP or IBSS probe responses */
7447 	if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7448 			     bsscfg->type == BRCMS_TYPE_ADHOC)) {
7449 		if (!wlc->probe_resp)
7450 			return;
7451 		brcms_c_bss_update_probe_resp(wlc, bsscfg, wlc->probe_resp,
7452 					      suspend);
7453 	}
7454 }
7455 
brcms_b_xmtfifo_sz_get(struct brcms_hardware * wlc_hw,uint fifo,uint * blocks)7456 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7457 			   uint *blocks)
7458 {
7459 	if (fifo >= NFIFO)
7460 		return -EINVAL;
7461 
7462 	*blocks = wlc_hw->xmtfifo_sz[fifo];
7463 
7464 	return 0;
7465 }
7466 
7467 void
brcms_c_set_addrmatch(struct brcms_c_info * wlc,int match_reg_offset,const u8 * addr)7468 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7469 		  const u8 *addr)
7470 {
7471 	brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7472 	if (match_reg_offset == RCM_BSSID_OFFSET)
7473 		memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7474 }
7475 
7476 /*
7477  * Flag 'scan in progress' to withhold dynamic phy calibration
7478  */
brcms_c_scan_start(struct brcms_c_info * wlc)7479 void brcms_c_scan_start(struct brcms_c_info *wlc)
7480 {
7481 	wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7482 }
7483 
brcms_c_scan_stop(struct brcms_c_info * wlc)7484 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7485 {
7486 	wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7487 }
7488 
brcms_c_associate_upd(struct brcms_c_info * wlc,bool state)7489 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7490 {
7491 	wlc->pub->associated = state;
7492 }
7493 
7494 /*
7495  * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7496  * AMPDU traffic, packets pending in hardware have to be invalidated so that
7497  * when later on hardware releases them, they can be handled appropriately.
7498  */
brcms_c_inval_dma_pkts(struct brcms_hardware * hw,struct ieee80211_sta * sta,void (* dma_callback_fn))7499 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7500 			       struct ieee80211_sta *sta,
7501 			       void (*dma_callback_fn))
7502 {
7503 	struct dma_pub *dmah;
7504 	int i;
7505 	for (i = 0; i < NFIFO; i++) {
7506 		dmah = hw->di[i];
7507 		if (dmah != NULL)
7508 			dma_walk_packets(dmah, dma_callback_fn, sta);
7509 	}
7510 }
7511 
brcms_c_get_curband(struct brcms_c_info * wlc)7512 int brcms_c_get_curband(struct brcms_c_info *wlc)
7513 {
7514 	return wlc->band->bandunit;
7515 }
7516 
brcms_c_tx_flush_completed(struct brcms_c_info * wlc)7517 bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc)
7518 {
7519 	int i;
7520 
7521 	/* Kick DMA to send any pending AMPDU */
7522 	for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7523 		if (wlc->hw->di[i])
7524 			dma_kick_tx(wlc->hw->di[i]);
7525 
7526 	return !brcms_txpktpendtot(wlc);
7527 }
7528 
brcms_c_set_beacon_listen_interval(struct brcms_c_info * wlc,u8 interval)7529 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7530 {
7531 	wlc->bcn_li_bcn = interval;
7532 	if (wlc->pub->up)
7533 		brcms_c_bcn_li_upd(wlc);
7534 }
7535 
brcms_c_tsf_get(struct brcms_c_info * wlc)7536 u64 brcms_c_tsf_get(struct brcms_c_info *wlc)
7537 {
7538 	u32 tsf_h, tsf_l;
7539 	u64 tsf;
7540 
7541 	brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7542 
7543 	tsf = tsf_h;
7544 	tsf <<= 32;
7545 	tsf |= tsf_l;
7546 
7547 	return tsf;
7548 }
7549 
brcms_c_tsf_set(struct brcms_c_info * wlc,u64 tsf)7550 void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf)
7551 {
7552 	u32 tsf_h, tsf_l;
7553 
7554 	brcms_c_time_lock(wlc);
7555 
7556 	tsf_l = tsf;
7557 	tsf_h = (tsf >> 32);
7558 
7559 	/* read the tsf timer low, then high to get an atomic read */
7560 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerlow), tsf_l);
7561 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerhigh), tsf_h);
7562 
7563 	brcms_c_time_unlock(wlc);
7564 }
7565 
brcms_c_set_tx_power(struct brcms_c_info * wlc,int txpwr)7566 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7567 {
7568 	uint qdbm;
7569 
7570 	/* Remove override bit and clip to max qdbm value */
7571 	qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7572 	return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7573 }
7574 
brcms_c_get_tx_power(struct brcms_c_info * wlc)7575 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7576 {
7577 	uint qdbm;
7578 	bool override;
7579 
7580 	wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7581 
7582 	/* Return qdbm units */
7583 	return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7584 }
7585 
7586 /* Process received frames */
7587 /*
7588  * Return true if more frames need to be processed. false otherwise.
7589  * Param 'bound' indicates max. # frames to process before break out.
7590  */
brcms_c_recv(struct brcms_c_info * wlc,struct sk_buff * p)7591 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7592 {
7593 	struct d11rxhdr *rxh;
7594 	struct ieee80211_hdr *h;
7595 	uint len;
7596 	bool is_amsdu;
7597 
7598 	/* frame starts with rxhdr */
7599 	rxh = (struct d11rxhdr *) (p->data);
7600 
7601 	/* strip off rxhdr */
7602 	skb_pull(p, BRCMS_HWRXOFF);
7603 
7604 	/* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7605 	if (rxh->RxStatus1 & RXS_PBPRES) {
7606 		if (p->len < 2) {
7607 			brcms_err(wlc->hw->d11core,
7608 				  "wl%d: recv: rcvd runt of len %d\n",
7609 				  wlc->pub->unit, p->len);
7610 			goto toss;
7611 		}
7612 		skb_pull(p, 2);
7613 	}
7614 
7615 	h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7616 	len = p->len;
7617 
7618 	if (rxh->RxStatus1 & RXS_FCSERR) {
7619 		if (!(wlc->filter_flags & FIF_FCSFAIL))
7620 			goto toss;
7621 	}
7622 
7623 	/* check received pkt has at least frame control field */
7624 	if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7625 		goto toss;
7626 
7627 	/* not supporting A-MSDU */
7628 	is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7629 	if (is_amsdu)
7630 		goto toss;
7631 
7632 	brcms_c_recvctl(wlc, rxh, p);
7633 	return;
7634 
7635  toss:
7636 	brcmu_pkt_buf_free_skb(p);
7637 }
7638 
7639 /* Process received frames */
7640 /*
7641  * Return true if more frames need to be processed. false otherwise.
7642  * Param 'bound' indicates max. # frames to process before break out.
7643  */
7644 static bool
brcms_b_recv(struct brcms_hardware * wlc_hw,uint fifo,bool bound)7645 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7646 {
7647 	struct sk_buff *p;
7648 	struct sk_buff *next = NULL;
7649 	struct sk_buff_head recv_frames;
7650 
7651 	uint n = 0;
7652 	uint bound_limit = bound ? RXBND : -1;
7653 	bool morepending = false;
7654 
7655 	skb_queue_head_init(&recv_frames);
7656 
7657 	/* gather received frames */
7658 	do {
7659 		/* !give others some time to run! */
7660 		if (n >= bound_limit)
7661 			break;
7662 
7663 		morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7664 		n++;
7665 	} while (morepending);
7666 
7667 	/* post more rbufs */
7668 	dma_rxfill(wlc_hw->di[fifo]);
7669 
7670 	/* process each frame */
7671 	skb_queue_walk_safe(&recv_frames, p, next) {
7672 		struct d11rxhdr_le *rxh_le;
7673 		struct d11rxhdr *rxh;
7674 
7675 		skb_unlink(p, &recv_frames);
7676 		rxh_le = (struct d11rxhdr_le *)p->data;
7677 		rxh = (struct d11rxhdr *)p->data;
7678 
7679 		/* fixup rx header endianness */
7680 		rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7681 		rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7682 		rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7683 		rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7684 		rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7685 		rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7686 		rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7687 		rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7688 		rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7689 		rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7690 		rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7691 
7692 		brcms_c_recv(wlc_hw->wlc, p);
7693 	}
7694 
7695 	return morepending;
7696 }
7697 
7698 /* second-level interrupt processing
7699  *   Return true if another dpc needs to be re-scheduled. false otherwise.
7700  *   Param 'bounded' indicates if applicable loops should be bounded.
7701  */
brcms_c_dpc(struct brcms_c_info * wlc,bool bounded)7702 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7703 {
7704 	u32 macintstatus;
7705 	struct brcms_hardware *wlc_hw = wlc->hw;
7706 	struct bcma_device *core = wlc_hw->d11core;
7707 
7708 	if (brcms_deviceremoved(wlc)) {
7709 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7710 			  __func__);
7711 		brcms_down(wlc->wl);
7712 		return false;
7713 	}
7714 
7715 	/* grab and clear the saved software intstatus bits */
7716 	macintstatus = wlc->macintstatus;
7717 	wlc->macintstatus = 0;
7718 
7719 	brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7720 		      wlc_hw->unit, macintstatus);
7721 
7722 	WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7723 
7724 	/* tx status */
7725 	if (macintstatus & MI_TFS) {
7726 		bool fatal;
7727 		if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7728 			wlc->macintstatus |= MI_TFS;
7729 		if (fatal) {
7730 			brcms_err(core, "MI_TFS: fatal\n");
7731 			goto fatal;
7732 		}
7733 	}
7734 
7735 	if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7736 		brcms_c_tbtt(wlc);
7737 
7738 	/* ATIM window end */
7739 	if (macintstatus & MI_ATIMWINEND) {
7740 		brcms_dbg_info(core, "end of ATIM window\n");
7741 		bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7742 		wlc->qvalid = 0;
7743 	}
7744 
7745 	/*
7746 	 * received data or control frame, MI_DMAINT is
7747 	 * indication of RX_FIFO interrupt
7748 	 */
7749 	if (macintstatus & MI_DMAINT)
7750 		if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7751 			wlc->macintstatus |= MI_DMAINT;
7752 
7753 	/* noise sample collected */
7754 	if (macintstatus & MI_BG_NOISE)
7755 		wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7756 
7757 	if (macintstatus & MI_GP0) {
7758 		brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7759 			  "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7760 
7761 		printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7762 			    __func__, ai_get_chip_id(wlc_hw->sih),
7763 			    ai_get_chiprev(wlc_hw->sih));
7764 		brcms_fatal_error(wlc_hw->wlc->wl);
7765 	}
7766 
7767 	/* gptimer timeout */
7768 	if (macintstatus & MI_TO)
7769 		bcma_write32(core, D11REGOFFS(gptimer), 0);
7770 
7771 	if (macintstatus & MI_RFDISABLE) {
7772 		brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7773 			       " RF Disable Input\n", wlc_hw->unit);
7774 		brcms_rfkill_set_hw_state(wlc->wl);
7775 	}
7776 
7777 	/* BCN template is available */
7778 	if (macintstatus & MI_BCNTPL)
7779 		brcms_c_update_beacon(wlc);
7780 
7781 	/* it isn't done and needs to be resched if macintstatus is non-zero */
7782 	return wlc->macintstatus != 0;
7783 
7784  fatal:
7785 	brcms_fatal_error(wlc_hw->wlc->wl);
7786 	return wlc->macintstatus != 0;
7787 }
7788 
brcms_c_init(struct brcms_c_info * wlc,bool mute_tx)7789 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7790 {
7791 	struct bcma_device *core = wlc->hw->d11core;
7792 	struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.chandef.chan;
7793 	u16 chanspec;
7794 
7795 	brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7796 
7797 	chanspec = ch20mhz_chspec(ch->hw_value);
7798 
7799 	brcms_b_init(wlc->hw, chanspec);
7800 
7801 	/* update beacon listen interval */
7802 	brcms_c_bcn_li_upd(wlc);
7803 
7804 	/* write ethernet address to core */
7805 	brcms_c_set_mac(wlc->bsscfg);
7806 	brcms_c_set_bssid(wlc->bsscfg);
7807 
7808 	/* Update tsf_cfprep if associated and up */
7809 	if (wlc->pub->associated && wlc->pub->up) {
7810 		u32 bi;
7811 
7812 		/* get beacon period and convert to uS */
7813 		bi = wlc->bsscfg->current_bss->beacon_period << 10;
7814 		/*
7815 		 * update since init path would reset
7816 		 * to default value
7817 		 */
7818 		bcma_write32(core, D11REGOFFS(tsf_cfprep),
7819 			     bi << CFPREP_CBI_SHIFT);
7820 
7821 		/* Update maccontrol PM related bits */
7822 		brcms_c_set_ps_ctrl(wlc);
7823 	}
7824 
7825 	brcms_c_bandinit_ordered(wlc, chanspec);
7826 
7827 	/* init probe response timeout */
7828 	brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7829 
7830 	/* init max burst txop (framebursting) */
7831 	brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7832 		      (wlc->
7833 		       _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7834 
7835 	/* initialize maximum allowed duty cycle */
7836 	brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7837 	brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7838 
7839 	/*
7840 	 * Update some shared memory locations related to
7841 	 * max AMPDU size allowed to received
7842 	 */
7843 	brcms_c_ampdu_shm_upd(wlc->ampdu);
7844 
7845 	/* band-specific inits */
7846 	brcms_c_bsinit(wlc);
7847 
7848 	/* Enable EDCF mode (while the MAC is suspended) */
7849 	bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7850 	brcms_c_edcf_setparams(wlc, false);
7851 
7852 	/* read the ucode version if we have not yet done so */
7853 	if (wlc->ucode_rev == 0) {
7854 		u16 rev;
7855 		u16 patch;
7856 
7857 		rev = brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR);
7858 		patch = brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
7859 		wlc->ucode_rev = (rev << NBITS(u16)) | patch;
7860 		snprintf(wlc->wiphy->fw_version,
7861 			 sizeof(wlc->wiphy->fw_version), "%u.%u", rev, patch);
7862 	}
7863 
7864 	/* ..now really unleash hell (allow the MAC out of suspend) */
7865 	brcms_c_enable_mac(wlc);
7866 
7867 	/* suspend the tx fifos and mute the phy for preism cac time */
7868 	if (mute_tx)
7869 		brcms_b_mute(wlc->hw, true);
7870 
7871 	/* enable the RF Disable Delay timer */
7872 	bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
7873 
7874 	/*
7875 	 * Initialize WME parameters; if they haven't been set by some other
7876 	 * mechanism (IOVar, etc) then read them from the hardware.
7877 	 */
7878 	if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
7879 		/* Uninitialized; read from HW */
7880 		int ac;
7881 
7882 		for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
7883 			wlc->wme_retries[ac] =
7884 			    brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
7885 	}
7886 }
7887 
7888 /*
7889  * The common driver entry routine. Error codes should be unique
7890  */
7891 struct brcms_c_info *
brcms_c_attach(struct brcms_info * wl,struct bcma_device * core,uint unit,bool piomode,uint * perr)7892 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
7893 	       bool piomode, uint *perr)
7894 {
7895 	struct brcms_c_info *wlc;
7896 	uint err = 0;
7897 	uint i, j;
7898 	struct brcms_pub *pub;
7899 
7900 	/* allocate struct brcms_c_info state and its substructures */
7901 	wlc = brcms_c_attach_malloc(unit, &err, 0);
7902 	if (wlc == NULL)
7903 		goto fail;
7904 	wlc->wiphy = wl->wiphy;
7905 	pub = wlc->pub;
7906 
7907 #if defined(DEBUG)
7908 	wlc_info_dbg = wlc;
7909 #endif
7910 
7911 	wlc->band = wlc->bandstate[0];
7912 	wlc->core = wlc->corestate;
7913 	wlc->wl = wl;
7914 	pub->unit = unit;
7915 	pub->_piomode = piomode;
7916 	wlc->bandinit_pending = false;
7917 	wlc->beacon_template_virgin = true;
7918 
7919 	/* populate struct brcms_c_info with default values  */
7920 	brcms_c_info_init(wlc, unit);
7921 
7922 	/* update sta/ap related parameters */
7923 	brcms_c_ap_upd(wlc);
7924 
7925 	/*
7926 	 * low level attach steps(all hw accesses go
7927 	 * inside, no more in rest of the attach)
7928 	 */
7929 	err = brcms_b_attach(wlc, core, unit, piomode);
7930 	if (err)
7931 		goto fail;
7932 
7933 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
7934 
7935 	pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
7936 
7937 	/* disable allowed duty cycle */
7938 	wlc->tx_duty_cycle_ofdm = 0;
7939 	wlc->tx_duty_cycle_cck = 0;
7940 
7941 	brcms_c_stf_phy_chain_calc(wlc);
7942 
7943 	/* txchain 1: txant 0, txchain 2: txant 1 */
7944 	if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
7945 		wlc->stf->txant = wlc->stf->hw_txchain - 1;
7946 
7947 	/* push to BMAC driver */
7948 	wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
7949 			       wlc->stf->hw_rxchain);
7950 
7951 	/* pull up some info resulting from the low attach */
7952 	for (i = 0; i < NFIFO; i++)
7953 		wlc->core->txavail[i] = wlc->hw->txavail[i];
7954 
7955 	memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7956 	memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7957 
7958 	for (j = 0; j < wlc->pub->_nbands; j++) {
7959 		wlc->band = wlc->bandstate[j];
7960 
7961 		if (!brcms_c_attach_stf_ant_init(wlc)) {
7962 			err = 24;
7963 			goto fail;
7964 		}
7965 
7966 		/* default contention windows size limits */
7967 		wlc->band->CWmin = APHY_CWMIN;
7968 		wlc->band->CWmax = PHY_CWMAX;
7969 
7970 		/* init gmode value */
7971 		if (wlc->band->bandtype == BRCM_BAND_2G) {
7972 			wlc->band->gmode = GMODE_AUTO;
7973 			brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
7974 					   wlc->band->gmode);
7975 		}
7976 
7977 		/* init _n_enab supported mode */
7978 		if (BRCMS_PHY_11N_CAP(wlc->band)) {
7979 			pub->_n_enab = SUPPORT_11N;
7980 			brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
7981 						   ((pub->_n_enab ==
7982 						     SUPPORT_11N) ? WL_11N_2x2 :
7983 						    WL_11N_3x3));
7984 		}
7985 
7986 		/* init per-band default rateset, depend on band->gmode */
7987 		brcms_default_rateset(wlc, &wlc->band->defrateset);
7988 
7989 		/* fill in hw_rateset */
7990 		brcms_c_rateset_filter(&wlc->band->defrateset,
7991 				   &wlc->band->hw_rateset, false,
7992 				   BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
7993 				   (bool) (wlc->pub->_n_enab & SUPPORT_11N));
7994 	}
7995 
7996 	/*
7997 	 * update antenna config due to
7998 	 * wlc->stf->txant/txchain/ant_rx_ovr change
7999 	 */
8000 	brcms_c_stf_phy_txant_upd(wlc);
8001 
8002 	/* attach each modules */
8003 	err = brcms_c_attach_module(wlc);
8004 	if (err != 0)
8005 		goto fail;
8006 
8007 	if (!brcms_c_timers_init(wlc, unit)) {
8008 		wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8009 			  __func__);
8010 		err = 32;
8011 		goto fail;
8012 	}
8013 
8014 	/* depend on rateset, gmode */
8015 	wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8016 	if (!wlc->cmi) {
8017 		wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8018 			  "\n", unit, __func__);
8019 		err = 33;
8020 		goto fail;
8021 	}
8022 
8023 	/* init default when all parameters are ready, i.e. ->rateset */
8024 	brcms_c_bss_default_init(wlc);
8025 
8026 	/*
8027 	 * Complete the wlc default state initializations..
8028 	 */
8029 
8030 	wlc->bsscfg->wlc = wlc;
8031 
8032 	wlc->mimoft = FT_HT;
8033 	wlc->mimo_40txbw = AUTO;
8034 	wlc->ofdm_40txbw = AUTO;
8035 	wlc->cck_40txbw = AUTO;
8036 	brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8037 
8038 	/* Set default values of SGI */
8039 	if (BRCMS_SGI_CAP_PHY(wlc)) {
8040 		brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8041 					       BRCMS_N_SGI_40));
8042 	} else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8043 		brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8044 					       BRCMS_N_SGI_40));
8045 	} else {
8046 		brcms_c_ht_update_sgi_rx(wlc, 0);
8047 	}
8048 
8049 	brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8050 
8051 	if (perr)
8052 		*perr = 0;
8053 
8054 	return wlc;
8055 
8056  fail:
8057 	wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8058 		  unit, __func__, err);
8059 	if (wlc)
8060 		brcms_c_detach(wlc);
8061 
8062 	if (perr)
8063 		*perr = err;
8064 	return NULL;
8065 }
8066