1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define NUM_PIXEL_FORMATS 10 80 81 enum tiling_mode { 82 TILING_MODE_INVALID, 83 TILING_MODE_LINEAR, 84 TILING_MODE_TILED, 85 TILING_MODE_COUNT 86 }; 87 88 enum view_3d_format { 89 VIEW_3D_FORMAT_NONE = 0, 90 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 91 VIEW_3D_FORMAT_SIDE_BY_SIDE, 92 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 93 VIEW_3D_FORMAT_COUNT, 94 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 95 }; 96 97 enum plane_stereo_format { 98 PLANE_STEREO_FORMAT_NONE = 0, 99 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 100 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 101 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 102 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 103 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 104 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 105 }; 106 107 /* TODO: Find way to calculate number of bits 108 * Please increase if pixel_format enum increases 109 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 110 */ 111 112 enum dc_edid_connector_type { 113 DC_EDID_CONNECTOR_UNKNOWN = 0, 114 DC_EDID_CONNECTOR_ANALOG = 1, 115 DC_EDID_CONNECTOR_DIGITAL = 10, 116 DC_EDID_CONNECTOR_DVI = 11, 117 DC_EDID_CONNECTOR_HDMIA = 12, 118 DC_EDID_CONNECTOR_MDDI = 14, 119 DC_EDID_CONNECTOR_DISPLAYPORT = 15 120 }; 121 122 enum dc_edid_status { 123 EDID_OK, 124 EDID_BAD_INPUT, 125 EDID_NO_RESPONSE, 126 EDID_BAD_CHECKSUM, 127 EDID_THE_SAME, 128 EDID_FALL_BACK, 129 EDID_PARTIAL_VALID, 130 }; 131 132 enum act_return_status { 133 ACT_SUCCESS, 134 ACT_LINK_LOST, 135 ACT_FAILED 136 }; 137 138 /* audio capability from EDID*/ 139 struct dc_cea_audio_mode { 140 uint8_t format_code; /* ucData[0] [6:3]*/ 141 uint8_t channel_count; /* ucData[0] [2:0]*/ 142 uint8_t sample_rate; /* ucData[1]*/ 143 union { 144 uint8_t sample_size; /* for LPCM*/ 145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 146 uint8_t max_bit_rate; 147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 148 }; 149 }; 150 151 struct dc_edid { 152 uint32_t length; 153 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 154 }; 155 156 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 157 * is used. In this case we assume speaker location are: front left, front 158 * right and front center. */ 159 #define DEFAULT_SPEAKER_LOCATION 5 160 161 #define DC_MAX_AUDIO_DESC_COUNT 16 162 163 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 164 165 struct dc_panel_patch { 166 unsigned int dppowerup_delay; 167 unsigned int extra_t12_ms; 168 unsigned int extra_delay_backlight_off; 169 unsigned int extra_t7_ms; 170 unsigned int skip_scdc_overwrite; 171 unsigned int delay_ignore_msa; 172 unsigned int disable_fec; 173 unsigned int extra_t3_ms; 174 unsigned int max_dsc_target_bpp_limit; 175 unsigned int embedded_tiled_slave; 176 unsigned int disable_fams; 177 unsigned int skip_avmute; 178 unsigned int mst_start_top_delay; 179 unsigned int remove_sink_ext_caps; 180 unsigned int disable_colorimetry; 181 uint8_t blankstream_before_otg_off; 182 bool oled_optimize_display_on; 183 unsigned int force_mst_blocked_discovery; 184 unsigned int wait_after_dpcd_poweroff_ms; 185 }; 186 187 struct dc_edid_caps { 188 /* sink identification */ 189 uint16_t manufacturer_id; 190 uint16_t product_id; 191 uint32_t serial_number; 192 uint8_t manufacture_week; 193 uint8_t manufacture_year; 194 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 195 196 /* audio caps */ 197 uint8_t speaker_flags; 198 uint32_t audio_mode_count; 199 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 200 uint32_t audio_latency; 201 uint32_t video_latency; 202 203 uint8_t qs_bit; 204 uint8_t qy_bit; 205 206 uint32_t max_tmds_clk_mhz; 207 208 /*HDMI 2.0 caps*/ 209 bool lte_340mcsc_scramble; 210 211 bool edid_hdmi; 212 bool hdr_supported; 213 214 struct dc_panel_patch panel_patch; 215 }; 216 217 struct dc_mode_flags { 218 /* note: part of refresh rate flag*/ 219 uint32_t INTERLACE :1; 220 /* native display timing*/ 221 uint32_t NATIVE :1; 222 /* preferred is the recommended mode, one per display */ 223 uint32_t PREFERRED :1; 224 /* true if this mode should use reduced blanking timings 225 *_not_ related to the Reduced Blanking adjustment*/ 226 uint32_t REDUCED_BLANKING :1; 227 /* note: part of refreshrate flag*/ 228 uint32_t VIDEO_OPTIMIZED_RATE :1; 229 /* should be reported to upper layers as mode_flags*/ 230 uint32_t PACKED_PIXEL_FORMAT :1; 231 /*< preferred view*/ 232 uint32_t PREFERRED_VIEW :1; 233 /* this timing should be used only in tiled mode*/ 234 uint32_t TILED_MODE :1; 235 uint32_t DSE_MODE :1; 236 /* Refresh rate divider when Miracast sink is using a 237 different rate than the output display device 238 Must be zero for wired displays and non-zero for 239 Miracast displays*/ 240 uint32_t MIRACAST_REFRESH_DIVIDER; 241 }; 242 243 244 enum dc_timing_source { 245 TIMING_SOURCE_UNDEFINED, 246 247 /* explicitly specifed by user, most important*/ 248 TIMING_SOURCE_USER_FORCED, 249 TIMING_SOURCE_USER_OVERRIDE, 250 TIMING_SOURCE_CUSTOM, 251 TIMING_SOURCE_EXPLICIT, 252 253 /* explicitly specified by the display device, more important*/ 254 TIMING_SOURCE_EDID_CEA_SVD_3D, 255 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 256 TIMING_SOURCE_EDID_CEA_SVD_420, 257 TIMING_SOURCE_EDID_DETAILED, 258 TIMING_SOURCE_EDID_ESTABLISHED, 259 TIMING_SOURCE_EDID_STANDARD, 260 TIMING_SOURCE_EDID_CEA_SVD, 261 TIMING_SOURCE_EDID_CVT_3BYTE, 262 TIMING_SOURCE_EDID_4BYTE, 263 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 264 TIMING_SOURCE_EDID_CEA_RID, 265 TIMING_SOURCE_VBIOS, 266 TIMING_SOURCE_CV, 267 TIMING_SOURCE_TV, 268 TIMING_SOURCE_HDMI_VIC, 269 270 /* implicitly specified by display device, still safe but less important*/ 271 TIMING_SOURCE_DEFAULT, 272 273 /* only used for custom base modes */ 274 TIMING_SOURCE_CUSTOM_BASE, 275 276 /* these timing might not work, least important*/ 277 TIMING_SOURCE_RANGELIMIT, 278 TIMING_SOURCE_OS_FORCED, 279 TIMING_SOURCE_IMPLICIT, 280 281 /* only used by default mode list*/ 282 TIMING_SOURCE_BASICMODE, 283 284 TIMING_SOURCE_COUNT 285 }; 286 287 288 struct stereo_3d_features { 289 bool supported ; 290 bool allTimings ; 291 bool cloneMode ; 292 bool scaling ; 293 bool singleFrameSWPacked; 294 }; 295 296 enum dc_timing_support_method { 297 TIMING_SUPPORT_METHOD_UNDEFINED, 298 TIMING_SUPPORT_METHOD_EXPLICIT, 299 TIMING_SUPPORT_METHOD_IMPLICIT, 300 TIMING_SUPPORT_METHOD_NATIVE 301 }; 302 303 struct dc_mode_info { 304 uint32_t pixel_width; 305 uint32_t pixel_height; 306 uint32_t field_rate; 307 /* Vertical refresh rate for progressive modes. 308 * Field rate for interlaced modes.*/ 309 310 enum dc_timing_standard timing_standard; 311 enum dc_timing_source timing_source; 312 struct dc_mode_flags flags; 313 }; 314 315 enum dc_power_state { 316 DC_POWER_STATE_ON = 1, 317 DC_POWER_STATE_STANDBY, 318 DC_POWER_STATE_SUSPEND, 319 DC_POWER_STATE_OFF 320 }; 321 322 /* DC PowerStates */ 323 enum dc_video_power_state { 324 DC_VIDEO_POWER_UNSPECIFIED = 0, 325 DC_VIDEO_POWER_ON = 1, 326 DC_VIDEO_POWER_STANDBY, 327 DC_VIDEO_POWER_SUSPEND, 328 DC_VIDEO_POWER_OFF, 329 DC_VIDEO_POWER_HIBERNATE, 330 DC_VIDEO_POWER_SHUTDOWN, 331 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 332 DC_VIDEO_POWER_AFTER_RESET, 333 DC_VIDEO_POWER_MAXIMUM 334 }; 335 336 enum dc_acpi_cm_power_state { 337 DC_ACPI_CM_POWER_STATE_D0 = 1, 338 DC_ACPI_CM_POWER_STATE_D1 = 2, 339 DC_ACPI_CM_POWER_STATE_D2 = 4, 340 DC_ACPI_CM_POWER_STATE_D3 = 8 341 }; 342 343 enum dc_connection_type { 344 dc_connection_none, 345 dc_connection_single, 346 dc_connection_mst_branch, 347 dc_connection_sst_branch 348 }; 349 350 struct dc_csc_adjustments { 351 struct fixed31_32 contrast; 352 struct fixed31_32 saturation; 353 struct fixed31_32 brightness; 354 struct fixed31_32 hue; 355 }; 356 357 /* Scaling format */ 358 enum scaling_transformation { 359 SCALING_TRANSFORMATION_UNINITIALIZED, 360 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 361 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 362 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 363 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 364 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 365 SCALING_TRANSFORMATION_INVALID = 0x80000000, 366 367 /* Flag the first and last */ 368 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 369 SCALING_TRANSFORMATION_END = 370 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 371 }; 372 373 enum display_content_type { 374 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 375 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 376 DISPLAY_CONTENT_TYPE_PHOTO = 2, 377 DISPLAY_CONTENT_TYPE_CINEMA = 4, 378 DISPLAY_CONTENT_TYPE_GAME = 8 379 }; 380 381 enum cm_gamut_adjust_type { 382 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 383 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 384 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 385 }; 386 387 struct cm_grph_csc_adjustment { 388 struct fixed31_32 temperature_matrix[12]; 389 enum cm_gamut_adjust_type gamut_adjust_type; 390 enum cm_gamut_coef_format gamut_coef_format; 391 }; 392 393 /* writeback */ 394 struct dwb_stereo_params { 395 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 396 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 397 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 398 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 399 }; 400 401 struct dc_dwb_cnv_params { 402 unsigned int src_width; /* input active width */ 403 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 404 unsigned int crop_width; /* cropped window width at cnv output */ 405 bool crop_en; /* window cropping enable in cnv */ 406 unsigned int crop_height; /* cropped window height at cnv output */ 407 unsigned int crop_x; /* cropped window start x value at cnv output */ 408 unsigned int crop_y; /* cropped window start y value at cnv output */ 409 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 410 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 411 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 412 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 413 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 414 }; 415 416 struct dc_dwb_params { 417 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 418 unsigned int hdr_mult; /* must be in FP1.6.12 */ 419 struct cm_grph_csc_adjustment csc_params; 420 struct dwb_stereo_params stereo_params; 421 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 422 unsigned int dest_width; /* Destination width */ 423 unsigned int dest_height; /* Destination height */ 424 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 425 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 426 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 427 struct scaling_taps scaler_taps; /* Scaling taps */ 428 enum dwb_subsample_position subsample_position; 429 const struct dc_transfer_func *out_transfer_func; 430 }; 431 432 /* audio*/ 433 434 union audio_sample_rates { 435 struct sample_rates { 436 uint8_t RATE_32:1; 437 uint8_t RATE_44_1:1; 438 uint8_t RATE_48:1; 439 uint8_t RATE_88_2:1; 440 uint8_t RATE_96:1; 441 uint8_t RATE_176_4:1; 442 uint8_t RATE_192:1; 443 } rate; 444 445 uint8_t all; 446 }; 447 448 struct audio_speaker_flags { 449 uint32_t FL_FR:1; 450 uint32_t LFE:1; 451 uint32_t FC:1; 452 uint32_t RL_RR:1; 453 uint32_t RC:1; 454 uint32_t FLC_FRC:1; 455 uint32_t RLC_RRC:1; 456 uint32_t SUPPORT_AI:1; 457 }; 458 459 struct audio_speaker_info { 460 uint32_t ALLSPEAKERS:7; 461 uint32_t SUPPORT_AI:1; 462 }; 463 464 465 struct audio_info_flags { 466 467 union { 468 469 struct audio_speaker_flags speaker_flags; 470 struct audio_speaker_info info; 471 472 uint8_t all; 473 }; 474 }; 475 476 enum audio_format_code { 477 AUDIO_FORMAT_CODE_FIRST = 1, 478 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 479 480 AUDIO_FORMAT_CODE_AC3, 481 /*Layers 1 & 2 */ 482 AUDIO_FORMAT_CODE_MPEG1, 483 /*MPEG1 Layer 3 */ 484 AUDIO_FORMAT_CODE_MP3, 485 /*multichannel */ 486 AUDIO_FORMAT_CODE_MPEG2, 487 AUDIO_FORMAT_CODE_AAC, 488 AUDIO_FORMAT_CODE_DTS, 489 AUDIO_FORMAT_CODE_ATRAC, 490 AUDIO_FORMAT_CODE_1BITAUDIO, 491 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 492 AUDIO_FORMAT_CODE_DTS_HD, 493 AUDIO_FORMAT_CODE_MAT_MLP, 494 AUDIO_FORMAT_CODE_DST, 495 AUDIO_FORMAT_CODE_WMAPRO, 496 AUDIO_FORMAT_CODE_LAST, 497 AUDIO_FORMAT_CODE_COUNT = 498 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 499 }; 500 501 struct audio_mode { 502 /* ucData[0] [6:3] */ 503 enum audio_format_code format_code; 504 /* ucData[0] [2:0] */ 505 uint8_t channel_count; 506 /* ucData[1] */ 507 union audio_sample_rates sample_rates; 508 union { 509 /* for LPCM */ 510 uint8_t sample_size; 511 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 512 uint8_t max_bit_rate; 513 /* for Audio Formats 9-15 */ 514 uint8_t vendor_specific; 515 }; 516 }; 517 518 struct audio_info { 519 struct audio_info_flags flags; 520 uint32_t video_latency; 521 uint32_t audio_latency; 522 uint32_t display_index; 523 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 524 uint32_t manufacture_id; 525 uint32_t product_id; 526 /* PortID used for ContainerID when defined */ 527 uint32_t port_id[2]; 528 uint32_t mode_count; 529 /* this field must be last in this struct */ 530 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 531 }; 532 struct audio_check { 533 unsigned int audio_packet_type; 534 unsigned int max_audiosample_rate; 535 unsigned int acat; 536 }; 537 enum dc_infoframe_type { 538 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 539 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 540 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 541 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 542 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 543 }; 544 545 struct dc_info_packet { 546 bool valid; 547 uint8_t hb0; 548 uint8_t hb1; 549 uint8_t hb2; 550 uint8_t hb3; 551 uint8_t sb[32]; 552 }; 553 554 struct dc_info_packet_128 { 555 bool valid; 556 uint8_t hb0; 557 uint8_t hb1; 558 uint8_t hb2; 559 uint8_t hb3; 560 uint8_t sb[128]; 561 }; 562 563 #define DC_PLANE_UPDATE_TIMES_MAX 10 564 565 struct dc_plane_flip_time { 566 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 567 unsigned int index; 568 unsigned int prev_update_time_in_us; 569 }; 570 571 enum dc_psr_state { 572 PSR_STATE0 = 0x0, 573 PSR_STATE1, 574 PSR_STATE1a, 575 PSR_STATE2, 576 PSR_STATE2a, 577 PSR_STATE2b, 578 PSR_STATE3, 579 PSR_STATE3Init, 580 PSR_STATE4, 581 PSR_STATE4a, 582 PSR_STATE4b, 583 PSR_STATE4c, 584 PSR_STATE4d, 585 PSR_STATE4_FULL_FRAME, 586 PSR_STATE4a_FULL_FRAME, 587 PSR_STATE4b_FULL_FRAME, 588 PSR_STATE4c_FULL_FRAME, 589 PSR_STATE4_FULL_FRAME_POWERUP, 590 PSR_STATE4_FULL_FRAME_HW_LOCK, 591 PSR_STATE5, 592 PSR_STATE5a, 593 PSR_STATE5b, 594 PSR_STATE5c, 595 PSR_STATE_HWLOCK_MGR, 596 PSR_STATE_POLLVUPDATE, 597 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME, 598 PSR_STATE_INVALID = 0xFF 599 }; 600 601 struct psr_config { 602 unsigned char psr_version; 603 unsigned int psr_rfb_setup_time; 604 bool psr_exit_link_training_required; 605 bool psr_frame_capture_indication_req; 606 unsigned int psr_sdp_transmit_line_num_deadline; 607 bool allow_smu_optimizations; 608 bool allow_multi_disp_optimizations; 609 /* Panel self refresh 2 selective update granularity required */ 610 bool su_granularity_required; 611 /* psr2 selective update y granularity capability */ 612 uint8_t su_y_granularity; 613 unsigned int line_time_in_us; 614 uint8_t rate_control_caps; 615 uint16_t dsc_slice_height; 616 }; 617 618 union dmcu_psr_level { 619 struct { 620 unsigned int SKIP_CRC:1; 621 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 622 unsigned int SKIP_PHY_POWER_DOWN:1; 623 unsigned int SKIP_AUX_ACK_CHECK:1; 624 unsigned int SKIP_CRTC_DISABLE:1; 625 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 626 unsigned int SKIP_SMU_NOTIFICATION:1; 627 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 628 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 629 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 630 unsigned int DISABLE_ALPM:1; 631 unsigned int ALPM_DEFAULT_PD_MODE:1; 632 unsigned int RESERVED:20; 633 } bits; 634 unsigned int u32all; 635 }; 636 637 enum physical_phy_id { 638 PHYLD_0, 639 PHYLD_1, 640 PHYLD_2, 641 PHYLD_3, 642 PHYLD_4, 643 PHYLD_5, 644 PHYLD_6, 645 PHYLD_7, 646 PHYLD_8, 647 PHYLD_9, 648 PHYLD_COUNT, 649 PHYLD_UNKNOWN = (-1L) 650 }; 651 652 enum phy_type { 653 PHY_TYPE_UNKNOWN = 1, 654 PHY_TYPE_PCIE_PHY = 2, 655 PHY_TYPE_UNIPHY = 3, 656 }; 657 658 struct psr_context { 659 /* ddc line */ 660 enum channel_id channel; 661 /* Transmitter id */ 662 enum transmitter transmitterId; 663 /* Engine Id is used for Dig Be source select */ 664 enum engine_id engineId; 665 /* Controller Id used for Dig Fe source select */ 666 enum controller_id controllerId; 667 /* Pcie or Uniphy */ 668 enum phy_type phyType; 669 /* Physical PHY Id used by SMU interpretation */ 670 enum physical_phy_id smuPhyId; 671 /* Vertical total pixels from crtc timing. 672 * This is used for static screen detection. 673 * ie. If we want to detect half a frame, 674 * we use this to determine the hyst lines. 675 */ 676 unsigned int crtcTimingVerticalTotal; 677 /* PSR supported from panel capabilities and 678 * current display configuration 679 */ 680 bool psrSupportedDisplayConfig; 681 /* Whether fast link training is supported by the panel */ 682 bool psrExitLinkTrainingRequired; 683 /* If RFB setup time is greater than the total VBLANK time, 684 * it is not possible for the sink to capture the video frame 685 * in the same frame the SDP is sent. In this case, 686 * the frame capture indication bit should be set and an extra 687 * static frame should be transmitted to the sink. 688 */ 689 bool psrFrameCaptureIndicationReq; 690 /* Set the last possible line SDP may be transmitted without violating 691 * the RFB setup time or entering the active video frame. 692 */ 693 unsigned int sdpTransmitLineNumDeadline; 694 /* The VSync rate in Hz used to calculate the 695 * step size for smooth brightness feature 696 */ 697 unsigned int vsync_rate_hz; 698 unsigned int skipPsrWaitForPllLock; 699 unsigned int numberOfControllers; 700 /* Unused, for future use. To indicate that first changed frame from 701 * state3 shouldn't result in psr_inactive, but rather to perform 702 * an automatic single frame rfb_update. 703 */ 704 bool rfb_update_auto_en; 705 /* Number of frame before entering static screen */ 706 unsigned int timehyst_frames; 707 /* Partial frames before entering static screen */ 708 unsigned int hyst_lines; 709 /* # of repeated AUX transaction attempts to make before 710 * indicating failure to the driver 711 */ 712 unsigned int aux_repeats; 713 /* Controls hw blocks to power down during PSR active state */ 714 union dmcu_psr_level psr_level; 715 /* Controls additional delay after remote frame capture before 716 * continuing powerd own 717 */ 718 unsigned int frame_delay; 719 bool allow_smu_optimizations; 720 bool allow_multi_disp_optimizations; 721 /* Panel self refresh 2 selective update granularity required */ 722 bool su_granularity_required; 723 /* psr2 selective update y granularity capability */ 724 uint8_t su_y_granularity; 725 unsigned int line_time_in_us; 726 uint8_t rate_control_caps; 727 uint16_t dsc_slice_height; 728 }; 729 730 struct colorspace_transform { 731 struct fixed31_32 matrix[12]; 732 bool enable_remap; 733 }; 734 735 enum i2c_mot_mode { 736 I2C_MOT_UNDEF, 737 I2C_MOT_TRUE, 738 I2C_MOT_FALSE 739 }; 740 741 struct AsicStateEx { 742 unsigned int memoryClock; 743 unsigned int displayClock; 744 unsigned int engineClock; 745 unsigned int maxSupportedDppClock; 746 unsigned int dppClock; 747 unsigned int socClock; 748 unsigned int dcfClockDeepSleep; 749 unsigned int fClock; 750 unsigned int phyClock; 751 }; 752 753 754 enum dc_clock_type { 755 DC_CLOCK_TYPE_DISPCLK = 0, 756 DC_CLOCK_TYPE_DPPCLK = 1, 757 }; 758 759 struct dc_clock_config { 760 uint32_t max_clock_khz; 761 uint32_t min_clock_khz; 762 uint32_t bw_requirequired_clock_khz; 763 uint32_t current_clock_khz;/*current clock in use*/ 764 }; 765 766 struct hw_asic_id { 767 uint32_t chip_id; 768 uint32_t chip_family; 769 uint32_t pci_revision_id; 770 uint32_t hw_internal_rev; 771 uint32_t vram_type; 772 uint32_t vram_width; 773 uint32_t feature_flags; 774 uint32_t fake_paths_num; 775 void *atombios_base_address; 776 }; 777 778 struct dc_context { 779 struct dc *dc; 780 781 void *driver_context; /* e.g. amdgpu_device */ 782 struct dal_logger *logger; 783 struct dc_perf_trace *perf_trace; 784 void *cgs_device; 785 786 enum dce_environment dce_environment; 787 struct hw_asic_id asic_id; 788 789 /* todo: below should probably move to dc. to facilitate removal 790 * of AS we will store these here 791 */ 792 enum dce_version dce_version; 793 struct dc_bios *dc_bios; 794 bool created_bios; 795 struct gpio_service *gpio_service; 796 uint32_t dc_sink_id_count; 797 uint32_t dc_stream_id_count; 798 uint32_t dc_edp_id_count; 799 uint64_t fbc_gpu_addr; 800 struct dc_dmub_srv *dmub_srv; 801 struct cp_psp cp_psp; 802 uint32_t *dcn_reg_offsets; 803 uint32_t *nbio_reg_offsets; 804 uint32_t *clk_reg_offsets; 805 }; 806 807 /* DSC DPCD capabilities */ 808 union dsc_slice_caps1 { 809 struct { 810 uint8_t NUM_SLICES_1 : 1; 811 uint8_t NUM_SLICES_2 : 1; 812 uint8_t RESERVED : 1; 813 uint8_t NUM_SLICES_4 : 1; 814 uint8_t NUM_SLICES_6 : 1; 815 uint8_t NUM_SLICES_8 : 1; 816 uint8_t NUM_SLICES_10 : 1; 817 uint8_t NUM_SLICES_12 : 1; 818 } bits; 819 uint8_t raw; 820 }; 821 822 union dsc_slice_caps2 { 823 struct { 824 uint8_t NUM_SLICES_16 : 1; 825 uint8_t NUM_SLICES_20 : 1; 826 uint8_t NUM_SLICES_24 : 1; 827 uint8_t RESERVED : 5; 828 } bits; 829 uint8_t raw; 830 }; 831 832 union dsc_color_formats { 833 struct { 834 uint8_t RGB : 1; 835 uint8_t YCBCR_444 : 1; 836 uint8_t YCBCR_SIMPLE_422 : 1; 837 uint8_t YCBCR_NATIVE_422 : 1; 838 uint8_t YCBCR_NATIVE_420 : 1; 839 uint8_t RESERVED : 3; 840 } bits; 841 uint8_t raw; 842 }; 843 844 union dsc_color_depth { 845 struct { 846 uint8_t RESERVED1 : 1; 847 uint8_t COLOR_DEPTH_8_BPC : 1; 848 uint8_t COLOR_DEPTH_10_BPC : 1; 849 uint8_t COLOR_DEPTH_12_BPC : 1; 850 uint8_t RESERVED2 : 3; 851 } bits; 852 uint8_t raw; 853 }; 854 855 struct dsc_dec_dpcd_caps { 856 bool is_dsc_supported; 857 uint8_t dsc_version; 858 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 859 union dsc_slice_caps1 slice_caps1; 860 union dsc_slice_caps2 slice_caps2; 861 int32_t lb_bit_depth; 862 bool is_block_pred_supported; 863 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 864 union dsc_color_formats color_formats; 865 union dsc_color_depth color_depth; 866 int32_t throughput_mode_0_mps; /* In MPs */ 867 int32_t throughput_mode_1_mps; /* In MPs */ 868 int32_t max_slice_width; 869 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 870 871 /* Extended DSC caps */ 872 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 873 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 874 uint32_t branch_max_line_width; 875 bool is_dp; /* Decoded format */ 876 }; 877 878 struct hblank_expansion_dpcd_caps { 879 bool expansion_supported; 880 bool reduction_supported; 881 bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/ 882 bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/ 883 uint32_t buffer_size; /* Add 1 to value and multiply by 32 */ 884 }; 885 886 struct dc_golden_table { 887 uint16_t dc_golden_table_ver; 888 uint32_t aux_dphy_rx_control0_val; 889 uint32_t aux_dphy_tx_control_val; 890 uint32_t aux_dphy_rx_control1_val; 891 uint32_t dc_gpio_aux_ctrl_0_val; 892 uint32_t dc_gpio_aux_ctrl_1_val; 893 uint32_t dc_gpio_aux_ctrl_2_val; 894 uint32_t dc_gpio_aux_ctrl_3_val; 895 uint32_t dc_gpio_aux_ctrl_4_val; 896 uint32_t dc_gpio_aux_ctrl_5_val; 897 }; 898 899 enum dc_gpu_mem_alloc_type { 900 DC_MEM_ALLOC_TYPE_GART, 901 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 902 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 903 DC_MEM_ALLOC_TYPE_AGP 904 }; 905 906 enum dc_link_encoding_format { 907 DC_LINK_ENCODING_UNSPECIFIED = 0, 908 DC_LINK_ENCODING_DP_8b_10b, 909 DC_LINK_ENCODING_DP_128b_132b, 910 DC_LINK_ENCODING_HDMI_TMDS, 911 DC_LINK_ENCODING_HDMI_FRL 912 }; 913 914 enum dc_psr_version { 915 DC_PSR_VERSION_1 = 0, 916 DC_PSR_VERSION_SU_1 = 1, 917 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 918 }; 919 920 /* Possible values of display_endpoint_id.endpoint */ 921 enum display_endpoint_type { 922 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 923 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 924 DISPLAY_ENDPOINT_UNKNOWN = -1 925 }; 926 927 /* Extends graphics_object_id with an additional member 'ep_type' for 928 * distinguishing between physical endpoints (with entries in BIOS connector table) and 929 * logical endpoints. 930 */ 931 struct display_endpoint_id { 932 struct graphics_object_id link_id; 933 enum display_endpoint_type ep_type; 934 }; 935 936 enum backlight_control_type { 937 BACKLIGHT_CONTROL_PWM = 0, 938 BACKLIGHT_CONTROL_VESA_AUX = 1, 939 BACKLIGHT_CONTROL_AMD_AUX = 2, 940 }; 941 942 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 943 #define MAX_CRC_WINDOW_NUM 2 944 945 struct otg_phy_mux { 946 uint8_t phy_output_num; 947 uint8_t otg_output_num; 948 }; 949 950 struct crc_window { 951 struct rect rect; 952 bool enable; 953 }; 954 #endif 955 956 enum dc_detect_reason { 957 DETECT_REASON_BOOT, 958 DETECT_REASON_RESUMEFROMS3S4, 959 DETECT_REASON_HPD, 960 DETECT_REASON_HPDRX, 961 DETECT_REASON_FALLBACK, 962 DETECT_REASON_RETRAIN, 963 DETECT_REASON_TDR, 964 }; 965 966 struct dc_link_status { 967 bool link_active; 968 struct dpcd_caps *dpcd_caps; 969 }; 970 971 union hdcp_rx_caps { 972 struct { 973 uint8_t version; 974 uint8_t reserved; 975 struct { 976 uint8_t repeater : 1; 977 uint8_t hdcp_capable : 1; 978 uint8_t reserved : 6; 979 } byte0; 980 } fields; 981 uint8_t raw[3]; 982 }; 983 984 union hdcp_bcaps { 985 struct { 986 uint8_t HDCP_CAPABLE:1; 987 uint8_t REPEATER:1; 988 uint8_t RESERVED:6; 989 } bits; 990 uint8_t raw; 991 }; 992 993 struct hdcp_caps { 994 union hdcp_rx_caps rx_caps; 995 union hdcp_bcaps bcaps; 996 }; 997 998 /* DP MST stream allocation (payload bandwidth number) */ 999 struct link_mst_stream_allocation { 1000 /* DIG front */ 1001 const struct stream_encoder *stream_enc; 1002 /* HPO DP Stream Encoder */ 1003 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 1004 /* associate DRM payload table with DC stream encoder */ 1005 uint8_t vcp_id; 1006 /* number of slots required for the DP stream in transport packet */ 1007 uint8_t slot_count; 1008 }; 1009 1010 #define MAX_CONTROLLER_NUM 6 1011 1012 /* DP MST stream allocation table */ 1013 struct link_mst_stream_allocation_table { 1014 /* number of DP video streams */ 1015 int stream_count; 1016 /* array of stream allocations */ 1017 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 1018 }; 1019 1020 /* PSR feature flags */ 1021 struct psr_settings { 1022 bool psr_feature_enabled; // PSR is supported by sink 1023 bool psr_allow_active; // PSR is currently active 1024 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1025 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1026 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1027 1028 /* These parameters are calculated in Driver, 1029 * based on display timing and Sink capabilities. 1030 * If VBLANK region is too small and Sink takes a long time 1031 * to set up RFB, it may take an extra frame to enter PSR state. 1032 */ 1033 bool psr_frame_capture_indication_req; 1034 unsigned int psr_sdp_transmit_line_num_deadline; 1035 uint8_t force_ffu_mode; 1036 unsigned int psr_power_opt; 1037 1038 /** 1039 * Some panels cannot handle idle pattern during PSR entry. 1040 * To power down phy before disable stream to avoid sending 1041 * idle pattern. 1042 */ 1043 uint8_t power_down_phy_before_disable_stream; 1044 }; 1045 1046 enum replay_coasting_vtotal_type { 1047 PR_COASTING_TYPE_NOM = 0, 1048 PR_COASTING_TYPE_STATIC, 1049 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1050 PR_COASTING_TYPE_TEST_HARNESS, 1051 PR_COASTING_TYPE_NUM, 1052 }; 1053 1054 enum replay_link_off_frame_count_level { 1055 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0, 1056 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2, 1057 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6, 1058 }; 1059 1060 /* 1061 * This is general Interface for Replay to 1062 * set an 32 bit variable to dmub 1063 * The Message_type indicates which variable 1064 * passed to DMUB. 1065 */ 1066 enum replay_FW_Message_type { 1067 Replay_Msg_Not_Support = -1, 1068 Replay_Set_Timing_Sync_Supported, 1069 Replay_Set_Residency_Frameupdate_Timer, 1070 Replay_Set_Pseudo_VTotal, 1071 Replay_Disabled_Adaptive_Sync_SDP, 1072 Replay_Set_General_Cmd, 1073 }; 1074 1075 union replay_error_status { 1076 struct { 1077 unsigned int STATE_TRANSITION_ERROR :1; 1078 unsigned int LINK_CRC_ERROR :1; 1079 unsigned int DESYNC_ERROR :1; 1080 unsigned int RESERVED_3 :1; 1081 unsigned int LOW_RR_INCORRECT_VTOTAL :1; 1082 unsigned int NO_DOUBLED_RR :1; 1083 unsigned int RESERVED_6_7 :2; 1084 } bits; 1085 unsigned char raw; 1086 }; 1087 1088 union replay_low_refresh_rate_enable_options { 1089 struct { 1090 //BIT[0-3]: Replay Low Hz Support control 1091 unsigned int ENABLE_LOW_RR_SUPPORT :1; 1092 unsigned int RESERVED_1_3 :3; 1093 //BIT[4-15]: Replay Low Hz Enable Scenarios 1094 unsigned int ENABLE_STATIC_SCREEN :1; 1095 unsigned int ENABLE_FULL_SCREEN_VIDEO :1; 1096 unsigned int ENABLE_GENERAL_UI :1; 1097 unsigned int RESERVED_7_15 :9; 1098 //BIT[16-31]: Replay Low Hz Enable Check 1099 unsigned int ENABLE_STATIC_FLICKER_CHECK :1; 1100 unsigned int RESERVED_17_31 :15; 1101 } bits; 1102 unsigned int raw; 1103 }; 1104 1105 struct replay_config { 1106 /* Replay feature is supported */ 1107 bool replay_supported; 1108 /* Replay caps support DPCD & EDID caps*/ 1109 bool replay_cap_support; 1110 /* Power opt flags that are supported */ 1111 unsigned int replay_power_opt_supported; 1112 /* SMU optimization is supported */ 1113 bool replay_smu_opt_supported; 1114 /* Replay enablement option */ 1115 unsigned int replay_enable_option; 1116 /* Replay debug flags */ 1117 uint32_t debug_flags; 1118 /* Replay sync is supported */ 1119 bool replay_timing_sync_supported; 1120 /* Replay Disable desync error check. */ 1121 bool force_disable_desync_error_check; 1122 /* Replay Received Desync Error HPD. */ 1123 bool received_desync_error_hpd; 1124 /* Replay feature is supported long vblank */ 1125 bool replay_support_fast_resync_in_ultra_sleep_mode; 1126 /* Replay error status */ 1127 union replay_error_status replay_error_status; 1128 /* Replay Low Hz enable Options */ 1129 union replay_low_refresh_rate_enable_options low_rr_enable_options; 1130 /* Replay coasting vtotal is within low refresh rate range. */ 1131 bool low_rr_activated; 1132 }; 1133 1134 /* Replay feature flags*/ 1135 struct replay_settings { 1136 /* Replay configuration */ 1137 struct replay_config config; 1138 /* Replay feature is ready for activating */ 1139 bool replay_feature_enabled; 1140 /* Replay is currently active */ 1141 bool replay_allow_active; 1142 /* Replay is currently active */ 1143 bool replay_allow_long_vblank; 1144 /* Power opt flags that are activated currently */ 1145 unsigned int replay_power_opt_active; 1146 /* SMU optimization is enabled */ 1147 bool replay_smu_opt_enable; 1148 /* Current Coasting vtotal */ 1149 uint32_t coasting_vtotal; 1150 /* Coasting vtotal table */ 1151 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1152 /* Defer Update Coasting vtotal table */ 1153 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1154 /* Maximum link off frame count */ 1155 uint32_t link_off_frame_count; 1156 /* Replay pseudo vtotal for low refresh rate*/ 1157 uint16_t low_rr_full_screen_video_pseudo_vtotal; 1158 /* Replay last pseudo vtotal set to DMUB */ 1159 uint16_t last_pseudo_vtotal; 1160 /* Replay desync error */ 1161 uint32_t replay_desync_error_fail_count; 1162 }; 1163 1164 /* To split out "global" and "per-panel" config settings. 1165 * Add a struct dc_panel_config under dc_link 1166 */ 1167 struct dc_panel_config { 1168 /* extra panel power sequence parameters */ 1169 struct pps { 1170 unsigned int extra_t3_ms; 1171 unsigned int extra_t7_ms; 1172 unsigned int extra_delay_backlight_off; 1173 unsigned int extra_post_t7_ms; 1174 unsigned int extra_pre_t11_ms; 1175 unsigned int extra_t12_ms; 1176 unsigned int extra_post_OUI_ms; 1177 } pps; 1178 /* nit brightness */ 1179 struct nits_brightness { 1180 unsigned int peak; /* nits */ 1181 unsigned int max_avg; /* nits */ 1182 unsigned int min; /* 1/10000 nits */ 1183 unsigned int max_nonboost_brightness_millinits; 1184 unsigned int min_brightness_millinits; 1185 } nits_brightness; 1186 /* PSR */ 1187 struct psr { 1188 bool disable_psr; 1189 bool disallow_psrsu; 1190 bool disallow_replay; 1191 bool rc_disable; 1192 bool rc_allow_static_screen; 1193 bool rc_allow_fullscreen_VPB; 1194 unsigned int replay_enable_option; 1195 } psr; 1196 /* ABM */ 1197 struct varib { 1198 unsigned int varibright_feature_enable; 1199 unsigned int def_varibright_level; 1200 unsigned int abm_config_setting; 1201 } varib; 1202 /* edp DSC */ 1203 struct dsc { 1204 bool disable_dsc_edp; 1205 unsigned int force_dsc_edp_policy; 1206 } dsc; 1207 /* eDP ILR */ 1208 struct ilr { 1209 bool optimize_edp_link_rate; /* eDP ILR */ 1210 } ilr; 1211 }; 1212 1213 #define MAX_SINKS_PER_LINK 4 1214 1215 /* 1216 * USB4 DPIA BW ALLOCATION STRUCTS 1217 */ 1218 struct dc_dpia_bw_alloc { 1219 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1220 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1221 int link_max_bw; // The Max BW that link can require/support 1222 int allocated_bw; // The Actual Allocated BW for this DPIA 1223 int estimated_bw; // The estimated available BW for this DPIA 1224 int bw_granularity; // BW Granularity 1225 int dp_overhead; // DP overhead in dp tunneling 1226 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1227 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1228 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1229 }; 1230 1231 enum dc_hpd_enable_select { 1232 HPD_EN_FOR_ALL_EDP = 0, 1233 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1234 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1235 }; 1236 1237 enum dc_cm2_shaper_3dlut_setting { 1238 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL, 1239 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER, 1240 /* Bypassing Shaper will always bypass 3DLUT */ 1241 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT 1242 }; 1243 1244 enum dc_cm2_gpu_mem_layout { 1245 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB, 1246 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR, 1247 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR 1248 }; 1249 1250 enum dc_cm2_gpu_mem_pixel_component_order { 1251 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, 1252 }; 1253 1254 enum dc_cm2_gpu_mem_format { 1255 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB, 1256 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB, 1257 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10 1258 }; 1259 1260 struct dc_cm2_gpu_mem_format_parameters { 1261 enum dc_cm2_gpu_mem_format format; 1262 union { 1263 struct { 1264 /* bias & scale for float only */ 1265 uint16_t bias; 1266 uint16_t scale; 1267 } float_params; 1268 }; 1269 }; 1270 1271 enum dc_cm2_gpu_mem_size { 1272 DC_CM2_GPU_MEM_SIZE_171717, 1273 DC_CM2_GPU_MEM_SIZE_TRANSFORMED 1274 }; 1275 1276 struct dc_cm2_gpu_mem_parameters { 1277 struct dc_plane_address addr; 1278 enum dc_cm2_gpu_mem_layout layout; 1279 struct dc_cm2_gpu_mem_format_parameters format_params; 1280 enum dc_cm2_gpu_mem_pixel_component_order component_order; 1281 enum dc_cm2_gpu_mem_size size; 1282 }; 1283 1284 enum dc_cm2_transfer_func_source { 1285 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM, 1286 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM 1287 }; 1288 1289 struct dc_cm2_component_settings { 1290 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting; 1291 bool lut1d_enable; 1292 }; 1293 1294 /* 1295 * All pointers in this struct must remain valid for as long as the 3DLUTs are used 1296 */ 1297 struct dc_cm2_func_luts { 1298 const struct dc_transfer_func *shaper; 1299 struct { 1300 enum dc_cm2_transfer_func_source lut3d_src; 1301 union { 1302 const struct dc_3dlut *lut3d_func; 1303 struct dc_cm2_gpu_mem_parameters gpu_mem_params; 1304 }; 1305 } lut3d_data; 1306 const struct dc_transfer_func *lut1d_func; 1307 }; 1308 1309 struct dc_cm2_parameters { 1310 struct dc_cm2_component_settings component_settings; 1311 struct dc_cm2_func_luts cm2_luts; 1312 }; 1313 1314 enum mall_stream_type { 1315 SUBVP_NONE, // subvp not in use 1316 SUBVP_MAIN, // subvp in use, this stream is main stream 1317 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 1318 }; 1319 1320 enum dc_power_source_type { 1321 DC_POWER_SOURCE_AC, // wall power 1322 DC_POWER_SOURCE_DC, // battery power 1323 }; 1324 1325 struct dc_state_create_params { 1326 enum dc_power_source_type power_source; 1327 }; 1328 1329 struct dc_commit_streams_params { 1330 struct dc_stream_state **streams; 1331 uint8_t stream_count; 1332 enum dc_power_source_type power_source; 1333 }; 1334 1335 struct set_backlight_level_params { 1336 /* backlight in pwm */ 1337 uint32_t backlight_pwm_u16_16; 1338 /* brightness ramping */ 1339 uint32_t frame_ramp; 1340 /* backlight control type 1341 * 0: PWM backlight control 1342 * 1: VESA AUX backlight control 1343 * 2: AMD AUX backlight control 1344 */ 1345 enum backlight_control_type control_type; 1346 /* backlight in millinits */ 1347 uint32_t backlight_millinits; 1348 /* transition time in ms */ 1349 uint32_t transition_time_in_ms; 1350 /* minimum luminance in nits */ 1351 uint32_t min_luminance; 1352 /* maximum luminance in nits */ 1353 uint32_t max_luminance; 1354 /* minimum backlight in pwm */ 1355 uint32_t min_backlight_pwm; 1356 /* maximum backlight in pwm */ 1357 uint32_t max_backlight_pwm; 1358 /* AUX HW instance */ 1359 uint8_t aux_inst; 1360 }; 1361 1362 #endif /* DC_TYPES_H_ */ 1363