1 /*- 2 * Copyright (C) 2006-2012 Semihalf 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 /*- 26 * Copyright (C) 2001 Benno Rice 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 1. Redistributions of source code must retain the above copyright 33 * notice, this list of conditions and the following disclaimer. 34 * 2. Redistributions in binary form must reproduce the above copyright 35 * notice, this list of conditions and the following disclaimer in the 36 * documentation and/or other materials provided with the distribution. 37 * 38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 49 */ 50 /*- 51 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 52 * Copyright (C) 1995, 1996 TooLs GmbH. 53 * All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 3. All advertising materials mentioning features or use of this software 64 * must display the following acknowledgement: 65 * This product includes software developed by TooLs GmbH. 66 * 4. The name of TooLs GmbH may not be used to endorse or promote products 67 * derived from this software without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 #include "opt_ddb.h" 83 #include "opt_hwpmc_hooks.h" 84 #include "opt_kstack_pages.h" 85 #include "opt_platform.h" 86 87 #include <sys/types.h> 88 #include <sys/param.h> 89 #include <sys/proc.h> 90 #include <sys/systm.h> 91 #include <sys/time.h> 92 #include <sys/bio.h> 93 #include <sys/buf.h> 94 #include <sys/bus.h> 95 #include <sys/cons.h> 96 #include <sys/cpu.h> 97 #include <sys/kdb.h> 98 #include <sys/kernel.h> 99 #include <sys/lock.h> 100 #include <sys/malloc.h> 101 #include <sys/mutex.h> 102 #include <sys/rwlock.h> 103 #include <sys/sysctl.h> 104 #include <sys/exec.h> 105 #include <sys/ktr.h> 106 #include <sys/syscallsubr.h> 107 #include <sys/sysproto.h> 108 #include <sys/signalvar.h> 109 #include <sys/sysent.h> 110 #include <sys/imgact.h> 111 #include <sys/msgbuf.h> 112 #include <sys/ptrace.h> 113 114 #include <vm/vm.h> 115 #include <vm/pmap.h> 116 #include <vm/vm_extern.h> 117 #include <vm/vm_page.h> 118 #include <vm/vm_object.h> 119 #include <vm/vm_pager.h> 120 121 #include <machine/cpu.h> 122 #include <machine/kdb.h> 123 #include <machine/vmparam.h> 124 #include <machine/spr.h> 125 #include <machine/hid.h> 126 #include <machine/psl.h> 127 #include <machine/trap.h> 128 #include <machine/md_var.h> 129 #include <machine/mmuvar.h> 130 #include <machine/sigframe.h> 131 #include <machine/machdep.h> 132 #include <machine/metadata.h> 133 #include <machine/platform.h> 134 135 #include <sys/linker.h> 136 #include <sys/reboot.h> 137 138 #include <contrib/libfdt/libfdt.h> 139 #include <dev/fdt/fdt_common.h> 140 #include <dev/ofw/openfirm.h> 141 142 #ifdef DDB 143 #include <ddb/ddb.h> 144 #endif 145 146 #ifdef DEBUG 147 #define debugf(fmt, args...) printf(fmt, ##args) 148 #else 149 #define debugf(fmt, args...) 150 #endif 151 152 extern unsigned char _etext[]; 153 extern unsigned char _edata[]; 154 extern unsigned char __bss_start[]; 155 extern unsigned char __sbss_start[]; 156 extern unsigned char __sbss_end[]; 157 extern unsigned char _end[]; 158 extern vm_offset_t __endkernel; 159 extern vm_paddr_t kernload; 160 161 /* 162 * Bootinfo is passed to us by legacy loaders. Save the address of the 163 * structure to handle backward compatibility. 164 */ 165 uint32_t *bootinfo; 166 167 void print_kernel_section_addr(void); 168 void print_kenv(void); 169 uintptr_t booke_init(u_long, u_long); 170 void ivor_setup(void); 171 172 extern void *interrupt_vector_base; 173 extern void *int_critical_input; 174 extern void *int_machine_check; 175 extern void *int_data_storage; 176 extern void *int_instr_storage; 177 extern void *int_external_input; 178 extern void *int_alignment; 179 extern void *int_fpu; 180 extern void *int_program; 181 extern void *int_syscall; 182 extern void *int_decrementer; 183 extern void *int_fixed_interval_timer; 184 extern void *int_watchdog; 185 extern void *int_data_tlb_error; 186 extern void *int_inst_tlb_error; 187 extern void *int_debug; 188 extern void *int_debug_ed; 189 extern void *int_vec; 190 extern void *int_vecast; 191 #ifdef HWPMC_HOOKS 192 extern void *int_performance_counter; 193 #endif 194 195 #define SET_TRAP(ivor, handler) \ 196 KASSERT(((uintptr_t)(&handler) & ~0xffffUL) == \ 197 ((uintptr_t)(&interrupt_vector_base) & ~0xffffUL), \ 198 ("Handler " #handler " too far from interrupt vector base")); \ 199 mtspr(ivor, (uintptr_t)(&handler) & 0xffffUL); 200 201 uintptr_t powerpc_init(vm_offset_t fdt, vm_offset_t, vm_offset_t, void *mdp, 202 uint32_t mdp_cookie); 203 void booke_cpu_init(void); 204 205 void 206 booke_cpu_init(void) 207 { 208 209 cpu_features |= PPC_FEATURE_BOOKE; 210 211 psl_kernset = PSL_CE | PSL_ME | PSL_EE; 212 #ifdef __powerpc64__ 213 psl_kernset |= PSL_CM; 214 #endif 215 psl_userset = psl_kernset | PSL_PR; 216 #ifdef __powerpc64__ 217 psl_userset32 = psl_userset & ~PSL_CM; 218 #endif 219 /* 220 * Zeroed bits in this variable signify that the value of the bit 221 * in its position is allowed to vary between userspace contexts. 222 * 223 * All other bits are required to be identical for every userspace 224 * context. The actual *value* of the bit is determined by 225 * psl_userset and/or psl_userset32, and is not allowed to change. 226 * 227 * Remember to update this set when implementing support for 228 * *conditionally* enabling a processor facility. Failing to do 229 * this will cause swapcontext() in userspace to break when a 230 * process uses a conditionally-enabled facility. 231 * 232 * When *unconditionally* implementing support for a processor 233 * facility, update psl_userset / psl_userset32 instead. 234 * 235 * See the access control check in set_mcontext(). 236 */ 237 psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); 238 239 pmap_mmu_install(MMU_TYPE_BOOKE, BUS_PROBE_GENERIC); 240 } 241 242 void 243 ivor_setup(void) 244 { 245 246 mtspr(SPR_IVPR, ((uintptr_t)&interrupt_vector_base) & ~0xffffUL); 247 248 SET_TRAP(SPR_IVOR0, int_critical_input); 249 SET_TRAP(SPR_IVOR1, int_machine_check); 250 SET_TRAP(SPR_IVOR2, int_data_storage); 251 SET_TRAP(SPR_IVOR3, int_instr_storage); 252 SET_TRAP(SPR_IVOR4, int_external_input); 253 SET_TRAP(SPR_IVOR5, int_alignment); 254 SET_TRAP(SPR_IVOR6, int_program); 255 SET_TRAP(SPR_IVOR8, int_syscall); 256 SET_TRAP(SPR_IVOR10, int_decrementer); 257 SET_TRAP(SPR_IVOR11, int_fixed_interval_timer); 258 SET_TRAP(SPR_IVOR12, int_watchdog); 259 SET_TRAP(SPR_IVOR13, int_data_tlb_error); 260 SET_TRAP(SPR_IVOR14, int_inst_tlb_error); 261 SET_TRAP(SPR_IVOR15, int_debug); 262 #ifdef HWPMC_HOOKS 263 SET_TRAP(SPR_IVOR35, int_performance_counter); 264 #endif 265 switch ((mfpvr() >> 16) & 0xffff) { 266 case FSL_E6500: 267 SET_TRAP(SPR_IVOR32, int_vec); 268 SET_TRAP(SPR_IVOR33, int_vecast); 269 /* FALLTHROUGH */ 270 case FSL_E500mc: 271 case FSL_E5500: 272 SET_TRAP(SPR_IVOR7, int_fpu); 273 SET_TRAP(SPR_IVOR15, int_debug_ed); 274 break; 275 case FSL_E500v1: 276 case FSL_E500v2: 277 SET_TRAP(SPR_IVOR32, int_vec); 278 break; 279 } 280 281 #ifdef __powerpc64__ 282 /* Set 64-bit interrupt mode. */ 283 mtspr(SPR_EPCR, mfspr(SPR_EPCR) | EPCR_ICM); 284 #endif 285 } 286 287 static int 288 booke_check_for_fdt(uint32_t arg1, vm_offset_t *dtbp) 289 { 290 void *ptr; 291 int fdt_size; 292 293 if (arg1 % 8 != 0) 294 return (-1); 295 296 ptr = (void *)pmap_early_io_map(arg1, PAGE_SIZE); 297 if (fdt_check_header(ptr) != 0) 298 return (-1); 299 300 /* 301 * Read FDT total size from the header of FDT. 302 * This for sure hits within first page which is 303 * already mapped. 304 */ 305 fdt_size = fdt_totalsize((void *)ptr); 306 307 /* 308 * Ok, arg1 points to FDT, so we need to map it in. 309 * First, unmap this page and then map FDT again with full size 310 */ 311 pmap_early_io_unmap((vm_offset_t)ptr, PAGE_SIZE); 312 ptr = (void *)pmap_early_io_map(arg1, fdt_size); 313 *dtbp = (vm_offset_t)ptr; 314 315 return (0); 316 } 317 318 uintptr_t 319 booke_init(u_long arg1, u_long arg2) 320 { 321 uintptr_t ret; 322 void *mdp; 323 vm_offset_t dtbp, end; 324 325 end = (uintptr_t)_end; 326 dtbp = (vm_offset_t)NULL; 327 328 /* Set up TLB initially */ 329 bootinfo = NULL; 330 bzero(__sbss_start, __sbss_end - __sbss_start); 331 bzero(__bss_start, _end - __bss_start); 332 tlb1_init(); 333 334 /* 335 * Handle the various ways we can get loaded and started: 336 * - FreeBSD's loader passes the pointer to the metadata 337 * in arg1, with arg2 undefined. arg1 has a value that's 338 * relative to the kernel's link address (i.e. larger 339 * than 0xc0000000). 340 * - Juniper's loader passes the metadata pointer in arg2 341 * and sets arg1 to zero. This is to signal that the 342 * loader maps the kernel and starts it at its link 343 * address (unlike the FreeBSD loader). 344 * - U-Boot passes the standard argc and argv parameters 345 * in arg1 and arg2 (resp). arg1 is between 1 and some 346 * relatively small number, such as 64K. arg2 is the 347 * physical address of the argv vector. 348 * - ePAPR loaders pass an FDT blob in r3 (arg1) and the magic hex 349 * string 0x45504150 ('EPAP') in r6 (which has been lost by now). 350 * r4 (arg2) is supposed to be set to zero, but is not always. 351 */ 352 353 if (arg1 == 0) /* Juniper loader */ 354 mdp = (void *)arg2; 355 else if (booke_check_for_fdt(arg1, &dtbp) == 0) { /* ePAPR */ 356 end = roundup(end, 8); 357 memmove((void *)end, (void *)dtbp, fdt_totalsize((void *)dtbp)); 358 dtbp = end; 359 end += fdt_totalsize((void *)dtbp); 360 __endkernel = end; 361 mdp = NULL; 362 } else if (arg1 > (uintptr_t)kernload) /* FreeBSD loader */ 363 mdp = (void *)arg1; 364 else /* U-Boot */ 365 mdp = NULL; 366 367 /* Default to 32 byte cache line size. */ 368 switch ((mfpvr()) >> 16) { 369 case FSL_E500mc: 370 case FSL_E5500: 371 case FSL_E6500: 372 cacheline_size = 64; 373 break; 374 } 375 376 /* 377 * Last element is a magic cookie that indicates that the metadata 378 * pointer is meaningful. 379 */ 380 ret = powerpc_init(dtbp, 0, 0, mdp, (mdp == NULL) ? 0 : 0xfb5d104d); 381 382 /* Enable caches */ 383 booke_enable_l1_cache(); 384 booke_enable_l2_cache(); 385 386 booke_enable_bpred(); 387 388 return (ret); 389 } 390 391 #define RES_GRANULE cacheline_size 392 extern uintptr_t tlb0_miss_locks[]; 393 394 /* 395 * Stack for critical-class interrupts taken in kernel mode on the boot CPU. 396 * It is static because the boot CPU is initialised long before the VM is 397 * running; APs reach cpu_pcpu_init() at SI_SUB_CPU and can allocate. Sizing a 398 * MAXCPU array here would reserve megabytes for CPUs that do not exist. 399 */ 400 static char booke_boot_critstack[BOOKE_CRITSTACK_SIZE] __aligned(16); 401 static char booke_boot_mchkstack[BOOKE_CRITSTACK_SIZE] __aligned(16); 402 static bool booke_boot_critstack_used; 403 404 /* Initialise a struct pcpu. */ 405 void 406 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 407 { 408 char *critstack, *mchkstack; 409 410 pcpu->pc_booke.tid_next = TID_MIN; 411 412 /* 413 * Machine check and critical interrupts have their own stacks with 414 * their own stack pointer, because regular mode registers cannot be 415 * trusted. 416 */ 417 if (!booke_boot_critstack_used) { 418 booke_boot_critstack_used = true; 419 critstack = booke_boot_critstack; 420 mchkstack = booke_boot_mchkstack; 421 } else { 422 critstack = malloc(BOOKE_CRITSTACK_SIZE, M_DEVBUF, M_WAITOK); 423 mchkstack = malloc(BOOKE_CRITSTACK_SIZE, M_DEVBUF, M_WAITOK); 424 } 425 pcpu->pc_booke.critstack = critstack + BOOKE_CRITSTACK_SIZE; 426 pcpu->pc_booke.mchkstack = mchkstack + BOOKE_CRITSTACK_SIZE; 427 428 #ifdef SMP 429 uintptr_t *ptr; 430 int words_per_gran = RES_GRANULE / sizeof(uintptr_t); 431 432 ptr = &tlb0_miss_locks[cpuid * words_per_gran]; 433 pcpu->pc_booke.tlb_lock = ptr; 434 *ptr = TLB_UNLOCKED; 435 *(ptr + 1) = 0; /* recurse counter */ 436 #endif 437 } 438 439 #ifdef DDB 440 /* 441 * Dump an exception save area. In a nested save, R31 holds the DEAR of the 442 * outer exception. 443 */ 444 static void 445 db_show_booke_save(const char *name, register_t *sv) 446 { 447 448 db_printf("%s r30 %#jx r31 %#jx dear %#jx esr %#jx\n", name, 449 (uintmax_t)sv[CPUSAVE_R30], (uintmax_t)sv[CPUSAVE_R31], 450 (uintmax_t)sv[CPUSAVE_BOOKE_DEAR], 451 (uintmax_t)sv[CPUSAVE_BOOKE_ESR]); 452 db_printf("%s srr0 %#jx srr1 %#jx\n", name, 453 (uintmax_t)sv[CPUSAVE_SRR0], (uintmax_t)sv[CPUSAVE_SRR1]); 454 } 455 456 void 457 cpu_db_show_mdpcpu(struct pcpu *pc) 458 { 459 register_t *tlbsave; 460 int i; 461 462 db_printf("tid_next = %d tlb_level = %#jx critstack = %p\n", 463 pc->pc_booke.tid_next, (uintmax_t)pc->pc_booke.tlb_level, 464 pc->pc_booke.critstack); 465 db_show_booke_save("tempsave", pc->pc_tempsave); 466 db_show_booke_save("disisave", pc->pc_disisave); 467 db_show_booke_save("critsave", pc->pc_booke.critsave); 468 /* 469 * In critsave, CPUSAVE_SRR0-1 hold the interrupt's own CSRR0-1 (DSRR0-1 470 * for the enhanced-debug vector); the non-critical SRR0-1 that were 471 * live at the time are kept separately. 472 */ 473 db_printf("critsave held srr0 %#jx srr1 %#jx\n", 474 (uintmax_t)pc->pc_booke.critsave[BOOKE_CRITSAVE_SRR0], 475 (uintmax_t)pc->pc_booke.critsave[BOOKE_CRITSAVE_SRR1]); 476 db_show_booke_save("mchksave", pc->pc_booke.mchksave); 477 for (i = 0; i < BOOKE_TLB_MAXNEST && 478 i < (int)pc->pc_booke.tlb_level; i++) { 479 tlbsave = &pc->pc_booke.tlbsave[i * BOOKE_TLB_SAVELEN]; 480 db_printf("tlbsave%d srr0 %#jx srr1 %#jx\n", i, 481 (uintmax_t)tlbsave[TLBSAVE_BOOKE_SRR0], 482 (uintmax_t)tlbsave[TLBSAVE_BOOKE_SRR1]); 483 } 484 } 485 #endif /* DDB */ 486 487 /* Shutdown the CPU as much as possible. */ 488 void 489 cpu_halt(void) 490 { 491 492 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE)); 493 while (1) 494 ; 495 } 496 497 int 498 ptrace_single_step(struct thread *td) 499 { 500 struct trapframe *tf; 501 502 tf = td->td_frame; 503 tf->srr1 |= PSL_DE; 504 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC); 505 return (0); 506 } 507 508 int 509 ptrace_clear_single_step(struct thread *td) 510 { 511 struct trapframe *tf; 512 513 tf = td->td_frame; 514 tf->srr1 &= ~PSL_DE; 515 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC); 516 return (0); 517 } 518 519 void 520 kdb_cpu_clear_singlestep(void) 521 { 522 register_t r; 523 524 r = mfspr(SPR_DBCR0); 525 mtspr(SPR_DBCR0, r & ~DBCR0_IC); 526 kdb_frame->srr1 &= ~PSL_DE; 527 } 528 529 void 530 kdb_cpu_set_singlestep(void) 531 { 532 register_t r; 533 534 r = mfspr(SPR_DBCR0); 535 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM); 536 kdb_frame->srr1 |= PSL_DE; 537 } 538