xref: /linux/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c (revision dea3165f989b259bc1293d9dfc50053223f5f4b2)
1 /*
2  * Broadcom NetXtreme-E RoCE driver.
3  *
4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * BSD license below:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  *
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  * Description: RDMA Controller HW interface
37  */
38 
39 #define dev_fmt(fmt) "QPLIB: " fmt
40 
41 #include <linux/interrupt.h>
42 #include <linux/spinlock.h>
43 #include <linux/pci.h>
44 #include <linux/prefetch.h>
45 #include <linux/delay.h>
46 
47 #include "roce_hsi.h"
48 #include "qplib_res.h"
49 #include "qplib_rcfw.h"
50 #include "qplib_sp.h"
51 #include "qplib_fp.h"
52 #include "qplib_tlv.h"
53 
54 static void bnxt_qplib_service_creq(struct tasklet_struct *t);
55 
56 /**
57  * bnxt_qplib_map_rc  -  map return type based on opcode
58  * @opcode:  roce slow path opcode
59  *
60  * case #1
61  * Firmware initiated error recovery is a safe state machine and
62  * driver can consider all the underlying rdma resources are free.
63  * In this state, it is safe to return success for opcodes related to
64  * destroying rdma resources (like destroy qp, destroy cq etc.).
65  *
66  * case #2
67  * If driver detect potential firmware stall, it is not safe state machine
68  * and the driver can not consider all the underlying rdma resources are
69  * freed.
70  * In this state, it is not safe to return success for opcodes related to
71  * destroying rdma resources (like destroy qp, destroy cq etc.).
72  *
73  * Scope of this helper function is only for case #1.
74  *
75  * Returns:
76  * 0 to communicate success to caller.
77  * Non zero error code to communicate failure to caller.
78  */
bnxt_qplib_map_rc(u8 opcode)79 static int bnxt_qplib_map_rc(u8 opcode)
80 {
81 	switch (opcode) {
82 	case CMDQ_BASE_OPCODE_DESTROY_QP:
83 	case CMDQ_BASE_OPCODE_DESTROY_SRQ:
84 	case CMDQ_BASE_OPCODE_DESTROY_CQ:
85 	case CMDQ_BASE_OPCODE_DEALLOCATE_KEY:
86 	case CMDQ_BASE_OPCODE_DEREGISTER_MR:
87 	case CMDQ_BASE_OPCODE_DELETE_GID:
88 	case CMDQ_BASE_OPCODE_DESTROY_QP1:
89 	case CMDQ_BASE_OPCODE_DESTROY_AH:
90 	case CMDQ_BASE_OPCODE_DEINITIALIZE_FW:
91 	case CMDQ_BASE_OPCODE_MODIFY_ROCE_CC:
92 	case CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE:
93 		return 0;
94 	default:
95 		return -ETIMEDOUT;
96 	}
97 }
98 
99 /**
100  * bnxt_re_is_fw_stalled   -	Check firmware health
101  * @rcfw:     rcfw channel instance of rdev
102  * @cookie:   cookie to track the command
103  *
104  * If firmware has not responded any rcfw command within
105  * rcfw->max_timeout, consider firmware as stalled.
106  *
107  * Returns:
108  * 0 if firmware is responding
109  * -ENODEV if firmware is not responding
110  */
bnxt_re_is_fw_stalled(struct bnxt_qplib_rcfw * rcfw,u16 cookie)111 static int bnxt_re_is_fw_stalled(struct bnxt_qplib_rcfw *rcfw,
112 				 u16 cookie)
113 {
114 	struct bnxt_qplib_cmdq_ctx *cmdq;
115 	struct bnxt_qplib_crsqe *crsqe;
116 
117 	crsqe = &rcfw->crsqe_tbl[cookie];
118 	cmdq = &rcfw->cmdq;
119 
120 	if (time_after(jiffies, cmdq->last_seen +
121 		      (rcfw->max_timeout * HZ))) {
122 		dev_warn_ratelimited(&rcfw->pdev->dev,
123 				     "%s: FW STALL Detected. cmdq[%#x]=%#x waited (%d > %d) msec active %d ",
124 				     __func__, cookie, crsqe->opcode,
125 				     jiffies_to_msecs(jiffies - cmdq->last_seen),
126 				     rcfw->max_timeout * 1000,
127 				     crsqe->is_in_used);
128 		return -ENODEV;
129 	}
130 
131 	return 0;
132 }
133 
134 /**
135  * __wait_for_resp   -	Don't hold the cpu context and wait for response
136  * @rcfw:    rcfw channel instance of rdev
137  * @cookie:  cookie to track the command
138  *
139  * Wait for command completion in sleepable context.
140  *
141  * Returns:
142  * 0 if command is completed by firmware.
143  * Non zero error code for rest of the case.
144  */
__wait_for_resp(struct bnxt_qplib_rcfw * rcfw,u16 cookie)145 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
146 {
147 	struct bnxt_qplib_cmdq_ctx *cmdq;
148 	struct bnxt_qplib_crsqe *crsqe;
149 	int ret;
150 
151 	cmdq = &rcfw->cmdq;
152 	crsqe = &rcfw->crsqe_tbl[cookie];
153 
154 	do {
155 		if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags))
156 			return bnxt_qplib_map_rc(crsqe->opcode);
157 		if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
158 			return -ETIMEDOUT;
159 
160 		wait_event_timeout(cmdq->waitq,
161 				   !crsqe->is_in_used ||
162 				   test_bit(ERR_DEVICE_DETACHED, &cmdq->flags),
163 				   msecs_to_jiffies(rcfw->max_timeout * 1000));
164 
165 		if (!crsqe->is_in_used)
166 			return 0;
167 
168 		bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
169 
170 		if (!crsqe->is_in_used)
171 			return 0;
172 
173 		ret = bnxt_re_is_fw_stalled(rcfw, cookie);
174 		if (ret)
175 			return ret;
176 
177 	} while (true);
178 };
179 
180 /**
181  * __block_for_resp   -	hold the cpu context and wait for response
182  * @rcfw:    rcfw channel instance of rdev
183  * @cookie:  cookie to track the command
184  *
185  * This function will hold the cpu (non-sleepable context) and
186  * wait for command completion. Maximum holding interval is 8 second.
187  *
188  * Returns:
189  * -ETIMEOUT if command is not completed in specific time interval.
190  * 0 if command is completed by firmware.
191  */
__block_for_resp(struct bnxt_qplib_rcfw * rcfw,u16 cookie)192 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
193 {
194 	struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
195 	struct bnxt_qplib_crsqe *crsqe;
196 	unsigned long issue_time = 0;
197 
198 	issue_time = jiffies;
199 	crsqe = &rcfw->crsqe_tbl[cookie];
200 
201 	do {
202 		if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags))
203 			return bnxt_qplib_map_rc(crsqe->opcode);
204 		if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
205 			return -ETIMEDOUT;
206 
207 		udelay(1);
208 
209 		bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
210 		if (!crsqe->is_in_used)
211 			return 0;
212 
213 	} while (time_before(jiffies, issue_time + (8 * HZ)));
214 
215 	return -ETIMEDOUT;
216 };
217 
218 /*  __send_message_no_waiter -	get cookie and post the message.
219  * @rcfw:   rcfw channel instance of rdev
220  * @msg:    qplib message internal
221  *
222  * This function will just post and don't bother about completion.
223  * Current design of this function is -
224  * user must hold the completion queue hwq->lock.
225  * user must have used existing completion and free the resources.
226  * this function will not check queue full condition.
227  * this function will explicitly set is_waiter_alive=false.
228  * current use case is - send destroy_ah if create_ah is return
229  * after waiter of create_ah is lost. It can be extended for other
230  * use case as well.
231  *
232  * Returns: Nothing
233  *
234  */
__send_message_no_waiter(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_cmdqmsg * msg)235 static void __send_message_no_waiter(struct bnxt_qplib_rcfw *rcfw,
236 				     struct bnxt_qplib_cmdqmsg *msg)
237 {
238 	struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
239 	struct bnxt_qplib_hwq *hwq = &cmdq->hwq;
240 	struct bnxt_qplib_crsqe *crsqe;
241 	struct bnxt_qplib_cmdqe *cmdqe;
242 	u32 sw_prod, cmdq_prod;
243 	u16 cookie;
244 	u32 bsize;
245 	u8 *preq;
246 
247 	cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
248 	__set_cmdq_base_cookie(msg->req, msg->req_sz, cpu_to_le16(cookie));
249 	crsqe = &rcfw->crsqe_tbl[cookie];
250 
251 	/* Set cmd_size in terms of 16B slots in req. */
252 	bsize = bnxt_qplib_set_cmd_slots(msg->req);
253 	/* GET_CMD_SIZE would return number of slots in either case of tlv
254 	 * and non-tlv commands after call to bnxt_qplib_set_cmd_slots()
255 	 */
256 	crsqe->is_internal_cmd = true;
257 	crsqe->is_waiter_alive = false;
258 	crsqe->is_in_used = true;
259 	crsqe->req_size = __get_cmdq_base_cmd_size(msg->req, msg->req_sz);
260 
261 	preq = (u8 *)msg->req;
262 	do {
263 		/* Locate the next cmdq slot */
264 		sw_prod = HWQ_CMP(hwq->prod, hwq);
265 		cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL);
266 		/* Copy a segment of the req cmd to the cmdq */
267 		memset(cmdqe, 0, sizeof(*cmdqe));
268 		memcpy(cmdqe, preq, min_t(u32, bsize, sizeof(*cmdqe)));
269 		preq += min_t(u32, bsize, sizeof(*cmdqe));
270 		bsize -= min_t(u32, bsize, sizeof(*cmdqe));
271 		hwq->prod++;
272 	} while (bsize > 0);
273 	cmdq->seq_num++;
274 
275 	cmdq_prod = hwq->prod;
276 	atomic_inc(&rcfw->timeout_send);
277 	/* ring CMDQ DB */
278 	wmb();
279 	writel(cmdq_prod, cmdq->cmdq_mbox.prod);
280 	writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
281 }
282 
__send_message(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_cmdqmsg * msg,u8 opcode)283 static int __send_message(struct bnxt_qplib_rcfw *rcfw,
284 			  struct bnxt_qplib_cmdqmsg *msg, u8 opcode)
285 {
286 	u32 bsize, free_slots, required_slots;
287 	struct bnxt_qplib_cmdq_ctx *cmdq;
288 	struct bnxt_qplib_crsqe *crsqe;
289 	struct bnxt_qplib_cmdqe *cmdqe;
290 	struct bnxt_qplib_hwq *hwq;
291 	u32 sw_prod, cmdq_prod;
292 	struct pci_dev *pdev;
293 	u16 cookie;
294 	u8 *preq;
295 
296 	cmdq = &rcfw->cmdq;
297 	hwq = &cmdq->hwq;
298 	pdev = rcfw->pdev;
299 
300 	/* Cmdq are in 16-byte units, each request can consume 1 or more
301 	 * cmdqe
302 	 */
303 	spin_lock_bh(&hwq->lock);
304 	required_slots = bnxt_qplib_get_cmd_slots(msg->req);
305 	free_slots = HWQ_FREE_SLOTS(hwq);
306 	cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
307 	crsqe = &rcfw->crsqe_tbl[cookie];
308 
309 	if (required_slots >= free_slots) {
310 		dev_info_ratelimited(&pdev->dev,
311 				     "CMDQ is full req/free %d/%d!",
312 				     required_slots, free_slots);
313 		spin_unlock_bh(&hwq->lock);
314 		return -EAGAIN;
315 	}
316 	if (msg->block)
317 		cookie |= RCFW_CMD_IS_BLOCKING;
318 	__set_cmdq_base_cookie(msg->req, msg->req_sz, cpu_to_le16(cookie));
319 
320 	bsize = bnxt_qplib_set_cmd_slots(msg->req);
321 	crsqe->free_slots = free_slots;
322 	crsqe->resp = (struct creq_qp_event *)msg->resp;
323 	crsqe->resp->cookie = cpu_to_le16(cookie);
324 	crsqe->is_internal_cmd = false;
325 	crsqe->is_waiter_alive = true;
326 	crsqe->is_in_used = true;
327 	crsqe->opcode = opcode;
328 
329 	crsqe->req_size = __get_cmdq_base_cmd_size(msg->req, msg->req_sz);
330 	if (__get_cmdq_base_resp_size(msg->req, msg->req_sz) && msg->sb) {
331 		struct bnxt_qplib_rcfw_sbuf *sbuf = msg->sb;
332 
333 		__set_cmdq_base_resp_addr(msg->req, msg->req_sz,
334 					  cpu_to_le64(sbuf->dma_addr));
335 		__set_cmdq_base_resp_size(msg->req, msg->req_sz,
336 					  ALIGN(sbuf->size,
337 						BNXT_QPLIB_CMDQE_UNITS) /
338 						BNXT_QPLIB_CMDQE_UNITS);
339 	}
340 
341 	preq = (u8 *)msg->req;
342 	do {
343 		/* Locate the next cmdq slot */
344 		sw_prod = HWQ_CMP(hwq->prod, hwq);
345 		cmdqe = bnxt_qplib_get_qe(hwq, sw_prod, NULL);
346 		/* Copy a segment of the req cmd to the cmdq */
347 		memset(cmdqe, 0, sizeof(*cmdqe));
348 		memcpy(cmdqe, preq, min_t(u32, bsize, sizeof(*cmdqe)));
349 		preq += min_t(u32, bsize, sizeof(*cmdqe));
350 		bsize -= min_t(u32, bsize, sizeof(*cmdqe));
351 		hwq->prod++;
352 	} while (bsize > 0);
353 	cmdq->seq_num++;
354 
355 	cmdq_prod = hwq->prod & 0xFFFF;
356 	if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) {
357 		/* The very first doorbell write
358 		 * is required to set this flag
359 		 * which prompts the FW to reset
360 		 * its internal pointers
361 		 */
362 		cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG);
363 		clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
364 	}
365 	/* ring CMDQ DB */
366 	wmb();
367 	writel(cmdq_prod, cmdq->cmdq_mbox.prod);
368 	writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
369 	spin_unlock_bh(&hwq->lock);
370 	/* Return the CREQ response pointer */
371 	return 0;
372 }
373 
374 /**
375  * __poll_for_resp   -	self poll completion for rcfw command
376  * @rcfw:     rcfw channel instance of rdev
377  * @cookie:   cookie to track the command
378  *
379  * It works same as __wait_for_resp except this function will
380  * do self polling in sort interval since interrupt is disabled.
381  * This function can not be called from non-sleepable context.
382  *
383  * Returns:
384  * -ETIMEOUT if command is not completed in specific time interval.
385  * 0 if command is completed by firmware.
386  */
__poll_for_resp(struct bnxt_qplib_rcfw * rcfw,u16 cookie)387 static int __poll_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
388 {
389 	struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq;
390 	struct bnxt_qplib_crsqe *crsqe;
391 	unsigned long issue_time;
392 	int ret;
393 
394 	issue_time = jiffies;
395 	crsqe = &rcfw->crsqe_tbl[cookie];
396 
397 	do {
398 		if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags))
399 			return bnxt_qplib_map_rc(crsqe->opcode);
400 		if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
401 			return -ETIMEDOUT;
402 
403 		usleep_range(1000, 1001);
404 
405 		bnxt_qplib_service_creq(&rcfw->creq.creq_tasklet);
406 		if (!crsqe->is_in_used)
407 			return 0;
408 		if (jiffies_to_msecs(jiffies - issue_time) >
409 		    (rcfw->max_timeout * 1000)) {
410 			ret = bnxt_re_is_fw_stalled(rcfw, cookie);
411 			if (ret)
412 				return ret;
413 		}
414 	} while (true);
415 };
416 
__send_message_basic_sanity(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_cmdqmsg * msg,u8 opcode)417 static int __send_message_basic_sanity(struct bnxt_qplib_rcfw *rcfw,
418 				       struct bnxt_qplib_cmdqmsg *msg,
419 				       u8 opcode)
420 {
421 	struct bnxt_qplib_cmdq_ctx *cmdq;
422 
423 	cmdq = &rcfw->cmdq;
424 
425 	/* Prevent posting if f/w is not in a state to process */
426 	if (test_bit(ERR_DEVICE_DETACHED, &rcfw->cmdq.flags))
427 		return -ENXIO;
428 
429 	if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags))
430 		return -ETIMEDOUT;
431 
432 	if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
433 	    opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
434 		dev_err(&rcfw->pdev->dev, "QPLIB: RCFW already initialized!");
435 		return -EINVAL;
436 	}
437 
438 	if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) &&
439 	    (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
440 	     opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW &&
441 	     opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) {
442 		dev_err(&rcfw->pdev->dev,
443 			"QPLIB: RCFW not initialized, reject opcode 0x%x",
444 			opcode);
445 		return -EOPNOTSUPP;
446 	}
447 
448 	return 0;
449 }
450 
451 /* This function will just post and do not bother about completion */
__destroy_timedout_ah(struct bnxt_qplib_rcfw * rcfw,struct creq_create_ah_resp * create_ah_resp)452 static void __destroy_timedout_ah(struct bnxt_qplib_rcfw *rcfw,
453 				  struct creq_create_ah_resp *create_ah_resp)
454 {
455 	struct bnxt_qplib_cmdqmsg msg = {};
456 	struct cmdq_destroy_ah req = {};
457 
458 	bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
459 				 CMDQ_BASE_OPCODE_DESTROY_AH,
460 				 sizeof(req));
461 	req.ah_cid = create_ah_resp->xid;
462 	msg.req = (struct cmdq_base *)&req;
463 	msg.req_sz = sizeof(req);
464 	__send_message_no_waiter(rcfw, &msg);
465 	dev_info_ratelimited(&rcfw->pdev->dev,
466 			     "From %s: ah_cid = %d timeout_send %d\n",
467 			     __func__, req.ah_cid,
468 			     atomic_read(&rcfw->timeout_send));
469 }
470 
471 /**
472  * __bnxt_qplib_rcfw_send_message   -	qplib interface to send
473  * and complete rcfw command.
474  * @rcfw:   rcfw channel instance of rdev
475  * @msg:    qplib message internal
476  *
477  * This function does not account shadow queue depth. It will send
478  * all the command unconditionally as long as send queue is not full.
479  *
480  * Returns:
481  * 0 if command completed by firmware.
482  * Non zero if the command is not completed by firmware.
483  */
__bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_cmdqmsg * msg)484 static int __bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
485 					  struct bnxt_qplib_cmdqmsg *msg)
486 {
487 	struct creq_qp_event *evnt = (struct creq_qp_event *)msg->resp;
488 	struct bnxt_qplib_crsqe *crsqe;
489 	u16 cookie;
490 	int rc;
491 	u8 opcode;
492 
493 	opcode = __get_cmdq_base_opcode(msg->req, msg->req_sz);
494 
495 	rc = __send_message_basic_sanity(rcfw, msg, opcode);
496 	if (rc)
497 		return rc == -ENXIO ? bnxt_qplib_map_rc(opcode) : rc;
498 
499 	rc = __send_message(rcfw, msg, opcode);
500 	if (rc)
501 		return rc;
502 
503 	cookie = le16_to_cpu(__get_cmdq_base_cookie(msg->req, msg->req_sz))
504 				& RCFW_MAX_COOKIE_VALUE;
505 
506 	if (msg->block)
507 		rc = __block_for_resp(rcfw, cookie);
508 	else if (atomic_read(&rcfw->rcfw_intr_enabled))
509 		rc = __wait_for_resp(rcfw, cookie);
510 	else
511 		rc = __poll_for_resp(rcfw, cookie);
512 
513 	if (rc) {
514 		spin_lock_bh(&rcfw->cmdq.hwq.lock);
515 		crsqe = &rcfw->crsqe_tbl[cookie];
516 		crsqe->is_waiter_alive = false;
517 		if (rc == -ENODEV)
518 			set_bit(FIRMWARE_STALL_DETECTED, &rcfw->cmdq.flags);
519 		spin_unlock_bh(&rcfw->cmdq.hwq.lock);
520 		return -ETIMEDOUT;
521 	}
522 
523 	if (evnt->status) {
524 		/* failed with status */
525 		dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n",
526 			cookie, opcode, evnt->status);
527 		rc = -EIO;
528 	}
529 
530 	return rc;
531 }
532 
533 /**
534  * bnxt_qplib_rcfw_send_message   -	qplib interface to send
535  * and complete rcfw command.
536  * @rcfw:   rcfw channel instance of rdev
537  * @msg:    qplib message internal
538  *
539  * Driver interact with Firmware through rcfw channel/slow path in two ways.
540  * a. Blocking rcfw command send. In this path, driver cannot hold
541  * the context for longer period since it is holding cpu until
542  * command is not completed.
543  * b. Non-blocking rcfw command send. In this path, driver can hold the
544  * context for longer period. There may be many pending command waiting
545  * for completion because of non-blocking nature.
546  *
547  * Driver will use shadow queue depth. Current queue depth of 8K
548  * (due to size of rcfw message there can be actual ~4K rcfw outstanding)
549  * is not optimal for rcfw command processing in firmware.
550  *
551  * Restrict at max #RCFW_CMD_NON_BLOCKING_SHADOW_QD Non-Blocking rcfw commands.
552  * Allow all blocking commands until there is no queue full.
553  *
554  * Returns:
555  * 0 if command completed by firmware.
556  * Non zero if the command is not completed by firmware.
557  */
bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_cmdqmsg * msg)558 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
559 				 struct bnxt_qplib_cmdqmsg *msg)
560 {
561 	int ret;
562 
563 	if (!msg->block) {
564 		down(&rcfw->rcfw_inflight);
565 		ret = __bnxt_qplib_rcfw_send_message(rcfw, msg);
566 		up(&rcfw->rcfw_inflight);
567 	} else {
568 		ret = __bnxt_qplib_rcfw_send_message(rcfw, msg);
569 	}
570 
571 	return ret;
572 }
573 
574 /* Completions */
bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw * rcfw,struct creq_func_event * func_event)575 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
576 					 struct creq_func_event *func_event)
577 {
578 	int rc;
579 
580 	switch (func_event->event) {
581 	case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
582 		break;
583 	case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
584 		break;
585 	case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
586 		break;
587 	case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
588 		break;
589 	case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
590 		break;
591 	case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
592 		break;
593 	case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
594 		break;
595 	case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
596 		/* SRQ ctx error, call srq_handler??
597 		 * But there's no SRQ handle!
598 		 */
599 		break;
600 	case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
601 		break;
602 	case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
603 		break;
604 	case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
605 		break;
606 	case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST:
607 		break;
608 	case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED:
609 		break;
610 	default:
611 		return -EINVAL;
612 	}
613 
614 	rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL);
615 	return rc;
616 }
617 
bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw * rcfw,struct creq_qp_event * qp_event,u32 * num_wait)618 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
619 				       struct creq_qp_event *qp_event,
620 				       u32 *num_wait)
621 {
622 	struct creq_qp_error_notification *err_event;
623 	struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq;
624 	struct bnxt_qplib_crsqe *crsqe;
625 	u32 qp_id, tbl_indx, req_size;
626 	struct bnxt_qplib_qp *qp;
627 	u16 cookie, blocked = 0;
628 	bool is_waiter_alive;
629 	struct pci_dev *pdev;
630 	u32 wait_cmds = 0;
631 	int rc = 0;
632 
633 	pdev = rcfw->pdev;
634 	switch (qp_event->event) {
635 	case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
636 		err_event = (struct creq_qp_error_notification *)qp_event;
637 		qp_id = le32_to_cpu(err_event->xid);
638 		spin_lock(&rcfw->tbl_lock);
639 		tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw);
640 		qp = rcfw->qp_tbl[tbl_indx].qp_handle;
641 		if (!qp) {
642 			spin_unlock(&rcfw->tbl_lock);
643 			break;
644 		}
645 		bnxt_qplib_mark_qp_error(qp);
646 		rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp);
647 		spin_unlock(&rcfw->tbl_lock);
648 		dev_dbg(&pdev->dev, "Received QP error notification\n");
649 		dev_dbg(&pdev->dev,
650 			"qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
651 			qp_id, err_event->req_err_state_reason,
652 			err_event->res_err_state_reason);
653 		break;
654 	default:
655 		/*
656 		 * Command Response
657 		 * cmdq->lock needs to be acquired to synchronie
658 		 * the command send and completion reaping. This function
659 		 * is always called with creq->lock held. Using
660 		 * the nested variant of spin_lock.
661 		 *
662 		 */
663 
664 		spin_lock_nested(&hwq->lock, SINGLE_DEPTH_NESTING);
665 		cookie = le16_to_cpu(qp_event->cookie);
666 		blocked = cookie & RCFW_CMD_IS_BLOCKING;
667 		cookie &= RCFW_MAX_COOKIE_VALUE;
668 		crsqe = &rcfw->crsqe_tbl[cookie];
669 
670 		if (WARN_ONCE(test_bit(FIRMWARE_STALL_DETECTED,
671 				       &rcfw->cmdq.flags),
672 		    "QPLIB: Unreponsive rcfw channel detected.!!")) {
673 			dev_info(&pdev->dev,
674 				 "rcfw timedout: cookie = %#x, free_slots = %d",
675 				 cookie, crsqe->free_slots);
676 			spin_unlock(&hwq->lock);
677 			return rc;
678 		}
679 
680 		if (crsqe->is_internal_cmd && !qp_event->status)
681 			atomic_dec(&rcfw->timeout_send);
682 
683 		if (crsqe->is_waiter_alive) {
684 			if (crsqe->resp) {
685 				memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
686 				/* Insert write memory barrier to ensure that
687 				 * response data is copied before clearing the
688 				 * flags
689 				 */
690 				smp_wmb();
691 			}
692 			if (!blocked)
693 				wait_cmds++;
694 		}
695 
696 		req_size = crsqe->req_size;
697 		is_waiter_alive = crsqe->is_waiter_alive;
698 
699 		crsqe->req_size = 0;
700 		if (!is_waiter_alive)
701 			crsqe->resp = NULL;
702 
703 		crsqe->is_in_used = false;
704 
705 		hwq->cons += req_size;
706 
707 		/* This is a case to handle below scenario -
708 		 * Create AH is completed successfully by firmware,
709 		 * but completion took more time and driver already lost
710 		 * the context of create_ah from caller.
711 		 * We have already return failure for create_ah verbs,
712 		 * so let's destroy the same address vector since it is
713 		 * no more used in stack. We don't care about completion
714 		 * in __send_message_no_waiter.
715 		 * If destroy_ah is failued by firmware, there will be AH
716 		 * resource leak and relatively not critical +  unlikely
717 		 * scenario. Current design is not to handle such case.
718 		 */
719 		if (!is_waiter_alive && !qp_event->status &&
720 		    qp_event->event == CREQ_QP_EVENT_EVENT_CREATE_AH)
721 			__destroy_timedout_ah(rcfw,
722 					      (struct creq_create_ah_resp *)
723 					      qp_event);
724 		spin_unlock(&hwq->lock);
725 	}
726 	*num_wait += wait_cmds;
727 	return rc;
728 }
729 
730 /* SP - CREQ Completion handlers */
bnxt_qplib_service_creq(struct tasklet_struct * t)731 static void bnxt_qplib_service_creq(struct tasklet_struct *t)
732 {
733 	struct bnxt_qplib_rcfw *rcfw = from_tasklet(rcfw, t, creq.creq_tasklet);
734 	struct bnxt_qplib_creq_ctx *creq = &rcfw->creq;
735 	u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
736 	struct bnxt_qplib_hwq *hwq = &creq->hwq;
737 	struct creq_base *creqe;
738 	u32 num_wakeup = 0;
739 	u32 hw_polled = 0;
740 
741 	/* Service the CREQ until budget is over */
742 	spin_lock_bh(&hwq->lock);
743 	while (budget > 0) {
744 		creqe = bnxt_qplib_get_qe(hwq, hwq->cons, NULL);
745 		if (!CREQ_CMP_VALID(creqe, creq->creq_db.dbinfo.flags))
746 			break;
747 		/* The valid test of the entry must be done first before
748 		 * reading any further.
749 		 */
750 		dma_rmb();
751 		rcfw->cmdq.last_seen = jiffies;
752 
753 		type = creqe->type & CREQ_BASE_TYPE_MASK;
754 		switch (type) {
755 		case CREQ_BASE_TYPE_QP_EVENT:
756 			bnxt_qplib_process_qp_event
757 				(rcfw, (struct creq_qp_event *)creqe,
758 				 &num_wakeup);
759 			creq->stats.creq_qp_event_processed++;
760 			break;
761 		case CREQ_BASE_TYPE_FUNC_EVENT:
762 			if (!bnxt_qplib_process_func_event
763 			    (rcfw, (struct creq_func_event *)creqe))
764 				creq->stats.creq_func_event_processed++;
765 			else
766 				dev_warn(&rcfw->pdev->dev,
767 					 "aeqe:%#x Not handled\n", type);
768 			break;
769 		default:
770 			if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT)
771 				dev_warn(&rcfw->pdev->dev,
772 					 "creqe with event 0x%x not handled\n",
773 					 type);
774 			break;
775 		}
776 		budget--;
777 		hw_polled++;
778 		bnxt_qplib_hwq_incr_cons(hwq->max_elements, &hwq->cons,
779 					 1, &creq->creq_db.dbinfo.flags);
780 	}
781 
782 	if (hw_polled)
783 		bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo,
784 				      rcfw->res->cctx, true);
785 	spin_unlock_bh(&hwq->lock);
786 	if (num_wakeup)
787 		wake_up_nr(&rcfw->cmdq.waitq, num_wakeup);
788 }
789 
bnxt_qplib_creq_irq(int irq,void * dev_instance)790 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance)
791 {
792 	struct bnxt_qplib_rcfw *rcfw = dev_instance;
793 	struct bnxt_qplib_creq_ctx *creq;
794 	struct bnxt_qplib_hwq *hwq;
795 	u32 sw_cons;
796 
797 	creq = &rcfw->creq;
798 	hwq = &creq->hwq;
799 	/* Prefetch the CREQ element */
800 	sw_cons = HWQ_CMP(hwq->cons, hwq);
801 	prefetch(bnxt_qplib_get_qe(hwq, sw_cons, NULL));
802 
803 	tasklet_schedule(&creq->creq_tasklet);
804 
805 	return IRQ_HANDLED;
806 }
807 
808 /* RCFW */
bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw * rcfw)809 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)
810 {
811 	struct creq_deinitialize_fw_resp resp = {};
812 	struct cmdq_deinitialize_fw req = {};
813 	struct bnxt_qplib_cmdqmsg msg = {};
814 	int rc;
815 
816 	bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
817 				 CMDQ_BASE_OPCODE_DEINITIALIZE_FW,
818 				 sizeof(req));
819 	bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL,
820 				sizeof(req), sizeof(resp), 0);
821 	rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
822 	if (rc)
823 		return rc;
824 
825 	clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
826 	return 0;
827 }
828 
bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_ctx * ctx,int is_virtfn)829 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
830 			 struct bnxt_qplib_ctx *ctx, int is_virtfn)
831 {
832 	struct creq_initialize_fw_resp resp = {};
833 	struct cmdq_initialize_fw req = {};
834 	struct bnxt_qplib_cmdqmsg msg = {};
835 	u16 flags = 0;
836 	u8 pgsz, lvl;
837 	int rc;
838 
839 	bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
840 				 CMDQ_BASE_OPCODE_INITIALIZE_FW,
841 				 sizeof(req));
842 	/* Supply (log-base-2-of-host-page-size - base-page-shift)
843 	 * to bono to adjust the doorbell page sizes.
844 	 */
845 	req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
846 					   RCFW_DBR_BASE_PAGE_SHIFT);
847 	/*
848 	 * Gen P5 devices doesn't require this allocation
849 	 * as the L2 driver does the same for RoCE also.
850 	 * Also, VFs need not setup the HW context area, PF
851 	 * shall setup this area for VF. Skipping the
852 	 * HW programming
853 	 */
854 	if (is_virtfn || bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx))
855 		goto skip_ctx_setup;
856 
857 	lvl = ctx->qpc_tbl.level;
858 	pgsz = bnxt_qplib_base_pg_size(&ctx->qpc_tbl);
859 	req.qpc_pg_size_qpc_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
860 				   lvl;
861 	lvl = ctx->mrw_tbl.level;
862 	pgsz = bnxt_qplib_base_pg_size(&ctx->mrw_tbl);
863 	req.mrw_pg_size_mrw_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
864 				   lvl;
865 	lvl = ctx->srqc_tbl.level;
866 	pgsz = bnxt_qplib_base_pg_size(&ctx->srqc_tbl);
867 	req.srq_pg_size_srq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
868 				   lvl;
869 	lvl = ctx->cq_tbl.level;
870 	pgsz = bnxt_qplib_base_pg_size(&ctx->cq_tbl);
871 	req.cq_pg_size_cq_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
872 				 lvl;
873 	lvl = ctx->tim_tbl.level;
874 	pgsz = bnxt_qplib_base_pg_size(&ctx->tim_tbl);
875 	req.tim_pg_size_tim_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
876 				   lvl;
877 	lvl = ctx->tqm_ctx.pde.level;
878 	pgsz = bnxt_qplib_base_pg_size(&ctx->tqm_ctx.pde);
879 	req.tqm_pg_size_tqm_lvl = (pgsz << CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT) |
880 				   lvl;
881 	req.qpc_page_dir =
882 		cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
883 	req.mrw_page_dir =
884 		cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
885 	req.srq_page_dir =
886 		cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
887 	req.cq_page_dir =
888 		cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
889 	req.tim_page_dir =
890 		cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
891 	req.tqm_page_dir =
892 		cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]);
893 
894 	req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements);
895 	req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements);
896 	req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements);
897 	req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements);
898 
899 skip_ctx_setup:
900 	if (BNXT_RE_HW_RETX(rcfw->res->dattr->dev_cap_flags))
901 		flags |= CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED;
902 	if (_is_optimize_modify_qp_supported(rcfw->res->dattr->dev_cap_flags2))
903 		flags |= CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED;
904 	if (rcfw->res->en_dev->flags & BNXT_EN_FLAG_ROCE_VF_RES_MGMT)
905 		flags |= CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT;
906 	req.flags |= cpu_to_le16(flags);
907 	req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
908 	bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
909 	rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
910 	if (rc)
911 		return rc;
912 	set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags);
913 	return 0;
914 }
915 
bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw * rcfw)916 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
917 {
918 	kfree(rcfw->qp_tbl);
919 	kfree(rcfw->crsqe_tbl);
920 	bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq);
921 	bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq);
922 	rcfw->pdev = NULL;
923 }
924 
bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res * res,struct bnxt_qplib_rcfw * rcfw,struct bnxt_qplib_ctx * ctx,int qp_tbl_sz)925 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res,
926 				  struct bnxt_qplib_rcfw *rcfw,
927 				  struct bnxt_qplib_ctx *ctx,
928 				  int qp_tbl_sz)
929 {
930 	struct bnxt_qplib_hwq_attr hwq_attr = {};
931 	struct bnxt_qplib_sg_info sginfo = {};
932 	struct bnxt_qplib_cmdq_ctx *cmdq;
933 	struct bnxt_qplib_creq_ctx *creq;
934 
935 	rcfw->pdev = res->pdev;
936 	cmdq = &rcfw->cmdq;
937 	creq = &rcfw->creq;
938 	rcfw->res = res;
939 
940 	sginfo.pgsize = PAGE_SIZE;
941 	sginfo.pgshft = PAGE_SHIFT;
942 
943 	hwq_attr.sginfo = &sginfo;
944 	hwq_attr.res = rcfw->res;
945 	hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT;
946 	hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS;
947 	hwq_attr.type = bnxt_qplib_get_hwq_type(res);
948 
949 	if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) {
950 		dev_err(&rcfw->pdev->dev,
951 			"HW channel CREQ allocation failed\n");
952 		goto fail;
953 	}
954 
955 	rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT;
956 
957 	sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth);
958 	hwq_attr.depth = rcfw->cmdq_depth & 0x7FFFFFFF;
959 	hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS;
960 	hwq_attr.type = HWQ_TYPE_CTX;
961 	if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) {
962 		dev_err(&rcfw->pdev->dev,
963 			"HW channel CMDQ allocation failed\n");
964 		goto fail;
965 	}
966 
967 	rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements,
968 				  sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
969 	if (!rcfw->crsqe_tbl)
970 		goto fail;
971 
972 	/* Allocate one extra to hold the QP1 entries */
973 	rcfw->qp_tbl_size = qp_tbl_sz + 1;
974 	rcfw->qp_tbl = kcalloc(rcfw->qp_tbl_size, sizeof(struct bnxt_qplib_qp_node),
975 			       GFP_KERNEL);
976 	if (!rcfw->qp_tbl)
977 		goto fail;
978 	spin_lock_init(&rcfw->tbl_lock);
979 
980 	rcfw->max_timeout = res->cctx->hwrm_cmd_max_timeout;
981 
982 	return 0;
983 
984 fail:
985 	bnxt_qplib_free_rcfw_channel(rcfw);
986 	return -ENOMEM;
987 }
988 
bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw * rcfw,bool kill)989 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill)
990 {
991 	struct bnxt_qplib_creq_ctx *creq;
992 
993 	creq = &rcfw->creq;
994 
995 	if (!creq->requested)
996 		return;
997 
998 	creq->requested = false;
999 	/* Mask h/w interrupts */
1000 	bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false);
1001 	/* Sync with last running IRQ-handler */
1002 	synchronize_irq(creq->msix_vec);
1003 	free_irq(creq->msix_vec, rcfw);
1004 	kfree(creq->irq_name);
1005 	creq->irq_name = NULL;
1006 	atomic_set(&rcfw->rcfw_intr_enabled, 0);
1007 	if (kill)
1008 		tasklet_kill(&creq->creq_tasklet);
1009 	tasklet_disable(&creq->creq_tasklet);
1010 }
1011 
bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw * rcfw)1012 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
1013 {
1014 	struct bnxt_qplib_creq_ctx *creq;
1015 	struct bnxt_qplib_cmdq_ctx *cmdq;
1016 
1017 	creq = &rcfw->creq;
1018 	cmdq = &rcfw->cmdq;
1019 	/* Make sure the HW channel is stopped! */
1020 	bnxt_qplib_rcfw_stop_irq(rcfw, true);
1021 
1022 	iounmap(cmdq->cmdq_mbox.reg.bar_reg);
1023 	iounmap(creq->creq_db.reg.bar_reg);
1024 
1025 	cmdq->cmdq_mbox.reg.bar_reg = NULL;
1026 	creq->creq_db.reg.bar_reg = NULL;
1027 	creq->aeq_handler = NULL;
1028 	creq->msix_vec = 0;
1029 }
1030 
bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw * rcfw,int msix_vector,bool need_init)1031 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
1032 			      bool need_init)
1033 {
1034 	struct bnxt_qplib_creq_ctx *creq;
1035 	struct bnxt_qplib_res *res;
1036 	int rc;
1037 
1038 	creq = &rcfw->creq;
1039 	res = rcfw->res;
1040 
1041 	if (creq->requested)
1042 		return -EFAULT;
1043 
1044 	creq->msix_vec = msix_vector;
1045 	if (need_init)
1046 		tasklet_setup(&creq->creq_tasklet, bnxt_qplib_service_creq);
1047 	else
1048 		tasklet_enable(&creq->creq_tasklet);
1049 
1050 	creq->irq_name = kasprintf(GFP_KERNEL, "bnxt_re-creq@pci:%s",
1051 				   pci_name(res->pdev));
1052 	if (!creq->irq_name)
1053 		return -ENOMEM;
1054 	rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0,
1055 			 creq->irq_name, rcfw);
1056 	if (rc) {
1057 		kfree(creq->irq_name);
1058 		creq->irq_name = NULL;
1059 		tasklet_disable(&creq->creq_tasklet);
1060 		return rc;
1061 	}
1062 	creq->requested = true;
1063 
1064 	bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, res->cctx, true);
1065 	atomic_inc(&rcfw->rcfw_intr_enabled);
1066 
1067 	return 0;
1068 }
1069 
bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw * rcfw)1070 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw)
1071 {
1072 	struct bnxt_qplib_cmdq_mbox *mbox;
1073 	resource_size_t bar_reg;
1074 	struct pci_dev *pdev;
1075 
1076 	pdev = rcfw->pdev;
1077 	mbox = &rcfw->cmdq.cmdq_mbox;
1078 
1079 	mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION;
1080 	mbox->reg.len = RCFW_COMM_SIZE;
1081 	mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id);
1082 	if (!mbox->reg.bar_base) {
1083 		dev_err(&pdev->dev,
1084 			"QPLIB: CMDQ BAR region %d resc start is 0!\n",
1085 			mbox->reg.bar_id);
1086 		return -ENOMEM;
1087 	}
1088 
1089 	bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET;
1090 	mbox->reg.len = RCFW_COMM_SIZE;
1091 	mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len);
1092 	if (!mbox->reg.bar_reg) {
1093 		dev_err(&pdev->dev,
1094 			"QPLIB: CMDQ BAR region %d mapping failed\n",
1095 			mbox->reg.bar_id);
1096 		return -ENOMEM;
1097 	}
1098 
1099 	mbox->prod = (void  __iomem *)(mbox->reg.bar_reg +
1100 			RCFW_PF_VF_COMM_PROD_OFFSET);
1101 	mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET);
1102 	return 0;
1103 }
1104 
bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw * rcfw,u32 reg_offt)1105 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt)
1106 {
1107 	struct bnxt_qplib_creq_db *creq_db;
1108 	resource_size_t bar_reg;
1109 	struct pci_dev *pdev;
1110 
1111 	pdev = rcfw->pdev;
1112 	creq_db = &rcfw->creq.creq_db;
1113 
1114 	creq_db->dbinfo.flags = 0;
1115 	creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION;
1116 	creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id);
1117 	if (!creq_db->reg.bar_id)
1118 		dev_err(&pdev->dev,
1119 			"QPLIB: CREQ BAR region %d resc start is 0!",
1120 			creq_db->reg.bar_id);
1121 
1122 	bar_reg = creq_db->reg.bar_base + reg_offt;
1123 	/* Unconditionally map 8 bytes to support 57500 series */
1124 	creq_db->reg.len = 8;
1125 	creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len);
1126 	if (!creq_db->reg.bar_reg) {
1127 		dev_err(&pdev->dev,
1128 			"QPLIB: CREQ BAR region %d mapping failed",
1129 			creq_db->reg.bar_id);
1130 		return -ENOMEM;
1131 	}
1132 	creq_db->dbinfo.db = creq_db->reg.bar_reg;
1133 	creq_db->dbinfo.hwq = &rcfw->creq.hwq;
1134 	creq_db->dbinfo.xid = rcfw->creq.ring_id;
1135 	return 0;
1136 }
1137 
bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw * rcfw)1138 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw)
1139 {
1140 	struct bnxt_qplib_cmdq_ctx *cmdq;
1141 	struct bnxt_qplib_creq_ctx *creq;
1142 	struct bnxt_qplib_cmdq_mbox *mbox;
1143 	struct cmdq_init init = {0};
1144 
1145 	cmdq = &rcfw->cmdq;
1146 	creq = &rcfw->creq;
1147 	mbox = &cmdq->cmdq_mbox;
1148 
1149 	init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
1150 	init.cmdq_size_cmdq_lvl =
1151 			cpu_to_le16(((rcfw->cmdq_depth <<
1152 				      CMDQ_INIT_CMDQ_SIZE_SFT) &
1153 				    CMDQ_INIT_CMDQ_SIZE_MASK) |
1154 				    ((cmdq->hwq.level <<
1155 				      CMDQ_INIT_CMDQ_LVL_SFT) &
1156 				    CMDQ_INIT_CMDQ_LVL_MASK));
1157 	init.creq_ring_id = cpu_to_le16(creq->ring_id);
1158 	/* Write to the Bono mailbox register */
1159 	__iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4);
1160 }
1161 
bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw * rcfw,int msix_vector,int cp_bar_reg_off,aeq_handler_t aeq_handler)1162 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw,
1163 				   int msix_vector,
1164 				   int cp_bar_reg_off,
1165 				   aeq_handler_t aeq_handler)
1166 {
1167 	struct bnxt_qplib_cmdq_ctx *cmdq;
1168 	struct bnxt_qplib_creq_ctx *creq;
1169 	int rc;
1170 
1171 	cmdq = &rcfw->cmdq;
1172 	creq = &rcfw->creq;
1173 
1174 	/* Clear to defaults */
1175 
1176 	cmdq->seq_num = 0;
1177 	set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags);
1178 	init_waitqueue_head(&cmdq->waitq);
1179 
1180 	creq->stats.creq_qp_event_processed = 0;
1181 	creq->stats.creq_func_event_processed = 0;
1182 	creq->aeq_handler = aeq_handler;
1183 
1184 	rc = bnxt_qplib_map_cmdq_mbox(rcfw);
1185 	if (rc)
1186 		return rc;
1187 
1188 	rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off);
1189 	if (rc)
1190 		return rc;
1191 
1192 	rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true);
1193 	if (rc) {
1194 		dev_err(&rcfw->pdev->dev,
1195 			"Failed to request IRQ for CREQ rc = 0x%x\n", rc);
1196 		bnxt_qplib_disable_rcfw_channel(rcfw);
1197 		return rc;
1198 	}
1199 
1200 	sema_init(&rcfw->rcfw_inflight, RCFW_CMD_NON_BLOCKING_SHADOW_QD);
1201 	bnxt_qplib_start_rcfw(rcfw);
1202 
1203 	return 0;
1204 }
1205