1 /* 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008 Atheros Communications Inc. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #ifndef _ARN_CORE_H 23 #define _ARN_CORE_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #include <sys/note.h> 30 #include <sys/list.h> 31 #include <sys/net80211.h> 32 33 #include "arn_ath9k.h" 34 #include "arn_rc.h" 35 36 struct ath_node; 37 38 /* 39 * Node type of wifi device 40 */ 41 #ifndef DDI_NT_NET_WIFI 42 #define DDI_NT_NET_WIFI "ddi_network:wifi" 43 #endif 44 #define ARN_NODENAME "arn" 45 46 #define ARN_LOCK(_sc) mutex_enter(&(_sc)->sc_genlock) 47 #define ARN_UNLOCK(_sc) mutex_exit(&(_sc)->sc_genlock) 48 #define ARN_LOCK_ASSERT(_sc) ASSERT(mutex_owned(&(_sc)->sc_genlock)) 49 50 #define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0])) 51 52 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 53 54 #define ARN_MIN(a, b) ((a) < (b) ? (a) : (b)) 55 #define ARN_MAX(a, b) ((a) > (b) ? (a) : (b)) 56 57 #define abs(x) ((x) >= 0 ? (x) : -(x)) 58 59 enum ath9k_key_len { 60 ATH9K_LEN_WEP40 = 5, 61 ATH9K_LEN_WEP104 = 13, 62 }; 63 64 /* 65 * Sync a DMA area described by a dma_area_t 66 */ 67 #define ARN_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 68 (area).offset, (area).alength, (flag))) 69 70 #define list_empty(a) ((a)->list_head.list_next == &(a)->list_head) 71 #define list_d2l(a, obj) ((list_node_t *)(((char *)obj) + (a)->list_offset)) 72 #define list_object(a, node) ((void *)(((char *)node) - (a)->list_offset)) 73 #define list_entry(ptr, type, member) \ 74 ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member))) 75 #define list_is_last(node, list) \ 76 ((node)->list_next == &(list)->list_head) 77 78 #define list_for_each_entry_safe(object, temp, list_t) \ 79 for (object = list_head(list_t), \ 80 temp = list_object((list_t), ((list_d2l(list_t, object))->list_next));\ 81 ((list_d2l(list_t, temp))->list_next) != &((list_t)->list_head);\ 82 object = temp, \ 83 temp = list_object((list_t), (list_d2l(list_t, temp))->list_next)) 84 85 /* 86 * Insert src list after dst list. reinitialize src list thereafter. 87 */ 88 static __inline__ void 89 /* LINTED E_STATIC_UNUSED */ 90 list_splice_tail_init(list_t *dst, list_t *src) 91 { 92 list_node_t *dstnode = &dst->list_head; 93 list_node_t *srcnode = &src->list_head; 94 95 ASSERT(dst->list_size == src->list_size); 96 ASSERT(dst->list_offset == src->list_offset); 97 98 if (list_empty(src)) 99 return; 100 101 dstnode->list_prev->list_next = srcnode->list_next; 102 srcnode->list_next->list_prev = dstnode->list_prev; 103 dstnode->list_prev = srcnode->list_prev; 104 srcnode->list_prev->list_next = dstnode; 105 106 /* reinitialize src list */ 107 srcnode->list_next = srcnode->list_prev = srcnode; 108 } 109 110 #define ARN_LE_READ_16(p) \ 111 ((uint16_t) \ 112 ((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] << 8))) 113 114 #define ARN_LE_READ_32(p) \ 115 ((uint32_t) \ 116 ((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] << 8) | \ 117 (((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24))) 118 119 #define swab16(value) \ 120 ((((value) & 0xff) << 8) | ((value) >> 8)) 121 122 #define swab32(value) \ 123 (((uint32_t)swab16((uint16_t)((value) & 0xffff)) << 16) | \ 124 (uint32_t)swab16((uint16_t)((value) >> 16))) 125 126 #define swab64(value) \ 127 (((uint64_t)swab32((uint32_t)((value) & 0xffffffff)) \ 128 << 32) | \ 129 (uint64_t)swab32((uint32_t)((value) >> 32))) 130 131 /* Bit map related macros. */ 132 #define set_bit(i, a) ((a)[(i)/NBBY] |= (1 << ((i)%NBBY))) 133 #define clr_bit(i, a) ((a)[(i)/NBBY] &= ~(1 << ((i)%NBBY))) 134 #define is_set(i, a) ((a)[(i)/NBBY] & (1 << ((i)%NBBY))) 135 #define is_clr(i, a) (!((a)[(i)/NBBY] & (1 << ((i)%NBBY)))) 136 137 /* Macro to expand scalars to 64-bit objects */ 138 139 #define ito64(x) (sizeof (x) == 8) ? \ 140 (((unsigned long long int)(x)) & (0xff)) : \ 141 (sizeof (x) == 16) ? \ 142 (((unsigned long long int)(x)) & 0xffff) : \ 143 ((sizeof (x) == 32) ? \ 144 (((unsigned long long int)(x)) & 0xffffffff) : \ 145 (unsigned long long int)(x)) 146 147 /* increment with wrap-around */ 148 #define INCR(_l, _sz) do { \ 149 (_l)++; \ 150 (_l) &= ((_sz) - 1); \ 151 } while (0) 152 153 /* decrement with wrap-around */ 154 #define DECR(_l, _sz) do { \ 155 (_l)--; \ 156 (_l) &= ((_sz) - 1); \ 157 } while (0) 158 159 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 160 161 #define TSF_TO_TU(_h, _l) \ 162 ((((uint32_t)(_h)) << 22) | (((uint32_t)(_l)) >> 10)) 163 164 #define ARN_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 165 166 #define IEEE80211_IS_CHAN_HTA(_c) \ 167 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 168 ((_c)->ich_flags & IEEE80211_CHAN_HT)) 169 170 #define IEEE80211_IS_CHAN_HTG(_c) \ 171 (IEEE80211_IS_CHAN_2GHZ(_c) && \ 172 ((_c)->ich_flags & IEEE80211_CHAN_HT)) 173 174 #define IEEE80211_IS_DATA(_wh) \ 175 (((_wh)->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == \ 176 IEEE80211_FC0_TYPE_DATA) 177 178 #define IEEE80211_IS_DATA_QOS(_wh) \ 179 (((_wh)->i_fc[0] & (IEEE80211_FC0_TYPE_MASK | \ 180 IEEE80211_FC0_SUBTYPE_QOS)) == \ 181 (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) 182 183 #define IEEE80211_IS_MGMT(_wh) \ 184 (((_wh)->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == \ 185 IEEE80211_FC0_TYPE_MGT) 186 187 #define IEEE80211_IS_CTL(_wh) \ 188 (((_wh)->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == \ 189 IEEE80211_FC0_TYPE_CTL) 190 191 #define IEEE80211_IS_PSPOLL(_wh) \ 192 (((_wh)->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == \ 193 IEEE80211_FC0_SUBTYPE_PS_POLL) 194 195 #define IEEE80211_IS_BACK_REQ(_wh) \ 196 (((_wh)->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == \ 197 IEEE80211_FC0_SUBTYPE_BAR) 198 199 #define IEEE80211_HAS_MOREFRAGS(_wh) \ 200 (((_wh)->i_fc[1] & IEEE80211_FC1_MORE_FRAG) == \ 201 IEEE80211_FC1_MORE_FRAG) 202 203 /* Debugging */ 204 enum ARN_DEBUG { 205 ARN_DBG_HW = 0x00000001, 206 ARN_DBG_REG_IO = 0x00000002, 207 ARN_DBG_QUEUE = 0x00000004, 208 ARN_DBG_EEPROM = 0x00000008, 209 ARN_DBG_XMIT = 0x00000010, 210 ARN_DBG_RECV = 0x00000020, 211 ARN_DBG_CALIBRATE = 0x00000040, 212 ARN_DBG_CHANNEL = 0x00000080, 213 ARN_DBG_INTERRUPT = 0x00000100, 214 ARN_DBG_REGULATORY = 0x00000200, 215 ARN_DBG_ANI = 0x00000400, 216 ARN_DBG_POWER_MGMT = 0x00000800, 217 ARN_DBG_KEYCACHE = 0x00001000, 218 ARN_DBG_BEACON = 0x00002000, 219 ARN_DBG_RATE = 0x00004000, 220 ARN_DBG_INIT = 0x00008000, 221 ARN_DBG_ATTACH = 0x00010000, 222 ARN_DBG_DEATCH = 0x00020000, 223 ARN_DBG_AGGR = 0x00040000, 224 ARN_DBG_RESET = 0x00080000, 225 ARN_DBG_FATAL = 0x00100000, 226 ARN_DBG_ANY = 0x00200000, 227 ARN_DBG_ALL = 0x00FFFFFF, 228 }; 229 230 /* Debug and log functions */ 231 void arn_dbg(uint32_t dbg_flags, const int8_t *fmt, ...); /* debug function */ 232 void arn_log(const int8_t *fmt, ...); /* event log function */ 233 void arn_problem(const int8_t *fmt, ...); /* run-time problem function */ 234 235 #ifdef DEBUG 236 #define ARN_DDB(command) do { \ 237 { command; } \ 238 _NOTE(CONSTANTCONDITION)\ 239 } while (0) 240 #else 241 #define ARN_DDB(command) 242 #endif /* DEBUG */ 243 244 #define ARN_DBG(args) ARN_DDB(arn_dbg args) 245 246 struct ath_stats { 247 uint32_t ast_hardware; /* fatal hardware error interrupts */ 248 uint32_t ast_rxorn; /* rx overrun interrupts */ 249 uint32_t ast_rxeol; /* rx eol interrupts */ 250 uint32_t ast_txurn; /* tx underrun interrupts */ 251 uint32_t ast_tx_mgmt; /* management frames transmitted */ 252 uint32_t ast_tx_discard; /* frames discarded prior to assoc */ 253 uint32_t ast_tx_invalid; /* frames discarded 'cuz device gone */ 254 uint32_t ast_tx_qstop; /* tx queue stopped 'cuz full */ 255 uint32_t ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */ 256 uint32_t ast_tx_nobufmgt; /* tx failed 'cuz no tx buffer(mgmt) */ 257 uint32_t ast_tx_xretries; /* tx failed 'cuz too many retries */ 258 uint32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 259 uint32_t ast_tx_filtered; /* tx failed 'cuz xmit filtered */ 260 uint32_t ast_tx_shortretry; /* tx on-chip retries (short) */ 261 uint32_t ast_tx_longretry; /* tx on-chip retries (long) */ 262 uint32_t ast_tx_noack; /* tx frames with no ack marked */ 263 uint32_t ast_tx_rts; /* tx frames with rts enabled */ 264 uint32_t ast_tx_shortpre; /* tx frames with short preamble */ 265 uint32_t ast_tx_altrate; /* tx frames with alternate rate */ 266 uint32_t ast_tx_protect; /* tx frames with protection */ 267 int16_t ast_tx_rssi; /* tx rssi of last ack */ 268 int16_t ast_tx_rssidelta; /* tx rssi delta */ 269 uint32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 270 uint32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 271 uint32_t ast_rx_badcrypt; /* rx failed 'cuz decryption */ 272 uint32_t ast_rx_phyerr; /* rx PHY error summary count */ 273 uint32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ 274 uint32_t ast_rx_tooshort; /* rx discarded 'cuz frame too short */ 275 uint32_t ast_per_cal; /* periodic calibration calls */ 276 uint32_t ast_per_calfail; /* periodic calibration failed */ 277 uint32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 278 uint32_t ast_rate_calls; /* rate control checks */ 279 uint32_t ast_rate_raise; /* rate control raised xmit rate */ 280 uint32_t ast_rate_drop; /* rate control dropped xmit rate */ 281 }; 282 283 struct dma_area { 284 ddi_acc_handle_t acc_hdl; /* handle for memory */ 285 caddr_t mem_va; /* CPU VA of memory */ 286 uint32_t nslots; /* number of slots */ 287 uint32_t size; /* size per slot */ 288 size_t alength; /* allocated size */ 289 /* >= product of above */ 290 291 ddi_dma_handle_t dma_hdl; /* DMA handle */ 292 offset_t offset; /* relative to handle */ 293 ddi_dma_cookie_t cookie; /* associated cookie */ 294 uint32_t ncookies; /* must be 1 */ 295 uint32_t token; /* arbitrary identifier */ 296 }; 297 typedef struct dma_area dma_area_t; 298 299 /* Load-time Configuration */ 300 301 /* 302 * Per-instance load-time (note: NOT run-time) 303 * configurations for Atheros Device 304 */ 305 struct ath_config { 306 uint32_t ath_aggr_prot; 307 uint16_t txpowlimit; 308 uint16_t txpowlimit_override; 309 uint8_t cabqReadytime; /* Cabq Readytime % */ 310 uint8_t swBeaconProcess; /* Process received beacons in SW (vs HW) */ 311 }; 312 313 /* Descriptor Management */ 314 315 #define ATH_TXBUF_RESET(_bf) do { \ 316 (_bf)->bf_status = 0; \ 317 (_bf)->bf_lastbf = NULL; \ 318 (_bf)->bf_lastfrm = NULL; \ 319 (_bf)->bf_next = NULL; \ 320 (void) memset(&((_bf)->bf_state), 0, \ 321 sizeof (struct ath_buf_state)); \ 322 (void) memset(&((_bf)->tx_info_priv), 0, \ 323 sizeof (struct ath_tx_info_priv)); \ 324 _NOTE(CONSTCOND) \ 325 } while (0) 326 327 enum buffer_type { 328 BUF_DATA = BIT(0), 329 BUF_AGGR = BIT(1), 330 BUF_AMPDU = BIT(2), 331 BUF_HT = BIT(3), 332 BUF_RETRY = BIT(4), 333 BUF_XRETRY = BIT(5), 334 BUF_SHORT_PREAMBLE = BIT(6), 335 BUF_BAR = BIT(7), 336 BUF_PSPOLL = BIT(8), 337 BUF_AGGR_BURST = BIT(9), 338 BUF_CALC_AIRTIME = BIT(10), 339 }; 340 341 struct ath_buf_state { 342 int bfs_nframes; /* # frames in aggregate */ 343 uint16_t bfs_al; /* length of aggregate */ 344 uint16_t bfs_frmlen; /* length of frame */ 345 int bfs_seqno; /* sequence number */ 346 int bfs_tidno; /* tid of this frame */ 347 int bfs_retries; /* current retries */ 348 uint32_t bf_type; /* BUF_* (enum buffer_type) */ 349 /* key type used to encrypt this frame */ 350 uint32_t bfs_keyix; 351 enum ath9k_key_type bfs_keytype; 352 }; 353 354 #define bf_nframes bf_state.bfs_nframes 355 #define bf_al bf_state.bfs_al 356 #define bf_frmlen bf_state.bfs_frmlen 357 #define bf_retries bf_state.bfs_retries 358 #define bf_seqno bf_state.bfs_seqno 359 #define bf_tidno bf_state.bfs_tidno 360 #define bf_rcs bf_state.bfs_rcs 361 #define bf_keyix bf_state.bfs_keyix 362 #define bf_keytype bf_state.bfs_keytype 363 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA) 364 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 365 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 366 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) 367 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 368 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 369 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE) 370 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR) 371 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL) 372 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST) 373 374 /* 375 * Abstraction of a contiguous buffer to transmit/receive. 376 * There is only a single hw descriptor encapsulated here. 377 */ 378 struct ath_buf { 379 /* last buf of this unit (a frame or an aggregate) */ 380 struct ath_buf *bf_lastbf; 381 struct ath_buf *bf_lastfrm; /* last buf of this frame */ 382 struct ath_buf *bf_next; /* next subframe in the aggregate */ 383 mblk_t *bf_m; 384 struct ath_desc *bf_desc; /* virtual addr of desc */ 385 uint32_t bf_daddr; /* physical addr of desc */ 386 dma_area_t bf_dma; /* dma area for buf */ 387 struct ieee80211_node *bf_in; /* pointer to the node */ 388 uint32_t bf_status; 389 uint16_t bf_flags; /* tx descriptor flags */ 390 struct ath_buf_state bf_state; /* buffer state */ 391 392 /* Temp workground for rc */ 393 struct ath9k_tx_rate rates[4]; 394 struct ath_tx_info_priv tx_info_priv; 395 396 /* we're in list of sc->sc_txbuf_list or sc->sc_rxbuf_list */ 397 list_node_t bf_node; 398 }; 399 400 /* 401 * reset the rx buffer. 402 * any new fields added to the athbuf and require 403 * reset need to be added to this macro. 404 * currently bf_status is the only one requires that 405 * requires reset. 406 */ 407 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) 408 409 /* hw processing complete, desc processed by hal */ 410 #define ATH_BUFSTATUS_DONE 0x00000001 411 /* hw processing complete, desc hold for hw */ 412 #define ATH_BUFSTATUS_STALE 0x00000002 413 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */ 414 #define ATH_BUFSTATUS_FREE 0x00000004 415 416 /* RX / TX */ 417 418 #define ATH_MAX_ANTENNA 3 419 #define ATH_RXBUF 512 420 #define WME_NUM_TID 16 421 422 void arn_rx_buf_link(struct arn_softc *sc, struct ath_buf *bf); 423 int arn_startrecv(struct arn_softc *sc); 424 boolean_t arn_stoprecv(struct arn_softc *sc); 425 void arn_flushrecv(struct arn_softc *sc); 426 uint32_t arn_calcrxfilter(struct arn_softc *sc); 427 int arn_rx_init(struct arn_softc *sc, int nbufs); 428 void arn_rx_cleanup(struct arn_softc *sc); 429 uint_t arn_softint_handler(caddr_t data); 430 void arn_setdefantenna(struct arn_softc *sc, uint32_t antenna); 431 432 #define ATH_TXBUF 512 433 /* max number of transmit attempts (tries) */ 434 #define ATH_TXMAXTRY 13 435 /* max number of 11n transmit attempts (tries) */ 436 #define ATH_11N_TXMAXTRY 10 437 /* max number of tries for management and control frames */ 438 #define ATH_MGT_TXMAXTRY 4 439 #define WME_BA_BMP_SIZE 64 440 #define WME_MAX_BA WME_BA_BMP_SIZE 441 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) 442 443 /* Wireless Multimedia Extension Defines */ 444 #define WME_AC_BE 0 /* best effort */ 445 #define WME_AC_BK 1 /* background */ 446 #define WME_AC_VI 2 /* video */ 447 #define WME_AC_VO 3 /* voice */ 448 #define WME_NUM_AC 4 449 450 /* 451 * Data transmit queue state. One of these exists for each 452 * hardware transmit queue. Packets sent to us from above 453 * are assigned to queues based on their priority. Not all 454 * devices support a complete set of hardware transmit queues. 455 * For those devices the array sc_ac2q will map multiple 456 * priorities to fewer hardware queues (typically all to one 457 * hardware queue). 458 */ 459 460 struct ath_txq { 461 uint32_t axq_qnum; /* hardware q number */ 462 uint32_t *axq_link; /* link ptr in last TX desc */ 463 list_t axq_list; /* transmit queue */ 464 kmutex_t axq_lock; /* lock on q and link */ 465 unsigned long axq_lockflags; /* intr state when must cli */ 466 uint32_t axq_depth; /* queue depth (stat only) */ 467 uint8_t axq_aggr_depth; /* aggregates queued */ 468 uint32_t axq_totalqueued; /* total ever queued */ 469 boolean_t stopped; 470 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer */ 471 /* first desc of the last descriptor that contains CTS */ 472 struct ath_desc *axq_lastdsWithCTS; 473 474 /* 475 * final desc of the gating desc that determines whether 476 * lastdsWithCTS has been DMA'ed or not 477 */ 478 struct ath_desc *axq_gatingds; 479 480 list_t axq_acq; 481 482 uint32_t axq_intrcnt; /* interrupt count */ 483 }; 484 485 486 #define AGGR_CLEANUP BIT(1) 487 #define AGGR_ADDBA_COMPLETE BIT(2) 488 #define AGGR_ADDBA_PROGRESS BIT(3) 489 490 /* per TID aggregate tx state for a destination */ 491 struct ath_atx_tid { 492 list_node_t list; 493 list_t buf_q; 494 struct ath_node *an; 495 struct ath_atx_ac *ac; 496 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ 497 uint16_t seq_start; 498 uint16_t seq_next; 499 uint16_t baw_size; 500 int tidno; 501 int baw_head; /* first un-acked tx buffer */ 502 int baw_tail; /* next unused tx buffer slot */ 503 int sched; 504 int paused; 505 uint8_t state; 506 int addba_exchangeattempts; 507 }; 508 509 /* per access-category aggregate tx state for a destination */ 510 struct ath_atx_ac { 511 int sched; /* dest-ac is scheduled */ 512 int qnum; /* H/W queue number associated with this AC */ 513 list_node_t list; 514 list_t tid_q; 515 }; 516 517 /* per dest tx state */ 518 struct ath_atx { 519 struct ath_atx_tid tid[WME_NUM_TID]; 520 struct ath_atx_ac ac[WME_NUM_AC]; 521 }; 522 523 /* per-frame tx control block */ 524 struct ath_tx_control { 525 struct ath_txq *txq; 526 int if_id; 527 }; 528 529 /* per frame tx status block */ 530 struct ath_xmit_status { 531 /* number of retries to successufully transmit this frame */ 532 int retries; 533 int flags; /* status of transmit */ 534 #define ATH_TX_ERROR 0x01 535 #define ATH_TX_XRETRY 0x02 536 #define ATH_TX_BAR 0x04 537 }; 538 539 struct ath_tx_stat { 540 int rssi; /* RSSI (noise floor ajusted) */ 541 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 542 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 543 int rateieee; /* data rate xmitted (IEEE rate code) */ 544 int rateKbps; /* data rate xmitted (Kbps) */ 545 int ratecode; /* phy rate code */ 546 int flags; /* validity flags */ 547 /* if any of ctl,extn chain rssis are valid */ 548 #define ATH_TX_CHAIN_RSSI_VALID 0x01 549 /* if extn chain rssis are valid */ 550 #define ATH_TX_RSSI_EXTN_VALID 0x02 551 uint32_t airtime; /* time on air per final tx rate */ 552 }; 553 554 void arn_tx_node_init(struct arn_softc *sc, struct ath_node *an); 555 void arn_tx_node_cleanup(struct arn_softc *sc, struct ieee80211_node *in); 556 struct ath_txq *arn_txq_setup(struct arn_softc *sc, int qtype, int subtype); 557 void arn_tx_cleanupq(struct arn_softc *sc, struct ath_txq *txq); 558 int arn_tx_setup(struct arn_softc *sc, int haltype); 559 void arn_draintxq(struct arn_softc *sc, boolean_t retry_tx); 560 void arn_tx_draintxq(struct arn_softc *sc, struct ath_txq *txq); 561 void arn_txq_schedule(struct arn_softc *sc, struct ath_txq *txq); 562 int arn_tx(ieee80211com_t *ic, mblk_t *mp, uint8_t type); 563 int arn_txq_update(struct arn_softc *sc, int qnum, 564 struct ath9k_tx_queue_info *qinfo); 565 void arn_tx_int_proc(void *arg); 566 567 /* Node / Aggregation */ 568 569 #define ADDBA_EXCHANGE_ATTEMPTS 10 570 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */ 571 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 572 /* number of delimiters for encryption padding */ 573 #define ATH_AGGR_ENCRYPTDELIM 10 574 /* minimum h/w qdepth to be sustained to maximize aggregation */ 575 #define ATH_AGGR_MIN_QDEPTH 2 576 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 577 #define IEEE80211_SEQ_SEQ_SHIFT 4 578 #define IEEE80211_SEQ_MAX 4096 579 #define IEEE80211_MIN_AMPDU_BUF 0x8 580 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 581 582 /* 583 * return whether a bit at index _n in bitmap _bm is set 584 * _sz is the size of the bitmap 585 */ 586 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 587 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 588 589 /* return block-ack bitmap index given sequence and starting sequence */ 590 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 591 592 /* returns delimiter padding required given the packet length */ 593 #define ATH_AGGR_GET_NDELIM(_len) \ 594 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ 595 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) 596 597 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 598 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 599 600 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) 601 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) 602 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) 603 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 604 605 #define ATH_TX_ERROR 0x01 606 #define ATH_TX_XRETRY 0x02 607 #define ATH_TX_BAR 0x04 608 609 enum ATH_AGGR_STATUS { 610 ATH_AGGR_DONE, 611 ATH_AGGR_BAW_CLOSED, 612 ATH_AGGR_LIMITED, 613 }; 614 615 struct aggr_rifs_param { 616 int param_max_frames; 617 int param_max_len; 618 int param_rl; 619 int param_al; 620 struct ath_rc_series *param_rcs; 621 }; 622 623 /* RSSI correction */ 624 void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); 625 626 #define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE -85 627 #define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE -112 628 #define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE -118 629 630 #define ATH_RSSI_LPF_LEN 10 631 #define RSSI_LPF_THRESHOLD -20 632 #define ATH9K_RSSI_BAD -128 633 #define ATH_RSSI_EP_MULTIPLIER (1<<7) 634 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 635 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER)) 636 #define ATH_LPF_RSSI(x, y, len) \ 637 ((x != ATH_RSSI_DUMMY_MARKER) ? \ 638 (((x) * ((len) - 1) + (y)) / (len)) : (y)) 639 #define ATH_RSSI_LPF(x, y) do { \ 640 if ((y) >= RSSI_LPF_THRESHOLD) \ 641 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 642 } while (0) 643 #define ATH_EP_RND(x, mul) \ 644 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 645 646 /* driver-specific node state */ 647 struct ath_node { 648 struct ieee80211_node an_node; /* base class */ 649 uint32_t an_tx_times; /* rate ctl times on one rate */ 650 uint32_t an_tx_ok; /* tx ok pkt */ 651 uint32_t an_tx_err; /* tx !ok pkt */ 652 uint32_t an_tx_retr; /* tx retry count */ 653 int32_t an_tx_upper; /* tx upper rate req cnt */ 654 uint32_t an_tx_antenna; /* antenna for last good frame */ 655 uint8_t an_tx_rix0; /* series 0 rate index */ 656 uint8_t an_tx_try0; /* series 0 try count */ 657 uint8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */ 658 uint8_t an_tx_mgtratesp; /* short preamble h/w rate for " " */ 659 uint8_t an_tx_rate0; /* series 0 h/w rate */ 660 uint8_t an_tx_rate1; /* series 1 h/w rate */ 661 uint8_t an_tx_rate2; /* series 2 h/w rate */ 662 uint8_t an_tx_rate3; /* series 3 h/w rate */ 663 uint8_t an_tx_rate0sp; /* series 0 short preamble h/w rate */ 664 uint8_t an_tx_rate1sp; /* series 1 short preamble h/w rate */ 665 uint8_t an_tx_rate2sp; /* series 2 short preamble h/w rate */ 666 uint8_t an_tx_rate3sp; /* series 3 short preamble h/w rate */ 667 struct ath_rate_priv rate_priv; 668 struct ath_atx_tid tid[WME_NUM_TID]; 669 struct ath_atx_ac ac[WME_NUM_AC]; 670 uint16_t maxampdu; 671 uint8_t mpdudensity; 672 int last_rssi; 673 }; 674 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 675 676 /* 677 * Define the scheme that we select MAC address for multiple 678 * BSS on the same radio. The very first VAP will just use the MAC 679 * address from the EEPROM. For the next 3 VAPs, we set the 680 * U/L bit (bit 1) in MAC address, and use the next two bits as the 681 * index of the VAP. 682 */ 683 684 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ 685 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) 686 687 688 /* driver-specific vap state */ 689 struct ath_vap { 690 int av_bslot; /* beacon slot index */ 691 enum ath9k_opmode av_opmode; /* VAP operational mode */ 692 struct ath_buf *av_bcbuf; /* beacon buffer */ 693 struct ath_tx_control av_btxctl; /* txctl information for beacon */ 694 }; 695 696 /* Beacon Handling */ 697 698 /* 699 * Regardless of the number of beacons we stagger, (i.e. regardless of the 700 * number of BSSIDs) if a given beacon does not go out even after waiting this 701 * number of beacon intervals, the game's up. 702 */ 703 #define BSTUCK_THRESH (9 * ATH_BCBUF) 704 #define ATH_BCBUF 4 /* number of beacon buffers */ 705 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */ 706 #define ATH_DEFAULT_BMISS_LIMIT 10 707 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 708 709 /* beacon configuration */ 710 struct ath_beacon_config { 711 uint16_t beacon_interval; 712 uint16_t listen_interval; 713 uint16_t dtim_period; 714 uint16_t bmiss_timeout; 715 uint8_t dtim_count; 716 uint8_t tim_offset; 717 union { 718 uint64_t last_tsf; 719 uint8_t last_tstamp[8]; 720 } u; /* last received beacon/probe response timestamp of this BSS. */ 721 }; 722 723 uint32_t arn_beaconq_setup(struct ath_hal *ah); 724 int arn_beacon_alloc(struct arn_softc *sc, struct ieee80211_node *in); 725 void arn_beacon_config(struct arn_softc *sc); 726 void arn_beacon_return(struct arn_softc *sc); 727 void arn_beacon_sync(struct arn_softc *sc); 728 void arn_bmiss_proc(void *arg); 729 730 void arn_recv_mgmt(struct ieee80211com *ic, mblk_t *mp, 731 struct ieee80211_node *in, int subtype, int rssi, uint32_t rstamp); 732 733 /* ANI */ 734 735 /* 736 * ANI values for STA only. 737 * FIXME: Add appropriate values for AP later 738 */ 739 740 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */ 741 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */ 742 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */ 743 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */ 744 745 struct ath_ani { 746 boolean_t sc_caldone; 747 int16_t sc_noise_floor; 748 unsigned int sc_longcal_timer; 749 unsigned int sc_shortcal_timer; 750 unsigned int sc_resetcal_timer; 751 unsigned int sc_checkani_timer; 752 }; 753 754 /* LED Control */ 755 #define ATH_LED_PIN 1 756 757 enum ath_led_type { 758 ATH_LED_RADIO, 759 ATH_LED_ASSOC, 760 ATH_LED_TX, 761 ATH_LED_RX 762 }; 763 764 struct ath_led { 765 struct arn_softc *sc; 766 enum ath_led_type led_type; 767 char name[32]; 768 boolean_t registered; 769 }; 770 771 /* Rfkill */ 772 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */ 773 774 /* Main driver core */ 775 /* 776 * Default cache line size, in bytes. 777 * Used when PCI device not fully initialized by bootrom/BIOS 778 */ 779 #define DEFAULT_CACHELINE 32 780 #define ATH_DEFAULT_NOISE_FLOOR -95 781 #define ATH_REGCLASSIDS_MAX 10 782 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 783 #define ATH_MAX_SW_RETRIES 10 784 #define ATH_CHAN_MAX 255 785 #define IEEE80211_WEP_NKID 4 /* number of key ids */ 786 #define IEEE80211_RATE_VAL 0x7f 787 /* 788 * The key cache is used for h/w cipher state and also for 789 * tracking station state such as the current tx antenna. 790 * We also setup a mapping table between key cache slot indices 791 * and station state to short-circuit node lookups on rx. 792 * Different parts have different size key caches. We handle 793 * up to ATH_KEYMAX entries (could dynamically allocate state). 794 */ 795 #define ATH_KEYMAX 128 /* max key cache size we handle */ 796 797 #define ATH_IF_ID_ANY 0xff 798 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 799 #define ATH_RSSI_DUMMY_MARKER 0x127 800 #define ATH_RATE_DUMMY_MARKER 0 801 802 enum PROT_MODE { 803 PROT_M_NONE = 0, 804 PROT_M_RTSCTS, 805 PROT_M_CTSONLY 806 }; 807 808 #define SC_OP_INVALID BIT(0) 809 #define SC_OP_BEACONS BIT(1) 810 #define SC_OP_RXAGGR BIT(2) 811 #define SC_OP_TXAGGR BIT(3) 812 #define SC_OP_CHAINMASK_UPDATE BIT(4) 813 #define SC_OP_FULL_RESET BIT(5) 814 #define SC_OP_NO_RESET BIT(6) 815 #define SC_OP_PREAMBLE_SHORT BIT(7) 816 #define SC_OP_PROTECT_ENABLE BIT(8) 817 #define SC_OP_RXFLUSH BIT(9) 818 #define SC_OP_LED_ASSOCIATED BIT(10) 819 #define SC_OP_RFKILL_REGISTERED BIT(11) 820 #define SC_OP_RFKILL_SW_BLOCKED BIT(12) 821 #define SC_OP_RFKILL_HW_BLOCKED BIT(13) 822 823 /* HT */ 824 typedef struct ht_conf { 825 boolean_t ht_supported; 826 uint16_t cap; 827 uint8_t ampdu_factor; 828 uint8_t ampdu_density; 829 uint8_t rx_mcs_mask[10]; 830 } arn_ht_conf; 831 832 uint8_t parse_mpdudensity(uint8_t mpdudensity); 833 834 void arn_ampdu_recv_action(struct ieee80211_node *in, 835 const uint8_t *frm, const uint8_t *efrm); 836 int arn_ampdu_send_action(struct ieee80211_node *in, 837 int category, int action, uint16_t args[4]); 838 void arn_dump_line(unsigned char *p, uint32_t len, boolean_t isaddress, 839 uint32_t group); 840 void arn_dump_pkg(unsigned char *p, uint32_t len, boolean_t isaddress, 841 uint32_t group); 842 843 struct arn_softc { 844 ieee80211com_t sc_isc; /* IEEE 802.11 common */ 845 dev_info_t *sc_dev; /* back pointer to dev_info_t */ 846 ddi_taskq_t *sc_tq; /* private task queue */ 847 struct ath_hal *sc_ah; 848 struct ath_config sc_config; 849 caddr_t mem; 850 851 uint8_t sc_isrunning; /* device is operational */ 852 uint8_t sc_mrretry; /* multi-rate retry support */ 853 uint8_t sc_have11g; /* have 11g support */ 854 uint8_t sc_bsync; /* beacon sync */ 855 856 ddi_acc_handle_t sc_cfg_handle; /* DDI I/O handle */ 857 ddi_acc_handle_t sc_io_handle; /* DDI I/O handle */ 858 ddi_acc_handle_t sc_EEPROM_handle; /* DDI I/O handle */ 859 ddi_iblock_cookie_t sc_iblock; 860 ddi_softintr_t sc_softint_id; 861 862 /* 802.11n/HT capabilities */ 863 arn_ht_conf sc_ht_conf; 864 void (*sc_recv_action)(ieee80211_node_t *, 865 const uint8_t *, const uint8_t *); 866 int (*sc_send_action)(ieee80211_node_t *, 867 int, int, uint16_t[4]); 868 869 /* TX/RX descriptors */ 870 struct ath_desc *sc_desc; 871 /* descriptor structure */ 872 dma_area_t sc_desc_dma; 873 /* pointer to the first "struct ath_buf" */ 874 struct ath_buf *sc_vbufptr; 875 /* length of all allocated "struct ath_buf" */ 876 uint32_t sc_vbuflen; 877 /* size of one DMA TX/RX buffer based on 802.11 MTU */ 878 uint32_t tx_dmabuf_size; 879 uint32_t rx_dmabuf_size; 880 881 uint8_t sc_curbssid[6]; 882 uint8_t sc_myaddr[6]; 883 uint8_t sc_bssidmask[6]; 884 885 int sc_debug; 886 uint32_t sc_intrstatus; 887 uint32_t sc_flags; /* SC_OP_* */ 888 unsigned int rx_filter; 889 uint16_t sc_curtxpow; 890 uint16_t sc_curaid; 891 uint16_t sc_cachelsz; 892 int sc_slotupdate; /* slot to next advance fsm */ 893 int sc_slottime; 894 int sc_bslot[ATH_BCBUF]; 895 uint8_t sc_tx_chainmask; 896 uint8_t sc_rx_chainmask; 897 enum ath9k_int sc_imask; 898 enum PROT_MODE sc_protmode; 899 900 uint8_t sc_nbcnvaps; /* # of vaps sending beacons */ 901 uint16_t sc_nvaps; /* # of active virtual ap's */ 902 903 uint8_t sc_mcastantenna; 904 uint8_t sc_defant; /* current default antenna */ 905 uint8_t sc_rxotherant; /* rx's on non-default antenna */ 906 907 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */ 908 enum ath9k_ht_extprotspacing sc_ht_extprotspacing; 909 enum ath9k_ht_macmode tx_chan_width; 910 911 enum { 912 OK, /* no change needed */ 913 UPDATE, /* update pending */ 914 COMMIT /* beacon sent, commit change */ 915 } sc_updateslot; /* slot time update fsm */ 916 917 /* Crypto */ 918 uint32_t sc_keymax; /* size of key cache */ 919 uint8_t sc_keymap[16]; /* bit map of key cache use */ 920 uint8_t sc_splitmic; /* split TKIP MIC keys */ 921 922 /* RX */ 923 list_t sc_rxbuf_list; 924 int sc_rxbufsize; /* rx size based on mtu */ 925 uint32_t *sc_rxlink; /* link ptr in last RX desc */ 926 uint32_t sc_rx_pend; 927 uint64_t sc_lastrx; /* tsf at last rx'd frame */ 928 929 /* TX */ 930 list_t sc_txbuf_list; 931 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES]; 932 uint32_t sc_txqsetup; 933 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */ 934 uint16_t seq_no; /* TX sequence number */ 935 936 /* Beacon */ 937 struct ath9k_tx_queue_info sc_beacon_qi; 938 struct ath_txq *sc_cabq; 939 list_t sc_bcbuf_list; /* beacon buffer */ 940 uint32_t sc_beaconq; 941 uint32_t sc_bmisscount; 942 uint32_t ast_be_xmit; /* beacons transmitted */ 943 uint64_t bc_tstamp; 944 struct ieee80211_beacon_offsets asc_boff; /* dynamic update state */ 945 946 /* Rate */ 947 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 948 struct ath_rate_table *sc_currates; /* current rate table */ 949 uint8_t asc_rixmap[256]; /* IEEE to h/w rate table ix */ 950 uint8_t sc_protrix; /* protection rate index */ 951 952 /* mode */ 953 enum wireless_mode sc_curmode; /* current phy mode */ 954 955 /* Channel, Band */ 956 struct ath9k_channel sc_curchan; 957 958 /* Locks */ 959 kmutex_t sc_genlock; 960 kmutex_t sc_serial_rw; 961 kmutex_t sc_rxbuflock; /* recv lock */ 962 kmutex_t sc_txbuflock; /* txbuf lock */ 963 kmutex_t sc_rxflushlock; 964 kmutex_t sc_resetlock; 965 kmutex_t sc_bcbuflock; /* beacon buffer lock */ 966 kmutex_t sc_resched_lock; 967 boolean_t sc_resched_needed; 968 969 /* LEDs */ 970 struct ath_led radio_led; 971 struct ath_led assoc_led; 972 struct ath_led tx_led; 973 struct ath_led rx_led; 974 975 uint8_t sc_mcast_refs[64]; /* refer count */ 976 uint32_t sc_mcast_hash[2]; /* multicast hash table */ 977 978 /* Rfkill */ 979 980 /* ANI */ 981 struct ath_ani sc_ani; 982 983 /* interface statistics */ 984 struct ath_stats sc_stats; 985 986 boolean_t sc_promisc; /* Promiscuous mode enabled */ 987 988 timeout_id_t sc_scan_timer; 989 timeout_id_t sc_cal_timer; 990 991 int (*sc_newstate)(ieee80211com_t *, enum ieee80211_state, int); 992 void (*sc_recv_mgmt)(ieee80211com_t *, mblk_t *, ieee80211_node_t *, 993 int, int, uint32_t); 994 }; 995 996 int arn_reset(ieee80211com_t *ic); 997 998 int arn_get_hal_qnum(uint16_t queue, struct arn_softc *sc); 999 1000 int ath_cabq_update(struct arn_softc *); 1001 1002 void arn_update_chainmask(struct arn_softc *sc); 1003 1004 /* 1005 * Read and write, they both share the same lock. We do this to serialize 1006 * reads and writes on Atheros 802.11n PCI devices only. This is required 1007 * as the FIFO on these devices can only accept sanely 2 requests. After 1008 * that the device goes bananas. Serializing the reads/writes prevents this 1009 * from happening. 1010 */ 1011 void 1012 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val); 1013 unsigned int 1014 arn_ioread32(struct ath_hal *ah, uint32_t reg_offset); 1015 1016 #ifdef __cplusplus 1017 } 1018 #endif 1019 1020 #endif /* _ARN_CORE_H */ 1021