1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2023, Linaro Limited
5 */
6
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
14
15 #include "bcm-voter.h"
16 #include "icc-rpmh.h"
17
18 static struct qcom_icc_node qxm_qup3;
19 static struct qcom_icc_node xm_emac_0;
20 static struct qcom_icc_node xm_emac_1;
21 static struct qcom_icc_node xm_sdc1;
22 static struct qcom_icc_node xm_ufs_mem;
23 static struct qcom_icc_node xm_usb2_2;
24 static struct qcom_icc_node xm_usb3_0;
25 static struct qcom_icc_node xm_usb3_1;
26 static struct qcom_icc_node qns_a1noc_snoc;
27 static struct qcom_icc_node qhm_qdss_bam;
28 static struct qcom_icc_node qhm_qup0;
29 static struct qcom_icc_node qhm_qup1;
30 static struct qcom_icc_node qhm_qup2;
31 static struct qcom_icc_node qnm_cnoc_datapath;
32 static struct qcom_icc_node qxm_crypto_0;
33 static struct qcom_icc_node qxm_crypto_1;
34 static struct qcom_icc_node qxm_ipa;
35 static struct qcom_icc_node xm_qdss_etr_0;
36 static struct qcom_icc_node xm_qdss_etr_1;
37 static struct qcom_icc_node xm_ufs_card;
38 static struct qcom_icc_node qns_a2noc_snoc;
39 static struct qcom_icc_node qup0_core_master;
40 static struct qcom_icc_node qup1_core_master;
41 static struct qcom_icc_node qup2_core_master;
42 static struct qcom_icc_node qup3_core_master;
43 static struct qcom_icc_node qup0_core_slave;
44 static struct qcom_icc_node qup1_core_slave;
45 static struct qcom_icc_node qup2_core_slave;
46 static struct qcom_icc_node qup3_core_slave;
47 static struct qcom_icc_node qnm_gemnoc_cnoc;
48 static struct qcom_icc_node qnm_gemnoc_pcie;
49 static struct qcom_icc_node qhs_ahb2phy0;
50 static struct qcom_icc_node qhs_ahb2phy1;
51 static struct qcom_icc_node qhs_ahb2phy2;
52 static struct qcom_icc_node qhs_ahb2phy3;
53 static struct qcom_icc_node qhs_anoc_throttle_cfg;
54 static struct qcom_icc_node qhs_aoss;
55 static struct qcom_icc_node qhs_apss;
56 static struct qcom_icc_node qhs_boot_rom;
57 static struct qcom_icc_node qhs_camera_cfg;
58 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg;
59 static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
60 static struct qcom_icc_node qhs_clk_ctl;
61 static struct qcom_icc_node qhs_compute0_cfg;
62 static struct qcom_icc_node qhs_compute1_cfg;
63 static struct qcom_icc_node qhs_cpr_cx;
64 static struct qcom_icc_node qhs_cpr_mmcx;
65 static struct qcom_icc_node qhs_cpr_mx;
66 static struct qcom_icc_node qhs_cpr_nspcx;
67 static struct qcom_icc_node qhs_crypto0_cfg;
68 static struct qcom_icc_node qhs_cx_rdpm;
69 static struct qcom_icc_node qhs_display0_cfg;
70 static struct qcom_icc_node qhs_display0_rt_throttle_cfg;
71 static struct qcom_icc_node qhs_display1_cfg;
72 static struct qcom_icc_node qhs_display1_rt_throttle_cfg;
73 static struct qcom_icc_node qhs_emac0_cfg;
74 static struct qcom_icc_node qhs_emac1_cfg;
75 static struct qcom_icc_node qhs_gp_dsp0_cfg;
76 static struct qcom_icc_node qhs_gp_dsp1_cfg;
77 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg;
78 static struct qcom_icc_node qhs_gpdsp1_throttle_cfg;
79 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg;
80 static struct qcom_icc_node qhs_gpuss_cfg;
81 static struct qcom_icc_node qhs_hwkm;
82 static struct qcom_icc_node qhs_imem_cfg;
83 static struct qcom_icc_node qhs_ipa;
84 static struct qcom_icc_node qhs_ipc_router;
85 static struct qcom_icc_node qhs_lpass_cfg;
86 static struct qcom_icc_node qhs_lpass_throttle_cfg;
87 static struct qcom_icc_node qhs_mx_rdpm;
88 static struct qcom_icc_node qhs_mxc_rdpm;
89 static struct qcom_icc_node qhs_pcie0_cfg;
90 static struct qcom_icc_node qhs_pcie1_cfg;
91 static struct qcom_icc_node qhs_pcie_rsc_cfg;
92 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg;
93 static struct qcom_icc_node qhs_pcie_throttle_cfg;
94 static struct qcom_icc_node qhs_pdm;
95 static struct qcom_icc_node qhs_pimem_cfg;
96 static struct qcom_icc_node qhs_pke_wrapper_cfg;
97 static struct qcom_icc_node qhs_qdss_cfg;
98 static struct qcom_icc_node qhs_qm_cfg;
99 static struct qcom_icc_node qhs_qm_mpu_cfg;
100 static struct qcom_icc_node qhs_qup0;
101 static struct qcom_icc_node qhs_qup1;
102 static struct qcom_icc_node qhs_qup2;
103 static struct qcom_icc_node qhs_qup3;
104 static struct qcom_icc_node qhs_sail_throttle_cfg;
105 static struct qcom_icc_node qhs_sdc1;
106 static struct qcom_icc_node qhs_security;
107 static struct qcom_icc_node qhs_snoc_throttle_cfg;
108 static struct qcom_icc_node qhs_tcsr;
109 static struct qcom_icc_node qhs_tlmm;
110 static struct qcom_icc_node qhs_tsc_cfg;
111 static struct qcom_icc_node qhs_ufs_card_cfg;
112 static struct qcom_icc_node qhs_ufs_mem_cfg;
113 static struct qcom_icc_node qhs_usb2_0;
114 static struct qcom_icc_node qhs_usb3_0;
115 static struct qcom_icc_node qhs_usb3_1;
116 static struct qcom_icc_node qhs_venus_cfg;
117 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
118 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg;
119 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg;
120 static struct qcom_icc_node qns_ddrss_cfg;
121 static struct qcom_icc_node qns_gpdsp_noc_cfg;
122 static struct qcom_icc_node qns_mnoc_hf_cfg;
123 static struct qcom_icc_node qns_mnoc_sf_cfg;
124 static struct qcom_icc_node qns_pcie_anoc_cfg;
125 static struct qcom_icc_node qns_snoc_cfg;
126 static struct qcom_icc_node qxs_boot_imem;
127 static struct qcom_icc_node qxs_imem;
128 static struct qcom_icc_node qxs_pimem;
129 static struct qcom_icc_node xs_pcie_0;
130 static struct qcom_icc_node xs_pcie_1;
131 static struct qcom_icc_node xs_qdss_stm;
132 static struct qcom_icc_node xs_sys_tcu_cfg;
133 static struct qcom_icc_node qnm_cnoc_dc_noc;
134 static struct qcom_icc_node qhs_llcc;
135 static struct qcom_icc_node qns_gemnoc;
136 static struct qcom_icc_node alm_gpu_tcu;
137 static struct qcom_icc_node alm_pcie_tcu;
138 static struct qcom_icc_node alm_sys_tcu;
139 static struct qcom_icc_node chm_apps;
140 static struct qcom_icc_node qnm_cmpnoc0;
141 static struct qcom_icc_node qnm_cmpnoc1;
142 static struct qcom_icc_node qnm_gemnoc_cfg;
143 static struct qcom_icc_node qnm_gpdsp_sail;
144 static struct qcom_icc_node qnm_gpu;
145 static struct qcom_icc_node qnm_mnoc_hf;
146 static struct qcom_icc_node qnm_mnoc_sf;
147 static struct qcom_icc_node qnm_pcie;
148 static struct qcom_icc_node qnm_snoc_gc;
149 static struct qcom_icc_node qnm_snoc_sf;
150 static struct qcom_icc_node qns_gem_noc_cnoc;
151 static struct qcom_icc_node qns_llcc;
152 static struct qcom_icc_node qns_pcie;
153 static struct qcom_icc_node srvc_even_gemnoc;
154 static struct qcom_icc_node srvc_odd_gemnoc;
155 static struct qcom_icc_node srvc_sys_gemnoc;
156 static struct qcom_icc_node srvc_sys_gemnoc_2;
157 static struct qcom_icc_node qxm_dsp0;
158 static struct qcom_icc_node qxm_dsp1;
159 static struct qcom_icc_node qns_gp_dsp_sail_noc;
160 static struct qcom_icc_node qhm_config_noc;
161 static struct qcom_icc_node qxm_lpass_dsp;
162 static struct qcom_icc_node qhs_lpass_core;
163 static struct qcom_icc_node qhs_lpass_lpi;
164 static struct qcom_icc_node qhs_lpass_mpu;
165 static struct qcom_icc_node qhs_lpass_top;
166 static struct qcom_icc_node qns_sysnoc;
167 static struct qcom_icc_node srvc_niu_aml_noc;
168 static struct qcom_icc_node srvc_niu_lpass_agnoc;
169 static struct qcom_icc_node llcc_mc;
170 static struct qcom_icc_node ebi;
171 static struct qcom_icc_node qnm_camnoc_hf;
172 static struct qcom_icc_node qnm_camnoc_icp;
173 static struct qcom_icc_node qnm_camnoc_sf;
174 static struct qcom_icc_node qnm_mdp0_0;
175 static struct qcom_icc_node qnm_mdp0_1;
176 static struct qcom_icc_node qnm_mdp1_0;
177 static struct qcom_icc_node qnm_mdp1_1;
178 static struct qcom_icc_node qnm_mnoc_hf_cfg;
179 static struct qcom_icc_node qnm_mnoc_sf_cfg;
180 static struct qcom_icc_node qnm_video0;
181 static struct qcom_icc_node qnm_video1;
182 static struct qcom_icc_node qnm_video_cvp;
183 static struct qcom_icc_node qnm_video_v_cpu;
184 static struct qcom_icc_node qns_mem_noc_hf;
185 static struct qcom_icc_node qns_mem_noc_sf;
186 static struct qcom_icc_node srvc_mnoc_hf;
187 static struct qcom_icc_node srvc_mnoc_sf;
188 static struct qcom_icc_node qhm_nsp_noc_config;
189 static struct qcom_icc_node qxm_nsp;
190 static struct qcom_icc_node qns_hcp;
191 static struct qcom_icc_node qns_nsp_gemnoc;
192 static struct qcom_icc_node service_nsp_noc;
193 static struct qcom_icc_node qhm_nspb_noc_config;
194 static struct qcom_icc_node qxm_nspb;
195 static struct qcom_icc_node qns_nspb_gemnoc;
196 static struct qcom_icc_node qns_nspb_hcp;
197 static struct qcom_icc_node service_nspb_noc;
198 static struct qcom_icc_node xm_pcie3_0;
199 static struct qcom_icc_node xm_pcie3_1;
200 static struct qcom_icc_node qns_pcie_mem_noc;
201 static struct qcom_icc_node qhm_gic;
202 static struct qcom_icc_node qnm_aggre1_noc;
203 static struct qcom_icc_node qnm_aggre2_noc;
204 static struct qcom_icc_node qnm_lpass_noc;
205 static struct qcom_icc_node qnm_snoc_cfg;
206 static struct qcom_icc_node qxm_pimem;
207 static struct qcom_icc_node xm_gic;
208 static struct qcom_icc_node qns_gemnoc_gc;
209 static struct qcom_icc_node qns_gemnoc_sf;
210 static struct qcom_icc_node srvc_snoc;
211
212 static struct qcom_icc_node qxm_qup3 = {
213 .name = "qxm_qup3",
214 .channels = 1,
215 .buswidth = 8,
216 .num_links = 1,
217 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
218 };
219
220 static struct qcom_icc_node xm_emac_0 = {
221 .name = "xm_emac_0",
222 .channels = 1,
223 .buswidth = 8,
224 .num_links = 1,
225 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
226 };
227
228 static struct qcom_icc_node xm_emac_1 = {
229 .name = "xm_emac_1",
230 .channels = 1,
231 .buswidth = 8,
232 .num_links = 1,
233 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
234 };
235
236 static struct qcom_icc_node xm_sdc1 = {
237 .name = "xm_sdc1",
238 .channels = 1,
239 .buswidth = 8,
240 .num_links = 1,
241 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
242 };
243
244 static struct qcom_icc_node xm_ufs_mem = {
245 .name = "xm_ufs_mem",
246 .channels = 1,
247 .buswidth = 8,
248 .num_links = 1,
249 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
250 };
251
252 static struct qcom_icc_node xm_usb2_2 = {
253 .name = "xm_usb2_2",
254 .channels = 1,
255 .buswidth = 8,
256 .num_links = 1,
257 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
258 };
259
260 static struct qcom_icc_node xm_usb3_0 = {
261 .name = "xm_usb3_0",
262 .channels = 1,
263 .buswidth = 8,
264 .num_links = 1,
265 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
266 };
267
268 static struct qcom_icc_node xm_usb3_1 = {
269 .name = "xm_usb3_1",
270 .channels = 1,
271 .buswidth = 8,
272 .num_links = 1,
273 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
274 };
275
276 static struct qcom_icc_node qhm_qdss_bam = {
277 .name = "qhm_qdss_bam",
278 .channels = 1,
279 .buswidth = 4,
280 .num_links = 1,
281 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
282 };
283
284 static struct qcom_icc_node qhm_qup0 = {
285 .name = "qhm_qup0",
286 .channels = 1,
287 .buswidth = 4,
288 .num_links = 1,
289 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
290 };
291
292 static struct qcom_icc_node qhm_qup1 = {
293 .name = "qhm_qup1",
294 .channels = 1,
295 .buswidth = 4,
296 .num_links = 1,
297 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
298 };
299
300 static struct qcom_icc_node qhm_qup2 = {
301 .name = "qhm_qup2",
302 .channels = 1,
303 .buswidth = 4,
304 .num_links = 1,
305 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
306 };
307
308 static struct qcom_icc_node qnm_cnoc_datapath = {
309 .name = "qnm_cnoc_datapath",
310 .channels = 1,
311 .buswidth = 8,
312 .num_links = 1,
313 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
314 };
315
316 static struct qcom_icc_node qxm_crypto_0 = {
317 .name = "qxm_crypto_0",
318 .channels = 1,
319 .buswidth = 8,
320 .num_links = 1,
321 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
322 };
323
324 static struct qcom_icc_node qxm_crypto_1 = {
325 .name = "qxm_crypto_1",
326 .channels = 1,
327 .buswidth = 8,
328 .num_links = 1,
329 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
330 };
331
332 static struct qcom_icc_node qxm_ipa = {
333 .name = "qxm_ipa",
334 .channels = 1,
335 .buswidth = 8,
336 .num_links = 1,
337 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
338 };
339
340 static struct qcom_icc_node xm_qdss_etr_0 = {
341 .name = "xm_qdss_etr_0",
342 .channels = 1,
343 .buswidth = 8,
344 .num_links = 1,
345 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
346 };
347
348 static struct qcom_icc_node xm_qdss_etr_1 = {
349 .name = "xm_qdss_etr_1",
350 .channels = 1,
351 .buswidth = 8,
352 .num_links = 1,
353 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
354 };
355
356 static struct qcom_icc_node xm_ufs_card = {
357 .name = "xm_ufs_card",
358 .channels = 1,
359 .buswidth = 8,
360 .num_links = 1,
361 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
362 };
363
364 static struct qcom_icc_node qup0_core_master = {
365 .name = "qup0_core_master",
366 .channels = 1,
367 .buswidth = 4,
368 .num_links = 1,
369 .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave },
370 };
371
372 static struct qcom_icc_node qup1_core_master = {
373 .name = "qup1_core_master",
374 .channels = 1,
375 .buswidth = 4,
376 .num_links = 1,
377 .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave },
378 };
379
380 static struct qcom_icc_node qup2_core_master = {
381 .name = "qup2_core_master",
382 .channels = 1,
383 .buswidth = 4,
384 .num_links = 1,
385 .link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave },
386 };
387
388 static struct qcom_icc_node qup3_core_master = {
389 .name = "qup3_core_master",
390 .channels = 1,
391 .buswidth = 4,
392 .num_links = 1,
393 .link_nodes = (struct qcom_icc_node *[]) { &qup3_core_slave },
394 };
395
396 static struct qcom_icc_node qnm_gemnoc_cnoc = {
397 .name = "qnm_gemnoc_cnoc",
398 .channels = 1,
399 .buswidth = 16,
400 .num_links = 82,
401 .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1,
402 &qhs_ahb2phy2, &qhs_ahb2phy3,
403 &qhs_anoc_throttle_cfg, &qhs_aoss,
404 &qhs_apss, &qhs_boot_rom,
405 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
406 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
407 &qhs_compute0_cfg, &qhs_compute1_cfg,
408 &qhs_cpr_cx, &qhs_cpr_mmcx,
409 &qhs_cpr_mx, &qhs_cpr_nspcx,
410 &qhs_crypto0_cfg, &qhs_cx_rdpm,
411 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
412 &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
413 &qhs_emac0_cfg, &qhs_emac1_cfg,
414 &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
415 &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
416 &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
417 &qhs_hwkm, &qhs_imem_cfg,
418 &qhs_ipa, &qhs_ipc_router,
419 &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
420 &qhs_mx_rdpm, &qhs_mxc_rdpm,
421 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
422 &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
423 &qhs_pcie_throttle_cfg, &qhs_pdm,
424 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
425 &qhs_qdss_cfg, &qhs_qm_cfg,
426 &qhs_qm_mpu_cfg, &qhs_qup0,
427 &qhs_qup1, &qhs_qup2,
428 &qhs_qup3, &qhs_sail_throttle_cfg,
429 &qhs_sdc1, &qhs_security,
430 &qhs_snoc_throttle_cfg, &qhs_tcsr,
431 &qhs_tlmm, &qhs_tsc_cfg,
432 &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
433 &qhs_usb2_0, &qhs_usb3_0,
434 &qhs_usb3_1, &qhs_venus_cfg,
435 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
436 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
437 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
438 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
439 &qns_snoc_cfg, &qxs_boot_imem,
440 &qxs_imem, &qxs_pimem,
441 &xs_qdss_stm, &xs_sys_tcu_cfg },
442 };
443
444 static struct qcom_icc_node qnm_gemnoc_pcie = {
445 .name = "qnm_gemnoc_pcie",
446 .channels = 1,
447 .buswidth = 16,
448 .num_links = 2,
449 .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1 },
450 };
451
452 static struct qcom_icc_node qnm_cnoc_dc_noc = {
453 .name = "qnm_cnoc_dc_noc",
454 .channels = 1,
455 .buswidth = 4,
456 .num_links = 2,
457 .link_nodes = (struct qcom_icc_node *[]) { &qhs_llcc, &qns_gemnoc },
458 };
459
460 static struct qcom_icc_node alm_gpu_tcu = {
461 .name = "alm_gpu_tcu",
462 .channels = 1,
463 .buswidth = 8,
464 .num_links = 2,
465 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
466 };
467
468 static struct qcom_icc_node alm_pcie_tcu = {
469 .name = "alm_pcie_tcu",
470 .channels = 1,
471 .buswidth = 8,
472 .num_links = 2,
473 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
474 };
475
476 static struct qcom_icc_node alm_sys_tcu = {
477 .name = "alm_sys_tcu",
478 .channels = 1,
479 .buswidth = 8,
480 .num_links = 2,
481 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
482 };
483
484 static struct qcom_icc_node chm_apps = {
485 .name = "chm_apps",
486 .channels = 4,
487 .buswidth = 32,
488 .num_links = 3,
489 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
490 &qns_pcie },
491 };
492
493 static struct qcom_icc_node qnm_cmpnoc0 = {
494 .name = "qnm_cmpnoc0",
495 .channels = 2,
496 .buswidth = 32,
497 .num_links = 2,
498 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
499 };
500
501 static struct qcom_icc_node qnm_cmpnoc1 = {
502 .name = "qnm_cmpnoc1",
503 .channels = 2,
504 .buswidth = 32,
505 .num_links = 2,
506 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
507 };
508
509 static struct qcom_icc_node qnm_gemnoc_cfg = {
510 .name = "qnm_gemnoc_cfg",
511 .channels = 1,
512 .buswidth = 4,
513 .num_links = 4,
514 .link_nodes = (struct qcom_icc_node *[]) { &srvc_even_gemnoc, &srvc_odd_gemnoc,
515 &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 },
516 };
517
518 static struct qcom_icc_node qnm_gpdsp_sail = {
519 .name = "qnm_gpdsp_sail",
520 .channels = 1,
521 .buswidth = 16,
522 .num_links = 2,
523 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
524 };
525
526 static struct qcom_icc_node qnm_gpu = {
527 .name = "qnm_gpu",
528 .channels = 2,
529 .buswidth = 32,
530 .num_links = 2,
531 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
532 };
533
534 static struct qcom_icc_node qnm_mnoc_hf = {
535 .name = "qnm_mnoc_hf",
536 .channels = 2,
537 .buswidth = 32,
538 .num_links = 2,
539 .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie },
540 };
541
542 static struct qcom_icc_node qnm_mnoc_sf = {
543 .name = "qnm_mnoc_sf",
544 .channels = 2,
545 .buswidth = 32,
546 .num_links = 3,
547 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
548 &qns_pcie },
549 };
550
551 static struct qcom_icc_node qnm_pcie = {
552 .name = "qnm_pcie",
553 .channels = 1,
554 .buswidth = 32,
555 .num_links = 2,
556 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
557 };
558
559 static struct qcom_icc_node qnm_snoc_gc = {
560 .name = "qnm_snoc_gc",
561 .channels = 1,
562 .buswidth = 8,
563 .num_links = 1,
564 .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc },
565 };
566
567 static struct qcom_icc_node qnm_snoc_sf = {
568 .name = "qnm_snoc_sf",
569 .channels = 1,
570 .buswidth = 16,
571 .num_links = 3,
572 .link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
573 &qns_pcie },
574 };
575
576 static struct qcom_icc_node qxm_dsp0 = {
577 .name = "qxm_dsp0",
578 .channels = 1,
579 .buswidth = 16,
580 .num_links = 1,
581 .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc },
582 };
583
584 static struct qcom_icc_node qxm_dsp1 = {
585 .name = "qxm_dsp1",
586 .channels = 1,
587 .buswidth = 16,
588 .num_links = 1,
589 .link_nodes = (struct qcom_icc_node *[]) { &qns_gp_dsp_sail_noc },
590 };
591
592 static struct qcom_icc_node qhm_config_noc = {
593 .name = "qhm_config_noc",
594 .channels = 1,
595 .buswidth = 4,
596 .num_links = 6,
597 .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_core, &qhs_lpass_lpi,
598 &qhs_lpass_mpu, &qhs_lpass_top,
599 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
600 };
601
602 static struct qcom_icc_node qxm_lpass_dsp = {
603 .name = "qxm_lpass_dsp",
604 .channels = 1,
605 .buswidth = 8,
606 .num_links = 4,
607 .link_nodes = (struct qcom_icc_node *[]) { &qhs_lpass_top, &qns_sysnoc,
608 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
609 };
610
611 static struct qcom_icc_node llcc_mc = {
612 .name = "llcc_mc",
613 .channels = 8,
614 .buswidth = 4,
615 .num_links = 1,
616 .link_nodes = (struct qcom_icc_node *[]) { &ebi },
617 };
618
619 static struct qcom_icc_node qnm_camnoc_hf = {
620 .name = "qnm_camnoc_hf",
621 .channels = 1,
622 .buswidth = 32,
623 .num_links = 1,
624 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
625 };
626
627 static struct qcom_icc_node qnm_camnoc_icp = {
628 .name = "qnm_camnoc_icp",
629 .channels = 1,
630 .buswidth = 8,
631 .num_links = 1,
632 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
633 };
634
635 static struct qcom_icc_node qnm_camnoc_sf = {
636 .name = "qnm_camnoc_sf",
637 .channels = 1,
638 .buswidth = 32,
639 .num_links = 1,
640 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
641 };
642
643 static struct qcom_icc_node qnm_mdp0_0 = {
644 .name = "qnm_mdp0_0",
645 .channels = 1,
646 .buswidth = 32,
647 .num_links = 1,
648 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
649 };
650
651 static struct qcom_icc_node qnm_mdp0_1 = {
652 .name = "qnm_mdp0_1",
653 .channels = 1,
654 .buswidth = 32,
655 .num_links = 1,
656 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
657 };
658
659 static struct qcom_icc_node qnm_mdp1_0 = {
660 .name = "qnm_mdp1_0",
661 .channels = 1,
662 .buswidth = 32,
663 .num_links = 1,
664 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
665 };
666
667 static struct qcom_icc_node qnm_mdp1_1 = {
668 .name = "qnm_mdp1_1",
669 .channels = 1,
670 .buswidth = 32,
671 .num_links = 1,
672 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
673 };
674
675 static struct qcom_icc_node qnm_mnoc_hf_cfg = {
676 .name = "qnm_mnoc_hf_cfg",
677 .channels = 1,
678 .buswidth = 4,
679 .num_links = 1,
680 .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_hf },
681 };
682
683 static struct qcom_icc_node qnm_mnoc_sf_cfg = {
684 .name = "qnm_mnoc_sf_cfg",
685 .channels = 1,
686 .buswidth = 4,
687 .num_links = 1,
688 .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc_sf },
689 };
690
691 static struct qcom_icc_node qnm_video0 = {
692 .name = "qnm_video0",
693 .channels = 1,
694 .buswidth = 32,
695 .num_links = 1,
696 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
697 };
698
699 static struct qcom_icc_node qnm_video1 = {
700 .name = "qnm_video1",
701 .channels = 1,
702 .buswidth = 32,
703 .num_links = 1,
704 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
705 };
706
707 static struct qcom_icc_node qnm_video_cvp = {
708 .name = "qnm_video_cvp",
709 .channels = 1,
710 .buswidth = 32,
711 .num_links = 1,
712 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
713 };
714
715 static struct qcom_icc_node qnm_video_v_cpu = {
716 .name = "qnm_video_v_cpu",
717 .channels = 1,
718 .buswidth = 8,
719 .num_links = 1,
720 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
721 };
722
723 static struct qcom_icc_node qhm_nsp_noc_config = {
724 .name = "qhm_nsp_noc_config",
725 .channels = 1,
726 .buswidth = 4,
727 .num_links = 1,
728 .link_nodes = (struct qcom_icc_node *[]) { &service_nsp_noc },
729 };
730
731 static struct qcom_icc_node qxm_nsp = {
732 .name = "qxm_nsp",
733 .channels = 2,
734 .buswidth = 32,
735 .num_links = 2,
736 .link_nodes = (struct qcom_icc_node *[]) { &qns_hcp, &qns_nsp_gemnoc },
737 };
738
739 static struct qcom_icc_node qhm_nspb_noc_config = {
740 .name = "qhm_nspb_noc_config",
741 .channels = 1,
742 .buswidth = 4,
743 .num_links = 1,
744 .link_nodes = (struct qcom_icc_node *[]) { &service_nspb_noc },
745 };
746
747 static struct qcom_icc_node qxm_nspb = {
748 .name = "qxm_nspb",
749 .channels = 2,
750 .buswidth = 32,
751 .num_links = 2,
752 .link_nodes = (struct qcom_icc_node *[]) { &qns_nspb_hcp, &qns_nspb_gemnoc },
753 };
754
755 static struct qcom_icc_node xm_pcie3_0 = {
756 .name = "xm_pcie3_0",
757 .channels = 1,
758 .buswidth = 16,
759 .num_links = 1,
760 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
761 };
762
763 static struct qcom_icc_node xm_pcie3_1 = {
764 .name = "xm_pcie3_1",
765 .channels = 1,
766 .buswidth = 32,
767 .num_links = 1,
768 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
769 };
770
771 static struct qcom_icc_node qhm_gic = {
772 .name = "qhm_gic",
773 .channels = 1,
774 .buswidth = 4,
775 .num_links = 1,
776 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
777 };
778
779 static struct qcom_icc_node qnm_aggre1_noc = {
780 .name = "qnm_aggre1_noc",
781 .channels = 1,
782 .buswidth = 32,
783 .num_links = 1,
784 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
785 };
786
787 static struct qcom_icc_node qnm_aggre2_noc = {
788 .name = "qnm_aggre2_noc",
789 .channels = 1,
790 .buswidth = 16,
791 .num_links = 1,
792 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
793 };
794
795 static struct qcom_icc_node qnm_lpass_noc = {
796 .name = "qnm_lpass_noc",
797 .channels = 1,
798 .buswidth = 16,
799 .num_links = 1,
800 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
801 };
802
803 static struct qcom_icc_node qnm_snoc_cfg = {
804 .name = "qnm_snoc_cfg",
805 .channels = 1,
806 .buswidth = 4,
807 .num_links = 1,
808 .link_nodes = (struct qcom_icc_node *[]) { &srvc_snoc },
809 };
810
811 static struct qcom_icc_node qxm_pimem = {
812 .name = "qxm_pimem",
813 .channels = 1,
814 .buswidth = 8,
815 .num_links = 1,
816 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
817 };
818
819 static struct qcom_icc_node xm_gic = {
820 .name = "xm_gic",
821 .channels = 1,
822 .buswidth = 8,
823 .num_links = 1,
824 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
825 };
826
827 static struct qcom_icc_node qns_a1noc_snoc = {
828 .name = "qns_a1noc_snoc",
829 .channels = 1,
830 .buswidth = 32,
831 .num_links = 1,
832 .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc },
833 };
834
835 static struct qcom_icc_node qns_a2noc_snoc = {
836 .name = "qns_a2noc_snoc",
837 .channels = 1,
838 .buswidth = 16,
839 .num_links = 1,
840 .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc },
841 };
842
843 static struct qcom_icc_node qup0_core_slave = {
844 .name = "qup0_core_slave",
845 .channels = 1,
846 .buswidth = 4,
847 };
848
849 static struct qcom_icc_node qup1_core_slave = {
850 .name = "qup1_core_slave",
851 .channels = 1,
852 .buswidth = 4,
853 };
854
855 static struct qcom_icc_node qup2_core_slave = {
856 .name = "qup2_core_slave",
857 .channels = 1,
858 .buswidth = 4,
859 };
860
861 static struct qcom_icc_node qup3_core_slave = {
862 .name = "qup3_core_slave",
863 .channels = 1,
864 .buswidth = 4,
865 };
866
867 static struct qcom_icc_node qhs_ahb2phy0 = {
868 .name = "qhs_ahb2phy0",
869 .channels = 1,
870 .buswidth = 4,
871 };
872
873 static struct qcom_icc_node qhs_ahb2phy1 = {
874 .name = "qhs_ahb2phy1",
875 .channels = 1,
876 .buswidth = 4,
877 };
878
879 static struct qcom_icc_node qhs_ahb2phy2 = {
880 .name = "qhs_ahb2phy2",
881 .channels = 1,
882 .buswidth = 4,
883 };
884
885 static struct qcom_icc_node qhs_ahb2phy3 = {
886 .name = "qhs_ahb2phy3",
887 .channels = 1,
888 .buswidth = 4,
889 };
890
891 static struct qcom_icc_node qhs_anoc_throttle_cfg = {
892 .name = "qhs_anoc_throttle_cfg",
893 .channels = 1,
894 .buswidth = 4,
895 };
896
897 static struct qcom_icc_node qhs_aoss = {
898 .name = "qhs_aoss",
899 .channels = 1,
900 .buswidth = 4,
901 };
902
903 static struct qcom_icc_node qhs_apss = {
904 .name = "qhs_apss",
905 .channels = 1,
906 .buswidth = 8,
907 };
908
909 static struct qcom_icc_node qhs_boot_rom = {
910 .name = "qhs_boot_rom",
911 .channels = 1,
912 .buswidth = 4,
913 };
914
915 static struct qcom_icc_node qhs_camera_cfg = {
916 .name = "qhs_camera_cfg",
917 .channels = 1,
918 .buswidth = 4,
919 };
920
921 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
922 .name = "qhs_camera_nrt_throttle_cfg",
923 .channels = 1,
924 .buswidth = 4,
925 };
926
927 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
928 .name = "qhs_camera_rt_throttle_cfg",
929 .channels = 1,
930 .buswidth = 4,
931 };
932
933 static struct qcom_icc_node qhs_clk_ctl = {
934 .name = "qhs_clk_ctl",
935 .channels = 1,
936 .buswidth = 4,
937 };
938
939 static struct qcom_icc_node qhs_compute0_cfg = {
940 .name = "qhs_compute0_cfg",
941 .channels = 1,
942 .buswidth = 4,
943 .num_links = 1,
944 .link_nodes = (struct qcom_icc_node *[]) { &qhm_nsp_noc_config },
945 };
946
947 static struct qcom_icc_node qhs_compute1_cfg = {
948 .name = "qhs_compute1_cfg",
949 .channels = 1,
950 .buswidth = 4,
951 .num_links = 1,
952 .link_nodes = (struct qcom_icc_node *[]) { &qhm_nspb_noc_config },
953 };
954
955 static struct qcom_icc_node qhs_cpr_cx = {
956 .name = "qhs_cpr_cx",
957 .channels = 1,
958 .buswidth = 4,
959 };
960
961 static struct qcom_icc_node qhs_cpr_mmcx = {
962 .name = "qhs_cpr_mmcx",
963 .channels = 1,
964 .buswidth = 4,
965 };
966
967 static struct qcom_icc_node qhs_cpr_mx = {
968 .name = "qhs_cpr_mx",
969 .channels = 1,
970 .buswidth = 4,
971 };
972
973 static struct qcom_icc_node qhs_cpr_nspcx = {
974 .name = "qhs_cpr_nspcx",
975 .channels = 1,
976 .buswidth = 4,
977 };
978
979 static struct qcom_icc_node qhs_crypto0_cfg = {
980 .name = "qhs_crypto0_cfg",
981 .channels = 1,
982 .buswidth = 4,
983 };
984
985 static struct qcom_icc_node qhs_cx_rdpm = {
986 .name = "qhs_cx_rdpm",
987 .channels = 1,
988 .buswidth = 4,
989 };
990
991 static struct qcom_icc_node qhs_display0_cfg = {
992 .name = "qhs_display0_cfg",
993 .channels = 1,
994 .buswidth = 4,
995 };
996
997 static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
998 .name = "qhs_display0_rt_throttle_cfg",
999 .channels = 1,
1000 .buswidth = 4,
1001 };
1002
1003 static struct qcom_icc_node qhs_display1_cfg = {
1004 .name = "qhs_display1_cfg",
1005 .channels = 1,
1006 .buswidth = 4,
1007 };
1008
1009 static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
1010 .name = "qhs_display1_rt_throttle_cfg",
1011 .channels = 1,
1012 .buswidth = 4,
1013 };
1014
1015 static struct qcom_icc_node qhs_emac0_cfg = {
1016 .name = "qhs_emac0_cfg",
1017 .channels = 1,
1018 .buswidth = 4,
1019 };
1020
1021 static struct qcom_icc_node qhs_emac1_cfg = {
1022 .name = "qhs_emac1_cfg",
1023 .channels = 1,
1024 .buswidth = 4,
1025 };
1026
1027 static struct qcom_icc_node qhs_gp_dsp0_cfg = {
1028 .name = "qhs_gp_dsp0_cfg",
1029 .channels = 1,
1030 .buswidth = 4,
1031 };
1032
1033 static struct qcom_icc_node qhs_gp_dsp1_cfg = {
1034 .name = "qhs_gp_dsp1_cfg",
1035 .channels = 1,
1036 .buswidth = 4,
1037 };
1038
1039 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
1040 .name = "qhs_gpdsp0_throttle_cfg",
1041 .channels = 1,
1042 .buswidth = 4,
1043 };
1044
1045 static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
1046 .name = "qhs_gpdsp1_throttle_cfg",
1047 .channels = 1,
1048 .buswidth = 4,
1049 };
1050
1051 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
1052 .name = "qhs_gpu_tcu_throttle_cfg",
1053 .channels = 1,
1054 .buswidth = 4,
1055 };
1056
1057 static struct qcom_icc_node qhs_gpuss_cfg = {
1058 .name = "qhs_gpuss_cfg",
1059 .channels = 1,
1060 .buswidth = 8,
1061 };
1062
1063 static struct qcom_icc_node qhs_hwkm = {
1064 .name = "qhs_hwkm",
1065 .channels = 1,
1066 .buswidth = 4,
1067 };
1068
1069 static struct qcom_icc_node qhs_imem_cfg = {
1070 .name = "qhs_imem_cfg",
1071 .channels = 1,
1072 .buswidth = 4,
1073 };
1074
1075 static struct qcom_icc_node qhs_ipa = {
1076 .name = "qhs_ipa",
1077 .channels = 1,
1078 .buswidth = 4,
1079 };
1080
1081 static struct qcom_icc_node qhs_ipc_router = {
1082 .name = "qhs_ipc_router",
1083 .channels = 1,
1084 .buswidth = 4,
1085 };
1086
1087 static struct qcom_icc_node qhs_lpass_cfg = {
1088 .name = "qhs_lpass_cfg",
1089 .channels = 1,
1090 .buswidth = 4,
1091 .num_links = 1,
1092 .link_nodes = (struct qcom_icc_node *[]) { &qhm_config_noc },
1093 };
1094
1095 static struct qcom_icc_node qhs_lpass_throttle_cfg = {
1096 .name = "qhs_lpass_throttle_cfg",
1097 .channels = 1,
1098 .buswidth = 4,
1099 };
1100
1101 static struct qcom_icc_node qhs_mx_rdpm = {
1102 .name = "qhs_mx_rdpm",
1103 .channels = 1,
1104 .buswidth = 4,
1105 };
1106
1107 static struct qcom_icc_node qhs_mxc_rdpm = {
1108 .name = "qhs_mxc_rdpm",
1109 .channels = 1,
1110 .buswidth = 4,
1111 };
1112
1113 static struct qcom_icc_node qhs_pcie0_cfg = {
1114 .name = "qhs_pcie0_cfg",
1115 .channels = 1,
1116 .buswidth = 4,
1117 };
1118
1119 static struct qcom_icc_node qhs_pcie1_cfg = {
1120 .name = "qhs_pcie1_cfg",
1121 .channels = 1,
1122 .buswidth = 4,
1123 };
1124
1125 static struct qcom_icc_node qhs_pcie_rsc_cfg = {
1126 .name = "qhs_pcie_rsc_cfg",
1127 .channels = 1,
1128 .buswidth = 4,
1129 };
1130
1131 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
1132 .name = "qhs_pcie_tcu_throttle_cfg",
1133 .channels = 1,
1134 .buswidth = 4,
1135 };
1136
1137 static struct qcom_icc_node qhs_pcie_throttle_cfg = {
1138 .name = "qhs_pcie_throttle_cfg",
1139 .channels = 1,
1140 .buswidth = 4,
1141 };
1142
1143 static struct qcom_icc_node qhs_pdm = {
1144 .name = "qhs_pdm",
1145 .channels = 1,
1146 .buswidth = 4,
1147 };
1148
1149 static struct qcom_icc_node qhs_pimem_cfg = {
1150 .name = "qhs_pimem_cfg",
1151 .channels = 1,
1152 .buswidth = 4,
1153 };
1154
1155 static struct qcom_icc_node qhs_pke_wrapper_cfg = {
1156 .name = "qhs_pke_wrapper_cfg",
1157 .channels = 1,
1158 .buswidth = 4,
1159 };
1160
1161 static struct qcom_icc_node qhs_qdss_cfg = {
1162 .name = "qhs_qdss_cfg",
1163 .channels = 1,
1164 .buswidth = 4,
1165 };
1166
1167 static struct qcom_icc_node qhs_qm_cfg = {
1168 .name = "qhs_qm_cfg",
1169 .channels = 1,
1170 .buswidth = 4,
1171 };
1172
1173 static struct qcom_icc_node qhs_qm_mpu_cfg = {
1174 .name = "qhs_qm_mpu_cfg",
1175 .channels = 1,
1176 .buswidth = 4,
1177 };
1178
1179 static struct qcom_icc_node qhs_qup0 = {
1180 .name = "qhs_qup0",
1181 .channels = 1,
1182 .buswidth = 4,
1183 };
1184
1185 static struct qcom_icc_node qhs_qup1 = {
1186 .name = "qhs_qup1",
1187 .channels = 1,
1188 .buswidth = 4,
1189 };
1190
1191 static struct qcom_icc_node qhs_qup2 = {
1192 .name = "qhs_qup2",
1193 .channels = 1,
1194 .buswidth = 4,
1195 };
1196
1197 static struct qcom_icc_node qhs_qup3 = {
1198 .name = "qhs_qup3",
1199 .channels = 1,
1200 .buswidth = 4,
1201 };
1202
1203 static struct qcom_icc_node qhs_sail_throttle_cfg = {
1204 .name = "qhs_sail_throttle_cfg",
1205 .channels = 1,
1206 .buswidth = 4,
1207 };
1208
1209 static struct qcom_icc_node qhs_sdc1 = {
1210 .name = "qhs_sdc1",
1211 .channels = 1,
1212 .buswidth = 4,
1213 };
1214
1215 static struct qcom_icc_node qhs_security = {
1216 .name = "qhs_security",
1217 .channels = 1,
1218 .buswidth = 4,
1219 };
1220
1221 static struct qcom_icc_node qhs_snoc_throttle_cfg = {
1222 .name = "qhs_snoc_throttle_cfg",
1223 .channels = 1,
1224 .buswidth = 4,
1225 };
1226
1227 static struct qcom_icc_node qhs_tcsr = {
1228 .name = "qhs_tcsr",
1229 .channels = 1,
1230 .buswidth = 4,
1231 };
1232
1233 static struct qcom_icc_node qhs_tlmm = {
1234 .name = "qhs_tlmm",
1235 .channels = 1,
1236 .buswidth = 4,
1237 };
1238
1239 static struct qcom_icc_node qhs_tsc_cfg = {
1240 .name = "qhs_tsc_cfg",
1241 .channels = 1,
1242 .buswidth = 4,
1243 };
1244
1245 static struct qcom_icc_node qhs_ufs_card_cfg = {
1246 .name = "qhs_ufs_card_cfg",
1247 .channels = 1,
1248 .buswidth = 4,
1249 };
1250
1251 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1252 .name = "qhs_ufs_mem_cfg",
1253 .channels = 1,
1254 .buswidth = 4,
1255 };
1256
1257 static struct qcom_icc_node qhs_usb2_0 = {
1258 .name = "qhs_usb2_0",
1259 .channels = 1,
1260 .buswidth = 4,
1261 };
1262
1263 static struct qcom_icc_node qhs_usb3_0 = {
1264 .name = "qhs_usb3_0",
1265 .channels = 1,
1266 .buswidth = 4,
1267 };
1268
1269 static struct qcom_icc_node qhs_usb3_1 = {
1270 .name = "qhs_usb3_1",
1271 .channels = 1,
1272 .buswidth = 4,
1273 };
1274
1275 static struct qcom_icc_node qhs_venus_cfg = {
1276 .name = "qhs_venus_cfg",
1277 .channels = 1,
1278 .buswidth = 4,
1279 };
1280
1281 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1282 .name = "qhs_venus_cvp_throttle_cfg",
1283 .channels = 1,
1284 .buswidth = 4,
1285 };
1286
1287 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
1288 .name = "qhs_venus_v_cpu_throttle_cfg",
1289 .channels = 1,
1290 .buswidth = 4,
1291 };
1292
1293 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
1294 .name = "qhs_venus_vcodec_throttle_cfg",
1295 .channels = 1,
1296 .buswidth = 4,
1297 };
1298
1299 static struct qcom_icc_node qns_ddrss_cfg = {
1300 .name = "qns_ddrss_cfg",
1301 .channels = 1,
1302 .buswidth = 4,
1303 .num_links = 1,
1304 .link_nodes = (struct qcom_icc_node *[]) { &qnm_cnoc_dc_noc },
1305 };
1306
1307 static struct qcom_icc_node qns_gpdsp_noc_cfg = {
1308 .name = "qns_gpdsp_noc_cfg",
1309 .channels = 1,
1310 .buswidth = 4,
1311 };
1312
1313 static struct qcom_icc_node qns_mnoc_hf_cfg = {
1314 .name = "qns_mnoc_hf_cfg",
1315 .channels = 1,
1316 .buswidth = 4,
1317 .num_links = 1,
1318 .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf_cfg },
1319 };
1320
1321 static struct qcom_icc_node qns_mnoc_sf_cfg = {
1322 .name = "qns_mnoc_sf_cfg",
1323 .channels = 1,
1324 .buswidth = 4,
1325 .num_links = 1,
1326 .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf_cfg },
1327 };
1328
1329 static struct qcom_icc_node qns_pcie_anoc_cfg = {
1330 .name = "qns_pcie_anoc_cfg",
1331 .channels = 1,
1332 .buswidth = 4,
1333 };
1334
1335 static struct qcom_icc_node qns_snoc_cfg = {
1336 .name = "qns_snoc_cfg",
1337 .channels = 1,
1338 .buswidth = 4,
1339 .num_links = 1,
1340 .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_cfg },
1341 };
1342
1343 static struct qcom_icc_node qxs_boot_imem = {
1344 .name = "qxs_boot_imem",
1345 .channels = 1,
1346 .buswidth = 16,
1347 };
1348
1349 static struct qcom_icc_node qxs_imem = {
1350 .name = "qxs_imem",
1351 .channels = 1,
1352 .buswidth = 8,
1353 };
1354
1355 static struct qcom_icc_node qxs_pimem = {
1356 .name = "qxs_pimem",
1357 .channels = 1,
1358 .buswidth = 8,
1359 };
1360
1361 static struct qcom_icc_node xs_pcie_0 = {
1362 .name = "xs_pcie_0",
1363 .channels = 1,
1364 .buswidth = 16,
1365 };
1366
1367 static struct qcom_icc_node xs_pcie_1 = {
1368 .name = "xs_pcie_1",
1369 .channels = 1,
1370 .buswidth = 32,
1371 };
1372
1373 static struct qcom_icc_node xs_qdss_stm = {
1374 .name = "xs_qdss_stm",
1375 .channels = 1,
1376 .buswidth = 4,
1377 };
1378
1379 static struct qcom_icc_node xs_sys_tcu_cfg = {
1380 .name = "xs_sys_tcu_cfg",
1381 .channels = 1,
1382 .buswidth = 8,
1383 };
1384
1385 static struct qcom_icc_node qhs_llcc = {
1386 .name = "qhs_llcc",
1387 .channels = 1,
1388 .buswidth = 4,
1389 };
1390
1391 static struct qcom_icc_node qns_gemnoc = {
1392 .name = "qns_gemnoc",
1393 .channels = 1,
1394 .buswidth = 4,
1395 .num_links = 1,
1396 .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cfg },
1397 };
1398
1399 static struct qcom_icc_node qns_gem_noc_cnoc = {
1400 .name = "qns_gem_noc_cnoc",
1401 .channels = 1,
1402 .buswidth = 16,
1403 .num_links = 1,
1404 .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_cnoc },
1405 };
1406
1407 static struct qcom_icc_node qns_llcc = {
1408 .name = "qns_llcc",
1409 .channels = 6,
1410 .buswidth = 16,
1411 .num_links = 1,
1412 .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc },
1413 };
1414
1415 static struct qcom_icc_node qns_pcie = {
1416 .name = "qns_pcie",
1417 .channels = 1,
1418 .buswidth = 16,
1419 .num_links = 1,
1420 .link_nodes = (struct qcom_icc_node *[]) { &qnm_gemnoc_pcie },
1421 };
1422
1423 static struct qcom_icc_node srvc_even_gemnoc = {
1424 .name = "srvc_even_gemnoc",
1425 .channels = 1,
1426 .buswidth = 4,
1427 };
1428
1429 static struct qcom_icc_node srvc_odd_gemnoc = {
1430 .name = "srvc_odd_gemnoc",
1431 .channels = 1,
1432 .buswidth = 4,
1433 };
1434
1435 static struct qcom_icc_node srvc_sys_gemnoc = {
1436 .name = "srvc_sys_gemnoc",
1437 .channels = 1,
1438 .buswidth = 4,
1439 };
1440
1441 static struct qcom_icc_node srvc_sys_gemnoc_2 = {
1442 .name = "srvc_sys_gemnoc_2",
1443 .channels = 1,
1444 .buswidth = 4,
1445 };
1446
1447 static struct qcom_icc_node qns_gp_dsp_sail_noc = {
1448 .name = "qns_gp_dsp_sail_noc",
1449 .channels = 1,
1450 .buswidth = 16,
1451 .num_links = 1,
1452 .link_nodes = (struct qcom_icc_node *[]) { &qnm_gpdsp_sail },
1453 };
1454
1455 static struct qcom_icc_node qhs_lpass_core = {
1456 .name = "qhs_lpass_core",
1457 .channels = 1,
1458 .buswidth = 4,
1459 };
1460
1461 static struct qcom_icc_node qhs_lpass_lpi = {
1462 .name = "qhs_lpass_lpi",
1463 .channels = 1,
1464 .buswidth = 4,
1465 };
1466
1467 static struct qcom_icc_node qhs_lpass_mpu = {
1468 .name = "qhs_lpass_mpu",
1469 .channels = 1,
1470 .buswidth = 4,
1471 };
1472
1473 static struct qcom_icc_node qhs_lpass_top = {
1474 .name = "qhs_lpass_top",
1475 .channels = 1,
1476 .buswidth = 4,
1477 };
1478
1479 static struct qcom_icc_node qns_sysnoc = {
1480 .name = "qns_sysnoc",
1481 .channels = 1,
1482 .buswidth = 16,
1483 .num_links = 1,
1484 .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_noc },
1485 };
1486
1487 static struct qcom_icc_node srvc_niu_aml_noc = {
1488 .name = "srvc_niu_aml_noc",
1489 .channels = 1,
1490 .buswidth = 4,
1491 };
1492
1493 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1494 .name = "srvc_niu_lpass_agnoc",
1495 .channels = 1,
1496 .buswidth = 4,
1497 };
1498
1499 static struct qcom_icc_node ebi = {
1500 .name = "ebi",
1501 .channels = 8,
1502 .buswidth = 4,
1503 };
1504
1505 static struct qcom_icc_node qns_mem_noc_hf = {
1506 .name = "qns_mem_noc_hf",
1507 .channels = 2,
1508 .buswidth = 32,
1509 .num_links = 1,
1510 .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf },
1511 };
1512
1513 static struct qcom_icc_node qns_mem_noc_sf = {
1514 .name = "qns_mem_noc_sf",
1515 .channels = 2,
1516 .buswidth = 32,
1517 .num_links = 1,
1518 .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf },
1519 };
1520
1521 static struct qcom_icc_node srvc_mnoc_hf = {
1522 .name = "srvc_mnoc_hf",
1523 .channels = 1,
1524 .buswidth = 4,
1525 };
1526
1527 static struct qcom_icc_node srvc_mnoc_sf = {
1528 .name = "srvc_mnoc_sf",
1529 .channels = 1,
1530 .buswidth = 4,
1531 };
1532
1533 static struct qcom_icc_node qns_hcp = {
1534 .name = "qns_hcp",
1535 .channels = 2,
1536 .buswidth = 32,
1537 };
1538
1539 static struct qcom_icc_node qns_nsp_gemnoc = {
1540 .name = "qns_nsp_gemnoc",
1541 .channels = 2,
1542 .buswidth = 32,
1543 .num_links = 1,
1544 .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc0 },
1545 };
1546
1547 static struct qcom_icc_node service_nsp_noc = {
1548 .name = "service_nsp_noc",
1549 .channels = 1,
1550 .buswidth = 4,
1551 };
1552
1553 static struct qcom_icc_node qns_nspb_gemnoc = {
1554 .name = "qns_nspb_gemnoc",
1555 .channels = 2,
1556 .buswidth = 32,
1557 .num_links = 1,
1558 .link_nodes = (struct qcom_icc_node *[]) { &qnm_cmpnoc1 },
1559 };
1560
1561 static struct qcom_icc_node qns_nspb_hcp = {
1562 .name = "qns_nspb_hcp",
1563 .channels = 2,
1564 .buswidth = 32,
1565 };
1566
1567 static struct qcom_icc_node service_nspb_noc = {
1568 .name = "service_nspb_noc",
1569 .channels = 1,
1570 .buswidth = 4,
1571 };
1572
1573 static struct qcom_icc_node qns_pcie_mem_noc = {
1574 .name = "qns_pcie_mem_noc",
1575 .channels = 1,
1576 .buswidth = 32,
1577 .num_links = 1,
1578 .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie },
1579 };
1580
1581 static struct qcom_icc_node qns_gemnoc_gc = {
1582 .name = "qns_gemnoc_gc",
1583 .channels = 1,
1584 .buswidth = 8,
1585 .num_links = 1,
1586 .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_gc },
1587 };
1588
1589 static struct qcom_icc_node qns_gemnoc_sf = {
1590 .name = "qns_gemnoc_sf",
1591 .channels = 1,
1592 .buswidth = 16,
1593 .num_links = 1,
1594 .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf },
1595 };
1596
1597 static struct qcom_icc_node srvc_snoc = {
1598 .name = "srvc_snoc",
1599 .channels = 1,
1600 .buswidth = 4,
1601 };
1602
1603 static struct qcom_icc_bcm bcm_acv = {
1604 .name = "ACV",
1605 .enable_mask = 0x8,
1606 .num_nodes = 1,
1607 .nodes = { &ebi },
1608 };
1609
1610 static struct qcom_icc_bcm bcm_ce0 = {
1611 .name = "CE0",
1612 .num_nodes = 2,
1613 .nodes = { &qxm_crypto_0, &qxm_crypto_1 },
1614 };
1615
1616 static struct qcom_icc_bcm bcm_cn0 = {
1617 .name = "CN0",
1618 .keepalive = true,
1619 .num_nodes = 2,
1620 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1621 };
1622
1623 static struct qcom_icc_bcm bcm_cn1 = {
1624 .name = "CN1",
1625 .num_nodes = 76,
1626 .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
1627 &qhs_ahb2phy2, &qhs_ahb2phy3,
1628 &qhs_anoc_throttle_cfg, &qhs_aoss,
1629 &qhs_apss, &qhs_boot_rom,
1630 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
1631 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
1632 &qhs_compute0_cfg, &qhs_compute1_cfg,
1633 &qhs_cpr_cx, &qhs_cpr_mmcx,
1634 &qhs_cpr_mx, &qhs_cpr_nspcx,
1635 &qhs_crypto0_cfg, &qhs_cx_rdpm,
1636 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
1637 &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
1638 &qhs_emac0_cfg, &qhs_emac1_cfg,
1639 &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
1640 &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
1641 &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
1642 &qhs_hwkm, &qhs_imem_cfg,
1643 &qhs_ipa, &qhs_ipc_router,
1644 &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
1645 &qhs_mx_rdpm, &qhs_mxc_rdpm,
1646 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1647 &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
1648 &qhs_pcie_throttle_cfg, &qhs_pdm,
1649 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
1650 &qhs_qdss_cfg, &qhs_qm_cfg,
1651 &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
1652 &qhs_sdc1, &qhs_security,
1653 &qhs_snoc_throttle_cfg, &qhs_tcsr,
1654 &qhs_tlmm, &qhs_tsc_cfg,
1655 &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
1656 &qhs_usb2_0, &qhs_usb3_0,
1657 &qhs_usb3_1, &qhs_venus_cfg,
1658 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
1659 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
1660 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
1661 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
1662 &qns_snoc_cfg, &qxs_boot_imem,
1663 &qxs_imem, &xs_sys_tcu_cfg },
1664 };
1665
1666 static struct qcom_icc_bcm bcm_cn2 = {
1667 .name = "CN2",
1668 .num_nodes = 4,
1669 .nodes = { &qhs_qup0, &qhs_qup1,
1670 &qhs_qup2, &qhs_qup3 },
1671 };
1672
1673 static struct qcom_icc_bcm bcm_cn3 = {
1674 .name = "CN3",
1675 .num_nodes = 2,
1676 .nodes = { &xs_pcie_0, &xs_pcie_1 },
1677 };
1678
1679 static struct qcom_icc_bcm bcm_gna0 = {
1680 .name = "GNA0",
1681 .num_nodes = 1,
1682 .nodes = { &qxm_dsp0 },
1683 };
1684
1685 static struct qcom_icc_bcm bcm_gnb0 = {
1686 .name = "GNB0",
1687 .num_nodes = 1,
1688 .nodes = { &qxm_dsp1 },
1689 };
1690
1691 static struct qcom_icc_bcm bcm_mc0 = {
1692 .name = "MC0",
1693 .keepalive = true,
1694 .num_nodes = 1,
1695 .nodes = { &ebi },
1696 };
1697
1698 static struct qcom_icc_bcm bcm_mm0 = {
1699 .name = "MM0",
1700 .keepalive = true,
1701 .num_nodes = 5,
1702 .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
1703 &qnm_mdp0_1, &qnm_mdp1_0,
1704 &qns_mem_noc_hf },
1705 };
1706
1707 static struct qcom_icc_bcm bcm_mm1 = {
1708 .name = "MM1",
1709 .num_nodes = 7,
1710 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
1711 &qnm_video0, &qnm_video1,
1712 &qnm_video_cvp, &qnm_video_v_cpu,
1713 &qns_mem_noc_sf },
1714 };
1715
1716 static struct qcom_icc_bcm bcm_nsa0 = {
1717 .name = "NSA0",
1718 .num_nodes = 2,
1719 .nodes = { &qns_hcp, &qns_nsp_gemnoc },
1720 };
1721
1722 static struct qcom_icc_bcm bcm_nsa1 = {
1723 .name = "NSA1",
1724 .num_nodes = 1,
1725 .nodes = { &qxm_nsp },
1726 };
1727
1728 static struct qcom_icc_bcm bcm_nsb0 = {
1729 .name = "NSB0",
1730 .num_nodes = 2,
1731 .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
1732 };
1733
1734 static struct qcom_icc_bcm bcm_nsb1 = {
1735 .name = "NSB1",
1736 .num_nodes = 1,
1737 .nodes = { &qxm_nspb },
1738 };
1739
1740 static struct qcom_icc_bcm bcm_pci0 = {
1741 .name = "PCI0",
1742 .num_nodes = 1,
1743 .nodes = { &qns_pcie_mem_noc },
1744 };
1745
1746 static struct qcom_icc_bcm bcm_qup0 = {
1747 .name = "QUP0",
1748 .vote_scale = 1,
1749 .num_nodes = 1,
1750 .nodes = { &qup0_core_slave },
1751 };
1752
1753 static struct qcom_icc_bcm bcm_qup1 = {
1754 .name = "QUP1",
1755 .vote_scale = 1,
1756 .num_nodes = 1,
1757 .nodes = { &qup1_core_slave },
1758 };
1759
1760 static struct qcom_icc_bcm bcm_qup2 = {
1761 .name = "QUP2",
1762 .vote_scale = 1,
1763 .num_nodes = 2,
1764 .nodes = { &qup2_core_slave, &qup3_core_slave },
1765 };
1766
1767 static struct qcom_icc_bcm bcm_sh0 = {
1768 .name = "SH0",
1769 .keepalive = true,
1770 .num_nodes = 1,
1771 .nodes = { &qns_llcc },
1772 };
1773
1774 static struct qcom_icc_bcm bcm_sh2 = {
1775 .name = "SH2",
1776 .num_nodes = 1,
1777 .nodes = { &chm_apps },
1778 };
1779
1780 static struct qcom_icc_bcm bcm_sn0 = {
1781 .name = "SN0",
1782 .keepalive = true,
1783 .num_nodes = 1,
1784 .nodes = { &qns_gemnoc_sf },
1785 };
1786
1787 static struct qcom_icc_bcm bcm_sn1 = {
1788 .name = "SN1",
1789 .num_nodes = 1,
1790 .nodes = { &qns_gemnoc_gc },
1791 };
1792
1793 static struct qcom_icc_bcm bcm_sn2 = {
1794 .name = "SN2",
1795 .num_nodes = 1,
1796 .nodes = { &qxs_pimem },
1797 };
1798
1799 static struct qcom_icc_bcm bcm_sn3 = {
1800 .name = "SN3",
1801 .num_nodes = 2,
1802 .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
1803 };
1804
1805 static struct qcom_icc_bcm bcm_sn4 = {
1806 .name = "SN4",
1807 .num_nodes = 2,
1808 .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
1809 };
1810
1811 static struct qcom_icc_bcm bcm_sn9 = {
1812 .name = "SN9",
1813 .num_nodes = 2,
1814 .nodes = { &qns_sysnoc, &qnm_lpass_noc },
1815 };
1816
1817 static struct qcom_icc_bcm bcm_sn10 = {
1818 .name = "SN10",
1819 .num_nodes = 1,
1820 .nodes = { &xs_qdss_stm },
1821 };
1822
1823 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1824 &bcm_sn3,
1825 };
1826
1827 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1828 [MASTER_QUP_3] = &qxm_qup3,
1829 [MASTER_EMAC] = &xm_emac_0,
1830 [MASTER_EMAC_1] = &xm_emac_1,
1831 [MASTER_SDC] = &xm_sdc1,
1832 [MASTER_UFS_MEM] = &xm_ufs_mem,
1833 [MASTER_USB2] = &xm_usb2_2,
1834 [MASTER_USB3_0] = &xm_usb3_0,
1835 [MASTER_USB3_1] = &xm_usb3_1,
1836 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1837 };
1838
1839 static const struct qcom_icc_desc sa8775p_aggre1_noc = {
1840 .nodes = aggre1_noc_nodes,
1841 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1842 .bcms = aggre1_noc_bcms,
1843 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1844 .alloc_dyn_id = true,
1845 };
1846
1847 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1848 &bcm_ce0,
1849 &bcm_sn4,
1850 };
1851
1852 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1853 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1854 [MASTER_QUP_0] = &qhm_qup0,
1855 [MASTER_QUP_1] = &qhm_qup1,
1856 [MASTER_QUP_2] = &qhm_qup2,
1857 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1858 [MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
1859 [MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
1860 [MASTER_IPA] = &qxm_ipa,
1861 [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
1862 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1863 [MASTER_UFS_CARD] = &xm_ufs_card,
1864 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1865 };
1866
1867 static const struct qcom_icc_desc sa8775p_aggre2_noc = {
1868 .nodes = aggre2_noc_nodes,
1869 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1870 .bcms = aggre2_noc_bcms,
1871 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1872 .alloc_dyn_id = true,
1873 };
1874
1875 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1876 &bcm_qup0,
1877 &bcm_qup1,
1878 &bcm_qup2,
1879 };
1880
1881 static struct qcom_icc_node * const clk_virt_nodes[] = {
1882 [MASTER_QUP_CORE_0] = &qup0_core_master,
1883 [MASTER_QUP_CORE_1] = &qup1_core_master,
1884 [MASTER_QUP_CORE_2] = &qup2_core_master,
1885 [MASTER_QUP_CORE_3] = &qup3_core_master,
1886 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1887 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1888 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1889 [SLAVE_QUP_CORE_3] = &qup3_core_slave,
1890 };
1891
1892 static const struct qcom_icc_desc sa8775p_clk_virt = {
1893 .nodes = clk_virt_nodes,
1894 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1895 .bcms = clk_virt_bcms,
1896 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1897 .alloc_dyn_id = true,
1898 };
1899
1900 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1901 &bcm_cn0,
1902 &bcm_cn1,
1903 &bcm_cn2,
1904 &bcm_cn3,
1905 &bcm_sn2,
1906 &bcm_sn10,
1907 };
1908
1909 static struct qcom_icc_node * const config_noc_nodes[] = {
1910 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1911 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1912 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
1913 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
1914 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
1915 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
1916 [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
1917 [SLAVE_AOSS] = &qhs_aoss,
1918 [SLAVE_APPSS] = &qhs_apss,
1919 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
1920 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1921 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
1922 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1923 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1924 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
1925 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
1926 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1927 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1928 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1929 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1930 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1931 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1932 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
1933 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
1934 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
1935 [SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg,
1936 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
1937 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
1938 [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
1939 [SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg,
1940 [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
1941 [SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg,
1942 [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
1943 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1944 [SLAVE_HWKM] = &qhs_hwkm,
1945 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1946 [SLAVE_IPA_CFG] = &qhs_ipa,
1947 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1948 [SLAVE_LPASS] = &qhs_lpass_cfg,
1949 [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
1950 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1951 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
1952 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1953 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1954 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
1955 [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
1956 [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
1957 [SLAVE_PDM] = &qhs_pdm,
1958 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1959 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
1960 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1961 [SLAVE_QM_CFG] = &qhs_qm_cfg,
1962 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
1963 [SLAVE_QUP_0] = &qhs_qup0,
1964 [SLAVE_QUP_1] = &qhs_qup1,
1965 [SLAVE_QUP_2] = &qhs_qup2,
1966 [SLAVE_QUP_3] = &qhs_qup3,
1967 [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
1968 [SLAVE_SDC1] = &qhs_sdc1,
1969 [SLAVE_SECURITY] = &qhs_security,
1970 [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
1971 [SLAVE_TCSR] = &qhs_tcsr,
1972 [SLAVE_TLMM] = &qhs_tlmm,
1973 [SLAVE_TSC_CFG] = &qhs_tsc_cfg,
1974 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
1975 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1976 [SLAVE_USB2] = &qhs_usb2_0,
1977 [SLAVE_USB3_0] = &qhs_usb3_0,
1978 [SLAVE_USB3_1] = &qhs_usb3_1,
1979 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1980 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
1981 [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
1982 [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
1983 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1984 [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
1985 [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
1986 [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
1987 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
1988 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1989 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1990 [SLAVE_IMEM] = &qxs_imem,
1991 [SLAVE_PIMEM] = &qxs_pimem,
1992 [SLAVE_PCIE_0] = &xs_pcie_0,
1993 [SLAVE_PCIE_1] = &xs_pcie_1,
1994 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1995 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1996 };
1997
1998 static const struct qcom_icc_desc sa8775p_config_noc = {
1999 .nodes = config_noc_nodes,
2000 .num_nodes = ARRAY_SIZE(config_noc_nodes),
2001 .bcms = config_noc_bcms,
2002 .num_bcms = ARRAY_SIZE(config_noc_bcms),
2003 .alloc_dyn_id = true,
2004 };
2005
2006 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
2007 };
2008
2009 static struct qcom_icc_node * const dc_noc_nodes[] = {
2010 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2011 [SLAVE_LLCC_CFG] = &qhs_llcc,
2012 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
2013 };
2014
2015 static const struct qcom_icc_desc sa8775p_dc_noc = {
2016 .nodes = dc_noc_nodes,
2017 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
2018 .bcms = dc_noc_bcms,
2019 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
2020 .alloc_dyn_id = true,
2021 };
2022
2023 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
2024 &bcm_sh0,
2025 &bcm_sh2,
2026 };
2027
2028 static struct qcom_icc_node * const gem_noc_nodes[] = {
2029 [MASTER_GPU_TCU] = &alm_gpu_tcu,
2030 [MASTER_PCIE_TCU] = &alm_pcie_tcu,
2031 [MASTER_SYS_TCU] = &alm_sys_tcu,
2032 [MASTER_APPSS_PROC] = &chm_apps,
2033 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
2034 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
2035 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
2036 [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
2037 [MASTER_GFX3D] = &qnm_gpu,
2038 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
2039 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
2040 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
2041 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
2042 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
2043 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
2044 [SLAVE_LLCC] = &qns_llcc,
2045 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
2046 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
2047 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
2048 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
2049 [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
2050 };
2051
2052 static const struct qcom_icc_desc sa8775p_gem_noc = {
2053 .nodes = gem_noc_nodes,
2054 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
2055 .bcms = gem_noc_bcms,
2056 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
2057 .alloc_dyn_id = true,
2058 };
2059
2060 static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
2061 &bcm_gna0,
2062 &bcm_gnb0,
2063 };
2064
2065 static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
2066 [MASTER_DSP0] = &qxm_dsp0,
2067 [MASTER_DSP1] = &qxm_dsp1,
2068 [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
2069 };
2070
2071 static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
2072 .nodes = gpdsp_anoc_nodes,
2073 .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
2074 .bcms = gpdsp_anoc_bcms,
2075 .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
2076 .alloc_dyn_id = true,
2077 };
2078
2079 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
2080 &bcm_sn9,
2081 };
2082
2083 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2084 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2085 [MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2086 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
2087 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
2088 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
2089 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
2090 [SLAVE_LPASS_SNOC] = &qns_sysnoc,
2091 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
2092 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
2093 };
2094
2095 static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
2096 .nodes = lpass_ag_noc_nodes,
2097 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2098 .bcms = lpass_ag_noc_bcms,
2099 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2100 .alloc_dyn_id = true,
2101 };
2102
2103 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2104 &bcm_acv,
2105 &bcm_mc0,
2106 };
2107
2108 static struct qcom_icc_node * const mc_virt_nodes[] = {
2109 [MASTER_LLCC] = &llcc_mc,
2110 [SLAVE_EBI1] = &ebi,
2111 };
2112
2113 static const struct qcom_icc_desc sa8775p_mc_virt = {
2114 .nodes = mc_virt_nodes,
2115 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
2116 .bcms = mc_virt_bcms,
2117 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
2118 .alloc_dyn_id = true,
2119 };
2120
2121 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2122 &bcm_mm0,
2123 &bcm_mm1,
2124 };
2125
2126 static struct qcom_icc_node * const mmss_noc_nodes[] = {
2127 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2128 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2129 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2130 [MASTER_MDP0] = &qnm_mdp0_0,
2131 [MASTER_MDP1] = &qnm_mdp0_1,
2132 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
2133 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
2134 [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
2135 [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
2136 [MASTER_VIDEO_P0] = &qnm_video0,
2137 [MASTER_VIDEO_P1] = &qnm_video1,
2138 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
2139 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2140 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2141 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2142 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
2143 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
2144 };
2145
2146 static const struct qcom_icc_desc sa8775p_mmss_noc = {
2147 .nodes = mmss_noc_nodes,
2148 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2149 .bcms = mmss_noc_bcms,
2150 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2151 .alloc_dyn_id = true,
2152 };
2153
2154 static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
2155 &bcm_nsa0,
2156 &bcm_nsa1,
2157 };
2158
2159 static struct qcom_icc_node * const nspa_noc_nodes[] = {
2160 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2161 [MASTER_CDSP_PROC] = &qxm_nsp,
2162 [SLAVE_HCP_A] = &qns_hcp,
2163 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2164 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2165 };
2166
2167 static const struct qcom_icc_desc sa8775p_nspa_noc = {
2168 .nodes = nspa_noc_nodes,
2169 .num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2170 .bcms = nspa_noc_bcms,
2171 .num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2172 .alloc_dyn_id = true,
2173 };
2174
2175 static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
2176 &bcm_nsb0,
2177 &bcm_nsb1,
2178 };
2179
2180 static struct qcom_icc_node * const nspb_noc_nodes[] = {
2181 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
2182 [MASTER_CDSP_PROC_B] = &qxm_nspb,
2183 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
2184 [SLAVE_HCP_B] = &qns_nspb_hcp,
2185 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
2186 };
2187
2188 static const struct qcom_icc_desc sa8775p_nspb_noc = {
2189 .nodes = nspb_noc_nodes,
2190 .num_nodes = ARRAY_SIZE(nspb_noc_nodes),
2191 .bcms = nspb_noc_bcms,
2192 .num_bcms = ARRAY_SIZE(nspb_noc_bcms),
2193 .alloc_dyn_id = true,
2194 };
2195
2196 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
2197 &bcm_pci0,
2198 };
2199
2200 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
2201 [MASTER_PCIE_0] = &xm_pcie3_0,
2202 [MASTER_PCIE_1] = &xm_pcie3_1,
2203 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2204 };
2205
2206 static const struct qcom_icc_desc sa8775p_pcie_anoc = {
2207 .nodes = pcie_anoc_nodes,
2208 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2209 .bcms = pcie_anoc_bcms,
2210 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2211 .alloc_dyn_id = true,
2212 };
2213
2214 static struct qcom_icc_bcm * const system_noc_bcms[] = {
2215 &bcm_sn0,
2216 &bcm_sn1,
2217 &bcm_sn3,
2218 &bcm_sn4,
2219 &bcm_sn9,
2220 };
2221
2222 static struct qcom_icc_node * const system_noc_nodes[] = {
2223 [MASTER_GIC_AHB] = &qhm_gic,
2224 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2225 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2226 [MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2227 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2228 [MASTER_PIMEM] = &qxm_pimem,
2229 [MASTER_GIC] = &xm_gic,
2230 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2231 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2232 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
2233 };
2234
2235 static const struct qcom_icc_desc sa8775p_system_noc = {
2236 .nodes = system_noc_nodes,
2237 .num_nodes = ARRAY_SIZE(system_noc_nodes),
2238 .bcms = system_noc_bcms,
2239 .num_bcms = ARRAY_SIZE(system_noc_bcms),
2240 .alloc_dyn_id = true,
2241 };
2242
2243 static const struct of_device_id qnoc_of_match[] = {
2244 { .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, },
2245 { .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, },
2246 { .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, },
2247 { .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, },
2248 { .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, },
2249 { .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, },
2250 { .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, },
2251 { .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, },
2252 { .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, },
2253 { .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, },
2254 { .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, },
2255 { .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, },
2256 { .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, },
2257 { .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, },
2258 { }
2259 };
2260 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2261
2262 static struct platform_driver qnoc_driver = {
2263 .probe = qcom_icc_rpmh_probe,
2264 .remove = qcom_icc_rpmh_remove,
2265 .driver = {
2266 .name = "qnoc-sa8775p",
2267 .of_match_table = qnoc_of_match,
2268 .sync_state = icc_sync_state,
2269 },
2270 };
2271
qnoc_driver_init(void)2272 static int __init qnoc_driver_init(void)
2273 {
2274 return platform_driver_register(&qnoc_driver);
2275 }
2276 core_initcall(qnoc_driver_init);
2277
qnoc_driver_exit(void)2278 static void __exit qnoc_driver_exit(void)
2279 {
2280 platform_driver_unregister(&qnoc_driver);
2281 }
2282 module_exit(qnoc_driver_exit);
2283
2284 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver");
2285 MODULE_LICENSE("GPL");
2286