1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * All rights reserved.
6 *
7 * Based on OMAP3 INTC code by Ben Gray
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 #include "opt_platform.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/ktr.h>
39 #include <sys/module.h>
40 #include <sys/proc.h>
41 #include <sys/rman.h>
42 #include <machine/bus.h>
43 #include <machine/intr.h>
44
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48
49 #include "pic_if.h"
50
51 #define INTC_PENDING_BASIC 0x00
52 #define INTC_PENDING_BANK1 0x04
53 #define INTC_PENDING_BANK2 0x08
54 #define INTC_FIQ_CONTROL 0x0C
55 #define INTC_ENABLE_BANK1 0x10
56 #define INTC_ENABLE_BANK2 0x14
57 #define INTC_ENABLE_BASIC 0x18
58 #define INTC_DISABLE_BANK1 0x1C
59 #define INTC_DISABLE_BANK2 0x20
60 #define INTC_DISABLE_BASIC 0x24
61
62 #define INTC_PENDING_BASIC_ARM 0x0000FF
63 #define INTC_PENDING_BASIC_GPU1_PEND 0x000100
64 #define INTC_PENDING_BASIC_GPU2_PEND 0x000200
65 #define INTC_PENDING_BASIC_GPU1_7 0x000400
66 #define INTC_PENDING_BASIC_GPU1_9 0x000800
67 #define INTC_PENDING_BASIC_GPU1_10 0x001000
68 #define INTC_PENDING_BASIC_GPU1_18 0x002000
69 #define INTC_PENDING_BASIC_GPU1_19 0x004000
70 #define INTC_PENDING_BASIC_GPU2_21 0x008000
71 #define INTC_PENDING_BASIC_GPU2_22 0x010000
72 #define INTC_PENDING_BASIC_GPU2_23 0x020000
73 #define INTC_PENDING_BASIC_GPU2_24 0x040000
74 #define INTC_PENDING_BASIC_GPU2_25 0x080000
75 #define INTC_PENDING_BASIC_GPU2_30 0x100000
76 #define INTC_PENDING_BASIC_MASK 0x1FFFFF
77
78 #define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \
79 INTC_PENDING_BASIC_GPU1_9 | \
80 INTC_PENDING_BASIC_GPU1_10 | \
81 INTC_PENDING_BASIC_GPU1_18 | \
82 INTC_PENDING_BASIC_GPU1_19)
83
84 #define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \
85 INTC_PENDING_BASIC_GPU2_22 | \
86 INTC_PENDING_BASIC_GPU2_23 | \
87 INTC_PENDING_BASIC_GPU2_24 | \
88 INTC_PENDING_BASIC_GPU2_25 | \
89 INTC_PENDING_BASIC_GPU2_30)
90
91 #define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \
92 (1 << 18) | (1 << 19)))
93 #define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \
94 (1 << 24) | (1 << 25) | (1 << 30)))
95
96 #define BANK1_START 8
97 #define BANK1_END (BANK1_START + 32 - 1)
98 #define BANK2_START (BANK1_START + 32)
99 #define BANK2_END (BANK2_START + 32 - 1)
100
101 #define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START))
102 #define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END))
103 #define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END))
104 #define IRQ_BANK1(n) ((n) - BANK1_START)
105 #define IRQ_BANK2(n) ((n) - BANK2_START)
106
107 #ifdef DEBUG
108 #define dprintf(fmt, args...) printf(fmt, ##args)
109 #else
110 #define dprintf(fmt, args...)
111 #endif
112
113 #define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */
114
115 struct bcm_intc_irqsrc {
116 struct intr_irqsrc bii_isrc;
117 u_int bii_irq;
118 uint16_t bii_disable_reg;
119 uint16_t bii_enable_reg;
120 uint32_t bii_mask;
121 };
122
123 struct bcm_intc_softc {
124 device_t sc_dev;
125 struct resource * intc_res;
126 bus_space_tag_t intc_bst;
127 bus_space_handle_t intc_bsh;
128 struct resource * intc_irq_res;
129 void * intc_irq_hdl;
130 struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS];
131 };
132
133 static struct ofw_compat_data compat_data[] = {
134 {"broadcom,bcm2835-armctrl-ic", 1},
135 {"brcm,bcm2835-armctrl-ic", 1},
136 {"brcm,bcm2836-armctrl-ic", 1},
137 {NULL, 0}
138 };
139
140 static struct bcm_intc_softc *bcm_intc_sc = NULL;
141
142 #define intc_read_4(_sc, reg) \
143 bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg))
144 #define intc_write_4(_sc, reg, val) \
145 bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val))
146
147 static inline void
bcm_intc_isrc_mask(struct bcm_intc_softc * sc,struct bcm_intc_irqsrc * bii)148 bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
149 {
150
151 intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask);
152 }
153
154 static inline void
bcm_intc_isrc_unmask(struct bcm_intc_softc * sc,struct bcm_intc_irqsrc * bii)155 bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
156 {
157
158 intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask);
159 }
160
161 static inline int
bcm2835_intc_active_intr(struct bcm_intc_softc * sc)162 bcm2835_intc_active_intr(struct bcm_intc_softc *sc)
163 {
164 uint32_t pending, pending_gpu;
165
166 pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK;
167 if (pending == 0)
168 return (-1);
169 if (pending & INTC_PENDING_BASIC_ARM)
170 return (ffs(pending) - 1);
171 if (pending & INTC_PENDING_BASIC_GPU1_MASK) {
172 if (pending & INTC_PENDING_BASIC_GPU1_7)
173 return (BANK1_START + 7);
174 if (pending & INTC_PENDING_BASIC_GPU1_9)
175 return (BANK1_START + 9);
176 if (pending & INTC_PENDING_BASIC_GPU1_10)
177 return (BANK1_START + 10);
178 if (pending & INTC_PENDING_BASIC_GPU1_18)
179 return (BANK1_START + 18);
180 if (pending & INTC_PENDING_BASIC_GPU1_19)
181 return (BANK1_START + 19);
182 }
183 if (pending & INTC_PENDING_BASIC_GPU2_MASK) {
184 if (pending & INTC_PENDING_BASIC_GPU2_21)
185 return (BANK2_START + 21);
186 if (pending & INTC_PENDING_BASIC_GPU2_22)
187 return (BANK2_START + 22);
188 if (pending & INTC_PENDING_BASIC_GPU2_23)
189 return (BANK2_START + 23);
190 if (pending & INTC_PENDING_BASIC_GPU2_24)
191 return (BANK2_START + 24);
192 if (pending & INTC_PENDING_BASIC_GPU2_25)
193 return (BANK2_START + 25);
194 if (pending & INTC_PENDING_BASIC_GPU2_30)
195 return (BANK2_START + 30);
196 }
197 if (pending & INTC_PENDING_BASIC_GPU1_PEND) {
198 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1);
199 pending_gpu &= INTC_PENDING_BANK1_MASK;
200 if (pending_gpu != 0)
201 return (BANK1_START + ffs(pending_gpu) - 1);
202 }
203 if (pending & INTC_PENDING_BASIC_GPU2_PEND) {
204 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2);
205 pending_gpu &= INTC_PENDING_BANK2_MASK;
206 if (pending_gpu != 0)
207 return (BANK2_START + ffs(pending_gpu) - 1);
208 }
209 return (-1); /* It shouldn't end here, but it's hardware. */
210 }
211
212 static int
bcm2835_intc_intr(void * arg)213 bcm2835_intc_intr(void *arg)
214 {
215 int irq, num;
216 struct bcm_intc_softc *sc = arg;
217
218 for (num = 0; ; num++) {
219 irq = bcm2835_intc_active_intr(sc);
220 if (irq == -1)
221 break;
222 if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc,
223 curthread->td_intr_frame) != 0) {
224 bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]);
225 device_printf(sc->sc_dev, "Stray irq %u disabled\n",
226 irq);
227 }
228 arm_irq_memory_barrier(0); /* XXX */
229 }
230 if (num == 0 && bootverbose)
231 device_printf(sc->sc_dev, "Spurious interrupt detected\n");
232
233 return (FILTER_HANDLED);
234 }
235
236 static void
bcm_intc_enable_intr(device_t dev,struct intr_irqsrc * isrc)237 bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
238 {
239 struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc;
240
241 arm_irq_memory_barrier(bii->bii_irq);
242 bcm_intc_isrc_unmask(device_get_softc(dev), bii);
243 }
244
245 static void
bcm_intc_disable_intr(device_t dev,struct intr_irqsrc * isrc)246 bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
247 {
248
249 bcm_intc_isrc_mask(device_get_softc(dev),
250 (struct bcm_intc_irqsrc *)isrc);
251 }
252
253 static int
bcm_intc_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)254 bcm_intc_map_intr(device_t dev, struct intr_map_data *data,
255 struct intr_irqsrc **isrcp)
256 {
257 u_int irq;
258 struct intr_map_data_fdt *daf;
259 struct bcm_intc_softc *sc;
260 bool valid;
261
262 if (data->type != INTR_MAP_DATA_FDT)
263 return (ENOTSUP);
264
265 daf = (struct intr_map_data_fdt *)data;
266 if (daf->ncells == 1)
267 irq = daf->cells[0];
268 else if (daf->ncells == 2) {
269 valid = true;
270 switch (daf->cells[0]) {
271 case 0:
272 irq = daf->cells[1];
273 if (irq >= BANK1_START)
274 valid = false;
275 break;
276 case 1:
277 irq = daf->cells[1] + BANK1_START;
278 if (irq > BANK1_END)
279 valid = false;
280 break;
281 case 2:
282 irq = daf->cells[1] + BANK2_START;
283 if (irq > BANK2_END)
284 valid = false;
285 break;
286 default:
287 valid = false;
288 break;
289 }
290
291 if (!valid) {
292 device_printf(dev,
293 "invalid IRQ config: bank=%d, irq=%d\n",
294 daf->cells[0], daf->cells[1]);
295 return (EINVAL);
296 }
297 }
298 else
299 return (EINVAL);
300
301 if (irq >= BCM_INTC_NIRQS)
302 return (EINVAL);
303
304 sc = device_get_softc(dev);
305 *isrcp = &sc->intc_isrcs[irq].bii_isrc;
306 return (0);
307 }
308
309 static void
bcm_intc_pre_ithread(device_t dev,struct intr_irqsrc * isrc)310 bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
311 {
312
313 bcm_intc_disable_intr(dev, isrc);
314 }
315
316 static void
bcm_intc_post_ithread(device_t dev,struct intr_irqsrc * isrc)317 bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
318 {
319
320 bcm_intc_enable_intr(dev, isrc);
321 }
322
323 static void
bcm_intc_post_filter(device_t dev,struct intr_irqsrc * isrc)324 bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc)
325 {
326 }
327
328 static int
bcm_intc_pic_register(struct bcm_intc_softc * sc,intptr_t xref)329 bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref)
330 {
331 struct bcm_intc_irqsrc *bii;
332 int error;
333 uint32_t irq;
334 const char *name;
335
336 name = device_get_nameunit(sc->sc_dev);
337 for (irq = 0; irq < BCM_INTC_NIRQS; irq++) {
338 bii = &sc->intc_isrcs[irq];
339 bii->bii_irq = irq;
340 if (IS_IRQ_BASIC(irq)) {
341 bii->bii_disable_reg = INTC_DISABLE_BASIC;
342 bii->bii_enable_reg = INTC_ENABLE_BASIC;
343 bii->bii_mask = 1 << irq;
344 } else if (IS_IRQ_BANK1(irq)) {
345 bii->bii_disable_reg = INTC_DISABLE_BANK1;
346 bii->bii_enable_reg = INTC_ENABLE_BANK1;
347 bii->bii_mask = 1 << IRQ_BANK1(irq);
348 } else if (IS_IRQ_BANK2(irq)) {
349 bii->bii_disable_reg = INTC_DISABLE_BANK2;
350 bii->bii_enable_reg = INTC_ENABLE_BANK2;
351 bii->bii_mask = 1 << IRQ_BANK2(irq);
352 } else
353 return (ENXIO);
354
355 error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0,
356 "%s,%u", name, irq);
357 if (error != 0)
358 return (error);
359 }
360 if (intr_pic_register(sc->sc_dev, xref) == NULL)
361 return (ENXIO);
362
363 return (0);
364 }
365
366 static int
bcm_intc_probe(device_t dev)367 bcm_intc_probe(device_t dev)
368 {
369
370 if (!ofw_bus_status_okay(dev))
371 return (ENXIO);
372
373 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
374 return (ENXIO);
375
376 device_set_desc(dev, "BCM2835 Interrupt Controller");
377 return (BUS_PROBE_DEFAULT);
378 }
379
380 static int
bcm_intc_attach(device_t dev)381 bcm_intc_attach(device_t dev)
382 {
383 struct bcm_intc_softc *sc = device_get_softc(dev);
384 int rid = 0;
385 intptr_t xref;
386 sc->sc_dev = dev;
387
388 if (bcm_intc_sc)
389 return (ENXIO);
390
391 sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
392 if (sc->intc_res == NULL) {
393 device_printf(dev, "could not allocate memory resource\n");
394 return (ENXIO);
395 }
396
397 xref = OF_xref_from_node(ofw_bus_get_node(dev));
398 if (bcm_intc_pic_register(sc, xref) != 0) {
399 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res);
400 device_printf(dev, "could not register PIC\n");
401 return (ENXIO);
402 }
403
404 rid = 0;
405 sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
406 RF_ACTIVE);
407 if (sc->intc_irq_res == NULL) {
408 if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, INTR_ROOT_IRQ)
409 != 0) {
410 /* XXX clean up */
411 device_printf(dev, "could not set PIC as a root\n");
412 return (ENXIO);
413 }
414 } else {
415 if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK,
416 bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) {
417 /* XXX clean up */
418 device_printf(dev, "could not setup irq handler\n");
419 return (ENXIO);
420 }
421 }
422 sc->intc_bst = rman_get_bustag(sc->intc_res);
423 sc->intc_bsh = rman_get_bushandle(sc->intc_res);
424
425 bcm_intc_sc = sc;
426
427 return (0);
428 }
429
430 static device_method_t bcm_intc_methods[] = {
431 DEVMETHOD(device_probe, bcm_intc_probe),
432 DEVMETHOD(device_attach, bcm_intc_attach),
433
434 DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr),
435 DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr),
436 DEVMETHOD(pic_map_intr, bcm_intc_map_intr),
437 DEVMETHOD(pic_post_filter, bcm_intc_post_filter),
438 DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread),
439 DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread),
440 { 0, 0 }
441 };
442
443 static driver_t bcm_intc_driver = {
444 "intc",
445 bcm_intc_methods,
446 sizeof(struct bcm_intc_softc),
447 };
448
449 EARLY_DRIVER_MODULE(intc, simplebus, bcm_intc_driver, 0, 0,
450 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
451