1 // SPDX-License-Identifier: GPL-2.0
2 // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
3 // Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
4 //
5 // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
6 // interface according to the operating speed between 10GBASE-R,
7 // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
8 // word).
9 //
10 // This driver only supports those aspects of the PHY that I'm able to
11 // observe and test with the SFP+ module, which is an incomplete subset
12 // of what this PHY is able to support. For example, I only assume it
13 // supports a single lane Serdes connection, but it may be that the PHY
14 // is able to support more than that.
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/phy.h>
18
19 enum {
20 MDIO_AN_C22 = 0xffe0,
21 };
22
bcm84881_wait_init(struct phy_device * phydev)23 static int bcm84881_wait_init(struct phy_device *phydev)
24 {
25 int val;
26
27 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
28 val, !(val & MDIO_CTRL1_RESET),
29 100000, 2000000, false);
30 }
31
bcm84881_fill_possible_interfaces(struct phy_device * phydev)32 static void bcm84881_fill_possible_interfaces(struct phy_device *phydev)
33 {
34 unsigned long *possible = phydev->possible_interfaces;
35
36 __set_bit(PHY_INTERFACE_MODE_SGMII, possible);
37 __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
38 __set_bit(PHY_INTERFACE_MODE_10GBASER, possible);
39 }
40
bcm84881_config_init(struct phy_device * phydev)41 static int bcm84881_config_init(struct phy_device *phydev)
42 {
43 bcm84881_fill_possible_interfaces(phydev);
44
45 switch (phydev->interface) {
46 case PHY_INTERFACE_MODE_SGMII:
47 case PHY_INTERFACE_MODE_2500BASEX:
48 case PHY_INTERFACE_MODE_10GBASER:
49 break;
50 default:
51 return -ENODEV;
52 }
53
54 return 0;
55 }
56
bcm84881_probe(struct phy_device * phydev)57 static int bcm84881_probe(struct phy_device *phydev)
58 {
59 /* This driver requires PMAPMD and AN blocks */
60 const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
61
62 if (!phydev->is_c45 ||
63 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
64 return -ENODEV;
65
66 return 0;
67 }
68
bcm84881_get_features(struct phy_device * phydev)69 static int bcm84881_get_features(struct phy_device *phydev)
70 {
71 int ret;
72
73 ret = genphy_c45_pma_read_abilities(phydev);
74 if (ret)
75 return ret;
76
77 /* Although the PHY sets bit 1.11.8, it does not support 10M modes */
78 linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
79 phydev->supported);
80 linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
81 phydev->supported);
82
83 return 0;
84 }
85
bcm84881_config_aneg(struct phy_device * phydev)86 static int bcm84881_config_aneg(struct phy_device *phydev)
87 {
88 bool changed = false;
89 u32 adv;
90 int ret;
91
92 /* Wait for the PHY to finish initialising, otherwise our
93 * advertisement may be overwritten.
94 */
95 ret = bcm84881_wait_init(phydev);
96 if (ret)
97 return ret;
98
99 /* We don't support manual MDI control */
100 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
101
102 /* disabled autoneg doesn't seem to work with this PHY */
103 if (phydev->autoneg == AUTONEG_DISABLE)
104 return -EINVAL;
105
106 ret = genphy_c45_an_config_aneg(phydev);
107 if (ret < 0)
108 return ret;
109 if (ret > 0)
110 changed = true;
111
112 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
114 MDIO_AN_C22 + MII_CTRL1000,
115 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
116 adv);
117 if (ret < 0)
118 return ret;
119 if (ret > 0)
120 changed = true;
121
122 return genphy_c45_check_and_restart_aneg(phydev, changed);
123 }
124
bcm84881_aneg_done(struct phy_device * phydev)125 static int bcm84881_aneg_done(struct phy_device *phydev)
126 {
127 int bmsr, val;
128
129 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
130 if (val < 0)
131 return val;
132
133 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
134 if (bmsr < 0)
135 return bmsr;
136
137 return !!(val & MDIO_AN_STAT1_COMPLETE) &&
138 !!(bmsr & BMSR_ANEGCOMPLETE);
139 }
140
bcm84881_read_status(struct phy_device * phydev)141 static int bcm84881_read_status(struct phy_device *phydev)
142 {
143 unsigned int mode;
144 int bmsr, val;
145
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
147 if (val < 0)
148 return val;
149
150 if (val & MDIO_AN_CTRL1_RESTART) {
151 phydev->link = 0;
152 return 0;
153 }
154
155 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
156 if (val < 0)
157 return val;
158
159 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
160 if (bmsr < 0)
161 return bmsr;
162
163 phydev->autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
164 !!(bmsr & BMSR_ANEGCOMPLETE);
165 phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
166 !!(bmsr & BMSR_LSTATUS);
167 if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
168 phydev->link = false;
169
170 linkmode_zero(phydev->lp_advertising);
171 phydev->speed = SPEED_UNKNOWN;
172 phydev->duplex = DUPLEX_UNKNOWN;
173 phydev->pause = 0;
174 phydev->asym_pause = 0;
175 phydev->mdix = 0;
176
177 if (!phydev->link)
178 return 0;
179
180 if (phydev->autoneg_complete) {
181 val = genphy_c45_read_lpa(phydev);
182 if (val < 0)
183 return val;
184
185 val = phy_read_mmd(phydev, MDIO_MMD_AN,
186 MDIO_AN_C22 + MII_STAT1000);
187 if (val < 0)
188 return val;
189
190 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
191
192 if (phydev->autoneg == AUTONEG_ENABLE)
193 phy_resolve_aneg_linkmode(phydev);
194 }
195
196 if (phydev->autoneg == AUTONEG_DISABLE) {
197 /* disabled autoneg doesn't seem to work, so force the link
198 * down.
199 */
200 phydev->link = 0;
201 return 0;
202 }
203
204 /* Set the host link mode - we set the phy interface mode and
205 * the speed according to this register so that downshift works.
206 * We leave the duplex setting as per the resolution from the
207 * above.
208 */
209 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
210 mode = (val & 0x1e) >> 1;
211 if (mode == 1 || mode == 2)
212 phydev->interface = PHY_INTERFACE_MODE_SGMII;
213 else if (mode == 3)
214 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
215 else if (mode == 4)
216 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
217 switch (mode & 7) {
218 case 1:
219 phydev->speed = SPEED_100;
220 break;
221 case 2:
222 phydev->speed = SPEED_1000;
223 break;
224 case 3:
225 phydev->speed = SPEED_10000;
226 break;
227 case 4:
228 phydev->speed = SPEED_2500;
229 break;
230 case 5:
231 phydev->speed = SPEED_5000;
232 break;
233 }
234
235 return genphy_c45_read_mdix(phydev);
236 }
237
238 static struct phy_driver bcm84881_drivers[] = {
239 {
240 .phy_id = 0xae025150,
241 .phy_id_mask = 0xfffffff0,
242 .name = "Broadcom BCM84881",
243 .config_init = bcm84881_config_init,
244 .probe = bcm84881_probe,
245 .get_features = bcm84881_get_features,
246 .config_aneg = bcm84881_config_aneg,
247 .aneg_done = bcm84881_aneg_done,
248 .read_status = bcm84881_read_status,
249 },
250 };
251
252 module_phy_driver(bcm84881_drivers);
253
254 /* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
255 static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
256 { 0xae025150, 0xfffffff0 },
257 { },
258 };
259 MODULE_AUTHOR("Russell King");
260 MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
261 MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
262 MODULE_LICENSE("GPL");
263