xref: /linux/drivers/gpu/drm/i915/gvt/cmd_parser.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Ke Yu
25  *    Kevin Tian <kevin.tian@intel.com>
26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
27  *
28  * Contributors:
29  *    Min He <min.he@intel.com>
30  *    Ping Gao <ping.a.gao@intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Yulei Zhang <yulei.zhang@intel.com>
33  *    Zhi Wang <zhi.a.wang@intel.com>
34  *
35  */
36 
37 #include <linux/slab.h>
38 
39 #include "i915_drv.h"
40 #include "i915_reg.h"
41 #include "gt/intel_engine_regs.h"
42 #include "gt/intel_gpu_commands.h"
43 #include "gt/intel_gt_regs.h"
44 #include "gt/intel_lrc.h"
45 #include "gt/intel_ring.h"
46 #include "gt/intel_gt_requests.h"
47 #include "gt/shmem_utils.h"
48 #include "gvt.h"
49 #include "i915_pvinfo.h"
50 #include "trace.h"
51 
52 #include "display/i9xx_plane_regs.h"
53 #include "display/intel_display.h"
54 #include "display/intel_sprite_regs.h"
55 #include "gem/i915_gem_context.h"
56 #include "gem/i915_gem_pm.h"
57 #include "gt/intel_context.h"
58 
59 #define INVALID_OP    (~0U)
60 
61 #define OP_LEN_MI           9
62 #define OP_LEN_2D           10
63 #define OP_LEN_3D_MEDIA     16
64 #define OP_LEN_MFX_VC       16
65 #define OP_LEN_VEBOX	    16
66 
67 #define CMD_TYPE(cmd)	(((cmd) >> 29) & 7)
68 
69 struct sub_op_bits {
70 	int hi;
71 	int low;
72 };
73 struct decode_info {
74 	const char *name;
75 	int op_len;
76 	int nr_sub_op;
77 	const struct sub_op_bits *sub_op;
78 };
79 
80 #define   MAX_CMD_BUDGET			0x7fffffff
81 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
82 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
83 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
84 
85 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
86 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
87 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
88 
89 /* Render Command Map */
90 
91 /* MI_* command Opcode (28:23) */
92 #define OP_MI_NOOP                          0x0
93 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
94 #define OP_MI_USER_INTERRUPT                0x2
95 #define OP_MI_WAIT_FOR_EVENT                0x3
96 #define OP_MI_FLUSH                         0x4
97 #define OP_MI_ARB_CHECK                     0x5
98 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
99 #define OP_MI_REPORT_HEAD                   0x7
100 #define OP_MI_ARB_ON_OFF                    0x8
101 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
102 #define OP_MI_BATCH_BUFFER_END              0xA
103 #define OP_MI_SUSPEND_FLUSH                 0xB
104 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
105 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
106 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
107 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
108 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
109 #define OP_MI_DISPLAY_FLIP                  0x14
110 #define OP_MI_SEMAPHORE_MBOX                0x16
111 #define OP_MI_SET_CONTEXT                   0x18
112 #define OP_MI_MATH                          0x1A
113 #define OP_MI_URB_CLEAR                     0x19
114 #define OP_MI_SEMAPHORE_SIGNAL		    0x1B  /* BDW+ */
115 #define OP_MI_SEMAPHORE_WAIT		    0x1C  /* BDW+ */
116 
117 #define OP_MI_STORE_DATA_IMM                0x20
118 #define OP_MI_STORE_DATA_INDEX              0x21
119 #define OP_MI_LOAD_REGISTER_IMM             0x22
120 #define OP_MI_UPDATE_GTT                    0x23
121 #define OP_MI_STORE_REGISTER_MEM            0x24
122 #define OP_MI_FLUSH_DW                      0x26
123 #define OP_MI_CLFLUSH                       0x27
124 #define OP_MI_REPORT_PERF_COUNT             0x28
125 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
126 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
127 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
128 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
129 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
130 #define OP_MI_2E			    0x2E  /* BDW+ */
131 #define OP_MI_2F			    0x2F  /* BDW+ */
132 #define OP_MI_BATCH_BUFFER_START            0x31
133 
134 /* Bit definition for dword 0 */
135 #define _CMDBIT_BB_START_IN_PPGTT	(1UL << 8)
136 
137 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
138 
139 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
140 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
141 #define BATCH_BUFFER_ADR_SPACE_BIT(x)	(((x) >> 8) & 1U)
142 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
143 
144 /* 2D command: Opcode (28:22) */
145 #define OP_2D(x)    ((2<<7) | x)
146 
147 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
148 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
149 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
150 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
151 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
152 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
153 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
154 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
155 #define OP_XY_PAT_BLT                               OP_2D(0x51)
156 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
157 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
158 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
159 #define OP_XY_FULL_BLT                              OP_2D(0x55)
160 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
161 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
162 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
163 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
164 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
165 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
166 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
167 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
168 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
169 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
170 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
171 
172 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
173 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
174 	((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
175 
176 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
177 
178 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
179 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
180 #define OP_3D_MEDIA_0_1_4			OP_3D_MEDIA(0x0, 0x1, 0x04)
181 #define OP_SWTESS_BASE_ADDRESS			OP_3D_MEDIA(0x0, 0x1, 0x03)
182 
183 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
184 
185 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
186 
187 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
188 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
189 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
190 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
191 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
192 #define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
193 
194 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
195 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
196 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
197 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
198 
199 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
200 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
201 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
202 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
203 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
204 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
205 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
206 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
207 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
208 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
209 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
210 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
211 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
212 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
213 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
214 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
215 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
216 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
217 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
218 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
219 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
220 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
221 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
222 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
223 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
224 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
225 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
226 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
227 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
228 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
229 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
230 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
231 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
232 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
233 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
234 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
235 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
236 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
237 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
238 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
239 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
240 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
241 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
242 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
243 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
244 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
245 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
246 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
247 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
248 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
249 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
250 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
251 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
252 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
253 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
254 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
255 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
256 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
257 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
258 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
259 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
260 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
261 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
262 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
263 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
264 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
265 
266 #define OP_3DSTATE_VF_INSTANCING 		OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
267 #define OP_3DSTATE_VF_SGVS  			OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
268 #define OP_3DSTATE_VF_TOPOLOGY   		OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
269 #define OP_3DSTATE_WM_CHROMAKEY   		OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
270 #define OP_3DSTATE_PS_BLEND   			OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
271 #define OP_3DSTATE_WM_DEPTH_STENCIL   		OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
272 #define OP_3DSTATE_PS_EXTRA   			OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
273 #define OP_3DSTATE_RASTER   			OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
274 #define OP_3DSTATE_SBE_SWIZ   			OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
275 #define OP_3DSTATE_WM_HZ_OP   			OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
276 #define OP_3DSTATE_COMPONENT_PACKING		OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
277 
278 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
279 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
280 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
281 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
282 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
283 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
284 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
285 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
286 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
287 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
288 #define OP_3DSTATE_MULTISAMPLE_BDW		OP_3D_MEDIA(0x3, 0x0, 0x0D)
289 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
290 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
291 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
292 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
293 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
294 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
295 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
296 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
297 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
298 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
299 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
300 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
301 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
302 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
303 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
304 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
305 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
306 
307 /* VCCP Command Parser */
308 
309 /*
310  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
311  * git://anongit.freedesktop.org/vaapi/intel-driver
312  * src/i965_defines.h
313  *
314  */
315 
316 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
317 	(3 << 13 | \
318 	 (pipeline) << 11 | \
319 	 (op) << 8 | \
320 	 (sub_opa) << 5 | \
321 	 (sub_opb))
322 
323 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
324 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
325 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
326 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
327 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
328 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
329 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
330 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
331 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
332 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
333 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
334 
335 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
336 
337 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
338 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
339 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
340 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
341 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
342 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
343 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
344 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
345 #define OP_MFD_AVC_DPB_STATE			   OP_MFX(2, 1, 1, 6) /* IVB+ */
346 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
347 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
348 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
349 
350 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
351 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
352 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
353 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
354 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
355 
356 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
357 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
358 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
359 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
360 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
361 
362 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
363 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
364 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
365 
366 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
367 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
368 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
369 
370 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
371 	(3 << 13 | \
372 	 (pipeline) << 11 | \
373 	 (op) << 8 | \
374 	 (sub_opa) << 5 | \
375 	 (sub_opb))
376 
377 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
378 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
379 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
380 
381 struct parser_exec_state;
382 
383 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
384 
385 #define GVT_CMD_HASH_BITS   7
386 
387 /* which DWords need address fix */
388 #define ADDR_FIX_1(x1)			(1 << (x1))
389 #define ADDR_FIX_2(x1, x2)		(ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
390 #define ADDR_FIX_3(x1, x2, x3)		(ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
391 #define ADDR_FIX_4(x1, x2, x3, x4)	(ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
392 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
393 
394 #define DWORD_FIELD(dword, end, start) \
395 	FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
396 
397 #define OP_LENGTH_BIAS 2
398 #define CMD_LEN(value)  (value + OP_LENGTH_BIAS)
399 
gvt_check_valid_cmd_length(int len,int valid_len)400 static int gvt_check_valid_cmd_length(int len, int valid_len)
401 {
402 	if (valid_len != len) {
403 		gvt_err("len is not valid:  len=%u  valid_len=%u\n",
404 			len, valid_len);
405 		return -EFAULT;
406 	}
407 	return 0;
408 }
409 
410 struct cmd_info {
411 	const char *name;
412 	u32 opcode;
413 
414 #define F_LEN_MASK	3U
415 #define F_LEN_CONST  1U
416 #define F_LEN_VAR    0U
417 /* value is const although LEN maybe variable */
418 #define F_LEN_VAR_FIXED    (1<<1)
419 
420 /*
421  * command has its own ip advance logic
422  * e.g. MI_BATCH_START, MI_BATCH_END
423  */
424 #define F_IP_ADVANCE_CUSTOM (1<<2)
425 	u32 flag;
426 
427 #define R_RCS	BIT(RCS0)
428 #define R_VCS1  BIT(VCS0)
429 #define R_VCS2  BIT(VCS1)
430 #define R_VCS	(R_VCS1 | R_VCS2)
431 #define R_BCS	BIT(BCS0)
432 #define R_VECS	BIT(VECS0)
433 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
434 	/* rings that support this cmd: BLT/RCS/VCS/VECS */
435 	intel_engine_mask_t rings;
436 
437 	/* devices that support this cmd: SNB/IVB/HSW/... */
438 	u16 devices;
439 
440 	/* which DWords are address that need fix up.
441 	 * bit 0 means a 32-bit non address operand in command
442 	 * bit 1 means address operand, which could be 32-bit
443 	 * or 64-bit depending on different architectures.(
444 	 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
445 	 * No matter the address length, each address only takes
446 	 * one bit in the bitmap.
447 	 */
448 	u16 addr_bitmap;
449 
450 	/* flag == F_LEN_CONST : command length
451 	 * flag == F_LEN_VAR : length bias bits
452 	 * Note: length is in DWord
453 	 */
454 	u32 len;
455 
456 	parser_cmd_handler handler;
457 
458 	/* valid length in DWord */
459 	u32 valid_len;
460 };
461 
462 struct cmd_entry {
463 	struct hlist_node hlist;
464 	const struct cmd_info *info;
465 };
466 
467 enum {
468 	RING_BUFFER_INSTRUCTION,
469 	BATCH_BUFFER_INSTRUCTION,
470 	BATCH_BUFFER_2ND_LEVEL,
471 	RING_BUFFER_CTX,
472 };
473 
474 enum {
475 	GTT_BUFFER,
476 	PPGTT_BUFFER
477 };
478 
479 struct parser_exec_state {
480 	struct intel_vgpu *vgpu;
481 	const struct intel_engine_cs *engine;
482 
483 	int buf_type;
484 
485 	/* batch buffer address type */
486 	int buf_addr_type;
487 
488 	/* graphics memory address of ring buffer start */
489 	unsigned long ring_start;
490 	unsigned long ring_size;
491 	unsigned long ring_head;
492 	unsigned long ring_tail;
493 
494 	/* instruction graphics memory address */
495 	unsigned long ip_gma;
496 
497 	/* mapped va of the instr_gma */
498 	void *ip_va;
499 	void *rb_va;
500 
501 	void *ret_bb_va;
502 	/* next instruction when return from  batch buffer to ring buffer */
503 	unsigned long ret_ip_gma_ring;
504 
505 	/* next instruction when return from 2nd batch buffer to batch buffer */
506 	unsigned long ret_ip_gma_bb;
507 
508 	/* batch buffer address type (GTT or PPGTT)
509 	 * used when ret from 2nd level batch buffer
510 	 */
511 	int saved_buf_addr_type;
512 	bool is_ctx_wa;
513 	bool is_init_ctx;
514 
515 	const struct cmd_info *info;
516 
517 	struct intel_vgpu_workload *workload;
518 };
519 
520 #define gmadr_dw_number(s)	\
521 	(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
522 
523 static unsigned long bypass_scan_mask = 0;
524 
525 /* ring ALL, type = 0 */
526 static const struct sub_op_bits sub_op_mi[] = {
527 	{31, 29},
528 	{28, 23},
529 };
530 
531 static const struct decode_info decode_info_mi = {
532 	"MI",
533 	OP_LEN_MI,
534 	ARRAY_SIZE(sub_op_mi),
535 	sub_op_mi,
536 };
537 
538 /* ring RCS, command type 2 */
539 static const struct sub_op_bits sub_op_2d[] = {
540 	{31, 29},
541 	{28, 22},
542 };
543 
544 static const struct decode_info decode_info_2d = {
545 	"2D",
546 	OP_LEN_2D,
547 	ARRAY_SIZE(sub_op_2d),
548 	sub_op_2d,
549 };
550 
551 /* ring RCS, command type 3 */
552 static const struct sub_op_bits sub_op_3d_media[] = {
553 	{31, 29},
554 	{28, 27},
555 	{26, 24},
556 	{23, 16},
557 };
558 
559 static const struct decode_info decode_info_3d_media = {
560 	"3D_Media",
561 	OP_LEN_3D_MEDIA,
562 	ARRAY_SIZE(sub_op_3d_media),
563 	sub_op_3d_media,
564 };
565 
566 /* ring VCS, command type 3 */
567 static const struct sub_op_bits sub_op_mfx_vc[] = {
568 	{31, 29},
569 	{28, 27},
570 	{26, 24},
571 	{23, 21},
572 	{20, 16},
573 };
574 
575 static const struct decode_info decode_info_mfx_vc = {
576 	"MFX_VC",
577 	OP_LEN_MFX_VC,
578 	ARRAY_SIZE(sub_op_mfx_vc),
579 	sub_op_mfx_vc,
580 };
581 
582 /* ring VECS, command type 3 */
583 static const struct sub_op_bits sub_op_vebox[] = {
584 	{31, 29},
585 	{28, 27},
586 	{26, 24},
587 	{23, 21},
588 	{20, 16},
589 };
590 
591 static const struct decode_info decode_info_vebox = {
592 	"VEBOX",
593 	OP_LEN_VEBOX,
594 	ARRAY_SIZE(sub_op_vebox),
595 	sub_op_vebox,
596 };
597 
598 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
599 	[RCS0] = {
600 		&decode_info_mi,
601 		NULL,
602 		NULL,
603 		&decode_info_3d_media,
604 		NULL,
605 		NULL,
606 		NULL,
607 		NULL,
608 	},
609 
610 	[VCS0] = {
611 		&decode_info_mi,
612 		NULL,
613 		NULL,
614 		&decode_info_mfx_vc,
615 		NULL,
616 		NULL,
617 		NULL,
618 		NULL,
619 	},
620 
621 	[BCS0] = {
622 		&decode_info_mi,
623 		NULL,
624 		&decode_info_2d,
625 		NULL,
626 		NULL,
627 		NULL,
628 		NULL,
629 		NULL,
630 	},
631 
632 	[VECS0] = {
633 		&decode_info_mi,
634 		NULL,
635 		NULL,
636 		&decode_info_vebox,
637 		NULL,
638 		NULL,
639 		NULL,
640 		NULL,
641 	},
642 
643 	[VCS1] = {
644 		&decode_info_mi,
645 		NULL,
646 		NULL,
647 		&decode_info_mfx_vc,
648 		NULL,
649 		NULL,
650 		NULL,
651 		NULL,
652 	},
653 };
654 
get_opcode(u32 cmd,const struct intel_engine_cs * engine)655 static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
656 {
657 	const struct decode_info *d_info;
658 
659 	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
660 	if (d_info == NULL)
661 		return INVALID_OP;
662 
663 	return cmd >> (32 - d_info->op_len);
664 }
665 
666 static inline const struct cmd_info *
find_cmd_entry(struct intel_gvt * gvt,unsigned int opcode,const struct intel_engine_cs * engine)667 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
668 	       const struct intel_engine_cs *engine)
669 {
670 	struct cmd_entry *e;
671 
672 	hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
673 		if (opcode == e->info->opcode &&
674 		    e->info->rings & engine->mask)
675 			return e->info;
676 	}
677 	return NULL;
678 }
679 
680 static inline const struct cmd_info *
get_cmd_info(struct intel_gvt * gvt,u32 cmd,const struct intel_engine_cs * engine)681 get_cmd_info(struct intel_gvt *gvt, u32 cmd,
682 	     const struct intel_engine_cs *engine)
683 {
684 	u32 opcode;
685 
686 	opcode = get_opcode(cmd, engine);
687 	if (opcode == INVALID_OP)
688 		return NULL;
689 
690 	return find_cmd_entry(gvt, opcode, engine);
691 }
692 
sub_op_val(u32 cmd,u32 hi,u32 low)693 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
694 {
695 	return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
696 }
697 
print_opcode(u32 cmd,const struct intel_engine_cs * engine)698 static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
699 {
700 	const struct decode_info *d_info;
701 	int i;
702 
703 	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
704 	if (d_info == NULL)
705 		return;
706 
707 	gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
708 			cmd >> (32 - d_info->op_len), d_info->name);
709 
710 	for (i = 0; i < d_info->nr_sub_op; i++)
711 		pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
712 					d_info->sub_op[i].low));
713 
714 	pr_err("\n");
715 }
716 
cmd_ptr(struct parser_exec_state * s,int index)717 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
718 {
719 	return s->ip_va + (index << 2);
720 }
721 
cmd_val(struct parser_exec_state * s,int index)722 static inline u32 cmd_val(struct parser_exec_state *s, int index)
723 {
724 	return *cmd_ptr(s, index);
725 }
726 
is_init_ctx(struct parser_exec_state * s)727 static inline bool is_init_ctx(struct parser_exec_state *s)
728 {
729 	return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx);
730 }
731 
parser_exec_state_dump(struct parser_exec_state * s)732 static void parser_exec_state_dump(struct parser_exec_state *s)
733 {
734 	int cnt = 0;
735 	int i;
736 
737 	gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
738 		    " ring_head(%08lx) ring_tail(%08lx)\n",
739 		    s->vgpu->id, s->engine->name,
740 		    s->ring_start, s->ring_start + s->ring_size,
741 		    s->ring_head, s->ring_tail);
742 
743 	gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
744 			s->buf_type == RING_BUFFER_INSTRUCTION ?
745 			"RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ?
746 				"CTX_BUFFER" : "BATCH_BUFFER"),
747 			s->buf_addr_type == GTT_BUFFER ?
748 			"GTT" : "PPGTT", s->ip_gma);
749 
750 	if (s->ip_va == NULL) {
751 		gvt_dbg_cmd(" ip_va(NULL)");
752 		return;
753 	}
754 
755 	gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
756 			s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
757 			cmd_val(s, 2), cmd_val(s, 3));
758 
759 	print_opcode(cmd_val(s, 0), s->engine);
760 
761 	s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
762 
763 	while (cnt < 1024) {
764 		gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
765 		for (i = 0; i < 8; i++)
766 			gvt_dbg_cmd("%08x ", cmd_val(s, i));
767 		gvt_dbg_cmd("\n");
768 
769 		s->ip_va += 8 * sizeof(u32);
770 		cnt += 8;
771 	}
772 }
773 
update_ip_va(struct parser_exec_state * s)774 static inline void update_ip_va(struct parser_exec_state *s)
775 {
776 	unsigned long len = 0;
777 
778 	if (WARN_ON(s->ring_head == s->ring_tail))
779 		return;
780 
781 	if (s->buf_type == RING_BUFFER_INSTRUCTION ||
782 			s->buf_type == RING_BUFFER_CTX) {
783 		unsigned long ring_top = s->ring_start + s->ring_size;
784 
785 		if (s->ring_head > s->ring_tail) {
786 			if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
787 				len = (s->ip_gma - s->ring_head);
788 			else if (s->ip_gma >= s->ring_start &&
789 					s->ip_gma <= s->ring_tail)
790 				len = (ring_top - s->ring_head) +
791 					(s->ip_gma - s->ring_start);
792 		} else
793 			len = (s->ip_gma - s->ring_head);
794 
795 		s->ip_va = s->rb_va + len;
796 	} else {/* shadow batch buffer */
797 		s->ip_va = s->ret_bb_va;
798 	}
799 }
800 
ip_gma_set(struct parser_exec_state * s,unsigned long ip_gma)801 static inline int ip_gma_set(struct parser_exec_state *s,
802 		unsigned long ip_gma)
803 {
804 	WARN_ON(!IS_ALIGNED(ip_gma, 4));
805 
806 	s->ip_gma = ip_gma;
807 	update_ip_va(s);
808 	return 0;
809 }
810 
ip_gma_advance(struct parser_exec_state * s,unsigned int dw_len)811 static inline int ip_gma_advance(struct parser_exec_state *s,
812 		unsigned int dw_len)
813 {
814 	s->ip_gma += (dw_len << 2);
815 
816 	if (s->buf_type == RING_BUFFER_INSTRUCTION) {
817 		if (s->ip_gma >= s->ring_start + s->ring_size)
818 			s->ip_gma -= s->ring_size;
819 		update_ip_va(s);
820 	} else {
821 		s->ip_va += (dw_len << 2);
822 	}
823 
824 	return 0;
825 }
826 
get_cmd_length(const struct cmd_info * info,u32 cmd)827 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
828 {
829 	if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
830 		return info->len;
831 	else
832 		return (cmd & ((1U << info->len) - 1)) + 2;
833 	return 0;
834 }
835 
cmd_length(struct parser_exec_state * s)836 static inline int cmd_length(struct parser_exec_state *s)
837 {
838 	return get_cmd_length(s->info, cmd_val(s, 0));
839 }
840 
841 /* do not remove this, some platform may need clflush here */
842 #define patch_value(s, addr, val) do { \
843 	*addr = val; \
844 } while (0)
845 
is_mocs_mmio(unsigned int offset)846 static inline bool is_mocs_mmio(unsigned int offset)
847 {
848 	return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
849 		((offset >= 0xb020) && (offset <= 0xb0a0));
850 }
851 
is_cmd_update_pdps(unsigned int offset,struct parser_exec_state * s)852 static int is_cmd_update_pdps(unsigned int offset,
853 			      struct parser_exec_state *s)
854 {
855 	u32 base = s->workload->engine->mmio_base;
856 	return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
857 }
858 
cmd_pdp_mmio_update_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index)859 static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
860 				       unsigned int offset, unsigned int index)
861 {
862 	struct intel_vgpu *vgpu = s->vgpu;
863 	struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
864 	struct intel_vgpu_mm *mm;
865 	u64 pdps[GEN8_3LVL_PDPES];
866 
867 	if (shadow_mm->ppgtt_mm.root_entry_type ==
868 	    GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
869 		pdps[0] = (u64)cmd_val(s, 2) << 32;
870 		pdps[0] |= cmd_val(s, 4);
871 
872 		mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
873 		if (!mm) {
874 			gvt_vgpu_err("failed to get the 4-level shadow vm\n");
875 			return -EINVAL;
876 		}
877 		intel_vgpu_mm_get(mm);
878 		list_add_tail(&mm->ppgtt_mm.link,
879 			      &s->workload->lri_shadow_mm);
880 		*cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
881 		*cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
882 	} else {
883 		/* Currently all guests use PML4 table and now can't
884 		 * have a guest with 3-level table but uses LRI for
885 		 * PPGTT update. So this is simply un-testable. */
886 		GEM_BUG_ON(1);
887 		gvt_vgpu_err("invalid shared shadow vm type\n");
888 		return -EINVAL;
889 	}
890 	return 0;
891 }
892 
cmd_reg_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index,char * cmd)893 static int cmd_reg_handler(struct parser_exec_state *s,
894 	unsigned int offset, unsigned int index, char *cmd)
895 {
896 	struct intel_vgpu *vgpu = s->vgpu;
897 	struct intel_gvt *gvt = vgpu->gvt;
898 	u32 ctx_sr_ctl;
899 	u32 *vreg, vreg_old;
900 
901 	if (offset + 4 > gvt->device_info.mmio_size) {
902 		gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
903 				cmd, offset);
904 		return -EFAULT;
905 	}
906 
907 	if (is_init_ctx(s)) {
908 		struct intel_gvt_mmio_info *mmio_info;
909 
910 		intel_gvt_mmio_set_cmd_accessible(gvt, offset);
911 		mmio_info = intel_gvt_find_mmio_info(gvt, offset);
912 		if (mmio_info && mmio_info->write)
913 			intel_gvt_mmio_set_cmd_write_patch(gvt, offset);
914 		return 0;
915 	}
916 
917 	if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {
918 		gvt_vgpu_err("%s access to non-render register (%x)\n",
919 				cmd, offset);
920 		return -EBADRQC;
921 	}
922 
923 	if (!strncmp(cmd, "srm", 3) ||
924 			!strncmp(cmd, "lrm", 3)) {
925 		if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
926 		    offset == 0x21f0 ||
927 		    (IS_BROADWELL(gvt->gt->i915) &&
928 		     offset == i915_mmio_reg_offset(INSTPM)))
929 			return 0;
930 		else {
931 			gvt_vgpu_err("%s access to register (%x)\n",
932 					cmd, offset);
933 			return -EPERM;
934 		}
935 	}
936 
937 	if (!strncmp(cmd, "lrr-src", 7) ||
938 			!strncmp(cmd, "lrr-dst", 7)) {
939 		if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
940 			return 0;
941 		else {
942 			gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
943 			return -EPERM;
944 		}
945 	}
946 
947 	if (!strncmp(cmd, "pipe_ctrl", 9)) {
948 		/* TODO: add LRI POST logic here */
949 		return 0;
950 	}
951 
952 	if (strncmp(cmd, "lri", 3))
953 		return -EPERM;
954 
955 	/* below are all lri handlers */
956 	vreg = &vgpu_vreg(s->vgpu, offset);
957 
958 	if (is_cmd_update_pdps(offset, s) &&
959 	    cmd_pdp_mmio_update_handler(s, offset, index))
960 		return -EINVAL;
961 
962 	if (offset == i915_mmio_reg_offset(DERRMR) ||
963 		offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
964 		/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
965 		patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
966 	}
967 
968 	if (is_mocs_mmio(offset))
969 		*vreg = cmd_val(s, index + 1);
970 
971 	vreg_old = *vreg;
972 
973 	if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {
974 		u32 cmdval_new, cmdval;
975 		struct intel_gvt_mmio_info *mmio_info;
976 
977 		cmdval = cmd_val(s, index + 1);
978 
979 		mmio_info = intel_gvt_find_mmio_info(gvt, offset);
980 		if (!mmio_info) {
981 			cmdval_new = cmdval;
982 		} else {
983 			u64 ro_mask = mmio_info->ro_mask;
984 			int ret;
985 
986 			if (likely(!ro_mask))
987 				ret = mmio_info->write(s->vgpu, offset,
988 						&cmdval, 4);
989 			else {
990 				gvt_vgpu_err("try to write RO reg %x\n",
991 						offset);
992 				ret = -EBADRQC;
993 			}
994 			if (ret)
995 				return ret;
996 			cmdval_new = *vreg;
997 		}
998 		if (cmdval_new != cmdval)
999 			patch_value(s, cmd_ptr(s, index+1), cmdval_new);
1000 	}
1001 
1002 	/* only patch cmd. restore vreg value if changed in mmio write handler*/
1003 	*vreg = vreg_old;
1004 
1005 	/* TODO
1006 	 * In order to let workload with inhibit context to generate
1007 	 * correct image data into memory, vregs values will be loaded to
1008 	 * hw via LRIs in the workload with inhibit context. But as
1009 	 * indirect context is loaded prior to LRIs in workload, we don't
1010 	 * want reg values specified in indirect context overwritten by
1011 	 * LRIs in workloads. So, when scanning an indirect context, we
1012 	 * update reg values in it into vregs, so LRIs in workload with
1013 	 * inhibit context will restore with correct values
1014 	 */
1015 	if (GRAPHICS_VER(s->engine->i915) == 9 &&
1016 	    intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
1017 	    !strncmp(cmd, "lri", 3)) {
1018 		intel_gvt_read_gpa(s->vgpu,
1019 			s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
1020 		/* check inhibit context */
1021 		if (ctx_sr_ctl & 1) {
1022 			u32 data = cmd_val(s, index + 1);
1023 
1024 			if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
1025 				intel_vgpu_mask_mmio_write(vgpu,
1026 							offset, &data, 4);
1027 			else
1028 				vgpu_vreg(vgpu, offset) = data;
1029 		}
1030 	}
1031 
1032 	return 0;
1033 }
1034 
1035 #define cmd_reg(s, i) \
1036 	(cmd_val(s, i) & GENMASK(22, 2))
1037 
1038 #define cmd_reg_inhibit(s, i) \
1039 	(cmd_val(s, i) & GENMASK(22, 18))
1040 
1041 #define cmd_gma(s, i) \
1042 	(cmd_val(s, i) & GENMASK(31, 2))
1043 
1044 #define cmd_gma_hi(s, i) \
1045 	(cmd_val(s, i) & GENMASK(15, 0))
1046 
cmd_handler_lri(struct parser_exec_state * s)1047 static int cmd_handler_lri(struct parser_exec_state *s)
1048 {
1049 	int i, ret = 0;
1050 	int cmd_len = cmd_length(s);
1051 
1052 	for (i = 1; i < cmd_len; i += 2) {
1053 		if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
1054 			if (s->engine->id == BCS0 &&
1055 			    cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1056 				ret |= 0;
1057 			else
1058 				ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1059 		}
1060 		if (ret)
1061 			break;
1062 		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
1063 		if (ret)
1064 			break;
1065 	}
1066 	return ret;
1067 }
1068 
cmd_handler_lrr(struct parser_exec_state * s)1069 static int cmd_handler_lrr(struct parser_exec_state *s)
1070 {
1071 	int i, ret = 0;
1072 	int cmd_len = cmd_length(s);
1073 
1074 	for (i = 1; i < cmd_len; i += 2) {
1075 		if (IS_BROADWELL(s->engine->i915))
1076 			ret |= ((cmd_reg_inhibit(s, i) ||
1077 				 (cmd_reg_inhibit(s, i + 1)))) ?
1078 				-EBADRQC : 0;
1079 		if (ret)
1080 			break;
1081 		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1082 		if (ret)
1083 			break;
1084 		ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1085 		if (ret)
1086 			break;
1087 	}
1088 	return ret;
1089 }
1090 
1091 static inline int cmd_address_audit(struct parser_exec_state *s,
1092 		unsigned long guest_gma, int op_size, bool index_mode);
1093 
cmd_handler_lrm(struct parser_exec_state * s)1094 static int cmd_handler_lrm(struct parser_exec_state *s)
1095 {
1096 	struct intel_gvt *gvt = s->vgpu->gvt;
1097 	int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1098 	unsigned long gma;
1099 	int i, ret = 0;
1100 	int cmd_len = cmd_length(s);
1101 
1102 	for (i = 1; i < cmd_len;) {
1103 		if (IS_BROADWELL(s->engine->i915))
1104 			ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1105 		if (ret)
1106 			break;
1107 		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1108 		if (ret)
1109 			break;
1110 		if (cmd_val(s, 0) & (1 << 22)) {
1111 			gma = cmd_gma(s, i + 1);
1112 			if (gmadr_bytes == 8)
1113 				gma |= (cmd_gma_hi(s, i + 2)) << 32;
1114 			ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1115 			if (ret)
1116 				break;
1117 		}
1118 		i += gmadr_dw_number(s) + 1;
1119 	}
1120 	return ret;
1121 }
1122 
cmd_handler_srm(struct parser_exec_state * s)1123 static int cmd_handler_srm(struct parser_exec_state *s)
1124 {
1125 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1126 	unsigned long gma;
1127 	int i, ret = 0;
1128 	int cmd_len = cmd_length(s);
1129 
1130 	for (i = 1; i < cmd_len;) {
1131 		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1132 		if (ret)
1133 			break;
1134 		if (cmd_val(s, 0) & (1 << 22)) {
1135 			gma = cmd_gma(s, i + 1);
1136 			if (gmadr_bytes == 8)
1137 				gma |= (cmd_gma_hi(s, i + 2)) << 32;
1138 			ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1139 			if (ret)
1140 				break;
1141 		}
1142 		i += gmadr_dw_number(s) + 1;
1143 	}
1144 	return ret;
1145 }
1146 
1147 struct cmd_interrupt_event {
1148 	int pipe_control_notify;
1149 	int mi_flush_dw;
1150 	int mi_user_interrupt;
1151 };
1152 
1153 static const struct cmd_interrupt_event cmd_interrupt_events[] = {
1154 	[RCS0] = {
1155 		.pipe_control_notify = RCS_PIPE_CONTROL,
1156 		.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1157 		.mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1158 	},
1159 	[BCS0] = {
1160 		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1161 		.mi_flush_dw = BCS_MI_FLUSH_DW,
1162 		.mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1163 	},
1164 	[VCS0] = {
1165 		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1166 		.mi_flush_dw = VCS_MI_FLUSH_DW,
1167 		.mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1168 	},
1169 	[VCS1] = {
1170 		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1171 		.mi_flush_dw = VCS2_MI_FLUSH_DW,
1172 		.mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1173 	},
1174 	[VECS0] = {
1175 		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1176 		.mi_flush_dw = VECS_MI_FLUSH_DW,
1177 		.mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1178 	},
1179 };
1180 
cmd_handler_pipe_control(struct parser_exec_state * s)1181 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1182 {
1183 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1184 	unsigned long gma;
1185 	bool index_mode = false;
1186 	unsigned int post_sync;
1187 	int ret = 0;
1188 	u32 hws_pga, val;
1189 
1190 	post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1191 
1192 	/* LRI post sync */
1193 	if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1194 		ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1195 	/* post sync */
1196 	else if (post_sync) {
1197 		if (post_sync == 2)
1198 			ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1199 		else if (post_sync == 3)
1200 			ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1201 		else if (post_sync == 1) {
1202 			/* check ggtt*/
1203 			if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1204 				gma = cmd_val(s, 2) & GENMASK(31, 3);
1205 				if (gmadr_bytes == 8)
1206 					gma |= (cmd_gma_hi(s, 3)) << 32;
1207 				/* Store Data Index */
1208 				if (cmd_val(s, 1) & (1 << 21))
1209 					index_mode = true;
1210 				ret |= cmd_address_audit(s, gma, sizeof(u64),
1211 						index_mode);
1212 				if (ret)
1213 					return ret;
1214 				if (index_mode) {
1215 					hws_pga = s->vgpu->hws_pga[s->engine->id];
1216 					gma = hws_pga + gma;
1217 					patch_value(s, cmd_ptr(s, 2), gma);
1218 					val = cmd_val(s, 1) & (~(1 << 21));
1219 					patch_value(s, cmd_ptr(s, 1), val);
1220 				}
1221 			}
1222 		}
1223 	}
1224 
1225 	if (ret)
1226 		return ret;
1227 
1228 	if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1229 		set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1230 			s->workload->pending_events);
1231 	return 0;
1232 }
1233 
cmd_handler_mi_user_interrupt(struct parser_exec_state * s)1234 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1235 {
1236 	set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1237 		s->workload->pending_events);
1238 	patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1239 	return 0;
1240 }
1241 
cmd_advance_default(struct parser_exec_state * s)1242 static int cmd_advance_default(struct parser_exec_state *s)
1243 {
1244 	return ip_gma_advance(s, cmd_length(s));
1245 }
1246 
cmd_handler_mi_batch_buffer_end(struct parser_exec_state * s)1247 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1248 {
1249 	int ret;
1250 
1251 	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1252 		s->buf_type = BATCH_BUFFER_INSTRUCTION;
1253 		ret = ip_gma_set(s, s->ret_ip_gma_bb);
1254 		s->buf_addr_type = s->saved_buf_addr_type;
1255 	} else if (s->buf_type == RING_BUFFER_CTX) {
1256 		ret = ip_gma_set(s, s->ring_tail);
1257 	} else {
1258 		s->buf_type = RING_BUFFER_INSTRUCTION;
1259 		s->buf_addr_type = GTT_BUFFER;
1260 		if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1261 			s->ret_ip_gma_ring -= s->ring_size;
1262 		ret = ip_gma_set(s, s->ret_ip_gma_ring);
1263 	}
1264 	return ret;
1265 }
1266 
1267 struct mi_display_flip_command_info {
1268 	int pipe;
1269 	int plane;
1270 	int event;
1271 	i915_reg_t stride_reg;
1272 	i915_reg_t ctrl_reg;
1273 	i915_reg_t surf_reg;
1274 	u64 stride_val;
1275 	u64 tile_val;
1276 	u64 surf_val;
1277 	bool async_flip;
1278 };
1279 
1280 struct plane_code_mapping {
1281 	int pipe;
1282 	int plane;
1283 	int event;
1284 };
1285 
gen8_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1286 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1287 		struct mi_display_flip_command_info *info)
1288 {
1289 	struct drm_i915_private *dev_priv = s->engine->i915;
1290 	struct plane_code_mapping gen8_plane_code[] = {
1291 		[0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1292 		[1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1293 		[2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1294 		[3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1295 		[4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1296 		[5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1297 	};
1298 	u32 dword0, dword1, dword2;
1299 	u32 v;
1300 
1301 	dword0 = cmd_val(s, 0);
1302 	dword1 = cmd_val(s, 1);
1303 	dword2 = cmd_val(s, 2);
1304 
1305 	v = (dword0 & GENMASK(21, 19)) >> 19;
1306 	if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1307 		return -EBADRQC;
1308 
1309 	info->pipe = gen8_plane_code[v].pipe;
1310 	info->plane = gen8_plane_code[v].plane;
1311 	info->event = gen8_plane_code[v].event;
1312 	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1313 	info->tile_val = (dword1 & 0x1);
1314 	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1315 	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1316 
1317 	if (info->plane == PLANE_A) {
1318 		info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1319 		info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
1320 		info->surf_reg = DSPSURF(dev_priv, info->pipe);
1321 	} else if (info->plane == PLANE_B) {
1322 		info->ctrl_reg = SPRCTL(info->pipe);
1323 		info->stride_reg = SPRSTRIDE(info->pipe);
1324 		info->surf_reg = SPRSURF(info->pipe);
1325 	} else {
1326 		drm_WARN_ON(&dev_priv->drm, 1);
1327 		return -EBADRQC;
1328 	}
1329 	return 0;
1330 }
1331 
skl_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1332 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1333 		struct mi_display_flip_command_info *info)
1334 {
1335 	struct drm_i915_private *dev_priv = s->engine->i915;
1336 	struct intel_vgpu *vgpu = s->vgpu;
1337 	u32 dword0 = cmd_val(s, 0);
1338 	u32 dword1 = cmd_val(s, 1);
1339 	u32 dword2 = cmd_val(s, 2);
1340 	u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1341 
1342 	info->plane = PRIMARY_PLANE;
1343 
1344 	switch (plane) {
1345 	case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1346 		info->pipe = PIPE_A;
1347 		info->event = PRIMARY_A_FLIP_DONE;
1348 		break;
1349 	case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1350 		info->pipe = PIPE_B;
1351 		info->event = PRIMARY_B_FLIP_DONE;
1352 		break;
1353 	case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1354 		info->pipe = PIPE_C;
1355 		info->event = PRIMARY_C_FLIP_DONE;
1356 		break;
1357 
1358 	case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1359 		info->pipe = PIPE_A;
1360 		info->event = SPRITE_A_FLIP_DONE;
1361 		info->plane = SPRITE_PLANE;
1362 		break;
1363 	case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1364 		info->pipe = PIPE_B;
1365 		info->event = SPRITE_B_FLIP_DONE;
1366 		info->plane = SPRITE_PLANE;
1367 		break;
1368 	case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1369 		info->pipe = PIPE_C;
1370 		info->event = SPRITE_C_FLIP_DONE;
1371 		info->plane = SPRITE_PLANE;
1372 		break;
1373 
1374 	default:
1375 		gvt_vgpu_err("unknown plane code %d\n", plane);
1376 		return -EBADRQC;
1377 	}
1378 
1379 	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1380 	info->tile_val = (dword1 & GENMASK(2, 0));
1381 	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1382 	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1383 
1384 	info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1385 	info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
1386 	info->surf_reg = DSPSURF(dev_priv, info->pipe);
1387 
1388 	return 0;
1389 }
1390 
gen8_check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1391 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1392 		struct mi_display_flip_command_info *info)
1393 {
1394 	u32 stride, tile;
1395 
1396 	if (!info->async_flip)
1397 		return 0;
1398 
1399 	if (GRAPHICS_VER(s->engine->i915) >= 9) {
1400 		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1401 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1402 				GENMASK(12, 10)) >> 10;
1403 	} else {
1404 		stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1405 				GENMASK(15, 6)) >> 6;
1406 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1407 	}
1408 
1409 	if (stride != info->stride_val)
1410 		gvt_dbg_cmd("cannot change stride during async flip\n");
1411 
1412 	if (tile != info->tile_val)
1413 		gvt_dbg_cmd("cannot change tile during async flip\n");
1414 
1415 	return 0;
1416 }
1417 
gen8_update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1418 static int gen8_update_plane_mmio_from_mi_display_flip(
1419 		struct parser_exec_state *s,
1420 		struct mi_display_flip_command_info *info)
1421 {
1422 	struct drm_i915_private *dev_priv = s->engine->i915;
1423 	struct intel_vgpu *vgpu = s->vgpu;
1424 
1425 	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1426 		      info->surf_val << 12);
1427 	if (GRAPHICS_VER(dev_priv) >= 9) {
1428 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1429 			      info->stride_val);
1430 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1431 			      info->tile_val << 10);
1432 	} else {
1433 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1434 			      info->stride_val << 6);
1435 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1436 			      info->tile_val << 10);
1437 	}
1438 
1439 	if (info->plane == PLANE_PRIMARY)
1440 		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++;
1441 
1442 	if (info->async_flip)
1443 		intel_vgpu_trigger_virtual_event(vgpu, info->event);
1444 	else
1445 		set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1446 
1447 	return 0;
1448 }
1449 
decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1450 static int decode_mi_display_flip(struct parser_exec_state *s,
1451 		struct mi_display_flip_command_info *info)
1452 {
1453 	if (IS_BROADWELL(s->engine->i915))
1454 		return gen8_decode_mi_display_flip(s, info);
1455 	if (GRAPHICS_VER(s->engine->i915) >= 9)
1456 		return skl_decode_mi_display_flip(s, info);
1457 
1458 	return -ENODEV;
1459 }
1460 
check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1461 static int check_mi_display_flip(struct parser_exec_state *s,
1462 		struct mi_display_flip_command_info *info)
1463 {
1464 	return gen8_check_mi_display_flip(s, info);
1465 }
1466 
update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1467 static int update_plane_mmio_from_mi_display_flip(
1468 		struct parser_exec_state *s,
1469 		struct mi_display_flip_command_info *info)
1470 {
1471 	return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1472 }
1473 
cmd_handler_mi_display_flip(struct parser_exec_state * s)1474 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1475 {
1476 	struct mi_display_flip_command_info info;
1477 	struct intel_vgpu *vgpu = s->vgpu;
1478 	int ret;
1479 	int i;
1480 	int len = cmd_length(s);
1481 	u32 valid_len = CMD_LEN(1);
1482 
1483 	/* Flip Type == Stereo 3D Flip */
1484 	if (DWORD_FIELD(2, 1, 0) == 2)
1485 		valid_len++;
1486 	ret = gvt_check_valid_cmd_length(cmd_length(s),
1487 			valid_len);
1488 	if (ret)
1489 		return ret;
1490 
1491 	ret = decode_mi_display_flip(s, &info);
1492 	if (ret) {
1493 		gvt_vgpu_err("fail to decode MI display flip command\n");
1494 		return ret;
1495 	}
1496 
1497 	ret = check_mi_display_flip(s, &info);
1498 	if (ret) {
1499 		gvt_vgpu_err("invalid MI display flip command\n");
1500 		return ret;
1501 	}
1502 
1503 	ret = update_plane_mmio_from_mi_display_flip(s, &info);
1504 	if (ret) {
1505 		gvt_vgpu_err("fail to update plane mmio\n");
1506 		return ret;
1507 	}
1508 
1509 	for (i = 0; i < len; i++)
1510 		patch_value(s, cmd_ptr(s, i), MI_NOOP);
1511 	return 0;
1512 }
1513 
is_wait_for_flip_pending(u32 cmd)1514 static bool is_wait_for_flip_pending(u32 cmd)
1515 {
1516 	return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1517 			MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1518 			MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1519 			MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1520 			MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1521 			MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1522 }
1523 
cmd_handler_mi_wait_for_event(struct parser_exec_state * s)1524 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1525 {
1526 	u32 cmd = cmd_val(s, 0);
1527 
1528 	if (!is_wait_for_flip_pending(cmd))
1529 		return 0;
1530 
1531 	patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1532 	return 0;
1533 }
1534 
get_gma_bb_from_cmd(struct parser_exec_state * s,int index)1535 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1536 {
1537 	unsigned long addr;
1538 	unsigned long gma_high, gma_low;
1539 	struct intel_vgpu *vgpu = s->vgpu;
1540 	int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1541 
1542 	if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1543 		gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1544 		return INTEL_GVT_INVALID_ADDR;
1545 	}
1546 
1547 	gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1548 	if (gmadr_bytes == 4) {
1549 		addr = gma_low;
1550 	} else {
1551 		gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1552 		addr = (((unsigned long)gma_high) << 32) | gma_low;
1553 	}
1554 	return addr;
1555 }
1556 
cmd_address_audit(struct parser_exec_state * s,unsigned long guest_gma,int op_size,bool index_mode)1557 static inline int cmd_address_audit(struct parser_exec_state *s,
1558 		unsigned long guest_gma, int op_size, bool index_mode)
1559 {
1560 	struct intel_vgpu *vgpu = s->vgpu;
1561 	u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1562 	int i;
1563 	int ret;
1564 
1565 	if (op_size > max_surface_size) {
1566 		gvt_vgpu_err("command address audit fail name %s\n",
1567 			s->info->name);
1568 		return -EFAULT;
1569 	}
1570 
1571 	if (index_mode)	{
1572 		if (guest_gma >= I915_GTT_PAGE_SIZE) {
1573 			ret = -EFAULT;
1574 			goto err;
1575 		}
1576 	} else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1577 		ret = -EFAULT;
1578 		goto err;
1579 	}
1580 
1581 	return 0;
1582 
1583 err:
1584 	gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1585 			s->info->name, guest_gma, op_size);
1586 
1587 	pr_err("cmd dump: ");
1588 	for (i = 0; i < cmd_length(s); i++) {
1589 		if (!(i % 4))
1590 			pr_err("\n%08x ", cmd_val(s, i));
1591 		else
1592 			pr_err("%08x ", cmd_val(s, i));
1593 	}
1594 	pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1595 			vgpu->id,
1596 			vgpu_aperture_gmadr_base(vgpu),
1597 			vgpu_aperture_gmadr_end(vgpu),
1598 			vgpu_hidden_gmadr_base(vgpu),
1599 			vgpu_hidden_gmadr_end(vgpu));
1600 	return ret;
1601 }
1602 
cmd_handler_mi_store_data_imm(struct parser_exec_state * s)1603 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1604 {
1605 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1606 	int op_size = (cmd_length(s) - 3) * sizeof(u32);
1607 	int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1608 	unsigned long gma, gma_low, gma_high;
1609 	u32 valid_len = CMD_LEN(2);
1610 	int ret = 0;
1611 
1612 	/* check ppggt */
1613 	if (!(cmd_val(s, 0) & (1 << 22)))
1614 		return 0;
1615 
1616 	/* check if QWORD */
1617 	if (DWORD_FIELD(0, 21, 21))
1618 		valid_len++;
1619 	ret = gvt_check_valid_cmd_length(cmd_length(s),
1620 			valid_len);
1621 	if (ret)
1622 		return ret;
1623 
1624 	gma = cmd_val(s, 2) & GENMASK(31, 2);
1625 
1626 	if (gmadr_bytes == 8) {
1627 		gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1628 		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1629 		gma = (gma_high << 32) | gma_low;
1630 		core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1631 	}
1632 	ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1633 	return ret;
1634 }
1635 
unexpected_cmd(struct parser_exec_state * s)1636 static inline int unexpected_cmd(struct parser_exec_state *s)
1637 {
1638 	struct intel_vgpu *vgpu = s->vgpu;
1639 
1640 	gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1641 
1642 	return -EBADRQC;
1643 }
1644 
cmd_handler_mi_semaphore_wait(struct parser_exec_state * s)1645 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1646 {
1647 	return unexpected_cmd(s);
1648 }
1649 
cmd_handler_mi_report_perf_count(struct parser_exec_state * s)1650 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1651 {
1652 	return unexpected_cmd(s);
1653 }
1654 
cmd_handler_mi_op_2e(struct parser_exec_state * s)1655 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1656 {
1657 	return unexpected_cmd(s);
1658 }
1659 
cmd_handler_mi_op_2f(struct parser_exec_state * s)1660 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1661 {
1662 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1663 	int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1664 			sizeof(u32);
1665 	unsigned long gma, gma_high;
1666 	u32 valid_len = CMD_LEN(1);
1667 	int ret = 0;
1668 
1669 	if (!(cmd_val(s, 0) & (1 << 22)))
1670 		return ret;
1671 
1672 	/* check inline data */
1673 	if (cmd_val(s, 0) & BIT(18))
1674 		valid_len = CMD_LEN(9);
1675 	ret = gvt_check_valid_cmd_length(cmd_length(s),
1676 			valid_len);
1677 	if (ret)
1678 		return ret;
1679 
1680 	gma = cmd_val(s, 1) & GENMASK(31, 2);
1681 	if (gmadr_bytes == 8) {
1682 		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1683 		gma = (gma_high << 32) | gma;
1684 	}
1685 	ret = cmd_address_audit(s, gma, op_size, false);
1686 	return ret;
1687 }
1688 
cmd_handler_mi_store_data_index(struct parser_exec_state * s)1689 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1690 {
1691 	return unexpected_cmd(s);
1692 }
1693 
cmd_handler_mi_clflush(struct parser_exec_state * s)1694 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1695 {
1696 	return unexpected_cmd(s);
1697 }
1698 
cmd_handler_mi_conditional_batch_buffer_end(struct parser_exec_state * s)1699 static int cmd_handler_mi_conditional_batch_buffer_end(
1700 		struct parser_exec_state *s)
1701 {
1702 	return unexpected_cmd(s);
1703 }
1704 
cmd_handler_mi_update_gtt(struct parser_exec_state * s)1705 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1706 {
1707 	return unexpected_cmd(s);
1708 }
1709 
cmd_handler_mi_flush_dw(struct parser_exec_state * s)1710 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1711 {
1712 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1713 	unsigned long gma;
1714 	bool index_mode = false;
1715 	int ret = 0;
1716 	u32 hws_pga, val;
1717 	u32 valid_len = CMD_LEN(2);
1718 
1719 	ret = gvt_check_valid_cmd_length(cmd_length(s),
1720 			valid_len);
1721 	if (ret) {
1722 		/* Check again for Qword */
1723 		ret = gvt_check_valid_cmd_length(cmd_length(s),
1724 			++valid_len);
1725 		return ret;
1726 	}
1727 
1728 	/* Check post-sync and ppgtt bit */
1729 	if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1730 		gma = cmd_val(s, 1) & GENMASK(31, 3);
1731 		if (gmadr_bytes == 8)
1732 			gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1733 		/* Store Data Index */
1734 		if (cmd_val(s, 0) & (1 << 21))
1735 			index_mode = true;
1736 		ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1737 		if (ret)
1738 			return ret;
1739 		if (index_mode) {
1740 			hws_pga = s->vgpu->hws_pga[s->engine->id];
1741 			gma = hws_pga + gma;
1742 			patch_value(s, cmd_ptr(s, 1), gma);
1743 			val = cmd_val(s, 0) & (~(1 << 21));
1744 			patch_value(s, cmd_ptr(s, 0), val);
1745 		}
1746 	}
1747 	/* Check notify bit */
1748 	if ((cmd_val(s, 0) & (1 << 8)))
1749 		set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1750 			s->workload->pending_events);
1751 	return ret;
1752 }
1753 
addr_type_update_snb(struct parser_exec_state * s)1754 static void addr_type_update_snb(struct parser_exec_state *s)
1755 {
1756 	if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1757 			(BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1758 		s->buf_addr_type = PPGTT_BUFFER;
1759 	}
1760 }
1761 
1762 
copy_gma_to_hva(struct intel_vgpu * vgpu,struct intel_vgpu_mm * mm,unsigned long gma,unsigned long end_gma,void * va)1763 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1764 		unsigned long gma, unsigned long end_gma, void *va)
1765 {
1766 	unsigned long copy_len, offset;
1767 	unsigned long len = 0;
1768 	unsigned long gpa;
1769 
1770 	while (gma != end_gma) {
1771 		gpa = intel_vgpu_gma_to_gpa(mm, gma);
1772 		if (gpa == INTEL_GVT_INVALID_ADDR) {
1773 			gvt_vgpu_err("invalid gma address: %lx\n", gma);
1774 			return -EFAULT;
1775 		}
1776 
1777 		offset = gma & (I915_GTT_PAGE_SIZE - 1);
1778 
1779 		copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1780 			I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1781 
1782 		intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
1783 
1784 		len += copy_len;
1785 		gma += copy_len;
1786 	}
1787 	return len;
1788 }
1789 
1790 
1791 /*
1792  * Check whether a batch buffer needs to be scanned. Currently
1793  * the only criteria is based on privilege.
1794  */
batch_buffer_needs_scan(struct parser_exec_state * s)1795 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1796 {
1797 	/* Decide privilege based on address space */
1798 	if (cmd_val(s, 0) & BIT(8) &&
1799 	    !(s->vgpu->scan_nonprivbb & s->engine->mask))
1800 		return 0;
1801 
1802 	return 1;
1803 }
1804 
repr_addr_type(unsigned int type)1805 static const char *repr_addr_type(unsigned int type)
1806 {
1807 	return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1808 }
1809 
find_bb_size(struct parser_exec_state * s,unsigned long * bb_size,unsigned long * bb_end_cmd_offset)1810 static int find_bb_size(struct parser_exec_state *s,
1811 			unsigned long *bb_size,
1812 			unsigned long *bb_end_cmd_offset)
1813 {
1814 	unsigned long gma = 0;
1815 	const struct cmd_info *info;
1816 	u32 cmd_len = 0;
1817 	bool bb_end = false;
1818 	struct intel_vgpu *vgpu = s->vgpu;
1819 	u32 cmd;
1820 	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1821 		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1822 
1823 	*bb_size = 0;
1824 	*bb_end_cmd_offset = 0;
1825 
1826 	/* get the start gm address of the batch buffer */
1827 	gma = get_gma_bb_from_cmd(s, 1);
1828 	if (gma == INTEL_GVT_INVALID_ADDR)
1829 		return -EFAULT;
1830 
1831 	cmd = cmd_val(s, 0);
1832 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1833 	if (info == NULL) {
1834 		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1835 			     cmd, get_opcode(cmd, s->engine),
1836 			     repr_addr_type(s->buf_addr_type),
1837 			     s->engine->name, s->workload);
1838 		return -EBADRQC;
1839 	}
1840 	do {
1841 		if (copy_gma_to_hva(s->vgpu, mm,
1842 				    gma, gma + 4, &cmd) < 0)
1843 			return -EFAULT;
1844 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1845 		if (info == NULL) {
1846 			gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1847 				     cmd, get_opcode(cmd, s->engine),
1848 				     repr_addr_type(s->buf_addr_type),
1849 				     s->engine->name, s->workload);
1850 			return -EBADRQC;
1851 		}
1852 
1853 		if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1854 			bb_end = true;
1855 		} else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1856 			if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1857 				/* chained batch buffer */
1858 				bb_end = true;
1859 		}
1860 
1861 		if (bb_end)
1862 			*bb_end_cmd_offset = *bb_size;
1863 
1864 		cmd_len = get_cmd_length(info, cmd) << 2;
1865 		*bb_size += cmd_len;
1866 		gma += cmd_len;
1867 	} while (!bb_end);
1868 
1869 	return 0;
1870 }
1871 
audit_bb_end(struct parser_exec_state * s,void * va)1872 static int audit_bb_end(struct parser_exec_state *s, void *va)
1873 {
1874 	struct intel_vgpu *vgpu = s->vgpu;
1875 	u32 cmd = *(u32 *)va;
1876 	const struct cmd_info *info;
1877 
1878 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1879 	if (info == NULL) {
1880 		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1881 			     cmd, get_opcode(cmd, s->engine),
1882 			     repr_addr_type(s->buf_addr_type),
1883 			     s->engine->name, s->workload);
1884 		return -EBADRQC;
1885 	}
1886 
1887 	if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1888 	    ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1889 	     (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1890 		return 0;
1891 
1892 	return -EBADRQC;
1893 }
1894 
perform_bb_shadow(struct parser_exec_state * s)1895 static int perform_bb_shadow(struct parser_exec_state *s)
1896 {
1897 	struct intel_vgpu *vgpu = s->vgpu;
1898 	struct intel_vgpu_shadow_bb *bb;
1899 	unsigned long gma = 0;
1900 	unsigned long bb_size;
1901 	unsigned long bb_end_cmd_offset;
1902 	int ret = 0;
1903 	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1904 		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1905 	unsigned long start_offset = 0;
1906 
1907 	/* get the start gm address of the batch buffer */
1908 	gma = get_gma_bb_from_cmd(s, 1);
1909 	if (gma == INTEL_GVT_INVALID_ADDR)
1910 		return -EFAULT;
1911 
1912 	ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1913 	if (ret)
1914 		return ret;
1915 
1916 	bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1917 	if (!bb)
1918 		return -ENOMEM;
1919 
1920 	bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1921 
1922 	/* the start_offset stores the batch buffer's start gma's
1923 	 * offset relative to page boundary. so for non-privileged batch
1924 	 * buffer, the shadowed gem object holds exactly the same page
1925 	 * layout as original gem object. This is for the convience of
1926 	 * replacing the whole non-privilged batch buffer page to this
1927 	 * shadowed one in PPGTT at the same gma address. (this replacing
1928 	 * action is not implemented yet now, but may be necessary in
1929 	 * future).
1930 	 * for prileged batch buffer, we just change start gma address to
1931 	 * that of shadowed page.
1932 	 */
1933 	if (bb->ppgtt)
1934 		start_offset = gma & ~I915_GTT_PAGE_MASK;
1935 
1936 	bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1937 					       round_up(bb_size + start_offset,
1938 							PAGE_SIZE));
1939 	if (IS_ERR(bb->obj)) {
1940 		ret = PTR_ERR(bb->obj);
1941 		goto err_free_bb;
1942 	}
1943 
1944 	bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1945 	if (IS_ERR(bb->va)) {
1946 		ret = PTR_ERR(bb->va);
1947 		goto err_free_obj;
1948 	}
1949 
1950 	ret = copy_gma_to_hva(s->vgpu, mm,
1951 			      gma, gma + bb_size,
1952 			      bb->va + start_offset);
1953 	if (ret < 0) {
1954 		gvt_vgpu_err("fail to copy guest ring buffer\n");
1955 		ret = -EFAULT;
1956 		goto err_unmap;
1957 	}
1958 
1959 	ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1960 	if (ret)
1961 		goto err_unmap;
1962 
1963 	i915_gem_object_unlock(bb->obj);
1964 	INIT_LIST_HEAD(&bb->list);
1965 	list_add(&bb->list, &s->workload->shadow_bb);
1966 
1967 	bb->bb_start_cmd_va = s->ip_va;
1968 
1969 	if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1970 		bb->bb_offset = s->ip_va - s->rb_va;
1971 	else
1972 		bb->bb_offset = 0;
1973 
1974 	/*
1975 	 * ip_va saves the virtual address of the shadow batch buffer, while
1976 	 * ip_gma saves the graphics address of the original batch buffer.
1977 	 * As the shadow batch buffer is just a copy from the originial one,
1978 	 * it should be right to use shadow batch buffer'va and original batch
1979 	 * buffer's gma in pair. After all, we don't want to pin the shadow
1980 	 * buffer here (too early).
1981 	 */
1982 	s->ip_va = bb->va + start_offset;
1983 	s->ip_gma = gma;
1984 	return 0;
1985 err_unmap:
1986 	i915_gem_object_unpin_map(bb->obj);
1987 err_free_obj:
1988 	i915_gem_object_put(bb->obj);
1989 err_free_bb:
1990 	kfree(bb);
1991 	return ret;
1992 }
1993 
cmd_handler_mi_batch_buffer_start(struct parser_exec_state * s)1994 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1995 {
1996 	bool second_level;
1997 	int ret = 0;
1998 	struct intel_vgpu *vgpu = s->vgpu;
1999 
2000 	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
2001 		gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
2002 		return -EFAULT;
2003 	}
2004 
2005 	second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
2006 	if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
2007 		gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
2008 		return -EFAULT;
2009 	}
2010 
2011 	s->saved_buf_addr_type = s->buf_addr_type;
2012 	addr_type_update_snb(s);
2013 	if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2014 		s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
2015 		s->buf_type = BATCH_BUFFER_INSTRUCTION;
2016 	} else if (second_level) {
2017 		s->buf_type = BATCH_BUFFER_2ND_LEVEL;
2018 		s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
2019 		s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
2020 	}
2021 
2022 	if (batch_buffer_needs_scan(s)) {
2023 		ret = perform_bb_shadow(s);
2024 		if (ret < 0)
2025 			gvt_vgpu_err("invalid shadow batch buffer\n");
2026 	} else {
2027 		/* emulate a batch buffer end to do return right */
2028 		ret = cmd_handler_mi_batch_buffer_end(s);
2029 		if (ret < 0)
2030 			return ret;
2031 	}
2032 	return ret;
2033 }
2034 
2035 static int mi_noop_index;
2036 
2037 static const struct cmd_info cmd_info[] = {
2038 	{"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2039 
2040 	{"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2041 		0, 1, NULL},
2042 
2043 	{"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2044 		0, 1, cmd_handler_mi_user_interrupt},
2045 
2046 	{"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2047 		D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2048 
2049 	{"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2050 
2051 	{"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2052 		NULL},
2053 
2054 	{"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2055 		NULL},
2056 
2057 	{"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2058 		NULL},
2059 
2060 	{"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2061 		NULL},
2062 
2063 	{"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2064 		D_ALL, 0, 1, NULL},
2065 
2066 	{"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2067 		F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2068 		cmd_handler_mi_batch_buffer_end},
2069 
2070 	{"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2071 		0, 1, NULL},
2072 
2073 	{"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2074 		NULL},
2075 
2076 	{"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2077 		D_ALL, 0, 1, NULL},
2078 
2079 	{"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2080 		NULL},
2081 
2082 	{"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2083 		NULL},
2084 
2085 	{"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2086 		R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2087 
2088 	{"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2089 		R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2090 
2091 	{"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2092 
2093 	{"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2094 		D_ALL, 0, 8, NULL, CMD_LEN(0)},
2095 
2096 	{"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2097 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2098 		NULL, CMD_LEN(0)},
2099 
2100 	{"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2101 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2102 		8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2103 
2104 	{"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2105 		ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2106 
2107 	{"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2108 		0, 8, cmd_handler_mi_store_data_index},
2109 
2110 	{"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2111 		D_ALL, 0, 8, cmd_handler_lri},
2112 
2113 	{"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2114 		cmd_handler_mi_update_gtt},
2115 
2116 	{"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2117 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2118 		cmd_handler_srm, CMD_LEN(2)},
2119 
2120 	{"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2121 		cmd_handler_mi_flush_dw},
2122 
2123 	{"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2124 		10, cmd_handler_mi_clflush},
2125 
2126 	{"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2127 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2128 		cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2129 
2130 	{"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2131 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2132 		cmd_handler_lrm, CMD_LEN(2)},
2133 
2134 	{"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2135 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2136 		cmd_handler_lrr, CMD_LEN(1)},
2137 
2138 	{"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2139 		F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2140 		8, NULL, CMD_LEN(2)},
2141 
2142 	{"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2143 		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2144 
2145 	{"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2146 		ADDR_FIX_1(2), 8, NULL},
2147 
2148 	{"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2149 		ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2150 
2151 	{"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2152 		8, cmd_handler_mi_op_2f},
2153 
2154 	{"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2155 		F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2156 		cmd_handler_mi_batch_buffer_start},
2157 
2158 	{"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2159 		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2160 		cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2161 
2162 	{"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2163 		R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2164 
2165 	{"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2166 		ADDR_FIX_2(4, 7), 8, NULL},
2167 
2168 	{"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2169 		0, 8, NULL},
2170 
2171 	{"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2172 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2173 
2174 	{"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2175 
2176 	{"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2177 		0, 8, NULL},
2178 
2179 	{"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2180 		ADDR_FIX_1(3), 8, NULL},
2181 
2182 	{"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2183 		D_ALL, 0, 8, NULL},
2184 
2185 	{"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2186 		ADDR_FIX_1(4), 8, NULL},
2187 
2188 	{"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2189 		ADDR_FIX_2(4, 5), 8, NULL},
2190 
2191 	{"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2192 		ADDR_FIX_1(4), 8, NULL},
2193 
2194 	{"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2195 		ADDR_FIX_2(4, 7), 8, NULL},
2196 
2197 	{"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2198 		D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2199 
2200 	{"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2201 
2202 	{"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2203 		D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2204 
2205 	{"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2206 		R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2207 
2208 	{"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2209 		OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2210 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2211 
2212 	{"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2213 		D_ALL, ADDR_FIX_1(4), 8, NULL},
2214 
2215 	{"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2216 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2217 
2218 	{"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2219 		D_ALL, ADDR_FIX_1(4), 8, NULL},
2220 
2221 	{"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2222 		D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2223 
2224 	{"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2225 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2226 
2227 	{"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2228 		OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2229 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2230 
2231 	{"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2232 		ADDR_FIX_2(4, 5), 8, NULL},
2233 
2234 	{"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2235 		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2236 
2237 	{"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2238 		OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2239 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2240 
2241 	{"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2242 		OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2243 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2244 
2245 	{"3DSTATE_BLEND_STATE_POINTERS",
2246 		OP_3DSTATE_BLEND_STATE_POINTERS,
2247 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2248 
2249 	{"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2250 		OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2251 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2252 
2253 	{"3DSTATE_BINDING_TABLE_POINTERS_VS",
2254 		OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2255 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2256 
2257 	{"3DSTATE_BINDING_TABLE_POINTERS_HS",
2258 		OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2259 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2260 
2261 	{"3DSTATE_BINDING_TABLE_POINTERS_DS",
2262 		OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2263 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2264 
2265 	{"3DSTATE_BINDING_TABLE_POINTERS_GS",
2266 		OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2267 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2268 
2269 	{"3DSTATE_BINDING_TABLE_POINTERS_PS",
2270 		OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2271 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2272 
2273 	{"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2274 		OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2275 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2276 
2277 	{"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2278 		OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2279 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2280 
2281 	{"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2282 		OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2283 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2284 
2285 	{"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2286 		OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2287 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2288 
2289 	{"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2290 		OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2291 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2292 
2293 	{"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2294 		0, 8, NULL},
2295 
2296 	{"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2297 		0, 8, NULL},
2298 
2299 	{"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2300 		0, 8, NULL},
2301 
2302 	{"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2303 		0, 8, NULL},
2304 
2305 	{"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2306 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2307 
2308 	{"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2309 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2310 
2311 	{"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2312 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2313 
2314 	{"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2315 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2316 
2317 	{"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2318 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2319 
2320 	{"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2321 		F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2322 
2323 	{"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2324 		F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2325 
2326 	{"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2327 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2328 
2329 	{"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2330 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2331 
2332 	{"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2333 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2334 
2335 	{"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2336 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2337 
2338 	{"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2339 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2340 
2341 	{"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2342 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2343 
2344 	{"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2345 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2346 
2347 	{"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2348 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2349 
2350 	{"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2351 		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2352 
2353 	{"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2354 		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2355 
2356 	{"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2357 		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2358 
2359 	{"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2360 		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2361 
2362 	{"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2363 		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2364 
2365 	{"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2366 		D_BDW_PLUS, 0, 8, NULL},
2367 
2368 	{"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2369 		NULL},
2370 
2371 	{"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2372 		D_BDW_PLUS, 0, 8, NULL},
2373 
2374 	{"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2375 		D_BDW_PLUS, 0, 8, NULL},
2376 
2377 	{"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2378 		8, NULL},
2379 
2380 	{"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2381 		R_RCS, D_BDW_PLUS, 0, 8, NULL},
2382 
2383 	{"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2384 		8, NULL},
2385 
2386 	{"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2387 		NULL},
2388 
2389 	{"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2390 		NULL},
2391 
2392 	{"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2393 		NULL},
2394 
2395 	{"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2396 		D_BDW_PLUS, 0, 8, NULL},
2397 
2398 	{"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2399 		R_RCS, D_ALL, 0, 8, NULL},
2400 
2401 	{"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2402 		D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2403 
2404 	{"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2405 		R_RCS, D_ALL, 0, 1, NULL},
2406 
2407 	{"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2408 
2409 	{"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2410 		R_RCS, D_ALL, 0, 8, NULL},
2411 
2412 	{"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2413 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2414 
2415 	{"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2416 
2417 	{"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2418 
2419 	{"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2420 
2421 	{"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2422 		D_BDW_PLUS, 0, 8, NULL},
2423 
2424 	{"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2425 		D_BDW_PLUS, 0, 8, NULL},
2426 
2427 	{"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2428 		D_ALL, 0, 8, NULL},
2429 
2430 	{"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2431 		D_BDW_PLUS, 0, 8, NULL},
2432 
2433 	{"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2434 		D_BDW_PLUS, 0, 8, NULL},
2435 
2436 	{"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2437 
2438 	{"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2439 
2440 	{"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2441 
2442 	{"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2443 		D_ALL, 0, 8, NULL},
2444 
2445 	{"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2446 
2447 	{"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2448 
2449 	{"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2450 		R_RCS, D_ALL, 0, 8, NULL},
2451 
2452 	{"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2453 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2454 
2455 	{"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2456 		0, 8, NULL},
2457 
2458 	{"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2459 		D_ALL, ADDR_FIX_1(2), 8, NULL},
2460 
2461 	{"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2462 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2463 
2464 	{"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2465 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2466 
2467 	{"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2468 		D_ALL, 0, 8, NULL},
2469 
2470 	{"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2471 		D_ALL, 0, 8, NULL},
2472 
2473 	{"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2474 		D_ALL, 0, 8, NULL},
2475 
2476 	{"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2477 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2478 
2479 	{"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2480 		D_BDW_PLUS, 0, 8, NULL},
2481 
2482 	{"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2483 		D_ALL, ADDR_FIX_1(2), 8, NULL},
2484 
2485 	{"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2486 		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2487 
2488 	{"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2489 		R_RCS, D_ALL, 0, 8, NULL},
2490 
2491 	{"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2492 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2493 
2494 	{"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2495 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2496 
2497 	{"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2498 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2499 
2500 	{"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2501 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2502 
2503 	{"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2504 		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2505 
2506 	{"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2507 		R_RCS, D_ALL, 0, 8, NULL},
2508 
2509 	{"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2510 		D_ALL, 0, 9, NULL},
2511 
2512 	{"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2513 		ADDR_FIX_2(2, 4), 8, NULL},
2514 
2515 	{"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2516 		OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2517 		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2518 
2519 	{"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2520 		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2521 
2522 	{"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2523 		OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2524 		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2525 
2526 	{"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2527 		D_BDW_PLUS, 0, 8, NULL},
2528 
2529 	{"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2530 		ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2531 
2532 	{"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2533 
2534 	{"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2535 		1, NULL},
2536 
2537 	{"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2538 		ADDR_FIX_1(1), 8, NULL},
2539 
2540 	{"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2541 
2542 	{"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2543 		ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2544 
2545 	{"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2546 		ADDR_FIX_1(1), 8, NULL},
2547 
2548 	{"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2549 		F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2550 
2551 	{"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2552 
2553 	{"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2554 
2555 	{"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2556 		0, 8, NULL},
2557 
2558 	{"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2559 		D_SKL_PLUS, 0, 8, NULL},
2560 
2561 	{"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2562 		F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2563 
2564 	{"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2565 		0, 16, NULL},
2566 
2567 	{"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2568 		0, 16, NULL},
2569 
2570 	{"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2571 		0, 16, NULL},
2572 
2573 	{"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2574 
2575 	{"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2576 		0, 16, NULL},
2577 
2578 	{"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2579 		0, 16, NULL},
2580 
2581 	{"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2582 		0, 16, NULL},
2583 
2584 	{"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2585 		0, 8, NULL},
2586 
2587 	{"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2588 		NULL},
2589 
2590 	{"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2591 		F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2592 
2593 	{"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2594 		R_VCS, D_ALL, 0, 12, NULL},
2595 
2596 	{"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2597 		R_VCS, D_ALL, 0, 12, NULL},
2598 
2599 	{"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2600 		R_VCS, D_BDW_PLUS, 0, 12, NULL},
2601 
2602 	{"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2603 		F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2604 
2605 	{"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2606 		F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2607 
2608 	{"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2609 
2610 	{"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2611 		R_VCS, D_ALL, 0, 12, NULL},
2612 
2613 	{"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2614 		R_VCS, D_ALL, 0, 12, NULL},
2615 
2616 	{"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2617 		R_VCS, D_ALL, 0, 12, NULL},
2618 
2619 	{"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2620 		R_VCS, D_ALL, 0, 12, NULL},
2621 
2622 	{"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2623 		R_VCS, D_ALL, 0, 12, NULL},
2624 
2625 	{"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2626 		R_VCS, D_ALL, 0, 12, NULL},
2627 
2628 	{"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2629 		R_VCS, D_ALL, 0, 6, NULL},
2630 
2631 	{"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2632 		R_VCS, D_ALL, 0, 12, NULL},
2633 
2634 	{"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2635 		R_VCS, D_ALL, 0, 12, NULL},
2636 
2637 	{"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2638 		R_VCS, D_ALL, 0, 12, NULL},
2639 
2640 	{"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2641 		R_VCS, D_ALL, 0, 12, NULL},
2642 
2643 	{"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2644 		R_VCS, D_ALL, 0, 12, NULL},
2645 
2646 	{"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2647 		R_VCS, D_ALL, 0, 12, NULL},
2648 
2649 	{"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2650 		R_VCS, D_ALL, 0, 12, NULL},
2651 	{"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2652 		R_VCS, D_ALL, 0, 12, NULL},
2653 
2654 	{"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2655 		R_VCS, D_ALL, 0, 12, NULL},
2656 
2657 	{"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2658 		R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2659 
2660 	{"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2661 		R_VCS, D_ALL, 0, 12, NULL},
2662 
2663 	{"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2664 		R_VCS, D_ALL, 0, 12, NULL},
2665 
2666 	{"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2667 		R_VCS, D_ALL, 0, 12, NULL},
2668 
2669 	{"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2670 		R_VCS, D_ALL, 0, 12, NULL},
2671 
2672 	{"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2673 		R_VCS, D_ALL, 0, 12, NULL},
2674 
2675 	{"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2676 		R_VCS, D_ALL, 0, 12, NULL},
2677 
2678 	{"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2679 		R_VCS, D_ALL, 0, 12, NULL},
2680 
2681 	{"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2682 		R_VCS, D_ALL, 0, 12, NULL},
2683 
2684 	{"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2685 		R_VCS, D_ALL, 0, 12, NULL},
2686 
2687 	{"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2688 		R_VCS, D_ALL, 0, 12, NULL},
2689 
2690 	{"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2691 		R_VCS, D_ALL, 0, 12, NULL},
2692 
2693 	{"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2694 		0, 16, NULL},
2695 
2696 	{"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2697 
2698 	{"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2699 
2700 	{"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2701 		R_VCS, D_ALL, 0, 12, NULL},
2702 
2703 	{"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2704 		R_VCS, D_ALL, 0, 12, NULL},
2705 
2706 	{"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2707 		R_VCS, D_ALL, 0, 12, NULL},
2708 
2709 	{"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2710 
2711 	{"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2712 		0, 12, NULL},
2713 
2714 	{"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2715 		0, 12, NULL},
2716 };
2717 
add_cmd_entry(struct intel_gvt * gvt,struct cmd_entry * e)2718 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2719 {
2720 	hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2721 }
2722 
2723 /* call the cmd handler, and advance ip */
cmd_parser_exec(struct parser_exec_state * s)2724 static int cmd_parser_exec(struct parser_exec_state *s)
2725 {
2726 	struct intel_vgpu *vgpu = s->vgpu;
2727 	const struct cmd_info *info;
2728 	u32 cmd;
2729 	int ret = 0;
2730 
2731 	cmd = cmd_val(s, 0);
2732 
2733 	/* fastpath for MI_NOOP */
2734 	if (cmd == MI_NOOP)
2735 		info = &cmd_info[mi_noop_index];
2736 	else
2737 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2738 
2739 	if (info == NULL) {
2740 		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2741 			     cmd, get_opcode(cmd, s->engine),
2742 			     repr_addr_type(s->buf_addr_type),
2743 			     s->engine->name, s->workload);
2744 		return -EBADRQC;
2745 	}
2746 
2747 	s->info = info;
2748 
2749 	trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2750 			  cmd_length(s), s->buf_type, s->buf_addr_type,
2751 			  s->workload, info->name);
2752 
2753 	if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2754 		ret = gvt_check_valid_cmd_length(cmd_length(s),
2755 						 info->valid_len);
2756 		if (ret)
2757 			return ret;
2758 	}
2759 
2760 	if (info->handler) {
2761 		ret = info->handler(s);
2762 		if (ret < 0) {
2763 			gvt_vgpu_err("%s handler error\n", info->name);
2764 			return ret;
2765 		}
2766 	}
2767 
2768 	if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2769 		ret = cmd_advance_default(s);
2770 		if (ret) {
2771 			gvt_vgpu_err("%s IP advance error\n", info->name);
2772 			return ret;
2773 		}
2774 	}
2775 	return 0;
2776 }
2777 
gma_out_of_range(unsigned long gma,unsigned long gma_head,unsigned int gma_tail)2778 static inline bool gma_out_of_range(unsigned long gma,
2779 		unsigned long gma_head, unsigned int gma_tail)
2780 {
2781 	if (gma_tail >= gma_head)
2782 		return (gma < gma_head) || (gma > gma_tail);
2783 	else
2784 		return (gma > gma_tail) && (gma < gma_head);
2785 }
2786 
2787 /* Keep the consistent return type, e.g EBADRQC for unknown
2788  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2789  * works as the input of VM healthy status.
2790  */
command_scan(struct parser_exec_state * s,unsigned long rb_head,unsigned long rb_tail,unsigned long rb_start,unsigned long rb_len)2791 static int command_scan(struct parser_exec_state *s,
2792 		unsigned long rb_head, unsigned long rb_tail,
2793 		unsigned long rb_start, unsigned long rb_len)
2794 {
2795 
2796 	unsigned long gma_head, gma_tail, gma_bottom;
2797 	int ret = 0;
2798 	struct intel_vgpu *vgpu = s->vgpu;
2799 
2800 	gma_head = rb_start + rb_head;
2801 	gma_tail = rb_start + rb_tail;
2802 	gma_bottom = rb_start +  rb_len;
2803 
2804 	while (s->ip_gma != gma_tail) {
2805 		if (s->buf_type == RING_BUFFER_INSTRUCTION ||
2806 				s->buf_type == RING_BUFFER_CTX) {
2807 			if (!(s->ip_gma >= rb_start) ||
2808 				!(s->ip_gma < gma_bottom)) {
2809 				gvt_vgpu_err("ip_gma %lx out of ring scope."
2810 					"(base:0x%lx, bottom: 0x%lx)\n",
2811 					s->ip_gma, rb_start,
2812 					gma_bottom);
2813 				parser_exec_state_dump(s);
2814 				return -EFAULT;
2815 			}
2816 			if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2817 				gvt_vgpu_err("ip_gma %lx out of range."
2818 					"base 0x%lx head 0x%lx tail 0x%lx\n",
2819 					s->ip_gma, rb_start,
2820 					rb_head, rb_tail);
2821 				parser_exec_state_dump(s);
2822 				break;
2823 			}
2824 		}
2825 		ret = cmd_parser_exec(s);
2826 		if (ret) {
2827 			gvt_vgpu_err("cmd parser error\n");
2828 			parser_exec_state_dump(s);
2829 			break;
2830 		}
2831 	}
2832 
2833 	return ret;
2834 }
2835 
scan_workload(struct intel_vgpu_workload * workload)2836 static int scan_workload(struct intel_vgpu_workload *workload)
2837 {
2838 	unsigned long gma_head, gma_tail;
2839 	struct parser_exec_state s;
2840 	int ret = 0;
2841 
2842 	/* ring base is page aligned */
2843 	if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2844 		return -EINVAL;
2845 
2846 	gma_head = workload->rb_start + workload->rb_head;
2847 	gma_tail = workload->rb_start + workload->rb_tail;
2848 
2849 	s.buf_type = RING_BUFFER_INSTRUCTION;
2850 	s.buf_addr_type = GTT_BUFFER;
2851 	s.vgpu = workload->vgpu;
2852 	s.engine = workload->engine;
2853 	s.ring_start = workload->rb_start;
2854 	s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2855 	s.ring_head = gma_head;
2856 	s.ring_tail = gma_tail;
2857 	s.rb_va = workload->shadow_ring_buffer_va;
2858 	s.workload = workload;
2859 	s.is_ctx_wa = false;
2860 
2861 	if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2862 		return 0;
2863 
2864 	ret = ip_gma_set(&s, gma_head);
2865 	if (ret)
2866 		goto out;
2867 
2868 	ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2869 		workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2870 
2871 out:
2872 	return ret;
2873 }
2874 
scan_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)2875 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2876 {
2877 
2878 	unsigned long gma_head, gma_tail, ring_size, ring_tail;
2879 	struct parser_exec_state s;
2880 	int ret = 0;
2881 	struct intel_vgpu_workload *workload = container_of(wa_ctx,
2882 				struct intel_vgpu_workload,
2883 				wa_ctx);
2884 
2885 	/* ring base is page aligned */
2886 	if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2887 					I915_GTT_PAGE_SIZE)))
2888 		return -EINVAL;
2889 
2890 	ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2891 	ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2892 			PAGE_SIZE);
2893 	gma_head = wa_ctx->indirect_ctx.guest_gma;
2894 	gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2895 
2896 	s.buf_type = RING_BUFFER_INSTRUCTION;
2897 	s.buf_addr_type = GTT_BUFFER;
2898 	s.vgpu = workload->vgpu;
2899 	s.engine = workload->engine;
2900 	s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2901 	s.ring_size = ring_size;
2902 	s.ring_head = gma_head;
2903 	s.ring_tail = gma_tail;
2904 	s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2905 	s.workload = workload;
2906 	s.is_ctx_wa = true;
2907 
2908 	ret = ip_gma_set(&s, gma_head);
2909 	if (ret)
2910 		goto out;
2911 
2912 	ret = command_scan(&s, 0, ring_tail,
2913 		wa_ctx->indirect_ctx.guest_gma, ring_size);
2914 out:
2915 	return ret;
2916 }
2917 
shadow_workload_ring_buffer(struct intel_vgpu_workload * workload)2918 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2919 {
2920 	struct intel_vgpu *vgpu = workload->vgpu;
2921 	struct intel_vgpu_submission *s = &vgpu->submission;
2922 	unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2923 	void *shadow_ring_buffer_va;
2924 	int ret;
2925 
2926 	guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2927 
2928 	/* calculate workload ring buffer size */
2929 	workload->rb_len = (workload->rb_tail + guest_rb_size -
2930 			workload->rb_head) % guest_rb_size;
2931 
2932 	gma_head = workload->rb_start + workload->rb_head;
2933 	gma_tail = workload->rb_start + workload->rb_tail;
2934 	gma_top = workload->rb_start + guest_rb_size;
2935 
2936 	if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2937 		void *p;
2938 
2939 		/* realloc the new ring buffer if needed */
2940 		p = krealloc(s->ring_scan_buffer[workload->engine->id],
2941 			     workload->rb_len, GFP_KERNEL);
2942 		if (!p) {
2943 			gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2944 			return -ENOMEM;
2945 		}
2946 		s->ring_scan_buffer[workload->engine->id] = p;
2947 		s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2948 	}
2949 
2950 	shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2951 
2952 	/* get shadow ring buffer va */
2953 	workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2954 
2955 	/* head > tail --> copy head <-> top */
2956 	if (gma_head > gma_tail) {
2957 		ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2958 				      gma_head, gma_top, shadow_ring_buffer_va);
2959 		if (ret < 0) {
2960 			gvt_vgpu_err("fail to copy guest ring buffer\n");
2961 			return ret;
2962 		}
2963 		shadow_ring_buffer_va += ret;
2964 		gma_head = workload->rb_start;
2965 	}
2966 
2967 	/* copy head or start <-> tail */
2968 	ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2969 				shadow_ring_buffer_va);
2970 	if (ret < 0) {
2971 		gvt_vgpu_err("fail to copy guest ring buffer\n");
2972 		return ret;
2973 	}
2974 	return 0;
2975 }
2976 
intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload * workload)2977 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2978 {
2979 	int ret;
2980 	struct intel_vgpu *vgpu = workload->vgpu;
2981 
2982 	ret = shadow_workload_ring_buffer(workload);
2983 	if (ret) {
2984 		gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2985 		return ret;
2986 	}
2987 
2988 	ret = scan_workload(workload);
2989 	if (ret) {
2990 		gvt_vgpu_err("scan workload error\n");
2991 		return ret;
2992 	}
2993 	return 0;
2994 }
2995 
shadow_indirect_ctx(struct intel_shadow_wa_ctx * wa_ctx)2996 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2997 {
2998 	int ctx_size = wa_ctx->indirect_ctx.size;
2999 	unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
3000 	struct intel_vgpu_workload *workload = container_of(wa_ctx,
3001 					struct intel_vgpu_workload,
3002 					wa_ctx);
3003 	struct intel_vgpu *vgpu = workload->vgpu;
3004 	struct drm_i915_gem_object *obj;
3005 	int ret = 0;
3006 	void *map;
3007 
3008 	obj = i915_gem_object_create_shmem(workload->engine->i915,
3009 					   roundup(ctx_size + CACHELINE_BYTES,
3010 						   PAGE_SIZE));
3011 	if (IS_ERR(obj))
3012 		return PTR_ERR(obj);
3013 
3014 	/* get the va of the shadow batch buffer */
3015 	map = i915_gem_object_pin_map(obj, I915_MAP_WB);
3016 	if (IS_ERR(map)) {
3017 		gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
3018 		ret = PTR_ERR(map);
3019 		goto put_obj;
3020 	}
3021 
3022 	i915_gem_object_lock(obj, NULL);
3023 	ret = i915_gem_object_set_to_cpu_domain(obj, false);
3024 	i915_gem_object_unlock(obj);
3025 	if (ret) {
3026 		gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3027 		goto unmap_src;
3028 	}
3029 
3030 	ret = copy_gma_to_hva(workload->vgpu,
3031 				workload->vgpu->gtt.ggtt_mm,
3032 				guest_gma, guest_gma + ctx_size,
3033 				map);
3034 	if (ret < 0) {
3035 		gvt_vgpu_err("fail to copy guest indirect ctx\n");
3036 		goto unmap_src;
3037 	}
3038 
3039 	wa_ctx->indirect_ctx.obj = obj;
3040 	wa_ctx->indirect_ctx.shadow_va = map;
3041 	return 0;
3042 
3043 unmap_src:
3044 	i915_gem_object_unpin_map(obj);
3045 put_obj:
3046 	i915_gem_object_put(obj);
3047 	return ret;
3048 }
3049 
combine_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3050 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3051 {
3052 	u32 per_ctx_start[CACHELINE_DWORDS] = {};
3053 	unsigned char *bb_start_sva;
3054 
3055 	if (!wa_ctx->per_ctx.valid)
3056 		return 0;
3057 
3058 	per_ctx_start[0] = 0x18800001;
3059 	per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3060 
3061 	bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3062 				wa_ctx->indirect_ctx.size;
3063 
3064 	memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3065 
3066 	return 0;
3067 }
3068 
intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3069 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3070 {
3071 	int ret;
3072 	struct intel_vgpu_workload *workload = container_of(wa_ctx,
3073 					struct intel_vgpu_workload,
3074 					wa_ctx);
3075 	struct intel_vgpu *vgpu = workload->vgpu;
3076 
3077 	if (wa_ctx->indirect_ctx.size == 0)
3078 		return 0;
3079 
3080 	ret = shadow_indirect_ctx(wa_ctx);
3081 	if (ret) {
3082 		gvt_vgpu_err("fail to shadow indirect ctx\n");
3083 		return ret;
3084 	}
3085 
3086 	combine_wa_ctx(wa_ctx);
3087 
3088 	ret = scan_wa_ctx(wa_ctx);
3089 	if (ret) {
3090 		gvt_vgpu_err("scan wa ctx error\n");
3091 		return ret;
3092 	}
3093 
3094 	return 0;
3095 }
3096 
3097 /* generate dummy contexts by sending empty requests to HW, and let
3098  * the HW to fill Engine Contexts. This dummy contexts are used for
3099  * initialization purpose (update reg whitelist), so referred to as
3100  * init context here
3101  */
intel_gvt_update_reg_whitelist(struct intel_vgpu * vgpu)3102 void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3103 {
3104 	const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
3105 	struct intel_gvt *gvt = vgpu->gvt;
3106 	struct intel_engine_cs *engine;
3107 	enum intel_engine_id id;
3108 
3109 	if (gvt->is_reg_whitelist_updated)
3110 		return;
3111 
3112 	/* scan init ctx to update cmd accessible list */
3113 	for_each_engine(engine, gvt->gt, id) {
3114 		struct parser_exec_state s;
3115 		void *vaddr;
3116 		int ret;
3117 
3118 		if (!engine->default_state)
3119 			continue;
3120 
3121 		vaddr = shmem_pin_map(engine->default_state);
3122 		if (!vaddr) {
3123 			gvt_err("failed to map %s->default state\n",
3124 				engine->name);
3125 			return;
3126 		}
3127 
3128 		s.buf_type = RING_BUFFER_CTX;
3129 		s.buf_addr_type = GTT_BUFFER;
3130 		s.vgpu = vgpu;
3131 		s.engine = engine;
3132 		s.ring_start = 0;
3133 		s.ring_size = engine->context_size - start;
3134 		s.ring_head = 0;
3135 		s.ring_tail = s.ring_size;
3136 		s.rb_va = vaddr + start;
3137 		s.workload = NULL;
3138 		s.is_ctx_wa = false;
3139 		s.is_init_ctx = true;
3140 
3141 		/* skipping the first RING_CTX_SIZE(0x50) dwords */
3142 		ret = ip_gma_set(&s, RING_CTX_SIZE);
3143 		if (ret == 0) {
3144 			ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
3145 			if (ret)
3146 				gvt_err("Scan init ctx error\n");
3147 		}
3148 
3149 		shmem_unpin_map(engine->default_state, vaddr);
3150 		if (ret)
3151 			return;
3152 	}
3153 
3154 	gvt->is_reg_whitelist_updated = true;
3155 }
3156 
intel_gvt_scan_engine_context(struct intel_vgpu_workload * workload)3157 int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)
3158 {
3159 	struct intel_vgpu *vgpu = workload->vgpu;
3160 	unsigned long gma_head, gma_tail, gma_start, ctx_size;
3161 	struct parser_exec_state s;
3162 	int ring_id = workload->engine->id;
3163 	struct intel_context *ce = vgpu->submission.shadow[ring_id];
3164 	int ret;
3165 
3166 	GEM_BUG_ON(atomic_read(&ce->pin_count) < 0);
3167 
3168 	ctx_size = workload->engine->context_size - PAGE_SIZE;
3169 
3170 	/* Only ring contxt is loaded to HW for inhibit context, no need to
3171 	 * scan engine context
3172 	 */
3173 	if (is_inhibit_context(ce))
3174 		return 0;
3175 
3176 	gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
3177 	gma_head = 0;
3178 	gma_tail = ctx_size;
3179 
3180 	s.buf_type = RING_BUFFER_CTX;
3181 	s.buf_addr_type = GTT_BUFFER;
3182 	s.vgpu = workload->vgpu;
3183 	s.engine = workload->engine;
3184 	s.ring_start = gma_start;
3185 	s.ring_size = ctx_size;
3186 	s.ring_head = gma_start + gma_head;
3187 	s.ring_tail = gma_start + gma_tail;
3188 	s.rb_va = ce->lrc_reg_state;
3189 	s.workload = workload;
3190 	s.is_ctx_wa = false;
3191 	s.is_init_ctx = false;
3192 
3193 	/* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring
3194 	 * context
3195 	 */
3196 	ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE);
3197 	if (ret)
3198 		goto out;
3199 
3200 	ret = command_scan(&s, gma_head, gma_tail,
3201 		gma_start, ctx_size);
3202 out:
3203 	if (ret)
3204 		gvt_vgpu_err("scan shadow ctx error\n");
3205 
3206 	return ret;
3207 }
3208 
init_cmd_table(struct intel_gvt * gvt)3209 static int init_cmd_table(struct intel_gvt *gvt)
3210 {
3211 	unsigned int gen_type = intel_gvt_get_device_type(gvt);
3212 	int i;
3213 
3214 	for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3215 		struct cmd_entry *e;
3216 
3217 		if (!(cmd_info[i].devices & gen_type))
3218 			continue;
3219 
3220 		e = kzalloc(sizeof(*e), GFP_KERNEL);
3221 		if (!e)
3222 			return -ENOMEM;
3223 
3224 		e->info = &cmd_info[i];
3225 		if (cmd_info[i].opcode == OP_MI_NOOP)
3226 			mi_noop_index = i;
3227 
3228 		INIT_HLIST_NODE(&e->hlist);
3229 		add_cmd_entry(gvt, e);
3230 		gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3231 			    e->info->name, e->info->opcode, e->info->flag,
3232 			    e->info->devices, e->info->rings);
3233 	}
3234 
3235 	return 0;
3236 }
3237 
clean_cmd_table(struct intel_gvt * gvt)3238 static void clean_cmd_table(struct intel_gvt *gvt)
3239 {
3240 	struct hlist_node *tmp;
3241 	struct cmd_entry *e;
3242 	int i;
3243 
3244 	hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3245 		kfree(e);
3246 
3247 	hash_init(gvt->cmd_table);
3248 }
3249 
intel_gvt_clean_cmd_parser(struct intel_gvt * gvt)3250 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3251 {
3252 	clean_cmd_table(gvt);
3253 }
3254 
intel_gvt_init_cmd_parser(struct intel_gvt * gvt)3255 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3256 {
3257 	int ret;
3258 
3259 	ret = init_cmd_table(gvt);
3260 	if (ret) {
3261 		intel_gvt_clean_cmd_parser(gvt);
3262 		return ret;
3263 	}
3264 	return 0;
3265 }
3266