1 /*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * Allwinner USB PHY
28 */
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/rman.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/gpio.h>
37 #include <machine/bus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41 #include <dev/gpio/gpiobusvar.h>
42
43 #include <dev/clk/clk.h>
44 #include <dev/hwreset/hwreset.h>
45 #include <dev/regulator/regulator.h>
46 #include <dev/phy/phy_usb.h>
47
48 #include "phynode_if.h"
49
50 enum awusbphy_type {
51 AWUSBPHY_TYPE_A10 = 1,
52 AWUSBPHY_TYPE_A13,
53 AWUSBPHY_TYPE_A20,
54 AWUSBPHY_TYPE_A31,
55 AWUSBPHY_TYPE_H3,
56 AWUSBPHY_TYPE_A64,
57 AWUSBPHY_TYPE_A83T,
58 AWUSBPHY_TYPE_H6,
59 };
60
61 struct aw_usbphy_conf {
62 int num_phys;
63 enum awusbphy_type phy_type;
64 bool pmu_unk1;
65 bool phy0_route;
66 };
67
68 static const struct aw_usbphy_conf a10_usbphy_conf = {
69 .num_phys = 3,
70 .phy_type = AWUSBPHY_TYPE_A10,
71 .pmu_unk1 = false,
72 .phy0_route = false,
73 };
74
75 static const struct aw_usbphy_conf a13_usbphy_conf = {
76 .num_phys = 2,
77 .phy_type = AWUSBPHY_TYPE_A13,
78 .pmu_unk1 = false,
79 .phy0_route = false,
80 };
81
82 static const struct aw_usbphy_conf a20_usbphy_conf = {
83 .num_phys = 3,
84 .phy_type = AWUSBPHY_TYPE_A20,
85 .pmu_unk1 = false,
86 .phy0_route = false,
87 };
88
89 static const struct aw_usbphy_conf a31_usbphy_conf = {
90 .num_phys = 3,
91 .phy_type = AWUSBPHY_TYPE_A31,
92 .pmu_unk1 = false,
93 .phy0_route = false,
94 };
95
96 static const struct aw_usbphy_conf h3_usbphy_conf = {
97 .num_phys = 4,
98 .phy_type = AWUSBPHY_TYPE_H3,
99 .pmu_unk1 = true,
100 .phy0_route = true,
101 };
102
103 static const struct aw_usbphy_conf a64_usbphy_conf = {
104 .num_phys = 2,
105 .phy_type = AWUSBPHY_TYPE_A64,
106 .pmu_unk1 = true,
107 .phy0_route = true,
108 };
109
110 static const struct aw_usbphy_conf a83t_usbphy_conf = {
111 .num_phys = 3,
112 .phy_type = AWUSBPHY_TYPE_A83T,
113 .pmu_unk1 = false,
114 .phy0_route = false,
115 };
116
117 static const struct aw_usbphy_conf h6_usbphy_conf = {
118 .num_phys = 4,
119 .phy_type = AWUSBPHY_TYPE_H6,
120 .pmu_unk1 = false,
121 .phy0_route = true,
122 };
123
124 static struct ofw_compat_data compat_data[] = {
125 { "allwinner,sun4i-a10-usb-phy", (uintptr_t)&a10_usbphy_conf },
126 { "allwinner,sun5i-a13-usb-phy", (uintptr_t)&a13_usbphy_conf },
127 { "allwinner,sun6i-a31-usb-phy", (uintptr_t)&a31_usbphy_conf },
128 { "allwinner,sun7i-a20-usb-phy", (uintptr_t)&a20_usbphy_conf },
129 { "allwinner,sun8i-h3-usb-phy", (uintptr_t)&h3_usbphy_conf },
130 { "allwinner,sun50i-a64-usb-phy", (uintptr_t)&a64_usbphy_conf },
131 { "allwinner,sun8i-a83t-usb-phy", (uintptr_t)&a83t_usbphy_conf },
132 { "allwinner,sun50i-h6-usb-phy", (uintptr_t)&h6_usbphy_conf },
133 { NULL, 0 }
134 };
135
136 struct awusbphy_softc {
137 struct resource * phy_ctrl;
138 struct resource ** pmu;
139 regulator_t * reg;
140 gpio_pin_t id_det_pin;
141 int id_det_valid;
142 gpio_pin_t vbus_det_pin;
143 int vbus_det_valid;
144 struct aw_usbphy_conf *phy_conf;
145 int mode;
146 };
147
148 /* Phy class and methods. */
149 static int awusbphy_phy_enable(struct phynode *phy, bool enable);
150 static int awusbphy_get_mode(struct phynode *phy, int *mode);
151 static int awusbphy_set_mode(struct phynode *phy, int mode);
152 static phynode_usb_method_t awusbphy_phynode_methods[] = {
153 PHYNODEMETHOD(phynode_enable, awusbphy_phy_enable),
154 PHYNODEMETHOD(phynode_usb_get_mode, awusbphy_get_mode),
155 PHYNODEMETHOD(phynode_usb_set_mode, awusbphy_set_mode),
156
157 PHYNODEMETHOD_END
158 };
159 DEFINE_CLASS_1(awusbphy_phynode, awusbphy_phynode_class, awusbphy_phynode_methods,
160 sizeof(struct phynode_usb_sc), phynode_usb_class);
161
162 #define RD4(res, o) bus_read_4(res, (o))
163 #define WR4(res, o, v) bus_write_4(res, (o), (v))
164 #define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m))
165 #define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m))
166
167 #define PHY_CSR 0x00
168 #define ID_PULLUP_EN (1 << 17)
169 #define DPDM_PULLUP_EN (1 << 16)
170 #define FORCE_ID (0x3 << 14)
171 #define FORCE_ID_SHIFT 14
172 #define FORCE_ID_LOW 2
173 #define FORCE_ID_HIGH 3
174 #define FORCE_VBUS_VALID (0x3 << 12)
175 #define FORCE_VBUS_VALID_SHIFT 12
176 #define FORCE_VBUS_VALID_LOW 2
177 #define FORCE_VBUS_VALID_HIGH 3
178 #define VBUS_CHANGE_DET (1 << 6)
179 #define ID_CHANGE_DET (1 << 5)
180 #define DPDM_CHANGE_DET (1 << 4)
181 #define OTG_PHY_CFG 0x20
182 #define OTG_PHY_ROUTE_OTG (1 << 0)
183 #define PMU_IRQ_ENABLE 0x00
184 #define PMU_AHB_INCR8 (1 << 10)
185 #define PMU_AHB_INCR4 (1 << 9)
186 #define PMU_AHB_INCRX_ALIGN (1 << 8)
187 #define PMU_ULPI_BYPASS (1 << 0)
188 #define PMU_UNK_H3 0x10
189 #define PMU_UNK_H3_CLR 0x2
190
191 static void
awusbphy_configure(device_t dev,int phyno)192 awusbphy_configure(device_t dev, int phyno)
193 {
194 struct awusbphy_softc *sc;
195
196 sc = device_get_softc(dev);
197
198 if (sc->pmu[phyno] == NULL)
199 return;
200
201 if (sc->phy_conf->pmu_unk1 == true)
202 CLR4(sc->pmu[phyno], PMU_UNK_H3, PMU_UNK_H3_CLR);
203
204 SET4(sc->pmu[phyno], PMU_IRQ_ENABLE, PMU_ULPI_BYPASS |
205 PMU_AHB_INCR8 | PMU_AHB_INCR4 | PMU_AHB_INCRX_ALIGN);
206 }
207
208 static int
awusbphy_init(device_t dev)209 awusbphy_init(device_t dev)
210 {
211 struct awusbphy_softc *sc;
212 phandle_t node;
213 char pname[20];
214 uint32_t val;
215 int error, off, rid;
216 regulator_t reg;
217 hwreset_t rst;
218 clk_t clk;
219
220 sc = device_get_softc(dev);
221 node = ofw_bus_get_node(dev);
222
223 sc->phy_conf = (struct aw_usbphy_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
224
225 /* Get phy_ctrl region */
226 if (ofw_bus_find_string_index(node, "reg-names", "phy_ctrl", &rid) != 0) {
227 device_printf(dev, "Cannot locate phy control resource\n");
228 return (ENXIO);
229 }
230 sc->phy_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
231 RF_ACTIVE);
232 if (sc->phy_ctrl == NULL) {
233 device_printf(dev, "Cannot allocate resource\n");
234 return (ENXIO);
235 }
236
237 /* Enable clocks */
238 for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) {
239 error = clk_enable(clk);
240 if (error != 0) {
241 device_printf(dev, "couldn't enable clock %s\n",
242 clk_get_name(clk));
243 return (error);
244 }
245 }
246
247 /* De-assert resets */
248 for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) {
249 error = hwreset_deassert(rst);
250 if (error != 0) {
251 device_printf(dev, "couldn't de-assert reset %d\n",
252 off);
253 return (error);
254 }
255 }
256
257 /* Get GPIOs */
258 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_id_det-gpios",
259 &sc->id_det_pin);
260 if (error == 0)
261 sc->id_det_valid = 1;
262 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_vbus_det-gpios",
263 &sc->vbus_det_pin);
264 if (error == 0)
265 sc->vbus_det_valid = 1;
266
267 sc->reg = malloc(sizeof(*(sc->reg)) * sc->phy_conf->num_phys, M_DEVBUF,
268 M_WAITOK | M_ZERO);
269 sc->pmu = malloc(sizeof(*(sc->pmu)) * sc->phy_conf->num_phys, M_DEVBUF,
270 M_WAITOK | M_ZERO);
271 /* Get regulators */
272 for (off = 0; off < sc->phy_conf->num_phys; off++) {
273 snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off);
274 if (regulator_get_by_ofw_property(dev, 0, pname, ®) == 0)
275 sc->reg[off] = reg;
276
277 snprintf(pname, sizeof(pname), "pmu%d", off);
278 if (ofw_bus_find_string_index(node, "reg-names",
279 pname, &rid) != 0)
280 continue;
281
282 sc->pmu[off] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
283 RF_ACTIVE);
284 if (sc->pmu[off] == NULL) {
285 device_printf(dev, "Cannot allocate resource\n");
286 return (ENXIO);
287 }
288 }
289
290 /* Enable OTG PHY for host mode */
291 val = bus_read_4(sc->phy_ctrl, PHY_CSR);
292 val &= ~(VBUS_CHANGE_DET | ID_CHANGE_DET | DPDM_CHANGE_DET);
293 val |= (ID_PULLUP_EN | DPDM_PULLUP_EN);
294 val &= ~FORCE_ID;
295 val |= (FORCE_ID_LOW << FORCE_ID_SHIFT);
296 val &= ~FORCE_VBUS_VALID;
297 val |= (FORCE_VBUS_VALID_HIGH << FORCE_VBUS_VALID_SHIFT);
298 bus_write_4(sc->phy_ctrl, PHY_CSR, val);
299
300 return (0);
301 }
302
303 static int
awusbphy_vbus_detect(device_t dev,int * val)304 awusbphy_vbus_detect(device_t dev, int *val)
305 {
306 struct awusbphy_softc *sc;
307 bool active;
308 int error;
309
310 sc = device_get_softc(dev);
311
312 if (sc->vbus_det_valid) {
313 error = gpio_pin_is_active(sc->vbus_det_pin, &active);
314 if (error != 0) {
315 device_printf(dev, "Cannot get status of id pin %d\n",
316 error);
317 return (error);
318 }
319 *val = active;
320 return (0);
321 }
322
323 /* TODO check vbus_power-supply. */
324
325 /*
326 * If there is no way to detect, assume present.
327 */
328 *val = 1;
329 return (0);
330 }
331
332 static int
awusbphy_phy_enable(struct phynode * phynode,bool enable)333 awusbphy_phy_enable(struct phynode *phynode, bool enable)
334 {
335 device_t dev;
336 intptr_t phy;
337 struct awusbphy_softc *sc;
338 regulator_t reg;
339 int error, vbus_det;
340
341 dev = phynode_get_device(phynode);
342 phy = phynode_get_id(phynode);
343 sc = device_get_softc(dev);
344
345 if (phy < 0 || phy >= sc->phy_conf->num_phys)
346 return (ERANGE);
347
348 /* Configure PHY */
349 awusbphy_configure(dev, phy);
350
351 /* Regulators are optional. If not found, return success. */
352 reg = sc->reg[phy];
353 if (reg == NULL)
354 return (0);
355
356 if (phy == 0) {
357 /* If an external vbus is detected, do not enable phy 0 */
358 error = awusbphy_vbus_detect(dev, &vbus_det);
359 if (error)
360 goto out;
361
362 /* TODO check vbus_power-supply as well. */
363 if (sc->vbus_det_valid && vbus_det == 1) {
364 if (bootverbose)
365 device_printf(dev, "External VBUS detected, "
366 "not enabling the regulator\n");
367 return (0);
368 }
369 }
370 if (enable) {
371 /* Depending on the PHY we need to route OTG to OHCI/EHCI */
372 error = regulator_enable(reg);
373 } else
374 error = regulator_disable(reg);
375
376 out:
377 if (error != 0) {
378 device_printf(dev,
379 "couldn't %s regulator for phy %jd\n",
380 enable ? "enable" : "disable", (intmax_t)phy);
381 return (error);
382 }
383
384 return (0);
385 }
386
387 static int
awusbphy_get_mode(struct phynode * phynode,int * mode)388 awusbphy_get_mode(struct phynode *phynode, int *mode)
389 {
390 struct awusbphy_softc *sc;
391 device_t dev;
392
393 dev = phynode_get_device(phynode);
394 sc = device_get_softc(dev);
395
396 *mode = sc->mode;
397
398 return (0);
399 }
400
401 static int
awusbphy_set_mode(struct phynode * phynode,int mode)402 awusbphy_set_mode(struct phynode *phynode, int mode)
403 {
404 device_t dev;
405 intptr_t phy;
406 struct awusbphy_softc *sc;
407 uint32_t val;
408 int error, vbus_det;
409
410 dev = phynode_get_device(phynode);
411 phy = phynode_get_id(phynode);
412 sc = device_get_softc(dev);
413
414 if (phy != 0) {
415 if (mode != PHY_USB_MODE_HOST)
416 return (EINVAL);
417 return (0);
418 }
419
420 if (sc->mode == mode)
421 return (0);
422 if (mode == PHY_USB_MODE_OTG) /* TODO */
423 return (EOPNOTSUPP);
424
425 error = awusbphy_vbus_detect(dev, &vbus_det);
426 if (error != 0)
427 return (error);
428
429 val = bus_read_4(sc->phy_ctrl, PHY_CSR);
430 val &= ~(VBUS_CHANGE_DET | ID_CHANGE_DET | DPDM_CHANGE_DET);
431 val |= (ID_PULLUP_EN | DPDM_PULLUP_EN);
432 val &= ~FORCE_VBUS_VALID;
433 val |= (vbus_det ? FORCE_VBUS_VALID_HIGH : FORCE_VBUS_VALID_LOW) <<
434 FORCE_VBUS_VALID_SHIFT;
435 val &= ~FORCE_ID;
436
437 switch (mode) {
438 case PHY_USB_MODE_HOST:
439 val |= (FORCE_ID_LOW << FORCE_ID_SHIFT);
440 if (sc->phy_conf->phy0_route)
441 CLR4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
442 break;
443 case PHY_USB_MODE_DEVICE:
444 val |= (FORCE_ID_HIGH << FORCE_ID_SHIFT);
445 if (sc->phy_conf->phy0_route)
446 SET4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
447 break;
448 default:
449 return (EINVAL);
450 }
451
452 bus_write_4(sc->phy_ctrl, PHY_CSR, val);
453 sc->mode = mode;
454 return (0);
455 }
456
457 static int
awusbphy_probe(device_t dev)458 awusbphy_probe(device_t dev)
459 {
460 if (!ofw_bus_status_okay(dev))
461 return (ENXIO);
462
463 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
464 return (ENXIO);
465
466 device_set_desc(dev, "Allwinner USB PHY");
467 return (BUS_PROBE_DEFAULT);
468 }
469
470 static int
awusbphy_attach(device_t dev)471 awusbphy_attach(device_t dev)
472 {
473 int error;
474 struct phynode *phynode;
475 struct phynode_init_def phy_init;
476 struct awusbphy_softc *sc;
477 int i;
478
479 sc = device_get_softc(dev);
480 error = awusbphy_init(dev);
481 if (error) {
482 device_printf(dev, "failed to initialize USB PHY, error %d\n",
483 error);
484 return (error);
485 }
486
487 /* Create and register phys. */
488 for (i = 0; i < sc->phy_conf->num_phys; i++) {
489 bzero(&phy_init, sizeof(phy_init));
490 phy_init.id = i;
491 phy_init.ofw_node = ofw_bus_get_node(dev);
492 phynode = phynode_create(dev, &awusbphy_phynode_class,
493 &phy_init);
494 if (phynode == NULL) {
495 device_printf(dev, "failed to create USB PHY\n");
496 return (ENXIO);
497 }
498 if (phynode_register(phynode) == NULL) {
499 device_printf(dev, "failed to create USB PHY\n");
500 return (ENXIO);
501 }
502 }
503
504 return (error);
505 }
506
507 static device_method_t awusbphy_methods[] = {
508 /* Device interface */
509 DEVMETHOD(device_probe, awusbphy_probe),
510 DEVMETHOD(device_attach, awusbphy_attach),
511
512 DEVMETHOD_END
513 };
514
515 static driver_t awusbphy_driver = {
516 "awusbphy",
517 awusbphy_methods,
518 sizeof(struct awusbphy_softc)
519 };
520
521 /* aw_usbphy needs to come up after regulators/gpio/etc, but before ehci/ohci */
522 EARLY_DRIVER_MODULE(awusbphy, simplebus, awusbphy_driver, 0, 0,
523 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
524 MODULE_VERSION(awusbphy, 1);
525