xref: /titanic_41/usr/src/uts/common/io/ath/ath_impl.h (revision 129d67acdc2d029d3d6cff4022c0c26c81c76f89)
1 /*
2  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer,
15  *    without modification.
16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18  *    redistribution must be conditioned upon including a substantially
19  *    similar Disclaimer requirement for further binary redistribution.
20  * 3. Neither the names of the above-listed copyright holders nor the names
21  *    of any contributors may be used to endorse or promote products derived
22  *    from this software without specific prior written permission.
23  *
24  * NO WARRANTY
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
28  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
29  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
30  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
33  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
35  * THE POSSIBILITY OF SUCH DAMAGES.
36  *
37  */
38 
39 /*
40  * ath_impl.h is a bridge between the HAL and the driver. It
41  * defines some data structures encapsulating the HAL interface
42  * and communicating with the IEEE80211 MAC layer and other
43  * driver components.
44  */
45 
46 #ifndef	_ATH_IMPL_H
47 #define	_ATH_IMPL_H
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
53 /*
54  * Defintions for the Atheros Wireless LAN controller driver.
55  */
56 
57 #include <sys/note.h>
58 #include <sys/list.h>
59 #include <sys/net80211.h>
60 #include "ath_hal.h"
61 
62 /* Bit map related macros. */
63 #define	setbit(a, i)		((a)[(i)/NBBY] |= (1 << ((i)%NBBY)))
64 #define	clrbit(a, i)		((a)[(i)/NBBY] &= ~(1 << ((i)%NBBY)))
65 #define	isset(a, i)		((a)[(i)/NBBY] & (1 << ((i)%NBBY)))
66 #define	isclr(a, i)		(!((a)[(i)/NBBY] & (1 << ((i)%NBBY))))
67 
68 /*
69  * Bit flags in the ath_dbg_flags
70  */
71 #define	ATH_DBG_INIT		0x00000001	/* initialisation	*/
72 #define	ATH_DBG_GLD		0x00000002	/* GLD entry points	*/
73 #define	ATH_DBG_HAL		0x00000004	/* HAL related code	*/
74 #define	ATH_DBG_INT		0x00000008	/* interrupt handler	*/
75 #define	ATH_DBG_RECV		0x00000010	/* receive-side code	*/
76 #define	ATH_DBG_SEND		0x00000020	/* packet-send code	*/
77 #define	ATH_DBG_80211		0x00000040	/* 80211 state machine	*/
78 #define	ATH_DBG_IOCTL		0x00000080	/* ioctl code		*/
79 #define	ATH_DBG_STATS		0x00000100	/* statistics		*/
80 #define	ATH_DBG_RATE		0x00000200	/* rate control		*/
81 #define	ATH_DBG_AUX		0x00000400	/* for ath_aux.c	*/
82 #define	ATH_DBG_WIFICFG		0x00000800	/* wificonfig		*/
83 #define	ATH_DBG_OSDEP		0x00001000	/* osdep		*/
84 #define	ATH_DBG_ATTACH		0x00002000	/* attach		*/
85 #define	ATH_DBG_DETACH		0x00004000	/* detach		*/
86 #define	ATH_DBG_SUSPEND		0x00008000	/* suspend/resume	*/
87 #define	ATH_DBG_ALL		0x0000ffff	/* all			*/
88 
89 #ifdef DEBUG
90 #define	ATH_DDB(command)	do {				\
91 					{ command; }		\
92 					_NOTE(CONSTANTCONDITION)\
93 				} while (0)
94 #else
95 #define	ATH_DDB(command)
96 #endif /* DEBUG */
97 
98 /*
99  * Node type of wifi device
100  */
101 #ifndef DDI_NT_NET_WIFI
102 #define	DDI_NT_NET_WIFI	"ddi_network:wifi"
103 #endif
104 #define	ATH_NODENAME	"ath"
105 
106 #define	ATH_DEBUG(args)		ATH_DDB(ath_dbg args)
107 
108 #define	list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
109 #define	ATH_LE_READ_4(p)						\
110 	((uint32_t)							\
111 	((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] <<  8) |		\
112 	(((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24)))
113 #define	ATH_N(a)	(sizeof (a) / sizeof (a[0]))
114 #define	ATH_TXQ_SETUP(asc, i)	((asc)->asc_txqsetup & (1<<i))
115 #define	ATH_PA2DESC(_asc, _pa) \
116 	((struct ath_desc *)((caddr_t)(_asc)->asc_desc + \
117 	((_pa) - (_asc)->asc_desc_dma.cookie.dmac_address)))
118 /*
119  * Sync a DMA area described by a dma_area_t
120  */
121 #define	ATH_DMA_SYNC(area, flag)    ((void) ddi_dma_sync((area).dma_hdl,    \
122 				(area).offset, (area).alength, (flag)))
123 
124 #define	ATH_TXINTR_PERIOD 5
125 #define	ATH_TIMEOUT	1000
126 #define	ATH_RXBUF	80		/* number of RX buffers */
127 #define	ATH_TXBUF	200		/* number of TX buffers */
128 #define	ATH_TXDESC	1		/* number of descriptors per buffer */
129 #define	ATH_TXMAXTRY	11		/* max number of transmit attempts */
130 #define	ATH_MCHASH	64		/* multicast hash table size */
131 
132 #define	ATH_DEF_CACHE_BYTES	32	/* default cache line size */
133 
134 /* driver-specific node state */
135 struct ath_node {
136 	struct ieee80211_node an_node;	/* base class */
137 	uint32_t	an_tx_times;	/* rate ctl times on one rate */
138 	uint32_t	an_tx_ok;	/* tx ok pkt */
139 	uint32_t	an_tx_err;	/* tx !ok pkt */
140 	uint32_t	an_tx_retr;	/* tx retry count */
141 	int32_t		an_tx_upper;	/* tx upper rate req cnt */
142 	uint32_t	an_tx_antenna;	/* antenna for last good frame */
143 	uint8_t		an_tx_rix0;	/* series 0 rate index */
144 	uint8_t		an_tx_try0;	/* series 0 try count */
145 	uint8_t		an_tx_mgtrate;	/* h/w rate for management/ctl frames */
146 	uint8_t		an_tx_mgtratesp; /* short preamble h/w rate for " " */
147 	uint8_t		an_tx_rate0;	/* series 0 h/w rate */
148 	uint8_t		an_tx_rate1;	/* series 1 h/w rate */
149 	uint8_t		an_tx_rate2;	/* series 2 h/w rate */
150 	uint8_t		an_tx_rate3;	/* series 3 h/w rate */
151 	uint8_t		an_tx_rate0sp;	/* series 0 short preamble h/w rate */
152 	uint8_t		an_tx_rate1sp;	/* series 1 short preamble h/w rate */
153 	uint8_t		an_tx_rate2sp;	/* series 2 short preamble h/w rate */
154 	uint8_t		an_tx_rate3sp;	/* series 3 short preamble h/w rate */
155 };
156 #define	ATH_NODE(_n)	((struct ath_node *)(_n))
157 
158 
159 struct ath_stats {
160 	uint32_t	ast_hardware;	/* fatal hardware error interrupts */
161 	uint32_t	ast_rxorn;	/* rx overrun interrupts */
162 	uint32_t	ast_rxeol;	/* rx eol interrupts */
163 	uint32_t	ast_txurn;	/* tx underrun interrupts */
164 	uint32_t	ast_tx_mgmt;	/* management frames transmitted */
165 	uint32_t	ast_tx_discard;	/* frames discarded prior to assoc */
166 	uint32_t	ast_tx_invalid; /* frames discarded 'cuz device gone */
167 	uint32_t	ast_tx_qstop;	/* tx queue stopped 'cuz full */
168 	uint32_t	ast_tx_nobuf;	/* tx failed 'cuz no tx buffer (data) */
169 	uint32_t	ast_tx_nobufmgt; /* tx failed 'cuz no tx buffer(mgmt) */
170 	uint32_t	ast_tx_xretries; /* tx failed 'cuz too many retries */
171 	uint32_t	ast_tx_fifoerr;	/* tx failed 'cuz FIFO underrun */
172 	uint32_t	ast_tx_filtered; /* tx failed 'cuz xmit filtered */
173 	uint32_t	ast_tx_shortretry; /* tx on-chip retries (short) */
174 	uint32_t	ast_tx_longretry; /* tx on-chip retries (long) */
175 	uint32_t	ast_tx_noack;	/* tx frames with no ack marked */
176 	uint32_t	ast_tx_rts;	/* tx frames with rts enabled */
177 	uint32_t	ast_tx_shortpre; /* tx frames with short preamble */
178 	uint32_t	ast_tx_altrate;	/* tx frames with alternate rate */
179 	uint32_t	ast_tx_protect;	/* tx frames with protection */
180 	int16_t		ast_tx_rssi;	/* tx rssi of last ack */
181 	int16_t		ast_tx_rssidelta; /* tx rssi delta */
182 	uint32_t	ast_rx_crcerr;	/* rx failed 'cuz of bad CRC */
183 	uint32_t	ast_rx_fifoerr;	/* rx failed 'cuz of FIFO overrun */
184 	uint32_t	ast_rx_badcrypt; /* rx failed 'cuz decryption */
185 	uint32_t	ast_rx_phyerr;	/* rx PHY error summary count */
186 	uint32_t	ast_rx_phy[32];	/* rx PHY error per-code counts */
187 	uint32_t	ast_rx_tooshort; /* rx discarded 'cuz frame too short */
188 	uint32_t	ast_per_cal;	/* periodic calibration calls */
189 	uint32_t	ast_per_calfail; /* periodic calibration failed */
190 	uint32_t	ast_per_rfgain;	/* periodic calibration rfgain reset */
191 	uint32_t	ast_rate_calls;	/* rate control checks */
192 	uint32_t	ast_rate_raise;	/* rate control raised xmit rate */
193 	uint32_t	ast_rate_drop;	/* rate control dropped xmit rate */
194 };
195 
196 
197 /*
198  * Describes one chunk of allocated DMA-able memory
199  *
200  * In some cases, this is a single chunk as allocated from the system;
201  * but we also use this structure to represent slices carved off such
202  * a chunk.  Even when we don't really need all the information, we
203  * use this structure as a convenient way of correlating the various
204  * ways of looking at a piece of memory (kernel VA, IO space DVMA,
205  * handle+offset, etc).
206  */
207 struct dma_area {
208 	ddi_acc_handle_t	acc_hdl;	/* handle for memory */
209 	caddr_t			mem_va;		/* CPU VA of memory */
210 	uint32_t		nslots;		/* number of slots */
211 	uint32_t		size;		/* size per slot */
212 	size_t			alength;	/* allocated size */
213 						/* >= product of above */
214 
215 	ddi_dma_handle_t	dma_hdl;	/* DMA handle */
216 	offset_t		offset;		/* relative to handle */
217 	ddi_dma_cookie_t	cookie;		/* associated cookie */
218 	uint32_t		ncookies;	/* must be 1 */
219 	uint32_t		token;		/* arbitrary identifier */
220 };						/* 0x50 (80) bytes */
221 typedef struct dma_area dma_area_t;
222 
223 struct ath_buf {
224 	int			bf_flags;	/* tx descriptor flags */
225 	struct ath_desc		*bf_desc;	/* virtual addr of desc */
226 	struct ath_desc_status	bf_status;	/* tx/rx status */
227 	uint32_t		bf_daddr;	/* physical addr of desc */
228 	dma_area_t		bf_dma;		/* dma area for buf */
229 	mblk_t			*bf_m;		/* message for buf */
230 	struct ieee80211_node	*bf_in;		/* pointer to the node */
231 
232 	/* we're in list of asc->asc_txbuf_list or asc->asc_rxbuf_list */
233 	list_node_t		bf_node;
234 };
235 
236 
237 /*
238  * Data transmit queue state.  One of these exists for each
239  * hardware transmit queue.  Packets sent to us from above
240  * are assigned to queues based on their priority.  Not all
241  * devices support a complete set of hardware transmit queues.
242  * For those devices the array sc_ac2q will map multiple
243  * priorities to fewer hardware queues (typically all to one
244  * hardware queue).
245  */
246 struct ath_txq {
247 	uint_t		axq_qnum;	/* hardware q number */
248 	uint_t		axq_depth;	/* queue depth (stat only) */
249 	uint_t		axq_intrcnt;	/* interrupt count */
250 	uint32_t	*axq_link;	/* link ptr in last TX desc */
251 	list_t		axq_list;	/* transmit queue */
252 	kmutex_t	axq_lock;	/* lock on q and link */
253 };
254 
255 
256 /*
257  * asc_isc must be the first element, for convience of
258  * casting between iee80211com and ath
259  */
260 typedef struct ath {
261 	ieee80211com_t		asc_isc;	/* IEEE 802.11 common */
262 	dev_info_t		*asc_dev;	/* back pointer to dev_info_t */
263 	ddi_taskq_t		*asc_tq;	/* private task queue */
264 	struct ath_hal		*asc_ah;	/* Atheros HAL */
265 	uint32_t		asc_invalid : 1, /* being detached */
266 				asc_isrunning : 1, /* device is operational */
267 				asc_mrretry : 1, /* multi-rate retry support */
268 				asc_have11g : 1, /* have 11g support */
269 				asc_splitmic : 1, /* Split TKIP mic keys */
270 				asc_hasclrkey: 1; /* CLR key supported */
271 	const HAL_RATE_TABLE	*asc_rates[IEEE80211_MODE_MAX]; /* h/w rate */
272 	uint8_t			asc_protrix;	/* protect rate index */
273 	uint8_t			asc_mcastantenna; /* Multicast antenna number */
274 
275 	ddi_acc_handle_t	asc_cfg_handle;	/* DDI I/O handle */
276 	ddi_acc_handle_t	asc_io_handle;	/* DDI I/O handle */
277 	uint16_t		asc_cachelsz;	/* cache line size */
278 	ddi_iblock_cookie_t	asc_iblock;
279 	ddi_softintr_t		asc_softint_id;
280 
281 	struct ath_desc		*asc_desc;	/* TX/RX descriptors */
282 	dma_area_t		asc_desc_dma;	/* descriptor structure */
283 	/* pointer to the first "struct ath_buf" */
284 	struct ath_buf		*asc_vbufptr;
285 	/* length of all allocated "struct ath_buf" */
286 	uint32_t		asc_vbuflen;
287 	/* size of one DMA TX/RX buffer based on 802.11 MTU */
288 	int32_t			asc_dmabuf_size;
289 
290 	list_t			asc_rxbuf_list;
291 	kmutex_t		asc_rxbuflock;	/* recv lock for above data */
292 	uint32_t		*asc_rxlink;	/* link ptr in last RX desc */
293 	uint32_t		asc_rx_pend;
294 	uint64_t		asc_lastrx;	/* tsf at last rx'd frame */
295 
296 	list_t			asc_txbuf_list;
297 	kmutex_t		asc_txbuflock;	/* txbuf lock */
298 
299 	uint_t			asc_txqsetup;	/* h/w queues setup */
300 	struct ath_txq		asc_txq[HAL_NUM_TX_QUEUES]; /* tx queues */
301 	struct ath_txq		*asc_ac2q[5];	/* WME AC -> h/w qnum */
302 
303 	const HAL_RATE_TABLE	*asc_currates;	/* current rate table */
304 	enum ieee80211_phymode	asc_curmode;	/* current phy mode */
305 	HAL_CHANNEL		asc_curchan;	/* current h/w channel */
306 	uint8_t			asc_rixmap[256]; /* IEEE to h/w rate table ix */
307 	HAL_INT			asc_imask;	/* interrupt mask copy */
308 	struct ath_stats	asc_stats;	/* interface statistics */
309 	boolean_t		asc_promisc;	/* Promiscuous mode enabled */
310 	uint8_t			asc_mcast_refs[ATH_MCHASH]; /* refer count */
311 	uint32_t		asc_mcast_hash[2]; /* multicast hash table */
312 	kmutex_t		asc_genlock;
313 
314 	boolean_t		asc_resched_needed;
315 	kmutex_t		asc_resched_lock;
316 
317 	uint32_t		asc_keymax;	/* size of key cache */
318 	uint8_t			asc_keymap[16];	/* bit map of key cache use */
319 
320 	timeout_id_t		asc_scan_timer;
321 	int			(*asc_newstate)(ieee80211com_t *,
322 					enum ieee80211_state, int);
323 } ath_t;
324 
325 #define	ATH_STATE(macinfo)	((ath_t *)((macinfo)->gldm_private))
326 
327 #define	ATH_LOCK(_asc)		mutex_enter(&(_asc)->asc_genlock)
328 #define	ATH_UNLOCK(_asc)	mutex_exit(&(_asc)->asc_genlock)
329 #define	ATH_LOCK_ASSERT(_asc)	ASSERT(mutex_owned(&(_asc)->asc_genlock))
330 
331 #define	ATH_IS_RUNNING(_asc)	\
332 	(((_asc)->asc_invalid == 0) && ((_asc)->asc_isrunning == 1))
333 
334 /* Debug and log functions */
335 void ath_dbg(uint32_t dbg_flags, const char *fmt, ...);	/* debug function */
336 void ath_log(const char *fmt, ...);	/* event log function */
337 void ath_problem(const char *fmt, ...);	/* run-time problem function */
338 
339 #ifdef __cplusplus
340 }
341 #endif
342 
343 #endif /* _ATH_IMPL_H */
344