1 /*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30 #include <sys/cdefs.h>
31 /*
32 * Driver for the Atheros Wireless LAN controller.
33 *
34 * This software is derived from work of Atsushi Onoe; his contribution
35 * is greatly appreciated.
36 */
37
38 #include "opt_inet.h"
39 #include "opt_ath.h"
40 /*
41 * This is needed for register operations which are performed
42 * by the driver - eg, calls to ath_hal_gettsf32().
43 *
44 * It's also required for any AH_DEBUG checks in here, eg the
45 * module dependencies.
46 */
47 #include "opt_ah.h"
48 #include "opt_wlan.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/sysctl.h>
53 #include <sys/mbuf.h>
54 #include <sys/malloc.h>
55 #include <sys/lock.h>
56 #include <sys/mutex.h>
57 #include <sys/kernel.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/errno.h>
61 #include <sys/callout.h>
62 #include <sys/bus.h>
63 #include <sys/endian.h>
64 #include <sys/kthread.h>
65 #include <sys/taskqueue.h>
66 #include <sys/priv.h>
67 #include <sys/module.h>
68 #include <sys/ktr.h>
69 #include <sys/smp.h> /* for mp_ncpus */
70
71 #include <machine/bus.h>
72
73 #include <net/if.h>
74 #include <net/if_var.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/if_arp.h>
79 #include <net/ethernet.h>
80 #include <net/if_llc.h>
81
82 #include <net80211/ieee80211_var.h>
83 #include <net80211/ieee80211_regdomain.h>
84 #ifdef IEEE80211_SUPPORT_SUPERG
85 #include <net80211/ieee80211_superg.h>
86 #endif
87 #ifdef IEEE80211_SUPPORT_TDMA
88 #include <net80211/ieee80211_tdma.h>
89 #endif
90
91 #include <net/bpf.h>
92
93 #ifdef INET
94 #include <netinet/in.h>
95 #include <netinet/if_ether.h>
96 #endif
97
98 #include <dev/ath/if_athvar.h>
99 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
100 #include <dev/ath/ath_hal/ah_diagcodes.h>
101
102 #include <dev/ath/if_ath_debug.h>
103 #include <dev/ath/if_ath_misc.h>
104 #if 0
105 #include <dev/ath/if_ath_tsf.h>
106 #include <dev/ath/if_ath_tx.h>
107 #include <dev/ath/if_ath_sysctl.h>
108 #include <dev/ath/if_ath_led.h>
109 #include <dev/ath/if_ath_keycache.h>
110 #include <dev/ath/if_ath_rx.h>
111 #include <dev/ath/if_ath_rx_edma.h>
112 #include <dev/ath/if_ath_tx_edma.h>
113 #include <dev/ath/if_ath_beacon.h>
114 #include <dev/ath/if_ath_btcoex.h>
115 #include <dev/ath/if_ath_spectral.h>
116 #include <dev/ath/if_ath_lna_div.h>
117 #include <dev/ath/if_athdfs.h>
118 #endif
119 #include <dev/ath/if_ath_descdma.h>
120
121 MALLOC_DECLARE(M_ATHDEV);
122
123 /*
124 * This is the descriptor setup / busdma memory intialisation and
125 * teardown routines.
126 */
127
128 static void
ath_load_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)129 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
130 {
131 bus_addr_t *paddr = (bus_addr_t*) arg;
132 KASSERT(error == 0, ("error %u on bus_dma callback", error));
133 *paddr = segs->ds_addr;
134 }
135
136 /*
137 * Allocate the descriptors and appropriate DMA tag/setup.
138 *
139 * For some situations (eg EDMA TX completion), there isn't a requirement
140 * for the ath_buf entries to be allocated.
141 */
142 int
ath_descdma_alloc_desc(struct ath_softc * sc,struct ath_descdma * dd,ath_bufhead * head,const char * name,int ds_size,int ndesc)143 ath_descdma_alloc_desc(struct ath_softc *sc,
144 struct ath_descdma *dd, ath_bufhead *head,
145 const char *name, int ds_size, int ndesc)
146 {
147 #define DS2PHYS(_dd, _ds) \
148 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
149 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
150 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
151 int error;
152
153 dd->dd_descsize = ds_size;
154
155 DPRINTF(sc, ATH_DEBUG_RESET,
156 "%s: %s DMA: %u desc, %d bytes per descriptor\n",
157 __func__, name, ndesc, dd->dd_descsize);
158
159 dd->dd_name = name;
160 dd->dd_desc_len = dd->dd_descsize * ndesc;
161
162 /*
163 * Merlin work-around:
164 * Descriptors that cross the 4KB boundary can't be used.
165 * Assume one skipped descriptor per 4KB page.
166 */
167 if (! ath_hal_split4ktrans(sc->sc_ah)) {
168 int numpages = dd->dd_desc_len / 4096;
169 dd->dd_desc_len += ds_size * numpages;
170 }
171
172 /*
173 * Setup DMA descriptor area.
174 *
175 * BUS_DMA_ALLOCNOW is not used; we never use bounce
176 * buffers for the descriptors themselves.
177 */
178 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
179 PAGE_SIZE, 0, /* alignment, bounds */
180 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
181 BUS_SPACE_MAXADDR, /* highaddr */
182 NULL, NULL, /* filter, filterarg */
183 dd->dd_desc_len, /* maxsize */
184 1, /* nsegments */
185 dd->dd_desc_len, /* maxsegsize */
186 0, /* flags */
187 NULL, /* lockfunc */
188 NULL, /* lockarg */
189 &dd->dd_dmat);
190 if (error != 0) {
191 device_printf(sc->sc_dev,
192 "cannot allocate %s DMA tag\n", dd->dd_name);
193 return error;
194 }
195
196 /* allocate descriptors */
197 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
198 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
199 &dd->dd_dmamap);
200 if (error != 0) {
201 device_printf(sc->sc_dev,
202 "unable to alloc memory for %u %s descriptors, error %u\n",
203 ndesc, dd->dd_name, error);
204 goto fail1;
205 }
206
207 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
208 dd->dd_desc, dd->dd_desc_len,
209 ath_load_cb, &dd->dd_desc_paddr,
210 BUS_DMA_NOWAIT);
211 if (error != 0) {
212 device_printf(sc->sc_dev,
213 "unable to map %s descriptors, error %u\n",
214 dd->dd_name, error);
215 goto fail2;
216 }
217
218 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
219 __func__, dd->dd_name, (uint8_t *) dd->dd_desc,
220 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr,
221 /*XXX*/ (u_long) dd->dd_desc_len);
222
223 return (0);
224
225 fail2:
226 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
227 fail1:
228 bus_dma_tag_destroy(dd->dd_dmat);
229 memset(dd, 0, sizeof(*dd));
230 return error;
231 #undef DS2PHYS
232 #undef ATH_DESC_4KB_BOUND_CHECK
233 }
234
235 int
ath_descdma_setup(struct ath_softc * sc,struct ath_descdma * dd,ath_bufhead * head,const char * name,int ds_size,int nbuf,int ndesc)236 ath_descdma_setup(struct ath_softc *sc,
237 struct ath_descdma *dd, ath_bufhead *head,
238 const char *name, int ds_size, int nbuf, int ndesc)
239 {
240 #define DS2PHYS(_dd, _ds) \
241 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
242 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
243 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
244 uint8_t *ds;
245 struct ath_buf *bf;
246 int i, bsize, error;
247
248 /* Allocate descriptors */
249 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size,
250 nbuf * ndesc);
251
252 /* Assume any errors during allocation were dealt with */
253 if (error != 0) {
254 return (error);
255 }
256
257 ds = (uint8_t *) dd->dd_desc;
258
259 /* allocate rx buffers */
260 bsize = sizeof(struct ath_buf) * nbuf;
261 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
262 if (bf == NULL) {
263 device_printf(sc->sc_dev,
264 "malloc of %s buffers failed, size %u\n",
265 dd->dd_name, bsize);
266 goto fail3;
267 }
268 dd->dd_bufptr = bf;
269
270 TAILQ_INIT(head);
271 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) {
272 bf->bf_desc = (struct ath_desc *) ds;
273 bf->bf_daddr = DS2PHYS(dd, ds);
274 if (! ath_hal_split4ktrans(sc->sc_ah)) {
275 /*
276 * Merlin WAR: Skip descriptor addresses which
277 * cause 4KB boundary crossing along any point
278 * in the descriptor.
279 */
280 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
281 dd->dd_descsize)) {
282 /* Start at the next page */
283 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
284 bf->bf_desc = (struct ath_desc *) ds;
285 bf->bf_daddr = DS2PHYS(dd, ds);
286 }
287 }
288 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
289 &bf->bf_dmamap);
290 if (error != 0) {
291 device_printf(sc->sc_dev, "unable to create dmamap "
292 "for %s buffer %u, error %u\n",
293 dd->dd_name, i, error);
294 ath_descdma_cleanup(sc, dd, head);
295 return error;
296 }
297 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
298 TAILQ_INSERT_TAIL(head, bf, bf_list);
299 }
300
301 /*
302 * XXX TODO: ensure that ds doesn't overflow the descriptor
303 * allocation otherwise weird stuff will occur and crash your
304 * machine.
305 */
306 return 0;
307 /* XXX this should likely just call ath_descdma_cleanup() */
308 fail3:
309 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
310 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
311 bus_dma_tag_destroy(dd->dd_dmat);
312 memset(dd, 0, sizeof(*dd));
313 return error;
314 #undef DS2PHYS
315 #undef ATH_DESC_4KB_BOUND_CHECK
316 }
317
318 /*
319 * Allocate ath_buf entries but no descriptor contents.
320 *
321 * This is for RX EDMA where the descriptors are the header part of
322 * the RX buffer.
323 */
324 int
ath_descdma_setup_rx_edma(struct ath_softc * sc,struct ath_descdma * dd,ath_bufhead * head,const char * name,int nbuf,int rx_status_len)325 ath_descdma_setup_rx_edma(struct ath_softc *sc,
326 struct ath_descdma *dd, ath_bufhead *head,
327 const char *name, int nbuf, int rx_status_len)
328 {
329 struct ath_buf *bf;
330 int i, bsize, error;
331
332 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n",
333 __func__, name, nbuf);
334
335 dd->dd_name = name;
336 /*
337 * This is (mostly) purely for show. We're not allocating any actual
338 * descriptors here as EDMA RX has the descriptor be part
339 * of the RX buffer.
340 *
341 * However, dd_desc_len is used by ath_descdma_free() to determine
342 * whether we have already freed this DMA mapping.
343 */
344 dd->dd_desc_len = rx_status_len * nbuf;
345 dd->dd_descsize = rx_status_len;
346
347 /* allocate rx buffers */
348 bsize = sizeof(struct ath_buf) * nbuf;
349 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
350 if (bf == NULL) {
351 device_printf(sc->sc_dev,
352 "malloc of %s buffers failed, size %u\n",
353 dd->dd_name, bsize);
354 error = ENOMEM;
355 goto fail3;
356 }
357 dd->dd_bufptr = bf;
358
359 TAILQ_INIT(head);
360 for (i = 0; i < nbuf; i++, bf++) {
361 bf->bf_desc = NULL;
362 bf->bf_daddr = 0;
363 bf->bf_lastds = NULL; /* Just an initial value */
364
365 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
366 &bf->bf_dmamap);
367 if (error != 0) {
368 device_printf(sc->sc_dev, "unable to create dmamap "
369 "for %s buffer %u, error %u\n",
370 dd->dd_name, i, error);
371 ath_descdma_cleanup(sc, dd, head);
372 return error;
373 }
374 TAILQ_INSERT_TAIL(head, bf, bf_list);
375 }
376 return 0;
377 fail3:
378 memset(dd, 0, sizeof(*dd));
379 return error;
380 }
381
382 void
ath_descdma_cleanup(struct ath_softc * sc,struct ath_descdma * dd,ath_bufhead * head)383 ath_descdma_cleanup(struct ath_softc *sc,
384 struct ath_descdma *dd, ath_bufhead *head)
385 {
386 struct ath_buf *bf;
387 struct ieee80211_node *ni;
388 int do_warning = 0;
389
390 if (dd->dd_dmamap != 0) {
391 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
392 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
393 bus_dma_tag_destroy(dd->dd_dmat);
394 }
395
396 if (head != NULL) {
397 TAILQ_FOREACH(bf, head, bf_list) {
398 if (bf->bf_m) {
399 /*
400 * XXX warn if there's buffers here.
401 * XXX it should have been freed by the
402 * owner!
403 */
404
405 if (do_warning == 0) {
406 do_warning = 1;
407 device_printf(sc->sc_dev,
408 "%s: %s: mbuf should've been"
409 " unmapped/freed!\n",
410 __func__,
411 dd->dd_name);
412 }
413 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
414 BUS_DMASYNC_POSTREAD);
415 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
416 m_freem(bf->bf_m);
417 bf->bf_m = NULL;
418 }
419 if (bf->bf_dmamap != NULL) {
420 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
421 bf->bf_dmamap = NULL;
422 }
423 ni = bf->bf_node;
424 bf->bf_node = NULL;
425 if (ni != NULL) {
426 /*
427 * Reclaim node reference.
428 */
429 ieee80211_free_node(ni);
430 }
431 }
432 }
433
434 if (head != NULL)
435 TAILQ_INIT(head);
436
437 if (dd->dd_bufptr != NULL)
438 free(dd->dd_bufptr, M_ATHDEV);
439 memset(dd, 0, sizeof(*dd));
440 }
441