1 /*
2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 * Use is subject to license terms.
4 */
5
6 /*
7 * Copyright (c) 2008 Atheros Communications Inc.
8 *
9 * Permission to use, copy, modify, and/or distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22 #include <sys/param.h>
23 #include <sys/types.h>
24 #include <sys/cmn_err.h>
25 #include <sys/kmem.h>
26 #include <sys/ddi.h>
27 #include <sys/sunddi.h>
28 #include <sys/varargs.h>
29
30 #include "arn_ath9k.h"
31 #include "arn_core.h"
32 #include "arn_hw.h"
33 #include "arn_reg.h"
34 #include "arn_phy.h"
35 #include "arn_initvals.h"
36
37 static const uint8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
38
39 extern struct hal_percal_data iq_cal_multi_sample;
40 extern struct hal_percal_data iq_cal_single_sample;
41 extern struct hal_percal_data adc_gain_cal_multi_sample;
42 extern struct hal_percal_data adc_gain_cal_single_sample;
43 extern struct hal_percal_data adc_dc_cal_multi_sample;
44 extern struct hal_percal_data adc_dc_cal_single_sample;
45 extern struct hal_percal_data adc_init_dc_cal;
46
47 static boolean_t ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type);
48 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
49 enum ath9k_ht_macmode macmode);
50 static uint32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
51 struct ar5416_eeprom_def *pEepData,
52 uint32_t reg, uint32_t value);
53 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
54 struct ath9k_channel *chan);
55 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
56 struct ath9k_channel *chan);
57
58 /* Helper Functions */
59
60 static uint32_t
ath9k_hw_mac_usec(struct ath_hal * ah,uint32_t clks)61 ath9k_hw_mac_usec(struct ath_hal *ah, uint32_t clks)
62 {
63 if (ah->ah_curchan != NULL)
64 return (clks /
65 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]);
66 else
67 return (clks / CLOCK_RATE[ATH9K_MODE_11B]);
68 }
69
70 static uint32_t
ath9k_hw_mac_to_usec(struct ath_hal * ah,uint32_t clks)71 ath9k_hw_mac_to_usec(struct ath_hal *ah, uint32_t clks)
72 {
73 struct ath9k_channel *chan = ah->ah_curchan;
74
75 if (chan && IS_CHAN_HT40(chan))
76 return (ath9k_hw_mac_usec(ah, clks) / 2);
77 else
78 return (ath9k_hw_mac_usec(ah, clks));
79 }
80
81 static uint32_t
ath9k_hw_mac_clks(struct ath_hal * ah,uint32_t usecs)82 ath9k_hw_mac_clks(struct ath_hal *ah, uint32_t usecs)
83 {
84 if (ah->ah_curchan != NULL)
85 return (usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
86 ah->ah_curchan)]);
87 else
88 return (usecs * CLOCK_RATE[ATH9K_MODE_11B]);
89 }
90
91 static uint32_t
ath9k_hw_mac_to_clks(struct ath_hal * ah,uint32_t usecs)92 ath9k_hw_mac_to_clks(struct ath_hal *ah, uint32_t usecs)
93 {
94 struct ath9k_channel *chan = ah->ah_curchan;
95
96 if (chan && IS_CHAN_HT40(chan))
97 return (ath9k_hw_mac_clks(ah, usecs) * 2);
98 else
99 return (ath9k_hw_mac_clks(ah, usecs));
100 }
101
102 /* ARGSUSED */
103 enum wireless_mode
ath9k_hw_chan2wmode(struct ath_hal * ah,const struct ath9k_channel * chan)104 ath9k_hw_chan2wmode(struct ath_hal *ah, const struct ath9k_channel *chan)
105 {
106 if (IS_CHAN_B(chan))
107 return (ATH9K_MODE_11B);
108 if (IS_CHAN_G(chan))
109 return (ATH9K_MODE_11G);
110
111 return (ATH9K_MODE_11A);
112 }
113
114 boolean_t
ath9k_hw_wait(struct ath_hal * ah,uint32_t reg,uint32_t mask,uint32_t val)115 ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask, uint32_t val)
116 {
117 int i;
118
119 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
120 if ((REG_READ(ah, reg) & mask) == val)
121 return (B_TRUE);
122
123 drv_usecwait(AH_TIME_QUANTUM);
124 }
125 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_wait(): "
126 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 reg, REG_READ(ah, reg), mask, val));
128
129 return (B_FALSE);
130 }
131
132 uint32_t
ath9k_hw_reverse_bits(uint32_t val,uint32_t n)133 ath9k_hw_reverse_bits(uint32_t val, uint32_t n)
134 {
135 uint32_t retval;
136 int i;
137
138 for (i = 0, retval = 0; i < n; i++) {
139 retval = (retval << 1) | (val & 1);
140 val >>= 1;
141 }
142 return (retval);
143 }
144
145 boolean_t
ath9k_get_channel_edges(struct ath_hal * ah,uint16_t flags,uint16_t * low,uint16_t * high)146 ath9k_get_channel_edges(struct ath_hal *ah,
147 uint16_t flags, uint16_t *low, uint16_t *high)
148 {
149 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
150
151 if (flags & CHANNEL_5GHZ) {
152 *low = pCap->low_5ghz_chan;
153 *high = pCap->high_5ghz_chan;
154 return (B_TRUE);
155 }
156 if ((flags & CHANNEL_2GHZ)) {
157 *low = pCap->low_2ghz_chan;
158 *high = pCap->high_2ghz_chan;
159 return (B_TRUE);
160 }
161 return (B_FALSE);
162 }
163
164 uint16_t
ath9k_hw_computetxtime(struct ath_hal * ah,struct ath_rate_table * rates,uint32_t frameLen,uint16_t rateix,boolean_t shortPreamble)165 ath9k_hw_computetxtime(struct ath_hal *ah,
166 struct ath_rate_table *rates,
167 uint32_t frameLen, uint16_t rateix,
168 boolean_t shortPreamble)
169 {
170 uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
171 uint32_t kbps;
172
173 kbps = rates->info[rateix].ratekbps;
174
175 if (kbps == 0)
176 return (0);
177
178 switch (rates->info[rateix].phy) {
179 case WLAN_RC_PHY_CCK:
180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
181 if (shortPreamble && rates->info[rateix].short_preamble)
182 phyTime >>= 1;
183 numBits = frameLen << 3;
184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
185 break;
186 case WLAN_RC_PHY_OFDM:
187 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
188 bitsPerSymbol =
189 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER +
193 OFDM_PREAMBLE_TIME_QUARTER +
194 (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
195 } else if (ah->ah_curchan &&
196 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF +
202 (numSymbols * OFDM_SYMBOL_TIME_HALF);
203 } else {
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME +
208 (numSymbols * OFDM_SYMBOL_TIME);
209 }
210 break;
211 default:
212 arn_problem("arn: "
213 "%s: unknown phy %u (rate ix %u)\n", __func__,
214 rates->info[rateix].phy, rateix);
215 txTime = 0;
216 break;
217 }
218
219 return ((uint16_t)txTime);
220 }
221
222 uint32_t
ath9k_hw_mhz2ieee(struct ath_hal * ah,uint32_t freq,uint32_t flags)223 ath9k_hw_mhz2ieee(struct ath_hal *ah, uint32_t freq, uint32_t flags)
224 {
225 if (flags & CHANNEL_2GHZ) {
226 if (freq == 2484)
227 return (14);
228 if (freq < 2484)
229 return ((freq - 2407) / 5);
230 else
231 return (15 + ((freq - 2512) / 20));
232 } else if (flags & CHANNEL_5GHZ) {
233 if (ath9k_regd_is_public_safety_sku(ah) &&
234 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
235 return (((freq * 10) +
236 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5);
237 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
238 return ((freq - 4000) / 5);
239 } else {
240 return ((freq - 5000) / 5);
241 }
242 } else {
243 if (freq == 2484)
244 return (14);
245 if (freq < 2484)
246 return ((freq - 2407) / 5);
247 if (freq < 5000) {
248 if (ath9k_regd_is_public_safety_sku(ah) &&
249 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
250 return (((freq * 10) +
251 (((freq % 5) ==
252 2) ? 5 : 0) - 49400) / 5);
253 } else if (freq > 4900) {
254 return ((freq - 4000) / 5);
255 } else {
256 return (15 + ((freq - 2512) / 20));
257 }
258 }
259 return ((freq - 5000) / 5);
260 }
261 }
262
263 void
ath9k_hw_get_channel_centers(struct ath_hal * ah,struct ath9k_channel * chan,struct chan_centers * centers)264 ath9k_hw_get_channel_centers(struct ath_hal *ah,
265 struct ath9k_channel *chan,
266 struct chan_centers *centers)
267 {
268 int8_t extoff;
269 struct ath_hal_5416 *ahp = AH5416(ah);
270
271 if (!IS_CHAN_HT40(chan)) {
272 centers->ctl_center = centers->ext_center =
273 centers->synth_center = chan->channel;
274 return;
275 }
276
277 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
278 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
279 centers->synth_center =
280 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
281 extoff = 1;
282 } else {
283 centers->synth_center =
284 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
285 extoff = -1;
286 }
287
288 centers->ctl_center =
289 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
290 centers->ext_center =
291 centers->synth_center + (extoff *
292 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
293 HT40_CHANNEL_CENTER_SHIFT : 15));
294
295 }
296
297 /* Chip Revisions */
298
299 static void
ath9k_hw_read_revisions(struct ath_hal * ah)300 ath9k_hw_read_revisions(struct ath_hal *ah)
301 {
302 uint32_t val;
303
304 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
305
306 if (val == 0xFF) {
307 val = REG_READ(ah, AR_SREV);
308 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
309 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
310 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
311 } else {
312 if (!AR_SREV_9100(ah))
313 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
314
315 ah->ah_macRev = val & AR_SREV_REVISION;
316
317 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
318 ah->ah_isPciExpress = B_TRUE;
319 }
320 }
321
322 static int
ath9k_hw_get_radiorev(struct ath_hal * ah)323 ath9k_hw_get_radiorev(struct ath_hal *ah)
324 {
325 uint32_t val;
326 int i;
327
328 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
329
330 for (i = 0; i < 8; i++)
331 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
332 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
333 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
334
335 return (ath9k_hw_reverse_bits(val, 8));
336 }
337
338 /* HW Attach, Detach, Init Routines */
339
340 static void
ath9k_hw_disablepcie(struct ath_hal * ah)341 ath9k_hw_disablepcie(struct ath_hal *ah)
342 {
343 if (!AR_SREV_9100(ah))
344 return;
345
346 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
347 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
348 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
349 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
350 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
351 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
352 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
353 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
354 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
355
356 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
357 }
358
359 static boolean_t
ath9k_hw_chip_test(struct ath_hal * ah)360 ath9k_hw_chip_test(struct ath_hal *ah)
361 {
362 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
363 uint32_t regHold[2];
364 uint32_t patternData[4] = { 0x55555555, 0xaaaaaaaa,
365 0x66666666, 0x99999999 };
366 int i, j;
367
368 for (i = 0; i < 2; i++) {
369 uint32_t addr = regAddr[i];
370 uint32_t wrData, rdData;
371
372 regHold[i] = REG_READ(ah, addr);
373 for (j = 0; j < 0x100; j++) {
374 wrData = (j << 16) | j;
375 REG_WRITE(ah, addr, wrData);
376 rdData = REG_READ(ah, addr);
377 if (rdData != wrData) {
378 ARN_DBG((ARN_DBG_REG_IO,
379 "arn: ath9k_hw_chip_test(): "
380 "address test failed "
381 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
382 addr, wrData, rdData));
383
384 return (B_FALSE);
385 }
386 }
387 for (j = 0; j < 4; j++) {
388 wrData = patternData[j];
389 REG_WRITE(ah, addr, wrData);
390 rdData = REG_READ(ah, addr);
391 if (wrData != rdData) {
392 ARN_DBG((ARN_DBG_REG_IO,
393 "arn: ath9k_hw_chip_test(): "
394 "address test failed "
395 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
396 addr, wrData, rdData));
397
398 return (B_FALSE);
399 }
400 }
401 REG_WRITE(ah, regAddr[i], regHold[i]);
402 }
403 drv_usecwait(100);
404
405 return (B_TRUE);
406 }
407
408 static const char *
ath9k_hw_devname(uint16_t devid)409 ath9k_hw_devname(uint16_t devid)
410 {
411 switch (devid) {
412 case AR5416_DEVID_PCI:
413 return ("Atheros 5416");
414 case AR5416_DEVID_PCIE:
415 return ("Atheros 5418");
416 case AR9160_DEVID_PCI:
417 return ("Atheros 9160");
418 case AR9280_DEVID_PCI:
419 case AR9280_DEVID_PCIE:
420 return ("Atheros 9280");
421 case AR9285_DEVID_PCIE:
422 return ("Atheros 9285");
423 }
424
425 return (NULL);
426 }
427
428 static void
ath9k_hw_set_defaults(struct ath_hal * ah)429 ath9k_hw_set_defaults(struct ath_hal *ah)
430 {
431 int i;
432
433 ah->ah_config.dma_beacon_response_time = 2;
434 ah->ah_config.sw_beacon_response_time = 10;
435 ah->ah_config.additional_swba_backoff = 0;
436 ah->ah_config.ack_6mb = 0x0;
437 ah->ah_config.cwm_ignore_extcca = 0;
438 ah->ah_config.pcie_powersave_enable = 0;
439 ah->ah_config.pcie_l1skp_enable = 0;
440 ah->ah_config.pcie_clock_req = 0;
441 ah->ah_config.pcie_power_reset = 0x100;
442 ah->ah_config.pcie_restore = 0;
443 ah->ah_config.pcie_waen = 0;
444 ah->ah_config.analog_shiftreg = 1;
445 ah->ah_config.ht_enable = 1;
446 ah->ah_config.ofdm_trig_low = 200;
447 ah->ah_config.ofdm_trig_high = 500;
448 ah->ah_config.cck_trig_high = 200;
449 ah->ah_config.cck_trig_low = 100;
450 ah->ah_config.enable_ani = 1;
451 ah->ah_config.noise_immunity_level = 4;
452 ah->ah_config.ofdm_weaksignal_det = 1;
453 ah->ah_config.cck_weaksignal_thr = 0;
454 ah->ah_config.spur_immunity_level = 2;
455 ah->ah_config.firstep_level = 0;
456 ah->ah_config.rssi_thr_high = 40;
457 ah->ah_config.rssi_thr_low = 7;
458 ah->ah_config.diversity_control = 0;
459 ah->ah_config.antenna_switch_swap = 0;
460
461 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
462 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
463 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
464 }
465
466 ah->ah_config.intr_mitigation = 1;
467
468 /*
469 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
470 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
471 * This means we use it for all AR5416 devices, and the few
472 * minor PCI AR9280 devices out there.
473 *
474 * Serialization is required because these devices do not handle
475 * well the case of two concurrent reads/writes due to the latency
476 * involved. During one read/write another read/write can be issued
477 * on another CPU while the previous read/write may still be working
478 * on our hardware, if we hit this case the hardware poops in a loop.
479 * We prevent this by serializing reads and writes.
480 *
481 * This issue is not present on PCI-Express devices or pre-AR5416
482 * devices (legacy, 802.11abg).
483 */
484
485 /* num_of_cpus */
486 }
487
488 static struct ath_hal_5416 *
ath9k_hw_newstate(uint16_t device_id,struct arn_softc * sc,caddr_t mem,int * status)489 ath9k_hw_newstate(uint16_t device_id, struct arn_softc *sc, caddr_t mem,
490 int *status)
491 {
492 static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
493 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
494 struct ath_hal_5416 *ahp;
495 struct ath_hal *ah;
496
497 ahp = (struct ath_hal_5416 *)
498 kmem_zalloc(sizeof (struct ath_hal_5416), KM_SLEEP);
499 if (ahp == NULL) {
500 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_newstate(): "
501 "failed to alloc mem for ahp\n"));
502 *status = ENOMEM;
503 return (NULL);
504 }
505
506 ah = &ahp->ah;
507 ah->ah_sc = sc;
508 ah->ah_sh = mem;
509 ah->ah_magic = AR5416_MAGIC;
510 ah->ah_countryCode = CTRY_DEFAULT;
511 ah->ah_devid = device_id;
512 ah->ah_subvendorid = 0;
513
514 ah->ah_flags = 0;
515 if ((device_id == AR5416_AR9100_DEVID))
516 ah->ah_macVersion = AR_SREV_VERSION_9100;
517 if (!AR_SREV_9100(ah))
518 ah->ah_flags = AH_USE_EEPROM;
519
520 ah->ah_powerLimit = MAX_RATE_POWER;
521 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
522 ahp->ah_atimWindow = 0;
523 ahp->ah_diversityControl = ah->ah_config.diversity_control;
524 ahp->ah_antennaSwitchSwap =
525 ah->ah_config.antenna_switch_swap;
526 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
527 ahp->ah_beaconInterval = 100;
528 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
529 ahp->ah_slottime = (uint32_t)-1;
530 ahp->ah_acktimeout = (uint32_t)-1;
531 ahp->ah_ctstimeout = (uint32_t)-1;
532 ahp->ah_globaltxtimeout = (uint32_t)-1;
533 (void) memcpy(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
534
535 ahp->ah_gBeaconRate = 0;
536
537 return (ahp);
538 }
539
540 static int
ath9k_hw_rfattach(struct ath_hal * ah)541 ath9k_hw_rfattach(struct ath_hal *ah)
542 {
543 boolean_t rfStatus = B_FALSE;
544 int ecode = 0;
545
546 rfStatus = ath9k_hw_init_rf(ah, &ecode);
547 if (!rfStatus) {
548 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_rfattach(): "
549 "RF setup failed, status %u\n", ecode));
550
551 return (ecode);
552 }
553
554 return (0);
555 }
556
557 static int
ath9k_hw_rf_claim(struct ath_hal * ah)558 ath9k_hw_rf_claim(struct ath_hal *ah)
559 {
560 uint32_t val;
561
562 REG_WRITE(ah, AR_PHY(0), 0x00000007);
563
564 val = ath9k_hw_get_radiorev(ah);
565 switch (val & AR_RADIO_SREV_MAJOR) {
566 case 0:
567 val = AR_RAD5133_SREV_MAJOR;
568 break;
569 case AR_RAD5133_SREV_MAJOR:
570 case AR_RAD5122_SREV_MAJOR:
571 case AR_RAD2133_SREV_MAJOR:
572 case AR_RAD2122_SREV_MAJOR:
573 break;
574 default:
575 ARN_DBG((ARN_DBG_CHANNEL,
576 "arn: ath9k_hw_rf_claim(): "
577 "5G Radio Chip Rev 0x%02X "
578 "is not supported by this driver\n",
579 ah->ah_analog5GhzRev));
580
581 return (ENOTSUP);
582 }
583
584 ah->ah_analog5GhzRev = (uint16_t)val;
585
586 return (0);
587 }
588
589 static int
ath9k_hw_init_macaddr(struct ath_hal * ah)590 ath9k_hw_init_macaddr(struct ath_hal *ah)
591 {
592 uint32_t sum;
593 int i;
594 uint16_t eeval;
595 struct ath_hal_5416 *ahp = AH5416(ah);
596
597 sum = 0;
598 for (i = 0; i < 3; i++) {
599 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
600 sum += eeval;
601 ahp->ah_macaddr[2 * i] = eeval >> 8;
602 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
603 }
604 if (sum == 0 || sum == 0xffff * 3) {
605 ARN_DBG((ARN_DBG_EEPROM, "arn: ath9k_hw_init_macaddr(): "
606 "mac address read failed: %pM\n",
607 ahp->ah_macaddr));
608
609 return (EADDRNOTAVAIL);
610 }
611
612 return (0);
613 }
614
615 static void
ath9k_hw_init_rxgain_ini(struct ath_hal * ah)616 ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
617 {
618 uint32_t rxgain_type;
619 struct ath_hal_5416 *ahp = AH5416(ah);
620
621 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
622 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
623 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) {
624 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
625 ar9280Modes_backoff_13db_rxgain_9280_2,
626 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2),
627 6);
628 } else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) {
629 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
630 ar9280Modes_backoff_23db_rxgain_9280_2,
631 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2),
632 6);
633 } else {
634 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
635 ar9280Modes_original_rxgain_9280_2,
636 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
637 }
638 } else {
639 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
640 ar9280Modes_original_rxgain_9280_2,
641 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
642 }
643 }
644
645 static void
ath9k_hw_init_txgain_ini(struct ath_hal * ah)646 ath9k_hw_init_txgain_ini(struct ath_hal *ah)
647 {
648 uint32_t txgain_type;
649 struct ath_hal_5416 *ahp = AH5416(ah);
650
651 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
652 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
653
654 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
655 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
656 ar9280Modes_high_power_tx_gain_9280_2,
657 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2),
658 6);
659 } else {
660 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
661 ar9280Modes_original_tx_gain_9280_2,
662 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
663 }
664 } else {
665 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
666 ar9280Modes_original_tx_gain_9280_2,
667 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
668 }
669 }
670
671 static int
ath9k_hw_post_attach(struct ath_hal * ah)672 ath9k_hw_post_attach(struct ath_hal *ah)
673 {
674 int ecode;
675
676 if (!ath9k_hw_chip_test(ah)) {
677 ARN_DBG((ARN_DBG_REG_IO, "arn: ath9k_hw_post_attach(): "
678 "hardware self-test failed\n"));
679
680 }
681
682 ecode = ath9k_hw_rf_claim(ah);
683 if (ecode != 0)
684 return (ecode);
685
686 ecode = ath9k_hw_eeprom_attach(ah);
687 if (ecode != 0)
688 return (ecode);
689 ecode = ath9k_hw_rfattach(ah);
690 if (ecode != 0)
691 return (ecode);
692
693 if (!AR_SREV_9100(ah)) {
694 ath9k_hw_ani_setup(ah);
695 ath9k_hw_ani_attach(ah);
696 }
697
698 return (0);
699 }
700
701 static struct ath_hal *
ath9k_hw_do_attach(uint16_t device_id,struct arn_softc * sc,caddr_t mem,int * status)702 ath9k_hw_do_attach(uint16_t device_id, struct arn_softc *sc,
703 caddr_t mem, int *status)
704 {
705 struct ath_hal_5416 *ahp;
706 struct ath_hal *ah;
707 int ecode;
708 uint32_t i;
709 uint32_t j;
710
711 ahp = ath9k_hw_newstate(device_id, sc, mem, status);
712 if (ahp == NULL)
713 return (NULL);
714
715 ah = &ahp->ah;
716
717 ath9k_hw_set_defaults(ah);
718
719 if (ah->ah_config.intr_mitigation != 0)
720 ahp->ah_intrMitigation = B_TRUE;
721
722 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
723 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_reset_reg(): "
724 "couldn't reset chip \n"));
725 ecode = EIO;
726 goto bad;
727 }
728
729 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
730 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_setpower(): "
731 "couldn't wakeup chip \n"));
732 ecode = EIO;
733 goto bad;
734 }
735
736 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
737 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI ||
738 (AR_SREV_9280(ah) && !ah->ah_isPciExpress)) {
739 ah->ah_config.serialize_regmode =
740 SER_REG_MODE_ON;
741 } else {
742 ah->ah_config.serialize_regmode =
743 SER_REG_MODE_OFF;
744 }
745 }
746 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): "
747 "serialize_regmode is %d\n",
748 ah->ah_config.serialize_regmode));
749
750 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
751 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
752 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
753 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) &&
754 (!AR_SREV_9285(ah))) {
755 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): "
756 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
757 ah->ah_macVersion, ah->ah_macRev));
758 ecode = ENOTSUP;
759 goto bad;
760 }
761
762 if (AR_SREV_9100(ah)) {
763 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
764 ahp->ah_suppCals = IQ_MISMATCH_CAL;
765 ah->ah_isPciExpress = B_FALSE;
766 }
767 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
768
769 if (AR_SREV_9160_10_OR_LATER(ah)) {
770 if (AR_SREV_9280_10_OR_LATER(ah)) {
771 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
772 ahp->ah_adcGainCalData.calData =
773 &adc_gain_cal_single_sample;
774 ahp->ah_adcDcCalData.calData =
775 &adc_dc_cal_single_sample;
776 ahp->ah_adcDcCalInitData.calData =
777 &adc_init_dc_cal;
778 } else {
779 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
780 ahp->ah_adcGainCalData.calData =
781 &adc_gain_cal_multi_sample;
782 ahp->ah_adcDcCalData.calData =
783 &adc_dc_cal_multi_sample;
784 ahp->ah_adcDcCalInitData.calData =
785 &adc_init_dc_cal;
786 }
787 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
788 }
789
790 if (AR_SREV_9160(ah)) {
791 ah->ah_config.enable_ani = 1;
792 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
793 ATH9K_ANI_FIRSTEP_LEVEL);
794 } else {
795 ahp->ah_ani_function = ATH9K_ANI_ALL;
796 if (AR_SREV_9280_10_OR_LATER(ah)) {
797 ahp->ah_ani_function &=
798 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
799 }
800 }
801 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): "
802 "This Mac Chip Rev 0x%02x.%x is \n",
803 ah->ah_macVersion, ah->ah_macRev));
804
805 if (AR_SREV_9285_12_OR_LATER(ah)) {
806 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
807 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
808
809 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
810 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
811
812 if (ah->ah_config.pcie_clock_req) {
813 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
814 ar9285PciePhy_clkreq_off_L1_9285_1_2,
815 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2),
816 2);
817 } else {
818 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
819 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
820 ARRAY_SIZE
821 (ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 2);
822 }
823 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
824 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
825 ARRAY_SIZE(ar9285Modes_9285), 6);
826
827 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
828 ARRAY_SIZE(ar9285Common_9285), 2);
829
830 if (ah->ah_config.pcie_clock_req) {
831
832 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
833 ar9285PciePhy_clkreq_off_L1_9285,
834 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
835 } else {
836 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
837 ar9285PciePhy_clkreq_always_on_L1_9285,
838 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285),
839 2);
840 }
841 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
842 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
843 ARRAY_SIZE(ar9280Modes_9280_2), 6);
844
845 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
846 ARRAY_SIZE(ar9280Common_9280_2), 2);
847
848 if (ah->ah_config.pcie_clock_req) {
849 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
850 ar9280PciePhy_clkreq_off_L1_9280,
851 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
852 } else {
853 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
854 ar9280PciePhy_clkreq_always_on_L1_9280,
855 ARRAY_SIZE
856 (ar9280PciePhy_clkreq_always_on_L1_9280), 2);
857 }
858
859 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
860 ar9280Modes_fast_clock_9280_2,
861 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
862 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
863
864 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
865 ARRAY_SIZE(ar9280Modes_9280), 6);
866
867 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
868 ARRAY_SIZE(ar9280Common_9280), 2);
869 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
870 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
871 ARRAY_SIZE(ar5416Modes_9160), 6);
872
873 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
874 ARRAY_SIZE(ar5416Common_9160), 2);
875
876 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
877 ARRAY_SIZE(ar5416Bank0_9160), 2);
878
879 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
880 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
881
882 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
883 ARRAY_SIZE(ar5416Bank1_9160), 2);
884
885 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
886 ARRAY_SIZE(ar5416Bank2_9160), 2);
887
888 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
889 ARRAY_SIZE(ar5416Bank3_9160), 3);
890
891 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
892 ARRAY_SIZE(ar5416Bank6_9160), 3);
893
894 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
895 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
896
897 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
898 ARRAY_SIZE(ar5416Bank7_9160), 2);
899 if (AR_SREV_9160_11(ah)) {
900 INIT_INI_ARRAY(&ahp->ah_iniAddac,
901 ar5416Addac_91601_1,
902 ARRAY_SIZE(ar5416Addac_91601_1), 2);
903 } else {
904 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
905 ARRAY_SIZE(ar5416Addac_9160), 2);
906 }
907 } else if (AR_SREV_9100_OR_LATER(ah)) {
908 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
909 ARRAY_SIZE(ar5416Modes_9100), 6);
910
911 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
912 ARRAY_SIZE(ar5416Common_9100), 2);
913
914 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
915 ARRAY_SIZE(ar5416Bank0_9100), 2);
916
917 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
918 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
919
920 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
921 ARRAY_SIZE(ar5416Bank1_9100), 2);
922
923 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
924 ARRAY_SIZE(ar5416Bank2_9100), 2);
925
926 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
927 ARRAY_SIZE(ar5416Bank3_9100), 3);
928
929 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
930 ARRAY_SIZE(ar5416Bank6_9100), 3);
931
932 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
933 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
934
935 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
936 ARRAY_SIZE(ar5416Bank7_9100), 2);
937
938 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
939 ARRAY_SIZE(ar5416Addac_9100), 2);
940 } else {
941 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
942 ARRAY_SIZE(ar5416Modes), 6);
943
944 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
945 ARRAY_SIZE(ar5416Common), 2);
946
947 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
948 ARRAY_SIZE(ar5416Bank0), 2);
949
950 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
951 ARRAY_SIZE(ar5416BB_RfGain), 3);
952
953 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
954 ARRAY_SIZE(ar5416Bank1), 2);
955
956 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
957 ARRAY_SIZE(ar5416Bank2), 2);
958
959 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
960 ARRAY_SIZE(ar5416Bank3), 3);
961
962 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
963 ARRAY_SIZE(ar5416Bank6), 3);
964
965 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
966 ARRAY_SIZE(ar5416Bank6TPC), 3);
967
968 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
969 ARRAY_SIZE(ar5416Bank7), 2);
970
971 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
972 ARRAY_SIZE(ar5416Addac), 2);
973 }
974
975 if (ah->ah_isPciExpress)
976 ath9k_hw_configpcipowersave(ah, 0);
977 else
978 ath9k_hw_disablepcie(ah);
979
980 ecode = ath9k_hw_post_attach(ah);
981 if (ecode != 0)
982 goto bad;
983
984 /* rxgain table */
985 if (AR_SREV_9280_20(ah))
986 ath9k_hw_init_rxgain_ini(ah);
987
988 /* txgain table */
989 if (AR_SREV_9280_20(ah))
990 ath9k_hw_init_txgain_ini(ah);
991
992 if (ah->ah_devid == AR9280_DEVID_PCI) {
993 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
994 uint32_t reg =
995 INI_RA(&ahp->ah_iniModes, i, 0);
996
997 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
998 uint32_t val
999 = INI_RA(&ahp->ah_iniModes, i, j);
1000
1001 INI_RA(&ahp->ah_iniModes, i, j) =
1002 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom.def,
1003 reg, val);
1004 }
1005 }
1006 }
1007
1008 if (!ath9k_hw_fill_cap_info(ah)) {
1009 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_do_attach(): "
1010 "failed ath9k_hw_fill_cap_info\n"));
1011 goto bad;
1012 }
1013
1014 ecode = ath9k_hw_init_macaddr(ah);
1015 if (ecode != 0) {
1016 ARN_DBG((ARN_DBG_HW, "arn: "
1017 "%s: failed initializing mac address\n",
1018 __func__));
1019 goto bad;
1020 }
1021
1022 if (AR_SREV_9285(ah))
1023 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
1024 else
1025 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
1026
1027 ath9k_init_nfcal_hist_buffer(ah);
1028
1029 return (ah);
1030 bad:
1031 if (ahp)
1032 ath9k_hw_detach((struct ath_hal *)ahp);
1033 if (status)
1034 *status = ecode;
1035
1036 return (NULL);
1037 }
1038
1039 static void
ath9k_hw_init_bb(struct ath_hal * ah,struct ath9k_channel * chan)1040 ath9k_hw_init_bb(struct ath_hal *ah, struct ath9k_channel *chan)
1041 {
1042 uint32_t synthDelay;
1043
1044 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1045 if (IS_CHAN_B(chan))
1046 synthDelay = (4 * synthDelay) / 22;
1047 else
1048 synthDelay /= 10;
1049
1050 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1051
1052 drv_usecwait(synthDelay + BASE_ACTIVATE_DELAY);
1053 }
1054
1055 static void
ath9k_hw_init_qos(struct ath_hal * ah)1056 ath9k_hw_init_qos(struct ath_hal *ah)
1057 {
1058 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1059 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1060
1061 REG_WRITE(ah, AR_QOS_NO_ACK,
1062 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1063 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1064 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1065
1066 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1067 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1068 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1069 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1070 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1071 }
1072
1073 static void
ath9k_hw_init_pll(struct ath_hal * ah,struct ath9k_channel * chan)1074 ath9k_hw_init_pll(struct ath_hal *ah, struct ath9k_channel *chan)
1075 {
1076 uint32_t pll;
1077
1078 if (AR_SREV_9100(ah)) {
1079 if (chan && IS_CHAN_5GHZ(chan))
1080 pll = 0x1450;
1081 else
1082 pll = 0x1458;
1083 } else {
1084 if (AR_SREV_9280_10_OR_LATER(ah)) {
1085 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1086
1087 if (chan && IS_CHAN_HALF_RATE(chan))
1088 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1089 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1090 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1091
1092 if (chan && IS_CHAN_5GHZ(chan)) {
1093 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1094
1095
1096 if (AR_SREV_9280_20(ah)) {
1097 if (((chan->channel % 20) == 0) ||
1098 ((chan->channel % 10) == 0))
1099 pll = 0x2850;
1100 else
1101 pll = 0x142c;
1102 }
1103 } else {
1104 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1105 }
1106
1107 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1108
1109 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1110
1111 if (chan && IS_CHAN_HALF_RATE(chan))
1112 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1113 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1114 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1115
1116 if (chan && IS_CHAN_5GHZ(chan))
1117 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1118 else
1119 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1120 } else {
1121 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1122
1123 if (chan && IS_CHAN_HALF_RATE(chan))
1124 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1125 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1126 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1127
1128 if (chan && IS_CHAN_5GHZ(chan))
1129 pll |= SM(0xa, AR_RTC_PLL_DIV);
1130 else
1131 pll |= SM(0xb, AR_RTC_PLL_DIV);
1132 }
1133 }
1134 REG_WRITE(ah, (uint16_t)(AR_RTC_PLL_CONTROL), pll);
1135
1136 drv_usecwait(RTC_PLL_SETTLE_DELAY);
1137
1138 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1139 }
1140
1141 static void
ath9k_hw_init_chain_masks(struct ath_hal * ah)1142 ath9k_hw_init_chain_masks(struct ath_hal *ah)
1143 {
1144 struct ath_hal_5416 *ahp = AH5416(ah);
1145 int rx_chainmask, tx_chainmask;
1146
1147 rx_chainmask = ahp->ah_rxchainmask;
1148 tx_chainmask = ahp->ah_txchainmask;
1149
1150 switch (rx_chainmask) {
1151 case 0x5:
1152 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1153 AR_PHY_SWAP_ALT_CHAIN);
1154 /*FALLTHRU*/
1155 case 0x3:
1156 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1157 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1158 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1159 break;
1160 }
1161 /*FALLTHRU*/
1162 case 0x1:
1163 case 0x2:
1164 case 0x7:
1165 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1166 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1167 break;
1168 default:
1169 break;
1170 }
1171
1172 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1173 if (tx_chainmask == 0x5) {
1174 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1175 AR_PHY_SWAP_ALT_CHAIN);
1176 }
1177 if (AR_SREV_9100(ah))
1178 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1179 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1180 }
1181
1182 static void
ath9k_hw_init_interrupt_masks(struct ath_hal * ah,enum ath9k_opmode opmode)1183 ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
1184 {
1185 struct ath_hal_5416 *ahp = AH5416(ah);
1186
1187 ahp->ah_maskReg = AR_IMR_TXERR |
1188 AR_IMR_TXURN |
1189 AR_IMR_RXERR |
1190 AR_IMR_RXORN |
1191 AR_IMR_BCNMISC;
1192
1193 if (ahp->ah_intrMitigation)
1194 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1195 else
1196 ahp->ah_maskReg |= AR_IMR_RXOK;
1197
1198 ahp->ah_maskReg |= AR_IMR_TXOK;
1199
1200 if (opmode == ATH9K_M_HOSTAP)
1201 ahp->ah_maskReg |= AR_IMR_MIB;
1202
1203 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1204 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1205
1206 if (!AR_SREV_9100(ah)) {
1207 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1209 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1210 }
1211 }
1212
1213 static boolean_t
ath9k_hw_set_ack_timeout(struct ath_hal * ah,uint32_t us)1214 ath9k_hw_set_ack_timeout(struct ath_hal *ah, uint32_t us)
1215 {
1216 struct ath_hal_5416 *ahp = AH5416(ah);
1217
1218 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1219 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_ack_timeout(): "
1220 "bad ack timeout %u\n", us));
1221
1222 ahp->ah_acktimeout = (uint32_t)-1;
1223 return (B_FALSE);
1224 } else {
1225 REG_RMW_FIELD(ah, AR_TIME_OUT,
1226 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1227 ahp->ah_acktimeout = us;
1228 return (B_TRUE);
1229 }
1230 }
1231
1232 static boolean_t
ath9k_hw_set_cts_timeout(struct ath_hal * ah,uint32_t us)1233 ath9k_hw_set_cts_timeout(struct ath_hal *ah, uint32_t us)
1234 {
1235 struct ath_hal_5416 *ahp = AH5416(ah);
1236
1237 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1238 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_cts_timeout(): "
1239 "bad cts timeout %u\n", us));
1240
1241 ahp->ah_ctstimeout = (uint32_t)-1;
1242 return (B_FALSE);
1243 } else {
1244 REG_RMW_FIELD(ah, AR_TIME_OUT,
1245 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1246 ahp->ah_ctstimeout = us;
1247 return (B_TRUE);
1248 }
1249 }
1250
1251 static boolean_t
ath9k_hw_set_global_txtimeout(struct ath_hal * ah,uint32_t tu)1252 ath9k_hw_set_global_txtimeout(struct ath_hal *ah, uint32_t tu)
1253 {
1254 struct ath_hal_5416 *ahp = AH5416(ah);
1255
1256 if (tu > 0xFFFF) {
1257 ARN_DBG((ARN_DBG_XMIT,
1258 "arn: ath9k_hw_set_global_txtimeout(): "
1259 "ath9k_hw_set_global_txtimeout\n", tu));
1260
1261 ahp->ah_globaltxtimeout = (uint32_t)-1;
1262 return (B_FALSE);
1263 } else {
1264 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1265 ahp->ah_globaltxtimeout = tu;
1266 return (B_TRUE);
1267 }
1268 }
1269
1270 static void
ath9k_hw_init_user_settings(struct ath_hal * ah)1271 ath9k_hw_init_user_settings(struct ath_hal *ah)
1272 {
1273 struct ath_hal_5416 *ahp = AH5416(ah);
1274
1275 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_init_user_settings(): "
1276 "--AP ahp->ah_miscMode 0x%x\n", ahp->ah_miscMode));
1277
1278 if (ahp->ah_miscMode != 0)
1279 REG_WRITE(ah, AR_PCU_MISC,
1280 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1281 if (ahp->ah_slottime != (uint32_t)-1)
1282 (void) ath9k_hw_setslottime(ah, ahp->ah_slottime);
1283 if (ahp->ah_acktimeout != (uint32_t)-1)
1284 (void) ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1285 if (ahp->ah_ctstimeout != (uint32_t)-1)
1286 (void) ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1287 if (ahp->ah_globaltxtimeout != (uint32_t)-1)
1288 (void) ath9k_hw_set_global_txtimeout
1289 (ah, ahp->ah_globaltxtimeout);
1290 }
1291
1292 const char *
ath9k_hw_probe(uint16_t vendorid,uint16_t devid)1293 ath9k_hw_probe(uint16_t vendorid, uint16_t devid)
1294 {
1295 return (vendorid == ATHEROS_VENDOR_ID ?
1296 ath9k_hw_devname(devid) : NULL);
1297 }
1298
1299 void
ath9k_hw_detach(struct ath_hal * ah)1300 ath9k_hw_detach(struct ath_hal *ah)
1301 {
1302 if (!AR_SREV_9100(ah))
1303 ath9k_hw_ani_detach(ah);
1304
1305 ath9k_hw_rfdetach(ah);
1306 (void) ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1307 kmem_free(ah, sizeof (struct ath_hal_5416)); /* ???? */
1308 }
1309
1310 struct ath_hal *
ath9k_hw_attach(uint16_t device_id,struct arn_softc * sc,caddr_t mem,int * error)1311 ath9k_hw_attach(uint16_t device_id, struct arn_softc *sc,
1312 caddr_t mem, int *error)
1313 {
1314 struct ath_hal *ah = NULL;
1315
1316 switch (device_id) {
1317 case AR5416_DEVID_PCI:
1318 case AR5416_DEVID_PCIE:
1319 case AR9160_DEVID_PCI:
1320 case AR9280_DEVID_PCI:
1321 case AR9280_DEVID_PCIE:
1322 case AR9285_DEVID_PCIE:
1323 ah = ath9k_hw_do_attach(device_id, sc, mem, error);
1324 break;
1325 default:
1326 *error = ENXIO;
1327 break;
1328 }
1329
1330 return (ah);
1331 }
1332
1333 /* INI */
1334
1335 /* ARGSUSED */
1336 static void
ath9k_hw_override_ini(struct ath_hal * ah,struct ath9k_channel * chan)1337 ath9k_hw_override_ini(struct ath_hal *ah, struct ath9k_channel *chan)
1338 {
1339 /*
1340 * Set the RX_ABORT and RX_DIS and clear if off only after
1341 * RXE is set for MAC. This prevents frames with corrupted
1342 * descriptor status.
1343 */
1344 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1345
1346 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1347 AR_SREV_9280_10_OR_LATER(ah))
1348 return;
1349
1350 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1351 }
1352
1353 static uint32_t
ath9k_hw_def_ini_fixup(struct ath_hal * ah,struct ar5416_eeprom_def * pEepData,uint32_t reg,uint32_t value)1354 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1355 struct ar5416_eeprom_def *pEepData,
1356 uint32_t reg, uint32_t value)
1357 {
1358 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1359
1360 switch (ah->ah_devid) {
1361 case AR9280_DEVID_PCI:
1362 if (reg == 0x7894) {
1363 ARN_DBG((ARN_DBG_ANY,
1364 "arn: ath9k_hw_ini_fixup(): "
1365 "ini VAL: %x EEPROM: %x\n",
1366 value, (pBase->version & 0xff)));
1367
1368 if ((pBase->version & 0xff) > 0x0a) {
1369 ARN_DBG((ARN_DBG_ANY,
1370 "arn: ath9k_hw_ini_fixup(): "
1371 "PWDCLKIND: %d\n",
1372 pBase->pwdclkind));
1373
1374 value &= ~AR_AN_TOP2_PWDCLKIND;
1375 value |= AR_AN_TOP2_PWDCLKIND &
1376 (pBase->pwdclkind <<
1377 AR_AN_TOP2_PWDCLKIND_S);
1378 } else {
1379 ARN_DBG((ARN_DBG_ANY,
1380 "arn: ath9k_hw_ini_fixup(): "
1381 "PWDCLKIND Earlier Rev\n"));
1382 }
1383
1384 ARN_DBG((ARN_DBG_ANY,
1385 "arn: ath9k_hw_ini_fixup(): "
1386 "final ini VAL: %x\n\n", value));
1387 }
1388 break;
1389 }
1390
1391 return (value);
1392 }
1393
1394 static uint32_t
ath9k_hw_ini_fixup(struct ath_hal * ah,struct ar5416_eeprom_def * pEepData,uint32_t reg,uint32_t value)1395 ath9k_hw_ini_fixup(struct ath_hal *ah, struct ar5416_eeprom_def *pEepData,
1396 uint32_t reg, uint32_t value)
1397 {
1398 struct ath_hal_5416 *ahp = AH5416(ah);
1399
1400 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1401 return (value);
1402 else
1403 return (ath9k_hw_def_ini_fixup(ah, pEepData, reg, value));
1404 }
1405
1406 static int
ath9k_hw_process_ini(struct ath_hal * ah,struct ath9k_channel * chan,enum ath9k_ht_macmode macmode)1407 ath9k_hw_process_ini(struct ath_hal *ah,
1408 struct ath9k_channel *chan,
1409 enum ath9k_ht_macmode macmode)
1410 {
1411 int i, regWrites = 0;
1412 struct ath_hal_5416 *ahp = AH5416(ah);
1413 uint32_t modesIndex, freqIndex;
1414 int status;
1415
1416 switch (chan->chanmode) {
1417 case CHANNEL_A:
1418 case CHANNEL_A_HT20:
1419 modesIndex = 1;
1420 freqIndex = 1;
1421 break;
1422 case CHANNEL_A_HT40PLUS:
1423 case CHANNEL_A_HT40MINUS:
1424 modesIndex = 2;
1425 freqIndex = 1;
1426 break;
1427 case CHANNEL_G:
1428 case CHANNEL_G_HT20:
1429 case CHANNEL_B:
1430 modesIndex = 4;
1431 freqIndex = 2;
1432 break;
1433 case CHANNEL_G_HT40PLUS:
1434 case CHANNEL_G_HT40MINUS:
1435 modesIndex = 3;
1436 freqIndex = 2;
1437 break;
1438
1439 default:
1440 ARN_DBG((ARN_DBG_CHANNEL, "arn: "
1441 "%s: err: unknow chan->chanmode\n", __func__));
1442 return (EINVAL);
1443 }
1444
1445 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1446
1447 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1448
1449 ath9k_hw_set_addac(ah, chan);
1450
1451 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1452 /* LINTED: E_CONSTANT_CONDITION */
1453 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1454 } else {
1455 struct ar5416IniArray temp;
1456 uint32_t addacSize =
1457 sizeof (uint32_t) * ahp->ah_iniAddac.ia_rows *
1458 ahp->ah_iniAddac.ia_columns;
1459
1460 (void) memcpy(ahp->ah_addac5416_21,
1461 ahp->ah_iniAddac.ia_array, addacSize);
1462
1463 (ahp->ah_addac5416_21)
1464 [31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1465
1466 temp.ia_array = ahp->ah_addac5416_21;
1467 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1468 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1469 /* LINTED: E_CONSTANT_CONDITION */
1470 REG_WRITE_ARRAY(&temp, 1, regWrites);
1471 }
1472
1473 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1474
1475 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1476 uint32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
1477 uint32_t val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1478
1479 REG_WRITE(ah, reg, val);
1480
1481 if (reg >= 0x7800 && reg < 0x78a0 &&
1482 ah->ah_config.analog_shiftreg) {
1483 drv_usecwait(100);
1484 }
1485
1486 /* LINTED: E_CONSTANT_CONDITION */
1487 DO_DELAY(regWrites);
1488 }
1489
1490 if (AR_SREV_9280(ah)) {
1491 /* LINTED: E_CONSTANT_CONDITION */
1492 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex,
1493 regWrites);
1494 }
1495
1496 if (AR_SREV_9280(ah)) {
1497 /* LINTED: E_CONSTANT_CONDITION */
1498 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex,
1499 regWrites);
1500 }
1501
1502 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1503 uint32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1504 uint32_t val = INI_RA(&ahp->ah_iniCommon, i, 1);
1505
1506 REG_WRITE(ah, reg, val);
1507
1508 if (reg >= 0x7800 && reg < 0x78a0 &&
1509 ah->ah_config.analog_shiftreg) {
1510 drv_usecwait(100);
1511 }
1512
1513 /* LINTED: E_CONSTANT_CONDITION */
1514 DO_DELAY(regWrites);
1515 }
1516
1517 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1518
1519 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1520 /* LINTED: E_CONSTANT_CONDITION */
1521 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1522 regWrites);
1523 }
1524
1525 ath9k_hw_override_ini(ah, chan);
1526 ath9k_hw_set_regs(ah, chan, macmode);
1527 ath9k_hw_init_chain_masks(ah);
1528
1529 status = ath9k_hw_set_txpower(ah, chan,
1530 ath9k_regd_get_ctl(ah, chan),
1531 ath9k_regd_get_antenna_allowed(ah, chan),
1532 chan->maxRegTxPower * 2,
1533 min((uint32_t)MAX_RATE_POWER,
1534 (uint32_t)ah->ah_powerLimit));
1535 if (status != 0) {
1536 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_process_ini(): "
1537 "%s: error init'ing transmit power\n", __func__));
1538
1539 return (EIO);
1540 }
1541
1542 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1543 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_process_ini(): "
1544 "%s: ar5416SetRfRegs failed\n", __func__));
1545
1546 return (EIO);
1547 }
1548
1549 return (0);
1550 }
1551
1552 /* Reset and Channel Switching Routines */
1553
1554 static void
ath9k_hw_set_rfmode(struct ath_hal * ah,struct ath9k_channel * chan)1555 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1556 {
1557 uint32_t rfMode = 0;
1558
1559 if (chan == NULL)
1560 return;
1561
1562 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1563 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1564
1565 if (!AR_SREV_9280_10_OR_LATER(ah))
1566 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1567 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1568
1569 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1570 rfMode |= (AR_PHY_MODE_DYNAMIC |
1571 AR_PHY_MODE_DYN_CCK_DISABLE);
1572
1573 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1574 }
1575
1576 static void
ath9k_hw_mark_phy_inactive(struct ath_hal * ah)1577 ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1578 {
1579 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1580 }
1581
1582 static inline void
ath9k_hw_set_dma(struct ath_hal * ah)1583 ath9k_hw_set_dma(struct ath_hal *ah)
1584 {
1585 uint32_t regval;
1586
1587 regval = REG_READ(ah, AR_AHB_MODE);
1588 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1589
1590 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1591 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1592
1593 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1594
1595 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1596 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1597
1598 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1599
1600 if (AR_SREV_9285(ah)) {
1601 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1602 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1603 } else {
1604 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1605 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1606 }
1607 }
1608
1609 static void
ath9k_hw_set_operating_mode(struct ath_hal * ah,int opmode)1610 ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1611 {
1612 uint32_t val;
1613
1614 val = REG_READ(ah, AR_STA_ID1);
1615 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1616 switch (opmode) {
1617 case ATH9K_M_HOSTAP:
1618 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
1619 AR_STA_ID1_KSRCH_MODE);
1620 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1621 break;
1622 case ATH9K_M_IBSS:
1623 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
1624 AR_STA_ID1_KSRCH_MODE);
1625 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1626 break;
1627 case ATH9K_M_STA:
1628 case ATH9K_M_MONITOR:
1629 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1630 break;
1631 }
1632 }
1633
1634 /* ARGSUSED */
1635 static inline void
ath9k_hw_get_delta_slope_vals(struct ath_hal * ah,uint32_t coef_scaled,uint32_t * coef_mantissa,uint32_t * coef_exponent)1636 ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1637 uint32_t coef_scaled,
1638 uint32_t *coef_mantissa,
1639 uint32_t *coef_exponent)
1640 {
1641 uint32_t coef_exp, coef_man;
1642
1643 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1644 if ((coef_scaled >> coef_exp) & 0x1)
1645 break;
1646
1647 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1648
1649 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1650
1651 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1652 *coef_exponent = coef_exp - 16;
1653 }
1654
1655 static void
ath9k_hw_set_delta_slope(struct ath_hal * ah,struct ath9k_channel * chan)1656 ath9k_hw_set_delta_slope(struct ath_hal *ah,
1657 struct ath9k_channel *chan)
1658 {
1659 uint32_t coef_scaled, ds_coef_exp, ds_coef_man;
1660 uint32_t clockMhzScaled = 0x64000000;
1661 struct chan_centers centers;
1662
1663 if (IS_CHAN_HALF_RATE(chan))
1664 clockMhzScaled = clockMhzScaled >> 1;
1665 else if (IS_CHAN_QUARTER_RATE(chan))
1666 clockMhzScaled = clockMhzScaled >> 2;
1667
1668 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1669 coef_scaled = clockMhzScaled / centers.synth_center;
1670
1671 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1672 &ds_coef_exp);
1673
1674 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1675 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1676 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1677 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1678
1679 coef_scaled = (9 * coef_scaled) / 10;
1680
1681 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1682 &ds_coef_exp);
1683
1684 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1685 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1686 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1687 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1688 }
1689
1690 static boolean_t
ath9k_hw_set_reset(struct ath_hal * ah,int type)1691 ath9k_hw_set_reset(struct ath_hal *ah, int type)
1692 {
1693 uint32_t rst_flags;
1694 uint32_t tmpReg;
1695
1696 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1697 AR_RTC_FORCE_WAKE_ON_INT);
1698
1699 if (AR_SREV_9100(ah)) {
1700 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1701 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1702 } else {
1703 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1704 if (tmpReg &
1705 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1706 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1707 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1708 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1709 } else {
1710 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1711 }
1712
1713 rst_flags = AR_RTC_RC_MAC_WARM;
1714 if (type == ATH9K_RESET_COLD)
1715 rst_flags |= AR_RTC_RC_MAC_COLD;
1716 }
1717
1718 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), rst_flags);
1719 drv_usecwait(50);
1720
1721 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), 0);
1722 if (!ath9k_hw_wait(ah, (uint16_t)(AR_RTC_RC), AR_RTC_RC_M, 0)) {
1723 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_set_reset(): "
1724 "RTC stuck in MAC reset\n"));
1725
1726 return (B_FALSE);
1727 }
1728
1729 if (!AR_SREV_9100(ah))
1730 REG_WRITE(ah, AR_RC, 0);
1731
1732 ath9k_hw_init_pll(ah, NULL);
1733
1734 if (AR_SREV_9100(ah))
1735 drv_usecwait(50);
1736
1737 return (B_TRUE);
1738 }
1739
1740 static boolean_t
ath9k_hw_set_reset_power_on(struct ath_hal * ah)1741 ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1742 {
1743 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1744 AR_RTC_FORCE_WAKE_ON_INT);
1745
1746 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 0);
1747 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 1);
1748
1749 if (!ath9k_hw_wait(ah,
1750 AR_RTC_STATUS,
1751 AR_RTC_STATUS_M,
1752 AR_RTC_STATUS_ON)) {
1753 ARN_DBG((ARN_DBG_HW,
1754 "arn: ath9k_hw_set_reset_power_on(): "
1755 "RTC not waking up \n"));
1756
1757 return (B_FALSE);
1758 }
1759
1760 ath9k_hw_read_revisions(ah);
1761
1762 return (ath9k_hw_set_reset(ah, ATH9K_RESET_WARM));
1763 }
1764
1765 static boolean_t
ath9k_hw_set_reset_reg(struct ath_hal * ah,uint32_t type)1766 ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type)
1767 {
1768 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1769 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1770
1771 switch (type) {
1772 case ATH9K_RESET_POWER_ON:
1773 return (ath9k_hw_set_reset_power_on(ah));
1774 case ATH9K_RESET_WARM:
1775 case ATH9K_RESET_COLD:
1776 return (ath9k_hw_set_reset(ah, type));
1777 default:
1778 return (B_FALSE);
1779 }
1780 }
1781
1782 static void
ath9k_hw_set_regs(struct ath_hal * ah,struct ath9k_channel * chan,enum ath9k_ht_macmode macmode)1783 ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1784 enum ath9k_ht_macmode macmode)
1785 {
1786 uint32_t phymode;
1787 uint32_t enableDacFifo = 0;
1788 struct ath_hal_5416 *ahp = AH5416(ah);
1789
1790 if (AR_SREV_9285_10_OR_LATER(ah))
1791 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1792 AR_PHY_FC_ENABLE_DAC_FIFO);
1793
1794 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
1795 AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1796
1797 if (IS_CHAN_HT40(chan)) {
1798 phymode |= AR_PHY_FC_DYN2040_EN;
1799
1800 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1801 (chan->chanmode == CHANNEL_G_HT40PLUS))
1802 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1803
1804 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1805 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1806 }
1807 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1808
1809 ath9k_hw_set11nmac2040(ah, macmode);
1810
1811 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1812 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1813 }
1814
1815 static boolean_t
ath9k_hw_chip_reset(struct ath_hal * ah,struct ath9k_channel * chan)1816 ath9k_hw_chip_reset(struct ath_hal *ah,
1817 struct ath9k_channel *chan)
1818 {
1819 struct ath_hal_5416 *ahp = AH5416(ah);
1820
1821 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1822 return (B_FALSE);
1823
1824 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1825 return (B_FALSE);
1826
1827 ahp->ah_chipFullSleep = B_FALSE;
1828
1829 ath9k_hw_init_pll(ah, chan);
1830
1831 ath9k_hw_set_rfmode(ah, chan);
1832
1833 return (B_TRUE);
1834 }
1835
1836 static struct ath9k_channel *
ath9k_hw_check_chan(struct ath_hal * ah,struct ath9k_channel * chan)1837 ath9k_hw_check_chan(struct ath_hal *ah, struct ath9k_channel *chan)
1838 {
1839 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1840 ARN_DBG((ARN_DBG_CHANNEL, "arn: "
1841 "%s: invalid channel %u/0x%x; not marked as "
1842 "2GHz or 5GHz\n",
1843 __func__, chan->channel, chan->channelFlags));
1844 return (NULL);
1845 }
1846
1847 if (!IS_CHAN_OFDM(chan) &&
1848 !IS_CHAN_B(chan) &&
1849 !IS_CHAN_HT20(chan) &&
1850 !IS_CHAN_HT40(chan)) {
1851 ARN_DBG((ARN_DBG_CHANNEL, "arn: "
1852 "%s: invalid channel %u/0x%x; not marked as "
1853 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1854 __func__, chan->channel, chan->channelFlags));
1855
1856 return (NULL);
1857 }
1858 return (ath9k_regd_check_channel(ah, chan));
1859 }
1860
1861 static boolean_t
ath9k_hw_channel_change(struct ath_hal * ah,struct ath9k_channel * chan,enum ath9k_ht_macmode macmode)1862 ath9k_hw_channel_change(struct ath_hal *ah,
1863 struct ath9k_channel *chan,
1864 enum ath9k_ht_macmode macmode)
1865 {
1866 uint32_t synthDelay, qnum;
1867
1868 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1869 if (ath9k_hw_numtxpending(ah, qnum)) {
1870 ARN_DBG((ARN_DBG_QUEUE, "arn: "
1871 "%s: Transmit frames pending on queue %d\n",
1872 __func__, qnum));
1873
1874 return (B_FALSE);
1875 }
1876 }
1877
1878 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1879 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1880 AR_PHY_RFBUS_GRANT_EN)) {
1881 ARN_DBG((ARN_DBG_HW, "arn: "
1882 "%s: Could not kill baseband RX\n", __func__));
1883
1884 return (B_FALSE);
1885 }
1886
1887 ath9k_hw_set_regs(ah, chan, macmode);
1888
1889 if (AR_SREV_9280_10_OR_LATER(ah)) {
1890 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1891 ARN_DBG((ARN_DBG_CHANNEL, "arn: "
1892 "%s: failed to set channel\n", __func__));
1893 return (B_FALSE);
1894 }
1895 } else {
1896 if (!(ath9k_hw_set_channel(ah, chan))) {
1897 ARN_DBG((ARN_DBG_CHANNEL, "arn: "
1898 "%s: failed to set channel\n", __func__));
1899
1900 return (B_FALSE);
1901 }
1902 }
1903
1904 if (ath9k_hw_set_txpower(ah, chan,
1905 ath9k_regd_get_ctl(ah, chan),
1906 ath9k_regd_get_antenna_allowed(ah, chan),
1907 chan->maxRegTxPower * 2,
1908 min((uint32_t)MAX_RATE_POWER,
1909 (uint32_t)ah->ah_powerLimit)) != 0) {
1910 ARN_DBG((ARN_DBG_EEPROM, "arn: "
1911 "%s: error init'ing transmit power\n", __func__));
1912
1913 return (B_FALSE);
1914 }
1915
1916 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1917 if (IS_CHAN_B(chan))
1918 synthDelay = (4 * synthDelay) / 22;
1919 else
1920 synthDelay /= 10;
1921
1922 drv_usecwait(synthDelay + BASE_ACTIVATE_DELAY);
1923
1924 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1925
1926 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1927 ath9k_hw_set_delta_slope(ah, chan);
1928
1929 if (AR_SREV_9280_10_OR_LATER(ah))
1930 ath9k_hw_9280_spur_mitigate(ah, chan);
1931 else
1932 ath9k_hw_spur_mitigate(ah, chan);
1933
1934 if (!chan->oneTimeCalsDone)
1935 chan->oneTimeCalsDone = B_TRUE;
1936
1937 return (B_TRUE);
1938 }
1939
1940 static void
ath9k_hw_9280_spur_mitigate(struct ath_hal * ah,struct ath9k_channel * chan)1941 ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1942 {
1943 int bb_spur = AR_NO_SPUR;
1944 int freq;
1945 int bin, cur_bin;
1946 int bb_spur_off, spur_subchannel_sd;
1947 int spur_freq_sd;
1948 int spur_delta_phase;
1949 int denominator;
1950 int upper, lower, cur_vit_mask;
1951 int tmp, newVal;
1952 int i;
1953 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1954 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1955 };
1956 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1957 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1958 };
1959 int inc[4] = { 0, 100, 0, 0 };
1960 struct chan_centers centers;
1961
1962 int8_t mask_m[123];
1963 int8_t mask_p[123];
1964 int8_t mask_amt;
1965 int tmp_mask;
1966 int cur_bb_spur;
1967 boolean_t is2GHz = IS_CHAN_2GHZ(chan);
1968
1969 (void) memset(&mask_m, 0, sizeof (int8_t) * 123);
1970 (void) memset(&mask_p, 0, sizeof (int8_t) * 123);
1971
1972 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1973 freq = centers.synth_center;
1974
1975 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1976 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1977 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1978
1979 if (is2GHz)
1980 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1981 else
1982 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1983
1984 if (AR_NO_SPUR == cur_bb_spur)
1985 break;
1986 cur_bb_spur = cur_bb_spur - freq;
1987
1988 if (IS_CHAN_HT40(chan)) {
1989 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1990 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1991 bb_spur = cur_bb_spur;
1992 break;
1993 }
1994 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1995 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1996 bb_spur = cur_bb_spur;
1997 break;
1998 }
1999 }
2000
2001 if (AR_NO_SPUR == bb_spur) {
2002 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
2003 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
2004 return;
2005 } else {
2006 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
2007 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
2008 }
2009
2010 bin = bb_spur * 320;
2011
2012 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2013
2014 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2015 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2016 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2017 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2018 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
2019
2020 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2021 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2022 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2023 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2024 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2025 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
2026
2027 if (IS_CHAN_HT40(chan)) {
2028 if (bb_spur < 0) {
2029 spur_subchannel_sd = 1;
2030 bb_spur_off = bb_spur + 10;
2031 } else {
2032 spur_subchannel_sd = 0;
2033 bb_spur_off = bb_spur - 10;
2034 }
2035 } else {
2036 spur_subchannel_sd = 0;
2037 bb_spur_off = bb_spur;
2038 }
2039
2040 if (IS_CHAN_HT40(chan))
2041 spur_delta_phase =
2042 ((bb_spur * 262144) / 10) &
2043 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2044 else
2045 spur_delta_phase =
2046 ((bb_spur * 524288) / 10) &
2047 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2048
2049 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
2050 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
2051
2052 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2053 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2054 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2055 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2056
2057 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2058 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2059
2060 cur_bin = -6000;
2061 upper = bin + 100;
2062 lower = bin - 100;
2063
2064 for (i = 0; i < 4; i++) {
2065 int pilot_mask = 0;
2066 int chan_mask = 0;
2067 int bp = 0;
2068 for (bp = 0; bp < 30; bp++) {
2069 if ((cur_bin > lower) && (cur_bin < upper)) {
2070 pilot_mask = pilot_mask | 0x1 << bp;
2071 chan_mask = chan_mask | 0x1 << bp;
2072 }
2073 cur_bin += 100;
2074 }
2075 cur_bin += inc[i];
2076 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2077 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2078 }
2079
2080 cur_vit_mask = 6100;
2081 upper = bin + 120;
2082 lower = bin - 120;
2083
2084 for (i = 0; i < 123; i++) {
2085 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2086
2087 /* workaround for gcc bug #37014 */
2088 volatile int tmp = abs(cur_vit_mask - bin);
2089
2090 if (tmp < 75)
2091 mask_amt = 1;
2092 else
2093 mask_amt = 0;
2094 if (cur_vit_mask < 0)
2095 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2096 else
2097 mask_p[cur_vit_mask / 100] = mask_amt;
2098 }
2099 cur_vit_mask -= 100;
2100 }
2101
2102 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) |
2103 (mask_m[48] << 26) | (mask_m[49] << 24) |
2104 (mask_m[50] << 22) | (mask_m[51] << 20) |
2105 (mask_m[52] << 18) | (mask_m[53] << 16) |
2106 (mask_m[54] << 14) | (mask_m[55] << 12) |
2107 (mask_m[56] << 10) | (mask_m[57] << 8) |
2108 (mask_m[58] << 6) | (mask_m[59] << 4) |
2109 (mask_m[60] << 2) | (mask_m[61] << 0);
2110 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2111 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2112
2113 tmp_mask = (mask_m[31] << 28) |
2114 (mask_m[32] << 26) | (mask_m[33] << 24) |
2115 (mask_m[34] << 22) | (mask_m[35] << 20) |
2116 (mask_m[36] << 18) | (mask_m[37] << 16) |
2117 (mask_m[48] << 14) | (mask_m[39] << 12) |
2118 (mask_m[40] << 10) | (mask_m[41] << 8) |
2119 (mask_m[42] << 6) | (mask_m[43] << 4) |
2120 (mask_m[44] << 2) | (mask_m[45] << 0);
2121 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2122 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2123
2124 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) |
2125 (mask_m[18] << 26) | (mask_m[18] << 24) |
2126 (mask_m[20] << 22) | (mask_m[20] << 20) |
2127 (mask_m[22] << 18) | (mask_m[22] << 16) |
2128 (mask_m[24] << 14) | (mask_m[24] << 12) |
2129 (mask_m[25] << 10) | (mask_m[26] << 8) |
2130 (mask_m[27] << 6) | (mask_m[28] << 4) |
2131 (mask_m[29] << 2) | (mask_m[30] << 0);
2132 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2133 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2134
2135 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) |
2136 (mask_m[2] << 26) | (mask_m[3] << 24) |
2137 (mask_m[4] << 22) | (mask_m[5] << 20) |
2138 (mask_m[6] << 18) | (mask_m[7] << 16) |
2139 (mask_m[8] << 14) | (mask_m[9] << 12) |
2140 (mask_m[10] << 10) | (mask_m[11] << 8) |
2141 (mask_m[12] << 6) | (mask_m[13] << 4) |
2142 (mask_m[14] << 2) | (mask_m[15] << 0);
2143 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2144 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2145
2146 tmp_mask = (mask_p[15] << 28) |
2147 (mask_p[14] << 26) | (mask_p[13] << 24) |
2148 (mask_p[12] << 22) | (mask_p[11] << 20) |
2149 (mask_p[10] << 18) | (mask_p[9] << 16) |
2150 (mask_p[8] << 14) | (mask_p[7] << 12) |
2151 (mask_p[6] << 10) | (mask_p[5] << 8) |
2152 (mask_p[4] << 6) | (mask_p[3] << 4) |
2153 (mask_p[2] << 2) | (mask_p[1] << 0);
2154 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2155 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2156
2157 tmp_mask = (mask_p[30] << 28) |
2158 (mask_p[29] << 26) | (mask_p[28] << 24) |
2159 (mask_p[27] << 22) | (mask_p[26] << 20) |
2160 (mask_p[25] << 18) | (mask_p[24] << 16) |
2161 (mask_p[23] << 14) | (mask_p[22] << 12) |
2162 (mask_p[21] << 10) | (mask_p[20] << 8) |
2163 (mask_p[19] << 6) | (mask_p[18] << 4) |
2164 (mask_p[17] << 2) | (mask_p[16] << 0);
2165 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2166 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2167
2168 tmp_mask = (mask_p[45] << 28) |
2169 (mask_p[44] << 26) | (mask_p[43] << 24) |
2170 (mask_p[42] << 22) | (mask_p[41] << 20) |
2171 (mask_p[40] << 18) | (mask_p[39] << 16) |
2172 (mask_p[38] << 14) | (mask_p[37] << 12) |
2173 (mask_p[36] << 10) | (mask_p[35] << 8) |
2174 (mask_p[34] << 6) | (mask_p[33] << 4) |
2175 (mask_p[32] << 2) | (mask_p[31] << 0);
2176 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2177 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2178
2179 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) |
2180 (mask_p[59] << 26) | (mask_p[58] << 24) |
2181 (mask_p[57] << 22) | (mask_p[56] << 20) |
2182 (mask_p[55] << 18) | (mask_p[54] << 16) |
2183 (mask_p[53] << 14) | (mask_p[52] << 12) |
2184 (mask_p[51] << 10) | (mask_p[50] << 8) |
2185 (mask_p[49] << 6) | (mask_p[48] << 4) |
2186 (mask_p[47] << 2) | (mask_p[46] << 0);
2187 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2188 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2189 }
2190
2191 static void
ath9k_hw_spur_mitigate(struct ath_hal * ah,struct ath9k_channel * chan)2192 ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
2193 {
2194 int bb_spur = AR_NO_SPUR;
2195 int bin, cur_bin;
2196 int spur_freq_sd;
2197 int spur_delta_phase;
2198 int denominator;
2199 int upper, lower, cur_vit_mask;
2200 int tmp, new;
2201 int i;
2202 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2203 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2204 };
2205 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2206 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2207 };
2208 int inc[4] = { 0, 100, 0, 0 };
2209
2210 int8_t mask_m[123];
2211 int8_t mask_p[123];
2212 int8_t mask_amt;
2213 int tmp_mask;
2214 int cur_bb_spur;
2215 boolean_t is2GHz = IS_CHAN_2GHZ(chan);
2216
2217 (void) memset(&mask_m, 0, sizeof (int8_t) * 123);
2218 (void) memset(&mask_p, 0, sizeof (int8_t) * 123);
2219
2220 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2221 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2222 if (AR_NO_SPUR == cur_bb_spur)
2223 break;
2224 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2225 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2226 bb_spur = cur_bb_spur;
2227 break;
2228 }
2229 }
2230
2231 if (AR_NO_SPUR == bb_spur)
2232 return;
2233
2234 bin = bb_spur * 32;
2235
2236 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2237 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2238 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2239 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2240 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2241
2242 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2243
2244 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2245 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2246 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2247 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2248 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2249 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2250
2251 spur_delta_phase = ((bb_spur * 524288) / 100) &
2252 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2253
2254 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2255 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2256
2257 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2258 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2259 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2260 REG_WRITE(ah, AR_PHY_TIMING11, new);
2261
2262 cur_bin = -6000;
2263 upper = bin + 100;
2264 lower = bin - 100;
2265
2266 for (i = 0; i < 4; i++) {
2267 int pilot_mask = 0;
2268 int chan_mask = 0;
2269 int bp = 0;
2270 for (bp = 0; bp < 30; bp++) {
2271 if ((cur_bin > lower) && (cur_bin < upper)) {
2272 pilot_mask = pilot_mask | 0x1 << bp;
2273 chan_mask = chan_mask | 0x1 << bp;
2274 }
2275 cur_bin += 100;
2276 }
2277 cur_bin += inc[i];
2278 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2279 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2280 }
2281
2282 cur_vit_mask = 6100;
2283 upper = bin + 120;
2284 lower = bin - 120;
2285
2286 for (i = 0; i < 123; i++) {
2287 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2288
2289 /* workaround for gcc bug #37014 */
2290 volatile int tmp = abs(cur_vit_mask - bin);
2291
2292 if (tmp < 75)
2293 mask_amt = 1;
2294 else
2295 mask_amt = 0;
2296 if (cur_vit_mask < 0)
2297 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2298 else
2299 mask_p[cur_vit_mask / 100] = mask_amt;
2300 }
2301 cur_vit_mask -= 100;
2302 }
2303
2304 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) |
2305 (mask_m[48] << 26) | (mask_m[49] << 24) |
2306 (mask_m[50] << 22) | (mask_m[51] << 20) |
2307 (mask_m[52] << 18) | (mask_m[53] << 16) |
2308 (mask_m[54] << 14) | (mask_m[55] << 12) |
2309 (mask_m[56] << 10) | (mask_m[57] << 8) |
2310 (mask_m[58] << 6) | (mask_m[59] << 4) |
2311 (mask_m[60] << 2) | (mask_m[61] << 0);
2312 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2313 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2314
2315 tmp_mask = (mask_m[31] << 28) |
2316 (mask_m[32] << 26) | (mask_m[33] << 24) |
2317 (mask_m[34] << 22) | (mask_m[35] << 20) |
2318 (mask_m[36] << 18) | (mask_m[37] << 16) |
2319 (mask_m[48] << 14) | (mask_m[39] << 12) |
2320 (mask_m[40] << 10) | (mask_m[41] << 8) |
2321 (mask_m[42] << 6) | (mask_m[43] << 4) |
2322 (mask_m[44] << 2) | (mask_m[45] << 0);
2323 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2324 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2325
2326 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) |
2327 (mask_m[18] << 26) | (mask_m[18] << 24) |
2328 (mask_m[20] << 22) | (mask_m[20] << 20) |
2329 (mask_m[22] << 18) | (mask_m[22] << 16) |
2330 (mask_m[24] << 14) | (mask_m[24] << 12) |
2331 (mask_m[25] << 10) | (mask_m[26] << 8) |
2332 (mask_m[27] << 6) | (mask_m[28] << 4) |
2333 (mask_m[29] << 2) | (mask_m[30] << 0);
2334 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2335 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2336
2337 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) |
2338 (mask_m[2] << 26) | (mask_m[3] << 24) |
2339 (mask_m[4] << 22) | (mask_m[5] << 20) |
2340 (mask_m[6] << 18) | (mask_m[7] << 16) |
2341 (mask_m[8] << 14) | (mask_m[9] << 12) |
2342 (mask_m[10] << 10) | (mask_m[11] << 8) |
2343 (mask_m[12] << 6) | (mask_m[13] << 4) |
2344 (mask_m[14] << 2) | (mask_m[15] << 0);
2345 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2346 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2347
2348 tmp_mask = (mask_p[15] << 28) |
2349 (mask_p[14] << 26) | (mask_p[13] << 24) |
2350 (mask_p[12] << 22) | (mask_p[11] << 20) |
2351 (mask_p[10] << 18) | (mask_p[9] << 16) |
2352 (mask_p[8] << 14) | (mask_p[7] << 12) |
2353 (mask_p[6] << 10) | (mask_p[5] << 8) |
2354 (mask_p[4] << 6) | (mask_p[3] << 4) |
2355 (mask_p[2] << 2) | (mask_p[1] << 0);
2356 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2357 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2358
2359 tmp_mask = (mask_p[30] << 28) |
2360 (mask_p[29] << 26) | (mask_p[28] << 24) |
2361 (mask_p[27] << 22) | (mask_p[26] << 20) |
2362 (mask_p[25] << 18) | (mask_p[24] << 16) |
2363 (mask_p[23] << 14) | (mask_p[22] << 12) |
2364 (mask_p[21] << 10) | (mask_p[20] << 8) |
2365 (mask_p[19] << 6) | (mask_p[18] << 4) |
2366 (mask_p[17] << 2) | (mask_p[16] << 0);
2367 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2368 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2369
2370 tmp_mask = (mask_p[45] << 28) |
2371 (mask_p[44] << 26) | (mask_p[43] << 24) |
2372 (mask_p[42] << 22) | (mask_p[41] << 20) |
2373 (mask_p[40] << 18) | (mask_p[39] << 16) |
2374 (mask_p[38] << 14) | (mask_p[37] << 12) |
2375 (mask_p[36] << 10) | (mask_p[35] << 8) |
2376 (mask_p[34] << 6) | (mask_p[33] << 4) |
2377 (mask_p[32] << 2) | (mask_p[31] << 0);
2378 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2379 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2380
2381 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) |
2382 (mask_p[59] << 26) | (mask_p[58] << 24) |
2383 (mask_p[57] << 22) | (mask_p[56] << 20) |
2384 (mask_p[55] << 18) | (mask_p[54] << 16) |
2385 (mask_p[53] << 14) | (mask_p[52] << 12) |
2386 (mask_p[51] << 10) | (mask_p[50] << 8) |
2387 (mask_p[49] << 6) | (mask_p[48] << 4) |
2388 (mask_p[47] << 2) | (mask_p[46] << 0);
2389 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2390 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2391 }
2392
2393 boolean_t
ath9k_hw_reset(struct ath_hal * ah,struct ath9k_channel * chan,enum ath9k_ht_macmode macmode,uint8_t txchainmask,uint8_t rxchainmask,enum ath9k_ht_extprotspacing extprotspacing,boolean_t bChannelChange,int * status)2394 ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2395 enum ath9k_ht_macmode macmode,
2396 uint8_t txchainmask, uint8_t rxchainmask,
2397 enum ath9k_ht_extprotspacing extprotspacing,
2398 boolean_t bChannelChange, int *status)
2399 {
2400 uint32_t saveLedState;
2401 struct ath_hal_5416 *ahp = AH5416(ah);
2402 struct ath9k_channel *curchan = ah->ah_curchan;
2403 uint32_t saveDefAntenna;
2404 uint32_t macStaId1;
2405 int ecode;
2406 int i, rx_chainmask;
2407
2408 ahp->ah_extprotspacing = extprotspacing;
2409 ahp->ah_txchainmask = txchainmask;
2410 ahp->ah_rxchainmask = rxchainmask;
2411
2412 if (AR_SREV_9280(ah)) {
2413 ahp->ah_txchainmask &= 0x3;
2414 ahp->ah_rxchainmask &= 0x3;
2415 }
2416
2417 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2418 ARN_DBG((ARN_DBG_ANY, "arn: "
2419 "%s: invalid channel %u/0x%x; no mapping\n",
2420 __func__, chan->channel, chan->channelFlags));
2421 ecode = EINVAL;
2422 goto bad;
2423 }
2424
2425 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2426 ARN_DBG((ARN_DBG_ANY, "arn: "
2427 "%s: ath9k_hw_setpower failed!!!\n", __func__));
2428 ecode = EIO;
2429 goto bad;
2430 }
2431
2432 if (curchan)
2433 (void) ath9k_hw_getnf(ah, curchan);
2434
2435 if (bChannelChange &&
2436 (ahp->ah_chipFullSleep != B_TRUE) &&
2437 (ah->ah_curchan != NULL) &&
2438 (chan->channel != ah->ah_curchan->channel) &&
2439 ((chan->channelFlags & CHANNEL_ALL) ==
2440 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2441 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2442 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2443
2444 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2445 ath9k_hw_loadnf(ah, ah->ah_curchan);
2446 ath9k_hw_start_nfcal(ah);
2447 return (B_TRUE);
2448 }
2449 }
2450
2451 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2452 if (saveDefAntenna == 0)
2453 saveDefAntenna = 1;
2454
2455 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2456
2457 saveLedState = REG_READ(ah, AR_CFG_LED) &
2458 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2459 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2460
2461 ath9k_hw_mark_phy_inactive(ah);
2462
2463 if (!ath9k_hw_chip_reset(ah, chan)) {
2464 ARN_DBG((ARN_DBG_RESET, "arn: "
2465 "%s: chip reset failed\n", __func__));
2466 ecode = EINVAL;
2467 goto bad;
2468 }
2469
2470 if (AR_SREV_9280(ah)) {
2471 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2472 AR_GPIO_JTAG_DISABLE);
2473 if (is_set(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2474 if (IS_CHAN_5GHZ(chan))
2475 ath9k_hw_set_gpio(ah, 9, 0);
2476 else
2477 ath9k_hw_set_gpio(ah, 9, 1);
2478 }
2479 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2480 }
2481
2482 ecode = ath9k_hw_process_ini(ah, chan, macmode);
2483 if (ecode != 0) {
2484 ecode = EINVAL;
2485 goto bad;
2486 }
2487
2488 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2489 ath9k_hw_set_delta_slope(ah, chan);
2490
2491 if (AR_SREV_9280_10_OR_LATER(ah))
2492 ath9k_hw_9280_spur_mitigate(ah, chan);
2493 else
2494 ath9k_hw_spur_mitigate(ah, chan);
2495
2496 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2497 ARN_DBG((ARN_DBG_EEPROM, "arn: "
2498 "%s: error setting board options\n", __func__));
2499 ecode = EIO;
2500 goto bad;
2501 }
2502
2503 ath9k_hw_decrease_chain_power(ah, chan);
2504
2505 REG_WRITE(ah, AR_STA_ID0, ARN_LE_READ_32(ahp->ah_macaddr));
2506 REG_WRITE(ah, AR_STA_ID1, ARN_LE_READ_16(ahp->ah_macaddr + 4) |
2507 macStaId1 |
2508 AR_STA_ID1_RTS_USE_DEF |
2509 (ah->ah_config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2510 ahp->ah_staId1Defaults);
2511 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2512
2513 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
2514 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
2515
2516 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2517
2518 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
2519 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
2520 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2521
2522 REG_WRITE(ah, AR_ISR, ~0);
2523
2524 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2525
2526 if (AR_SREV_9280_10_OR_LATER(ah)) {
2527 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2528 ARN_DBG((ARN_DBG_FATAL, "arn: "
2529 "%s: ath9k_hw_ar9280_set_channel failed!!!\n",
2530 __func__));
2531 ecode = EIO;
2532 goto bad;
2533 }
2534 } else {
2535 if (!(ath9k_hw_set_channel(ah, chan))) {
2536 ARN_DBG((ARN_DBG_FATAL, "arn: "
2537 "%s: ath9k_hw_set_channel failed!!!\n", __func__));
2538 ecode = EIO;
2539 goto bad;
2540 }
2541 }
2542
2543 for (i = 0; i < AR_NUM_DCU; i++)
2544 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2545
2546 ahp->ah_intrTxqs = 0;
2547 for (i = 0; i < ah->ah_caps.total_queues; i++)
2548 (void) ath9k_hw_resettxqueue(ah, i);
2549
2550 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2551 ath9k_hw_init_qos(ah);
2552
2553 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2554 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2555 ath9k_enable_rfkill(ah);
2556 #endif
2557 ath9k_hw_init_user_settings(ah);
2558
2559 REG_WRITE(ah, AR_STA_ID1,
2560 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2561
2562 ath9k_hw_set_dma(ah);
2563
2564 REG_WRITE(ah, AR_OBS, 8);
2565
2566 if (ahp->ah_intrMitigation) {
2567
2568 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2569 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2570 }
2571
2572 ath9k_hw_init_bb(ah, chan);
2573
2574 if (!ath9k_hw_init_cal(ah, chan)) {
2575 ecode = EIO;
2576 goto bad;
2577 }
2578
2579 rx_chainmask = ahp->ah_rxchainmask;
2580 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2581 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2582 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2583 }
2584
2585 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2586
2587 if (AR_SREV_9100(ah)) {
2588 uint32_t mask;
2589 mask = REG_READ(ah, AR_CFG);
2590 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2591 ARN_DBG((ARN_DBG_RESET, "arn: "
2592 "%s CFG Byte Swap Set 0x%x\n",
2593 __func__, mask));
2594 } else {
2595 mask = INIT_CONFIG_STATUS |
2596 AR_CFG_SWRB | AR_CFG_SWTB;
2597 REG_WRITE(ah, AR_CFG, mask);
2598 ARN_DBG((ARN_DBG_RESET, "arn: "
2599 "%s Setting CFG 0x%x\n",
2600 __func__, REG_READ(ah, AR_CFG)));
2601 }
2602 } else {
2603 ARN_DBG((ARN_DBG_HW, "arn: ath9k_hw_keyreset(): "
2604 "#ifdef __BIG_ENDIAN \n"));
2605 #ifdef __BIG_ENDIAN
2606 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2607 #endif
2608 }
2609
2610 return (B_TRUE);
2611 bad:
2612 if (status)
2613 *status = ecode;
2614 return (B_FALSE);
2615 }
2616
2617 /* Key Cache Management */
2618
2619 boolean_t
ath9k_hw_keyreset(struct ath_hal * ah,uint16_t entry)2620 ath9k_hw_keyreset(struct ath_hal *ah, uint16_t entry)
2621 {
2622 uint32_t keyType;
2623
2624 if (entry >= ah->ah_caps.keycache_size) {
2625 ARN_DBG((ARN_DBG_KEYCACHE, "arn: ath9k_hw_keyreset(): "
2626 "entry %u out of range\n", entry));
2627
2628 return (B_FALSE);
2629 }
2630
2631 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2632
2633 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2634 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2635 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2636 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2637 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2638 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2639 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2640 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2641
2642 if (keyType == AR_KEYTABLE_TYPE_TKIP &&
2643 ATH9K_IS_MIC_ENABLED(ah)) {
2644 uint16_t micentry = entry + 64;
2645
2646 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2647 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2648 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2649 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2650
2651 }
2652
2653 if (ah->ah_curchan == NULL)
2654 return (B_TRUE);
2655
2656 return (B_TRUE);
2657 }
2658
2659 boolean_t
ath9k_hw_keysetmac(struct ath_hal * ah,uint16_t entry,const uint8_t * mac)2660 ath9k_hw_keysetmac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
2661 {
2662 uint32_t macHi, macLo;
2663
2664 if (entry >= ah->ah_caps.keycache_size) {
2665 ARN_DBG((ARN_DBG_KEYCACHE, "arn: "
2666 "%s: entry %u out of range\n", __func__, entry));
2667 return (B_FALSE);
2668 }
2669
2670 if (mac != NULL) {
2671 macHi = (mac[5] << 8) | mac[4];
2672 macLo = (mac[3] << 24) |
2673 (mac[2] << 16) |
2674 (mac[1] << 8) |
2675 mac[0];
2676 macLo >>= 1;
2677 macLo |= (macHi & 1) << 31;
2678 macHi >>= 1;
2679 } else {
2680 macLo = macHi = 0;
2681 }
2682 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2683 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2684
2685 return (B_TRUE);
2686 }
2687
2688 boolean_t
ath9k_hw_set_keycache_entry(struct ath_hal * ah,uint16_t entry,const struct ath9k_keyval * k,const uint8_t * mac,int xorKey)2689 ath9k_hw_set_keycache_entry(struct ath_hal *ah, uint16_t entry,
2690 const struct ath9k_keyval *k, const uint8_t *mac, int xorKey)
2691 {
2692 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2693 uint32_t key0, key1, key2, key3, key4;
2694 uint32_t keyType;
2695 uint32_t xorMask = xorKey ?
2696 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 |
2697 ATH9K_KEY_XOR << 8 | ATH9K_KEY_XOR) : 0;
2698 struct ath_hal_5416 *ahp = AH5416(ah);
2699
2700 if (entry >= pCap->keycache_size) {
2701 ARN_DBG((ARN_DBG_KEYCACHE, "arn: "
2702 "%s: entry %u out of range\n", __func__, entry));
2703 return (B_FALSE);
2704 }
2705
2706 switch (k->kv_type) {
2707 case ATH9K_CIPHER_AES_OCB:
2708 keyType = AR_KEYTABLE_TYPE_AES;
2709 break;
2710 case ATH9K_CIPHER_AES_CCM:
2711 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2712 ARN_DBG((ARN_DBG_KEYCACHE, "arn: "
2713 "%s: AES-CCM not supported by "
2714 "mac rev 0x%x\n", __func__,
2715 ah->ah_macRev));
2716 return (B_FALSE);
2717 }
2718 keyType = AR_KEYTABLE_TYPE_CCM;
2719 break;
2720 case ATH9K_CIPHER_TKIP:
2721 keyType = AR_KEYTABLE_TYPE_TKIP;
2722 if (ATH9K_IS_MIC_ENABLED(ah) &&
2723 entry + 64 >= pCap->keycache_size) {
2724 ARN_DBG((ARN_DBG_KEYCACHE, "arn: "
2725 "%s: entry %u inappropriate for TKIP\n",
2726 __func__, entry));
2727 return (B_FALSE);
2728 }
2729 break;
2730 case ATH9K_CIPHER_WEP:
2731 if (k->kv_len < ATH9K_LEN_WEP40) {
2732 ARN_DBG((ARN_DBG_KEYCACHE, "arn: "
2733 "%s: WEP key length %u too small\n",
2734 __func__, k->kv_len));
2735 return (B_FALSE);
2736 }
2737 if (k->kv_len <= ATH9K_LEN_WEP40)
2738 keyType = AR_KEYTABLE_TYPE_40;
2739 else if (k->kv_len <= ATH9K_LEN_WEP104)
2740 keyType = AR_KEYTABLE_TYPE_104;
2741 else
2742 keyType = AR_KEYTABLE_TYPE_128;
2743 break;
2744 case ATH9K_CIPHER_CLR:
2745 keyType = AR_KEYTABLE_TYPE_CLR;
2746 break;
2747 default:
2748 ARN_DBG((ARN_DBG_KEYCACHE, "arn: "
2749 "%s: cipher %u not supported\n", __func__,
2750 k->kv_type));
2751 return (B_FALSE);
2752 }
2753
2754 key0 = ARN_LE_READ_32(k->kv_val + 0) ^ xorMask;
2755 key1 = (ARN_LE_READ_16(k->kv_val + 4) ^ xorMask) & 0xffff;
2756 key2 = ARN_LE_READ_32(k->kv_val + 6) ^ xorMask;
2757 key3 = (ARN_LE_READ_16(k->kv_val + 10) ^ xorMask) & 0xffff;
2758 key4 = ARN_LE_READ_32(k->kv_val + 12) ^ xorMask;
2759
2760 if (k->kv_len <= ATH9K_LEN_WEP104)
2761 key4 &= 0xff;
2762
2763 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2764 uint16_t micentry = entry + 64;
2765
2766 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2767 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2768 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2769 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2770 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2771 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2772 (void) ath9k_hw_keysetmac(ah, entry, mac);
2773
2774 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2775 uint32_t mic0, mic1, mic2, mic3, mic4;
2776 mic0 = ARN_LE_READ_32(k->kv_mic + 0);
2777 mic2 = ARN_LE_READ_32(k->kv_mic + 4);
2778 mic1 = ARN_LE_READ_16(k->kv_txmic + 2) & 0xffff;
2779 mic3 = ARN_LE_READ_16(k->kv_txmic + 0) & 0xffff;
2780 mic4 = ARN_LE_READ_32(k->kv_txmic + 4);
2781 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2782 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2783 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2784 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2785 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2786 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2787 AR_KEYTABLE_TYPE_CLR);
2788
2789 } else {
2790 uint32_t mic0, mic2;
2791 mic0 = ARN_LE_READ_32(k->kv_mic + 0);
2792 mic2 = ARN_LE_READ_32(k->kv_mic + 4);
2793 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2794 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2795 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2796 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2797 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2798 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2799 AR_KEYTABLE_TYPE_CLR);
2800 }
2801 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2802 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2803 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2804 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2805 } else {
2806 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2807 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2808 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2809 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2810 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2811 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2812
2813 (void) ath9k_hw_keysetmac(ah, entry, mac);
2814 }
2815
2816 if (ah->ah_curchan == NULL)
2817 return (B_TRUE);
2818
2819 return (B_TRUE);
2820 }
2821
2822 boolean_t
ath9k_hw_keyisvalid(struct ath_hal * ah,uint16_t entry)2823 ath9k_hw_keyisvalid(struct ath_hal *ah, uint16_t entry)
2824 {
2825 if (entry < ah->ah_caps.keycache_size) {
2826 uint32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2827 if (val & AR_KEYTABLE_VALID)
2828 return (B_TRUE);
2829 }
2830 return (B_FALSE);
2831 }
2832
2833 /* Power Management (Chipset) */
2834
2835 static void
ath9k_set_power_sleep(struct ath_hal * ah,int setChip)2836 ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2837 {
2838 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2839 if (setChip) {
2840 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2841 AR_RTC_FORCE_WAKE_EN);
2842 if (!AR_SREV_9100(ah))
2843 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2844
2845 REG_CLR_BIT(ah, (uint16_t)(AR_RTC_RESET),
2846 AR_RTC_RESET_EN);
2847 }
2848 }
2849
2850 static void
ath9k_set_power_network_sleep(struct ath_hal * ah,int setChip)2851 ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2852 {
2853 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2854 if (setChip) {
2855 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2856
2857 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2858 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2859 AR_RTC_FORCE_WAKE_ON_INT);
2860 } else {
2861 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2862 AR_RTC_FORCE_WAKE_EN);
2863 }
2864 }
2865 }
2866
2867 static boolean_t
ath9k_hw_set_power_awake(struct ath_hal * ah,int setChip)2868 ath9k_hw_set_power_awake(struct ath_hal *ah, int setChip)
2869 {
2870 uint32_t val;
2871 int i;
2872
2873 if (setChip) {
2874 if ((REG_READ(ah, AR_RTC_STATUS) &
2875 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2876 if (ath9k_hw_set_reset_reg(ah,
2877 ATH9K_RESET_POWER_ON) != B_TRUE) {
2878 return (B_FALSE);
2879 }
2880 }
2881 if (AR_SREV_9100(ah))
2882 REG_SET_BIT(ah, AR_RTC_RESET,
2883 AR_RTC_RESET_EN);
2884
2885 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2886 AR_RTC_FORCE_WAKE_EN);
2887 drv_usecwait(50);
2888
2889 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2890 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2891 if (val == AR_RTC_STATUS_ON)
2892 break;
2893 drv_usecwait(50);
2894 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2895 AR_RTC_FORCE_WAKE_EN);
2896 }
2897 if (i == 0) {
2898 ARN_DBG((ARN_DBG_POWER_MGMT,
2899 "arn: ath9k_hw_set_power_awake(): "
2900 "Failed to wakeup in %uus\n",
2901 POWER_UP_TIME / 20));
2902
2903 return (B_FALSE);
2904 }
2905 }
2906
2907 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2908
2909 return (B_TRUE);
2910 }
2911
2912 boolean_t
ath9k_hw_setpower(struct ath_hal * ah,enum ath9k_power_mode mode)2913 ath9k_hw_setpower(struct ath_hal *ah, enum ath9k_power_mode mode)
2914 {
2915 struct ath_hal_5416 *ahp = AH5416(ah);
2916 static const char *modes[] = {
2917 "AWAKE",
2918 "FULL-SLEEP",
2919 "NETWORK SLEEP",
2920 "UNDEFINED"
2921 };
2922 int status = B_TRUE, setChip = B_TRUE;
2923 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_setpower(): "
2924 "%s -> %s (%s)\n",
2925 modes[ahp->ah_powerMode],
2926 modes[mode],
2927 setChip ? "set chip " : ""));
2928
2929 switch (mode) {
2930 case ATH9K_PM_AWAKE:
2931 status = ath9k_hw_set_power_awake(ah, setChip);
2932 break;
2933 case ATH9K_PM_FULL_SLEEP:
2934 ath9k_set_power_sleep(ah, setChip);
2935 ahp->ah_chipFullSleep = B_TRUE;
2936 break;
2937 case ATH9K_PM_NETWORK_SLEEP:
2938 ath9k_set_power_network_sleep(ah, setChip);
2939 break;
2940 default:
2941 ARN_DBG((ARN_DBG_ANY, "arn: ath9k_hw_setpower(): "
2942 "unknown power mode %u\n", mode));
2943 return (B_FALSE);
2944 }
2945 ahp->ah_powerMode = mode;
2946
2947 return (status);
2948 }
2949
2950 void
ath9k_hw_configpcipowersave(struct ath_hal * ah,int restore)2951 ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2952 {
2953 struct ath_hal_5416 *ahp = AH5416(ah);
2954 uint8_t i;
2955
2956 if (ah->ah_isPciExpress != B_TRUE)
2957 return;
2958
2959 if (ah->ah_config.pcie_powersave_enable == 2)
2960 return;
2961
2962 if (restore)
2963 return;
2964
2965 if (AR_SREV_9280_20_OR_LATER(ah)) {
2966 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2967 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2968 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2969 }
2970 drv_usecwait(1000);
2971 } else if (AR_SREV_9280(ah) &&
2972 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2973 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2974 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2975
2976 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2977 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2978 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2979
2980 if (ah->ah_config.pcie_clock_req)
2981 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2982 else
2983 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2984
2985 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2986 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2987 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2988
2989 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2990
2991 drv_usecwait(1000);
2992 } else {
2993 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2994 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2995 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2996 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2997 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2998 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2999 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3000 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3001 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3002 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3003 }
3004
3005 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3006
3007 if (ah->ah_config.pcie_waen) {
3008 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3009 } else {
3010 if (AR_SREV_9285(ah))
3011 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
3012 else if (AR_SREV_9280(ah))
3013 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
3014 else
3015 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3016 }
3017 }
3018
3019 /* Interrupt Handling */
3020
3021 boolean_t
ath9k_hw_intrpend(struct ath_hal * ah)3022 ath9k_hw_intrpend(struct ath_hal *ah)
3023 {
3024 uint32_t host_isr;
3025
3026 if (AR_SREV_9100(ah))
3027 return (B_TRUE);
3028
3029 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3030 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3031 return (B_TRUE);
3032
3033 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3034
3035 if ((host_isr & AR_INTR_SYNC_DEFAULT) &&
3036 (host_isr != AR_INTR_SPURIOUS))
3037 return (B_TRUE);
3038
3039 return (B_FALSE);
3040 }
3041
3042 boolean_t
ath9k_hw_getisr(struct ath_hal * ah,enum ath9k_int * masked)3043 ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
3044 {
3045 uint32_t isr = 0;
3046 uint32_t mask2 = 0;
3047 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3048 uint32_t sync_cause = 0;
3049 boolean_t fatal_int = B_FALSE;
3050 struct ath_hal_5416 *ahp = AH5416(ah);
3051
3052 if (!AR_SREV_9100(ah)) {
3053 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3054 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3055 == AR_RTC_STATUS_ON) {
3056 isr = REG_READ(ah, AR_ISR);
3057 }
3058 }
3059
3060 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3061 AR_INTR_SYNC_DEFAULT;
3062
3063 *masked = 0;
3064
3065 if (!isr && !sync_cause)
3066 return (B_FALSE);
3067 } else {
3068 *masked = 0;
3069 isr = REG_READ(ah, AR_ISR);
3070 }
3071
3072 if (isr) {
3073 if (isr & AR_ISR_BCNMISC) {
3074 uint32_t isr2;
3075 isr2 = REG_READ(ah, AR_ISR_S2);
3076 if (isr2 & AR_ISR_S2_TIM)
3077 mask2 |= ATH9K_INT_TIM;
3078 if (isr2 & AR_ISR_S2_DTIM)
3079 mask2 |= ATH9K_INT_DTIM;
3080 if (isr2 & AR_ISR_S2_DTIMSYNC)
3081 mask2 |= ATH9K_INT_DTIMSYNC;
3082 if (isr2 & (AR_ISR_S2_CABEND))
3083 mask2 |= ATH9K_INT_CABEND;
3084 if (isr2 & AR_ISR_S2_GTT)
3085 mask2 |= ATH9K_INT_GTT;
3086 if (isr2 & AR_ISR_S2_CST)
3087 mask2 |= ATH9K_INT_CST;
3088 }
3089
3090 isr = REG_READ(ah, AR_ISR_RAC);
3091 if (isr == 0xffffffff) {
3092 *masked = 0;
3093 return (B_FALSE);
3094 }
3095
3096 *masked = isr & ATH9K_INT_COMMON;
3097
3098 if (ahp->ah_intrMitigation) {
3099 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3100 *masked |= ATH9K_INT_RX;
3101 }
3102
3103 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3104 *masked |= ATH9K_INT_RX;
3105 if (isr &
3106 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3107 AR_ISR_TXEOL)) {
3108 uint32_t s0_s, s1_s;
3109
3110 *masked |= ATH9K_INT_TX;
3111
3112 s0_s = REG_READ(ah, AR_ISR_S0_S);
3113 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3114 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3115
3116 s1_s = REG_READ(ah, AR_ISR_S1_S);
3117 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3118 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3119 }
3120
3121 if (isr & AR_ISR_RXORN) {
3122 ARN_DBG((ARN_DBG_INTERRUPT, "arn: "
3123 "%s: receive FIFO overrun interrupt\n", __func__));
3124 }
3125
3126 if (!AR_SREV_9100(ah)) {
3127 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3128 uint32_t isr5 = REG_READ(ah, AR_ISR_S5_S);
3129 if (isr5 & AR_ISR_S5_TIM_TIMER)
3130 *masked |= ATH9K_INT_TIM_TIMER;
3131 }
3132 }
3133
3134 *masked |= mask2;
3135 }
3136
3137 if (AR_SREV_9100(ah))
3138 return (B_TRUE);
3139
3140 if (sync_cause) {
3141 fatal_int = (sync_cause &
3142 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) ?
3143 B_TRUE : B_FALSE;
3144
3145 if (fatal_int) {
3146 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3147 ARN_DBG((ARN_DBG_INTERRUPT, "arn: "
3148 "%s: received PCI FATAL interrupt\n",
3149 __func__));
3150 }
3151 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3152 ARN_DBG((ARN_DBG_INTERRUPT, "arn: "
3153 "%s: received PCI PERR interrupt\n",
3154 __func__));
3155 }
3156 }
3157 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3158 ARN_DBG((ARN_DBG_INTERRUPT, "arn: "
3159 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
3160 __func__));
3161
3162 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3163 REG_WRITE(ah, AR_RC, 0);
3164 *masked |= ATH9K_INT_FATAL;
3165 }
3166 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3167 ARN_DBG((ARN_DBG_ANY, "arn: "
3168 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
3169 __func__));
3170 }
3171
3172 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3173 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3174 }
3175
3176 return (B_TRUE);
3177 }
3178
3179 enum ath9k_int
ath9k_hw_intrget(struct ath_hal * ah)3180 ath9k_hw_intrget(struct ath_hal *ah)
3181 {
3182 return (AH5416(ah)->ah_maskReg);
3183 }
3184
3185 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hal * ah,enum ath9k_int ints)3186 ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3187 {
3188 struct ath_hal_5416 *ahp = AH5416(ah);
3189 uint32_t omask = ahp->ah_maskReg;
3190 uint32_t mask, mask2;
3191 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3192
3193 ARN_DBG((ARN_DBG_INTERRUPT,
3194 "arn: ath9k_hw_set_interrupts(): "
3195 "0x%x => 0x%x\n", omask, ints));
3196
3197 if (omask & ATH9K_INT_GLOBAL) {
3198 ARN_DBG((ARN_DBG_INTERRUPT,
3199 "arn: ath9k_hw_set_interrupts(): "
3200 "disable IER\n"));
3201
3202 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3203 (void) REG_READ(ah, AR_IER);
3204 if (!AR_SREV_9100(ah)) {
3205 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3206 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3207
3208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3209 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3210 }
3211 }
3212
3213 mask = ints & ATH9K_INT_COMMON;
3214 mask2 = 0;
3215
3216 if (ints & ATH9K_INT_TX) {
3217 if (ahp->ah_txOkInterruptMask)
3218 mask |= AR_IMR_TXOK;
3219 if (ahp->ah_txDescInterruptMask)
3220 mask |= AR_IMR_TXDESC;
3221 if (ahp->ah_txErrInterruptMask)
3222 mask |= AR_IMR_TXERR;
3223 if (ahp->ah_txEolInterruptMask)
3224 mask |= AR_IMR_TXEOL;
3225 }
3226 if (ints & ATH9K_INT_RX) {
3227 mask |= AR_IMR_RXERR;
3228 if (ahp->ah_intrMitigation)
3229 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3230 else
3231 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3232 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3233 mask |= AR_IMR_GENTMR;
3234 }
3235
3236 if (ints & (ATH9K_INT_BMISC)) {
3237 mask |= AR_IMR_BCNMISC;
3238 if (ints & ATH9K_INT_TIM)
3239 mask2 |= AR_IMR_S2_TIM;
3240 if (ints & ATH9K_INT_DTIM)
3241 mask2 |= AR_IMR_S2_DTIM;
3242 if (ints & ATH9K_INT_DTIMSYNC)
3243 mask2 |= AR_IMR_S2_DTIMSYNC;
3244 if (ints & ATH9K_INT_CABEND)
3245 mask2 |= (AR_IMR_S2_CABEND);
3246 }
3247
3248 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3249 mask |= AR_IMR_BCNMISC;
3250 if (ints & ATH9K_INT_GTT)
3251 mask2 |= AR_IMR_S2_GTT;
3252 if (ints & ATH9K_INT_CST)
3253 mask2 |= AR_IMR_S2_CST;
3254 }
3255
3256 REG_WRITE(ah, AR_IMR, mask);
3257 mask = REG_READ(ah, AR_IMR_S2) &
3258 ~(AR_IMR_S2_TIM |
3259 AR_IMR_S2_DTIM |
3260 AR_IMR_S2_DTIMSYNC |
3261 AR_IMR_S2_CABEND |
3262 AR_IMR_S2_CABTO |
3263 AR_IMR_S2_TSFOOR |
3264 AR_IMR_S2_GTT |
3265 AR_IMR_S2_CST);
3266 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3267 ahp->ah_maskReg = ints;
3268
3269 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3270 if (ints & ATH9K_INT_TIM_TIMER)
3271 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3272 else
3273 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3274 }
3275
3276 if (ints & ATH9K_INT_GLOBAL) {
3277 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3278 if (!AR_SREV_9100(ah)) {
3279 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3280 AR_INTR_MAC_IRQ);
3281 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3282
3283
3284 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3285 AR_INTR_SYNC_DEFAULT);
3286 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3287 AR_INTR_SYNC_DEFAULT);
3288 }
3289
3290 }
3291
3292 return (omask);
3293 }
3294
3295 /* Beacon Handling */
3296
3297 void
ath9k_hw_beaconinit(struct ath_hal * ah,uint32_t next_beacon,uint32_t beacon_period)3298 ath9k_hw_beaconinit(struct ath_hal *ah, uint32_t next_beacon,
3299 uint32_t beacon_period)
3300 {
3301 struct ath_hal_5416 *ahp = AH5416(ah);
3302 int flags = 0;
3303
3304 ahp->ah_beaconInterval = beacon_period;
3305
3306 switch (ah->ah_opmode) {
3307 case ATH9K_M_STA:
3308 case ATH9K_M_MONITOR:
3309 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3310 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3311 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3312 flags |= AR_TBTT_TIMER_EN;
3313 break;
3314 case ATH9K_M_IBSS:
3315 REG_SET_BIT(ah, AR_TXCFG,
3316 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3317 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3318 TU_TO_USEC(next_beacon +
3319 (ahp->ah_atimWindow ? ahp->
3320 ah_atimWindow : 1)));
3321 flags |= AR_NDP_TIMER_EN;
3322 /*FALLTHRU*/
3323 case ATH9K_M_HOSTAP:
3324 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3325 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3326 TU_TO_USEC(next_beacon -
3327 ah->ah_config.
3328 dma_beacon_response_time));
3329 REG_WRITE(ah, AR_NEXT_SWBA,
3330 TU_TO_USEC(next_beacon -
3331 ah->ah_config.
3332 sw_beacon_response_time));
3333 flags |=
3334 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3335 break;
3336 default:
3337 ARN_DBG((ARN_DBG_BEACON,
3338 "%s: unsupported opmode: %d\n",
3339 __func__, ah->ah_opmode));
3340 return;
3341 }
3342
3343 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3344 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3345 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3346 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3347
3348 beacon_period &= ~ATH9K_BEACON_ENA;
3349 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3350 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3351 ath9k_hw_reset_tsf(ah);
3352 }
3353
3354 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3355 }
3356
3357 void
ath9k_hw_set_sta_beacon_timers(struct ath_hal * ah,const struct ath9k_beacon_state * bs)3358 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3359 const struct ath9k_beacon_state *bs)
3360 {
3361 uint32_t nextTbtt, beaconintval, dtimperiod, beacontimeout;
3362 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3363
3364 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3365
3366 REG_WRITE(ah, AR_BEACON_PERIOD,
3367 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3368 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3369 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3370
3371 REG_RMW_FIELD(ah, AR_RSSI_THR,
3372 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3373
3374 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3375
3376 if (bs->bs_sleepduration > beaconintval)
3377 beaconintval = bs->bs_sleepduration;
3378
3379 dtimperiod = bs->bs_dtimperiod;
3380 if (bs->bs_sleepduration > dtimperiod)
3381 dtimperiod = bs->bs_sleepduration;
3382
3383 if (beaconintval == dtimperiod)
3384 nextTbtt = bs->bs_nextdtim;
3385 else
3386 nextTbtt = bs->bs_nexttbtt;
3387
3388 ARN_DBG((ARN_DBG_BEACON, "arn: "
3389 "%s: next DTIM %d\n", __func__, bs->bs_nextdtim));
3390 ARN_DBG((ARN_DBG_BEACON, "arn: "
3391 "%s: next beacon %d\n", __func__, nextTbtt));
3392 ARN_DBG((ARN_DBG_BEACON, "arn: "
3393 "%s: beacon period %d\n", __func__, beaconintval));
3394 ARN_DBG((ARN_DBG_BEACON, "arn: "
3395 "%s: DTIM period %d\n", __func__, dtimperiod));
3396
3397 REG_WRITE(ah, AR_NEXT_DTIM,
3398 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3399 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3400
3401 REG_WRITE(ah, AR_SLEEP1,
3402 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) |
3403 AR_SLEEP1_ASSUME_DTIM);
3404
3405 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3406 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3407 else
3408 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3409
3410 REG_WRITE(ah, AR_SLEEP2,
3411 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3412
3413 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3414 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3415
3416 REG_SET_BIT(ah, AR_TIMER_MODE,
3417 AR_TBTT_TIMER_EN |
3418 AR_TIM_TIMER_EN |
3419 AR_DTIM_TIMER_EN);
3420
3421 /* TSF Out of Range Threshold */
3422 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3423 }
3424
3425 /* HW Capabilities */
3426
3427 boolean_t
ath9k_hw_fill_cap_info(struct ath_hal * ah)3428 ath9k_hw_fill_cap_info(struct ath_hal *ah)
3429 {
3430 struct ath_hal_5416 *ahp = AH5416(ah);
3431 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3432 uint16_t capField = 0, eeval;
3433
3434 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3435
3436 ah->ah_currentRD = eeval;
3437
3438 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3439 ah->ah_currentRDExt = eeval;
3440
3441 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3442
3443 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
3444 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3445 if (ah->ah_currentRD == 0x64 ||
3446 ah->ah_currentRD == 0x65)
3447 ah->ah_currentRD += 5;
3448 else if (ah->ah_currentRD == 0x41)
3449 ah->ah_currentRD = 0x43;
3450
3451 ARN_DBG((ARN_DBG_REGULATORY,
3452 "%s: regdomain mapped to 0x%x\n", __func__,
3453 ah->ah_currentRD));
3454 }
3455
3456 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3457
3458 bzero(pCap->wireless_modes, sizeof (uint8_t)*4);
3459
3460 if (eeval & AR5416_OPFLAGS_11A) {
3461 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3462 if (ah->ah_config.ht_enable) {
3463 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3464 set_bit(ATH9K_MODE_11NA_HT20,
3465 pCap->wireless_modes);
3466 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3467 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3468 pCap->wireless_modes);
3469 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3470 pCap->wireless_modes);
3471 }
3472 }
3473 }
3474
3475 if (eeval & AR5416_OPFLAGS_11G) {
3476 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3477 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3478 if (ah->ah_config.ht_enable) {
3479 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3480 set_bit(ATH9K_MODE_11NG_HT20,
3481 pCap->wireless_modes);
3482 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3483 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3484 pCap->wireless_modes);
3485 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3486 pCap->wireless_modes);
3487 }
3488 }
3489 }
3490
3491 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3492 if ((ah->ah_isPciExpress) ||
3493 (eeval & AR5416_OPFLAGS_11A)) {
3494 pCap->rx_chainmask =
3495 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3496 } else {
3497 pCap->rx_chainmask =
3498 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3499 }
3500
3501 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3502 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3503
3504 pCap->low_2ghz_chan = 2312;
3505 pCap->high_2ghz_chan = 2732;
3506
3507 pCap->low_5ghz_chan = 4920;
3508 pCap->high_5ghz_chan = 6100;
3509
3510 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3511 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3512 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3513
3514 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3515 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3516 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3517
3518 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3519
3520 if (ah->ah_config.ht_enable)
3521 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3522 else
3523 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3524
3525 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3526 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3527 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3528 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3529
3530 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3531 pCap->total_queues =
3532 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3533 else
3534 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3535
3536 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3537 pCap->keycache_size =
3538 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3539 else
3540 pCap->keycache_size = AR_KEYTABLE_SIZE;
3541
3542 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3543 pCap->num_mr_retries = 4;
3544 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3545
3546 if (AR_SREV_9280_10_OR_LATER(ah))
3547 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3548 else
3549 pCap->num_gpio_pins = AR_NUM_GPIO;
3550
3551 if (AR_SREV_9280_10_OR_LATER(ah)) {
3552 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3553 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3554 } else {
3555 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3556 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3557 }
3558
3559 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3560 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3561 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3562 } else {
3563 pCap->rts_aggr_limit = (8 * 1024);
3564 }
3565
3566 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3567
3568 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3569 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3570 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3571 ah->ah_rfkill_gpio =
3572 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3573 ah->ah_rfkill_polarity =
3574 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3575
3576 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3577 }
3578 #endif
3579
3580 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3581 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3582 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3583 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3584 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3585 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3586 else
3587 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3588
3589 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3590 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3591 else
3592 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3593
3594 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3595 pCap->reg_cap =
3596 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3597 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3598 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3599 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3600 } else {
3601 pCap->reg_cap =
3602 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3603 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3604 }
3605
3606 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3607
3608 /* ATH9K_HAL_FREQ_BAND_5GHZ == 0 */
3609 pCap->num_antcfg_5ghz =
3610 ath9k_hw_get_num_ant_config(ah, 0);
3611 /* ATH9K_HAL_FREQ_BAND_2GHZ == 1 */
3612 pCap->num_antcfg_2ghz =
3613 ath9k_hw_get_num_ant_config(ah, 1);
3614
3615 return (B_TRUE);
3616 }
3617
3618 boolean_t
ath9k_hw_getcapability(struct ath_hal * ah,enum ath9k_capability_type type,uint32_t capability,uint32_t * result)3619 ath9k_hw_getcapability(struct ath_hal *ah,
3620 enum ath9k_capability_type type,
3621 uint32_t capability, uint32_t *result)
3622 {
3623 struct ath_hal_5416 *ahp = AH5416(ah);
3624 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3625
3626 switch (type) {
3627 case ATH9K_CAP_CIPHER:
3628 switch (capability) {
3629 case ATH9K_CIPHER_AES_CCM:
3630 case ATH9K_CIPHER_AES_OCB:
3631 case ATH9K_CIPHER_TKIP:
3632 case ATH9K_CIPHER_WEP:
3633 case ATH9K_CIPHER_MIC:
3634 case ATH9K_CIPHER_CLR:
3635 return (B_TRUE);
3636 default:
3637 return (B_FALSE);
3638 }
3639 case ATH9K_CAP_TKIP_MIC:
3640 switch (capability) {
3641 case 0:
3642 return (B_TRUE);
3643 case 1:
3644 return ((ahp->ah_staId1Defaults &
3645 AR_STA_ID1_CRPT_MIC_ENABLE) ? B_TRUE :
3646 B_FALSE);
3647 }
3648 /*FALLTHRU*/
3649 case ATH9K_CAP_TKIP_SPLIT:
3650 return ((ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3651 B_FALSE : B_TRUE);
3652 case ATH9K_CAP_WME_TKIPMIC:
3653 return (0);
3654 case ATH9K_CAP_PHYCOUNTERS:
3655 return (ahp->ah_hasHwPhyCounters ? 0 : -ENXIO);
3656 case ATH9K_CAP_DIVERSITY:
3657 return ((REG_READ(ah, AR_PHY_CCK_DETECT) &
3658 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3659 B_TRUE : B_FALSE);
3660 case ATH9K_CAP_PHYDIAG:
3661 return (B_TRUE);
3662 case ATH9K_CAP_MCAST_KEYSRCH:
3663 switch (capability) {
3664 case 0:
3665 return (B_TRUE);
3666 case 1:
3667 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3668 return (B_FALSE);
3669 } else {
3670 return ((ahp->ah_staId1Defaults &
3671 AR_STA_ID1_MCAST_KSRCH) ? B_TRUE :
3672 B_FALSE);
3673 }
3674 }
3675 return (B_FALSE);
3676 case ATH9K_CAP_TSF_ADJUST:
3677 return ((ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3678 B_TRUE : B_FALSE);
3679 case ATH9K_CAP_RFSILENT:
3680 if (capability == 3)
3681 return (B_FALSE);
3682 /*FALLTHRU*/
3683 case ATH9K_CAP_ANT_CFG_2GHZ:
3684 *result = pCap->num_antcfg_2ghz;
3685 return (B_TRUE);
3686 case ATH9K_CAP_ANT_CFG_5GHZ:
3687 *result = pCap->num_antcfg_5ghz;
3688 return (B_TRUE);
3689 case ATH9K_CAP_TXPOW:
3690 switch (capability) {
3691 case 0:
3692 return (0);
3693 case 1:
3694 *result = ah->ah_powerLimit;
3695 return (0);
3696 case 2:
3697 *result = ah->ah_maxPowerLevel;
3698 return (0);
3699 case 3:
3700 *result = ah->ah_tpScale;
3701 return (0);
3702 }
3703 return (B_FALSE);
3704 default:
3705 return (B_FALSE);
3706 }
3707 }
3708
3709 /* ARGSUSED */
3710 boolean_t
ath9k_hw_setcapability(struct ath_hal * ah,enum ath9k_capability_type type,uint32_t capability,uint32_t setting,int * status)3711 ath9k_hw_setcapability(struct ath_hal *ah,
3712 enum ath9k_capability_type type,
3713 uint32_t capability, uint32_t setting,
3714 int *status)
3715 {
3716 struct ath_hal_5416 *ahp = AH5416(ah);
3717 uint32_t v;
3718
3719 switch (type) {
3720 case ATH9K_CAP_TKIP_MIC:
3721 if (setting)
3722 ahp->ah_staId1Defaults |=
3723 AR_STA_ID1_CRPT_MIC_ENABLE;
3724 else
3725 ahp->ah_staId1Defaults &=
3726 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3727 return (B_TRUE);
3728 case ATH9K_CAP_DIVERSITY:
3729 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3730 if (setting)
3731 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3732 else
3733 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3734 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3735 return (B_TRUE);
3736 case ATH9K_CAP_MCAST_KEYSRCH:
3737 if (setting)
3738 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3739 else
3740 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3741 return (B_TRUE);
3742 case ATH9K_CAP_TSF_ADJUST:
3743 if (setting)
3744 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3745 else
3746 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3747 return (B_TRUE);
3748 default:
3749 return (B_FALSE);
3750 }
3751 }
3752
3753 /* GPIO / RFKILL / Antennae */
3754
3755 static void
ath9k_hw_gpio_cfg_output_mux(struct ath_hal * ah,uint32_t gpio,uint32_t type)3756 ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3757 uint32_t gpio, uint32_t type)
3758 {
3759 int addr;
3760 uint32_t gpio_shift, tmp;
3761
3762 if (gpio > 11)
3763 addr = AR_GPIO_OUTPUT_MUX3;
3764 else if (gpio > 5)
3765 addr = AR_GPIO_OUTPUT_MUX2;
3766 else
3767 addr = AR_GPIO_OUTPUT_MUX1;
3768
3769 gpio_shift = (gpio % 6) * 5;
3770
3771 if (AR_SREV_9280_20_OR_LATER(ah) ||
3772 (addr != AR_GPIO_OUTPUT_MUX1)) {
3773 REG_RMW(ah, addr, (type << gpio_shift),
3774 (0x1f << gpio_shift));
3775 } else {
3776 tmp = REG_READ(ah, addr);
3777 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3778 tmp &= ~(0x1f << gpio_shift);
3779 tmp |= (type << gpio_shift);
3780 REG_WRITE(ah, addr, tmp);
3781 }
3782 }
3783
3784 void
ath9k_hw_cfg_gpio_input(struct ath_hal * ah,uint32_t gpio)3785 ath9k_hw_cfg_gpio_input(struct ath_hal *ah, uint32_t gpio)
3786 {
3787 uint32_t gpio_shift;
3788
3789 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3790
3791 gpio_shift = gpio << 1;
3792
3793 REG_RMW(ah,
3794 AR_GPIO_OE_OUT,
3795 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3796 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3797 }
3798
3799 uint32_t
ath9k_hw_gpio_get(struct ath_hal * ah,uint32_t gpio)3800 ath9k_hw_gpio_get(struct ath_hal *ah, uint32_t gpio)
3801 {
3802 if (gpio >= ah->ah_caps.num_gpio_pins)
3803 return (0xffffffff);
3804
3805 if (AR_SREV_9280_10_OR_LATER(ah)) {
3806 return ((MS(REG_READ(ah, AR_GPIO_IN_OUT),
3807 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0);
3808 } else {
3809 return ((MS(REG_READ(ah,
3810 AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3811 AR_GPIO_BIT(gpio)) != 0);
3812 }
3813 }
3814
3815 void
ath9k_hw_cfg_output(struct ath_hal * ah,uint32_t gpio,uint32_t ah_signal_type)3816 ath9k_hw_cfg_output(struct ath_hal *ah, uint32_t gpio,
3817 uint32_t ah_signal_type)
3818 {
3819 uint32_t gpio_shift;
3820
3821 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3822
3823 gpio_shift = 2 * gpio;
3824
3825 REG_RMW(ah,
3826 AR_GPIO_OE_OUT,
3827 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3828 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3829 }
3830
3831 void
ath9k_hw_set_gpio(struct ath_hal * ah,uint32_t gpio,uint32_t val)3832 ath9k_hw_set_gpio(struct ath_hal *ah, uint32_t gpio, uint32_t val)
3833 {
3834 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3835 AR_GPIO_BIT(gpio));
3836 }
3837
3838 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3839 void
ath9k_enable_rfkill(struct ath_hal * ah)3840 ath9k_enable_rfkill(struct ath_hal *ah)
3841 {
3842 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3843 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3844
3845 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3846 AR_GPIO_INPUT_MUX2_RFSILENT);
3847
3848 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3849 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3850 }
3851 #endif
3852
3853 int
ath9k_hw_select_antconfig(struct ath_hal * ah,uint32_t cfg)3854 ath9k_hw_select_antconfig(struct ath_hal *ah, uint32_t cfg)
3855 {
3856 struct ath9k_channel *chan = ah->ah_curchan;
3857 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3858 uint16_t ant_config;
3859 uint32_t halNumAntConfig;
3860
3861 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3862 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3863
3864 if (cfg < halNumAntConfig) {
3865 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3866 cfg, &ant_config)) {
3867 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3868 return (0);
3869 }
3870 }
3871
3872 return (-EINVAL);
3873 }
3874
3875 uint32_t
ath9k_hw_getdefantenna(struct ath_hal * ah)3876 ath9k_hw_getdefantenna(struct ath_hal *ah)
3877 {
3878 return (REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
3879 }
3880
3881 void
ath9k_hw_setantenna(struct ath_hal * ah,uint32_t antenna)3882 ath9k_hw_setantenna(struct ath_hal *ah, uint32_t antenna)
3883 {
3884 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3885 }
3886
3887 /* ARGSUSED */
3888 boolean_t
ath9k_hw_setantennaswitch(struct ath_hal * ah,enum ath9k_ant_setting settings,struct ath9k_channel * chan,uint8_t * tx_chainmask,uint8_t * rx_chainmask,uint8_t * antenna_cfgd)3889 ath9k_hw_setantennaswitch(struct ath_hal *ah,
3890 enum ath9k_ant_setting settings,
3891 struct ath9k_channel *chan,
3892 uint8_t *tx_chainmask,
3893 uint8_t *rx_chainmask,
3894 uint8_t *antenna_cfgd)
3895 {
3896 struct ath_hal_5416 *ahp = AH5416(ah);
3897 static uint8_t tx_chainmask_cfg, rx_chainmask_cfg;
3898
3899 if (AR_SREV_9280(ah)) {
3900 if (!tx_chainmask_cfg) {
3901
3902 tx_chainmask_cfg = *tx_chainmask;
3903 rx_chainmask_cfg = *rx_chainmask;
3904 }
3905
3906 switch (settings) {
3907 case ATH9K_ANT_FIXED_A:
3908 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3909 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3910 *antenna_cfgd = B_TRUE;
3911 break;
3912 case ATH9K_ANT_FIXED_B:
3913 if (ah->ah_caps.tx_chainmask >
3914 ATH9K_ANTENNA1_CHAINMASK) {
3915 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3916 }
3917 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3918 *antenna_cfgd = B_TRUE;
3919 break;
3920 case ATH9K_ANT_VARIABLE:
3921 *tx_chainmask = tx_chainmask_cfg;
3922 *rx_chainmask = rx_chainmask_cfg;
3923 *antenna_cfgd = B_TRUE;
3924 break;
3925 default:
3926 break;
3927 }
3928 } else {
3929 ahp->ah_diversityControl = settings;
3930 }
3931
3932 return (B_TRUE);
3933 }
3934
3935 /* General Operation */
3936
3937 uint32_t
ath9k_hw_getrxfilter(struct ath_hal * ah)3938 ath9k_hw_getrxfilter(struct ath_hal *ah)
3939 {
3940 uint32_t bits = REG_READ(ah, AR_RX_FILTER);
3941 uint32_t phybits = REG_READ(ah, AR_PHY_ERR);
3942
3943 if (phybits & AR_PHY_ERR_RADAR)
3944 bits |= ATH9K_RX_FILTER_PHYRADAR;
3945 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3946 bits |= ATH9K_RX_FILTER_PHYERR;
3947
3948 return (bits);
3949 }
3950
3951 void
ath9k_hw_setrxfilter(struct ath_hal * ah,uint32_t bits)3952 ath9k_hw_setrxfilter(struct ath_hal *ah, uint32_t bits)
3953 {
3954 uint32_t phybits;
3955
3956 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3957 phybits = 0;
3958 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3959 phybits |= AR_PHY_ERR_RADAR;
3960 if (bits & ATH9K_RX_FILTER_PHYERR)
3961 phybits |= AR_PHY_ERR_OFDM_TIMING |
3962 AR_PHY_ERR_CCK_TIMING;
3963 REG_WRITE(ah, AR_PHY_ERR, phybits);
3964
3965 if (phybits)
3966 REG_WRITE(ah, AR_RXCFG,
3967 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3968 else
3969 REG_WRITE(ah, AR_RXCFG,
3970 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3971 }
3972
3973 boolean_t
ath9k_hw_phy_disable(struct ath_hal * ah)3974 ath9k_hw_phy_disable(struct ath_hal *ah)
3975 {
3976 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM));
3977 }
3978
3979 boolean_t
ath9k_hw_disable(struct ath_hal * ah)3980 ath9k_hw_disable(struct ath_hal *ah)
3981 {
3982 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3983 return (B_FALSE);
3984
3985 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD));
3986 }
3987
3988 boolean_t
ath9k_hw_set_txpowerlimit(struct ath_hal * ah,uint32_t limit)3989 ath9k_hw_set_txpowerlimit(struct ath_hal *ah, uint32_t limit)
3990 {
3991 struct ath9k_channel *chan = ah->ah_curchan;
3992
3993 /* LINT */
3994 ah->ah_powerLimit = (uint16_t)min(limit, (uint32_t)MAX_RATE_POWER);
3995
3996 if (ath9k_hw_set_txpower(ah, chan,
3997 ath9k_regd_get_ctl(ah, chan),
3998 ath9k_regd_get_antenna_allowed(ah, chan),
3999 chan->maxRegTxPower * 2,
4000 ARN_MIN((uint32_t)MAX_RATE_POWER,
4001 (uint32_t)ah->ah_powerLimit)) != 0)
4002 return (B_FALSE);
4003
4004 return (B_TRUE);
4005 }
4006
4007 void
ath9k_hw_getmac(struct ath_hal * ah,uint8_t * mac)4008 ath9k_hw_getmac(struct ath_hal *ah, uint8_t *mac)
4009 {
4010 struct ath_hal_5416 *ahp = AH5416(ah);
4011
4012 (void) memcpy(mac, ahp->ah_macaddr, 6);
4013 }
4014
4015 boolean_t
ath9k_hw_setmac(struct ath_hal * ah,const uint8_t * mac)4016 ath9k_hw_setmac(struct ath_hal *ah, const uint8_t *mac)
4017 {
4018 struct ath_hal_5416 *ahp = AH5416(ah);
4019
4020 (void) memcpy(ahp->ah_macaddr, mac, 6);
4021
4022 return (B_TRUE);
4023 }
4024
4025 void
ath9k_hw_setopmode(struct ath_hal * ah)4026 ath9k_hw_setopmode(struct ath_hal *ah)
4027 {
4028 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
4029 }
4030
4031 void
ath9k_hw_setmcastfilter(struct ath_hal * ah,uint32_t filter0,uint32_t filter1)4032 ath9k_hw_setmcastfilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
4033 {
4034 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4035 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4036 }
4037
4038 void
ath9k_hw_getbssidmask(struct ath_hal * ah,uint8_t * mask)4039 ath9k_hw_getbssidmask(struct ath_hal *ah, uint8_t *mask)
4040 {
4041 struct ath_hal_5416 *ahp = AH5416(ah);
4042
4043 (void) memcpy(mask, ahp->ah_bssidmask, 6);
4044 }
4045
4046 boolean_t
ath9k_hw_setbssidmask(struct ath_hal * ah,const uint8_t * mask)4047 ath9k_hw_setbssidmask(struct ath_hal *ah, const uint8_t *mask)
4048 {
4049 struct ath_hal_5416 *ahp = AH5416(ah);
4050
4051 (void) memcpy(ahp->ah_bssidmask, mask, 6);
4052
4053 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
4054 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
4055
4056 return (B_TRUE);
4057 }
4058
4059 void
ath9k_hw_write_associd(struct ath_hal * ah,const uint8_t * bssid,uint16_t assocId)4060 ath9k_hw_write_associd(struct ath_hal *ah,
4061 const uint8_t *bssid, uint16_t assocId)
4062 {
4063 struct ath_hal_5416 *ahp = AH5416(ah);
4064
4065 (void) memcpy(ahp->ah_bssid, bssid, 6);
4066 ahp->ah_assocId = assocId;
4067
4068 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
4069 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
4070 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
4071 }
4072
4073 uint64_t
ath9k_hw_gettsf64(struct ath_hal * ah)4074 ath9k_hw_gettsf64(struct ath_hal *ah)
4075 {
4076 uint64_t tsf;
4077
4078 tsf = REG_READ(ah, AR_TSF_U32);
4079 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4080
4081 return (tsf);
4082 }
4083
4084 void
ath9k_hw_reset_tsf(struct ath_hal * ah)4085 ath9k_hw_reset_tsf(struct ath_hal *ah)
4086 {
4087 int count;
4088
4089 count = 0;
4090 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
4091 count++;
4092 if (count > 10) {
4093 ARN_DBG((ARN_DBG_HW, "arn: "
4094 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
4095 __func__));
4096
4097 break;
4098 }
4099 drv_usecwait(10);
4100 }
4101 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4102 }
4103
4104 boolean_t
ath9k_hw_set_tsfadjust(struct ath_hal * ah,uint32_t setting)4105 ath9k_hw_set_tsfadjust(struct ath_hal *ah, uint32_t setting)
4106 {
4107 struct ath_hal_5416 *ahp = AH5416(ah);
4108
4109 if (setting)
4110 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
4111 else
4112 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
4113
4114 return (B_TRUE);
4115 }
4116
4117 boolean_t
ath9k_hw_setslottime(struct ath_hal * ah,uint32_t us)4118 ath9k_hw_setslottime(struct ath_hal *ah, uint32_t us)
4119 {
4120 struct ath_hal_5416 *ahp = AH5416(ah);
4121
4122 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4123 ARN_DBG((ARN_DBG_HW, "arn: "
4124 "%s: bad slot time %u\n", __func__, us));
4125
4126 ahp->ah_slottime = (uint32_t)-1;
4127 return (B_FALSE);
4128 } else {
4129 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4130 ahp->ah_slottime = us;
4131 return (B_TRUE);
4132 }
4133 }
4134
4135 void
ath9k_hw_set11nmac2040(struct ath_hal * ah,enum ath9k_ht_macmode mode)4136 ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
4137 {
4138 uint32_t macmode;
4139
4140 if (mode == ATH9K_HT_MACMODE_2040 &&
4141 !ah->ah_config.cwm_ignore_extcca)
4142 macmode = AR_2040_JOINED_RX_CLEAR;
4143 else
4144 macmode = 0;
4145
4146 REG_WRITE(ah, AR_2040_MODE, macmode);
4147 }
4148