1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_CORE_H
8 #define ATH12K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/firmware.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/panic_notifier.h>
19 #include <linux/average.h>
20 #include <linux/of.h>
21 #include "qmi.h"
22 #include "htc.h"
23 #include "wmi.h"
24 #include "hal.h"
25 #include "dp.h"
26 #include "ce.h"
27 #include "mac.h"
28 #include "hw.h"
29 #include "hal_rx.h"
30 #include "reg.h"
31 #include "dbring.h"
32 #include "fw.h"
33 #include "acpi.h"
34 #include "wow.h"
35 #include "debugfs_htt_stats.h"
36 #include "coredump.h"
37
38 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
39
40 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
41
42 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
43
44 /* Pending management packets threshold for dropping probe responses */
45 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
46
47 /* SMBIOS type containing Board Data File Name Extension */
48 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8
49
50 /* SMBIOS type structure length (excluding strings-set) */
51 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9
52
53 /* The magic used by QCA spec */
54 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_"
55
56 #define ATH12K_INVALID_HW_MAC_ID 0xFF
57 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ)
58
59 #define ATH12K_MON_TIMER_INTERVAL 10
60 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
61 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
62 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
63 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
64 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
65 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
66
67 #define ATH12K_MAX_DEVICES 3
68 #define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_DEVICES * MAX_RADIOS)
69 #define ATH12K_INVALID_GROUP_ID 0xFF
70 #define ATH12K_INVALID_DEVICE_ID 0xFF
71
72 #define ATH12K_MAX_MLO_PEERS 256
73 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF
74
75 enum ath12k_bdf_search {
76 ATH12K_BDF_SEARCH_DEFAULT,
77 ATH12K_BDF_SEARCH_BUS_AND_BOARD,
78 };
79
80 enum wme_ac {
81 WME_AC_BE,
82 WME_AC_BK,
83 WME_AC_VI,
84 WME_AC_VO,
85 WME_NUM_AC
86 };
87
88 #define ATH12K_HT_MCS_MAX 7
89 #define ATH12K_VHT_MCS_MAX 9
90 #define ATH12K_HE_MCS_MAX 11
91 #define ATH12K_EHT_MCS_MAX 15
92
93 enum ath12k_crypt_mode {
94 /* Only use hardware crypto engine */
95 ATH12K_CRYPT_MODE_HW,
96 /* Only use software crypto */
97 ATH12K_CRYPT_MODE_SW,
98 };
99
ath12k_tid_to_ac(u32 tid)100 static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
101 {
102 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
103 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
104 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
105 WME_AC_VO);
106 }
107
ath12k_le32hilo_to_u64(__le32 hi,__le32 lo)108 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo)
109 {
110 u64 hi64 = le32_to_cpu(hi);
111 u64 lo64 = le32_to_cpu(lo);
112
113 return (hi64 << 32) | lo64;
114 }
115
116 enum ath12k_skb_flags {
117 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
118 ATH12K_SKB_CIPHER_SET = BIT(1),
119 ATH12K_SKB_MLO_STA = BIT(2),
120 };
121
122 struct ath12k_skb_cb {
123 dma_addr_t paddr;
124 struct ath12k *ar;
125 struct ieee80211_vif *vif;
126 dma_addr_t paddr_ext_desc;
127 u32 cipher;
128 u8 flags;
129 u8 link_id;
130 };
131
132 struct ath12k_skb_rxcb {
133 dma_addr_t paddr;
134 bool is_first_msdu;
135 bool is_last_msdu;
136 bool is_continuation;
137 bool is_mcbc;
138 bool is_eapol;
139 struct hal_rx_desc *rx_desc;
140 u8 err_rel_src;
141 u8 err_code;
142 u8 hw_link_id;
143 u8 unmapped;
144 u8 is_frag;
145 u8 tid;
146 u16 peer_id;
147 bool is_end_of_ppdu;
148 };
149
150 enum ath12k_hw_rev {
151 ATH12K_HW_QCN9274_HW10,
152 ATH12K_HW_QCN9274_HW20,
153 ATH12K_HW_WCN7850_HW20,
154 ATH12K_HW_IPQ5332_HW10,
155 };
156
157 enum ath12k_firmware_mode {
158 /* the default mode, standard 802.11 functionality */
159 ATH12K_FIRMWARE_MODE_NORMAL,
160
161 /* factory tests etc */
162 ATH12K_FIRMWARE_MODE_FTM,
163 };
164
165 #define ATH12K_IRQ_NUM_MAX 57
166 #define ATH12K_EXT_IRQ_NUM_MAX 16
167 #define ATH12K_MAX_TCL_RING_NUM 3
168
169 struct ath12k_ext_irq_grp {
170 struct ath12k_base *ab;
171 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
172 u32 num_irq;
173 u32 grp_id;
174 u64 timestamp;
175 bool napi_enabled;
176 struct napi_struct napi;
177 struct net_device *napi_ndev;
178 };
179
180 enum ath12k_smbios_cc_type {
181 /* disable country code setting from SMBIOS */
182 ATH12K_SMBIOS_CC_DISABLE = 0,
183
184 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
185 ATH12K_SMBIOS_CC_ISO = 1,
186
187 /* worldwide regdomain */
188 ATH12K_SMBIOS_CC_WW = 2,
189 };
190
191 struct ath12k_smbios_bdf {
192 struct dmi_header hdr;
193 u8 features_disabled;
194
195 /* enum ath12k_smbios_cc_type */
196 u8 country_code_flag;
197
198 /* To set specific country, you need to set country code
199 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United
200 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
201 * 0x53). To set country to INDONESIA, then country code value =
202 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
203 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory
204 * setting.
205 */
206 u16 cc_code;
207
208 u8 bdf_enabled;
209 u8 bdf_ext[];
210 } __packed;
211
212 #define HEHANDLE_CAP_PHYINFO_SIZE 3
213 #define HECAP_PHYINFO_SIZE 9
214 #define HECAP_MACINFO_SIZE 5
215 #define HECAP_TXRX_MCS_NSS_SIZE 2
216 #define HECAP_PPET16_PPET8_MAX_SIZE 25
217
218 #define HE_PPET16_PPET8_SIZE 8
219
220 /* 802.11ax PPE (PPDU packet Extension) threshold */
221 struct he_ppe_threshold {
222 u32 numss_m1;
223 u32 ru_mask;
224 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
225 };
226
227 struct ath12k_he {
228 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
229 u32 hecap_rxmcsnssmap;
230 u32 hecap_txmcsnssmap;
231 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
232 struct he_ppe_threshold hecap_ppet;
233 u32 heop_param;
234 };
235
236 enum {
237 WMI_HOST_TP_SCALE_MAX = 0,
238 WMI_HOST_TP_SCALE_50 = 1,
239 WMI_HOST_TP_SCALE_25 = 2,
240 WMI_HOST_TP_SCALE_12 = 3,
241 WMI_HOST_TP_SCALE_MIN = 4,
242 WMI_HOST_TP_SCALE_SIZE = 5,
243 };
244
245 enum ath12k_scan_state {
246 ATH12K_SCAN_IDLE,
247 ATH12K_SCAN_STARTING,
248 ATH12K_SCAN_RUNNING,
249 ATH12K_SCAN_ABORTING,
250 };
251
252 enum ath12k_11d_state {
253 ATH12K_11D_IDLE,
254 ATH12K_11D_PREPARING,
255 ATH12K_11D_RUNNING,
256 };
257
258 enum ath12k_hw_group_flags {
259 ATH12K_GROUP_FLAG_REGISTERED,
260 ATH12K_GROUP_FLAG_UNREGISTER,
261 };
262
263 enum ath12k_dev_flags {
264 ATH12K_FLAG_CAC_RUNNING,
265 ATH12K_FLAG_CRASH_FLUSH,
266 ATH12K_FLAG_RAW_MODE,
267 ATH12K_FLAG_HW_CRYPTO_DISABLED,
268 ATH12K_FLAG_RECOVERY,
269 ATH12K_FLAG_UNREGISTERING,
270 ATH12K_FLAG_REGISTERED,
271 ATH12K_FLAG_QMI_FAIL,
272 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
273 ATH12K_FLAG_CE_IRQ_ENABLED,
274 ATH12K_FLAG_EXT_IRQ_ENABLED,
275 ATH12K_FLAG_QMI_FW_READY_COMPLETE,
276 ATH12K_FLAG_FTM_SEGMENTED,
277 ATH12K_FLAG_FIXED_MEM_REGION,
278 };
279
280 struct ath12k_tx_conf {
281 bool changed;
282 u16 ac;
283 struct ieee80211_tx_queue_params tx_queue_params;
284 };
285
286 struct ath12k_key_conf {
287 enum set_key_cmd cmd;
288 struct list_head list;
289 struct ieee80211_sta *sta;
290 struct ieee80211_key_conf *key;
291 };
292
293 struct ath12k_vif_cache {
294 struct ath12k_tx_conf tx_conf;
295 struct ath12k_key_conf key_conf;
296 u32 bss_conf_changed;
297 };
298
299 struct ath12k_rekey_data {
300 u8 kck[NL80211_KCK_LEN];
301 u8 kek[NL80211_KCK_LEN];
302 u64 replay_ctr;
303 bool enable_offload;
304 };
305
306 struct ath12k_link_vif {
307 u32 vdev_id;
308 u32 beacon_interval;
309 u32 dtim_period;
310 u16 ast_hash;
311 u16 ast_idx;
312 u16 tcl_metadata;
313 u8 hal_addr_search_flags;
314 u8 search_type;
315
316 struct ath12k *ar;
317
318 int bank_id;
319 u8 vdev_id_check_en;
320 bool beacon_prot;
321
322 struct wmi_wmm_params_all_arg wmm_params;
323 struct list_head list;
324
325 bool is_created;
326 bool is_started;
327 bool is_up;
328 u8 bssid[ETH_ALEN];
329 struct cfg80211_bitrate_mask bitrate_mask;
330 struct delayed_work connection_loss_work;
331 int num_legacy_stations;
332 int rtscts_prot_mode;
333 int txpower;
334 bool rsnie_present;
335 bool wpaie_present;
336 u8 vdev_stats_id;
337 u32 punct_bitmap;
338 u8 link_id;
339 struct ath12k_vif *ahvif;
340 struct ath12k_rekey_data rekey_data;
341 struct ath12k_link_stats link_stats;
342 spinlock_t link_stats_lock; /* Protects updates to link_stats */
343
344 u8 current_cntdown_counter;
345
346 /* only used in station mode */
347 bool is_sta_assoc_link;
348
349 struct ath12k_reg_tpc_power_info reg_tpc_info;
350
351 bool group_key_valid;
352 struct wmi_vdev_install_key_arg group_key;
353 bool pairwise_key_done;
354 u16 num_stations;
355 };
356
357 struct ath12k_vif {
358 enum wmi_vdev_type vdev_type;
359 enum wmi_vdev_subtype vdev_subtype;
360 struct ieee80211_vif *vif;
361 struct ath12k_hw *ah;
362
363 union {
364 struct {
365 u32 uapsd;
366 } sta;
367 struct {
368 /* 127 stations; wmi limit */
369 u8 tim_bitmap[16];
370 u8 tim_len;
371 u32 ssid_len;
372 u8 ssid[IEEE80211_MAX_SSID_LEN];
373 bool hidden_ssid;
374 /* P2P_IE with NoA attribute for P2P_GO case */
375 u32 noa_len;
376 u8 *noa_data;
377 } ap;
378 } u;
379
380 u32 aid;
381 u32 key_cipher;
382 u8 tx_encap_type;
383 bool ps;
384 atomic_t mcbc_gsn;
385
386 struct ath12k_link_vif deflink;
387 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS];
388 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS];
389 /* indicates bitmap of link vif created in FW */
390 u32 links_map;
391 /* Must be last - ends in a flexible-array member.
392 *
393 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
394 * especially because it has a flexible array. Find a better way.
395 */
396 struct ieee80211_chanctx_conf chanctx;
397 };
398
399 struct ath12k_vif_iter {
400 u32 vdev_id;
401 struct ath12k *ar;
402 struct ath12k_link_vif *arvif;
403 };
404
405 #define HAL_AST_IDX_INVALID 0xFFFF
406 #define HAL_RX_MAX_MCS 12
407 #define HAL_RX_MAX_MCS_HT 31
408 #define HAL_RX_MAX_MCS_VHT 9
409 #define HAL_RX_MAX_MCS_HE 11
410 #define HAL_RX_MAX_MCS_BE 15
411 #define HAL_RX_MAX_NSS 8
412 #define HAL_RX_MAX_NUM_LEGACY_RATES 12
413
414 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ)
415
416 struct ath12k_rx_peer_rate_stats {
417 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
418 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
419 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
420 u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1];
421 u64 nss_count[HAL_RX_MAX_NSS];
422 u64 bw_count[HAL_RX_BW_MAX];
423 u64 gi_count[HAL_RX_GI_MAX];
424 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
425 u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1];
426 };
427
428 struct ath12k_rx_peer_stats {
429 u64 num_msdu;
430 u64 num_mpdu_fcs_ok;
431 u64 num_mpdu_fcs_err;
432 u64 tcp_msdu_count;
433 u64 udp_msdu_count;
434 u64 other_msdu_count;
435 u64 ampdu_msdu_count;
436 u64 non_ampdu_msdu_count;
437 u64 stbc_count;
438 u64 beamformed_count;
439 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
440 u64 tid_count[IEEE80211_NUM_TIDS + 1];
441 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
442 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
443 u64 rx_duration;
444 u64 dcm_count;
445 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
446 struct ath12k_rx_peer_rate_stats pkt_stats;
447 struct ath12k_rx_peer_rate_stats byte_stats;
448 };
449
450 #define ATH12K_HE_MCS_NUM 12
451 #define ATH12K_VHT_MCS_NUM 10
452 #define ATH12K_BW_NUM 5
453 #define ATH12K_NSS_NUM 4
454 #define ATH12K_LEGACY_NUM 12
455 #define ATH12K_GI_NUM 4
456 #define ATH12K_HT_MCS_NUM 32
457
458 enum ath12k_pkt_rx_err {
459 ATH12K_PKT_RX_ERR_FCS,
460 ATH12K_PKT_RX_ERR_TKIP,
461 ATH12K_PKT_RX_ERR_CRYPT,
462 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
463 ATH12K_PKT_RX_ERR_MAX,
464 };
465
466 enum ath12k_ampdu_subfrm_num {
467 ATH12K_AMPDU_SUBFRM_NUM_10,
468 ATH12K_AMPDU_SUBFRM_NUM_20,
469 ATH12K_AMPDU_SUBFRM_NUM_30,
470 ATH12K_AMPDU_SUBFRM_NUM_40,
471 ATH12K_AMPDU_SUBFRM_NUM_50,
472 ATH12K_AMPDU_SUBFRM_NUM_60,
473 ATH12K_AMPDU_SUBFRM_NUM_MORE,
474 ATH12K_AMPDU_SUBFRM_NUM_MAX,
475 };
476
477 enum ath12k_amsdu_subfrm_num {
478 ATH12K_AMSDU_SUBFRM_NUM_1,
479 ATH12K_AMSDU_SUBFRM_NUM_2,
480 ATH12K_AMSDU_SUBFRM_NUM_3,
481 ATH12K_AMSDU_SUBFRM_NUM_4,
482 ATH12K_AMSDU_SUBFRM_NUM_MORE,
483 ATH12K_AMSDU_SUBFRM_NUM_MAX,
484 };
485
486 enum ath12k_counter_type {
487 ATH12K_COUNTER_TYPE_BYTES,
488 ATH12K_COUNTER_TYPE_PKTS,
489 ATH12K_COUNTER_TYPE_MAX,
490 };
491
492 enum ath12k_stats_type {
493 ATH12K_STATS_TYPE_SUCC,
494 ATH12K_STATS_TYPE_FAIL,
495 ATH12K_STATS_TYPE_RETRY,
496 ATH12K_STATS_TYPE_AMPDU,
497 ATH12K_STATS_TYPE_MAX,
498 };
499
500 struct ath12k_htt_data_stats {
501 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
502 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
503 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
504 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
505 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
506 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
507 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
508 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
509 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
510 };
511
512 struct ath12k_htt_tx_stats {
513 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
514 u64 tx_duration;
515 u64 ba_fails;
516 u64 ack_fails;
517 u16 ru_start;
518 u16 ru_tones;
519 u32 mu_group[MAX_MU_GROUP_ID];
520 };
521
522 struct ath12k_per_ppdu_tx_stats {
523 u16 succ_pkts;
524 u16 failed_pkts;
525 u16 retry_pkts;
526 u32 succ_bytes;
527 u32 failed_bytes;
528 u32 retry_bytes;
529 };
530
531 struct ath12k_wbm_tx_stats {
532 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
533 };
534
535 DECLARE_EWMA(avg_rssi, 10, 8)
536
537 struct ath12k_link_sta {
538 struct ath12k_link_vif *arvif;
539 struct ath12k_sta *ahsta;
540
541 /* link address similar to ieee80211_link_sta */
542 u8 addr[ETH_ALEN];
543
544 /* the following are protected by ar->data_lock */
545 u32 changed; /* IEEE80211_RC_* */
546 u32 bw;
547 u32 nss;
548 u32 smps;
549
550 struct wiphy_work update_wk;
551 struct rate_info txrate;
552 struct rate_info last_txrate;
553 u64 rx_duration;
554 u64 tx_duration;
555 u8 rssi_comb;
556 struct ewma_avg_rssi avg_rssi;
557 u8 link_id;
558 struct ath12k_rx_peer_stats *rx_stats;
559 struct ath12k_wbm_tx_stats *wbm_tx_stats;
560 u32 bw_prev;
561 u32 peer_nss;
562 s8 rssi_beacon;
563
564 /* For now the assoc link will be considered primary */
565 bool is_assoc_link;
566
567 /* for firmware use only */
568 u8 link_idx;
569 u32 tx_retry_failed;
570 u32 tx_retry_count;
571 };
572
573 struct ath12k_reoq_buf {
574 void *vaddr;
575 dma_addr_t paddr_aligned;
576 u32 size;
577 };
578
579 struct ath12k_sta {
580 struct ath12k_vif *ahvif;
581 enum hal_pn_type pn_type;
582 struct ath12k_link_sta deflink;
583 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
584 /* indicates bitmap of link sta created in FW */
585 u16 links_map;
586 u8 assoc_link_id;
587 u16 ml_peer_id;
588 u8 num_peer;
589
590 enum ieee80211_sta_state state;
591
592 struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1];
593 };
594
595 #define ATH12K_HALF_20MHZ_BW 10
596 #define ATH12K_2GHZ_MIN_CENTER 2412
597 #define ATH12K_2GHZ_MAX_CENTER 2484
598 #define ATH12K_5GHZ_MIN_CENTER 4900
599 #define ATH12K_5GHZ_MAX_CENTER 5920
600 #define ATH12K_6GHZ_MIN_CENTER 5935
601 #define ATH12K_6GHZ_MAX_CENTER 7115
602 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1)
603 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1)
604 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
605 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
606 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
607 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
608 #define ATH12K_NUM_CHANS 101
609 #define ATH12K_MAX_5GHZ_CHAN 173
610
ath12k_is_2ghz_channel_freq(u32 freq)611 static inline bool ath12k_is_2ghz_channel_freq(u32 freq)
612 {
613 return freq >= ATH12K_MIN_2GHZ_FREQ &&
614 freq <= ATH12K_MAX_2GHZ_FREQ;
615 }
616
617 enum ath12k_hw_state {
618 ATH12K_HW_STATE_OFF,
619 ATH12K_HW_STATE_ON,
620 ATH12K_HW_STATE_RESTARTING,
621 ATH12K_HW_STATE_RESTARTED,
622 ATH12K_HW_STATE_WEDGED,
623 ATH12K_HW_STATE_TM,
624 /* Add other states as required */
625 };
626
627 /* Antenna noise floor */
628 #define ATH12K_DEFAULT_NOISE_FLOOR -95
629
630 struct ath12k_ftm_event_obj {
631 u32 data_pos;
632 u32 expected_seq;
633 u8 *eventdata;
634 };
635
636 struct ath12k_fw_stats {
637 u32 pdev_id;
638 u32 stats_id;
639 struct list_head pdevs;
640 struct list_head vdevs;
641 struct list_head bcn;
642 u32 num_vdev_recvd;
643 u32 num_bcn_recvd;
644 };
645
646 struct ath12k_dbg_htt_stats {
647 enum ath12k_dbg_htt_ext_stats_type type;
648 u32 cfg_param[4];
649 u8 reset;
650 struct debug_htt_stats_req *stats_req;
651 };
652
653 struct ath12k_debug {
654 struct dentry *debugfs_pdev;
655 struct dentry *debugfs_pdev_symlink;
656 struct ath12k_dbg_htt_stats htt_stats;
657 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type;
658 bool tpc_request;
659 struct completion tpc_complete;
660 struct wmi_tpc_stats_arg *tpc_stats;
661 u32 rx_filter;
662 bool extd_rx_stats;
663 };
664
665 struct ath12k_per_peer_tx_stats {
666 u32 succ_bytes;
667 u32 retry_bytes;
668 u32 failed_bytes;
669 u32 duration;
670 u16 succ_pkts;
671 u16 retry_pkts;
672 u16 failed_pkts;
673 u16 ru_start;
674 u16 ru_tones;
675 u8 ba_fails;
676 u8 ppdu_type;
677 u32 mu_grpid;
678 u32 mu_pos;
679 bool is_ampdu;
680 };
681
682 struct ath12k_pdev_rssi_offsets {
683 s32 temp_offset;
684 s8 min_nf_dbm;
685 /* Cache the sum here to avoid calculating it every time in hot path
686 * noise_floor = min_nf_dbm + temp_offset
687 */
688 s32 noise_floor;
689 };
690
691 #define ATH12K_FLUSH_TIMEOUT (5 * HZ)
692 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
693
694 struct ath12k {
695 struct ath12k_base *ab;
696 struct ath12k_pdev *pdev;
697 struct ath12k_hw *ah;
698 struct ath12k_wmi_pdev *wmi;
699 struct ath12k_pdev_dp dp;
700 u8 mac_addr[ETH_ALEN];
701 u32 ht_cap_info;
702 u32 vht_cap_info;
703 struct ath12k_he ar_he;
704 bool supports_6ghz;
705 struct {
706 struct completion started;
707 struct completion completed;
708 struct completion on_channel;
709 struct delayed_work timeout;
710 enum ath12k_scan_state state;
711 bool is_roc;
712 int roc_freq;
713 bool roc_notify;
714 struct wiphy_work vdev_clean_wk;
715 struct ath12k_link_vif *arvif;
716 } scan;
717
718 struct {
719 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
720 struct ieee80211_sband_iftype_data
721 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
722 } mac;
723
724 unsigned long dev_flags;
725 unsigned int filter_flags;
726 u32 min_tx_power;
727 u32 max_tx_power;
728 u32 txpower_limit_2g;
729 u32 txpower_limit_5g;
730 u32 txpower_scale;
731 u32 power_scale;
732 u32 chan_tx_pwr;
733 u32 num_stations;
734 u32 max_num_stations;
735
736 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
737 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info,
738 * channel context data, survey info, test mode data, regd_channel_update_queue.
739 */
740 spinlock_t data_lock;
741
742 struct list_head arvifs;
743 /* should never be NULL; needed for regular htt rx */
744 struct ieee80211_channel *rx_channel;
745
746 /* valid during scan; needed for mgmt rx during scan */
747 struct ieee80211_channel *scan_channel;
748
749 u8 cfg_tx_chainmask;
750 u8 cfg_rx_chainmask;
751 u8 num_rx_chains;
752 u8 num_tx_chains;
753 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
754 u8 pdev_idx;
755 u8 lmac_id;
756 u8 hw_link_id;
757
758 struct completion peer_assoc_done;
759 struct completion peer_delete_done;
760
761 int install_key_status;
762 struct completion install_key_done;
763
764 int last_wmi_vdev_start_status;
765 struct completion vdev_setup_done;
766 struct completion vdev_delete_done;
767
768 int num_peers;
769 int max_num_peers;
770 u32 num_started_vdevs;
771 u32 num_created_vdevs;
772 unsigned long long allocated_vdev_map;
773
774 struct idr txmgmt_idr;
775 /* protects txmgmt_idr data */
776 spinlock_t txmgmt_idr_lock;
777 atomic_t num_pending_mgmt_tx;
778 wait_queue_head_t txmgmt_empty_waitq;
779
780 /* cycle count is reported twice for each visited channel during scan.
781 * access protected by data_lock
782 */
783 u32 survey_last_rx_clear_count;
784 u32 survey_last_cycle_count;
785
786 /* Channel info events are expected to come in pairs without and with
787 * COMPLETE flag set respectively for each channel visit during scan.
788 *
789 * However there are deviations from this rule. This flag is used to
790 * avoid reporting garbage data.
791 */
792 bool ch_info_can_report_survey;
793 struct survey_info survey[ATH12K_NUM_CHANS];
794 struct completion bss_survey_done;
795
796 struct work_struct regd_update_work;
797 struct work_struct regd_channel_update_work;
798 struct list_head regd_channel_update_queue;
799
800 struct wiphy_work wmi_mgmt_tx_work;
801 struct sk_buff_head wmi_mgmt_tx_queue;
802
803 struct ath12k_wow wow;
804 struct completion target_suspend;
805 bool target_suspend_ack;
806 struct ath12k_per_peer_tx_stats peer_tx_stats;
807 struct list_head ppdu_stats_info;
808 u32 ppdu_stat_list_depth;
809
810 struct ath12k_per_peer_tx_stats cached_stats;
811 u32 last_ppdu_id;
812 u32 cached_ppdu_id;
813 #ifdef CONFIG_ATH12K_DEBUGFS
814 struct ath12k_debug debug;
815 #endif
816
817 bool dfs_block_radar_events;
818 bool monitor_vdev_created;
819 bool monitor_started;
820 int monitor_vdev_id;
821
822 struct wiphy_radio_freq_range freq_range;
823
824 bool nlo_enabled;
825
826 /* Protected by wiphy::mtx lock. */
827 u32 vdev_id_11d_scan;
828 struct completion completed_11d_scan;
829 enum ath12k_11d_state state_11d;
830 u8 alpha2[REG_ALPHA2_LEN];
831 bool regdom_set_by_user;
832 struct completion regd_update_completed;
833
834 struct completion fw_stats_complete;
835 struct completion fw_stats_done;
836
837 struct completion mlo_setup_done;
838 u32 mlo_setup_status;
839 u8 ftm_msgref;
840 struct ath12k_fw_stats fw_stats;
841 unsigned long last_tx_power_update;
842
843 s8 max_allowed_tx_power;
844 struct ath12k_pdev_rssi_offsets rssi_info;
845 };
846
847 struct ath12k_hw {
848 struct ieee80211_hw *hw;
849 struct device *dev;
850
851 /* Protect the write operation of the hardware state ath12k_hw::state
852 * between hardware start<=>reconfigure<=>stop transitions.
853 */
854 struct mutex hw_mutex;
855 enum ath12k_hw_state state;
856 bool regd_updated;
857 bool use_6ghz_regd;
858
859 u8 num_radio;
860
861 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS);
862
863 /* protected by wiphy_lock() */
864 struct list_head ml_peers;
865
866 /* Keep last */
867 struct ath12k radio[] __aligned(sizeof(void *));
868 };
869
870 struct ath12k_band_cap {
871 u32 phy_id;
872 u32 max_bw_supported;
873 u32 ht_cap_info;
874 u32 he_cap_info[2];
875 u32 he_mcs;
876 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
877 struct ath12k_wmi_ppe_threshold_arg he_ppet;
878 u16 he_6ghz_capa;
879 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
880 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
881 u32 eht_mcs_20_only;
882 u32 eht_mcs_80;
883 u32 eht_mcs_160;
884 u32 eht_mcs_320;
885 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
886 u32 eht_cap_info_internal;
887 };
888
889 struct ath12k_pdev_cap {
890 u32 supported_bands;
891 u32 ampdu_density;
892 u32 vht_cap;
893 u32 vht_mcs;
894 u32 he_mcs;
895 u32 tx_chain_mask;
896 u32 rx_chain_mask;
897 u32 tx_chain_mask_shift;
898 u32 rx_chain_mask_shift;
899 struct ath12k_band_cap band[NUM_NL80211_BANDS];
900 u32 eml_cap;
901 u32 mld_cap;
902 bool nss_ratio_enabled;
903 u8 nss_ratio_info;
904 };
905
906 struct mlo_timestamp {
907 u32 info;
908 u32 sync_timestamp_lo_us;
909 u32 sync_timestamp_hi_us;
910 u32 mlo_offset_lo;
911 u32 mlo_offset_hi;
912 u32 mlo_offset_clks;
913 u32 mlo_comp_clks;
914 u32 mlo_comp_timer;
915 };
916
917 struct ath12k_pdev {
918 struct ath12k *ar;
919 u32 pdev_id;
920 u32 hw_link_id;
921 struct ath12k_pdev_cap cap;
922 u8 mac_addr[ETH_ALEN];
923 struct mlo_timestamp timestamp;
924 };
925
926 struct ath12k_fw_pdev {
927 u32 pdev_id;
928 u32 phy_id;
929 u32 supported_bands;
930 };
931
932 struct ath12k_board_data {
933 const struct firmware *fw;
934 const void *data;
935 size_t len;
936 };
937
938 struct ath12k_device_dp_tx_err_stats {
939 /* TCL Ring Descriptor unavailable */
940 u32 desc_na[DP_TCL_NUM_RING_MAX];
941 /* Other failures during dp_tx due to mem allocation failure
942 * idr unavailable etc.
943 */
944 atomic_t misc_fail;
945 };
946
947 struct ath12k_device_dp_stats {
948 u32 err_ring_pkts;
949 u32 invalid_rbm;
950 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
951 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
952 u32 hal_reo_error[DP_REO_DST_RING_MAX];
953 struct ath12k_device_dp_tx_err_stats tx_err;
954 u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES];
955 u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES];
956 u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON];
957 u32 fw_tx_status[MAX_FW_TX_STATUS];
958 u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX];
959 u32 tx_enqueued[DP_TCL_NUM_RING_MAX];
960 u32 tx_completed[DP_TCL_NUM_RING_MAX];
961 };
962
963 struct ath12k_reg_freq {
964 u32 start_freq;
965 u32 end_freq;
966 };
967
968 struct ath12k_mlo_memory {
969 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
970 int mlo_mem_size;
971 bool init_done;
972 };
973
974 struct ath12k_hw_link {
975 u8 device_id;
976 u8 pdev_idx;
977 };
978
979 /* Holds info on the group of devices that are registered as a single
980 * wiphy, protected with struct ath12k_hw_group::mutex.
981 */
982 struct ath12k_hw_group {
983 struct list_head list;
984 u8 id;
985 u8 num_devices;
986 u8 num_probed;
987 u8 num_started;
988 unsigned long flags;
989 struct ath12k_base *ab[ATH12K_MAX_DEVICES];
990
991 /* protects access to this struct */
992 struct mutex mutex;
993
994 /* Holds information of wiphy (hw) registration.
995 *
996 * In Multi/Single Link Operation case, all pdevs are registered as
997 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is
998 * registered as separate wiphys.
999 */
1000 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO];
1001 u8 num_hw;
1002 bool mlo_capable;
1003 struct device_node *wsi_node[ATH12K_MAX_DEVICES];
1004 struct ath12k_mlo_memory mlo_mem;
1005 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO];
1006 bool hw_link_id_init_done;
1007 };
1008
1009 /* Holds WSI info specific to each device, excluding WSI group info */
1010 struct ath12k_wsi_info {
1011 u32 index;
1012 u32 hw_link_id_base;
1013 };
1014
1015 struct ath12k_dp_profile_params {
1016 u32 tx_comp_ring_size;
1017 u32 rxdma_monitor_buf_ring_size;
1018 u32 rxdma_monitor_dst_ring_size;
1019 u32 num_pool_tx_desc;
1020 u32 rx_desc_count;
1021 };
1022
1023 struct ath12k_mem_profile_based_param {
1024 u32 num_vdevs;
1025 u32 max_client_single;
1026 u32 max_client_dbs;
1027 u32 max_client_dbs_sbs;
1028 struct ath12k_dp_profile_params dp_params;
1029 };
1030
1031 /* Master structure to hold the hw data which may be used in core module */
1032 struct ath12k_base {
1033 enum ath12k_hw_rev hw_rev;
1034 struct platform_device *pdev;
1035 struct device *dev;
1036 struct ath12k_qmi qmi;
1037 struct ath12k_wmi_base wmi_ab;
1038 struct completion fw_ready;
1039 u8 device_id;
1040 int num_radios;
1041 /* HW channel counters frequency value in hertz common to all MACs */
1042 u32 cc_freq_hz;
1043
1044 struct ath12k_dump_file_data *dump_data;
1045 size_t ath12k_coredump_len;
1046 struct work_struct dump_work;
1047
1048 struct ath12k_htc htc;
1049
1050 struct ath12k_dp dp;
1051
1052 void __iomem *mem;
1053 unsigned long mem_len;
1054
1055 void __iomem *mem_ce;
1056 u32 ce_remap_base_addr;
1057 bool ce_remap;
1058
1059 struct {
1060 enum ath12k_bus bus;
1061 const struct ath12k_hif_ops *ops;
1062 } hif;
1063
1064 struct {
1065 struct completion wakeup_completed;
1066 u32 wmi_conf_rx_decap_mode;
1067 } wow;
1068
1069 struct ath12k_ce ce;
1070 struct timer_list rx_replenish_retry;
1071 struct ath12k_hal hal;
1072 /* To synchronize core_start/core_stop */
1073 struct mutex core_lock;
1074 /* Protects data like peers */
1075 spinlock_t base_lock;
1076
1077 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
1078 *
1079 * Firmware maintains data for all bands but advertises a single
1080 * phy to the host which is stored as a single element in this
1081 * array.
1082 *
1083 * Other devices:
1084 *
1085 * This array will contain as many elements as the number of
1086 * radios.
1087 */
1088 struct ath12k_pdev pdevs[MAX_RADIOS];
1089
1090 /* struct ath12k_hw_params::single_pdev_only devices use this to
1091 * store phy specific data
1092 */
1093 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
1094 u8 fw_pdev_count;
1095
1096 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
1097
1098 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
1099 unsigned long long free_vdev_map;
1100 unsigned long long free_vdev_stats_id_map;
1101 struct list_head peers;
1102 wait_queue_head_t peer_mapping_wq;
1103 u8 mac_addr[ETH_ALEN];
1104 bool wmi_ready;
1105 u32 wlan_init_status;
1106 int irq_num[ATH12K_IRQ_NUM_MAX];
1107 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
1108 struct napi_struct *napi;
1109 struct ath12k_wmi_target_cap_arg target_caps;
1110 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
1111 bool pdevs_macaddr_valid;
1112
1113 const struct ath12k_hw_params *hw_params;
1114
1115 const struct firmware *cal_file;
1116
1117 /* Below regd's are protected by ab->data_lock */
1118 /* This is the regd set for every radio
1119 * by the firmware during initialization
1120 */
1121 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
1122 /* This regd is set during dynamic country setting
1123 * This may or may not be used during the runtime
1124 */
1125 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
1126
1127 struct ath12k_reg_info *reg_info[MAX_RADIOS];
1128
1129 /* Current DFS Regulatory */
1130 enum ath12k_dfs_region dfs_region;
1131 struct ath12k_device_dp_stats device_stats;
1132 #ifdef CONFIG_ATH12K_DEBUGFS
1133 struct dentry *debugfs_soc;
1134 #endif
1135
1136 unsigned long dev_flags;
1137 struct completion driver_recovery;
1138 struct workqueue_struct *workqueue;
1139 struct work_struct restart_work;
1140 struct workqueue_struct *workqueue_aux;
1141 struct work_struct reset_work;
1142 atomic_t reset_count;
1143 atomic_t recovery_count;
1144 bool is_reset;
1145 struct completion reset_complete;
1146 /* continuous recovery fail count */
1147 atomic_t fail_cont_count;
1148 unsigned long reset_fail_timeout;
1149 struct work_struct update_11d_work;
1150 u8 new_alpha2[2];
1151 struct {
1152 /* protected by data_lock */
1153 u32 fw_crash_counter;
1154 } stats;
1155 u32 pktlog_defs_checksum;
1156
1157 struct ath12k_dbring_cap *db_caps;
1158 u32 num_db_cap;
1159
1160 struct completion htc_suspend;
1161
1162 u64 fw_soc_drop_count;
1163 bool static_window_map;
1164
1165 struct work_struct rfkill_work;
1166 /* true means radio is on */
1167 bool rfkill_radio_on;
1168
1169 struct {
1170 enum ath12k_bdf_search bdf_search;
1171 u32 vendor;
1172 u32 device;
1173 u32 subsystem_vendor;
1174 u32 subsystem_device;
1175 } id;
1176
1177 struct {
1178 u32 api_version;
1179
1180 const struct firmware *fw;
1181 const u8 *amss_data;
1182 size_t amss_len;
1183 const u8 *amss_dualmac_data;
1184 size_t amss_dualmac_len;
1185 const u8 *m3_data;
1186 size_t m3_len;
1187
1188 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT);
1189 bool fw_features_valid;
1190 } fw;
1191
1192 const struct hal_rx_ops *hal_rx_ops;
1193
1194 struct completion restart_completed;
1195
1196 #ifdef CONFIG_ACPI
1197
1198 struct {
1199 bool started;
1200 u32 func_bit;
1201 bool acpi_tas_enable;
1202 bool acpi_bios_sar_enable;
1203 bool acpi_disable_11be;
1204 bool acpi_disable_rfkill;
1205 bool acpi_cca_enable;
1206 bool acpi_band_edge_enable;
1207 bool acpi_enable_bdf;
1208 u32 bit_flag;
1209 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN];
1210 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE];
1211 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE];
1212 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE];
1213 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE];
1214 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE];
1215 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE];
1216 } acpi;
1217
1218 #endif /* CONFIG_ACPI */
1219
1220 struct notifier_block panic_nb;
1221
1222 struct ath12k_hw_group *ag;
1223 struct ath12k_wsi_info wsi_info;
1224 enum ath12k_firmware_mode fw_mode;
1225 struct ath12k_ftm_event_obj ftm_event_obj;
1226 bool hw_group_ref;
1227
1228 /* Denote whether MLO is possible within the device */
1229 bool single_chip_mlo_support;
1230
1231 struct ath12k_reg_freq reg_freq_2ghz;
1232 struct ath12k_reg_freq reg_freq_5ghz;
1233 struct ath12k_reg_freq reg_freq_6ghz;
1234 const struct ath12k_mem_profile_based_param *profile_param;
1235 enum ath12k_qmi_mem_mode target_mem_mode;
1236
1237 /* must be last */
1238 u8 drv_priv[] __aligned(sizeof(void *));
1239 };
1240
1241 struct ath12k_pdev_map {
1242 struct ath12k_base *ab;
1243 u8 pdev_idx;
1244 };
1245
1246 struct ath12k_fw_stats_vdev {
1247 struct list_head list;
1248
1249 u32 vdev_id;
1250 u32 beacon_snr;
1251 u32 data_snr;
1252 u32 num_tx_frames[WLAN_MAX_AC];
1253 u32 num_rx_frames;
1254 u32 num_tx_frames_retries[WLAN_MAX_AC];
1255 u32 num_tx_frames_failures[WLAN_MAX_AC];
1256 u32 num_rts_fail;
1257 u32 num_rts_success;
1258 u32 num_rx_err;
1259 u32 num_rx_discard;
1260 u32 num_tx_not_acked;
1261 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1262 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1263 };
1264
1265 struct ath12k_fw_stats_bcn {
1266 struct list_head list;
1267
1268 u32 vdev_id;
1269 u32 tx_bcn_succ_cnt;
1270 u32 tx_bcn_outage_cnt;
1271 };
1272
1273 struct ath12k_fw_stats_pdev {
1274 struct list_head list;
1275
1276 /* PDEV stats */
1277 s32 ch_noise_floor;
1278 u32 tx_frame_count;
1279 u32 rx_frame_count;
1280 u32 rx_clear_count;
1281 u32 cycle_count;
1282 u32 phy_err_count;
1283 u32 chan_tx_power;
1284 u32 ack_rx_bad;
1285 u32 rts_bad;
1286 u32 rts_good;
1287 u32 fcs_bad;
1288 u32 no_beacons;
1289 u32 mib_int_count;
1290
1291 /* PDEV TX stats */
1292 s32 comp_queued;
1293 s32 comp_delivered;
1294 s32 msdu_enqued;
1295 s32 mpdu_enqued;
1296 s32 wmm_drop;
1297 s32 local_enqued;
1298 s32 local_freed;
1299 s32 hw_queued;
1300 s32 hw_reaped;
1301 s32 underrun;
1302 s32 tx_abort;
1303 s32 mpdus_requed;
1304 u32 tx_ko;
1305 u32 data_rc;
1306 u32 self_triggers;
1307 u32 sw_retry_failure;
1308 u32 illgl_rate_phy_err;
1309 u32 pdev_cont_xretry;
1310 u32 pdev_tx_timeout;
1311 u32 pdev_resets;
1312 u32 stateless_tid_alloc_failure;
1313 u32 phy_underrun;
1314 u32 txop_ovf;
1315
1316 /* PDEV RX stats */
1317 s32 mid_ppdu_route_change;
1318 s32 status_rcvd;
1319 s32 r0_frags;
1320 s32 r1_frags;
1321 s32 r2_frags;
1322 s32 r3_frags;
1323 s32 htt_msdus;
1324 s32 htt_mpdus;
1325 s32 loc_msdus;
1326 s32 loc_mpdus;
1327 s32 oversize_amsdu;
1328 s32 phy_errs;
1329 s32 phy_err_drop;
1330 s32 mpdu_errs;
1331 };
1332
1333 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
1334 void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag);
1335 int ath12k_core_pre_init(struct ath12k_base *ab);
1336 int ath12k_core_init(struct ath12k_base *ath12k);
1337 void ath12k_core_deinit(struct ath12k_base *ath12k);
1338 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
1339 enum ath12k_bus bus);
1340 void ath12k_core_free(struct ath12k_base *ath12k);
1341 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
1342 struct ath12k_board_data *bd,
1343 char *filename);
1344 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
1345 struct ath12k_board_data *bd);
1346 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
1347 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd);
1348 int ath12k_core_check_dt(struct ath12k_base *ath12k);
1349 int ath12k_core_check_smbios(struct ath12k_base *ab);
1350 void ath12k_core_halt(struct ath12k *ar);
1351 int ath12k_core_resume_early(struct ath12k_base *ab);
1352 int ath12k_core_resume(struct ath12k_base *ab);
1353 int ath12k_core_suspend(struct ath12k_base *ab);
1354 int ath12k_core_suspend_late(struct ath12k_base *ab);
1355 void ath12k_core_hw_group_unassign(struct ath12k_base *ab);
1356 u8 ath12k_get_num_partner_link(struct ath12k *ar);
1357
1358 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
1359 const char *filename);
1360 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab);
1361 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab);
1362
1363 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag);
1364 void ath12k_fw_stats_init(struct ath12k *ar);
1365 void ath12k_fw_stats_bcn_free(struct list_head *head);
1366 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats);
1367 void ath12k_fw_stats_reset(struct ath12k *ar);
1368 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab,
1369 int index);
1370 enum ath12k_qmi_mem_mode ath12k_core_get_memory_mode(struct ath12k_base *ab);
1371
ath12k_scan_state_str(enum ath12k_scan_state state)1372 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
1373 {
1374 switch (state) {
1375 case ATH12K_SCAN_IDLE:
1376 return "idle";
1377 case ATH12K_SCAN_STARTING:
1378 return "starting";
1379 case ATH12K_SCAN_RUNNING:
1380 return "running";
1381 case ATH12K_SCAN_ABORTING:
1382 return "aborting";
1383 }
1384
1385 return "unknown";
1386 }
1387
ATH12K_SKB_CB(struct sk_buff * skb)1388 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
1389 {
1390 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
1391 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1392 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1393 }
1394
ATH12K_SKB_RXCB(struct sk_buff * skb)1395 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
1396 {
1397 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
1398 return (struct ath12k_skb_rxcb *)skb->cb;
1399 }
1400
ath12k_vif_to_ahvif(struct ieee80211_vif * vif)1401 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif)
1402 {
1403 return (struct ath12k_vif *)vif->drv_priv;
1404 }
1405
ath12k_sta_to_ahsta(struct ieee80211_sta * sta)1406 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta)
1407 {
1408 return (struct ath12k_sta *)sta->drv_priv;
1409 }
1410
ath12k_ahsta_to_sta(struct ath12k_sta * ahsta)1411 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta)
1412 {
1413 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv);
1414 }
1415
ath12k_ahvif_to_vif(struct ath12k_vif * ahvif)1416 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif)
1417 {
1418 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv);
1419 }
1420
ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)1421 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
1422 int mac_id)
1423 {
1424 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
1425 }
1426
ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)1427 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
1428 const char *filename,
1429 void *buf, size_t buf_len)
1430 {
1431 const char *fw_name = NULL;
1432
1433 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name);
1434
1435 if (fw_name && strncmp(filename, "board", 5))
1436 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR,
1437 ab->hw_params->fw.dir, fw_name, filename);
1438 else
1439 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
1440 ab->hw_params->fw.dir, filename);
1441 }
1442
ath12k_bus_str(enum ath12k_bus bus)1443 static inline const char *ath12k_bus_str(enum ath12k_bus bus)
1444 {
1445 switch (bus) {
1446 case ATH12K_BUS_PCI:
1447 return "pci";
1448 case ATH12K_BUS_AHB:
1449 return "ahb";
1450 }
1451
1452 return "unknown";
1453 }
1454
ath12k_hw_to_ah(struct ieee80211_hw * hw)1455 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw)
1456 {
1457 return hw->priv;
1458 }
1459
ath12k_ah_to_ar(struct ath12k_hw * ah,u8 hw_link_id)1460 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id)
1461 {
1462 if (WARN(hw_link_id >= ah->num_radio,
1463 "bad hw link id %d, so switch to default link\n", hw_link_id))
1464 hw_link_id = 0;
1465
1466 return &ah->radio[hw_link_id];
1467 }
1468
ath12k_ar_to_ah(struct ath12k * ar)1469 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar)
1470 {
1471 return ar->ah;
1472 }
1473
ath12k_ar_to_hw(struct ath12k * ar)1474 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar)
1475 {
1476 return ar->ah->hw;
1477 }
1478
1479 #define for_each_ar(ah, ar, index) \
1480 for ((index) = 0; ((index) < (ah)->num_radio && \
1481 ((ar) = &(ah)->radio[(index)])); (index)++)
1482
ath12k_ag_to_ah(struct ath12k_hw_group * ag,int idx)1483 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx)
1484 {
1485 return ag->ah[idx];
1486 }
1487
ath12k_ag_set_ah(struct ath12k_hw_group * ag,int idx,struct ath12k_hw * ah)1488 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx,
1489 struct ath12k_hw *ah)
1490 {
1491 ag->ah[idx] = ah;
1492 }
1493
ath12k_ab_to_ag(struct ath12k_base * ab)1494 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab)
1495 {
1496 return ab->ag;
1497 }
1498
ath12k_ag_to_ab(struct ath12k_hw_group * ag,u8 device_id)1499 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag,
1500 u8 device_id)
1501 {
1502 return ag->ab[device_id];
1503 }
1504
ath12k_pdev_get_noise_floor(struct ath12k * ar)1505 static inline s32 ath12k_pdev_get_noise_floor(struct ath12k *ar)
1506 {
1507 lockdep_assert_held(&ar->data_lock);
1508
1509 return ar->rssi_info.noise_floor;
1510 }
1511
1512 #endif /* _CORE_H_ */
1513