xref: /linux/drivers/net/wireless/ath/ath12k/dp_rx.c (revision 1a9239bb4253f9076b5b4b2a1a4e8d7defd77a95)
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "hal_desc.h"
14 #include "hw.h"
15 #include "dp_rx.h"
16 #include "hal_rx.h"
17 #include "dp_tx.h"
18 #include "peer.h"
19 #include "dp_mon.h"
20 #include "debugfs_htt_stats.h"
21 
22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23 
ath12k_dp_rx_h_enctype(struct ath12k_base * ab,struct hal_rx_desc * desc)24 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab,
25 						    struct hal_rx_desc *desc)
26 {
27 	if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc))
28 		return HAL_ENCRYPT_TYPE_OPEN;
29 
30 	return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc);
31 }
32 
ath12k_dp_rx_h_decap_type(struct ath12k_base * ab,struct hal_rx_desc * desc)33 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab,
34 			     struct hal_rx_desc *desc)
35 {
36 	return ab->hal_rx_ops->rx_desc_get_decap_type(desc);
37 }
38 
ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base * ab,struct hal_rx_desc * desc)39 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab,
40 					  struct hal_rx_desc *desc)
41 {
42 	return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc);
43 }
44 
ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)45 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab,
46 					  struct hal_rx_desc *desc)
47 {
48 	return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
49 }
50 
ath12k_dp_rx_h_fc_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)51 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab,
52 				    struct hal_rx_desc *desc)
53 {
54 	return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc);
55 }
56 
ath12k_dp_rx_h_more_frags(struct ath12k_base * ab,struct sk_buff * skb)57 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab,
58 				      struct sk_buff *skb)
59 {
60 	struct ieee80211_hdr *hdr;
61 
62 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
63 	return ieee80211_has_morefrags(hdr->frame_control);
64 }
65 
ath12k_dp_rx_h_frag_no(struct ath12k_base * ab,struct sk_buff * skb)66 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab,
67 				  struct sk_buff *skb)
68 {
69 	struct ieee80211_hdr *hdr;
70 
71 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
72 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
73 }
74 
ath12k_dp_rx_h_seq_no(struct ath12k_base * ab,struct hal_rx_desc * desc)75 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab,
76 				 struct hal_rx_desc *desc)
77 {
78 	return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc);
79 }
80 
ath12k_dp_rx_h_msdu_done(struct ath12k_base * ab,struct hal_rx_desc * desc)81 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab,
82 				     struct hal_rx_desc *desc)
83 {
84 	return ab->hal_rx_ops->dp_rx_h_msdu_done(desc);
85 }
86 
ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)87 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab,
88 					 struct hal_rx_desc *desc)
89 {
90 	return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc);
91 }
92 
ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)93 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab,
94 					 struct hal_rx_desc *desc)
95 {
96 	return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc);
97 }
98 
ath12k_dp_rx_h_is_decrypted(struct ath12k_base * ab,struct hal_rx_desc * desc)99 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab,
100 					struct hal_rx_desc *desc)
101 {
102 	return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc);
103 }
104 
ath12k_dp_rx_h_mpdu_err(struct ath12k_base * ab,struct hal_rx_desc * desc)105 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab,
106 			    struct hal_rx_desc *desc)
107 {
108 	return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc);
109 }
110 
ath12k_dp_rx_h_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc)111 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab,
112 				   struct hal_rx_desc *desc)
113 {
114 	return ab->hal_rx_ops->rx_desc_get_msdu_len(desc);
115 }
116 
ath12k_dp_rx_h_sgi(struct ath12k_base * ab,struct hal_rx_desc * desc)117 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab,
118 			     struct hal_rx_desc *desc)
119 {
120 	return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc);
121 }
122 
ath12k_dp_rx_h_rate_mcs(struct ath12k_base * ab,struct hal_rx_desc * desc)123 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab,
124 				  struct hal_rx_desc *desc)
125 {
126 	return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc);
127 }
128 
ath12k_dp_rx_h_rx_bw(struct ath12k_base * ab,struct hal_rx_desc * desc)129 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab,
130 			       struct hal_rx_desc *desc)
131 {
132 	return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc);
133 }
134 
ath12k_dp_rx_h_freq(struct ath12k_base * ab,struct hal_rx_desc * desc)135 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab,
136 			       struct hal_rx_desc *desc)
137 {
138 	return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc);
139 }
140 
ath12k_dp_rx_h_pkt_type(struct ath12k_base * ab,struct hal_rx_desc * desc)141 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab,
142 				  struct hal_rx_desc *desc)
143 {
144 	return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc);
145 }
146 
ath12k_dp_rx_h_nss(struct ath12k_base * ab,struct hal_rx_desc * desc)147 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab,
148 			     struct hal_rx_desc *desc)
149 {
150 	return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc));
151 }
152 
ath12k_dp_rx_h_tid(struct ath12k_base * ab,struct hal_rx_desc * desc)153 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab,
154 			     struct hal_rx_desc *desc)
155 {
156 	return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc);
157 }
158 
ath12k_dp_rx_h_peer_id(struct ath12k_base * ab,struct hal_rx_desc * desc)159 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab,
160 				  struct hal_rx_desc *desc)
161 {
162 	return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc);
163 }
164 
ath12k_dp_rx_h_l3pad(struct ath12k_base * ab,struct hal_rx_desc * desc)165 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab,
166 			struct hal_rx_desc *desc)
167 {
168 	return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc);
169 }
170 
ath12k_dp_rx_h_first_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)171 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab,
172 				      struct hal_rx_desc *desc)
173 {
174 	return ab->hal_rx_ops->rx_desc_get_first_msdu(desc);
175 }
176 
ath12k_dp_rx_h_last_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)177 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab,
178 				     struct hal_rx_desc *desc)
179 {
180 	return ab->hal_rx_ops->rx_desc_get_last_msdu(desc);
181 }
182 
ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)183 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab,
184 					   struct hal_rx_desc *fdesc,
185 					   struct hal_rx_desc *ldesc)
186 {
187 	ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc);
188 }
189 
ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc,u16 len)190 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab,
191 					  struct hal_rx_desc *desc,
192 					  u16 len)
193 {
194 	ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len);
195 }
196 
ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base * ab,struct hal_rx_desc * desc)197 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab,
198 				      struct hal_rx_desc *desc)
199 {
200 	return (ath12k_dp_rx_h_first_msdu(ab, desc) &&
201 		ab->hal_rx_ops->rx_desc_is_da_mcbc(desc));
202 }
203 
ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)204 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab,
205 					     struct hal_rx_desc *desc)
206 {
207 	return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc);
208 }
209 
ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base * ab,struct hal_rx_desc * desc)210 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab,
211 						 struct hal_rx_desc *desc)
212 {
213 	return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc);
214 }
215 
ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base * ab,struct hal_rx_desc * desc,struct ieee80211_hdr * hdr)216 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab,
217 					    struct hal_rx_desc *desc,
218 					    struct ieee80211_hdr *hdr)
219 {
220 	ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr);
221 }
222 
ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base * ab,struct hal_rx_desc * desc,u8 * crypto_hdr,enum hal_encrypt_type enctype)223 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab,
224 						struct hal_rx_desc *desc,
225 						u8 *crypto_hdr,
226 						enum hal_encrypt_type enctype)
227 {
228 	ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype);
229 }
230 
ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base * ab,struct hal_rx_desc * desc)231 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab,
232 						struct hal_rx_desc *desc)
233 {
234 	return ab->hal_rx_ops->rx_desc_get_mpdu_frame_ctl(desc);
235 }
236 
ath12k_dp_rx_get_msdu_src_link(struct ath12k_base * ab,struct hal_rx_desc * desc)237 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab,
238 						struct hal_rx_desc *desc)
239 {
240 	return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc);
241 }
242 
ath12k_dp_clean_up_skb_list(struct sk_buff_head * skb_list)243 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list)
244 {
245 	struct sk_buff *skb;
246 
247 	while ((skb = __skb_dequeue(skb_list)))
248 		dev_kfree_skb_any(skb);
249 }
250 
ath12k_dp_list_cut_nodes(struct list_head * list,struct list_head * head,size_t count)251 static size_t ath12k_dp_list_cut_nodes(struct list_head *list,
252 				       struct list_head *head,
253 				       size_t count)
254 {
255 	struct list_head *cur;
256 	struct ath12k_rx_desc_info *rx_desc;
257 	size_t nodes = 0;
258 
259 	if (!count) {
260 		INIT_LIST_HEAD(list);
261 		goto out;
262 	}
263 
264 	list_for_each(cur, head) {
265 		if (!count)
266 			break;
267 
268 		rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list);
269 		rx_desc->in_use = true;
270 
271 		count--;
272 		nodes++;
273 	}
274 
275 	list_cut_before(list, head, cur);
276 out:
277 	return nodes;
278 }
279 
ath12k_dp_rx_enqueue_free(struct ath12k_dp * dp,struct list_head * used_list)280 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp,
281 				      struct list_head *used_list)
282 {
283 	struct ath12k_rx_desc_info *rx_desc, *safe;
284 
285 	/* Reset the use flag */
286 	list_for_each_entry_safe(rx_desc, safe, used_list, list)
287 		rx_desc->in_use = false;
288 
289 	spin_lock_bh(&dp->rx_desc_lock);
290 	list_splice_tail(used_list, &dp->rx_desc_free_list);
291 	spin_unlock_bh(&dp->rx_desc_lock);
292 }
293 
294 /* Returns number of Rx buffers replenished */
ath12k_dp_rx_bufs_replenish(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring,struct list_head * used_list,int req_entries)295 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab,
296 				struct dp_rxdma_ring *rx_ring,
297 				struct list_head *used_list,
298 				int req_entries)
299 {
300 	struct ath12k_buffer_addr *desc;
301 	struct hal_srng *srng;
302 	struct sk_buff *skb;
303 	int num_free;
304 	int num_remain;
305 	u32 cookie;
306 	dma_addr_t paddr;
307 	struct ath12k_dp *dp = &ab->dp;
308 	struct ath12k_rx_desc_info *rx_desc;
309 	enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm;
310 
311 	req_entries = min(req_entries, rx_ring->bufs_max);
312 
313 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
314 
315 	spin_lock_bh(&srng->lock);
316 
317 	ath12k_hal_srng_access_begin(ab, srng);
318 
319 	num_free = ath12k_hal_srng_src_num_free(ab, srng, true);
320 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
321 		req_entries = num_free;
322 
323 	req_entries = min(num_free, req_entries);
324 	num_remain = req_entries;
325 
326 	if (!num_remain)
327 		goto out;
328 
329 	/* Get the descriptor from free list */
330 	if (list_empty(used_list)) {
331 		spin_lock_bh(&dp->rx_desc_lock);
332 		req_entries = ath12k_dp_list_cut_nodes(used_list,
333 						       &dp->rx_desc_free_list,
334 						       num_remain);
335 		spin_unlock_bh(&dp->rx_desc_lock);
336 		num_remain = req_entries;
337 	}
338 
339 	while (num_remain > 0) {
340 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
341 				    DP_RX_BUFFER_ALIGN_SIZE);
342 		if (!skb)
343 			break;
344 
345 		if (!IS_ALIGNED((unsigned long)skb->data,
346 				DP_RX_BUFFER_ALIGN_SIZE)) {
347 			skb_pull(skb,
348 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
349 				 skb->data);
350 		}
351 
352 		paddr = dma_map_single(ab->dev, skb->data,
353 				       skb->len + skb_tailroom(skb),
354 				       DMA_FROM_DEVICE);
355 		if (dma_mapping_error(ab->dev, paddr))
356 			goto fail_free_skb;
357 
358 		rx_desc = list_first_entry_or_null(used_list,
359 						   struct ath12k_rx_desc_info,
360 						   list);
361 		if (!rx_desc)
362 			goto fail_dma_unmap;
363 
364 		rx_desc->skb = skb;
365 		cookie = rx_desc->cookie;
366 
367 		desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
368 		if (!desc)
369 			goto fail_dma_unmap;
370 
371 		list_del(&rx_desc->list);
372 		ATH12K_SKB_RXCB(skb)->paddr = paddr;
373 
374 		num_remain--;
375 
376 		ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
377 	}
378 
379 	goto out;
380 
381 fail_dma_unmap:
382 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
383 			 DMA_FROM_DEVICE);
384 fail_free_skb:
385 	dev_kfree_skb_any(skb);
386 out:
387 	ath12k_hal_srng_access_end(ab, srng);
388 
389 	if (!list_empty(used_list))
390 		ath12k_dp_rx_enqueue_free(dp, used_list);
391 
392 	spin_unlock_bh(&srng->lock);
393 
394 	return req_entries - num_remain;
395 }
396 
ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring)397 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab,
398 					     struct dp_rxdma_mon_ring *rx_ring)
399 {
400 	struct sk_buff *skb;
401 	int buf_id;
402 
403 	spin_lock_bh(&rx_ring->idr_lock);
404 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
405 		idr_remove(&rx_ring->bufs_idr, buf_id);
406 		/* TODO: Understand where internal driver does this dma_unmap
407 		 * of rxdma_buffer.
408 		 */
409 		dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
410 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
411 		dev_kfree_skb_any(skb);
412 	}
413 
414 	idr_destroy(&rx_ring->bufs_idr);
415 	spin_unlock_bh(&rx_ring->idr_lock);
416 
417 	return 0;
418 }
419 
ath12k_dp_rxdma_buf_free(struct ath12k_base * ab)420 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab)
421 {
422 	struct ath12k_dp *dp = &ab->dp;
423 
424 	ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring);
425 
426 	return 0;
427 }
428 
ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring,u32 ringtype)429 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab,
430 					      struct dp_rxdma_mon_ring *rx_ring,
431 					      u32 ringtype)
432 {
433 	int num_entries;
434 
435 	num_entries = rx_ring->refill_buf_ring.size /
436 		ath12k_hal_srng_get_entrysize(ab, ringtype);
437 
438 	rx_ring->bufs_max = num_entries;
439 	ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries);
440 
441 	return 0;
442 }
443 
ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring)444 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab,
445 					  struct dp_rxdma_ring *rx_ring)
446 {
447 	LIST_HEAD(list);
448 
449 	rx_ring->bufs_max = rx_ring->refill_buf_ring.size /
450 			ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF);
451 
452 	ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
453 
454 	return 0;
455 }
456 
ath12k_dp_rxdma_buf_setup(struct ath12k_base * ab)457 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab)
458 {
459 	struct ath12k_dp *dp = &ab->dp;
460 	int ret;
461 
462 	ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring);
463 	if (ret) {
464 		ath12k_warn(ab,
465 			    "failed to setup HAL_RXDMA_BUF\n");
466 		return ret;
467 	}
468 
469 	if (ab->hw_params->rxdma1_enable) {
470 		ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab,
471 							 &dp->rxdma_mon_buf_ring,
472 							 HAL_RXDMA_MONITOR_BUF);
473 		if (ret) {
474 			ath12k_warn(ab,
475 				    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
476 			return ret;
477 		}
478 	}
479 
480 	return 0;
481 }
482 
ath12k_dp_rx_pdev_srng_free(struct ath12k * ar)483 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar)
484 {
485 	struct ath12k_pdev_dp *dp = &ar->dp;
486 	struct ath12k_base *ab = ar->ab;
487 	int i;
488 
489 	for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++)
490 		ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]);
491 }
492 
ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base * ab)493 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab)
494 {
495 	struct ath12k_dp *dp = &ab->dp;
496 	int i;
497 
498 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
499 		ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
500 }
501 
ath12k_dp_rx_pdev_reo_setup(struct ath12k_base * ab)502 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab)
503 {
504 	struct ath12k_dp *dp = &ab->dp;
505 	int ret;
506 	int i;
507 
508 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
509 		ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
510 					   HAL_REO_DST, i, 0,
511 					   DP_REO_DST_RING_SIZE);
512 		if (ret) {
513 			ath12k_warn(ab, "failed to setup reo_dst_ring\n");
514 			goto err_reo_cleanup;
515 		}
516 	}
517 
518 	return 0;
519 
520 err_reo_cleanup:
521 	ath12k_dp_rx_pdev_reo_cleanup(ab);
522 
523 	return ret;
524 }
525 
ath12k_dp_rx_pdev_srng_alloc(struct ath12k * ar)526 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar)
527 {
528 	struct ath12k_pdev_dp *dp = &ar->dp;
529 	struct ath12k_base *ab = ar->ab;
530 	int i;
531 	int ret;
532 	u32 mac_id = dp->mac_id;
533 
534 	for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
535 		ret = ath12k_dp_srng_setup(ar->ab,
536 					   &dp->rxdma_mon_dst_ring[i],
537 					   HAL_RXDMA_MONITOR_DST,
538 					   0, mac_id + i,
539 					   DP_RXDMA_MONITOR_DST_RING_SIZE);
540 		if (ret) {
541 			ath12k_warn(ar->ab,
542 				    "failed to setup HAL_RXDMA_MONITOR_DST\n");
543 			return ret;
544 		}
545 	}
546 
547 	return 0;
548 }
549 
ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base * ab)550 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab)
551 {
552 	struct ath12k_dp *dp = &ab->dp;
553 	struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
554 	struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache;
555 
556 	spin_lock_bh(&dp->reo_cmd_lock);
557 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
558 		list_del(&cmd->list);
559 		dma_unmap_single(ab->dev, cmd->data.paddr,
560 				 cmd->data.size, DMA_BIDIRECTIONAL);
561 		kfree(cmd->data.vaddr);
562 		kfree(cmd);
563 	}
564 
565 	list_for_each_entry_safe(cmd_cache, tmp_cache,
566 				 &dp->reo_cmd_cache_flush_list, list) {
567 		list_del(&cmd_cache->list);
568 		dp->reo_cmd_cache_flush_count--;
569 		dma_unmap_single(ab->dev, cmd_cache->data.paddr,
570 				 cmd_cache->data.size, DMA_BIDIRECTIONAL);
571 		kfree(cmd_cache->data.vaddr);
572 		kfree(cmd_cache);
573 	}
574 	spin_unlock_bh(&dp->reo_cmd_lock);
575 }
576 
ath12k_dp_reo_cmd_free(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)577 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx,
578 				   enum hal_reo_cmd_status status)
579 {
580 	struct ath12k_dp_rx_tid *rx_tid = ctx;
581 
582 	if (status != HAL_REO_CMD_SUCCESS)
583 		ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
584 			    rx_tid->tid, status);
585 
586 	dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
587 			 DMA_BIDIRECTIONAL);
588 	kfree(rx_tid->vaddr);
589 	rx_tid->vaddr = NULL;
590 }
591 
ath12k_dp_reo_cmd_send(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid,enum hal_reo_cmd_type type,struct ath12k_hal_reo_cmd * cmd,void (* cb)(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status))592 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid,
593 				  enum hal_reo_cmd_type type,
594 				  struct ath12k_hal_reo_cmd *cmd,
595 				  void (*cb)(struct ath12k_dp *dp, void *ctx,
596 					     enum hal_reo_cmd_status status))
597 {
598 	struct ath12k_dp *dp = &ab->dp;
599 	struct ath12k_dp_rx_reo_cmd *dp_cmd;
600 	struct hal_srng *cmd_ring;
601 	int cmd_num;
602 
603 	cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
604 	cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
605 
606 	/* cmd_num should start from 1, during failure return the error code */
607 	if (cmd_num < 0)
608 		return cmd_num;
609 
610 	/* reo cmd ring descriptors has cmd_num starting from 1 */
611 	if (cmd_num == 0)
612 		return -EINVAL;
613 
614 	if (!cb)
615 		return 0;
616 
617 	/* Can this be optimized so that we keep the pending command list only
618 	 * for tid delete command to free up the resource on the command status
619 	 * indication?
620 	 */
621 	dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
622 
623 	if (!dp_cmd)
624 		return -ENOMEM;
625 
626 	memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid));
627 	dp_cmd->cmd_num = cmd_num;
628 	dp_cmd->handler = cb;
629 
630 	spin_lock_bh(&dp->reo_cmd_lock);
631 	list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
632 	spin_unlock_bh(&dp->reo_cmd_lock);
633 
634 	return 0;
635 }
636 
ath12k_dp_reo_cache_flush(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid)637 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab,
638 				      struct ath12k_dp_rx_tid *rx_tid)
639 {
640 	struct ath12k_hal_reo_cmd cmd = {0};
641 	unsigned long tot_desc_sz, desc_sz;
642 	int ret;
643 
644 	tot_desc_sz = rx_tid->size;
645 	desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
646 
647 	while (tot_desc_sz > desc_sz) {
648 		tot_desc_sz -= desc_sz;
649 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
650 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
651 		ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
652 					     HAL_REO_CMD_FLUSH_CACHE, &cmd,
653 					     NULL);
654 		if (ret)
655 			ath12k_warn(ab,
656 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
657 				    rx_tid->tid, ret);
658 	}
659 
660 	memset(&cmd, 0, sizeof(cmd));
661 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
662 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
663 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
664 	ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
665 				     HAL_REO_CMD_FLUSH_CACHE,
666 				     &cmd, ath12k_dp_reo_cmd_free);
667 	if (ret) {
668 		ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
669 			   rx_tid->tid, ret);
670 		dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
671 				 DMA_BIDIRECTIONAL);
672 		kfree(rx_tid->vaddr);
673 		rx_tid->vaddr = NULL;
674 	}
675 }
676 
ath12k_dp_rx_tid_del_func(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)677 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx,
678 				      enum hal_reo_cmd_status status)
679 {
680 	struct ath12k_base *ab = dp->ab;
681 	struct ath12k_dp_rx_tid *rx_tid = ctx;
682 	struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp;
683 
684 	if (status == HAL_REO_CMD_DRAIN) {
685 		goto free_desc;
686 	} else if (status != HAL_REO_CMD_SUCCESS) {
687 		/* Shouldn't happen! Cleanup in case of other failure? */
688 		ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
689 			    rx_tid->tid, status);
690 		return;
691 	}
692 
693 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
694 	if (!elem)
695 		goto free_desc;
696 
697 	elem->ts = jiffies;
698 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
699 
700 	spin_lock_bh(&dp->reo_cmd_lock);
701 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
702 	dp->reo_cmd_cache_flush_count++;
703 
704 	/* Flush and invalidate aged REO desc from HW cache */
705 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
706 				 list) {
707 		if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES ||
708 		    time_after(jiffies, elem->ts +
709 			       msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) {
710 			list_del(&elem->list);
711 			dp->reo_cmd_cache_flush_count--;
712 
713 			/* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send()
714 			 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list
715 			 * is used in only two contexts, one is in this function called
716 			 * from napi and the other in ath12k_dp_free during core destroy.
717 			 * Before dp_free, the irqs would be disabled and would wait to
718 			 * synchronize. Hence there wouldn’t be any race against add or
719 			 * delete to this list. Hence unlock-lock is safe here.
720 			 */
721 			spin_unlock_bh(&dp->reo_cmd_lock);
722 
723 			ath12k_dp_reo_cache_flush(ab, &elem->data);
724 			kfree(elem);
725 			spin_lock_bh(&dp->reo_cmd_lock);
726 		}
727 	}
728 	spin_unlock_bh(&dp->reo_cmd_lock);
729 
730 	return;
731 free_desc:
732 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
733 			 DMA_BIDIRECTIONAL);
734 	kfree(rx_tid->vaddr);
735 	rx_tid->vaddr = NULL;
736 }
737 
ath12k_peer_rx_tid_qref_setup(struct ath12k_base * ab,u16 peer_id,u16 tid,dma_addr_t paddr)738 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid,
739 					  dma_addr_t paddr)
740 {
741 	struct ath12k_reo_queue_ref *qref;
742 	struct ath12k_dp *dp = &ab->dp;
743 	bool ml_peer = false;
744 
745 	if (!ab->hw_params->reoq_lut_support)
746 		return;
747 
748 	if (peer_id & ATH12K_PEER_ML_ID_VALID) {
749 		peer_id &= ~ATH12K_PEER_ML_ID_VALID;
750 		ml_peer = true;
751 	}
752 
753 	if (ml_peer)
754 		qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr +
755 				(peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
756 	else
757 		qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
758 				(peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
759 
760 	qref->info0 = u32_encode_bits(lower_32_bits(paddr),
761 				      BUFFER_ADDR_INFO0_ADDR);
762 	qref->info1 = u32_encode_bits(upper_32_bits(paddr),
763 				      BUFFER_ADDR_INFO1_ADDR) |
764 		      u32_encode_bits(tid, DP_REO_QREF_NUM);
765 }
766 
ath12k_peer_rx_tid_qref_reset(struct ath12k_base * ab,u16 peer_id,u16 tid)767 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid)
768 {
769 	struct ath12k_reo_queue_ref *qref;
770 	struct ath12k_dp *dp = &ab->dp;
771 	bool ml_peer = false;
772 
773 	if (!ab->hw_params->reoq_lut_support)
774 		return;
775 
776 	if (peer_id & ATH12K_PEER_ML_ID_VALID) {
777 		peer_id &= ~ATH12K_PEER_ML_ID_VALID;
778 		ml_peer = true;
779 	}
780 
781 	if (ml_peer)
782 		qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr +
783 				(peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
784 	else
785 		qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
786 				(peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
787 
788 	qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR);
789 	qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) |
790 		      u32_encode_bits(tid, DP_REO_QREF_NUM);
791 }
792 
ath12k_dp_rx_peer_tid_delete(struct ath12k * ar,struct ath12k_peer * peer,u8 tid)793 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar,
794 				  struct ath12k_peer *peer, u8 tid)
795 {
796 	struct ath12k_hal_reo_cmd cmd = {0};
797 	struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid];
798 	int ret;
799 
800 	if (!rx_tid->active)
801 		return;
802 
803 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
804 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
805 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
806 	cmd.upd0 = HAL_REO_CMD_UPD0_VLD;
807 	ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
808 				     HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
809 				     ath12k_dp_rx_tid_del_func);
810 	if (ret) {
811 		ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
812 			   tid, ret);
813 		dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
814 				 DMA_BIDIRECTIONAL);
815 		kfree(rx_tid->vaddr);
816 		rx_tid->vaddr = NULL;
817 	}
818 
819 	if (peer->mlo)
820 		ath12k_peer_rx_tid_qref_reset(ar->ab, peer->ml_id, tid);
821 	else
822 		ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid);
823 
824 	rx_tid->active = false;
825 }
826 
827 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted
828  * to struct hal_wbm_release_ring, I couldn't figure out the logic behind
829  * that.
830  */
ath12k_dp_rx_link_desc_return(struct ath12k_base * ab,struct hal_reo_dest_ring * ring,enum hal_wbm_rel_bm_act action)831 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab,
832 					 struct hal_reo_dest_ring *ring,
833 					 enum hal_wbm_rel_bm_act action)
834 {
835 	struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring;
836 	struct hal_wbm_release_ring *desc;
837 	struct ath12k_dp *dp = &ab->dp;
838 	struct hal_srng *srng;
839 	int ret = 0;
840 
841 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
842 
843 	spin_lock_bh(&srng->lock);
844 
845 	ath12k_hal_srng_access_begin(ab, srng);
846 
847 	desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
848 	if (!desc) {
849 		ret = -ENOBUFS;
850 		goto exit;
851 	}
852 
853 	ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action);
854 
855 exit:
856 	ath12k_hal_srng_access_end(ab, srng);
857 
858 	spin_unlock_bh(&srng->lock);
859 
860 	return ret;
861 }
862 
ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid * rx_tid,bool rel_link_desc)863 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid,
864 				       bool rel_link_desc)
865 {
866 	struct ath12k_base *ab = rx_tid->ab;
867 
868 	lockdep_assert_held(&ab->base_lock);
869 
870 	if (rx_tid->dst_ring_desc) {
871 		if (rel_link_desc)
872 			ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc,
873 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
874 		kfree(rx_tid->dst_ring_desc);
875 		rx_tid->dst_ring_desc = NULL;
876 	}
877 
878 	rx_tid->cur_sn = 0;
879 	rx_tid->last_frag_no = 0;
880 	rx_tid->rx_frag_bitmap = 0;
881 	__skb_queue_purge(&rx_tid->rx_frags);
882 }
883 
ath12k_dp_rx_peer_tid_cleanup(struct ath12k * ar,struct ath12k_peer * peer)884 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer)
885 {
886 	struct ath12k_dp_rx_tid *rx_tid;
887 	int i;
888 
889 	lockdep_assert_held(&ar->ab->base_lock);
890 
891 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
892 		rx_tid = &peer->rx_tid[i];
893 
894 		ath12k_dp_rx_peer_tid_delete(ar, peer, i);
895 		ath12k_dp_rx_frags_cleanup(rx_tid, true);
896 
897 		spin_unlock_bh(&ar->ab->base_lock);
898 		del_timer_sync(&rx_tid->frag_timer);
899 		spin_lock_bh(&ar->ab->base_lock);
900 	}
901 }
902 
ath12k_peer_rx_tid_reo_update(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)903 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar,
904 					 struct ath12k_peer *peer,
905 					 struct ath12k_dp_rx_tid *rx_tid,
906 					 u32 ba_win_sz, u16 ssn,
907 					 bool update_ssn)
908 {
909 	struct ath12k_hal_reo_cmd cmd = {0};
910 	int ret;
911 
912 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
913 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
914 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
915 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
916 	cmd.ba_window_size = ba_win_sz;
917 
918 	if (update_ssn) {
919 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
920 		cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN);
921 	}
922 
923 	ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
924 				     HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
925 				     NULL);
926 	if (ret) {
927 		ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
928 			    rx_tid->tid, ret);
929 		return ret;
930 	}
931 
932 	rx_tid->ba_win_sz = ba_win_sz;
933 
934 	return 0;
935 }
936 
ath12k_dp_rx_peer_tid_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)937 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id,
938 				u8 tid, u32 ba_win_sz, u16 ssn,
939 				enum hal_pn_type pn_type)
940 {
941 	struct ath12k_base *ab = ar->ab;
942 	struct ath12k_dp *dp = &ab->dp;
943 	struct hal_rx_reo_queue *addr_aligned;
944 	struct ath12k_peer *peer;
945 	struct ath12k_dp_rx_tid *rx_tid;
946 	u32 hw_desc_sz;
947 	void *vaddr;
948 	dma_addr_t paddr;
949 	int ret;
950 
951 	spin_lock_bh(&ab->base_lock);
952 
953 	peer = ath12k_peer_find(ab, vdev_id, peer_mac);
954 	if (!peer) {
955 		spin_unlock_bh(&ab->base_lock);
956 		ath12k_warn(ab, "failed to find the peer to set up rx tid\n");
957 		return -ENOENT;
958 	}
959 
960 	if (!peer->primary_link) {
961 		spin_unlock_bh(&ab->base_lock);
962 		return 0;
963 	}
964 
965 	if (ab->hw_params->reoq_lut_support &&
966 	    (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) {
967 		spin_unlock_bh(&ab->base_lock);
968 		ath12k_warn(ab, "reo qref table is not setup\n");
969 		return -EINVAL;
970 	}
971 
972 	if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) {
973 		ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n",
974 			    peer->peer_id, tid);
975 		spin_unlock_bh(&ab->base_lock);
976 		return -EINVAL;
977 	}
978 
979 	rx_tid = &peer->rx_tid[tid];
980 	/* Update the tid queue if it is already setup */
981 	if (rx_tid->active) {
982 		paddr = rx_tid->paddr;
983 		ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid,
984 						    ba_win_sz, ssn, true);
985 		spin_unlock_bh(&ab->base_lock);
986 		if (ret) {
987 			ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid);
988 			return ret;
989 		}
990 
991 		if (!ab->hw_params->reoq_lut_support) {
992 			ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
993 								     peer_mac,
994 								     paddr, tid, 1,
995 								     ba_win_sz);
996 			if (ret) {
997 				ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n",
998 					    tid, ret);
999 				return ret;
1000 			}
1001 		}
1002 
1003 		return 0;
1004 	}
1005 
1006 	rx_tid->tid = tid;
1007 
1008 	rx_tid->ba_win_sz = ba_win_sz;
1009 
1010 	/* TODO: Optimize the memory allocation for qos tid based on
1011 	 * the actual BA window size in REO tid update path.
1012 	 */
1013 	if (tid == HAL_DESC_REO_NON_QOS_TID)
1014 		hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid);
1015 	else
1016 		hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1017 
1018 	vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1019 	if (!vaddr) {
1020 		spin_unlock_bh(&ab->base_lock);
1021 		return -ENOMEM;
1022 	}
1023 
1024 	addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1025 
1026 	ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1027 				   ssn, pn_type);
1028 
1029 	paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1030 			       DMA_BIDIRECTIONAL);
1031 
1032 	ret = dma_mapping_error(ab->dev, paddr);
1033 	if (ret) {
1034 		spin_unlock_bh(&ab->base_lock);
1035 		goto err_mem_free;
1036 	}
1037 
1038 	rx_tid->vaddr = vaddr;
1039 	rx_tid->paddr = paddr;
1040 	rx_tid->size = hw_desc_sz;
1041 	rx_tid->active = true;
1042 
1043 	if (ab->hw_params->reoq_lut_support) {
1044 		/* Update the REO queue LUT at the corresponding peer id
1045 		 * and tid with qaddr.
1046 		 */
1047 		if (peer->mlo)
1048 			ath12k_peer_rx_tid_qref_setup(ab, peer->ml_id, tid, paddr);
1049 		else
1050 			ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr);
1051 
1052 		spin_unlock_bh(&ab->base_lock);
1053 	} else {
1054 		spin_unlock_bh(&ab->base_lock);
1055 		ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1056 							     paddr, tid, 1, ba_win_sz);
1057 	}
1058 
1059 	return ret;
1060 
1061 err_mem_free:
1062 	kfree(vaddr);
1063 
1064 	return ret;
1065 }
1066 
ath12k_dp_rx_ampdu_start(struct ath12k * ar,struct ieee80211_ampdu_params * params,u8 link_id)1067 int ath12k_dp_rx_ampdu_start(struct ath12k *ar,
1068 			     struct ieee80211_ampdu_params *params,
1069 			     u8 link_id)
1070 {
1071 	struct ath12k_base *ab = ar->ab;
1072 	struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta);
1073 	struct ath12k_link_sta *arsta;
1074 	int vdev_id;
1075 	int ret;
1076 
1077 	lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy);
1078 
1079 	arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy,
1080 				  ahsta->link[link_id]);
1081 	if (!arsta)
1082 		return -ENOLINK;
1083 
1084 	vdev_id = arsta->arvif->vdev_id;
1085 
1086 	ret = ath12k_dp_rx_peer_tid_setup(ar, arsta->addr, vdev_id,
1087 					  params->tid, params->buf_size,
1088 					  params->ssn, arsta->ahsta->pn_type);
1089 	if (ret)
1090 		ath12k_warn(ab, "failed to setup rx tid %d\n", ret);
1091 
1092 	return ret;
1093 }
1094 
ath12k_dp_rx_ampdu_stop(struct ath12k * ar,struct ieee80211_ampdu_params * params,u8 link_id)1095 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar,
1096 			    struct ieee80211_ampdu_params *params,
1097 			    u8 link_id)
1098 {
1099 	struct ath12k_base *ab = ar->ab;
1100 	struct ath12k_peer *peer;
1101 	struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta);
1102 	struct ath12k_link_sta *arsta;
1103 	int vdev_id;
1104 	bool active;
1105 	int ret;
1106 
1107 	lockdep_assert_wiphy(ath12k_ar_to_hw(ar)->wiphy);
1108 
1109 	arsta = wiphy_dereference(ath12k_ar_to_hw(ar)->wiphy,
1110 				  ahsta->link[link_id]);
1111 	if (!arsta)
1112 		return -ENOLINK;
1113 
1114 	vdev_id = arsta->arvif->vdev_id;
1115 
1116 	spin_lock_bh(&ab->base_lock);
1117 
1118 	peer = ath12k_peer_find(ab, vdev_id, arsta->addr);
1119 	if (!peer) {
1120 		spin_unlock_bh(&ab->base_lock);
1121 		ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1122 		return -ENOENT;
1123 	}
1124 
1125 	active = peer->rx_tid[params->tid].active;
1126 
1127 	if (!active) {
1128 		spin_unlock_bh(&ab->base_lock);
1129 		return 0;
1130 	}
1131 
1132 	ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1133 	spin_unlock_bh(&ab->base_lock);
1134 	if (ret) {
1135 		ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1136 			    params->tid, ret);
1137 		return ret;
1138 	}
1139 
1140 	return ret;
1141 }
1142 
ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1143 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif,
1144 				       const u8 *peer_addr,
1145 				       enum set_key_cmd key_cmd,
1146 				       struct ieee80211_key_conf *key)
1147 {
1148 	struct ath12k *ar = arvif->ar;
1149 	struct ath12k_base *ab = ar->ab;
1150 	struct ath12k_hal_reo_cmd cmd = {0};
1151 	struct ath12k_peer *peer;
1152 	struct ath12k_dp_rx_tid *rx_tid;
1153 	u8 tid;
1154 	int ret = 0;
1155 
1156 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1157 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1158 	 * for now.
1159 	 */
1160 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1161 		return 0;
1162 
1163 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
1164 	cmd.upd0 = HAL_REO_CMD_UPD0_PN |
1165 		    HAL_REO_CMD_UPD0_PN_SIZE |
1166 		    HAL_REO_CMD_UPD0_PN_VALID |
1167 		    HAL_REO_CMD_UPD0_PN_CHECK |
1168 		    HAL_REO_CMD_UPD0_SVLD;
1169 
1170 	switch (key->cipher) {
1171 	case WLAN_CIPHER_SUITE_TKIP:
1172 	case WLAN_CIPHER_SUITE_CCMP:
1173 	case WLAN_CIPHER_SUITE_CCMP_256:
1174 	case WLAN_CIPHER_SUITE_GCMP:
1175 	case WLAN_CIPHER_SUITE_GCMP_256:
1176 		if (key_cmd == SET_KEY) {
1177 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1178 			cmd.pn_size = 48;
1179 		}
1180 		break;
1181 	default:
1182 		break;
1183 	}
1184 
1185 	spin_lock_bh(&ab->base_lock);
1186 
1187 	peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr);
1188 	if (!peer) {
1189 		spin_unlock_bh(&ab->base_lock);
1190 		ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n",
1191 			    peer_addr);
1192 		return -ENOENT;
1193 	}
1194 
1195 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1196 		rx_tid = &peer->rx_tid[tid];
1197 		if (!rx_tid->active)
1198 			continue;
1199 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1200 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1201 		ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
1202 					     HAL_REO_CMD_UPDATE_RX_QUEUE,
1203 					     &cmd, NULL);
1204 		if (ret) {
1205 			ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n",
1206 				    tid, peer_addr, ret);
1207 			break;
1208 		}
1209 	}
1210 
1211 	spin_unlock_bh(&ab->base_lock);
1212 
1213 	return ret;
1214 }
1215 
ath12k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1216 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1217 				      u16 peer_id)
1218 {
1219 	int i;
1220 
1221 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1222 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1223 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1224 				return i;
1225 		} else {
1226 			return i;
1227 		}
1228 	}
1229 
1230 	return -EINVAL;
1231 }
1232 
ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1233 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab,
1234 					   u16 tag, u16 len, const void *ptr,
1235 					   void *data)
1236 {
1237 	const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status;
1238 	const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn;
1239 	const struct htt_ppdu_stats_user_rate *user_rate;
1240 	struct htt_ppdu_stats_info *ppdu_info;
1241 	struct htt_ppdu_user_stats *user_stats;
1242 	int cur_user;
1243 	u16 peer_id;
1244 
1245 	ppdu_info = data;
1246 
1247 	switch (tag) {
1248 	case HTT_PPDU_STATS_TAG_COMMON:
1249 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1250 			ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1251 				    len, tag);
1252 			return -EINVAL;
1253 		}
1254 		memcpy(&ppdu_info->ppdu_stats.common, ptr,
1255 		       sizeof(struct htt_ppdu_stats_common));
1256 		break;
1257 	case HTT_PPDU_STATS_TAG_USR_RATE:
1258 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1259 			ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1260 				    len, tag);
1261 			return -EINVAL;
1262 		}
1263 		user_rate = ptr;
1264 		peer_id = le16_to_cpu(user_rate->sw_peer_id);
1265 		cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1266 						      peer_id);
1267 		if (cur_user < 0)
1268 			return -EINVAL;
1269 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1270 		user_stats->peer_id = peer_id;
1271 		user_stats->is_valid_peer_id = true;
1272 		memcpy(&user_stats->rate, ptr,
1273 		       sizeof(struct htt_ppdu_stats_user_rate));
1274 		user_stats->tlv_flags |= BIT(tag);
1275 		break;
1276 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1277 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1278 			ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1279 				    len, tag);
1280 			return -EINVAL;
1281 		}
1282 
1283 		cmplt_cmn = ptr;
1284 		peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id);
1285 		cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1286 						      peer_id);
1287 		if (cur_user < 0)
1288 			return -EINVAL;
1289 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1290 		user_stats->peer_id = peer_id;
1291 		user_stats->is_valid_peer_id = true;
1292 		memcpy(&user_stats->cmpltn_cmn, ptr,
1293 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1294 		user_stats->tlv_flags |= BIT(tag);
1295 		break;
1296 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1297 		if (len <
1298 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1299 			ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1300 				    len, tag);
1301 			return -EINVAL;
1302 		}
1303 
1304 		ba_status = ptr;
1305 		peer_id = le16_to_cpu(ba_status->sw_peer_id);
1306 		cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1307 						      peer_id);
1308 		if (cur_user < 0)
1309 			return -EINVAL;
1310 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1311 		user_stats->peer_id = peer_id;
1312 		user_stats->is_valid_peer_id = true;
1313 		memcpy(&user_stats->ack_ba, ptr,
1314 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1315 		user_stats->tlv_flags |= BIT(tag);
1316 		break;
1317 	}
1318 	return 0;
1319 }
1320 
ath12k_dp_htt_tlv_iter(struct ath12k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath12k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1321 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
1322 			   int (*iter)(struct ath12k_base *ar, u16 tag, u16 len,
1323 				       const void *ptr, void *data),
1324 			   void *data)
1325 {
1326 	const struct htt_tlv *tlv;
1327 	const void *begin = ptr;
1328 	u16 tlv_tag, tlv_len;
1329 	int ret = -EINVAL;
1330 
1331 	while (len > 0) {
1332 		if (len < sizeof(*tlv)) {
1333 			ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1334 				   ptr - begin, len, sizeof(*tlv));
1335 			return -EINVAL;
1336 		}
1337 		tlv = (struct htt_tlv *)ptr;
1338 		tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG);
1339 		tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN);
1340 		ptr += sizeof(*tlv);
1341 		len -= sizeof(*tlv);
1342 
1343 		if (tlv_len > len) {
1344 			ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1345 				   tlv_tag, ptr - begin, len, tlv_len);
1346 			return -EINVAL;
1347 		}
1348 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1349 		if (ret == -ENOMEM)
1350 			return ret;
1351 
1352 		ptr += tlv_len;
1353 		len -= tlv_len;
1354 	}
1355 	return 0;
1356 }
1357 
1358 static void
ath12k_update_per_peer_tx_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1359 ath12k_update_per_peer_tx_stats(struct ath12k *ar,
1360 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1361 {
1362 	struct ath12k_base *ab = ar->ab;
1363 	struct ath12k_peer *peer;
1364 	struct ieee80211_sta *sta;
1365 	struct ath12k_sta *ahsta;
1366 	struct ath12k_link_sta *arsta;
1367 	struct htt_ppdu_stats_user_rate *user_rate;
1368 	struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1369 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1370 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1371 	int ret;
1372 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1373 	u32 v, succ_bytes = 0;
1374 	u16 tones, rate = 0, succ_pkts = 0;
1375 	u32 tx_duration = 0;
1376 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1377 	bool is_ampdu = false;
1378 
1379 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1380 		return;
1381 
1382 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1383 		is_ampdu =
1384 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1385 
1386 	if (usr_stats->tlv_flags &
1387 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1388 		succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes);
1389 		succ_pkts = le32_get_bits(usr_stats->ack_ba.info,
1390 					  HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M);
1391 		tid = le32_get_bits(usr_stats->ack_ba.info,
1392 				    HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM);
1393 	}
1394 
1395 	if (common->fes_duration_us)
1396 		tx_duration = le32_to_cpu(common->fes_duration_us);
1397 
1398 	user_rate = &usr_stats->rate;
1399 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1400 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1401 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1402 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1403 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1404 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1405 
1406 	/* Note: If host configured fixed rates and in some other special
1407 	 * cases, the broadcast/management frames are sent in different rates.
1408 	 * Firmware rate's control to be skipped for this?
1409 	 */
1410 
1411 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) {
1412 		ath12k_warn(ab, "Invalid HE mcs %d peer stats",  mcs);
1413 		return;
1414 	}
1415 
1416 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) {
1417 		ath12k_warn(ab, "Invalid VHT mcs %d peer stats",  mcs);
1418 		return;
1419 	}
1420 
1421 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) {
1422 		ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1423 			    mcs, nss);
1424 		return;
1425 	}
1426 
1427 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1428 		ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs,
1429 							    flags,
1430 							    &rate_idx,
1431 							    &rate);
1432 		if (ret < 0)
1433 			return;
1434 	}
1435 
1436 	rcu_read_lock();
1437 	spin_lock_bh(&ab->base_lock);
1438 	peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id);
1439 
1440 	if (!peer || !peer->sta) {
1441 		spin_unlock_bh(&ab->base_lock);
1442 		rcu_read_unlock();
1443 		return;
1444 	}
1445 
1446 	sta = peer->sta;
1447 	ahsta = ath12k_sta_to_ahsta(sta);
1448 	arsta = &ahsta->deflink;
1449 
1450 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1451 
1452 	switch (flags) {
1453 	case WMI_RATE_PREAMBLE_OFDM:
1454 		arsta->txrate.legacy = rate;
1455 		break;
1456 	case WMI_RATE_PREAMBLE_CCK:
1457 		arsta->txrate.legacy = rate;
1458 		break;
1459 	case WMI_RATE_PREAMBLE_HT:
1460 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1461 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1462 		if (sgi)
1463 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1464 		break;
1465 	case WMI_RATE_PREAMBLE_VHT:
1466 		arsta->txrate.mcs = mcs;
1467 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1468 		if (sgi)
1469 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1470 		break;
1471 	case WMI_RATE_PREAMBLE_HE:
1472 		arsta->txrate.mcs = mcs;
1473 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1474 		arsta->txrate.he_dcm = dcm;
1475 		arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
1476 		tones = le16_to_cpu(user_rate->ru_end) -
1477 			le16_to_cpu(user_rate->ru_start) + 1;
1478 		v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones);
1479 		arsta->txrate.he_ru_alloc = v;
1480 		break;
1481 	}
1482 
1483 	arsta->txrate.nss = nss;
1484 	arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw);
1485 	arsta->tx_duration += tx_duration;
1486 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1487 
1488 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1489 	 * So skip peer stats update for mgmt packets.
1490 	 */
1491 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1492 		memset(peer_stats, 0, sizeof(*peer_stats));
1493 		peer_stats->succ_pkts = succ_pkts;
1494 		peer_stats->succ_bytes = succ_bytes;
1495 		peer_stats->is_ampdu = is_ampdu;
1496 		peer_stats->duration = tx_duration;
1497 		peer_stats->ba_fails =
1498 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1499 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1500 	}
1501 
1502 	spin_unlock_bh(&ab->base_lock);
1503 	rcu_read_unlock();
1504 }
1505 
ath12k_htt_update_ppdu_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats)1506 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar,
1507 					 struct htt_ppdu_stats *ppdu_stats)
1508 {
1509 	u8 user;
1510 
1511 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1512 		ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1513 }
1514 
1515 static
ath12k_dp_htt_get_ppdu_desc(struct ath12k * ar,u32 ppdu_id)1516 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar,
1517 							u32 ppdu_id)
1518 {
1519 	struct htt_ppdu_stats_info *ppdu_info;
1520 
1521 	lockdep_assert_held(&ar->data_lock);
1522 	if (!list_empty(&ar->ppdu_stats_info)) {
1523 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1524 			if (ppdu_info->ppdu_id == ppdu_id)
1525 				return ppdu_info;
1526 		}
1527 
1528 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1529 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1530 						     typeof(*ppdu_info), list);
1531 			list_del(&ppdu_info->list);
1532 			ar->ppdu_stat_list_depth--;
1533 			ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1534 			kfree(ppdu_info);
1535 		}
1536 	}
1537 
1538 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1539 	if (!ppdu_info)
1540 		return NULL;
1541 
1542 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1543 	ar->ppdu_stat_list_depth++;
1544 
1545 	return ppdu_info;
1546 }
1547 
ath12k_copy_to_delay_stats(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1548 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer,
1549 				       struct htt_ppdu_user_stats *usr_stats)
1550 {
1551 	peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id);
1552 	peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0);
1553 	peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end);
1554 	peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start);
1555 	peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1);
1556 	peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags);
1557 	peer->ppdu_stats_delayba.resp_rate_flags =
1558 		le32_to_cpu(usr_stats->rate.resp_rate_flags);
1559 
1560 	peer->delayba_flag = true;
1561 }
1562 
ath12k_copy_to_bar(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1563 static void ath12k_copy_to_bar(struct ath12k_peer *peer,
1564 			       struct htt_ppdu_user_stats *usr_stats)
1565 {
1566 	usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id);
1567 	usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0);
1568 	usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end);
1569 	usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start);
1570 	usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1);
1571 	usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags);
1572 	usr_stats->rate.resp_rate_flags =
1573 		cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags);
1574 
1575 	peer->delayba_flag = false;
1576 }
1577 
ath12k_htt_pull_ppdu_stats(struct ath12k_base * ab,struct sk_buff * skb)1578 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab,
1579 				      struct sk_buff *skb)
1580 {
1581 	struct ath12k_htt_ppdu_stats_msg *msg;
1582 	struct htt_ppdu_stats_info *ppdu_info;
1583 	struct ath12k_peer *peer = NULL;
1584 	struct htt_ppdu_user_stats *usr_stats = NULL;
1585 	u32 peer_id = 0;
1586 	struct ath12k *ar;
1587 	int ret, i;
1588 	u8 pdev_id;
1589 	u32 ppdu_id, len;
1590 
1591 	msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data;
1592 	len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE);
1593 	if (len > (skb->len - struct_size(msg, data, 0))) {
1594 		ath12k_warn(ab,
1595 			    "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n",
1596 			    len, skb->len);
1597 		return -EINVAL;
1598 	}
1599 
1600 	pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID);
1601 	ppdu_id = le32_to_cpu(msg->ppdu_id);
1602 
1603 	rcu_read_lock();
1604 	ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1605 	if (!ar) {
1606 		ret = -EINVAL;
1607 		goto exit;
1608 	}
1609 
1610 	spin_lock_bh(&ar->data_lock);
1611 	ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1612 	if (!ppdu_info) {
1613 		spin_unlock_bh(&ar->data_lock);
1614 		ret = -EINVAL;
1615 		goto exit;
1616 	}
1617 
1618 	ppdu_info->ppdu_id = ppdu_id;
1619 	ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len,
1620 				     ath12k_htt_tlv_ppdu_stats_parse,
1621 				     (void *)ppdu_info);
1622 	if (ret) {
1623 		spin_unlock_bh(&ar->data_lock);
1624 		ath12k_warn(ab, "Failed to parse tlv %d\n", ret);
1625 		goto exit;
1626 	}
1627 
1628 	if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) {
1629 		spin_unlock_bh(&ar->data_lock);
1630 		ath12k_warn(ab,
1631 			    "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n",
1632 			    ppdu_info->ppdu_stats.common.num_users,
1633 			    HTT_PPDU_STATS_MAX_USERS);
1634 		ret = -EINVAL;
1635 		goto exit;
1636 	}
1637 
1638 	/* back up data rate tlv for all peers */
1639 	if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA &&
1640 	    (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) &&
1641 	    ppdu_info->delay_ba) {
1642 		for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) {
1643 			peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1644 			spin_lock_bh(&ab->base_lock);
1645 			peer = ath12k_peer_find_by_id(ab, peer_id);
1646 			if (!peer) {
1647 				spin_unlock_bh(&ab->base_lock);
1648 				continue;
1649 			}
1650 
1651 			usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1652 			if (usr_stats->delay_ba)
1653 				ath12k_copy_to_delay_stats(peer, usr_stats);
1654 			spin_unlock_bh(&ab->base_lock);
1655 		}
1656 	}
1657 
1658 	/* restore all peers' data rate tlv to mu-bar tlv */
1659 	if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR &&
1660 	    (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) {
1661 		for (i = 0; i < ppdu_info->bar_num_users; i++) {
1662 			peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1663 			spin_lock_bh(&ab->base_lock);
1664 			peer = ath12k_peer_find_by_id(ab, peer_id);
1665 			if (!peer) {
1666 				spin_unlock_bh(&ab->base_lock);
1667 				continue;
1668 			}
1669 
1670 			usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1671 			if (peer->delayba_flag)
1672 				ath12k_copy_to_bar(peer, usr_stats);
1673 			spin_unlock_bh(&ab->base_lock);
1674 		}
1675 	}
1676 
1677 	spin_unlock_bh(&ar->data_lock);
1678 
1679 exit:
1680 	rcu_read_unlock();
1681 
1682 	return ret;
1683 }
1684 
ath12k_htt_mlo_offset_event_handler(struct ath12k_base * ab,struct sk_buff * skb)1685 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab,
1686 						struct sk_buff *skb)
1687 {
1688 	struct ath12k_htt_mlo_offset_msg *msg;
1689 	struct ath12k_pdev *pdev;
1690 	struct ath12k *ar;
1691 	u8 pdev_id;
1692 
1693 	msg = (struct ath12k_htt_mlo_offset_msg *)skb->data;
1694 	pdev_id = u32_get_bits(__le32_to_cpu(msg->info),
1695 			       HTT_T2H_MLO_OFFSET_INFO_PDEV_ID);
1696 
1697 	rcu_read_lock();
1698 	ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1699 	if (!ar) {
1700 		/* It is possible that the ar is not yet active (started).
1701 		 * The above function will only look for the active pdev
1702 		 * and hence %NULL return is possible. Just silently
1703 		 * discard this message
1704 		 */
1705 		goto exit;
1706 	}
1707 
1708 	spin_lock_bh(&ar->data_lock);
1709 	pdev = ar->pdev;
1710 
1711 	pdev->timestamp.info = __le32_to_cpu(msg->info);
1712 	pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us);
1713 	pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us);
1714 	pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo);
1715 	pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi);
1716 	pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks);
1717 	pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks);
1718 	pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer);
1719 
1720 	spin_unlock_bh(&ar->data_lock);
1721 exit:
1722 	rcu_read_unlock();
1723 }
1724 
ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base * ab,struct sk_buff * skb)1725 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
1726 				       struct sk_buff *skb)
1727 {
1728 	struct ath12k_dp *dp = &ab->dp;
1729 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1730 	enum htt_t2h_msg_type type;
1731 	u16 peer_id;
1732 	u8 vdev_id;
1733 	u8 mac_addr[ETH_ALEN];
1734 	u16 peer_mac_h16;
1735 	u16 ast_hash = 0;
1736 	u16 hw_peer_id;
1737 
1738 	type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE);
1739 
1740 	ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1741 
1742 	switch (type) {
1743 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1744 		dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version,
1745 						      HTT_T2H_VERSION_CONF_MAJOR);
1746 		dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version,
1747 						      HTT_T2H_VERSION_CONF_MINOR);
1748 		complete(&dp->htt_tgt_version_received);
1749 		break;
1750 	/* TODO: remove unused peer map versions after testing */
1751 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1752 		vdev_id = le32_get_bits(resp->peer_map_ev.info,
1753 					HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1754 		peer_id = le32_get_bits(resp->peer_map_ev.info,
1755 					HTT_T2H_PEER_MAP_INFO_PEER_ID);
1756 		peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1757 					     HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1758 		ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1759 				       peer_mac_h16, mac_addr);
1760 		ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1761 		break;
1762 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1763 		vdev_id = le32_get_bits(resp->peer_map_ev.info,
1764 					HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1765 		peer_id = le32_get_bits(resp->peer_map_ev.info,
1766 					HTT_T2H_PEER_MAP_INFO_PEER_ID);
1767 		peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1768 					     HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1769 		ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1770 				       peer_mac_h16, mac_addr);
1771 		ast_hash = le32_get_bits(resp->peer_map_ev.info2,
1772 					 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL);
1773 		hw_peer_id = le32_get_bits(resp->peer_map_ev.info1,
1774 					   HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID);
1775 		ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1776 				      hw_peer_id);
1777 		break;
1778 	case HTT_T2H_MSG_TYPE_PEER_MAP3:
1779 		vdev_id = le32_get_bits(resp->peer_map_ev.info,
1780 					HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1781 		peer_id = le32_get_bits(resp->peer_map_ev.info,
1782 					HTT_T2H_PEER_MAP_INFO_PEER_ID);
1783 		peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1784 					     HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1785 		ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1786 				       peer_mac_h16, mac_addr);
1787 		ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1788 				      peer_id);
1789 		break;
1790 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1791 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1792 		peer_id = le32_get_bits(resp->peer_unmap_ev.info,
1793 					HTT_T2H_PEER_UNMAP_INFO_PEER_ID);
1794 		ath12k_peer_unmap_event(ab, peer_id);
1795 		break;
1796 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1797 		ath12k_htt_pull_ppdu_stats(ab, skb);
1798 		break;
1799 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1800 		ath12k_debugfs_htt_ext_stats_handler(ab, skb);
1801 		break;
1802 	case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND:
1803 		ath12k_htt_mlo_offset_event_handler(ab, skb);
1804 		break;
1805 	default:
1806 		ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n",
1807 			   type);
1808 		break;
1809 	}
1810 
1811 	dev_kfree_skb_any(skb);
1812 }
1813 
ath12k_dp_rx_msdu_coalesce(struct ath12k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1814 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar,
1815 				      struct sk_buff_head *msdu_list,
1816 				      struct sk_buff *first, struct sk_buff *last,
1817 				      u8 l3pad_bytes, int msdu_len)
1818 {
1819 	struct ath12k_base *ab = ar->ab;
1820 	struct sk_buff *skb;
1821 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1822 	int buf_first_hdr_len, buf_first_len;
1823 	struct hal_rx_desc *ldesc;
1824 	int space_extra, rem_len, buf_len;
1825 	u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
1826 
1827 	/* As the msdu is spread across multiple rx buffers,
1828 	 * find the offset to the start of msdu for computing
1829 	 * the length of the msdu in the first buffer.
1830 	 */
1831 	buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1832 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1833 
1834 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1835 		skb_put(first, buf_first_hdr_len + msdu_len);
1836 		skb_pull(first, buf_first_hdr_len);
1837 		return 0;
1838 	}
1839 
1840 	ldesc = (struct hal_rx_desc *)last->data;
1841 	rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc);
1842 	rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc);
1843 
1844 	/* MSDU spans over multiple buffers because the length of the MSDU
1845 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1846 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1847 	 */
1848 	skb_put(first, DP_RX_BUFFER_SIZE);
1849 	skb_pull(first, buf_first_hdr_len);
1850 
1851 	/* When an MSDU spread over multiple buffers MSDU_END
1852 	 * tlvs are valid only in the last buffer. Copy those tlvs.
1853 	 */
1854 	ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1855 
1856 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1857 	if (space_extra > 0 &&
1858 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1859 		/* Free up all buffers of the MSDU */
1860 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1861 			rxcb = ATH12K_SKB_RXCB(skb);
1862 			if (!rxcb->is_continuation) {
1863 				dev_kfree_skb_any(skb);
1864 				break;
1865 			}
1866 			dev_kfree_skb_any(skb);
1867 		}
1868 		return -ENOMEM;
1869 	}
1870 
1871 	rem_len = msdu_len - buf_first_len;
1872 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1873 		rxcb = ATH12K_SKB_RXCB(skb);
1874 		if (rxcb->is_continuation)
1875 			buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1876 		else
1877 			buf_len = rem_len;
1878 
1879 		if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1880 			WARN_ON_ONCE(1);
1881 			dev_kfree_skb_any(skb);
1882 			return -EINVAL;
1883 		}
1884 
1885 		skb_put(skb, buf_len + hal_rx_desc_sz);
1886 		skb_pull(skb, hal_rx_desc_sz);
1887 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1888 					  buf_len);
1889 		dev_kfree_skb_any(skb);
1890 
1891 		rem_len -= buf_len;
1892 		if (!rxcb->is_continuation)
1893 			break;
1894 	}
1895 
1896 	return 0;
1897 }
1898 
ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1899 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1900 						      struct sk_buff *first)
1901 {
1902 	struct sk_buff *skb;
1903 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1904 
1905 	if (!rxcb->is_continuation)
1906 		return first;
1907 
1908 	skb_queue_walk(msdu_list, skb) {
1909 		rxcb = ATH12K_SKB_RXCB(skb);
1910 		if (!rxcb->is_continuation)
1911 			return skb;
1912 	}
1913 
1914 	return NULL;
1915 }
1916 
ath12k_dp_rx_h_csum_offload(struct ath12k * ar,struct sk_buff * msdu)1917 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu)
1918 {
1919 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1920 	struct ath12k_base *ab = ar->ab;
1921 	bool ip_csum_fail, l4_csum_fail;
1922 
1923 	ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc);
1924 	l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc);
1925 
1926 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1927 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1928 }
1929 
ath12k_dp_rx_crypto_mic_len(struct ath12k * ar,enum hal_encrypt_type enctype)1930 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar,
1931 				       enum hal_encrypt_type enctype)
1932 {
1933 	switch (enctype) {
1934 	case HAL_ENCRYPT_TYPE_OPEN:
1935 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1936 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1937 		return 0;
1938 	case HAL_ENCRYPT_TYPE_CCMP_128:
1939 		return IEEE80211_CCMP_MIC_LEN;
1940 	case HAL_ENCRYPT_TYPE_CCMP_256:
1941 		return IEEE80211_CCMP_256_MIC_LEN;
1942 	case HAL_ENCRYPT_TYPE_GCMP_128:
1943 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1944 		return IEEE80211_GCMP_MIC_LEN;
1945 	case HAL_ENCRYPT_TYPE_WEP_40:
1946 	case HAL_ENCRYPT_TYPE_WEP_104:
1947 	case HAL_ENCRYPT_TYPE_WEP_128:
1948 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1949 	case HAL_ENCRYPT_TYPE_WAPI:
1950 		break;
1951 	}
1952 
1953 	ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1954 	return 0;
1955 }
1956 
ath12k_dp_rx_crypto_param_len(struct ath12k * ar,enum hal_encrypt_type enctype)1957 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar,
1958 					 enum hal_encrypt_type enctype)
1959 {
1960 	switch (enctype) {
1961 	case HAL_ENCRYPT_TYPE_OPEN:
1962 		return 0;
1963 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1964 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1965 		return IEEE80211_TKIP_IV_LEN;
1966 	case HAL_ENCRYPT_TYPE_CCMP_128:
1967 		return IEEE80211_CCMP_HDR_LEN;
1968 	case HAL_ENCRYPT_TYPE_CCMP_256:
1969 		return IEEE80211_CCMP_256_HDR_LEN;
1970 	case HAL_ENCRYPT_TYPE_GCMP_128:
1971 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1972 		return IEEE80211_GCMP_HDR_LEN;
1973 	case HAL_ENCRYPT_TYPE_WEP_40:
1974 	case HAL_ENCRYPT_TYPE_WEP_104:
1975 	case HAL_ENCRYPT_TYPE_WEP_128:
1976 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1977 	case HAL_ENCRYPT_TYPE_WAPI:
1978 		break;
1979 	}
1980 
1981 	ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1982 	return 0;
1983 }
1984 
ath12k_dp_rx_crypto_icv_len(struct ath12k * ar,enum hal_encrypt_type enctype)1985 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar,
1986 				       enum hal_encrypt_type enctype)
1987 {
1988 	switch (enctype) {
1989 	case HAL_ENCRYPT_TYPE_OPEN:
1990 	case HAL_ENCRYPT_TYPE_CCMP_128:
1991 	case HAL_ENCRYPT_TYPE_CCMP_256:
1992 	case HAL_ENCRYPT_TYPE_GCMP_128:
1993 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1994 		return 0;
1995 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1996 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1997 		return IEEE80211_TKIP_ICV_LEN;
1998 	case HAL_ENCRYPT_TYPE_WEP_40:
1999 	case HAL_ENCRYPT_TYPE_WEP_104:
2000 	case HAL_ENCRYPT_TYPE_WEP_128:
2001 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
2002 	case HAL_ENCRYPT_TYPE_WAPI:
2003 		break;
2004 	}
2005 
2006 	ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
2007 	return 0;
2008 }
2009 
ath12k_dp_rx_h_undecap_nwifi(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2010 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar,
2011 					 struct sk_buff *msdu,
2012 					 enum hal_encrypt_type enctype,
2013 					 struct ieee80211_rx_status *status)
2014 {
2015 	struct ath12k_base *ab = ar->ab;
2016 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2017 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
2018 	struct ieee80211_hdr *hdr;
2019 	size_t hdr_len;
2020 	u8 *crypto_hdr;
2021 	u16 qos_ctl;
2022 
2023 	/* pull decapped header */
2024 	hdr = (struct ieee80211_hdr *)msdu->data;
2025 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2026 	skb_pull(msdu, hdr_len);
2027 
2028 	/*  Rebuild qos header */
2029 	hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2030 
2031 	/* Reset the order bit as the HT_Control header is stripped */
2032 	hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2033 
2034 	qos_ctl = rxcb->tid;
2035 
2036 	if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc))
2037 		qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2038 
2039 	/* TODO: Add other QoS ctl fields when required */
2040 
2041 	/* copy decap header before overwriting for reuse below */
2042 	memcpy(decap_hdr, hdr, hdr_len);
2043 
2044 	/* Rebuild crypto header for mac80211 use */
2045 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2046 		crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype));
2047 		ath12k_dp_rx_desc_get_crypto_header(ar->ab,
2048 						    rxcb->rx_desc, crypto_hdr,
2049 						    enctype);
2050 	}
2051 
2052 	memcpy(skb_push(msdu,
2053 			IEEE80211_QOS_CTL_LEN), &qos_ctl,
2054 			IEEE80211_QOS_CTL_LEN);
2055 	memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2056 }
2057 
ath12k_dp_rx_h_undecap_raw(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2058 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu,
2059 				       enum hal_encrypt_type enctype,
2060 				       struct ieee80211_rx_status *status,
2061 				       bool decrypted)
2062 {
2063 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2064 	struct ieee80211_hdr *hdr;
2065 	size_t hdr_len;
2066 	size_t crypto_len;
2067 
2068 	if (!rxcb->is_first_msdu ||
2069 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2070 		WARN_ON_ONCE(1);
2071 		return;
2072 	}
2073 
2074 	skb_trim(msdu, msdu->len - FCS_LEN);
2075 
2076 	if (!decrypted)
2077 		return;
2078 
2079 	hdr = (void *)msdu->data;
2080 
2081 	/* Tail */
2082 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2083 		skb_trim(msdu, msdu->len -
2084 			 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2085 
2086 		skb_trim(msdu, msdu->len -
2087 			 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2088 	} else {
2089 		/* MIC */
2090 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2091 			skb_trim(msdu, msdu->len -
2092 				 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2093 
2094 		/* ICV */
2095 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2096 			skb_trim(msdu, msdu->len -
2097 				 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2098 	}
2099 
2100 	/* MMIC */
2101 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2102 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2103 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2104 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2105 
2106 	/* Head */
2107 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2108 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2109 		crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2110 
2111 		memmove(msdu->data + crypto_len, msdu->data, hdr_len);
2112 		skb_pull(msdu, crypto_len);
2113 	}
2114 }
2115 
ath12k_get_dot11_hdr_from_rx_desc(struct ath12k * ar,struct sk_buff * msdu,struct ath12k_skb_rxcb * rxcb,struct ieee80211_rx_status * status,enum hal_encrypt_type enctype)2116 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar,
2117 					      struct sk_buff *msdu,
2118 					      struct ath12k_skb_rxcb *rxcb,
2119 					      struct ieee80211_rx_status *status,
2120 					      enum hal_encrypt_type enctype)
2121 {
2122 	struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2123 	struct ath12k_base *ab = ar->ab;
2124 	size_t hdr_len, crypto_len;
2125 	struct ieee80211_hdr *hdr;
2126 	u16 qos_ctl;
2127 	__le16 fc;
2128 	u8 *crypto_hdr;
2129 
2130 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2131 		crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2132 		crypto_hdr = skb_push(msdu, crypto_len);
2133 		ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype);
2134 	}
2135 
2136 	fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc));
2137 	hdr_len = ieee80211_hdrlen(fc);
2138 	skb_push(msdu, hdr_len);
2139 	hdr = (struct ieee80211_hdr *)msdu->data;
2140 	hdr->frame_control = fc;
2141 
2142 	/* Get wifi header from rx_desc */
2143 	ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr);
2144 
2145 	if (rxcb->is_mcbc)
2146 		status->flag &= ~RX_FLAG_PN_VALIDATED;
2147 
2148 	/* Add QOS header */
2149 	if (ieee80211_is_data_qos(hdr->frame_control)) {
2150 		qos_ctl = rxcb->tid;
2151 		if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc))
2152 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2153 
2154 		/* TODO: Add other QoS ctl fields when required */
2155 		memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN),
2156 		       &qos_ctl, IEEE80211_QOS_CTL_LEN);
2157 	}
2158 }
2159 
ath12k_dp_rx_h_undecap_eth(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2160 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar,
2161 				       struct sk_buff *msdu,
2162 				       enum hal_encrypt_type enctype,
2163 				       struct ieee80211_rx_status *status)
2164 {
2165 	struct ieee80211_hdr *hdr;
2166 	struct ethhdr *eth;
2167 	u8 da[ETH_ALEN];
2168 	u8 sa[ETH_ALEN];
2169 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2170 	struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}};
2171 
2172 	eth = (struct ethhdr *)msdu->data;
2173 	ether_addr_copy(da, eth->h_dest);
2174 	ether_addr_copy(sa, eth->h_source);
2175 	rfc.snap_type = eth->h_proto;
2176 	skb_pull(msdu, sizeof(*eth));
2177 	memcpy(skb_push(msdu, sizeof(rfc)), &rfc,
2178 	       sizeof(rfc));
2179 	ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype);
2180 
2181 	/* original 802.11 header has a different DA and in
2182 	 * case of 4addr it may also have different SA
2183 	 */
2184 	hdr = (struct ieee80211_hdr *)msdu->data;
2185 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2186 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2187 }
2188 
ath12k_dp_rx_h_undecap(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2189 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu,
2190 				   struct hal_rx_desc *rx_desc,
2191 				   enum hal_encrypt_type enctype,
2192 				   struct ieee80211_rx_status *status,
2193 				   bool decrypted)
2194 {
2195 	struct ath12k_base *ab = ar->ab;
2196 	u8 decap;
2197 	struct ethhdr *ehdr;
2198 
2199 	decap = ath12k_dp_rx_h_decap_type(ab, rx_desc);
2200 
2201 	switch (decap) {
2202 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2203 		ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status);
2204 		break;
2205 	case DP_RX_DECAP_TYPE_RAW:
2206 		ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2207 					   decrypted);
2208 		break;
2209 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2210 		ehdr = (struct ethhdr *)msdu->data;
2211 
2212 		/* mac80211 allows fast path only for authorized STA */
2213 		if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2214 			ATH12K_SKB_RXCB(msdu)->is_eapol = true;
2215 			ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2216 			break;
2217 		}
2218 
2219 		/* PN for mcast packets will be validated in mac80211;
2220 		 * remove eth header and add 802.11 header.
2221 		 */
2222 		if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2223 			ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2224 		break;
2225 	case DP_RX_DECAP_TYPE_8023:
2226 		/* TODO: Handle undecap for these formats */
2227 		break;
2228 	}
2229 }
2230 
2231 struct ath12k_peer *
ath12k_dp_rx_h_find_peer(struct ath12k_base * ab,struct sk_buff * msdu)2232 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu)
2233 {
2234 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2235 	struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2236 	struct ath12k_peer *peer = NULL;
2237 
2238 	lockdep_assert_held(&ab->base_lock);
2239 
2240 	if (rxcb->peer_id)
2241 		peer = ath12k_peer_find_by_id(ab, rxcb->peer_id);
2242 
2243 	if (peer)
2244 		return peer;
2245 
2246 	if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2247 		return NULL;
2248 
2249 	peer = ath12k_peer_find_by_addr(ab,
2250 					ath12k_dp_rxdesc_get_mpdu_start_addr2(ab,
2251 									      rx_desc));
2252 	return peer;
2253 }
2254 
ath12k_dp_rx_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2255 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar,
2256 				struct sk_buff *msdu,
2257 				struct hal_rx_desc *rx_desc,
2258 				struct ieee80211_rx_status *rx_status)
2259 {
2260 	bool  fill_crypto_hdr;
2261 	struct ath12k_base *ab = ar->ab;
2262 	struct ath12k_skb_rxcb *rxcb;
2263 	enum hal_encrypt_type enctype;
2264 	bool is_decrypted = false;
2265 	struct ieee80211_hdr *hdr;
2266 	struct ath12k_peer *peer;
2267 	u32 err_bitmap;
2268 
2269 	/* PN for multicast packets will be checked in mac80211 */
2270 	rxcb = ATH12K_SKB_RXCB(msdu);
2271 	fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc);
2272 	rxcb->is_mcbc = fill_crypto_hdr;
2273 
2274 	if (rxcb->is_mcbc)
2275 		rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc);
2276 
2277 	spin_lock_bh(&ar->ab->base_lock);
2278 	peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
2279 	if (peer) {
2280 		if (rxcb->is_mcbc)
2281 			enctype = peer->sec_type_grp;
2282 		else
2283 			enctype = peer->sec_type;
2284 	} else {
2285 		enctype = HAL_ENCRYPT_TYPE_OPEN;
2286 	}
2287 	spin_unlock_bh(&ar->ab->base_lock);
2288 
2289 	err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
2290 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2291 		is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc);
2292 
2293 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2294 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2295 			     RX_FLAG_MMIC_ERROR |
2296 			     RX_FLAG_DECRYPTED |
2297 			     RX_FLAG_IV_STRIPPED |
2298 			     RX_FLAG_MMIC_STRIPPED);
2299 
2300 	if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
2301 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2302 	if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC)
2303 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2304 
2305 	if (is_decrypted) {
2306 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2307 
2308 		if (fill_crypto_hdr)
2309 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2310 					RX_FLAG_ICV_STRIPPED;
2311 		else
2312 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2313 					   RX_FLAG_PN_VALIDATED;
2314 	}
2315 
2316 	ath12k_dp_rx_h_csum_offload(ar, msdu);
2317 	ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
2318 			       enctype, rx_status, is_decrypted);
2319 
2320 	if (!is_decrypted || fill_crypto_hdr)
2321 		return;
2322 
2323 	if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) !=
2324 	    DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2325 		hdr = (void *)msdu->data;
2326 		hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2327 	}
2328 }
2329 
ath12k_dp_rx_h_rate(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2330 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2331 				struct ieee80211_rx_status *rx_status)
2332 {
2333 	struct ath12k_base *ab = ar->ab;
2334 	struct ieee80211_supported_band *sband;
2335 	enum rx_msdu_start_pkt_type pkt_type;
2336 	u8 bw;
2337 	u8 rate_mcs, nss;
2338 	u8 sgi;
2339 	bool is_cck;
2340 
2341 	pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc);
2342 	bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc);
2343 	rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc);
2344 	nss = ath12k_dp_rx_h_nss(ab, rx_desc);
2345 	sgi = ath12k_dp_rx_h_sgi(ab, rx_desc);
2346 
2347 	switch (pkt_type) {
2348 	case RX_MSDU_START_PKT_TYPE_11A:
2349 	case RX_MSDU_START_PKT_TYPE_11B:
2350 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2351 		sband = &ar->mac.sbands[rx_status->band];
2352 		rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs,
2353 								is_cck);
2354 		break;
2355 	case RX_MSDU_START_PKT_TYPE_11N:
2356 		rx_status->encoding = RX_ENC_HT;
2357 		if (rate_mcs > ATH12K_HT_MCS_MAX) {
2358 			ath12k_warn(ar->ab,
2359 				    "Received with invalid mcs in HT mode %d\n",
2360 				     rate_mcs);
2361 			break;
2362 		}
2363 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2364 		if (sgi)
2365 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2366 		rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2367 		break;
2368 	case RX_MSDU_START_PKT_TYPE_11AC:
2369 		rx_status->encoding = RX_ENC_VHT;
2370 		rx_status->rate_idx = rate_mcs;
2371 		if (rate_mcs > ATH12K_VHT_MCS_MAX) {
2372 			ath12k_warn(ar->ab,
2373 				    "Received with invalid mcs in VHT mode %d\n",
2374 				     rate_mcs);
2375 			break;
2376 		}
2377 		rx_status->nss = nss;
2378 		if (sgi)
2379 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2380 		rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2381 		break;
2382 	case RX_MSDU_START_PKT_TYPE_11AX:
2383 		rx_status->rate_idx = rate_mcs;
2384 		if (rate_mcs > ATH12K_HE_MCS_MAX) {
2385 			ath12k_warn(ar->ab,
2386 				    "Received with invalid mcs in HE mode %d\n",
2387 				    rate_mcs);
2388 			break;
2389 		}
2390 		rx_status->encoding = RX_ENC_HE;
2391 		rx_status->nss = nss;
2392 		rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
2393 		rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2394 		break;
2395 	case RX_MSDU_START_PKT_TYPE_11BE:
2396 		rx_status->rate_idx = rate_mcs;
2397 
2398 		if (rate_mcs > ATH12K_EHT_MCS_MAX) {
2399 			ath12k_warn(ar->ab,
2400 				    "Received with invalid mcs in EHT mode %d\n",
2401 				    rate_mcs);
2402 			break;
2403 		}
2404 
2405 		rx_status->encoding = RX_ENC_EHT;
2406 		rx_status->nss = nss;
2407 		rx_status->eht.gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(sgi);
2408 		rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2409 		break;
2410 	default:
2411 		break;
2412 	}
2413 }
2414 
ath12k_dp_rx_h_ppdu(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2415 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2416 			 struct ieee80211_rx_status *rx_status)
2417 {
2418 	struct ath12k_base *ab = ar->ab;
2419 	u8 channel_num;
2420 	u32 center_freq, meta_data;
2421 	struct ieee80211_channel *channel;
2422 
2423 	rx_status->freq = 0;
2424 	rx_status->rate_idx = 0;
2425 	rx_status->nss = 0;
2426 	rx_status->encoding = RX_ENC_LEGACY;
2427 	rx_status->bw = RATE_INFO_BW_20;
2428 	rx_status->enc_flags = 0;
2429 
2430 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2431 
2432 	meta_data = ath12k_dp_rx_h_freq(ab, rx_desc);
2433 	channel_num = meta_data;
2434 	center_freq = meta_data >> 16;
2435 
2436 	if (center_freq >= ATH12K_MIN_6G_FREQ &&
2437 	    center_freq <= ATH12K_MAX_6G_FREQ) {
2438 		rx_status->band = NL80211_BAND_6GHZ;
2439 		rx_status->freq = center_freq;
2440 	} else if (channel_num >= 1 && channel_num <= 14) {
2441 		rx_status->band = NL80211_BAND_2GHZ;
2442 	} else if (channel_num >= 36 && channel_num <= 173) {
2443 		rx_status->band = NL80211_BAND_5GHZ;
2444 	} else {
2445 		spin_lock_bh(&ar->data_lock);
2446 		channel = ar->rx_channel;
2447 		if (channel) {
2448 			rx_status->band = channel->band;
2449 			channel_num =
2450 				ieee80211_frequency_to_channel(channel->center_freq);
2451 		}
2452 		spin_unlock_bh(&ar->data_lock);
2453 		ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ",
2454 				rx_desc, sizeof(*rx_desc));
2455 	}
2456 
2457 	if (rx_status->band != NL80211_BAND_6GHZ)
2458 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2459 								 rx_status->band);
2460 
2461 	ath12k_dp_rx_h_rate(ar, rx_desc, rx_status);
2462 }
2463 
ath12k_dp_rx_deliver_msdu(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2464 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
2465 				      struct sk_buff *msdu,
2466 				      struct ieee80211_rx_status *status)
2467 {
2468 	struct ath12k_base *ab = ar->ab;
2469 	static const struct ieee80211_radiotap_he known = {
2470 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2471 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2472 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2473 	};
2474 	struct ieee80211_radiotap_he *he;
2475 	struct ieee80211_rx_status *rx_status;
2476 	struct ieee80211_sta *pubsta;
2477 	struct ath12k_peer *peer;
2478 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2479 	u8 decap = DP_RX_DECAP_TYPE_RAW;
2480 	bool is_mcbc = rxcb->is_mcbc;
2481 	bool is_eapol = rxcb->is_eapol;
2482 
2483 	if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2484 	    !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2485 		he = skb_push(msdu, sizeof(known));
2486 		memcpy(he, &known, sizeof(known));
2487 		status->flag |= RX_FLAG_RADIOTAP_HE;
2488 	}
2489 
2490 	if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2491 		decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc);
2492 
2493 	spin_lock_bh(&ab->base_lock);
2494 	peer = ath12k_dp_rx_h_find_peer(ab, msdu);
2495 
2496 	pubsta = peer ? peer->sta : NULL;
2497 
2498 	if (pubsta && pubsta->valid_links) {
2499 		status->link_valid = 1;
2500 		status->link_id = peer->link_id;
2501 	}
2502 
2503 	spin_unlock_bh(&ab->base_lock);
2504 
2505 	ath12k_dbg(ab, ATH12K_DBG_DATA,
2506 		   "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2507 		   msdu,
2508 		   msdu->len,
2509 		   peer ? peer->addr : NULL,
2510 		   rxcb->tid,
2511 		   is_mcbc ? "mcast" : "ucast",
2512 		   ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc),
2513 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2514 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2515 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2516 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2517 		   (status->encoding == RX_ENC_EHT) ? "eht" : "",
2518 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2519 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2520 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2521 		   (status->bw == RATE_INFO_BW_320) ? "320" : "",
2522 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2523 		   status->rate_idx,
2524 		   status->nss,
2525 		   status->freq,
2526 		   status->band, status->flag,
2527 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2528 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2529 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2530 
2531 	ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
2532 			msdu->data, msdu->len);
2533 
2534 	rx_status = IEEE80211_SKB_RXCB(msdu);
2535 	*rx_status = *status;
2536 
2537 	/* TODO: trace rx packet */
2538 
2539 	/* PN for multicast packets are not validate in HW,
2540 	 * so skip 802.3 rx path
2541 	 * Also, fast_rx expects the STA to be authorized, hence
2542 	 * eapol packets are sent in slow path.
2543 	 */
2544 	if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2545 	    !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2546 		rx_status->flag |= RX_FLAG_8023;
2547 
2548 	ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
2549 }
2550 
ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base * ab,struct hal_rx_desc * rx_desc,struct sk_buff * msdu)2551 static bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base *ab,
2552 						   struct hal_rx_desc *rx_desc,
2553 						   struct sk_buff *msdu)
2554 {
2555 	struct ieee80211_hdr *hdr;
2556 	u8 decap_type;
2557 	u32 hdr_len;
2558 
2559 	decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc);
2560 	if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI)
2561 		return true;
2562 
2563 	hdr = (struct ieee80211_hdr *)msdu->data;
2564 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2565 
2566 	if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN)))
2567 		return true;
2568 
2569 	ab->soc_stats.invalid_rbm++;
2570 	WARN_ON_ONCE(1);
2571 	return false;
2572 }
2573 
ath12k_dp_rx_process_msdu(struct ath12k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2574 static int ath12k_dp_rx_process_msdu(struct ath12k *ar,
2575 				     struct sk_buff *msdu,
2576 				     struct sk_buff_head *msdu_list,
2577 				     struct ieee80211_rx_status *rx_status)
2578 {
2579 	struct ath12k_base *ab = ar->ab;
2580 	struct hal_rx_desc *rx_desc, *lrx_desc;
2581 	struct ath12k_skb_rxcb *rxcb;
2582 	struct sk_buff *last_buf;
2583 	u8 l3_pad_bytes;
2584 	u16 msdu_len;
2585 	int ret;
2586 	u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2587 
2588 	last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2589 	if (!last_buf) {
2590 		ath12k_warn(ab,
2591 			    "No valid Rx buffer to access MSDU_END tlv\n");
2592 		ret = -EIO;
2593 		goto free_out;
2594 	}
2595 
2596 	rx_desc = (struct hal_rx_desc *)msdu->data;
2597 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2598 	if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) {
2599 		ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n");
2600 		ret = -EIO;
2601 		goto free_out;
2602 	}
2603 
2604 	rxcb = ATH12K_SKB_RXCB(msdu);
2605 	rxcb->rx_desc = rx_desc;
2606 	msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc);
2607 	l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc);
2608 
2609 	if (rxcb->is_frag) {
2610 		skb_pull(msdu, hal_rx_desc_sz);
2611 	} else if (!rxcb->is_continuation) {
2612 		if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2613 			ret = -EINVAL;
2614 			ath12k_warn(ab, "invalid msdu len %u\n", msdu_len);
2615 			ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
2616 					sizeof(*rx_desc));
2617 			goto free_out;
2618 		}
2619 		skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2620 		skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2621 	} else {
2622 		ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list,
2623 						 msdu, last_buf,
2624 						 l3_pad_bytes, msdu_len);
2625 		if (ret) {
2626 			ath12k_warn(ab,
2627 				    "failed to coalesce msdu rx buffer%d\n", ret);
2628 			goto free_out;
2629 		}
2630 	}
2631 
2632 	if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) {
2633 		ret = -EINVAL;
2634 		goto free_out;
2635 	}
2636 
2637 	ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2638 	ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2639 
2640 	rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2641 
2642 	return 0;
2643 
2644 free_out:
2645 	return ret;
2646 }
2647 
ath12k_dp_rx_process_received_packets(struct ath12k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int ring_id)2648 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab,
2649 						  struct napi_struct *napi,
2650 						  struct sk_buff_head *msdu_list,
2651 						  int ring_id)
2652 {
2653 	struct ath12k_hw_group *ag = ab->ag;
2654 	struct ieee80211_rx_status rx_status = {0};
2655 	struct ath12k_skb_rxcb *rxcb;
2656 	struct sk_buff *msdu;
2657 	struct ath12k *ar;
2658 	struct ath12k_hw_link *hw_links = ag->hw_links;
2659 	struct ath12k_base *partner_ab;
2660 	u8 hw_link_id, pdev_id;
2661 	int ret;
2662 
2663 	if (skb_queue_empty(msdu_list))
2664 		return;
2665 
2666 	rcu_read_lock();
2667 
2668 	while ((msdu = __skb_dequeue(msdu_list))) {
2669 		rxcb = ATH12K_SKB_RXCB(msdu);
2670 		hw_link_id = rxcb->hw_link_id;
2671 		partner_ab = ath12k_ag_to_ab(ag,
2672 					     hw_links[hw_link_id].device_id);
2673 		pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params,
2674 						      hw_links[hw_link_id].pdev_idx);
2675 		ar = partner_ab->pdevs[pdev_id].ar;
2676 		if (!rcu_dereference(partner_ab->pdevs_active[pdev_id])) {
2677 			dev_kfree_skb_any(msdu);
2678 			continue;
2679 		}
2680 
2681 		if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) {
2682 			dev_kfree_skb_any(msdu);
2683 			continue;
2684 		}
2685 
2686 		ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2687 		if (ret) {
2688 			ath12k_dbg(ab, ATH12K_DBG_DATA,
2689 				   "Unable to process msdu %d", ret);
2690 			dev_kfree_skb_any(msdu);
2691 			continue;
2692 		}
2693 
2694 		ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2695 	}
2696 
2697 	rcu_read_unlock();
2698 }
2699 
ath12k_dp_rx_get_peer_id(struct ath12k_base * ab,enum ath12k_peer_metadata_version ver,__le32 peer_metadata)2700 static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab,
2701 				    enum ath12k_peer_metadata_version ver,
2702 				    __le32 peer_metadata)
2703 {
2704 	switch (ver) {
2705 	default:
2706 		ath12k_warn(ab, "Unknown peer metadata version: %d", ver);
2707 		fallthrough;
2708 	case ATH12K_PEER_METADATA_V0:
2709 		return le32_get_bits(peer_metadata,
2710 				     RX_MPDU_DESC_META_DATA_V0_PEER_ID);
2711 	case ATH12K_PEER_METADATA_V1:
2712 		return le32_get_bits(peer_metadata,
2713 				     RX_MPDU_DESC_META_DATA_V1_PEER_ID);
2714 	case ATH12K_PEER_METADATA_V1A:
2715 		return le32_get_bits(peer_metadata,
2716 				     RX_MPDU_DESC_META_DATA_V1A_PEER_ID);
2717 	case ATH12K_PEER_METADATA_V1B:
2718 		return le32_get_bits(peer_metadata,
2719 				     RX_MPDU_DESC_META_DATA_V1B_PEER_ID);
2720 	}
2721 }
2722 
ath12k_dp_rx_process(struct ath12k_base * ab,int ring_id,struct napi_struct * napi,int budget)2723 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id,
2724 			 struct napi_struct *napi, int budget)
2725 {
2726 	struct ath12k_hw_group *ag = ab->ag;
2727 	struct list_head rx_desc_used_list[ATH12K_MAX_SOCS];
2728 	struct ath12k_hw_link *hw_links = ag->hw_links;
2729 	int num_buffs_reaped[ATH12K_MAX_SOCS] = {};
2730 	struct ath12k_rx_desc_info *desc_info;
2731 	struct ath12k_dp *dp = &ab->dp;
2732 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
2733 	struct hal_reo_dest_ring *desc;
2734 	struct ath12k_base *partner_ab;
2735 	struct sk_buff_head msdu_list;
2736 	struct ath12k_skb_rxcb *rxcb;
2737 	int total_msdu_reaped = 0;
2738 	u8 hw_link_id, device_id;
2739 	struct hal_srng *srng;
2740 	struct sk_buff *msdu;
2741 	bool done = false;
2742 	u64 desc_va;
2743 
2744 	__skb_queue_head_init(&msdu_list);
2745 
2746 	for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++)
2747 		INIT_LIST_HEAD(&rx_desc_used_list[device_id]);
2748 
2749 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2750 
2751 	spin_lock_bh(&srng->lock);
2752 
2753 try_again:
2754 	ath12k_hal_srng_access_begin(ab, srng);
2755 
2756 	while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
2757 		struct rx_mpdu_desc *mpdu_info;
2758 		struct rx_msdu_desc *msdu_info;
2759 		enum hal_reo_dest_ring_push_reason push_reason;
2760 		u32 cookie;
2761 
2762 		cookie = le32_get_bits(desc->buf_addr_info.info1,
2763 				       BUFFER_ADDR_INFO1_SW_COOKIE);
2764 
2765 		hw_link_id = le32_get_bits(desc->info0,
2766 					   HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
2767 
2768 		desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
2769 			   le32_to_cpu(desc->buf_va_lo));
2770 		desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
2771 
2772 		device_id = hw_links[hw_link_id].device_id;
2773 		partner_ab = ath12k_ag_to_ab(ag, device_id);
2774 		if (unlikely(!partner_ab)) {
2775 			if (desc_info->skb) {
2776 				dev_kfree_skb_any(desc_info->skb);
2777 				desc_info->skb = NULL;
2778 			}
2779 
2780 			continue;
2781 		}
2782 
2783 		/* retry manual desc retrieval */
2784 		if (!desc_info) {
2785 			desc_info = ath12k_dp_get_rx_desc(partner_ab, cookie);
2786 			if (!desc_info) {
2787 				ath12k_warn(partner_ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n",
2788 					    cookie);
2789 				continue;
2790 			}
2791 		}
2792 
2793 		if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
2794 			ath12k_warn(ab, "Check HW CC implementation");
2795 
2796 		msdu = desc_info->skb;
2797 		desc_info->skb = NULL;
2798 
2799 		list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]);
2800 
2801 		rxcb = ATH12K_SKB_RXCB(msdu);
2802 		dma_unmap_single(partner_ab->dev, rxcb->paddr,
2803 				 msdu->len + skb_tailroom(msdu),
2804 				 DMA_FROM_DEVICE);
2805 
2806 		num_buffs_reaped[device_id]++;
2807 
2808 		push_reason = le32_get_bits(desc->info0,
2809 					    HAL_REO_DEST_RING_INFO0_PUSH_REASON);
2810 		if (push_reason !=
2811 		    HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2812 			dev_kfree_skb_any(msdu);
2813 			ab->soc_stats.hal_reo_error[ring_id]++;
2814 			continue;
2815 		}
2816 
2817 		msdu_info = &desc->rx_msdu_info;
2818 		mpdu_info = &desc->rx_mpdu_info;
2819 
2820 		rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) &
2821 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2822 		rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) &
2823 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2824 		rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) &
2825 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2826 		rxcb->hw_link_id = hw_link_id;
2827 		rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver,
2828 							 mpdu_info->peer_meta_data);
2829 		rxcb->tid = le32_get_bits(mpdu_info->info0,
2830 					  RX_MPDU_DESC_INFO0_TID);
2831 
2832 		__skb_queue_tail(&msdu_list, msdu);
2833 
2834 		if (!rxcb->is_continuation) {
2835 			total_msdu_reaped++;
2836 			done = true;
2837 		} else {
2838 			done = false;
2839 		}
2840 
2841 		if (total_msdu_reaped >= budget)
2842 			break;
2843 	}
2844 
2845 	/* Hw might have updated the head pointer after we cached it.
2846 	 * In this case, even though there are entries in the ring we'll
2847 	 * get rx_desc NULL. Give the read another try with updated cached
2848 	 * head pointer so that we can reap complete MPDU in the current
2849 	 * rx processing.
2850 	 */
2851 	if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) {
2852 		ath12k_hal_srng_access_end(ab, srng);
2853 		goto try_again;
2854 	}
2855 
2856 	ath12k_hal_srng_access_end(ab, srng);
2857 
2858 	spin_unlock_bh(&srng->lock);
2859 
2860 	if (!total_msdu_reaped)
2861 		goto exit;
2862 
2863 	for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++) {
2864 		if (!num_buffs_reaped[device_id])
2865 			continue;
2866 
2867 		partner_ab = ath12k_ag_to_ab(ag, device_id);
2868 		rx_ring = &partner_ab->dp.rx_refill_buf_ring;
2869 
2870 		ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring,
2871 					    &rx_desc_used_list[device_id],
2872 					    num_buffs_reaped[device_id]);
2873 	}
2874 
2875 	ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2876 					      ring_id);
2877 
2878 exit:
2879 	return total_msdu_reaped;
2880 }
2881 
ath12k_dp_rx_frag_timer(struct timer_list * timer)2882 static void ath12k_dp_rx_frag_timer(struct timer_list *timer)
2883 {
2884 	struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
2885 
2886 	spin_lock_bh(&rx_tid->ab->base_lock);
2887 	if (rx_tid->last_frag_no &&
2888 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
2889 		spin_unlock_bh(&rx_tid->ab->base_lock);
2890 		return;
2891 	}
2892 	ath12k_dp_rx_frags_cleanup(rx_tid, true);
2893 	spin_unlock_bh(&rx_tid->ab->base_lock);
2894 }
2895 
ath12k_dp_rx_peer_frag_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id)2896 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id)
2897 {
2898 	struct ath12k_base *ab = ar->ab;
2899 	struct crypto_shash *tfm;
2900 	struct ath12k_peer *peer;
2901 	struct ath12k_dp_rx_tid *rx_tid;
2902 	int i;
2903 
2904 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
2905 	if (IS_ERR(tfm))
2906 		return PTR_ERR(tfm);
2907 
2908 	spin_lock_bh(&ab->base_lock);
2909 
2910 	peer = ath12k_peer_find(ab, vdev_id, peer_mac);
2911 	if (!peer) {
2912 		spin_unlock_bh(&ab->base_lock);
2913 		crypto_free_shash(tfm);
2914 		ath12k_warn(ab, "failed to find the peer to set up fragment info\n");
2915 		return -ENOENT;
2916 	}
2917 
2918 	if (!peer->primary_link) {
2919 		spin_unlock_bh(&ab->base_lock);
2920 		crypto_free_shash(tfm);
2921 		return 0;
2922 	}
2923 
2924 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
2925 		rx_tid = &peer->rx_tid[i];
2926 		rx_tid->ab = ab;
2927 		timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0);
2928 		skb_queue_head_init(&rx_tid->rx_frags);
2929 	}
2930 
2931 	peer->tfm_mmic = tfm;
2932 	peer->dp_setup_done = true;
2933 	spin_unlock_bh(&ab->base_lock);
2934 
2935 	return 0;
2936 }
2937 
ath12k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)2938 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
2939 				      struct ieee80211_hdr *hdr, u8 *data,
2940 				      size_t data_len, u8 *mic)
2941 {
2942 	SHASH_DESC_ON_STACK(desc, tfm);
2943 	u8 mic_hdr[16] = {0};
2944 	u8 tid = 0;
2945 	int ret;
2946 
2947 	if (!tfm)
2948 		return -EINVAL;
2949 
2950 	desc->tfm = tfm;
2951 
2952 	ret = crypto_shash_setkey(tfm, key, 8);
2953 	if (ret)
2954 		goto out;
2955 
2956 	ret = crypto_shash_init(desc);
2957 	if (ret)
2958 		goto out;
2959 
2960 	/* TKIP MIC header */
2961 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
2962 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
2963 	if (ieee80211_is_data_qos(hdr->frame_control))
2964 		tid = ieee80211_get_tid(hdr);
2965 	mic_hdr[12] = tid;
2966 
2967 	ret = crypto_shash_update(desc, mic_hdr, 16);
2968 	if (ret)
2969 		goto out;
2970 	ret = crypto_shash_update(desc, data, data_len);
2971 	if (ret)
2972 		goto out;
2973 	ret = crypto_shash_final(desc, mic);
2974 out:
2975 	shash_desc_zero(desc);
2976 	return ret;
2977 }
2978 
ath12k_dp_rx_h_verify_tkip_mic(struct ath12k * ar,struct ath12k_peer * peer,struct sk_buff * msdu)2979 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer,
2980 					  struct sk_buff *msdu)
2981 {
2982 	struct ath12k_base *ab = ar->ab;
2983 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
2984 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
2985 	struct ieee80211_key_conf *key_conf;
2986 	struct ieee80211_hdr *hdr;
2987 	u8 mic[IEEE80211_CCMP_MIC_LEN];
2988 	int head_len, tail_len, ret;
2989 	size_t data_len;
2990 	u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2991 	u8 *key, *data;
2992 	u8 key_idx;
2993 
2994 	if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
2995 		return 0;
2996 
2997 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
2998 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2999 	head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3000 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3001 
3002 	if (!is_multicast_ether_addr(hdr->addr1))
3003 		key_idx = peer->ucast_keyidx;
3004 	else
3005 		key_idx = peer->mcast_keyidx;
3006 
3007 	key_conf = peer->keys[key_idx];
3008 
3009 	data = msdu->data + head_len;
3010 	data_len = msdu->len - head_len - tail_len;
3011 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3012 
3013 	ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3014 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3015 		goto mic_fail;
3016 
3017 	return 0;
3018 
3019 mic_fail:
3020 	(ATH12K_SKB_RXCB(msdu))->is_first_msdu = true;
3021 	(ATH12K_SKB_RXCB(msdu))->is_last_msdu = true;
3022 
3023 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3024 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3025 	skb_pull(msdu, hal_rx_desc_sz);
3026 
3027 	if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu)))
3028 		return -EINVAL;
3029 
3030 	ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3031 	ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
3032 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3033 	ieee80211_rx(ath12k_ar_to_hw(ar), msdu);
3034 	return -EINVAL;
3035 }
3036 
ath12k_dp_rx_h_undecap_frag(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3037 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu,
3038 					enum hal_encrypt_type enctype, u32 flags)
3039 {
3040 	struct ieee80211_hdr *hdr;
3041 	size_t hdr_len;
3042 	size_t crypto_len;
3043 	u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3044 
3045 	if (!flags)
3046 		return;
3047 
3048 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3049 
3050 	if (flags & RX_FLAG_MIC_STRIPPED)
3051 		skb_trim(msdu, msdu->len -
3052 			 ath12k_dp_rx_crypto_mic_len(ar, enctype));
3053 
3054 	if (flags & RX_FLAG_ICV_STRIPPED)
3055 		skb_trim(msdu, msdu->len -
3056 			 ath12k_dp_rx_crypto_icv_len(ar, enctype));
3057 
3058 	if (flags & RX_FLAG_IV_STRIPPED) {
3059 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3060 		crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
3061 
3062 		memmove(msdu->data + hal_rx_desc_sz + crypto_len,
3063 			msdu->data + hal_rx_desc_sz, hdr_len);
3064 		skb_pull(msdu, crypto_len);
3065 	}
3066 }
3067 
ath12k_dp_rx_h_defrag(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3068 static int ath12k_dp_rx_h_defrag(struct ath12k *ar,
3069 				 struct ath12k_peer *peer,
3070 				 struct ath12k_dp_rx_tid *rx_tid,
3071 				 struct sk_buff **defrag_skb)
3072 {
3073 	struct ath12k_base *ab = ar->ab;
3074 	struct hal_rx_desc *rx_desc;
3075 	struct sk_buff *skb, *first_frag, *last_frag;
3076 	struct ieee80211_hdr *hdr;
3077 	enum hal_encrypt_type enctype;
3078 	bool is_decrypted = false;
3079 	int msdu_len = 0;
3080 	int extra_space;
3081 	u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3082 
3083 	first_frag = skb_peek(&rx_tid->rx_frags);
3084 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3085 
3086 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3087 		flags = 0;
3088 		rx_desc = (struct hal_rx_desc *)skb->data;
3089 		hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3090 
3091 		enctype = ath12k_dp_rx_h_enctype(ab, rx_desc);
3092 		if (enctype != HAL_ENCRYPT_TYPE_OPEN)
3093 			is_decrypted = ath12k_dp_rx_h_is_decrypted(ab,
3094 								   rx_desc);
3095 
3096 		if (is_decrypted) {
3097 			if (skb != first_frag)
3098 				flags |= RX_FLAG_IV_STRIPPED;
3099 			if (skb != last_frag)
3100 				flags |= RX_FLAG_ICV_STRIPPED |
3101 					 RX_FLAG_MIC_STRIPPED;
3102 		}
3103 
3104 		/* RX fragments are always raw packets */
3105 		if (skb != last_frag)
3106 			skb_trim(skb, skb->len - FCS_LEN);
3107 		ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3108 
3109 		if (skb != first_frag)
3110 			skb_pull(skb, hal_rx_desc_sz +
3111 				      ieee80211_hdrlen(hdr->frame_control));
3112 		msdu_len += skb->len;
3113 	}
3114 
3115 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3116 	if (extra_space > 0 &&
3117 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3118 		return -ENOMEM;
3119 
3120 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3121 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3122 		skb_put_data(first_frag, skb->data, skb->len);
3123 		dev_kfree_skb_any(skb);
3124 	}
3125 
3126 	hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3127 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3128 	ATH12K_SKB_RXCB(first_frag)->is_frag = 1;
3129 
3130 	if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3131 		first_frag = NULL;
3132 
3133 	*defrag_skb = first_frag;
3134 	return 0;
3135 }
3136 
ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3137 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar,
3138 					      struct ath12k_dp_rx_tid *rx_tid,
3139 					      struct sk_buff *defrag_skb)
3140 {
3141 	struct ath12k_base *ab = ar->ab;
3142 	struct ath12k_dp *dp = &ab->dp;
3143 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3144 	struct hal_reo_entrance_ring *reo_ent_ring;
3145 	struct hal_reo_dest_ring *reo_dest_ring;
3146 	struct dp_link_desc_bank *link_desc_banks;
3147 	struct hal_rx_msdu_link *msdu_link;
3148 	struct hal_rx_msdu_details *msdu0;
3149 	struct hal_srng *srng;
3150 	dma_addr_t link_paddr, buf_paddr;
3151 	u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info;
3152 	u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi;
3153 	int ret;
3154 	struct ath12k_rx_desc_info *desc_info;
3155 	enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm;
3156 	u8 dst_ind;
3157 
3158 	hal_rx_desc_sz = ab->hal.hal_desc_sz;
3159 	link_desc_banks = dp->link_desc_banks;
3160 	reo_dest_ring = rx_tid->dst_ring_desc;
3161 
3162 	ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info,
3163 					&link_paddr, &cookie);
3164 	desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK);
3165 
3166 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3167 			(link_paddr - link_desc_banks[desc_bank].paddr));
3168 	msdu0 = &msdu_link->msdu_link[0];
3169 	msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0);
3170 	dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND);
3171 
3172 	memset(msdu0, 0, sizeof(*msdu0));
3173 
3174 	msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) |
3175 		    u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) |
3176 		    u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) |
3177 		    u32_encode_bits(defrag_skb->len - hal_rx_desc_sz,
3178 				    RX_MSDU_DESC_INFO0_MSDU_LENGTH) |
3179 		    u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) |
3180 		    u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA);
3181 	msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info);
3182 	msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info);
3183 
3184 	/* change msdu len in hal rx desc */
3185 	ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3186 
3187 	buf_paddr = dma_map_single(ab->dev, defrag_skb->data,
3188 				   defrag_skb->len + skb_tailroom(defrag_skb),
3189 				   DMA_TO_DEVICE);
3190 	if (dma_mapping_error(ab->dev, buf_paddr))
3191 		return -ENOMEM;
3192 
3193 	spin_lock_bh(&dp->rx_desc_lock);
3194 	desc_info = list_first_entry_or_null(&dp->rx_desc_free_list,
3195 					     struct ath12k_rx_desc_info,
3196 					     list);
3197 	if (!desc_info) {
3198 		spin_unlock_bh(&dp->rx_desc_lock);
3199 		ath12k_warn(ab, "failed to find rx desc for reinject\n");
3200 		ret = -ENOMEM;
3201 		goto err_unmap_dma;
3202 	}
3203 
3204 	desc_info->skb = defrag_skb;
3205 	desc_info->in_use = true;
3206 
3207 	list_del(&desc_info->list);
3208 	spin_unlock_bh(&dp->rx_desc_lock);
3209 
3210 	ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr;
3211 
3212 	ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr,
3213 					desc_info->cookie,
3214 					HAL_RX_BUF_RBM_SW3_BM);
3215 
3216 	/* Fill mpdu details into reo entrance ring */
3217 	srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id];
3218 
3219 	spin_lock_bh(&srng->lock);
3220 	ath12k_hal_srng_access_begin(ab, srng);
3221 
3222 	reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng);
3223 	if (!reo_ent_ring) {
3224 		ath12k_hal_srng_access_end(ab, srng);
3225 		spin_unlock_bh(&srng->lock);
3226 		ret = -ENOSPC;
3227 		goto err_free_desc;
3228 	}
3229 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3230 
3231 	ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr,
3232 					cookie,
3233 					idle_link_rbm);
3234 
3235 	mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) |
3236 		    u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) |
3237 		    u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) |
3238 		    u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) |
3239 		    u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID);
3240 
3241 	reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info);
3242 	reo_ent_ring->rx_mpdu_info.peer_meta_data =
3243 		reo_dest_ring->rx_mpdu_info.peer_meta_data;
3244 
3245 	reo_ent_ring->queue_addr_lo = cpu_to_le32(lower_32_bits(rx_tid->paddr));
3246 	queue_addr_hi = upper_32_bits(rx_tid->paddr);
3247 	reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi,
3248 					       HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) |
3249 			      le32_encode_bits(dst_ind,
3250 					       HAL_REO_ENTR_RING_INFO0_DEST_IND);
3251 
3252 	reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn,
3253 					       HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM);
3254 	dest_ring_info0 = le32_get_bits(reo_dest_ring->info0,
3255 					HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3256 	reo_ent_ring->info2 =
3257 		cpu_to_le32(u32_get_bits(dest_ring_info0,
3258 					 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID));
3259 
3260 	ath12k_hal_srng_access_end(ab, srng);
3261 	spin_unlock_bh(&srng->lock);
3262 
3263 	return 0;
3264 
3265 err_free_desc:
3266 	spin_lock_bh(&dp->rx_desc_lock);
3267 	desc_info->in_use = false;
3268 	desc_info->skb = NULL;
3269 	list_add_tail(&desc_info->list, &dp->rx_desc_free_list);
3270 	spin_unlock_bh(&dp->rx_desc_lock);
3271 err_unmap_dma:
3272 	dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3273 			 DMA_TO_DEVICE);
3274 	return ret;
3275 }
3276 
ath12k_dp_rx_h_cmp_frags(struct ath12k_base * ab,struct sk_buff * a,struct sk_buff * b)3277 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab,
3278 				    struct sk_buff *a, struct sk_buff *b)
3279 {
3280 	int frag1, frag2;
3281 
3282 	frag1 = ath12k_dp_rx_h_frag_no(ab, a);
3283 	frag2 = ath12k_dp_rx_h_frag_no(ab, b);
3284 
3285 	return frag1 - frag2;
3286 }
3287 
ath12k_dp_rx_h_sort_frags(struct ath12k_base * ab,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3288 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab,
3289 				      struct sk_buff_head *frag_list,
3290 				      struct sk_buff *cur_frag)
3291 {
3292 	struct sk_buff *skb;
3293 	int cmp;
3294 
3295 	skb_queue_walk(frag_list, skb) {
3296 		cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag);
3297 		if (cmp < 0)
3298 			continue;
3299 		__skb_queue_before(frag_list, skb, cur_frag);
3300 		return;
3301 	}
3302 	__skb_queue_tail(frag_list, cur_frag);
3303 }
3304 
ath12k_dp_rx_h_get_pn(struct ath12k * ar,struct sk_buff * skb)3305 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb)
3306 {
3307 	struct ieee80211_hdr *hdr;
3308 	u64 pn = 0;
3309 	u8 *ehdr;
3310 	u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3311 
3312 	hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3313 	ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3314 
3315 	pn = ehdr[0];
3316 	pn |= (u64)ehdr[1] << 8;
3317 	pn |= (u64)ehdr[4] << 16;
3318 	pn |= (u64)ehdr[5] << 24;
3319 	pn |= (u64)ehdr[6] << 32;
3320 	pn |= (u64)ehdr[7] << 40;
3321 
3322 	return pn;
3323 }
3324 
3325 static bool
ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid)3326 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid)
3327 {
3328 	struct ath12k_base *ab = ar->ab;
3329 	enum hal_encrypt_type encrypt_type;
3330 	struct sk_buff *first_frag, *skb;
3331 	struct hal_rx_desc *desc;
3332 	u64 last_pn;
3333 	u64 cur_pn;
3334 
3335 	first_frag = skb_peek(&rx_tid->rx_frags);
3336 	desc = (struct hal_rx_desc *)first_frag->data;
3337 
3338 	encrypt_type = ath12k_dp_rx_h_enctype(ab, desc);
3339 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3340 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3341 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3342 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3343 		return true;
3344 
3345 	last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag);
3346 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3347 		if (skb == first_frag)
3348 			continue;
3349 
3350 		cur_pn = ath12k_dp_rx_h_get_pn(ar, skb);
3351 		if (cur_pn != last_pn + 1)
3352 			return false;
3353 		last_pn = cur_pn;
3354 	}
3355 	return true;
3356 }
3357 
ath12k_dp_rx_frag_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_reo_dest_ring * ring_desc)3358 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar,
3359 				    struct sk_buff *msdu,
3360 				    struct hal_reo_dest_ring *ring_desc)
3361 {
3362 	struct ath12k_base *ab = ar->ab;
3363 	struct hal_rx_desc *rx_desc;
3364 	struct ath12k_peer *peer;
3365 	struct ath12k_dp_rx_tid *rx_tid;
3366 	struct sk_buff *defrag_skb = NULL;
3367 	u32 peer_id;
3368 	u16 seqno, frag_no;
3369 	u8 tid;
3370 	int ret = 0;
3371 	bool more_frags;
3372 
3373 	rx_desc = (struct hal_rx_desc *)msdu->data;
3374 	peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc);
3375 	tid = ath12k_dp_rx_h_tid(ab, rx_desc);
3376 	seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc);
3377 	frag_no = ath12k_dp_rx_h_frag_no(ab, msdu);
3378 	more_frags = ath12k_dp_rx_h_more_frags(ab, msdu);
3379 
3380 	if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) ||
3381 	    !ath12k_dp_rx_h_fc_valid(ab, rx_desc) ||
3382 	    tid > IEEE80211_NUM_TIDS)
3383 		return -EINVAL;
3384 
3385 	/* received unfragmented packet in reo
3386 	 * exception ring, this shouldn't happen
3387 	 * as these packets typically come from
3388 	 * reo2sw srngs.
3389 	 */
3390 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3391 		return -EINVAL;
3392 
3393 	spin_lock_bh(&ab->base_lock);
3394 	peer = ath12k_peer_find_by_id(ab, peer_id);
3395 	if (!peer) {
3396 		ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3397 			    peer_id);
3398 		ret = -ENOENT;
3399 		goto out_unlock;
3400 	}
3401 
3402 	if (!peer->dp_setup_done) {
3403 		ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3404 			    peer->addr, peer_id);
3405 		ret = -ENOENT;
3406 		goto out_unlock;
3407 	}
3408 
3409 	rx_tid = &peer->rx_tid[tid];
3410 
3411 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3412 	    skb_queue_empty(&rx_tid->rx_frags)) {
3413 		/* Flush stored fragments and start a new sequence */
3414 		ath12k_dp_rx_frags_cleanup(rx_tid, true);
3415 		rx_tid->cur_sn = seqno;
3416 	}
3417 
3418 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3419 		/* Fragment already present */
3420 		ret = -EINVAL;
3421 		goto out_unlock;
3422 	}
3423 
3424 	if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap)))
3425 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3426 	else
3427 		ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu);
3428 
3429 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3430 	if (!more_frags)
3431 		rx_tid->last_frag_no = frag_no;
3432 
3433 	if (frag_no == 0) {
3434 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3435 						sizeof(*rx_tid->dst_ring_desc),
3436 						GFP_ATOMIC);
3437 		if (!rx_tid->dst_ring_desc) {
3438 			ret = -ENOMEM;
3439 			goto out_unlock;
3440 		}
3441 	} else {
3442 		ath12k_dp_rx_link_desc_return(ab, ring_desc,
3443 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3444 	}
3445 
3446 	if (!rx_tid->last_frag_no ||
3447 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3448 		mod_timer(&rx_tid->frag_timer, jiffies +
3449 					       ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS);
3450 		goto out_unlock;
3451 	}
3452 
3453 	spin_unlock_bh(&ab->base_lock);
3454 	del_timer_sync(&rx_tid->frag_timer);
3455 	spin_lock_bh(&ab->base_lock);
3456 
3457 	peer = ath12k_peer_find_by_id(ab, peer_id);
3458 	if (!peer)
3459 		goto err_frags_cleanup;
3460 
3461 	if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3462 		goto err_frags_cleanup;
3463 
3464 	if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3465 		goto err_frags_cleanup;
3466 
3467 	if (!defrag_skb)
3468 		goto err_frags_cleanup;
3469 
3470 	if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3471 		goto err_frags_cleanup;
3472 
3473 	ath12k_dp_rx_frags_cleanup(rx_tid, false);
3474 	goto out_unlock;
3475 
3476 err_frags_cleanup:
3477 	dev_kfree_skb_any(defrag_skb);
3478 	ath12k_dp_rx_frags_cleanup(rx_tid, true);
3479 out_unlock:
3480 	spin_unlock_bh(&ab->base_lock);
3481 	return ret;
3482 }
3483 
3484 static int
ath12k_dp_process_rx_err_buf(struct ath12k * ar,struct hal_reo_dest_ring * desc,struct list_head * used_list,bool drop,u32 cookie)3485 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc,
3486 			     struct list_head *used_list,
3487 			     bool drop, u32 cookie)
3488 {
3489 	struct ath12k_base *ab = ar->ab;
3490 	struct sk_buff *msdu;
3491 	struct ath12k_skb_rxcb *rxcb;
3492 	struct hal_rx_desc *rx_desc;
3493 	u16 msdu_len;
3494 	u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
3495 	struct ath12k_rx_desc_info *desc_info;
3496 	u64 desc_va;
3497 
3498 	desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
3499 		   le32_to_cpu(desc->buf_va_lo));
3500 	desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
3501 
3502 	/* retry manual desc retrieval */
3503 	if (!desc_info) {
3504 		desc_info = ath12k_dp_get_rx_desc(ab, cookie);
3505 		if (!desc_info) {
3506 			ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n",
3507 				    cookie);
3508 			return -EINVAL;
3509 		}
3510 	}
3511 
3512 	if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3513 		ath12k_warn(ab, " RX Exception, Check HW CC implementation");
3514 
3515 	msdu = desc_info->skb;
3516 	desc_info->skb = NULL;
3517 
3518 	list_add_tail(&desc_info->list, used_list);
3519 
3520 	rxcb = ATH12K_SKB_RXCB(msdu);
3521 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3522 			 msdu->len + skb_tailroom(msdu),
3523 			 DMA_FROM_DEVICE);
3524 
3525 	if (drop) {
3526 		dev_kfree_skb_any(msdu);
3527 		return 0;
3528 	}
3529 
3530 	rcu_read_lock();
3531 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3532 		dev_kfree_skb_any(msdu);
3533 		goto exit;
3534 	}
3535 
3536 	if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) {
3537 		dev_kfree_skb_any(msdu);
3538 		goto exit;
3539 	}
3540 
3541 	rx_desc = (struct hal_rx_desc *)msdu->data;
3542 	msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc);
3543 	if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3544 		ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3545 		ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
3546 				sizeof(*rx_desc));
3547 		dev_kfree_skb_any(msdu);
3548 		goto exit;
3549 	}
3550 
3551 	skb_put(msdu, hal_rx_desc_sz + msdu_len);
3552 
3553 	if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) {
3554 		dev_kfree_skb_any(msdu);
3555 		ath12k_dp_rx_link_desc_return(ar->ab, desc,
3556 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3557 	}
3558 exit:
3559 	rcu_read_unlock();
3560 	return 0;
3561 }
3562 
ath12k_dp_rx_process_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3563 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi,
3564 			     int budget)
3565 {
3566 	struct ath12k_hw_group *ag = ab->ag;
3567 	struct list_head rx_desc_used_list[ATH12K_MAX_SOCS];
3568 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3569 	int num_buffs_reaped[ATH12K_MAX_SOCS] = {};
3570 	struct dp_link_desc_bank *link_desc_banks;
3571 	enum hal_rx_buf_return_buf_manager rbm;
3572 	struct hal_rx_msdu_link *link_desc_va;
3573 	int tot_n_bufs_reaped, quota, ret, i;
3574 	struct hal_reo_dest_ring *reo_desc;
3575 	struct dp_rxdma_ring *rx_ring;
3576 	struct dp_srng *reo_except;
3577 	struct ath12k_hw_link *hw_links = ag->hw_links;
3578 	struct ath12k_base *partner_ab;
3579 	u8 hw_link_id, device_id;
3580 	u32 desc_bank, num_msdus;
3581 	struct hal_srng *srng;
3582 	struct ath12k *ar;
3583 	dma_addr_t paddr;
3584 	bool is_frag;
3585 	bool drop;
3586 	int pdev_id;
3587 
3588 	tot_n_bufs_reaped = 0;
3589 	quota = budget;
3590 
3591 	for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++)
3592 		INIT_LIST_HEAD(&rx_desc_used_list[device_id]);
3593 
3594 	reo_except = &ab->dp.reo_except_ring;
3595 
3596 	srng = &ab->hal.srng_list[reo_except->ring_id];
3597 
3598 	spin_lock_bh(&srng->lock);
3599 
3600 	ath12k_hal_srng_access_begin(ab, srng);
3601 
3602 	while (budget &&
3603 	       (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
3604 		drop = false;
3605 		ab->soc_stats.err_ring_pkts++;
3606 
3607 		ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr,
3608 						    &desc_bank);
3609 		if (ret) {
3610 			ath12k_warn(ab, "failed to parse error reo desc %d\n",
3611 				    ret);
3612 			continue;
3613 		}
3614 
3615 		hw_link_id = le32_get_bits(reo_desc->info0,
3616 					   HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3617 		device_id = hw_links[hw_link_id].device_id;
3618 		partner_ab = ath12k_ag_to_ab(ag, device_id);
3619 
3620 		pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params,
3621 						      hw_links[hw_link_id].pdev_idx);
3622 		ar = partner_ab->pdevs[pdev_id].ar;
3623 
3624 		link_desc_banks = partner_ab->dp.link_desc_banks;
3625 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3626 			       (paddr - link_desc_banks[desc_bank].paddr);
3627 		ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3628 						 &rbm);
3629 		if (rbm != partner_ab->dp.idle_link_rbm &&
3630 		    rbm != HAL_RX_BUF_RBM_SW3_BM &&
3631 		    rbm != partner_ab->hw_params->hal_params->rx_buf_rbm) {
3632 			ab->soc_stats.invalid_rbm++;
3633 			ath12k_warn(ab, "invalid return buffer manager %d\n", rbm);
3634 			ath12k_dp_rx_link_desc_return(partner_ab, reo_desc,
3635 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3636 			continue;
3637 		}
3638 
3639 		is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) &
3640 			     RX_MPDU_DESC_INFO0_FRAG_FLAG);
3641 
3642 		/* Process only rx fragments with one msdu per link desc below, and drop
3643 		 * msdu's indicated due to error reasons.
3644 		 * Dynamic fragmentation not supported in Multi-link client, so drop the
3645 		 * partner device buffers.
3646 		 */
3647 		if (!is_frag || num_msdus > 1 ||
3648 		    partner_ab->device_id != ab->device_id) {
3649 			drop = true;
3650 
3651 			/* Return the link desc back to wbm idle list */
3652 			ath12k_dp_rx_link_desc_return(partner_ab, reo_desc,
3653 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3654 		}
3655 
3656 		for (i = 0; i < num_msdus; i++) {
3657 			if (!ath12k_dp_process_rx_err_buf(ar, reo_desc,
3658 							  &rx_desc_used_list[device_id],
3659 							  drop,
3660 							  msdu_cookies[i])) {
3661 				num_buffs_reaped[device_id]++;
3662 				tot_n_bufs_reaped++;
3663 			}
3664 		}
3665 
3666 		if (tot_n_bufs_reaped >= quota) {
3667 			tot_n_bufs_reaped = quota;
3668 			goto exit;
3669 		}
3670 
3671 		budget = quota - tot_n_bufs_reaped;
3672 	}
3673 
3674 exit:
3675 	ath12k_hal_srng_access_end(ab, srng);
3676 
3677 	spin_unlock_bh(&srng->lock);
3678 
3679 	for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++) {
3680 		if (!num_buffs_reaped[device_id])
3681 			continue;
3682 
3683 		partner_ab = ath12k_ag_to_ab(ag, device_id);
3684 		rx_ring = &partner_ab->dp.rx_refill_buf_ring;
3685 
3686 		ath12k_dp_rx_bufs_replenish(partner_ab, rx_ring,
3687 					    &rx_desc_used_list[device_id],
3688 					    num_buffs_reaped[device_id]);
3689 	}
3690 
3691 	return tot_n_bufs_reaped;
3692 }
3693 
ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k * ar,int msdu_len,struct sk_buff_head * msdu_list)3694 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar,
3695 					     int msdu_len,
3696 					     struct sk_buff_head *msdu_list)
3697 {
3698 	struct sk_buff *skb, *tmp;
3699 	struct ath12k_skb_rxcb *rxcb;
3700 	int n_buffs;
3701 
3702 	n_buffs = DIV_ROUND_UP(msdu_len,
3703 			       (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz));
3704 
3705 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3706 		rxcb = ATH12K_SKB_RXCB(skb);
3707 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3708 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3709 			if (!n_buffs)
3710 				break;
3711 			__skb_unlink(skb, msdu_list);
3712 			dev_kfree_skb_any(skb);
3713 			n_buffs--;
3714 		}
3715 	}
3716 }
3717 
ath12k_dp_rx_h_null_q_desc(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3718 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu,
3719 				      struct ieee80211_rx_status *status,
3720 				      struct sk_buff_head *msdu_list)
3721 {
3722 	struct ath12k_base *ab = ar->ab;
3723 	u16 msdu_len;
3724 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3725 	u8 l3pad_bytes;
3726 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3727 	u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3728 
3729 	msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3730 
3731 	if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3732 		/* First buffer will be freed by the caller, so deduct it's length */
3733 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3734 		ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3735 		return -EINVAL;
3736 	}
3737 
3738 	/* Even after cleaning up the sg buffers in the msdu list with above check
3739 	 * any msdu received with continuation flag needs to be dropped as invalid.
3740 	 * This protects against some random err frame with continuation flag.
3741 	 */
3742 	if (rxcb->is_continuation)
3743 		return -EINVAL;
3744 
3745 	if (!ath12k_dp_rx_h_msdu_done(ab, desc)) {
3746 		ath12k_warn(ar->ab,
3747 			    "msdu_done bit not set in null_q_des processing\n");
3748 		__skb_queue_purge(msdu_list);
3749 		return -EIO;
3750 	}
3751 
3752 	/* Handle NULL queue descriptor violations arising out a missing
3753 	 * REO queue for a given peer or a given TID. This typically
3754 	 * may happen if a packet is received on a QOS enabled TID before the
3755 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3756 	 * it may also happen for MC/BC frames if they are not routed to the
3757 	 * non-QOS TID queue, in the absence of any other default TID queue.
3758 	 * This error can show up both in a REO destination or WBM release ring.
3759 	 */
3760 
3761 	if (rxcb->is_frag) {
3762 		skb_pull(msdu, hal_rx_desc_sz);
3763 	} else {
3764 		l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3765 
3766 		if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3767 			return -EINVAL;
3768 
3769 		skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3770 		skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3771 	}
3772 	if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
3773 		return -EINVAL;
3774 
3775 	ath12k_dp_rx_h_ppdu(ar, desc, status);
3776 
3777 	ath12k_dp_rx_h_mpdu(ar, msdu, desc, status);
3778 
3779 	rxcb->tid = ath12k_dp_rx_h_tid(ab, desc);
3780 
3781 	/* Please note that caller will having the access to msdu and completing
3782 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3783 	 */
3784 
3785 	return 0;
3786 }
3787 
ath12k_dp_rx_h_reo_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3788 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu,
3789 				   struct ieee80211_rx_status *status,
3790 				   struct sk_buff_head *msdu_list)
3791 {
3792 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3793 	bool drop = false;
3794 
3795 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3796 
3797 	switch (rxcb->err_code) {
3798 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3799 		if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3800 			drop = true;
3801 		break;
3802 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3803 		/* TODO: Do not drop PN failed packets in the driver;
3804 		 * instead, it is good to drop such packets in mac80211
3805 		 * after incrementing the replay counters.
3806 		 */
3807 		fallthrough;
3808 	default:
3809 		/* TODO: Review other errors and process them to mac80211
3810 		 * as appropriate.
3811 		 */
3812 		drop = true;
3813 		break;
3814 	}
3815 
3816 	return drop;
3817 }
3818 
ath12k_dp_rx_h_tkip_mic_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3819 static bool ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu,
3820 					struct ieee80211_rx_status *status)
3821 {
3822 	struct ath12k_base *ab = ar->ab;
3823 	u16 msdu_len;
3824 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3825 	u8 l3pad_bytes;
3826 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3827 	u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3828 
3829 	rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc);
3830 	rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc);
3831 
3832 	l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3833 	msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3834 	skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3835 	skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3836 
3837 	if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
3838 		return true;
3839 
3840 	ath12k_dp_rx_h_ppdu(ar, desc, status);
3841 
3842 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3843 			 RX_FLAG_DECRYPTED);
3844 
3845 	ath12k_dp_rx_h_undecap(ar, msdu, desc,
3846 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3847 	return false;
3848 }
3849 
ath12k_dp_rx_h_rxdma_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3850 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar,  struct sk_buff *msdu,
3851 				     struct ieee80211_rx_status *status)
3852 {
3853 	struct ath12k_base *ab = ar->ab;
3854 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3855 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3856 	bool drop = false;
3857 	u32 err_bitmap;
3858 
3859 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3860 
3861 	switch (rxcb->err_code) {
3862 	case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR:
3863 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3864 		err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
3865 		if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) {
3866 			drop = ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3867 			break;
3868 		}
3869 		fallthrough;
3870 	default:
3871 		/* TODO: Review other rxdma error code to check if anything is
3872 		 * worth reporting to mac80211
3873 		 */
3874 		drop = true;
3875 		break;
3876 	}
3877 
3878 	return drop;
3879 }
3880 
ath12k_dp_rx_wbm_err(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3881 static void ath12k_dp_rx_wbm_err(struct ath12k *ar,
3882 				 struct napi_struct *napi,
3883 				 struct sk_buff *msdu,
3884 				 struct sk_buff_head *msdu_list)
3885 {
3886 	struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3887 	struct ieee80211_rx_status rxs = {0};
3888 	bool drop = true;
3889 
3890 	switch (rxcb->err_rel_src) {
3891 	case HAL_WBM_REL_SRC_MODULE_REO:
3892 		drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3893 		break;
3894 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
3895 		drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3896 		break;
3897 	default:
3898 		/* msdu will get freed */
3899 		break;
3900 	}
3901 
3902 	if (drop) {
3903 		dev_kfree_skb_any(msdu);
3904 		return;
3905 	}
3906 
3907 	ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
3908 }
3909 
ath12k_dp_rx_process_wbm_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3910 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,
3911 				 struct napi_struct *napi, int budget)
3912 {
3913 	struct list_head rx_desc_used_list[ATH12K_MAX_SOCS];
3914 	struct ath12k_hw_group *ag = ab->ag;
3915 	struct ath12k *ar;
3916 	struct ath12k_dp *dp = &ab->dp;
3917 	struct dp_rxdma_ring *rx_ring;
3918 	struct hal_rx_wbm_rel_info err_info;
3919 	struct hal_srng *srng;
3920 	struct sk_buff *msdu;
3921 	struct sk_buff_head msdu_list, scatter_msdu_list;
3922 	struct ath12k_skb_rxcb *rxcb;
3923 	void *rx_desc;
3924 	int num_buffs_reaped[ATH12K_MAX_SOCS] = {};
3925 	int total_num_buffs_reaped = 0;
3926 	struct ath12k_rx_desc_info *desc_info;
3927 	struct ath12k_hw_link *hw_links = ag->hw_links;
3928 	struct ath12k_base *partner_ab;
3929 	u8 hw_link_id, device_id;
3930 	int ret, pdev_id;
3931 	struct hal_rx_desc *msdu_data;
3932 
3933 	__skb_queue_head_init(&msdu_list);
3934 	__skb_queue_head_init(&scatter_msdu_list);
3935 
3936 	for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++)
3937 		INIT_LIST_HEAD(&rx_desc_used_list[device_id]);
3938 
3939 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
3940 	spin_lock_bh(&srng->lock);
3941 
3942 	ath12k_hal_srng_access_begin(ab, srng);
3943 
3944 	while (budget) {
3945 		rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
3946 		if (!rx_desc)
3947 			break;
3948 
3949 		ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
3950 		if (ret) {
3951 			ath12k_warn(ab,
3952 				    "failed to parse rx error in wbm_rel ring desc %d\n",
3953 				    ret);
3954 			continue;
3955 		}
3956 
3957 		desc_info = err_info.rx_desc;
3958 
3959 		/* retry manual desc retrieval if hw cc is not done */
3960 		if (!desc_info) {
3961 			desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie);
3962 			if (!desc_info) {
3963 				ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n",
3964 					    err_info.cookie);
3965 				continue;
3966 			}
3967 		}
3968 
3969 		if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3970 			ath12k_warn(ab, "WBM RX err, Check HW CC implementation");
3971 
3972 		msdu = desc_info->skb;
3973 		desc_info->skb = NULL;
3974 
3975 		device_id = desc_info->device_id;
3976 		partner_ab = ath12k_ag_to_ab(ag, device_id);
3977 		if (unlikely(!partner_ab)) {
3978 			dev_kfree_skb_any(msdu);
3979 
3980 			/* In any case continuation bit is set
3981 			 * in the previous record, cleanup scatter_msdu_list
3982 			 */
3983 			ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
3984 			continue;
3985 		}
3986 
3987 		list_add_tail(&desc_info->list, &rx_desc_used_list[device_id]);
3988 
3989 		rxcb = ATH12K_SKB_RXCB(msdu);
3990 		dma_unmap_single(partner_ab->dev, rxcb->paddr,
3991 				 msdu->len + skb_tailroom(msdu),
3992 				 DMA_FROM_DEVICE);
3993 
3994 		num_buffs_reaped[device_id]++;
3995 		total_num_buffs_reaped++;
3996 
3997 		if (!err_info.continuation)
3998 			budget--;
3999 
4000 		if (err_info.push_reason !=
4001 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4002 			dev_kfree_skb_any(msdu);
4003 			continue;
4004 		}
4005 
4006 		msdu_data = (struct hal_rx_desc *)msdu->data;
4007 		rxcb->err_rel_src = err_info.err_rel_src;
4008 		rxcb->err_code = err_info.err_code;
4009 		rxcb->is_first_msdu = err_info.first_msdu;
4010 		rxcb->is_last_msdu = err_info.last_msdu;
4011 		rxcb->is_continuation = err_info.continuation;
4012 		rxcb->rx_desc = msdu_data;
4013 
4014 		if (err_info.continuation) {
4015 			__skb_queue_tail(&scatter_msdu_list, msdu);
4016 			continue;
4017 		}
4018 
4019 		hw_link_id = ath12k_dp_rx_get_msdu_src_link(partner_ab,
4020 							    msdu_data);
4021 		if (hw_link_id >= ATH12K_GROUP_MAX_RADIO) {
4022 			dev_kfree_skb_any(msdu);
4023 
4024 			/* In any case continuation bit is set
4025 			 * in the previous record, cleanup scatter_msdu_list
4026 			 */
4027 			ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
4028 			continue;
4029 		}
4030 
4031 		if (!skb_queue_empty(&scatter_msdu_list)) {
4032 			struct sk_buff *msdu;
4033 
4034 			skb_queue_walk(&scatter_msdu_list, msdu) {
4035 				rxcb = ATH12K_SKB_RXCB(msdu);
4036 				rxcb->hw_link_id = hw_link_id;
4037 			}
4038 
4039 			skb_queue_splice_tail_init(&scatter_msdu_list,
4040 						   &msdu_list);
4041 		}
4042 
4043 		rxcb = ATH12K_SKB_RXCB(msdu);
4044 		rxcb->hw_link_id = hw_link_id;
4045 		__skb_queue_tail(&msdu_list, msdu);
4046 	}
4047 
4048 	/* In any case continuation bit is set in the
4049 	 * last record, cleanup scatter_msdu_list
4050 	 */
4051 	ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
4052 
4053 	ath12k_hal_srng_access_end(ab, srng);
4054 
4055 	spin_unlock_bh(&srng->lock);
4056 
4057 	if (!total_num_buffs_reaped)
4058 		goto done;
4059 
4060 	for (device_id = 0; device_id < ATH12K_MAX_SOCS; device_id++) {
4061 		if (!num_buffs_reaped[device_id])
4062 			continue;
4063 
4064 		partner_ab = ath12k_ag_to_ab(ag, device_id);
4065 		rx_ring = &partner_ab->dp.rx_refill_buf_ring;
4066 
4067 		ath12k_dp_rx_bufs_replenish(ab, rx_ring,
4068 					    &rx_desc_used_list[device_id],
4069 					    num_buffs_reaped[device_id]);
4070 	}
4071 
4072 	rcu_read_lock();
4073 	while ((msdu = __skb_dequeue(&msdu_list))) {
4074 		rxcb = ATH12K_SKB_RXCB(msdu);
4075 		hw_link_id = rxcb->hw_link_id;
4076 
4077 		device_id = hw_links[hw_link_id].device_id;
4078 		partner_ab = ath12k_ag_to_ab(ag, device_id);
4079 		if (unlikely(!partner_ab)) {
4080 			ath12k_dbg(ab, ATH12K_DBG_DATA,
4081 				   "Unable to process WBM error msdu due to invalid hw link id %d device id %d\n",
4082 				   hw_link_id, device_id);
4083 			dev_kfree_skb_any(msdu);
4084 			continue;
4085 		}
4086 
4087 		pdev_id = ath12k_hw_mac_id_to_pdev_id(partner_ab->hw_params,
4088 						      hw_links[hw_link_id].pdev_idx);
4089 		ar = partner_ab->pdevs[pdev_id].ar;
4090 
4091 		if (!ar || !rcu_dereference(ar->ab->pdevs_active[pdev_id])) {
4092 			dev_kfree_skb_any(msdu);
4093 			continue;
4094 		}
4095 
4096 		if (test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) {
4097 			dev_kfree_skb_any(msdu);
4098 			continue;
4099 		}
4100 		ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list);
4101 	}
4102 	rcu_read_unlock();
4103 done:
4104 	return total_num_buffs_reaped;
4105 }
4106 
ath12k_dp_rx_process_reo_status(struct ath12k_base * ab)4107 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab)
4108 {
4109 	struct ath12k_dp *dp = &ab->dp;
4110 	struct hal_tlv_64_hdr *hdr;
4111 	struct hal_srng *srng;
4112 	struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
4113 	bool found = false;
4114 	u16 tag;
4115 	struct hal_reo_status reo_status;
4116 
4117 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4118 
4119 	memset(&reo_status, 0, sizeof(reo_status));
4120 
4121 	spin_lock_bh(&srng->lock);
4122 
4123 	ath12k_hal_srng_access_begin(ab, srng);
4124 
4125 	while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
4126 		tag = le64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG);
4127 
4128 		switch (tag) {
4129 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4130 			ath12k_hal_reo_status_queue_stats(ab, hdr,
4131 							  &reo_status);
4132 			break;
4133 		case HAL_REO_FLUSH_QUEUE_STATUS:
4134 			ath12k_hal_reo_flush_queue_status(ab, hdr,
4135 							  &reo_status);
4136 			break;
4137 		case HAL_REO_FLUSH_CACHE_STATUS:
4138 			ath12k_hal_reo_flush_cache_status(ab, hdr,
4139 							  &reo_status);
4140 			break;
4141 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4142 			ath12k_hal_reo_unblk_cache_status(ab, hdr,
4143 							  &reo_status);
4144 			break;
4145 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4146 			ath12k_hal_reo_flush_timeout_list_status(ab, hdr,
4147 								 &reo_status);
4148 			break;
4149 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4150 			ath12k_hal_reo_desc_thresh_reached_status(ab, hdr,
4151 								  &reo_status);
4152 			break;
4153 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4154 			ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr,
4155 								  &reo_status);
4156 			break;
4157 		default:
4158 			ath12k_warn(ab, "Unknown reo status type %d\n", tag);
4159 			continue;
4160 		}
4161 
4162 		spin_lock_bh(&dp->reo_cmd_lock);
4163 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4164 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4165 				found = true;
4166 				list_del(&cmd->list);
4167 				break;
4168 			}
4169 		}
4170 		spin_unlock_bh(&dp->reo_cmd_lock);
4171 
4172 		if (found) {
4173 			cmd->handler(dp, (void *)&cmd->data,
4174 				     reo_status.uniform_hdr.cmd_status);
4175 			kfree(cmd);
4176 		}
4177 
4178 		found = false;
4179 	}
4180 
4181 	ath12k_hal_srng_access_end(ab, srng);
4182 
4183 	spin_unlock_bh(&srng->lock);
4184 }
4185 
ath12k_dp_rx_free(struct ath12k_base * ab)4186 void ath12k_dp_rx_free(struct ath12k_base *ab)
4187 {
4188 	struct ath12k_dp *dp = &ab->dp;
4189 	int i;
4190 
4191 	ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
4192 
4193 	for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4194 		if (ab->hw_params->rx_mac_buf_ring)
4195 			ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
4196 	}
4197 
4198 	for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++)
4199 		ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
4200 
4201 	ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
4202 
4203 	ath12k_dp_rxdma_buf_free(ab);
4204 }
4205 
ath12k_dp_rx_pdev_free(struct ath12k_base * ab,int mac_id)4206 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id)
4207 {
4208 	struct ath12k *ar = ab->pdevs[mac_id].ar;
4209 
4210 	ath12k_dp_rx_pdev_srng_free(ar);
4211 }
4212 
ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base * ab)4213 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab)
4214 {
4215 	struct ath12k_dp *dp = &ab->dp;
4216 	struct htt_rx_ring_tlv_filter tlv_filter = {0};
4217 	u32 ring_id;
4218 	int ret;
4219 	u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4220 
4221 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4222 
4223 	tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4224 	tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4225 	tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4226 					HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4227 					HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4228 	tlv_filter.offset_valid = true;
4229 	tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4230 
4231 	tlv_filter.rx_mpdu_start_offset =
4232 		ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4233 	tlv_filter.rx_msdu_end_offset =
4234 		ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4235 
4236 	if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
4237 		tlv_filter.rx_mpdu_start_wmask =
4238 			ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start();
4239 		tlv_filter.rx_msdu_end_wmask =
4240 			ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end();
4241 		ath12k_dbg(ab, ATH12K_DBG_DATA,
4242 			   "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n",
4243 			   tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask);
4244 	}
4245 
4246 	ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0,
4247 					       HAL_RXDMA_BUF,
4248 					       DP_RXDMA_REFILL_RING_SIZE,
4249 					       &tlv_filter);
4250 
4251 	return ret;
4252 }
4253 
ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base * ab)4254 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab)
4255 {
4256 	struct ath12k_dp *dp = &ab->dp;
4257 	struct htt_rx_ring_tlv_filter tlv_filter = {0};
4258 	u32 ring_id;
4259 	int ret = 0;
4260 	u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4261 	int i;
4262 
4263 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4264 
4265 	tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4266 	tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4267 	tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4268 					HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4269 					HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4270 	tlv_filter.offset_valid = true;
4271 	tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4272 
4273 	tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv);
4274 
4275 	tlv_filter.rx_mpdu_start_offset =
4276 		ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4277 	tlv_filter.rx_msdu_end_offset =
4278 		ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4279 
4280 	/* TODO: Selectively subscribe to required qwords within msdu_end
4281 	 * and mpdu_start and setup the mask in below msg
4282 	 * and modify the rx_desc struct
4283 	 */
4284 
4285 	for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4286 		ring_id = dp->rx_mac_buf_ring[i].ring_id;
4287 		ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i,
4288 						       HAL_RXDMA_BUF,
4289 						       DP_RXDMA_REFILL_RING_SIZE,
4290 						       &tlv_filter);
4291 	}
4292 
4293 	return ret;
4294 }
4295 
ath12k_dp_rx_htt_setup(struct ath12k_base * ab)4296 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab)
4297 {
4298 	struct ath12k_dp *dp = &ab->dp;
4299 	u32 ring_id;
4300 	int i, ret;
4301 
4302 	/* TODO: Need to verify the HTT setup for QCN9224 */
4303 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4304 	ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF);
4305 	if (ret) {
4306 		ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4307 			    ret);
4308 		return ret;
4309 	}
4310 
4311 	if (ab->hw_params->rx_mac_buf_ring) {
4312 		for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4313 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4314 			ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4315 							  i, HAL_RXDMA_BUF);
4316 			if (ret) {
4317 				ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4318 					    i, ret);
4319 				return ret;
4320 			}
4321 		}
4322 	}
4323 
4324 	for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4325 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4326 		ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4327 						  i, HAL_RXDMA_DST);
4328 		if (ret) {
4329 			ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4330 				    i, ret);
4331 			return ret;
4332 		}
4333 	}
4334 
4335 	if (ab->hw_params->rxdma1_enable) {
4336 		ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4337 		ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4338 						  0, HAL_RXDMA_MONITOR_BUF);
4339 		if (ret) {
4340 			ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4341 				    ret);
4342 			return ret;
4343 		}
4344 	}
4345 
4346 	ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab);
4347 	if (ret) {
4348 		ath12k_warn(ab, "failed to setup rxdma ring selection config\n");
4349 		return ret;
4350 	}
4351 
4352 	return 0;
4353 }
4354 
ath12k_dp_rx_alloc(struct ath12k_base * ab)4355 int ath12k_dp_rx_alloc(struct ath12k_base *ab)
4356 {
4357 	struct ath12k_dp *dp = &ab->dp;
4358 	int i, ret;
4359 
4360 	idr_init(&dp->rxdma_mon_buf_ring.bufs_idr);
4361 	spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock);
4362 
4363 	ret = ath12k_dp_srng_setup(ab,
4364 				   &dp->rx_refill_buf_ring.refill_buf_ring,
4365 				   HAL_RXDMA_BUF, 0, 0,
4366 				   DP_RXDMA_BUF_RING_SIZE);
4367 	if (ret) {
4368 		ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n");
4369 		return ret;
4370 	}
4371 
4372 	if (ab->hw_params->rx_mac_buf_ring) {
4373 		for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4374 			ret = ath12k_dp_srng_setup(ab,
4375 						   &dp->rx_mac_buf_ring[i],
4376 						   HAL_RXDMA_BUF, 1,
4377 						   i, DP_RX_MAC_BUF_RING_SIZE);
4378 			if (ret) {
4379 				ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n",
4380 					    i);
4381 				return ret;
4382 			}
4383 		}
4384 	}
4385 
4386 	for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4387 		ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i],
4388 					   HAL_RXDMA_DST, 0, i,
4389 					   DP_RXDMA_ERR_DST_RING_SIZE);
4390 		if (ret) {
4391 			ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i);
4392 			return ret;
4393 		}
4394 	}
4395 
4396 	if (ab->hw_params->rxdma1_enable) {
4397 		ret = ath12k_dp_srng_setup(ab,
4398 					   &dp->rxdma_mon_buf_ring.refill_buf_ring,
4399 					   HAL_RXDMA_MONITOR_BUF, 0, 0,
4400 					   DP_RXDMA_MONITOR_BUF_RING_SIZE);
4401 		if (ret) {
4402 			ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n");
4403 			return ret;
4404 		}
4405 	}
4406 
4407 	ret = ath12k_dp_rxdma_buf_setup(ab);
4408 	if (ret) {
4409 		ath12k_warn(ab, "failed to setup rxdma ring\n");
4410 		return ret;
4411 	}
4412 
4413 	return 0;
4414 }
4415 
ath12k_dp_rx_pdev_alloc(struct ath12k_base * ab,int mac_id)4416 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id)
4417 {
4418 	struct ath12k *ar = ab->pdevs[mac_id].ar;
4419 	struct ath12k_pdev_dp *dp = &ar->dp;
4420 	u32 ring_id;
4421 	int i;
4422 	int ret;
4423 
4424 	if (!ab->hw_params->rxdma1_enable)
4425 		goto out;
4426 
4427 	ret = ath12k_dp_rx_pdev_srng_alloc(ar);
4428 	if (ret) {
4429 		ath12k_warn(ab, "failed to setup rx srngs\n");
4430 		return ret;
4431 	}
4432 
4433 	for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4434 		ring_id = dp->rxdma_mon_dst_ring[i].ring_id;
4435 		ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4436 						  mac_id + i,
4437 						  HAL_RXDMA_MONITOR_DST);
4438 		if (ret) {
4439 			ath12k_warn(ab,
4440 				    "failed to configure rxdma_mon_dst_ring %d %d\n",
4441 				    i, ret);
4442 			return ret;
4443 		}
4444 	}
4445 out:
4446 	return 0;
4447 }
4448 
ath12k_dp_rx_pdev_mon_status_attach(struct ath12k * ar)4449 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar)
4450 {
4451 	struct ath12k_pdev_dp *dp = &ar->dp;
4452 	struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data;
4453 
4454 	skb_queue_head_init(&pmon->rx_status_q);
4455 
4456 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4457 
4458 	memset(&pmon->rx_mon_stats, 0,
4459 	       sizeof(pmon->rx_mon_stats));
4460 	return 0;
4461 }
4462 
ath12k_dp_rx_pdev_mon_attach(struct ath12k * ar)4463 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar)
4464 {
4465 	struct ath12k_pdev_dp *dp = &ar->dp;
4466 	struct ath12k_mon_data *pmon = &dp->mon_data;
4467 	int ret = 0;
4468 
4469 	ret = ath12k_dp_rx_pdev_mon_status_attach(ar);
4470 	if (ret) {
4471 		ath12k_warn(ar->ab, "pdev_mon_status_attach() failed");
4472 		return ret;
4473 	}
4474 
4475 	/* if rxdma1_enable is false, no need to setup
4476 	 * rxdma_mon_desc_ring.
4477 	 */
4478 	if (!ar->ab->hw_params->rxdma1_enable)
4479 		return 0;
4480 
4481 	pmon->mon_last_linkdesc_paddr = 0;
4482 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
4483 	spin_lock_init(&pmon->mon_lock);
4484 
4485 	return 0;
4486 }
4487