1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "hal_desc.h"
14 #include "hw.h"
15 #include "dp_rx.h"
16 #include "hal_rx.h"
17 #include "dp_tx.h"
18 #include "peer.h"
19 #include "dp_mon.h"
20 #include "debugfs_htt_stats.h"
21
22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
ath12k_dp_rx_h_enctype(struct ath12k_base * ab,struct hal_rx_desc * desc)24 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab,
25 struct hal_rx_desc *desc)
26 {
27 if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc))
28 return HAL_ENCRYPT_TYPE_OPEN;
29
30 return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc);
31 }
32
ath12k_dp_rx_h_decap_type(struct ath12k_base * ab,struct hal_rx_desc * desc)33 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab,
34 struct hal_rx_desc *desc)
35 {
36 return ab->hal_rx_ops->rx_desc_get_decap_type(desc);
37 }
38
ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base * ab,struct hal_rx_desc * desc)39 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab,
40 struct hal_rx_desc *desc)
41 {
42 return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc);
43 }
44
ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)45 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab,
46 struct hal_rx_desc *desc)
47 {
48 return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
49 }
50
ath12k_dp_rx_h_fc_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)51 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab,
52 struct hal_rx_desc *desc)
53 {
54 return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc);
55 }
56
ath12k_dp_rx_h_more_frags(struct ath12k_base * ab,struct sk_buff * skb)57 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab,
58 struct sk_buff *skb)
59 {
60 struct ieee80211_hdr *hdr;
61
62 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
63 return ieee80211_has_morefrags(hdr->frame_control);
64 }
65
ath12k_dp_rx_h_frag_no(struct ath12k_base * ab,struct sk_buff * skb)66 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab,
67 struct sk_buff *skb)
68 {
69 struct ieee80211_hdr *hdr;
70
71 hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
72 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
73 }
74
ath12k_dp_rx_h_seq_no(struct ath12k_base * ab,struct hal_rx_desc * desc)75 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab,
76 struct hal_rx_desc *desc)
77 {
78 return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc);
79 }
80
ath12k_dp_rx_h_msdu_done(struct ath12k_base * ab,struct hal_rx_desc * desc)81 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab,
82 struct hal_rx_desc *desc)
83 {
84 return ab->hal_rx_ops->dp_rx_h_msdu_done(desc);
85 }
86
ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)87 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab,
88 struct hal_rx_desc *desc)
89 {
90 return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc);
91 }
92
ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base * ab,struct hal_rx_desc * desc)93 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab,
94 struct hal_rx_desc *desc)
95 {
96 return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc);
97 }
98
ath12k_dp_rx_h_is_decrypted(struct ath12k_base * ab,struct hal_rx_desc * desc)99 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab,
100 struct hal_rx_desc *desc)
101 {
102 return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc);
103 }
104
ath12k_dp_rx_h_mpdu_err(struct ath12k_base * ab,struct hal_rx_desc * desc)105 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab,
106 struct hal_rx_desc *desc)
107 {
108 return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc);
109 }
110
ath12k_dp_rx_h_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc)111 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab,
112 struct hal_rx_desc *desc)
113 {
114 return ab->hal_rx_ops->rx_desc_get_msdu_len(desc);
115 }
116
ath12k_dp_rx_h_sgi(struct ath12k_base * ab,struct hal_rx_desc * desc)117 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab,
118 struct hal_rx_desc *desc)
119 {
120 return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc);
121 }
122
ath12k_dp_rx_h_rate_mcs(struct ath12k_base * ab,struct hal_rx_desc * desc)123 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab,
124 struct hal_rx_desc *desc)
125 {
126 return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc);
127 }
128
ath12k_dp_rx_h_rx_bw(struct ath12k_base * ab,struct hal_rx_desc * desc)129 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab,
130 struct hal_rx_desc *desc)
131 {
132 return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc);
133 }
134
ath12k_dp_rx_h_freq(struct ath12k_base * ab,struct hal_rx_desc * desc)135 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab,
136 struct hal_rx_desc *desc)
137 {
138 return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc);
139 }
140
ath12k_dp_rx_h_pkt_type(struct ath12k_base * ab,struct hal_rx_desc * desc)141 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab,
142 struct hal_rx_desc *desc)
143 {
144 return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc);
145 }
146
ath12k_dp_rx_h_nss(struct ath12k_base * ab,struct hal_rx_desc * desc)147 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab,
148 struct hal_rx_desc *desc)
149 {
150 return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc));
151 }
152
ath12k_dp_rx_h_tid(struct ath12k_base * ab,struct hal_rx_desc * desc)153 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab,
154 struct hal_rx_desc *desc)
155 {
156 return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc);
157 }
158
ath12k_dp_rx_h_peer_id(struct ath12k_base * ab,struct hal_rx_desc * desc)159 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab,
160 struct hal_rx_desc *desc)
161 {
162 return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc);
163 }
164
ath12k_dp_rx_h_l3pad(struct ath12k_base * ab,struct hal_rx_desc * desc)165 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab,
166 struct hal_rx_desc *desc)
167 {
168 return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc);
169 }
170
ath12k_dp_rx_h_first_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)171 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab,
172 struct hal_rx_desc *desc)
173 {
174 return ab->hal_rx_ops->rx_desc_get_first_msdu(desc);
175 }
176
ath12k_dp_rx_h_last_msdu(struct ath12k_base * ab,struct hal_rx_desc * desc)177 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab,
178 struct hal_rx_desc *desc)
179 {
180 return ab->hal_rx_ops->rx_desc_get_last_msdu(desc);
181 }
182
ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)183 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab,
184 struct hal_rx_desc *fdesc,
185 struct hal_rx_desc *ldesc)
186 {
187 ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc);
188 }
189
ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base * ab,struct hal_rx_desc * desc,u16 len)190 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab,
191 struct hal_rx_desc *desc,
192 u16 len)
193 {
194 ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len);
195 }
196
ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base * ab,struct hal_rx_desc * desc)197 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab,
198 struct hal_rx_desc *desc)
199 {
200 return (ath12k_dp_rx_h_first_msdu(ab, desc) &&
201 ab->hal_rx_ops->rx_desc_is_da_mcbc(desc));
202 }
203
ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base * ab,struct hal_rx_desc * desc)204 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab,
205 struct hal_rx_desc *desc)
206 {
207 return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc);
208 }
209
ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base * ab,struct hal_rx_desc * desc)210 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab,
211 struct hal_rx_desc *desc)
212 {
213 return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc);
214 }
215
ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base * ab,struct hal_rx_desc * desc,struct ieee80211_hdr * hdr)216 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab,
217 struct hal_rx_desc *desc,
218 struct ieee80211_hdr *hdr)
219 {
220 ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr);
221 }
222
ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base * ab,struct hal_rx_desc * desc,u8 * crypto_hdr,enum hal_encrypt_type enctype)223 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab,
224 struct hal_rx_desc *desc,
225 u8 *crypto_hdr,
226 enum hal_encrypt_type enctype)
227 {
228 ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype);
229 }
230
ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base * ab,struct hal_rx_desc * desc)231 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab,
232 struct hal_rx_desc *desc)
233 {
234 return ab->hal_rx_ops->rx_desc_get_mpdu_frame_ctl(desc);
235 }
236
ath12k_dp_rx_get_msdu_src_link(struct ath12k_base * ab,struct hal_rx_desc * desc)237 static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab,
238 struct hal_rx_desc *desc)
239 {
240 return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc);
241 }
242
ath12k_dp_clean_up_skb_list(struct sk_buff_head * skb_list)243 static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list)
244 {
245 struct sk_buff *skb;
246
247 while ((skb = __skb_dequeue(skb_list)))
248 dev_kfree_skb_any(skb);
249 }
250
ath12k_dp_list_cut_nodes(struct list_head * list,struct list_head * head,size_t count)251 static size_t ath12k_dp_list_cut_nodes(struct list_head *list,
252 struct list_head *head,
253 size_t count)
254 {
255 struct list_head *cur;
256 struct ath12k_rx_desc_info *rx_desc;
257 size_t nodes = 0;
258
259 if (!count) {
260 INIT_LIST_HEAD(list);
261 goto out;
262 }
263
264 list_for_each(cur, head) {
265 if (!count)
266 break;
267
268 rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list);
269 rx_desc->in_use = true;
270
271 count--;
272 nodes++;
273 }
274
275 list_cut_before(list, head, cur);
276 out:
277 return nodes;
278 }
279
ath12k_dp_rx_enqueue_free(struct ath12k_dp * dp,struct list_head * used_list)280 static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp,
281 struct list_head *used_list)
282 {
283 struct ath12k_rx_desc_info *rx_desc, *safe;
284
285 /* Reset the use flag */
286 list_for_each_entry_safe(rx_desc, safe, used_list, list)
287 rx_desc->in_use = false;
288
289 spin_lock_bh(&dp->rx_desc_lock);
290 list_splice_tail(used_list, &dp->rx_desc_free_list);
291 spin_unlock_bh(&dp->rx_desc_lock);
292 }
293
294 /* Returns number of Rx buffers replenished */
ath12k_dp_rx_bufs_replenish(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring,struct list_head * used_list,int req_entries)295 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab,
296 struct dp_rxdma_ring *rx_ring,
297 struct list_head *used_list,
298 int req_entries)
299 {
300 struct ath12k_buffer_addr *desc;
301 struct hal_srng *srng;
302 struct sk_buff *skb;
303 int num_free;
304 int num_remain;
305 u32 cookie;
306 dma_addr_t paddr;
307 struct ath12k_dp *dp = &ab->dp;
308 struct ath12k_rx_desc_info *rx_desc;
309 enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm;
310
311 req_entries = min(req_entries, rx_ring->bufs_max);
312
313 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
314
315 spin_lock_bh(&srng->lock);
316
317 ath12k_hal_srng_access_begin(ab, srng);
318
319 num_free = ath12k_hal_srng_src_num_free(ab, srng, true);
320 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
321 req_entries = num_free;
322
323 req_entries = min(num_free, req_entries);
324 num_remain = req_entries;
325
326 if (!num_remain)
327 goto out;
328
329 /* Get the descriptor from free list */
330 if (list_empty(used_list)) {
331 spin_lock_bh(&dp->rx_desc_lock);
332 req_entries = ath12k_dp_list_cut_nodes(used_list,
333 &dp->rx_desc_free_list,
334 num_remain);
335 spin_unlock_bh(&dp->rx_desc_lock);
336 num_remain = req_entries;
337 }
338
339 while (num_remain > 0) {
340 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
341 DP_RX_BUFFER_ALIGN_SIZE);
342 if (!skb)
343 break;
344
345 if (!IS_ALIGNED((unsigned long)skb->data,
346 DP_RX_BUFFER_ALIGN_SIZE)) {
347 skb_pull(skb,
348 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
349 skb->data);
350 }
351
352 paddr = dma_map_single(ab->dev, skb->data,
353 skb->len + skb_tailroom(skb),
354 DMA_FROM_DEVICE);
355 if (dma_mapping_error(ab->dev, paddr))
356 goto fail_free_skb;
357
358 rx_desc = list_first_entry_or_null(used_list,
359 struct ath12k_rx_desc_info,
360 list);
361 if (!rx_desc)
362 goto fail_dma_unmap;
363
364 rx_desc->skb = skb;
365 cookie = rx_desc->cookie;
366
367 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
368 if (!desc)
369 goto fail_dma_unmap;
370
371 list_del(&rx_desc->list);
372 ATH12K_SKB_RXCB(skb)->paddr = paddr;
373
374 num_remain--;
375
376 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
377 }
378
379 goto out;
380
381 fail_dma_unmap:
382 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
383 DMA_FROM_DEVICE);
384 fail_free_skb:
385 dev_kfree_skb_any(skb);
386 out:
387 ath12k_hal_srng_access_end(ab, srng);
388
389 if (!list_empty(used_list))
390 ath12k_dp_rx_enqueue_free(dp, used_list);
391
392 spin_unlock_bh(&srng->lock);
393
394 return req_entries - num_remain;
395 }
396
ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring)397 static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab,
398 struct dp_rxdma_mon_ring *rx_ring)
399 {
400 struct sk_buff *skb;
401 int buf_id;
402
403 spin_lock_bh(&rx_ring->idr_lock);
404 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
405 idr_remove(&rx_ring->bufs_idr, buf_id);
406 /* TODO: Understand where internal driver does this dma_unmap
407 * of rxdma_buffer.
408 */
409 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
410 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
411 dev_kfree_skb_any(skb);
412 }
413
414 idr_destroy(&rx_ring->bufs_idr);
415 spin_unlock_bh(&rx_ring->idr_lock);
416
417 return 0;
418 }
419
ath12k_dp_rxdma_buf_free(struct ath12k_base * ab)420 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab)
421 {
422 struct ath12k_dp *dp = &ab->dp;
423
424 ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring);
425
426 return 0;
427 }
428
ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_mon_ring * rx_ring,u32 ringtype)429 static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab,
430 struct dp_rxdma_mon_ring *rx_ring,
431 u32 ringtype)
432 {
433 int num_entries;
434
435 num_entries = rx_ring->refill_buf_ring.size /
436 ath12k_hal_srng_get_entrysize(ab, ringtype);
437
438 rx_ring->bufs_max = num_entries;
439 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries);
440
441 return 0;
442 }
443
ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base * ab,struct dp_rxdma_ring * rx_ring)444 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab,
445 struct dp_rxdma_ring *rx_ring)
446 {
447 LIST_HEAD(list);
448
449 rx_ring->bufs_max = rx_ring->refill_buf_ring.size /
450 ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF);
451
452 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
453
454 return 0;
455 }
456
ath12k_dp_rxdma_buf_setup(struct ath12k_base * ab)457 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab)
458 {
459 struct ath12k_dp *dp = &ab->dp;
460 int ret;
461
462 ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring);
463 if (ret) {
464 ath12k_warn(ab,
465 "failed to setup HAL_RXDMA_BUF\n");
466 return ret;
467 }
468
469 if (ab->hw_params->rxdma1_enable) {
470 ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab,
471 &dp->rxdma_mon_buf_ring,
472 HAL_RXDMA_MONITOR_BUF);
473 if (ret) {
474 ath12k_warn(ab,
475 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
476 return ret;
477 }
478 }
479
480 return 0;
481 }
482
ath12k_dp_rx_pdev_srng_free(struct ath12k * ar)483 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar)
484 {
485 struct ath12k_pdev_dp *dp = &ar->dp;
486 struct ath12k_base *ab = ar->ab;
487 int i;
488
489 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++)
490 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]);
491 }
492
ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base * ab)493 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab)
494 {
495 struct ath12k_dp *dp = &ab->dp;
496 int i;
497
498 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
499 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
500 }
501
ath12k_dp_rx_pdev_reo_setup(struct ath12k_base * ab)502 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab)
503 {
504 struct ath12k_dp *dp = &ab->dp;
505 int ret;
506 int i;
507
508 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
509 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
510 HAL_REO_DST, i, 0,
511 DP_REO_DST_RING_SIZE);
512 if (ret) {
513 ath12k_warn(ab, "failed to setup reo_dst_ring\n");
514 goto err_reo_cleanup;
515 }
516 }
517
518 return 0;
519
520 err_reo_cleanup:
521 ath12k_dp_rx_pdev_reo_cleanup(ab);
522
523 return ret;
524 }
525
ath12k_dp_rx_pdev_srng_alloc(struct ath12k * ar)526 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar)
527 {
528 struct ath12k_pdev_dp *dp = &ar->dp;
529 struct ath12k_base *ab = ar->ab;
530 int i;
531 int ret;
532 u32 mac_id = dp->mac_id;
533
534 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
535 ret = ath12k_dp_srng_setup(ar->ab,
536 &dp->rxdma_mon_dst_ring[i],
537 HAL_RXDMA_MONITOR_DST,
538 0, mac_id + i,
539 DP_RXDMA_MONITOR_DST_RING_SIZE);
540 if (ret) {
541 ath12k_warn(ar->ab,
542 "failed to setup HAL_RXDMA_MONITOR_DST\n");
543 return ret;
544 }
545 }
546
547 return 0;
548 }
549
ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base * ab)550 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab)
551 {
552 struct ath12k_dp *dp = &ab->dp;
553 struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
554 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache;
555
556 spin_lock_bh(&dp->reo_cmd_lock);
557 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
558 list_del(&cmd->list);
559 dma_unmap_single(ab->dev, cmd->data.paddr,
560 cmd->data.size, DMA_BIDIRECTIONAL);
561 kfree(cmd->data.vaddr);
562 kfree(cmd);
563 }
564
565 list_for_each_entry_safe(cmd_cache, tmp_cache,
566 &dp->reo_cmd_cache_flush_list, list) {
567 list_del(&cmd_cache->list);
568 dp->reo_cmd_cache_flush_count--;
569 dma_unmap_single(ab->dev, cmd_cache->data.paddr,
570 cmd_cache->data.size, DMA_BIDIRECTIONAL);
571 kfree(cmd_cache->data.vaddr);
572 kfree(cmd_cache);
573 }
574 spin_unlock_bh(&dp->reo_cmd_lock);
575 }
576
ath12k_dp_reo_cmd_free(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)577 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx,
578 enum hal_reo_cmd_status status)
579 {
580 struct ath12k_dp_rx_tid *rx_tid = ctx;
581
582 if (status != HAL_REO_CMD_SUCCESS)
583 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
584 rx_tid->tid, status);
585
586 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
587 DMA_BIDIRECTIONAL);
588 kfree(rx_tid->vaddr);
589 rx_tid->vaddr = NULL;
590 }
591
ath12k_dp_reo_cmd_send(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid,enum hal_reo_cmd_type type,struct ath12k_hal_reo_cmd * cmd,void (* cb)(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status))592 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid,
593 enum hal_reo_cmd_type type,
594 struct ath12k_hal_reo_cmd *cmd,
595 void (*cb)(struct ath12k_dp *dp, void *ctx,
596 enum hal_reo_cmd_status status))
597 {
598 struct ath12k_dp *dp = &ab->dp;
599 struct ath12k_dp_rx_reo_cmd *dp_cmd;
600 struct hal_srng *cmd_ring;
601 int cmd_num;
602
603 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
604 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
605
606 /* cmd_num should start from 1, during failure return the error code */
607 if (cmd_num < 0)
608 return cmd_num;
609
610 /* reo cmd ring descriptors has cmd_num starting from 1 */
611 if (cmd_num == 0)
612 return -EINVAL;
613
614 if (!cb)
615 return 0;
616
617 /* Can this be optimized so that we keep the pending command list only
618 * for tid delete command to free up the resource on the command status
619 * indication?
620 */
621 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
622
623 if (!dp_cmd)
624 return -ENOMEM;
625
626 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid));
627 dp_cmd->cmd_num = cmd_num;
628 dp_cmd->handler = cb;
629
630 spin_lock_bh(&dp->reo_cmd_lock);
631 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
632 spin_unlock_bh(&dp->reo_cmd_lock);
633
634 return 0;
635 }
636
ath12k_dp_reo_cache_flush(struct ath12k_base * ab,struct ath12k_dp_rx_tid * rx_tid)637 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab,
638 struct ath12k_dp_rx_tid *rx_tid)
639 {
640 struct ath12k_hal_reo_cmd cmd = {0};
641 unsigned long tot_desc_sz, desc_sz;
642 int ret;
643
644 tot_desc_sz = rx_tid->size;
645 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
646
647 while (tot_desc_sz > desc_sz) {
648 tot_desc_sz -= desc_sz;
649 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
650 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
651 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
652 HAL_REO_CMD_FLUSH_CACHE, &cmd,
653 NULL);
654 if (ret)
655 ath12k_warn(ab,
656 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
657 rx_tid->tid, ret);
658 }
659
660 memset(&cmd, 0, sizeof(cmd));
661 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
662 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
663 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
664 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
665 HAL_REO_CMD_FLUSH_CACHE,
666 &cmd, ath12k_dp_reo_cmd_free);
667 if (ret) {
668 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
669 rx_tid->tid, ret);
670 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
671 DMA_BIDIRECTIONAL);
672 kfree(rx_tid->vaddr);
673 rx_tid->vaddr = NULL;
674 }
675 }
676
ath12k_dp_rx_tid_del_func(struct ath12k_dp * dp,void * ctx,enum hal_reo_cmd_status status)677 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx,
678 enum hal_reo_cmd_status status)
679 {
680 struct ath12k_base *ab = dp->ab;
681 struct ath12k_dp_rx_tid *rx_tid = ctx;
682 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp;
683
684 if (status == HAL_REO_CMD_DRAIN) {
685 goto free_desc;
686 } else if (status != HAL_REO_CMD_SUCCESS) {
687 /* Shouldn't happen! Cleanup in case of other failure? */
688 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
689 rx_tid->tid, status);
690 return;
691 }
692
693 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
694 if (!elem)
695 goto free_desc;
696
697 elem->ts = jiffies;
698 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
699
700 spin_lock_bh(&dp->reo_cmd_lock);
701 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
702 dp->reo_cmd_cache_flush_count++;
703
704 /* Flush and invalidate aged REO desc from HW cache */
705 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
706 list) {
707 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES ||
708 time_after(jiffies, elem->ts +
709 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) {
710 list_del(&elem->list);
711 dp->reo_cmd_cache_flush_count--;
712
713 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send()
714 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list
715 * is used in only two contexts, one is in this function called
716 * from napi and the other in ath12k_dp_free during core destroy.
717 * Before dp_free, the irqs would be disabled and would wait to
718 * synchronize. Hence there wouldn’t be any race against add or
719 * delete to this list. Hence unlock-lock is safe here.
720 */
721 spin_unlock_bh(&dp->reo_cmd_lock);
722
723 ath12k_dp_reo_cache_flush(ab, &elem->data);
724 kfree(elem);
725 spin_lock_bh(&dp->reo_cmd_lock);
726 }
727 }
728 spin_unlock_bh(&dp->reo_cmd_lock);
729
730 return;
731 free_desc:
732 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
733 DMA_BIDIRECTIONAL);
734 kfree(rx_tid->vaddr);
735 rx_tid->vaddr = NULL;
736 }
737
ath12k_peer_rx_tid_qref_setup(struct ath12k_base * ab,u16 peer_id,u16 tid,dma_addr_t paddr)738 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid,
739 dma_addr_t paddr)
740 {
741 struct ath12k_reo_queue_ref *qref;
742 struct ath12k_dp *dp = &ab->dp;
743
744 if (!ab->hw_params->reoq_lut_support)
745 return;
746
747 /* TODO: based on ML peer or not, select the LUT. below assumes non
748 * ML peer
749 */
750 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
751 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
752
753 qref->info0 = u32_encode_bits(lower_32_bits(paddr),
754 BUFFER_ADDR_INFO0_ADDR);
755 qref->info1 = u32_encode_bits(upper_32_bits(paddr),
756 BUFFER_ADDR_INFO1_ADDR) |
757 u32_encode_bits(tid, DP_REO_QREF_NUM);
758 }
759
ath12k_peer_rx_tid_qref_reset(struct ath12k_base * ab,u16 peer_id,u16 tid)760 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid)
761 {
762 struct ath12k_reo_queue_ref *qref;
763 struct ath12k_dp *dp = &ab->dp;
764
765 if (!ab->hw_params->reoq_lut_support)
766 return;
767
768 /* TODO: based on ML peer or not, select the LUT. below assumes non
769 * ML peer
770 */
771 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
772 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
773
774 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR);
775 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) |
776 u32_encode_bits(tid, DP_REO_QREF_NUM);
777 }
778
ath12k_dp_rx_peer_tid_delete(struct ath12k * ar,struct ath12k_peer * peer,u8 tid)779 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar,
780 struct ath12k_peer *peer, u8 tid)
781 {
782 struct ath12k_hal_reo_cmd cmd = {0};
783 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid];
784 int ret;
785
786 if (!rx_tid->active)
787 return;
788
789 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
790 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
791 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
792 cmd.upd0 = HAL_REO_CMD_UPD0_VLD;
793 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
794 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
795 ath12k_dp_rx_tid_del_func);
796 if (ret) {
797 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
798 tid, ret);
799 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
800 DMA_BIDIRECTIONAL);
801 kfree(rx_tid->vaddr);
802 rx_tid->vaddr = NULL;
803 }
804
805 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid);
806
807 rx_tid->active = false;
808 }
809
810 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted
811 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind
812 * that.
813 */
ath12k_dp_rx_link_desc_return(struct ath12k_base * ab,struct hal_reo_dest_ring * ring,enum hal_wbm_rel_bm_act action)814 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab,
815 struct hal_reo_dest_ring *ring,
816 enum hal_wbm_rel_bm_act action)
817 {
818 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring;
819 struct hal_wbm_release_ring *desc;
820 struct ath12k_dp *dp = &ab->dp;
821 struct hal_srng *srng;
822 int ret = 0;
823
824 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
825
826 spin_lock_bh(&srng->lock);
827
828 ath12k_hal_srng_access_begin(ab, srng);
829
830 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
831 if (!desc) {
832 ret = -ENOBUFS;
833 goto exit;
834 }
835
836 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action);
837
838 exit:
839 ath12k_hal_srng_access_end(ab, srng);
840
841 spin_unlock_bh(&srng->lock);
842
843 return ret;
844 }
845
ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid * rx_tid,bool rel_link_desc)846 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid,
847 bool rel_link_desc)
848 {
849 struct ath12k_base *ab = rx_tid->ab;
850
851 lockdep_assert_held(&ab->base_lock);
852
853 if (rx_tid->dst_ring_desc) {
854 if (rel_link_desc)
855 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc,
856 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
857 kfree(rx_tid->dst_ring_desc);
858 rx_tid->dst_ring_desc = NULL;
859 }
860
861 rx_tid->cur_sn = 0;
862 rx_tid->last_frag_no = 0;
863 rx_tid->rx_frag_bitmap = 0;
864 __skb_queue_purge(&rx_tid->rx_frags);
865 }
866
ath12k_dp_rx_peer_tid_cleanup(struct ath12k * ar,struct ath12k_peer * peer)867 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer)
868 {
869 struct ath12k_dp_rx_tid *rx_tid;
870 int i;
871
872 lockdep_assert_held(&ar->ab->base_lock);
873
874 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
875 rx_tid = &peer->rx_tid[i];
876
877 ath12k_dp_rx_peer_tid_delete(ar, peer, i);
878 ath12k_dp_rx_frags_cleanup(rx_tid, true);
879
880 spin_unlock_bh(&ar->ab->base_lock);
881 del_timer_sync(&rx_tid->frag_timer);
882 spin_lock_bh(&ar->ab->base_lock);
883 }
884 }
885
ath12k_peer_rx_tid_reo_update(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)886 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar,
887 struct ath12k_peer *peer,
888 struct ath12k_dp_rx_tid *rx_tid,
889 u32 ba_win_sz, u16 ssn,
890 bool update_ssn)
891 {
892 struct ath12k_hal_reo_cmd cmd = {0};
893 int ret;
894
895 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
896 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
897 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
898 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
899 cmd.ba_window_size = ba_win_sz;
900
901 if (update_ssn) {
902 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
903 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN);
904 }
905
906 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
907 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
908 NULL);
909 if (ret) {
910 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
911 rx_tid->tid, ret);
912 return ret;
913 }
914
915 rx_tid->ba_win_sz = ba_win_sz;
916
917 return 0;
918 }
919
ath12k_dp_rx_peer_tid_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)920 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id,
921 u8 tid, u32 ba_win_sz, u16 ssn,
922 enum hal_pn_type pn_type)
923 {
924 struct ath12k_base *ab = ar->ab;
925 struct ath12k_dp *dp = &ab->dp;
926 struct hal_rx_reo_queue *addr_aligned;
927 struct ath12k_peer *peer;
928 struct ath12k_dp_rx_tid *rx_tid;
929 u32 hw_desc_sz;
930 void *vaddr;
931 dma_addr_t paddr;
932 int ret;
933
934 spin_lock_bh(&ab->base_lock);
935
936 peer = ath12k_peer_find(ab, vdev_id, peer_mac);
937 if (!peer) {
938 spin_unlock_bh(&ab->base_lock);
939 ath12k_warn(ab, "failed to find the peer to set up rx tid\n");
940 return -ENOENT;
941 }
942
943 if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) {
944 spin_unlock_bh(&ab->base_lock);
945 ath12k_warn(ab, "reo qref table is not setup\n");
946 return -EINVAL;
947 }
948
949 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) {
950 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n",
951 peer->peer_id, tid);
952 spin_unlock_bh(&ab->base_lock);
953 return -EINVAL;
954 }
955
956 rx_tid = &peer->rx_tid[tid];
957 /* Update the tid queue if it is already setup */
958 if (rx_tid->active) {
959 paddr = rx_tid->paddr;
960 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid,
961 ba_win_sz, ssn, true);
962 spin_unlock_bh(&ab->base_lock);
963 if (ret) {
964 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid);
965 return ret;
966 }
967
968 if (!ab->hw_params->reoq_lut_support) {
969 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
970 peer_mac,
971 paddr, tid, 1,
972 ba_win_sz);
973 if (ret) {
974 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n",
975 tid, ret);
976 return ret;
977 }
978 }
979
980 return 0;
981 }
982
983 rx_tid->tid = tid;
984
985 rx_tid->ba_win_sz = ba_win_sz;
986
987 /* TODO: Optimize the memory allocation for qos tid based on
988 * the actual BA window size in REO tid update path.
989 */
990 if (tid == HAL_DESC_REO_NON_QOS_TID)
991 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid);
992 else
993 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
994
995 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
996 if (!vaddr) {
997 spin_unlock_bh(&ab->base_lock);
998 return -ENOMEM;
999 }
1000
1001 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1002
1003 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1004 ssn, pn_type);
1005
1006 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1007 DMA_BIDIRECTIONAL);
1008
1009 ret = dma_mapping_error(ab->dev, paddr);
1010 if (ret) {
1011 spin_unlock_bh(&ab->base_lock);
1012 goto err_mem_free;
1013 }
1014
1015 rx_tid->vaddr = vaddr;
1016 rx_tid->paddr = paddr;
1017 rx_tid->size = hw_desc_sz;
1018 rx_tid->active = true;
1019
1020 if (ab->hw_params->reoq_lut_support) {
1021 /* Update the REO queue LUT at the corresponding peer id
1022 * and tid with qaddr.
1023 */
1024 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr);
1025 spin_unlock_bh(&ab->base_lock);
1026 } else {
1027 spin_unlock_bh(&ab->base_lock);
1028 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1029 paddr, tid, 1, ba_win_sz);
1030 }
1031
1032 return ret;
1033
1034 err_mem_free:
1035 kfree(vaddr);
1036
1037 return ret;
1038 }
1039
ath12k_dp_rx_ampdu_start(struct ath12k * ar,struct ieee80211_ampdu_params * params)1040 int ath12k_dp_rx_ampdu_start(struct ath12k *ar,
1041 struct ieee80211_ampdu_params *params)
1042 {
1043 struct ath12k_base *ab = ar->ab;
1044 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta);
1045 int vdev_id = arsta->arvif->vdev_id;
1046 int ret;
1047
1048 ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id,
1049 params->tid, params->buf_size,
1050 params->ssn, arsta->pn_type);
1051 if (ret)
1052 ath12k_warn(ab, "failed to setup rx tid %d\n", ret);
1053
1054 return ret;
1055 }
1056
ath12k_dp_rx_ampdu_stop(struct ath12k * ar,struct ieee80211_ampdu_params * params)1057 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar,
1058 struct ieee80211_ampdu_params *params)
1059 {
1060 struct ath12k_base *ab = ar->ab;
1061 struct ath12k_peer *peer;
1062 struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta);
1063 int vdev_id = arsta->arvif->vdev_id;
1064 bool active;
1065 int ret;
1066
1067 spin_lock_bh(&ab->base_lock);
1068
1069 peer = ath12k_peer_find(ab, vdev_id, params->sta->addr);
1070 if (!peer) {
1071 spin_unlock_bh(&ab->base_lock);
1072 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1073 return -ENOENT;
1074 }
1075
1076 active = peer->rx_tid[params->tid].active;
1077
1078 if (!active) {
1079 spin_unlock_bh(&ab->base_lock);
1080 return 0;
1081 }
1082
1083 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1084 spin_unlock_bh(&ab->base_lock);
1085 if (ret) {
1086 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1087 params->tid, ret);
1088 return ret;
1089 }
1090
1091 return ret;
1092 }
1093
ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1094 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif,
1095 const u8 *peer_addr,
1096 enum set_key_cmd key_cmd,
1097 struct ieee80211_key_conf *key)
1098 {
1099 struct ath12k *ar = arvif->ar;
1100 struct ath12k_base *ab = ar->ab;
1101 struct ath12k_hal_reo_cmd cmd = {0};
1102 struct ath12k_peer *peer;
1103 struct ath12k_dp_rx_tid *rx_tid;
1104 u8 tid;
1105 int ret = 0;
1106
1107 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1108 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1109 * for now.
1110 */
1111 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1112 return 0;
1113
1114 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
1115 cmd.upd0 = HAL_REO_CMD_UPD0_PN |
1116 HAL_REO_CMD_UPD0_PN_SIZE |
1117 HAL_REO_CMD_UPD0_PN_VALID |
1118 HAL_REO_CMD_UPD0_PN_CHECK |
1119 HAL_REO_CMD_UPD0_SVLD;
1120
1121 switch (key->cipher) {
1122 case WLAN_CIPHER_SUITE_TKIP:
1123 case WLAN_CIPHER_SUITE_CCMP:
1124 case WLAN_CIPHER_SUITE_CCMP_256:
1125 case WLAN_CIPHER_SUITE_GCMP:
1126 case WLAN_CIPHER_SUITE_GCMP_256:
1127 if (key_cmd == SET_KEY) {
1128 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1129 cmd.pn_size = 48;
1130 }
1131 break;
1132 default:
1133 break;
1134 }
1135
1136 spin_lock_bh(&ab->base_lock);
1137
1138 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr);
1139 if (!peer) {
1140 spin_unlock_bh(&ab->base_lock);
1141 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n",
1142 peer_addr);
1143 return -ENOENT;
1144 }
1145
1146 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1147 rx_tid = &peer->rx_tid[tid];
1148 if (!rx_tid->active)
1149 continue;
1150 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1151 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1152 ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
1153 HAL_REO_CMD_UPDATE_RX_QUEUE,
1154 &cmd, NULL);
1155 if (ret) {
1156 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n",
1157 tid, peer_addr, ret);
1158 break;
1159 }
1160 }
1161
1162 spin_unlock_bh(&ab->base_lock);
1163
1164 return ret;
1165 }
1166
ath12k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1167 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1168 u16 peer_id)
1169 {
1170 int i;
1171
1172 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1173 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1174 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1175 return i;
1176 } else {
1177 return i;
1178 }
1179 }
1180
1181 return -EINVAL;
1182 }
1183
ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1184 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab,
1185 u16 tag, u16 len, const void *ptr,
1186 void *data)
1187 {
1188 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status;
1189 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn;
1190 const struct htt_ppdu_stats_user_rate *user_rate;
1191 struct htt_ppdu_stats_info *ppdu_info;
1192 struct htt_ppdu_user_stats *user_stats;
1193 int cur_user;
1194 u16 peer_id;
1195
1196 ppdu_info = data;
1197
1198 switch (tag) {
1199 case HTT_PPDU_STATS_TAG_COMMON:
1200 if (len < sizeof(struct htt_ppdu_stats_common)) {
1201 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1202 len, tag);
1203 return -EINVAL;
1204 }
1205 memcpy(&ppdu_info->ppdu_stats.common, ptr,
1206 sizeof(struct htt_ppdu_stats_common));
1207 break;
1208 case HTT_PPDU_STATS_TAG_USR_RATE:
1209 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1210 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1211 len, tag);
1212 return -EINVAL;
1213 }
1214 user_rate = ptr;
1215 peer_id = le16_to_cpu(user_rate->sw_peer_id);
1216 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1217 peer_id);
1218 if (cur_user < 0)
1219 return -EINVAL;
1220 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1221 user_stats->peer_id = peer_id;
1222 user_stats->is_valid_peer_id = true;
1223 memcpy(&user_stats->rate, ptr,
1224 sizeof(struct htt_ppdu_stats_user_rate));
1225 user_stats->tlv_flags |= BIT(tag);
1226 break;
1227 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1228 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1229 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1230 len, tag);
1231 return -EINVAL;
1232 }
1233
1234 cmplt_cmn = ptr;
1235 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id);
1236 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1237 peer_id);
1238 if (cur_user < 0)
1239 return -EINVAL;
1240 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1241 user_stats->peer_id = peer_id;
1242 user_stats->is_valid_peer_id = true;
1243 memcpy(&user_stats->cmpltn_cmn, ptr,
1244 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1245 user_stats->tlv_flags |= BIT(tag);
1246 break;
1247 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1248 if (len <
1249 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1250 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1251 len, tag);
1252 return -EINVAL;
1253 }
1254
1255 ba_status = ptr;
1256 peer_id = le16_to_cpu(ba_status->sw_peer_id);
1257 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1258 peer_id);
1259 if (cur_user < 0)
1260 return -EINVAL;
1261 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1262 user_stats->peer_id = peer_id;
1263 user_stats->is_valid_peer_id = true;
1264 memcpy(&user_stats->ack_ba, ptr,
1265 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1266 user_stats->tlv_flags |= BIT(tag);
1267 break;
1268 }
1269 return 0;
1270 }
1271
ath12k_dp_htt_tlv_iter(struct ath12k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath12k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1272 int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
1273 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len,
1274 const void *ptr, void *data),
1275 void *data)
1276 {
1277 const struct htt_tlv *tlv;
1278 const void *begin = ptr;
1279 u16 tlv_tag, tlv_len;
1280 int ret = -EINVAL;
1281
1282 while (len > 0) {
1283 if (len < sizeof(*tlv)) {
1284 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1285 ptr - begin, len, sizeof(*tlv));
1286 return -EINVAL;
1287 }
1288 tlv = (struct htt_tlv *)ptr;
1289 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG);
1290 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN);
1291 ptr += sizeof(*tlv);
1292 len -= sizeof(*tlv);
1293
1294 if (tlv_len > len) {
1295 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1296 tlv_tag, ptr - begin, len, tlv_len);
1297 return -EINVAL;
1298 }
1299 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1300 if (ret == -ENOMEM)
1301 return ret;
1302
1303 ptr += tlv_len;
1304 len -= tlv_len;
1305 }
1306 return 0;
1307 }
1308
1309 static void
ath12k_update_per_peer_tx_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1310 ath12k_update_per_peer_tx_stats(struct ath12k *ar,
1311 struct htt_ppdu_stats *ppdu_stats, u8 user)
1312 {
1313 struct ath12k_base *ab = ar->ab;
1314 struct ath12k_peer *peer;
1315 struct ieee80211_sta *sta;
1316 struct ath12k_sta *arsta;
1317 struct htt_ppdu_stats_user_rate *user_rate;
1318 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1319 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1320 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1321 int ret;
1322 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1323 u32 v, succ_bytes = 0;
1324 u16 tones, rate = 0, succ_pkts = 0;
1325 u32 tx_duration = 0;
1326 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1327 bool is_ampdu = false;
1328
1329 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1330 return;
1331
1332 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1333 is_ampdu =
1334 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1335
1336 if (usr_stats->tlv_flags &
1337 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1338 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes);
1339 succ_pkts = le32_get_bits(usr_stats->ack_ba.info,
1340 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M);
1341 tid = le32_get_bits(usr_stats->ack_ba.info,
1342 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM);
1343 }
1344
1345 if (common->fes_duration_us)
1346 tx_duration = le32_to_cpu(common->fes_duration_us);
1347
1348 user_rate = &usr_stats->rate;
1349 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1350 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1351 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1352 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1353 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1354 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1355
1356 /* Note: If host configured fixed rates and in some other special
1357 * cases, the broadcast/management frames are sent in different rates.
1358 * Firmware rate's control to be skipped for this?
1359 */
1360
1361 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) {
1362 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1363 return;
1364 }
1365
1366 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) {
1367 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1368 return;
1369 }
1370
1371 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) {
1372 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1373 mcs, nss);
1374 return;
1375 }
1376
1377 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1378 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs,
1379 flags,
1380 &rate_idx,
1381 &rate);
1382 if (ret < 0)
1383 return;
1384 }
1385
1386 rcu_read_lock();
1387 spin_lock_bh(&ab->base_lock);
1388 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id);
1389
1390 if (!peer || !peer->sta) {
1391 spin_unlock_bh(&ab->base_lock);
1392 rcu_read_unlock();
1393 return;
1394 }
1395
1396 sta = peer->sta;
1397 arsta = ath12k_sta_to_arsta(sta);
1398
1399 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1400
1401 switch (flags) {
1402 case WMI_RATE_PREAMBLE_OFDM:
1403 arsta->txrate.legacy = rate;
1404 break;
1405 case WMI_RATE_PREAMBLE_CCK:
1406 arsta->txrate.legacy = rate;
1407 break;
1408 case WMI_RATE_PREAMBLE_HT:
1409 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1410 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1411 if (sgi)
1412 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1413 break;
1414 case WMI_RATE_PREAMBLE_VHT:
1415 arsta->txrate.mcs = mcs;
1416 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1417 if (sgi)
1418 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1419 break;
1420 case WMI_RATE_PREAMBLE_HE:
1421 arsta->txrate.mcs = mcs;
1422 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1423 arsta->txrate.he_dcm = dcm;
1424 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
1425 tones = le16_to_cpu(user_rate->ru_end) -
1426 le16_to_cpu(user_rate->ru_start) + 1;
1427 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones);
1428 arsta->txrate.he_ru_alloc = v;
1429 break;
1430 }
1431
1432 arsta->txrate.nss = nss;
1433 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw);
1434 arsta->tx_duration += tx_duration;
1435 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1436
1437 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1438 * So skip peer stats update for mgmt packets.
1439 */
1440 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1441 memset(peer_stats, 0, sizeof(*peer_stats));
1442 peer_stats->succ_pkts = succ_pkts;
1443 peer_stats->succ_bytes = succ_bytes;
1444 peer_stats->is_ampdu = is_ampdu;
1445 peer_stats->duration = tx_duration;
1446 peer_stats->ba_fails =
1447 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1448 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1449 }
1450
1451 spin_unlock_bh(&ab->base_lock);
1452 rcu_read_unlock();
1453 }
1454
ath12k_htt_update_ppdu_stats(struct ath12k * ar,struct htt_ppdu_stats * ppdu_stats)1455 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar,
1456 struct htt_ppdu_stats *ppdu_stats)
1457 {
1458 u8 user;
1459
1460 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1461 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1462 }
1463
1464 static
ath12k_dp_htt_get_ppdu_desc(struct ath12k * ar,u32 ppdu_id)1465 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar,
1466 u32 ppdu_id)
1467 {
1468 struct htt_ppdu_stats_info *ppdu_info;
1469
1470 lockdep_assert_held(&ar->data_lock);
1471 if (!list_empty(&ar->ppdu_stats_info)) {
1472 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1473 if (ppdu_info->ppdu_id == ppdu_id)
1474 return ppdu_info;
1475 }
1476
1477 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1478 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1479 typeof(*ppdu_info), list);
1480 list_del(&ppdu_info->list);
1481 ar->ppdu_stat_list_depth--;
1482 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1483 kfree(ppdu_info);
1484 }
1485 }
1486
1487 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1488 if (!ppdu_info)
1489 return NULL;
1490
1491 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1492 ar->ppdu_stat_list_depth++;
1493
1494 return ppdu_info;
1495 }
1496
ath12k_copy_to_delay_stats(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1497 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer,
1498 struct htt_ppdu_user_stats *usr_stats)
1499 {
1500 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id);
1501 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0);
1502 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end);
1503 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start);
1504 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1);
1505 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags);
1506 peer->ppdu_stats_delayba.resp_rate_flags =
1507 le32_to_cpu(usr_stats->rate.resp_rate_flags);
1508
1509 peer->delayba_flag = true;
1510 }
1511
ath12k_copy_to_bar(struct ath12k_peer * peer,struct htt_ppdu_user_stats * usr_stats)1512 static void ath12k_copy_to_bar(struct ath12k_peer *peer,
1513 struct htt_ppdu_user_stats *usr_stats)
1514 {
1515 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id);
1516 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0);
1517 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end);
1518 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start);
1519 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1);
1520 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags);
1521 usr_stats->rate.resp_rate_flags =
1522 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags);
1523
1524 peer->delayba_flag = false;
1525 }
1526
ath12k_htt_pull_ppdu_stats(struct ath12k_base * ab,struct sk_buff * skb)1527 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab,
1528 struct sk_buff *skb)
1529 {
1530 struct ath12k_htt_ppdu_stats_msg *msg;
1531 struct htt_ppdu_stats_info *ppdu_info;
1532 struct ath12k_peer *peer = NULL;
1533 struct htt_ppdu_user_stats *usr_stats = NULL;
1534 u32 peer_id = 0;
1535 struct ath12k *ar;
1536 int ret, i;
1537 u8 pdev_id;
1538 u32 ppdu_id, len;
1539
1540 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data;
1541 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE);
1542 if (len > (skb->len - struct_size(msg, data, 0))) {
1543 ath12k_warn(ab,
1544 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n",
1545 len, skb->len);
1546 return -EINVAL;
1547 }
1548
1549 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID);
1550 ppdu_id = le32_to_cpu(msg->ppdu_id);
1551
1552 rcu_read_lock();
1553 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1554 if (!ar) {
1555 ret = -EINVAL;
1556 goto exit;
1557 }
1558
1559 spin_lock_bh(&ar->data_lock);
1560 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1561 if (!ppdu_info) {
1562 spin_unlock_bh(&ar->data_lock);
1563 ret = -EINVAL;
1564 goto exit;
1565 }
1566
1567 ppdu_info->ppdu_id = ppdu_id;
1568 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len,
1569 ath12k_htt_tlv_ppdu_stats_parse,
1570 (void *)ppdu_info);
1571 if (ret) {
1572 spin_unlock_bh(&ar->data_lock);
1573 ath12k_warn(ab, "Failed to parse tlv %d\n", ret);
1574 goto exit;
1575 }
1576
1577 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) {
1578 spin_unlock_bh(&ar->data_lock);
1579 ath12k_warn(ab,
1580 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n",
1581 ppdu_info->ppdu_stats.common.num_users,
1582 HTT_PPDU_STATS_MAX_USERS);
1583 ret = -EINVAL;
1584 goto exit;
1585 }
1586
1587 /* back up data rate tlv for all peers */
1588 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA &&
1589 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) &&
1590 ppdu_info->delay_ba) {
1591 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) {
1592 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1593 spin_lock_bh(&ab->base_lock);
1594 peer = ath12k_peer_find_by_id(ab, peer_id);
1595 if (!peer) {
1596 spin_unlock_bh(&ab->base_lock);
1597 continue;
1598 }
1599
1600 usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1601 if (usr_stats->delay_ba)
1602 ath12k_copy_to_delay_stats(peer, usr_stats);
1603 spin_unlock_bh(&ab->base_lock);
1604 }
1605 }
1606
1607 /* restore all peers' data rate tlv to mu-bar tlv */
1608 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR &&
1609 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) {
1610 for (i = 0; i < ppdu_info->bar_num_users; i++) {
1611 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
1612 spin_lock_bh(&ab->base_lock);
1613 peer = ath12k_peer_find_by_id(ab, peer_id);
1614 if (!peer) {
1615 spin_unlock_bh(&ab->base_lock);
1616 continue;
1617 }
1618
1619 usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
1620 if (peer->delayba_flag)
1621 ath12k_copy_to_bar(peer, usr_stats);
1622 spin_unlock_bh(&ab->base_lock);
1623 }
1624 }
1625
1626 spin_unlock_bh(&ar->data_lock);
1627
1628 exit:
1629 rcu_read_unlock();
1630
1631 return ret;
1632 }
1633
ath12k_htt_mlo_offset_event_handler(struct ath12k_base * ab,struct sk_buff * skb)1634 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab,
1635 struct sk_buff *skb)
1636 {
1637 struct ath12k_htt_mlo_offset_msg *msg;
1638 struct ath12k_pdev *pdev;
1639 struct ath12k *ar;
1640 u8 pdev_id;
1641
1642 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data;
1643 pdev_id = u32_get_bits(__le32_to_cpu(msg->info),
1644 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID);
1645
1646 rcu_read_lock();
1647 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
1648 if (!ar) {
1649 ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id);
1650 goto exit;
1651 }
1652
1653 spin_lock_bh(&ar->data_lock);
1654 pdev = ar->pdev;
1655
1656 pdev->timestamp.info = __le32_to_cpu(msg->info);
1657 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us);
1658 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us);
1659 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo);
1660 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi);
1661 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks);
1662 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks);
1663 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer);
1664
1665 spin_unlock_bh(&ar->data_lock);
1666 exit:
1667 rcu_read_unlock();
1668 }
1669
ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base * ab,struct sk_buff * skb)1670 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
1671 struct sk_buff *skb)
1672 {
1673 struct ath12k_dp *dp = &ab->dp;
1674 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1675 enum htt_t2h_msg_type type;
1676 u16 peer_id;
1677 u8 vdev_id;
1678 u8 mac_addr[ETH_ALEN];
1679 u16 peer_mac_h16;
1680 u16 ast_hash = 0;
1681 u16 hw_peer_id;
1682
1683 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE);
1684
1685 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1686
1687 switch (type) {
1688 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1689 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version,
1690 HTT_T2H_VERSION_CONF_MAJOR);
1691 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version,
1692 HTT_T2H_VERSION_CONF_MINOR);
1693 complete(&dp->htt_tgt_version_received);
1694 break;
1695 /* TODO: remove unused peer map versions after testing */
1696 case HTT_T2H_MSG_TYPE_PEER_MAP:
1697 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1698 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1699 peer_id = le32_get_bits(resp->peer_map_ev.info,
1700 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1701 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1702 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1703 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1704 peer_mac_h16, mac_addr);
1705 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1706 break;
1707 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1708 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1709 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1710 peer_id = le32_get_bits(resp->peer_map_ev.info,
1711 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1712 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1713 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1714 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1715 peer_mac_h16, mac_addr);
1716 ast_hash = le32_get_bits(resp->peer_map_ev.info2,
1717 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL);
1718 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1,
1719 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID);
1720 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1721 hw_peer_id);
1722 break;
1723 case HTT_T2H_MSG_TYPE_PEER_MAP3:
1724 vdev_id = le32_get_bits(resp->peer_map_ev.info,
1725 HTT_T2H_PEER_MAP_INFO_VDEV_ID);
1726 peer_id = le32_get_bits(resp->peer_map_ev.info,
1727 HTT_T2H_PEER_MAP_INFO_PEER_ID);
1728 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
1729 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
1730 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
1731 peer_mac_h16, mac_addr);
1732 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1733 peer_id);
1734 break;
1735 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1736 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1737 peer_id = le32_get_bits(resp->peer_unmap_ev.info,
1738 HTT_T2H_PEER_UNMAP_INFO_PEER_ID);
1739 ath12k_peer_unmap_event(ab, peer_id);
1740 break;
1741 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1742 ath12k_htt_pull_ppdu_stats(ab, skb);
1743 break;
1744 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1745 ath12k_debugfs_htt_ext_stats_handler(ab, skb);
1746 break;
1747 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND:
1748 ath12k_htt_mlo_offset_event_handler(ab, skb);
1749 break;
1750 default:
1751 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n",
1752 type);
1753 break;
1754 }
1755
1756 dev_kfree_skb_any(skb);
1757 }
1758
ath12k_dp_rx_msdu_coalesce(struct ath12k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1759 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar,
1760 struct sk_buff_head *msdu_list,
1761 struct sk_buff *first, struct sk_buff *last,
1762 u8 l3pad_bytes, int msdu_len)
1763 {
1764 struct ath12k_base *ab = ar->ab;
1765 struct sk_buff *skb;
1766 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1767 int buf_first_hdr_len, buf_first_len;
1768 struct hal_rx_desc *ldesc;
1769 int space_extra, rem_len, buf_len;
1770 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
1771
1772 /* As the msdu is spread across multiple rx buffers,
1773 * find the offset to the start of msdu for computing
1774 * the length of the msdu in the first buffer.
1775 */
1776 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1777 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1778
1779 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1780 skb_put(first, buf_first_hdr_len + msdu_len);
1781 skb_pull(first, buf_first_hdr_len);
1782 return 0;
1783 }
1784
1785 ldesc = (struct hal_rx_desc *)last->data;
1786 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc);
1787 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc);
1788
1789 /* MSDU spans over multiple buffers because the length of the MSDU
1790 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1791 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1792 */
1793 skb_put(first, DP_RX_BUFFER_SIZE);
1794 skb_pull(first, buf_first_hdr_len);
1795
1796 /* When an MSDU spread over multiple buffers MSDU_END
1797 * tlvs are valid only in the last buffer. Copy those tlvs.
1798 */
1799 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1800
1801 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1802 if (space_extra > 0 &&
1803 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1804 /* Free up all buffers of the MSDU */
1805 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1806 rxcb = ATH12K_SKB_RXCB(skb);
1807 if (!rxcb->is_continuation) {
1808 dev_kfree_skb_any(skb);
1809 break;
1810 }
1811 dev_kfree_skb_any(skb);
1812 }
1813 return -ENOMEM;
1814 }
1815
1816 rem_len = msdu_len - buf_first_len;
1817 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1818 rxcb = ATH12K_SKB_RXCB(skb);
1819 if (rxcb->is_continuation)
1820 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1821 else
1822 buf_len = rem_len;
1823
1824 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1825 WARN_ON_ONCE(1);
1826 dev_kfree_skb_any(skb);
1827 return -EINVAL;
1828 }
1829
1830 skb_put(skb, buf_len + hal_rx_desc_sz);
1831 skb_pull(skb, hal_rx_desc_sz);
1832 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1833 buf_len);
1834 dev_kfree_skb_any(skb);
1835
1836 rem_len -= buf_len;
1837 if (!rxcb->is_continuation)
1838 break;
1839 }
1840
1841 return 0;
1842 }
1843
ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1844 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1845 struct sk_buff *first)
1846 {
1847 struct sk_buff *skb;
1848 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
1849
1850 if (!rxcb->is_continuation)
1851 return first;
1852
1853 skb_queue_walk(msdu_list, skb) {
1854 rxcb = ATH12K_SKB_RXCB(skb);
1855 if (!rxcb->is_continuation)
1856 return skb;
1857 }
1858
1859 return NULL;
1860 }
1861
ath12k_dp_rx_h_csum_offload(struct ath12k * ar,struct sk_buff * msdu)1862 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu)
1863 {
1864 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1865 struct ath12k_base *ab = ar->ab;
1866 bool ip_csum_fail, l4_csum_fail;
1867
1868 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc);
1869 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc);
1870
1871 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1872 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1873 }
1874
ath12k_dp_rx_crypto_mic_len(struct ath12k * ar,enum hal_encrypt_type enctype)1875 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar,
1876 enum hal_encrypt_type enctype)
1877 {
1878 switch (enctype) {
1879 case HAL_ENCRYPT_TYPE_OPEN:
1880 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1881 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1882 return 0;
1883 case HAL_ENCRYPT_TYPE_CCMP_128:
1884 return IEEE80211_CCMP_MIC_LEN;
1885 case HAL_ENCRYPT_TYPE_CCMP_256:
1886 return IEEE80211_CCMP_256_MIC_LEN;
1887 case HAL_ENCRYPT_TYPE_GCMP_128:
1888 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1889 return IEEE80211_GCMP_MIC_LEN;
1890 case HAL_ENCRYPT_TYPE_WEP_40:
1891 case HAL_ENCRYPT_TYPE_WEP_104:
1892 case HAL_ENCRYPT_TYPE_WEP_128:
1893 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1894 case HAL_ENCRYPT_TYPE_WAPI:
1895 break;
1896 }
1897
1898 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1899 return 0;
1900 }
1901
ath12k_dp_rx_crypto_param_len(struct ath12k * ar,enum hal_encrypt_type enctype)1902 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar,
1903 enum hal_encrypt_type enctype)
1904 {
1905 switch (enctype) {
1906 case HAL_ENCRYPT_TYPE_OPEN:
1907 return 0;
1908 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1909 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1910 return IEEE80211_TKIP_IV_LEN;
1911 case HAL_ENCRYPT_TYPE_CCMP_128:
1912 return IEEE80211_CCMP_HDR_LEN;
1913 case HAL_ENCRYPT_TYPE_CCMP_256:
1914 return IEEE80211_CCMP_256_HDR_LEN;
1915 case HAL_ENCRYPT_TYPE_GCMP_128:
1916 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1917 return IEEE80211_GCMP_HDR_LEN;
1918 case HAL_ENCRYPT_TYPE_WEP_40:
1919 case HAL_ENCRYPT_TYPE_WEP_104:
1920 case HAL_ENCRYPT_TYPE_WEP_128:
1921 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1922 case HAL_ENCRYPT_TYPE_WAPI:
1923 break;
1924 }
1925
1926 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1927 return 0;
1928 }
1929
ath12k_dp_rx_crypto_icv_len(struct ath12k * ar,enum hal_encrypt_type enctype)1930 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar,
1931 enum hal_encrypt_type enctype)
1932 {
1933 switch (enctype) {
1934 case HAL_ENCRYPT_TYPE_OPEN:
1935 case HAL_ENCRYPT_TYPE_CCMP_128:
1936 case HAL_ENCRYPT_TYPE_CCMP_256:
1937 case HAL_ENCRYPT_TYPE_GCMP_128:
1938 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1939 return 0;
1940 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1941 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1942 return IEEE80211_TKIP_ICV_LEN;
1943 case HAL_ENCRYPT_TYPE_WEP_40:
1944 case HAL_ENCRYPT_TYPE_WEP_104:
1945 case HAL_ENCRYPT_TYPE_WEP_128:
1946 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1947 case HAL_ENCRYPT_TYPE_WAPI:
1948 break;
1949 }
1950
1951 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1952 return 0;
1953 }
1954
ath12k_dp_rx_h_undecap_nwifi(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1955 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar,
1956 struct sk_buff *msdu,
1957 enum hal_encrypt_type enctype,
1958 struct ieee80211_rx_status *status)
1959 {
1960 struct ath12k_base *ab = ar->ab;
1961 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
1962 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1963 struct ieee80211_hdr *hdr;
1964 size_t hdr_len;
1965 u8 *crypto_hdr;
1966 u16 qos_ctl;
1967
1968 /* pull decapped header */
1969 hdr = (struct ieee80211_hdr *)msdu->data;
1970 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1971 skb_pull(msdu, hdr_len);
1972
1973 /* Rebuild qos header */
1974 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1975
1976 /* Reset the order bit as the HT_Control header is stripped */
1977 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1978
1979 qos_ctl = rxcb->tid;
1980
1981 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc))
1982 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1983
1984 /* TODO: Add other QoS ctl fields when required */
1985
1986 /* copy decap header before overwriting for reuse below */
1987 memcpy(decap_hdr, hdr, hdr_len);
1988
1989 /* Rebuild crypto header for mac80211 use */
1990 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
1991 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype));
1992 ath12k_dp_rx_desc_get_crypto_header(ar->ab,
1993 rxcb->rx_desc, crypto_hdr,
1994 enctype);
1995 }
1996
1997 memcpy(skb_push(msdu,
1998 IEEE80211_QOS_CTL_LEN), &qos_ctl,
1999 IEEE80211_QOS_CTL_LEN);
2000 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2001 }
2002
ath12k_dp_rx_h_undecap_raw(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2003 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu,
2004 enum hal_encrypt_type enctype,
2005 struct ieee80211_rx_status *status,
2006 bool decrypted)
2007 {
2008 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2009 struct ieee80211_hdr *hdr;
2010 size_t hdr_len;
2011 size_t crypto_len;
2012
2013 if (!rxcb->is_first_msdu ||
2014 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2015 WARN_ON_ONCE(1);
2016 return;
2017 }
2018
2019 skb_trim(msdu, msdu->len - FCS_LEN);
2020
2021 if (!decrypted)
2022 return;
2023
2024 hdr = (void *)msdu->data;
2025
2026 /* Tail */
2027 if (status->flag & RX_FLAG_IV_STRIPPED) {
2028 skb_trim(msdu, msdu->len -
2029 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2030
2031 skb_trim(msdu, msdu->len -
2032 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2033 } else {
2034 /* MIC */
2035 if (status->flag & RX_FLAG_MIC_STRIPPED)
2036 skb_trim(msdu, msdu->len -
2037 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2038
2039 /* ICV */
2040 if (status->flag & RX_FLAG_ICV_STRIPPED)
2041 skb_trim(msdu, msdu->len -
2042 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2043 }
2044
2045 /* MMIC */
2046 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2047 !ieee80211_has_morefrags(hdr->frame_control) &&
2048 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2049 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2050
2051 /* Head */
2052 if (status->flag & RX_FLAG_IV_STRIPPED) {
2053 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2054 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2055
2056 memmove(msdu->data + crypto_len, msdu->data, hdr_len);
2057 skb_pull(msdu, crypto_len);
2058 }
2059 }
2060
ath12k_get_dot11_hdr_from_rx_desc(struct ath12k * ar,struct sk_buff * msdu,struct ath12k_skb_rxcb * rxcb,struct ieee80211_rx_status * status,enum hal_encrypt_type enctype)2061 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar,
2062 struct sk_buff *msdu,
2063 struct ath12k_skb_rxcb *rxcb,
2064 struct ieee80211_rx_status *status,
2065 enum hal_encrypt_type enctype)
2066 {
2067 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2068 struct ath12k_base *ab = ar->ab;
2069 size_t hdr_len, crypto_len;
2070 struct ieee80211_hdr *hdr;
2071 u16 qos_ctl;
2072 __le16 fc;
2073 u8 *crypto_hdr;
2074
2075 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2076 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2077 crypto_hdr = skb_push(msdu, crypto_len);
2078 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype);
2079 }
2080
2081 fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc));
2082 hdr_len = ieee80211_hdrlen(fc);
2083 skb_push(msdu, hdr_len);
2084 hdr = (struct ieee80211_hdr *)msdu->data;
2085 hdr->frame_control = fc;
2086
2087 /* Get wifi header from rx_desc */
2088 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr);
2089
2090 if (rxcb->is_mcbc)
2091 status->flag &= ~RX_FLAG_PN_VALIDATED;
2092
2093 /* Add QOS header */
2094 if (ieee80211_is_data_qos(hdr->frame_control)) {
2095 qos_ctl = rxcb->tid;
2096 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc))
2097 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2098
2099 /* TODO: Add other QoS ctl fields when required */
2100 memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN),
2101 &qos_ctl, IEEE80211_QOS_CTL_LEN);
2102 }
2103 }
2104
ath12k_dp_rx_h_undecap_eth(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2105 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar,
2106 struct sk_buff *msdu,
2107 enum hal_encrypt_type enctype,
2108 struct ieee80211_rx_status *status)
2109 {
2110 struct ieee80211_hdr *hdr;
2111 struct ethhdr *eth;
2112 u8 da[ETH_ALEN];
2113 u8 sa[ETH_ALEN];
2114 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2115 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}};
2116
2117 eth = (struct ethhdr *)msdu->data;
2118 ether_addr_copy(da, eth->h_dest);
2119 ether_addr_copy(sa, eth->h_source);
2120 rfc.snap_type = eth->h_proto;
2121 skb_pull(msdu, sizeof(*eth));
2122 memcpy(skb_push(msdu, sizeof(rfc)), &rfc,
2123 sizeof(rfc));
2124 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype);
2125
2126 /* original 802.11 header has a different DA and in
2127 * case of 4addr it may also have different SA
2128 */
2129 hdr = (struct ieee80211_hdr *)msdu->data;
2130 ether_addr_copy(ieee80211_get_DA(hdr), da);
2131 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2132 }
2133
ath12k_dp_rx_h_undecap(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2134 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu,
2135 struct hal_rx_desc *rx_desc,
2136 enum hal_encrypt_type enctype,
2137 struct ieee80211_rx_status *status,
2138 bool decrypted)
2139 {
2140 struct ath12k_base *ab = ar->ab;
2141 u8 decap;
2142 struct ethhdr *ehdr;
2143
2144 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc);
2145
2146 switch (decap) {
2147 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2148 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status);
2149 break;
2150 case DP_RX_DECAP_TYPE_RAW:
2151 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2152 decrypted);
2153 break;
2154 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2155 ehdr = (struct ethhdr *)msdu->data;
2156
2157 /* mac80211 allows fast path only for authorized STA */
2158 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2159 ATH12K_SKB_RXCB(msdu)->is_eapol = true;
2160 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2161 break;
2162 }
2163
2164 /* PN for mcast packets will be validated in mac80211;
2165 * remove eth header and add 802.11 header.
2166 */
2167 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2168 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
2169 break;
2170 case DP_RX_DECAP_TYPE_8023:
2171 /* TODO: Handle undecap for these formats */
2172 break;
2173 }
2174 }
2175
2176 struct ath12k_peer *
ath12k_dp_rx_h_find_peer(struct ath12k_base * ab,struct sk_buff * msdu)2177 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu)
2178 {
2179 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2180 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2181 struct ath12k_peer *peer = NULL;
2182
2183 lockdep_assert_held(&ab->base_lock);
2184
2185 if (rxcb->peer_id)
2186 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id);
2187
2188 if (peer)
2189 return peer;
2190
2191 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2192 return NULL;
2193
2194 peer = ath12k_peer_find_by_addr(ab,
2195 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab,
2196 rx_desc));
2197 return peer;
2198 }
2199
ath12k_dp_rx_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2200 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar,
2201 struct sk_buff *msdu,
2202 struct hal_rx_desc *rx_desc,
2203 struct ieee80211_rx_status *rx_status)
2204 {
2205 bool fill_crypto_hdr;
2206 struct ath12k_base *ab = ar->ab;
2207 struct ath12k_skb_rxcb *rxcb;
2208 enum hal_encrypt_type enctype;
2209 bool is_decrypted = false;
2210 struct ieee80211_hdr *hdr;
2211 struct ath12k_peer *peer;
2212 u32 err_bitmap;
2213
2214 /* PN for multicast packets will be checked in mac80211 */
2215 rxcb = ATH12K_SKB_RXCB(msdu);
2216 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc);
2217 rxcb->is_mcbc = fill_crypto_hdr;
2218
2219 if (rxcb->is_mcbc)
2220 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc);
2221
2222 spin_lock_bh(&ar->ab->base_lock);
2223 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
2224 if (peer) {
2225 if (rxcb->is_mcbc)
2226 enctype = peer->sec_type_grp;
2227 else
2228 enctype = peer->sec_type;
2229 } else {
2230 enctype = HAL_ENCRYPT_TYPE_OPEN;
2231 }
2232 spin_unlock_bh(&ar->ab->base_lock);
2233
2234 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
2235 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2236 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc);
2237
2238 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2239 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2240 RX_FLAG_MMIC_ERROR |
2241 RX_FLAG_DECRYPTED |
2242 RX_FLAG_IV_STRIPPED |
2243 RX_FLAG_MMIC_STRIPPED);
2244
2245 if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
2246 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2247 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC)
2248 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2249
2250 if (is_decrypted) {
2251 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2252
2253 if (fill_crypto_hdr)
2254 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2255 RX_FLAG_ICV_STRIPPED;
2256 else
2257 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2258 RX_FLAG_PN_VALIDATED;
2259 }
2260
2261 ath12k_dp_rx_h_csum_offload(ar, msdu);
2262 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
2263 enctype, rx_status, is_decrypted);
2264
2265 if (!is_decrypted || fill_crypto_hdr)
2266 return;
2267
2268 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) !=
2269 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2270 hdr = (void *)msdu->data;
2271 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2272 }
2273 }
2274
ath12k_dp_rx_h_rate(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2275 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2276 struct ieee80211_rx_status *rx_status)
2277 {
2278 struct ath12k_base *ab = ar->ab;
2279 struct ieee80211_supported_band *sband;
2280 enum rx_msdu_start_pkt_type pkt_type;
2281 u8 bw;
2282 u8 rate_mcs, nss;
2283 u8 sgi;
2284 bool is_cck;
2285
2286 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc);
2287 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc);
2288 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc);
2289 nss = ath12k_dp_rx_h_nss(ab, rx_desc);
2290 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc);
2291
2292 switch (pkt_type) {
2293 case RX_MSDU_START_PKT_TYPE_11A:
2294 case RX_MSDU_START_PKT_TYPE_11B:
2295 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2296 sband = &ar->mac.sbands[rx_status->band];
2297 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs,
2298 is_cck);
2299 break;
2300 case RX_MSDU_START_PKT_TYPE_11N:
2301 rx_status->encoding = RX_ENC_HT;
2302 if (rate_mcs > ATH12K_HT_MCS_MAX) {
2303 ath12k_warn(ar->ab,
2304 "Received with invalid mcs in HT mode %d\n",
2305 rate_mcs);
2306 break;
2307 }
2308 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2309 if (sgi)
2310 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2311 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2312 break;
2313 case RX_MSDU_START_PKT_TYPE_11AC:
2314 rx_status->encoding = RX_ENC_VHT;
2315 rx_status->rate_idx = rate_mcs;
2316 if (rate_mcs > ATH12K_VHT_MCS_MAX) {
2317 ath12k_warn(ar->ab,
2318 "Received with invalid mcs in VHT mode %d\n",
2319 rate_mcs);
2320 break;
2321 }
2322 rx_status->nss = nss;
2323 if (sgi)
2324 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2325 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2326 break;
2327 case RX_MSDU_START_PKT_TYPE_11AX:
2328 rx_status->rate_idx = rate_mcs;
2329 if (rate_mcs > ATH12K_HE_MCS_MAX) {
2330 ath12k_warn(ar->ab,
2331 "Received with invalid mcs in HE mode %d\n",
2332 rate_mcs);
2333 break;
2334 }
2335 rx_status->encoding = RX_ENC_HE;
2336 rx_status->nss = nss;
2337 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
2338 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
2339 break;
2340 }
2341 }
2342
ath12k_dp_rx_h_ppdu(struct ath12k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2343 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc,
2344 struct ieee80211_rx_status *rx_status)
2345 {
2346 struct ath12k_base *ab = ar->ab;
2347 u8 channel_num;
2348 u32 center_freq, meta_data;
2349 struct ieee80211_channel *channel;
2350
2351 rx_status->freq = 0;
2352 rx_status->rate_idx = 0;
2353 rx_status->nss = 0;
2354 rx_status->encoding = RX_ENC_LEGACY;
2355 rx_status->bw = RATE_INFO_BW_20;
2356 rx_status->enc_flags = 0;
2357
2358 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2359
2360 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc);
2361 channel_num = meta_data;
2362 center_freq = meta_data >> 16;
2363
2364 if (center_freq >= ATH12K_MIN_6G_FREQ &&
2365 center_freq <= ATH12K_MAX_6G_FREQ) {
2366 rx_status->band = NL80211_BAND_6GHZ;
2367 rx_status->freq = center_freq;
2368 } else if (channel_num >= 1 && channel_num <= 14) {
2369 rx_status->band = NL80211_BAND_2GHZ;
2370 } else if (channel_num >= 36 && channel_num <= 173) {
2371 rx_status->band = NL80211_BAND_5GHZ;
2372 } else {
2373 spin_lock_bh(&ar->data_lock);
2374 channel = ar->rx_channel;
2375 if (channel) {
2376 rx_status->band = channel->band;
2377 channel_num =
2378 ieee80211_frequency_to_channel(channel->center_freq);
2379 }
2380 spin_unlock_bh(&ar->data_lock);
2381 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ",
2382 rx_desc, sizeof(*rx_desc));
2383 }
2384
2385 if (rx_status->band != NL80211_BAND_6GHZ)
2386 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2387 rx_status->band);
2388
2389 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status);
2390 }
2391
ath12k_dp_rx_deliver_msdu(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2392 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
2393 struct sk_buff *msdu,
2394 struct ieee80211_rx_status *status)
2395 {
2396 struct ath12k_base *ab = ar->ab;
2397 static const struct ieee80211_radiotap_he known = {
2398 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2399 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2400 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2401 };
2402 struct ieee80211_radiotap_he *he;
2403 struct ieee80211_rx_status *rx_status;
2404 struct ieee80211_sta *pubsta;
2405 struct ath12k_peer *peer;
2406 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
2407 u8 decap = DP_RX_DECAP_TYPE_RAW;
2408 bool is_mcbc = rxcb->is_mcbc;
2409 bool is_eapol = rxcb->is_eapol;
2410
2411 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2412 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2413 he = skb_push(msdu, sizeof(known));
2414 memcpy(he, &known, sizeof(known));
2415 status->flag |= RX_FLAG_RADIOTAP_HE;
2416 }
2417
2418 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2419 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc);
2420
2421 spin_lock_bh(&ab->base_lock);
2422 peer = ath12k_dp_rx_h_find_peer(ab, msdu);
2423
2424 pubsta = peer ? peer->sta : NULL;
2425
2426 spin_unlock_bh(&ab->base_lock);
2427
2428 ath12k_dbg(ab, ATH12K_DBG_DATA,
2429 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2430 msdu,
2431 msdu->len,
2432 peer ? peer->addr : NULL,
2433 rxcb->tid,
2434 is_mcbc ? "mcast" : "ucast",
2435 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc),
2436 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2437 (status->encoding == RX_ENC_HT) ? "ht" : "",
2438 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2439 (status->encoding == RX_ENC_HE) ? "he" : "",
2440 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2441 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2442 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2443 (status->bw == RATE_INFO_BW_320) ? "320" : "",
2444 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2445 status->rate_idx,
2446 status->nss,
2447 status->freq,
2448 status->band, status->flag,
2449 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2450 !!(status->flag & RX_FLAG_MMIC_ERROR),
2451 !!(status->flag & RX_FLAG_AMSDU_MORE));
2452
2453 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
2454 msdu->data, msdu->len);
2455
2456 rx_status = IEEE80211_SKB_RXCB(msdu);
2457 *rx_status = *status;
2458
2459 /* TODO: trace rx packet */
2460
2461 /* PN for multicast packets are not validate in HW,
2462 * so skip 802.3 rx path
2463 * Also, fast_rx expects the STA to be authorized, hence
2464 * eapol packets are sent in slow path.
2465 */
2466 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2467 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2468 rx_status->flag |= RX_FLAG_8023;
2469
2470 ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
2471 }
2472
ath12k_dp_rx_process_msdu(struct ath12k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2473 static int ath12k_dp_rx_process_msdu(struct ath12k *ar,
2474 struct sk_buff *msdu,
2475 struct sk_buff_head *msdu_list,
2476 struct ieee80211_rx_status *rx_status)
2477 {
2478 struct ath12k_base *ab = ar->ab;
2479 struct hal_rx_desc *rx_desc, *lrx_desc;
2480 struct ath12k_skb_rxcb *rxcb;
2481 struct sk_buff *last_buf;
2482 u8 l3_pad_bytes;
2483 u16 msdu_len;
2484 int ret;
2485 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2486
2487 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2488 if (!last_buf) {
2489 ath12k_warn(ab,
2490 "No valid Rx buffer to access MSDU_END tlv\n");
2491 ret = -EIO;
2492 goto free_out;
2493 }
2494
2495 rx_desc = (struct hal_rx_desc *)msdu->data;
2496 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2497 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) {
2498 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n");
2499 ret = -EIO;
2500 goto free_out;
2501 }
2502
2503 rxcb = ATH12K_SKB_RXCB(msdu);
2504 rxcb->rx_desc = rx_desc;
2505 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc);
2506 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc);
2507
2508 if (rxcb->is_frag) {
2509 skb_pull(msdu, hal_rx_desc_sz);
2510 } else if (!rxcb->is_continuation) {
2511 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2512 ret = -EINVAL;
2513 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len);
2514 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
2515 sizeof(*rx_desc));
2516 goto free_out;
2517 }
2518 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2519 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2520 } else {
2521 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list,
2522 msdu, last_buf,
2523 l3_pad_bytes, msdu_len);
2524 if (ret) {
2525 ath12k_warn(ab,
2526 "failed to coalesce msdu rx buffer%d\n", ret);
2527 goto free_out;
2528 }
2529 }
2530
2531 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2532 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2533
2534 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2535
2536 return 0;
2537
2538 free_out:
2539 return ret;
2540 }
2541
ath12k_dp_rx_process_received_packets(struct ath12k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int ring_id)2542 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab,
2543 struct napi_struct *napi,
2544 struct sk_buff_head *msdu_list,
2545 int ring_id)
2546 {
2547 struct ieee80211_rx_status rx_status = {0};
2548 struct ath12k_skb_rxcb *rxcb;
2549 struct sk_buff *msdu;
2550 struct ath12k *ar;
2551 u8 mac_id, pdev_id;
2552 int ret;
2553
2554 if (skb_queue_empty(msdu_list))
2555 return;
2556
2557 rcu_read_lock();
2558
2559 while ((msdu = __skb_dequeue(msdu_list))) {
2560 rxcb = ATH12K_SKB_RXCB(msdu);
2561 mac_id = rxcb->mac_id;
2562 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
2563 ar = ab->pdevs[pdev_id].ar;
2564 if (!rcu_dereference(ab->pdevs_active[pdev_id])) {
2565 dev_kfree_skb_any(msdu);
2566 continue;
2567 }
2568
2569 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
2570 dev_kfree_skb_any(msdu);
2571 continue;
2572 }
2573
2574 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2575 if (ret) {
2576 ath12k_dbg(ab, ATH12K_DBG_DATA,
2577 "Unable to process msdu %d", ret);
2578 dev_kfree_skb_any(msdu);
2579 continue;
2580 }
2581
2582 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2583 }
2584
2585 rcu_read_unlock();
2586 }
2587
ath12k_dp_rx_get_peer_id(struct ath12k_base * ab,enum ath12k_peer_metadata_version ver,__le32 peer_metadata)2588 static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab,
2589 enum ath12k_peer_metadata_version ver,
2590 __le32 peer_metadata)
2591 {
2592 switch (ver) {
2593 default:
2594 ath12k_warn(ab, "Unknown peer metadata version: %d", ver);
2595 fallthrough;
2596 case ATH12K_PEER_METADATA_V0:
2597 return le32_get_bits(peer_metadata,
2598 RX_MPDU_DESC_META_DATA_V0_PEER_ID);
2599 case ATH12K_PEER_METADATA_V1:
2600 return le32_get_bits(peer_metadata,
2601 RX_MPDU_DESC_META_DATA_V1_PEER_ID);
2602 case ATH12K_PEER_METADATA_V1A:
2603 return le32_get_bits(peer_metadata,
2604 RX_MPDU_DESC_META_DATA_V1A_PEER_ID);
2605 case ATH12K_PEER_METADATA_V1B:
2606 return le32_get_bits(peer_metadata,
2607 RX_MPDU_DESC_META_DATA_V1B_PEER_ID);
2608 }
2609 }
2610
ath12k_dp_rx_process(struct ath12k_base * ab,int ring_id,struct napi_struct * napi,int budget)2611 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id,
2612 struct napi_struct *napi, int budget)
2613 {
2614 LIST_HEAD(rx_desc_used_list);
2615 struct ath12k_rx_desc_info *desc_info;
2616 struct ath12k_dp *dp = &ab->dp;
2617 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
2618 struct hal_reo_dest_ring *desc;
2619 int num_buffs_reaped = 0;
2620 struct sk_buff_head msdu_list;
2621 struct ath12k_skb_rxcb *rxcb;
2622 int total_msdu_reaped = 0;
2623 struct hal_srng *srng;
2624 struct sk_buff *msdu;
2625 bool done = false;
2626 int mac_id;
2627 u64 desc_va;
2628
2629 __skb_queue_head_init(&msdu_list);
2630
2631 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2632
2633 spin_lock_bh(&srng->lock);
2634
2635 try_again:
2636 ath12k_hal_srng_access_begin(ab, srng);
2637
2638 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
2639 struct rx_mpdu_desc *mpdu_info;
2640 struct rx_msdu_desc *msdu_info;
2641 enum hal_reo_dest_ring_push_reason push_reason;
2642 u32 cookie;
2643
2644 cookie = le32_get_bits(desc->buf_addr_info.info1,
2645 BUFFER_ADDR_INFO1_SW_COOKIE);
2646
2647 mac_id = le32_get_bits(desc->info0,
2648 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
2649
2650 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
2651 le32_to_cpu(desc->buf_va_lo));
2652 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
2653
2654 /* retry manual desc retrieval */
2655 if (!desc_info) {
2656 desc_info = ath12k_dp_get_rx_desc(ab, cookie);
2657 if (!desc_info) {
2658 ath12k_warn(ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n",
2659 cookie);
2660 continue;
2661 }
2662 }
2663
2664 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
2665 ath12k_warn(ab, "Check HW CC implementation");
2666
2667 msdu = desc_info->skb;
2668 desc_info->skb = NULL;
2669
2670 list_add_tail(&desc_info->list, &rx_desc_used_list);
2671
2672 rxcb = ATH12K_SKB_RXCB(msdu);
2673 dma_unmap_single(ab->dev, rxcb->paddr,
2674 msdu->len + skb_tailroom(msdu),
2675 DMA_FROM_DEVICE);
2676
2677 num_buffs_reaped++;
2678
2679 push_reason = le32_get_bits(desc->info0,
2680 HAL_REO_DEST_RING_INFO0_PUSH_REASON);
2681 if (push_reason !=
2682 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2683 dev_kfree_skb_any(msdu);
2684 ab->soc_stats.hal_reo_error[ring_id]++;
2685 continue;
2686 }
2687
2688 msdu_info = &desc->rx_msdu_info;
2689 mpdu_info = &desc->rx_mpdu_info;
2690
2691 rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) &
2692 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2693 rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) &
2694 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2695 rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) &
2696 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2697 rxcb->mac_id = mac_id;
2698 rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver,
2699 mpdu_info->peer_meta_data);
2700 rxcb->tid = le32_get_bits(mpdu_info->info0,
2701 RX_MPDU_DESC_INFO0_TID);
2702
2703 __skb_queue_tail(&msdu_list, msdu);
2704
2705 if (!rxcb->is_continuation) {
2706 total_msdu_reaped++;
2707 done = true;
2708 } else {
2709 done = false;
2710 }
2711
2712 if (total_msdu_reaped >= budget)
2713 break;
2714 }
2715
2716 /* Hw might have updated the head pointer after we cached it.
2717 * In this case, even though there are entries in the ring we'll
2718 * get rx_desc NULL. Give the read another try with updated cached
2719 * head pointer so that we can reap complete MPDU in the current
2720 * rx processing.
2721 */
2722 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) {
2723 ath12k_hal_srng_access_end(ab, srng);
2724 goto try_again;
2725 }
2726
2727 ath12k_hal_srng_access_end(ab, srng);
2728
2729 spin_unlock_bh(&srng->lock);
2730
2731 if (!total_msdu_reaped)
2732 goto exit;
2733
2734 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
2735 num_buffs_reaped);
2736
2737 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2738 ring_id);
2739
2740 exit:
2741 return total_msdu_reaped;
2742 }
2743
ath12k_dp_rx_frag_timer(struct timer_list * timer)2744 static void ath12k_dp_rx_frag_timer(struct timer_list *timer)
2745 {
2746 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
2747
2748 spin_lock_bh(&rx_tid->ab->base_lock);
2749 if (rx_tid->last_frag_no &&
2750 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
2751 spin_unlock_bh(&rx_tid->ab->base_lock);
2752 return;
2753 }
2754 ath12k_dp_rx_frags_cleanup(rx_tid, true);
2755 spin_unlock_bh(&rx_tid->ab->base_lock);
2756 }
2757
ath12k_dp_rx_peer_frag_setup(struct ath12k * ar,const u8 * peer_mac,int vdev_id)2758 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id)
2759 {
2760 struct ath12k_base *ab = ar->ab;
2761 struct crypto_shash *tfm;
2762 struct ath12k_peer *peer;
2763 struct ath12k_dp_rx_tid *rx_tid;
2764 int i;
2765
2766 tfm = crypto_alloc_shash("michael_mic", 0, 0);
2767 if (IS_ERR(tfm))
2768 return PTR_ERR(tfm);
2769
2770 spin_lock_bh(&ab->base_lock);
2771
2772 peer = ath12k_peer_find(ab, vdev_id, peer_mac);
2773 if (!peer) {
2774 spin_unlock_bh(&ab->base_lock);
2775 crypto_free_shash(tfm);
2776 ath12k_warn(ab, "failed to find the peer to set up fragment info\n");
2777 return -ENOENT;
2778 }
2779
2780 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
2781 rx_tid = &peer->rx_tid[i];
2782 rx_tid->ab = ab;
2783 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0);
2784 skb_queue_head_init(&rx_tid->rx_frags);
2785 }
2786
2787 peer->tfm_mmic = tfm;
2788 peer->dp_setup_done = true;
2789 spin_unlock_bh(&ab->base_lock);
2790
2791 return 0;
2792 }
2793
ath12k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)2794 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
2795 struct ieee80211_hdr *hdr, u8 *data,
2796 size_t data_len, u8 *mic)
2797 {
2798 SHASH_DESC_ON_STACK(desc, tfm);
2799 u8 mic_hdr[16] = {0};
2800 u8 tid = 0;
2801 int ret;
2802
2803 if (!tfm)
2804 return -EINVAL;
2805
2806 desc->tfm = tfm;
2807
2808 ret = crypto_shash_setkey(tfm, key, 8);
2809 if (ret)
2810 goto out;
2811
2812 ret = crypto_shash_init(desc);
2813 if (ret)
2814 goto out;
2815
2816 /* TKIP MIC header */
2817 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
2818 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
2819 if (ieee80211_is_data_qos(hdr->frame_control))
2820 tid = ieee80211_get_tid(hdr);
2821 mic_hdr[12] = tid;
2822
2823 ret = crypto_shash_update(desc, mic_hdr, 16);
2824 if (ret)
2825 goto out;
2826 ret = crypto_shash_update(desc, data, data_len);
2827 if (ret)
2828 goto out;
2829 ret = crypto_shash_final(desc, mic);
2830 out:
2831 shash_desc_zero(desc);
2832 return ret;
2833 }
2834
ath12k_dp_rx_h_verify_tkip_mic(struct ath12k * ar,struct ath12k_peer * peer,struct sk_buff * msdu)2835 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer,
2836 struct sk_buff *msdu)
2837 {
2838 struct ath12k_base *ab = ar->ab;
2839 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
2840 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
2841 struct ieee80211_key_conf *key_conf;
2842 struct ieee80211_hdr *hdr;
2843 u8 mic[IEEE80211_CCMP_MIC_LEN];
2844 int head_len, tail_len, ret;
2845 size_t data_len;
2846 u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2847 u8 *key, *data;
2848 u8 key_idx;
2849
2850 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
2851 return 0;
2852
2853 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
2854 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2855 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
2856 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
2857
2858 if (!is_multicast_ether_addr(hdr->addr1))
2859 key_idx = peer->ucast_keyidx;
2860 else
2861 key_idx = peer->mcast_keyidx;
2862
2863 key_conf = peer->keys[key_idx];
2864
2865 data = msdu->data + head_len;
2866 data_len = msdu->len - head_len - tail_len;
2867 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
2868
2869 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
2870 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
2871 goto mic_fail;
2872
2873 return 0;
2874
2875 mic_fail:
2876 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true;
2877 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true;
2878
2879 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
2880 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
2881 skb_pull(msdu, hal_rx_desc_sz);
2882
2883 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs);
2884 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
2885 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
2886 ieee80211_rx(ath12k_ar_to_hw(ar), msdu);
2887 return -EINVAL;
2888 }
2889
ath12k_dp_rx_h_undecap_frag(struct ath12k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)2890 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu,
2891 enum hal_encrypt_type enctype, u32 flags)
2892 {
2893 struct ieee80211_hdr *hdr;
2894 size_t hdr_len;
2895 size_t crypto_len;
2896 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2897
2898 if (!flags)
2899 return;
2900
2901 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
2902
2903 if (flags & RX_FLAG_MIC_STRIPPED)
2904 skb_trim(msdu, msdu->len -
2905 ath12k_dp_rx_crypto_mic_len(ar, enctype));
2906
2907 if (flags & RX_FLAG_ICV_STRIPPED)
2908 skb_trim(msdu, msdu->len -
2909 ath12k_dp_rx_crypto_icv_len(ar, enctype));
2910
2911 if (flags & RX_FLAG_IV_STRIPPED) {
2912 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2913 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
2914
2915 memmove(msdu->data + hal_rx_desc_sz + crypto_len,
2916 msdu->data + hal_rx_desc_sz, hdr_len);
2917 skb_pull(msdu, crypto_len);
2918 }
2919 }
2920
ath12k_dp_rx_h_defrag(struct ath12k * ar,struct ath12k_peer * peer,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)2921 static int ath12k_dp_rx_h_defrag(struct ath12k *ar,
2922 struct ath12k_peer *peer,
2923 struct ath12k_dp_rx_tid *rx_tid,
2924 struct sk_buff **defrag_skb)
2925 {
2926 struct ath12k_base *ab = ar->ab;
2927 struct hal_rx_desc *rx_desc;
2928 struct sk_buff *skb, *first_frag, *last_frag;
2929 struct ieee80211_hdr *hdr;
2930 enum hal_encrypt_type enctype;
2931 bool is_decrypted = false;
2932 int msdu_len = 0;
2933 int extra_space;
2934 u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
2935
2936 first_frag = skb_peek(&rx_tid->rx_frags);
2937 last_frag = skb_peek_tail(&rx_tid->rx_frags);
2938
2939 skb_queue_walk(&rx_tid->rx_frags, skb) {
2940 flags = 0;
2941 rx_desc = (struct hal_rx_desc *)skb->data;
2942 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
2943
2944 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc);
2945 if (enctype != HAL_ENCRYPT_TYPE_OPEN)
2946 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab,
2947 rx_desc);
2948
2949 if (is_decrypted) {
2950 if (skb != first_frag)
2951 flags |= RX_FLAG_IV_STRIPPED;
2952 if (skb != last_frag)
2953 flags |= RX_FLAG_ICV_STRIPPED |
2954 RX_FLAG_MIC_STRIPPED;
2955 }
2956
2957 /* RX fragments are always raw packets */
2958 if (skb != last_frag)
2959 skb_trim(skb, skb->len - FCS_LEN);
2960 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
2961
2962 if (skb != first_frag)
2963 skb_pull(skb, hal_rx_desc_sz +
2964 ieee80211_hdrlen(hdr->frame_control));
2965 msdu_len += skb->len;
2966 }
2967
2968 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
2969 if (extra_space > 0 &&
2970 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
2971 return -ENOMEM;
2972
2973 __skb_unlink(first_frag, &rx_tid->rx_frags);
2974 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
2975 skb_put_data(first_frag, skb->data, skb->len);
2976 dev_kfree_skb_any(skb);
2977 }
2978
2979 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
2980 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
2981 ATH12K_SKB_RXCB(first_frag)->is_frag = 1;
2982
2983 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
2984 first_frag = NULL;
2985
2986 *defrag_skb = first_frag;
2987 return 0;
2988 }
2989
ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)2990 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar,
2991 struct ath12k_dp_rx_tid *rx_tid,
2992 struct sk_buff *defrag_skb)
2993 {
2994 struct ath12k_base *ab = ar->ab;
2995 struct ath12k_dp *dp = &ab->dp;
2996 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
2997 struct hal_reo_entrance_ring *reo_ent_ring;
2998 struct hal_reo_dest_ring *reo_dest_ring;
2999 struct dp_link_desc_bank *link_desc_banks;
3000 struct hal_rx_msdu_link *msdu_link;
3001 struct hal_rx_msdu_details *msdu0;
3002 struct hal_srng *srng;
3003 dma_addr_t link_paddr, buf_paddr;
3004 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info;
3005 u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi;
3006 int ret;
3007 struct ath12k_rx_desc_info *desc_info;
3008 enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm;
3009 u8 dst_ind;
3010
3011 hal_rx_desc_sz = ab->hal.hal_desc_sz;
3012 link_desc_banks = dp->link_desc_banks;
3013 reo_dest_ring = rx_tid->dst_ring_desc;
3014
3015 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info,
3016 &link_paddr, &cookie);
3017 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK);
3018
3019 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3020 (link_paddr - link_desc_banks[desc_bank].paddr));
3021 msdu0 = &msdu_link->msdu_link[0];
3022 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0);
3023 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND);
3024
3025 memset(msdu0, 0, sizeof(*msdu0));
3026
3027 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) |
3028 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) |
3029 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) |
3030 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz,
3031 RX_MSDU_DESC_INFO0_MSDU_LENGTH) |
3032 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) |
3033 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA);
3034 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info);
3035 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info);
3036
3037 /* change msdu len in hal rx desc */
3038 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3039
3040 buf_paddr = dma_map_single(ab->dev, defrag_skb->data,
3041 defrag_skb->len + skb_tailroom(defrag_skb),
3042 DMA_TO_DEVICE);
3043 if (dma_mapping_error(ab->dev, buf_paddr))
3044 return -ENOMEM;
3045
3046 spin_lock_bh(&dp->rx_desc_lock);
3047 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list,
3048 struct ath12k_rx_desc_info,
3049 list);
3050 if (!desc_info) {
3051 spin_unlock_bh(&dp->rx_desc_lock);
3052 ath12k_warn(ab, "failed to find rx desc for reinject\n");
3053 ret = -ENOMEM;
3054 goto err_unmap_dma;
3055 }
3056
3057 desc_info->skb = defrag_skb;
3058 desc_info->in_use = true;
3059
3060 list_del(&desc_info->list);
3061 spin_unlock_bh(&dp->rx_desc_lock);
3062
3063 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr;
3064
3065 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr,
3066 desc_info->cookie,
3067 HAL_RX_BUF_RBM_SW3_BM);
3068
3069 /* Fill mpdu details into reo entrance ring */
3070 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id];
3071
3072 spin_lock_bh(&srng->lock);
3073 ath12k_hal_srng_access_begin(ab, srng);
3074
3075 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng);
3076 if (!reo_ent_ring) {
3077 ath12k_hal_srng_access_end(ab, srng);
3078 spin_unlock_bh(&srng->lock);
3079 ret = -ENOSPC;
3080 goto err_free_desc;
3081 }
3082 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3083
3084 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr,
3085 cookie,
3086 idle_link_rbm);
3087
3088 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) |
3089 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) |
3090 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) |
3091 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) |
3092 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID);
3093
3094 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info);
3095 reo_ent_ring->rx_mpdu_info.peer_meta_data =
3096 reo_dest_ring->rx_mpdu_info.peer_meta_data;
3097
3098 reo_ent_ring->queue_addr_lo = cpu_to_le32(lower_32_bits(rx_tid->paddr));
3099 queue_addr_hi = upper_32_bits(rx_tid->paddr);
3100 reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi,
3101 HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) |
3102 le32_encode_bits(dst_ind,
3103 HAL_REO_ENTR_RING_INFO0_DEST_IND);
3104
3105 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn,
3106 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM);
3107 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0,
3108 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3109 reo_ent_ring->info2 =
3110 cpu_to_le32(u32_get_bits(dest_ring_info0,
3111 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID));
3112
3113 ath12k_hal_srng_access_end(ab, srng);
3114 spin_unlock_bh(&srng->lock);
3115
3116 return 0;
3117
3118 err_free_desc:
3119 spin_lock_bh(&dp->rx_desc_lock);
3120 desc_info->in_use = false;
3121 desc_info->skb = NULL;
3122 list_add_tail(&desc_info->list, &dp->rx_desc_free_list);
3123 spin_unlock_bh(&dp->rx_desc_lock);
3124 err_unmap_dma:
3125 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3126 DMA_TO_DEVICE);
3127 return ret;
3128 }
3129
ath12k_dp_rx_h_cmp_frags(struct ath12k_base * ab,struct sk_buff * a,struct sk_buff * b)3130 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab,
3131 struct sk_buff *a, struct sk_buff *b)
3132 {
3133 int frag1, frag2;
3134
3135 frag1 = ath12k_dp_rx_h_frag_no(ab, a);
3136 frag2 = ath12k_dp_rx_h_frag_no(ab, b);
3137
3138 return frag1 - frag2;
3139 }
3140
ath12k_dp_rx_h_sort_frags(struct ath12k_base * ab,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3141 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab,
3142 struct sk_buff_head *frag_list,
3143 struct sk_buff *cur_frag)
3144 {
3145 struct sk_buff *skb;
3146 int cmp;
3147
3148 skb_queue_walk(frag_list, skb) {
3149 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag);
3150 if (cmp < 0)
3151 continue;
3152 __skb_queue_before(frag_list, skb, cur_frag);
3153 return;
3154 }
3155 __skb_queue_tail(frag_list, cur_frag);
3156 }
3157
ath12k_dp_rx_h_get_pn(struct ath12k * ar,struct sk_buff * skb)3158 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb)
3159 {
3160 struct ieee80211_hdr *hdr;
3161 u64 pn = 0;
3162 u8 *ehdr;
3163 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3164
3165 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3166 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3167
3168 pn = ehdr[0];
3169 pn |= (u64)ehdr[1] << 8;
3170 pn |= (u64)ehdr[4] << 16;
3171 pn |= (u64)ehdr[5] << 24;
3172 pn |= (u64)ehdr[6] << 32;
3173 pn |= (u64)ehdr[7] << 40;
3174
3175 return pn;
3176 }
3177
3178 static bool
ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k * ar,struct ath12k_dp_rx_tid * rx_tid)3179 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid)
3180 {
3181 struct ath12k_base *ab = ar->ab;
3182 enum hal_encrypt_type encrypt_type;
3183 struct sk_buff *first_frag, *skb;
3184 struct hal_rx_desc *desc;
3185 u64 last_pn;
3186 u64 cur_pn;
3187
3188 first_frag = skb_peek(&rx_tid->rx_frags);
3189 desc = (struct hal_rx_desc *)first_frag->data;
3190
3191 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc);
3192 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3193 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3194 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3195 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3196 return true;
3197
3198 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag);
3199 skb_queue_walk(&rx_tid->rx_frags, skb) {
3200 if (skb == first_frag)
3201 continue;
3202
3203 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb);
3204 if (cur_pn != last_pn + 1)
3205 return false;
3206 last_pn = cur_pn;
3207 }
3208 return true;
3209 }
3210
ath12k_dp_rx_frag_h_mpdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_reo_dest_ring * ring_desc)3211 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar,
3212 struct sk_buff *msdu,
3213 struct hal_reo_dest_ring *ring_desc)
3214 {
3215 struct ath12k_base *ab = ar->ab;
3216 struct hal_rx_desc *rx_desc;
3217 struct ath12k_peer *peer;
3218 struct ath12k_dp_rx_tid *rx_tid;
3219 struct sk_buff *defrag_skb = NULL;
3220 u32 peer_id;
3221 u16 seqno, frag_no;
3222 u8 tid;
3223 int ret = 0;
3224 bool more_frags;
3225
3226 rx_desc = (struct hal_rx_desc *)msdu->data;
3227 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc);
3228 tid = ath12k_dp_rx_h_tid(ab, rx_desc);
3229 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc);
3230 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu);
3231 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu);
3232
3233 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) ||
3234 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) ||
3235 tid > IEEE80211_NUM_TIDS)
3236 return -EINVAL;
3237
3238 /* received unfragmented packet in reo
3239 * exception ring, this shouldn't happen
3240 * as these packets typically come from
3241 * reo2sw srngs.
3242 */
3243 if (WARN_ON_ONCE(!frag_no && !more_frags))
3244 return -EINVAL;
3245
3246 spin_lock_bh(&ab->base_lock);
3247 peer = ath12k_peer_find_by_id(ab, peer_id);
3248 if (!peer) {
3249 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3250 peer_id);
3251 ret = -ENOENT;
3252 goto out_unlock;
3253 }
3254
3255 if (!peer->dp_setup_done) {
3256 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3257 peer->addr, peer_id);
3258 ret = -ENOENT;
3259 goto out_unlock;
3260 }
3261
3262 rx_tid = &peer->rx_tid[tid];
3263
3264 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3265 skb_queue_empty(&rx_tid->rx_frags)) {
3266 /* Flush stored fragments and start a new sequence */
3267 ath12k_dp_rx_frags_cleanup(rx_tid, true);
3268 rx_tid->cur_sn = seqno;
3269 }
3270
3271 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3272 /* Fragment already present */
3273 ret = -EINVAL;
3274 goto out_unlock;
3275 }
3276
3277 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap)))
3278 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3279 else
3280 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu);
3281
3282 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3283 if (!more_frags)
3284 rx_tid->last_frag_no = frag_no;
3285
3286 if (frag_no == 0) {
3287 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3288 sizeof(*rx_tid->dst_ring_desc),
3289 GFP_ATOMIC);
3290 if (!rx_tid->dst_ring_desc) {
3291 ret = -ENOMEM;
3292 goto out_unlock;
3293 }
3294 } else {
3295 ath12k_dp_rx_link_desc_return(ab, ring_desc,
3296 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3297 }
3298
3299 if (!rx_tid->last_frag_no ||
3300 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3301 mod_timer(&rx_tid->frag_timer, jiffies +
3302 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS);
3303 goto out_unlock;
3304 }
3305
3306 spin_unlock_bh(&ab->base_lock);
3307 del_timer_sync(&rx_tid->frag_timer);
3308 spin_lock_bh(&ab->base_lock);
3309
3310 peer = ath12k_peer_find_by_id(ab, peer_id);
3311 if (!peer)
3312 goto err_frags_cleanup;
3313
3314 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3315 goto err_frags_cleanup;
3316
3317 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3318 goto err_frags_cleanup;
3319
3320 if (!defrag_skb)
3321 goto err_frags_cleanup;
3322
3323 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3324 goto err_frags_cleanup;
3325
3326 ath12k_dp_rx_frags_cleanup(rx_tid, false);
3327 goto out_unlock;
3328
3329 err_frags_cleanup:
3330 dev_kfree_skb_any(defrag_skb);
3331 ath12k_dp_rx_frags_cleanup(rx_tid, true);
3332 out_unlock:
3333 spin_unlock_bh(&ab->base_lock);
3334 return ret;
3335 }
3336
3337 static int
ath12k_dp_process_rx_err_buf(struct ath12k * ar,struct hal_reo_dest_ring * desc,struct list_head * used_list,bool drop,u32 cookie)3338 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc,
3339 struct list_head *used_list,
3340 bool drop, u32 cookie)
3341 {
3342 struct ath12k_base *ab = ar->ab;
3343 struct sk_buff *msdu;
3344 struct ath12k_skb_rxcb *rxcb;
3345 struct hal_rx_desc *rx_desc;
3346 u16 msdu_len;
3347 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
3348 struct ath12k_rx_desc_info *desc_info;
3349 u64 desc_va;
3350
3351 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
3352 le32_to_cpu(desc->buf_va_lo));
3353 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
3354
3355 /* retry manual desc retrieval */
3356 if (!desc_info) {
3357 desc_info = ath12k_dp_get_rx_desc(ab, cookie);
3358 if (!desc_info) {
3359 ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n",
3360 cookie);
3361 return -EINVAL;
3362 }
3363 }
3364
3365 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3366 ath12k_warn(ab, " RX Exception, Check HW CC implementation");
3367
3368 msdu = desc_info->skb;
3369 desc_info->skb = NULL;
3370
3371 list_add_tail(&desc_info->list, used_list);
3372
3373 rxcb = ATH12K_SKB_RXCB(msdu);
3374 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3375 msdu->len + skb_tailroom(msdu),
3376 DMA_FROM_DEVICE);
3377
3378 if (drop) {
3379 dev_kfree_skb_any(msdu);
3380 return 0;
3381 }
3382
3383 rcu_read_lock();
3384 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3385 dev_kfree_skb_any(msdu);
3386 goto exit;
3387 }
3388
3389 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
3390 dev_kfree_skb_any(msdu);
3391 goto exit;
3392 }
3393
3394 rx_desc = (struct hal_rx_desc *)msdu->data;
3395 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc);
3396 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3397 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3398 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
3399 sizeof(*rx_desc));
3400 dev_kfree_skb_any(msdu);
3401 goto exit;
3402 }
3403
3404 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3405
3406 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) {
3407 dev_kfree_skb_any(msdu);
3408 ath12k_dp_rx_link_desc_return(ar->ab, desc,
3409 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3410 }
3411 exit:
3412 rcu_read_unlock();
3413 return 0;
3414 }
3415
ath12k_dp_rx_process_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3416 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi,
3417 int budget)
3418 {
3419 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3420 struct dp_link_desc_bank *link_desc_banks;
3421 enum hal_rx_buf_return_buf_manager rbm;
3422 struct hal_rx_msdu_link *link_desc_va;
3423 int tot_n_bufs_reaped, quota, ret, i;
3424 struct hal_reo_dest_ring *reo_desc;
3425 struct dp_rxdma_ring *rx_ring;
3426 struct dp_srng *reo_except;
3427 LIST_HEAD(rx_desc_used_list);
3428 u32 desc_bank, num_msdus;
3429 struct hal_srng *srng;
3430 struct ath12k_dp *dp;
3431 int mac_id;
3432 struct ath12k *ar;
3433 dma_addr_t paddr;
3434 bool is_frag;
3435 bool drop;
3436 int pdev_id;
3437
3438 tot_n_bufs_reaped = 0;
3439 quota = budget;
3440
3441 dp = &ab->dp;
3442 reo_except = &dp->reo_except_ring;
3443 link_desc_banks = dp->link_desc_banks;
3444
3445 srng = &ab->hal.srng_list[reo_except->ring_id];
3446
3447 spin_lock_bh(&srng->lock);
3448
3449 ath12k_hal_srng_access_begin(ab, srng);
3450
3451 while (budget &&
3452 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
3453 drop = false;
3454 ab->soc_stats.err_ring_pkts++;
3455
3456 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr,
3457 &desc_bank);
3458 if (ret) {
3459 ath12k_warn(ab, "failed to parse error reo desc %d\n",
3460 ret);
3461 continue;
3462 }
3463 link_desc_va = link_desc_banks[desc_bank].vaddr +
3464 (paddr - link_desc_banks[desc_bank].paddr);
3465 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3466 &rbm);
3467 if (rbm != dp->idle_link_rbm &&
3468 rbm != HAL_RX_BUF_RBM_SW3_BM &&
3469 rbm != ab->hw_params->hal_params->rx_buf_rbm) {
3470 ab->soc_stats.invalid_rbm++;
3471 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm);
3472 ath12k_dp_rx_link_desc_return(ab, reo_desc,
3473 HAL_WBM_REL_BM_ACT_REL_MSDU);
3474 continue;
3475 }
3476
3477 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) &
3478 RX_MPDU_DESC_INFO0_FRAG_FLAG);
3479
3480 /* Process only rx fragments with one msdu per link desc below, and drop
3481 * msdu's indicated due to error reasons.
3482 */
3483 if (!is_frag || num_msdus > 1) {
3484 drop = true;
3485 /* Return the link desc back to wbm idle list */
3486 ath12k_dp_rx_link_desc_return(ab, reo_desc,
3487 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3488 }
3489
3490 for (i = 0; i < num_msdus; i++) {
3491 mac_id = le32_get_bits(reo_desc->info0,
3492 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
3493
3494 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
3495 ar = ab->pdevs[pdev_id].ar;
3496
3497 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc,
3498 &rx_desc_used_list,
3499 drop,
3500 msdu_cookies[i]))
3501 tot_n_bufs_reaped++;
3502 }
3503
3504 if (tot_n_bufs_reaped >= quota) {
3505 tot_n_bufs_reaped = quota;
3506 goto exit;
3507 }
3508
3509 budget = quota - tot_n_bufs_reaped;
3510 }
3511
3512 exit:
3513 ath12k_hal_srng_access_end(ab, srng);
3514
3515 spin_unlock_bh(&srng->lock);
3516
3517 rx_ring = &dp->rx_refill_buf_ring;
3518
3519 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
3520 tot_n_bufs_reaped);
3521
3522 return tot_n_bufs_reaped;
3523 }
3524
ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k * ar,int msdu_len,struct sk_buff_head * msdu_list)3525 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar,
3526 int msdu_len,
3527 struct sk_buff_head *msdu_list)
3528 {
3529 struct sk_buff *skb, *tmp;
3530 struct ath12k_skb_rxcb *rxcb;
3531 int n_buffs;
3532
3533 n_buffs = DIV_ROUND_UP(msdu_len,
3534 (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz));
3535
3536 skb_queue_walk_safe(msdu_list, skb, tmp) {
3537 rxcb = ATH12K_SKB_RXCB(skb);
3538 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3539 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3540 if (!n_buffs)
3541 break;
3542 __skb_unlink(skb, msdu_list);
3543 dev_kfree_skb_any(skb);
3544 n_buffs--;
3545 }
3546 }
3547 }
3548
ath12k_dp_rx_h_null_q_desc(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3549 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu,
3550 struct ieee80211_rx_status *status,
3551 struct sk_buff_head *msdu_list)
3552 {
3553 struct ath12k_base *ab = ar->ab;
3554 u16 msdu_len;
3555 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3556 u8 l3pad_bytes;
3557 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3558 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3559
3560 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3561
3562 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3563 /* First buffer will be freed by the caller, so deduct it's length */
3564 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3565 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3566 return -EINVAL;
3567 }
3568
3569 /* Even after cleaning up the sg buffers in the msdu list with above check
3570 * any msdu received with continuation flag needs to be dropped as invalid.
3571 * This protects against some random err frame with continuation flag.
3572 */
3573 if (rxcb->is_continuation)
3574 return -EINVAL;
3575
3576 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) {
3577 ath12k_warn(ar->ab,
3578 "msdu_done bit not set in null_q_des processing\n");
3579 __skb_queue_purge(msdu_list);
3580 return -EIO;
3581 }
3582
3583 /* Handle NULL queue descriptor violations arising out a missing
3584 * REO queue for a given peer or a given TID. This typically
3585 * may happen if a packet is received on a QOS enabled TID before the
3586 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3587 * it may also happen for MC/BC frames if they are not routed to the
3588 * non-QOS TID queue, in the absence of any other default TID queue.
3589 * This error can show up both in a REO destination or WBM release ring.
3590 */
3591
3592 if (rxcb->is_frag) {
3593 skb_pull(msdu, hal_rx_desc_sz);
3594 } else {
3595 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3596
3597 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3598 return -EINVAL;
3599
3600 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3601 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3602 }
3603 ath12k_dp_rx_h_ppdu(ar, desc, status);
3604
3605 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status);
3606
3607 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc);
3608
3609 /* Please note that caller will having the access to msdu and completing
3610 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3611 */
3612
3613 return 0;
3614 }
3615
ath12k_dp_rx_h_reo_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3616 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu,
3617 struct ieee80211_rx_status *status,
3618 struct sk_buff_head *msdu_list)
3619 {
3620 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3621 bool drop = false;
3622
3623 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3624
3625 switch (rxcb->err_code) {
3626 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3627 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3628 drop = true;
3629 break;
3630 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3631 /* TODO: Do not drop PN failed packets in the driver;
3632 * instead, it is good to drop such packets in mac80211
3633 * after incrementing the replay counters.
3634 */
3635 fallthrough;
3636 default:
3637 /* TODO: Review other errors and process them to mac80211
3638 * as appropriate.
3639 */
3640 drop = true;
3641 break;
3642 }
3643
3644 return drop;
3645 }
3646
ath12k_dp_rx_h_tkip_mic_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3647 static void ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu,
3648 struct ieee80211_rx_status *status)
3649 {
3650 struct ath12k_base *ab = ar->ab;
3651 u16 msdu_len;
3652 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3653 u8 l3pad_bytes;
3654 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3655 u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
3656
3657 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc);
3658 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc);
3659
3660 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
3661 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
3662 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3663 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3664
3665 ath12k_dp_rx_h_ppdu(ar, desc, status);
3666
3667 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3668 RX_FLAG_DECRYPTED);
3669
3670 ath12k_dp_rx_h_undecap(ar, msdu, desc,
3671 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3672 }
3673
ath12k_dp_rx_h_rxdma_err(struct ath12k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3674 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu,
3675 struct ieee80211_rx_status *status)
3676 {
3677 struct ath12k_base *ab = ar->ab;
3678 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3679 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3680 bool drop = false;
3681 u32 err_bitmap;
3682
3683 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3684
3685 switch (rxcb->err_code) {
3686 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR:
3687 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3688 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
3689 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) {
3690 ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3691 break;
3692 }
3693 fallthrough;
3694 default:
3695 /* TODO: Review other rxdma error code to check if anything is
3696 * worth reporting to mac80211
3697 */
3698 drop = true;
3699 break;
3700 }
3701
3702 return drop;
3703 }
3704
ath12k_dp_rx_wbm_err(struct ath12k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3705 static void ath12k_dp_rx_wbm_err(struct ath12k *ar,
3706 struct napi_struct *napi,
3707 struct sk_buff *msdu,
3708 struct sk_buff_head *msdu_list)
3709 {
3710 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
3711 struct ieee80211_rx_status rxs = {0};
3712 bool drop = true;
3713
3714 switch (rxcb->err_rel_src) {
3715 case HAL_WBM_REL_SRC_MODULE_REO:
3716 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3717 break;
3718 case HAL_WBM_REL_SRC_MODULE_RXDMA:
3719 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3720 break;
3721 default:
3722 /* msdu will get freed */
3723 break;
3724 }
3725
3726 if (drop) {
3727 dev_kfree_skb_any(msdu);
3728 return;
3729 }
3730
3731 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
3732 }
3733
ath12k_dp_rx_process_wbm_err(struct ath12k_base * ab,struct napi_struct * napi,int budget)3734 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,
3735 struct napi_struct *napi, int budget)
3736 {
3737 LIST_HEAD(rx_desc_used_list);
3738 struct ath12k *ar;
3739 struct ath12k_dp *dp = &ab->dp;
3740 struct dp_rxdma_ring *rx_ring;
3741 struct hal_rx_wbm_rel_info err_info;
3742 struct hal_srng *srng;
3743 struct sk_buff *msdu;
3744 struct sk_buff_head msdu_list, scatter_msdu_list;
3745 struct ath12k_skb_rxcb *rxcb;
3746 void *rx_desc;
3747 u8 mac_id;
3748 int num_buffs_reaped = 0;
3749 struct ath12k_rx_desc_info *desc_info;
3750 int ret, pdev_id;
3751 struct hal_rx_desc *msdu_data;
3752
3753 __skb_queue_head_init(&msdu_list);
3754 __skb_queue_head_init(&scatter_msdu_list);
3755
3756 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
3757 rx_ring = &dp->rx_refill_buf_ring;
3758 spin_lock_bh(&srng->lock);
3759
3760 ath12k_hal_srng_access_begin(ab, srng);
3761
3762 while (budget) {
3763 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
3764 if (!rx_desc)
3765 break;
3766
3767 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
3768 if (ret) {
3769 ath12k_warn(ab,
3770 "failed to parse rx error in wbm_rel ring desc %d\n",
3771 ret);
3772 continue;
3773 }
3774
3775 desc_info = err_info.rx_desc;
3776
3777 /* retry manual desc retrieval if hw cc is not done */
3778 if (!desc_info) {
3779 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie);
3780 if (!desc_info) {
3781 ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n",
3782 err_info.cookie);
3783 continue;
3784 }
3785 }
3786
3787 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
3788 ath12k_warn(ab, "WBM RX err, Check HW CC implementation");
3789
3790 msdu = desc_info->skb;
3791 desc_info->skb = NULL;
3792
3793 list_add_tail(&desc_info->list, &rx_desc_used_list);
3794
3795 rxcb = ATH12K_SKB_RXCB(msdu);
3796 dma_unmap_single(ab->dev, rxcb->paddr,
3797 msdu->len + skb_tailroom(msdu),
3798 DMA_FROM_DEVICE);
3799
3800 num_buffs_reaped++;
3801
3802 if (!err_info.continuation)
3803 budget--;
3804
3805 if (err_info.push_reason !=
3806 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
3807 dev_kfree_skb_any(msdu);
3808 continue;
3809 }
3810
3811 msdu_data = (struct hal_rx_desc *)msdu->data;
3812 rxcb->err_rel_src = err_info.err_rel_src;
3813 rxcb->err_code = err_info.err_code;
3814 rxcb->is_first_msdu = err_info.first_msdu;
3815 rxcb->is_last_msdu = err_info.last_msdu;
3816 rxcb->is_continuation = err_info.continuation;
3817 rxcb->rx_desc = msdu_data;
3818
3819 if (err_info.continuation) {
3820 __skb_queue_tail(&scatter_msdu_list, msdu);
3821 continue;
3822 }
3823
3824 mac_id = ath12k_dp_rx_get_msdu_src_link(ab,
3825 msdu_data);
3826 if (mac_id >= MAX_RADIOS) {
3827 dev_kfree_skb_any(msdu);
3828
3829 /* In any case continuation bit is set
3830 * in the previous record, cleanup scatter_msdu_list
3831 */
3832 ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
3833 continue;
3834 }
3835
3836 if (!skb_queue_empty(&scatter_msdu_list)) {
3837 struct sk_buff *msdu;
3838
3839 skb_queue_walk(&scatter_msdu_list, msdu) {
3840 rxcb = ATH12K_SKB_RXCB(msdu);
3841 rxcb->mac_id = mac_id;
3842 }
3843
3844 skb_queue_splice_tail_init(&scatter_msdu_list,
3845 &msdu_list);
3846 }
3847
3848 rxcb = ATH12K_SKB_RXCB(msdu);
3849 rxcb->mac_id = mac_id;
3850 __skb_queue_tail(&msdu_list, msdu);
3851 }
3852
3853 /* In any case continuation bit is set in the
3854 * last record, cleanup scatter_msdu_list
3855 */
3856 ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
3857
3858 ath12k_hal_srng_access_end(ab, srng);
3859
3860 spin_unlock_bh(&srng->lock);
3861
3862 if (!num_buffs_reaped)
3863 goto done;
3864
3865 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
3866 num_buffs_reaped);
3867
3868 rcu_read_lock();
3869 while ((msdu = __skb_dequeue(&msdu_list))) {
3870 rxcb = ATH12K_SKB_RXCB(msdu);
3871 mac_id = rxcb->mac_id;
3872
3873 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
3874 ar = ab->pdevs[pdev_id].ar;
3875
3876 if (!ar || !rcu_dereference(ar->ab->pdevs_active[mac_id])) {
3877 dev_kfree_skb_any(msdu);
3878 continue;
3879 }
3880
3881 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
3882 dev_kfree_skb_any(msdu);
3883 continue;
3884 }
3885 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list);
3886 }
3887 rcu_read_unlock();
3888 done:
3889 return num_buffs_reaped;
3890 }
3891
ath12k_dp_rx_process_reo_status(struct ath12k_base * ab)3892 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab)
3893 {
3894 struct ath12k_dp *dp = &ab->dp;
3895 struct hal_tlv_64_hdr *hdr;
3896 struct hal_srng *srng;
3897 struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
3898 bool found = false;
3899 u16 tag;
3900 struct hal_reo_status reo_status;
3901
3902 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
3903
3904 memset(&reo_status, 0, sizeof(reo_status));
3905
3906 spin_lock_bh(&srng->lock);
3907
3908 ath12k_hal_srng_access_begin(ab, srng);
3909
3910 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
3911 tag = u64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG);
3912
3913 switch (tag) {
3914 case HAL_REO_GET_QUEUE_STATS_STATUS:
3915 ath12k_hal_reo_status_queue_stats(ab, hdr,
3916 &reo_status);
3917 break;
3918 case HAL_REO_FLUSH_QUEUE_STATUS:
3919 ath12k_hal_reo_flush_queue_status(ab, hdr,
3920 &reo_status);
3921 break;
3922 case HAL_REO_FLUSH_CACHE_STATUS:
3923 ath12k_hal_reo_flush_cache_status(ab, hdr,
3924 &reo_status);
3925 break;
3926 case HAL_REO_UNBLOCK_CACHE_STATUS:
3927 ath12k_hal_reo_unblk_cache_status(ab, hdr,
3928 &reo_status);
3929 break;
3930 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
3931 ath12k_hal_reo_flush_timeout_list_status(ab, hdr,
3932 &reo_status);
3933 break;
3934 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
3935 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr,
3936 &reo_status);
3937 break;
3938 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
3939 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr,
3940 &reo_status);
3941 break;
3942 default:
3943 ath12k_warn(ab, "Unknown reo status type %d\n", tag);
3944 continue;
3945 }
3946
3947 spin_lock_bh(&dp->reo_cmd_lock);
3948 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
3949 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
3950 found = true;
3951 list_del(&cmd->list);
3952 break;
3953 }
3954 }
3955 spin_unlock_bh(&dp->reo_cmd_lock);
3956
3957 if (found) {
3958 cmd->handler(dp, (void *)&cmd->data,
3959 reo_status.uniform_hdr.cmd_status);
3960 kfree(cmd);
3961 }
3962
3963 found = false;
3964 }
3965
3966 ath12k_hal_srng_access_end(ab, srng);
3967
3968 spin_unlock_bh(&srng->lock);
3969 }
3970
ath12k_dp_rx_free(struct ath12k_base * ab)3971 void ath12k_dp_rx_free(struct ath12k_base *ab)
3972 {
3973 struct ath12k_dp *dp = &ab->dp;
3974 int i;
3975
3976 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
3977
3978 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
3979 if (ab->hw_params->rx_mac_buf_ring)
3980 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
3981 }
3982
3983 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++)
3984 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
3985
3986 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
3987
3988 ath12k_dp_rxdma_buf_free(ab);
3989 }
3990
ath12k_dp_rx_pdev_free(struct ath12k_base * ab,int mac_id)3991 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id)
3992 {
3993 struct ath12k *ar = ab->pdevs[mac_id].ar;
3994
3995 ath12k_dp_rx_pdev_srng_free(ar);
3996 }
3997
ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base * ab)3998 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab)
3999 {
4000 struct ath12k_dp *dp = &ab->dp;
4001 struct htt_rx_ring_tlv_filter tlv_filter = {0};
4002 u32 ring_id;
4003 int ret;
4004 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4005
4006 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4007
4008 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4009 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4010 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4011 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4012 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4013 tlv_filter.offset_valid = true;
4014 tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4015
4016 tlv_filter.rx_mpdu_start_offset =
4017 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4018 tlv_filter.rx_msdu_end_offset =
4019 ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4020
4021 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
4022 tlv_filter.rx_mpdu_start_wmask =
4023 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start();
4024 tlv_filter.rx_msdu_end_wmask =
4025 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end();
4026 ath12k_dbg(ab, ATH12K_DBG_DATA,
4027 "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n",
4028 tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask);
4029 }
4030
4031 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0,
4032 HAL_RXDMA_BUF,
4033 DP_RXDMA_REFILL_RING_SIZE,
4034 &tlv_filter);
4035
4036 return ret;
4037 }
4038
ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base * ab)4039 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab)
4040 {
4041 struct ath12k_dp *dp = &ab->dp;
4042 struct htt_rx_ring_tlv_filter tlv_filter = {0};
4043 u32 ring_id;
4044 int ret = 0;
4045 u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
4046 int i;
4047
4048 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4049
4050 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
4051 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
4052 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
4053 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
4054 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
4055 tlv_filter.offset_valid = true;
4056 tlv_filter.rx_packet_offset = hal_rx_desc_sz;
4057
4058 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv);
4059
4060 tlv_filter.rx_mpdu_start_offset =
4061 ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
4062 tlv_filter.rx_msdu_end_offset =
4063 ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
4064
4065 /* TODO: Selectively subscribe to required qwords within msdu_end
4066 * and mpdu_start and setup the mask in below msg
4067 * and modify the rx_desc struct
4068 */
4069
4070 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4071 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4072 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i,
4073 HAL_RXDMA_BUF,
4074 DP_RXDMA_REFILL_RING_SIZE,
4075 &tlv_filter);
4076 }
4077
4078 return ret;
4079 }
4080
ath12k_dp_rx_htt_setup(struct ath12k_base * ab)4081 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab)
4082 {
4083 struct ath12k_dp *dp = &ab->dp;
4084 u32 ring_id;
4085 int i, ret;
4086
4087 /* TODO: Need to verify the HTT setup for QCN9224 */
4088 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4089 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF);
4090 if (ret) {
4091 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4092 ret);
4093 return ret;
4094 }
4095
4096 if (ab->hw_params->rx_mac_buf_ring) {
4097 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4098 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4099 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4100 i, HAL_RXDMA_BUF);
4101 if (ret) {
4102 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4103 i, ret);
4104 return ret;
4105 }
4106 }
4107 }
4108
4109 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4110 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4111 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4112 i, HAL_RXDMA_DST);
4113 if (ret) {
4114 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4115 i, ret);
4116 return ret;
4117 }
4118 }
4119
4120 if (ab->hw_params->rxdma1_enable) {
4121 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4122 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4123 0, HAL_RXDMA_MONITOR_BUF);
4124 if (ret) {
4125 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4126 ret);
4127 return ret;
4128 }
4129 }
4130
4131 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab);
4132 if (ret) {
4133 ath12k_warn(ab, "failed to setup rxdma ring selection config\n");
4134 return ret;
4135 }
4136
4137 return 0;
4138 }
4139
ath12k_dp_rx_alloc(struct ath12k_base * ab)4140 int ath12k_dp_rx_alloc(struct ath12k_base *ab)
4141 {
4142 struct ath12k_dp *dp = &ab->dp;
4143 int i, ret;
4144
4145 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr);
4146 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock);
4147
4148 ret = ath12k_dp_srng_setup(ab,
4149 &dp->rx_refill_buf_ring.refill_buf_ring,
4150 HAL_RXDMA_BUF, 0, 0,
4151 DP_RXDMA_BUF_RING_SIZE);
4152 if (ret) {
4153 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n");
4154 return ret;
4155 }
4156
4157 if (ab->hw_params->rx_mac_buf_ring) {
4158 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4159 ret = ath12k_dp_srng_setup(ab,
4160 &dp->rx_mac_buf_ring[i],
4161 HAL_RXDMA_BUF, 1,
4162 i, DP_RX_MAC_BUF_RING_SIZE);
4163 if (ret) {
4164 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n",
4165 i);
4166 return ret;
4167 }
4168 }
4169 }
4170
4171 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
4172 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i],
4173 HAL_RXDMA_DST, 0, i,
4174 DP_RXDMA_ERR_DST_RING_SIZE);
4175 if (ret) {
4176 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i);
4177 return ret;
4178 }
4179 }
4180
4181 if (ab->hw_params->rxdma1_enable) {
4182 ret = ath12k_dp_srng_setup(ab,
4183 &dp->rxdma_mon_buf_ring.refill_buf_ring,
4184 HAL_RXDMA_MONITOR_BUF, 0, 0,
4185 DP_RXDMA_MONITOR_BUF_RING_SIZE);
4186 if (ret) {
4187 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n");
4188 return ret;
4189 }
4190 }
4191
4192 ret = ath12k_dp_rxdma_buf_setup(ab);
4193 if (ret) {
4194 ath12k_warn(ab, "failed to setup rxdma ring\n");
4195 return ret;
4196 }
4197
4198 return 0;
4199 }
4200
ath12k_dp_rx_pdev_alloc(struct ath12k_base * ab,int mac_id)4201 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id)
4202 {
4203 struct ath12k *ar = ab->pdevs[mac_id].ar;
4204 struct ath12k_pdev_dp *dp = &ar->dp;
4205 u32 ring_id;
4206 int i;
4207 int ret;
4208
4209 if (!ab->hw_params->rxdma1_enable)
4210 goto out;
4211
4212 ret = ath12k_dp_rx_pdev_srng_alloc(ar);
4213 if (ret) {
4214 ath12k_warn(ab, "failed to setup rx srngs\n");
4215 return ret;
4216 }
4217
4218 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
4219 ring_id = dp->rxdma_mon_dst_ring[i].ring_id;
4220 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
4221 mac_id + i,
4222 HAL_RXDMA_MONITOR_DST);
4223 if (ret) {
4224 ath12k_warn(ab,
4225 "failed to configure rxdma_mon_dst_ring %d %d\n",
4226 i, ret);
4227 return ret;
4228 }
4229 }
4230 out:
4231 return 0;
4232 }
4233
ath12k_dp_rx_pdev_mon_status_attach(struct ath12k * ar)4234 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar)
4235 {
4236 struct ath12k_pdev_dp *dp = &ar->dp;
4237 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data;
4238
4239 skb_queue_head_init(&pmon->rx_status_q);
4240
4241 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4242
4243 memset(&pmon->rx_mon_stats, 0,
4244 sizeof(pmon->rx_mon_stats));
4245 return 0;
4246 }
4247
ath12k_dp_rx_pdev_mon_attach(struct ath12k * ar)4248 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar)
4249 {
4250 struct ath12k_pdev_dp *dp = &ar->dp;
4251 struct ath12k_mon_data *pmon = &dp->mon_data;
4252 int ret = 0;
4253
4254 ret = ath12k_dp_rx_pdev_mon_status_attach(ar);
4255 if (ret) {
4256 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed");
4257 return ret;
4258 }
4259
4260 /* if rxdma1_enable is false, no need to setup
4261 * rxdma_mon_desc_ring.
4262 */
4263 if (!ar->ab->hw_params->rxdma1_enable)
4264 return 0;
4265
4266 pmon->mon_last_linkdesc_paddr = 0;
4267 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
4268 spin_lock_init(&pmon->mon_lock);
4269
4270 return 0;
4271 }
4272