1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "hif.h" 10 #include "hal.h" 11 #include "debug.h" 12 #include "peer.h" 13 #include "dp_cmn.h" 14 15 enum ath12k_dp_desc_type { 16 ATH12K_DP_TX_DESC, 17 ATH12K_DP_RX_DESC, 18 }; 19 20 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr) 21 { 22 struct ath12k_base *ab = ar->ab; 23 struct ath12k_dp_link_peer *peer; 24 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 25 26 /* TODO: Any other peer specific DP cleanup */ 27 28 spin_lock_bh(&dp->dp_lock); 29 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, addr); 30 if (!peer || !peer->dp_peer) { 31 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n", 32 addr, vdev_id); 33 spin_unlock_bh(&dp->dp_lock); 34 return; 35 } 36 37 if (!peer->primary_link) { 38 spin_unlock_bh(&dp->dp_lock); 39 return; 40 } 41 42 ath12k_dp_rx_peer_tid_cleanup(ar, peer); 43 peer->dp_peer->dp_setup_done = false; 44 spin_unlock_bh(&dp->dp_lock); 45 } 46 47 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr) 48 { 49 struct ath12k_base *ab = ar->ab; 50 struct ath12k_dp_link_peer *peer; 51 u32 reo_dest; 52 int ret = 0, tid; 53 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 54 55 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */ 56 reo_dest = ar->dp.mac_id + 1; 57 ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id, 58 WMI_PEER_SET_DEFAULT_ROUTING, 59 DP_RX_HASH_ENABLE | (reo_dest << 1)); 60 61 if (ret) { 62 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n", 63 ret, addr, vdev_id); 64 return ret; 65 } 66 67 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 68 ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0, 69 HAL_PN_TYPE_NONE); 70 if (ret) { 71 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n", 72 tid, ret); 73 goto peer_clean; 74 } 75 } 76 77 ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id); 78 if (ret) { 79 ath12k_warn(ab, "failed to setup rx defrag context\n"); 80 goto peer_clean; 81 } 82 83 /* TODO: Setup other peer specific resource used in data path */ 84 85 return 0; 86 87 peer_clean: 88 spin_lock_bh(&dp->dp_lock); 89 90 peer = ath12k_dp_link_peer_find_by_vdev_and_addr(dp, vdev_id, addr); 91 if (!peer) { 92 ath12k_warn(ab, "failed to find the peer to del rx tid\n"); 93 spin_unlock_bh(&dp->dp_lock); 94 return -ENOENT; 95 } 96 97 for (tid--; tid >= 0; tid--) 98 ath12k_dp_arch_rx_peer_tid_delete(dp, peer, tid); 99 100 spin_unlock_bh(&dp->dp_lock); 101 102 return ret; 103 } 104 105 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring) 106 { 107 if (!ring->vaddr_unaligned) 108 return; 109 110 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned, 111 ring->paddr_unaligned); 112 113 ring->vaddr_unaligned = NULL; 114 } 115 116 static int ath12k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask) 117 { 118 int ext_group_num; 119 u8 mask = 1 << ring_num; 120 121 for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX; 122 ext_group_num++) { 123 if (mask & grp_mask[ext_group_num]) 124 return ext_group_num; 125 } 126 127 return -ENOENT; 128 } 129 130 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab, 131 enum hal_ring_type type, int ring_num) 132 { 133 const struct ath12k_hal_tcl_to_wbm_rbm_map *map; 134 const u8 *grp_mask; 135 int i; 136 137 switch (type) { 138 case HAL_WBM2SW_RELEASE: 139 if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) { 140 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0]; 141 ring_num = 0; 142 } else { 143 map = ab->hal.tcl_to_wbm_rbm_map; 144 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 145 if (ring_num == map[i].wbm_ring_num) { 146 ring_num = i; 147 break; 148 } 149 } 150 151 grp_mask = &ab->hw_params->ring_mask->tx[0]; 152 } 153 break; 154 case HAL_REO_EXCEPTION: 155 grp_mask = &ab->hw_params->ring_mask->rx_err[0]; 156 break; 157 case HAL_REO_DST: 158 grp_mask = &ab->hw_params->ring_mask->rx[0]; 159 break; 160 case HAL_REO_STATUS: 161 grp_mask = &ab->hw_params->ring_mask->reo_status[0]; 162 break; 163 case HAL_RXDMA_MONITOR_STATUS: 164 grp_mask = &ab->hw_params->ring_mask->rx_mon_status[0]; 165 break; 166 case HAL_RXDMA_MONITOR_DST: 167 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0]; 168 break; 169 case HAL_TX_MONITOR_DST: 170 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0]; 171 break; 172 case HAL_RXDMA_BUF: 173 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0]; 174 break; 175 case HAL_RXDMA_MONITOR_BUF: 176 case HAL_TCL_DATA: 177 case HAL_TCL_CMD: 178 case HAL_REO_CMD: 179 case HAL_SW2WBM_RELEASE: 180 case HAL_WBM_IDLE_LINK: 181 case HAL_TCL_STATUS: 182 case HAL_REO_REINJECT: 183 case HAL_CE_SRC: 184 case HAL_CE_DST: 185 case HAL_CE_DST_STATUS: 186 default: 187 return -ENOENT; 188 } 189 190 return ath12k_dp_srng_find_ring_in_mask(ring_num, grp_mask); 191 } 192 193 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab, 194 struct hal_srng_params *ring_params, 195 enum hal_ring_type type, int ring_num) 196 { 197 int msi_group_number, msi_data_count; 198 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi; 199 int ret; 200 201 ret = ath12k_hif_get_user_msi_vector(ab, "DP", 202 &msi_data_count, &msi_data_start, 203 &msi_irq_start); 204 if (ret) 205 return; 206 207 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type, 208 ring_num); 209 if (msi_group_number < 0) { 210 ath12k_dbg(ab, ATH12K_DBG_PCI, 211 "ring not part of an ext_group; ring_type: %d,ring_num %d", 212 type, ring_num); 213 ring_params->msi_addr = 0; 214 ring_params->msi_data = 0; 215 return; 216 } 217 218 if (msi_group_number > msi_data_count) { 219 ath12k_dbg(ab, ATH12K_DBG_PCI, 220 "multiple msi_groups share one msi, msi_group_num %d", 221 msi_group_number); 222 } 223 224 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi); 225 226 ring_params->msi_addr = addr_lo; 227 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); 228 ring_params->msi_data = (msi_group_number % msi_data_count) 229 + msi_data_start; 230 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; 231 } 232 233 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 234 enum hal_ring_type type, int ring_num, 235 int mac_id, int num_entries) 236 { 237 struct hal_srng_params params = {}; 238 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type); 239 int max_entries = ath12k_hal_srng_get_max_entries(ab, type); 240 int ret; 241 242 if (max_entries < 0 || entry_sz < 0) 243 return -EINVAL; 244 245 if (num_entries > max_entries) 246 num_entries = max_entries; 247 248 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1; 249 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size, 250 &ring->paddr_unaligned, 251 GFP_KERNEL); 252 if (!ring->vaddr_unaligned) 253 return -ENOMEM; 254 255 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN); 256 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr - 257 (unsigned long)ring->vaddr_unaligned); 258 259 params.ring_base_vaddr = ring->vaddr; 260 params.ring_base_paddr = ring->paddr; 261 params.num_entries = num_entries; 262 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id); 263 264 switch (type) { 265 case HAL_REO_DST: 266 params.intr_batch_cntr_thres_entries = 267 HAL_SRNG_INT_BATCH_THRESHOLD_RX; 268 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 269 break; 270 case HAL_RXDMA_BUF: 271 case HAL_RXDMA_MONITOR_BUF: 272 params.low_threshold = num_entries >> 3; 273 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 274 params.intr_batch_cntr_thres_entries = 0; 275 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 276 break; 277 case HAL_RXDMA_MONITOR_STATUS: 278 params.low_threshold = num_entries >> 3; 279 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 280 params.intr_batch_cntr_thres_entries = 1; 281 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 282 break; 283 case HAL_TX_MONITOR_DST: 284 params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3; 285 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 286 params.intr_batch_cntr_thres_entries = 0; 287 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 288 break; 289 case HAL_WBM2SW_RELEASE: 290 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) { 291 params.intr_batch_cntr_thres_entries = 292 HAL_SRNG_INT_BATCH_THRESHOLD_TX; 293 params.intr_timer_thres_us = 294 HAL_SRNG_INT_TIMER_THRESHOLD_TX; 295 break; 296 } 297 /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */ 298 fallthrough; 299 case HAL_REO_EXCEPTION: 300 case HAL_REO_REINJECT: 301 case HAL_REO_CMD: 302 case HAL_REO_STATUS: 303 case HAL_TCL_DATA: 304 case HAL_TCL_CMD: 305 case HAL_TCL_STATUS: 306 case HAL_WBM_IDLE_LINK: 307 case HAL_SW2WBM_RELEASE: 308 case HAL_RXDMA_DST: 309 case HAL_RXDMA_MONITOR_DST: 310 case HAL_RXDMA_MONITOR_DESC: 311 params.intr_batch_cntr_thres_entries = 312 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER; 313 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER; 314 break; 315 case HAL_RXDMA_DIR_BUF: 316 break; 317 default: 318 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type); 319 return -EINVAL; 320 } 321 322 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms); 323 if (ret < 0) { 324 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n", 325 ret, ring_num); 326 return ret; 327 } 328 329 ring->ring_id = ret; 330 331 return 0; 332 } 333 334 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, 335 struct ath12k_link_vif *arvif, 336 struct ath12k_dp *dp) 337 { 338 int bank_id = DP_INVALID_BANK_ID; 339 int i; 340 u32 bank_config; 341 bool configure_register = false; 342 343 /* convert vdev params into hal_tx_bank_config */ 344 bank_config = ath12k_dp_arch_tx_get_vdev_bank_config(dp, arvif); 345 346 spin_lock_bh(&dp->tx_bank_lock); 347 /* TODO: implement using idr kernel framework*/ 348 for (i = 0; i < dp->num_bank_profiles; i++) { 349 if (dp->bank_profiles[i].is_configured && 350 (dp->bank_profiles[i].bank_config ^ bank_config) == 0) { 351 bank_id = i; 352 goto inc_ref_and_return; 353 } 354 if (!dp->bank_profiles[i].is_configured || 355 !dp->bank_profiles[i].num_users) { 356 bank_id = i; 357 goto configure_and_return; 358 } 359 } 360 361 if (bank_id == DP_INVALID_BANK_ID) { 362 spin_unlock_bh(&dp->tx_bank_lock); 363 ath12k_err(ab, "unable to find TX bank!"); 364 return bank_id; 365 } 366 367 configure_and_return: 368 dp->bank_profiles[bank_id].is_configured = true; 369 dp->bank_profiles[bank_id].bank_config = bank_config; 370 configure_register = true; 371 inc_ref_and_return: 372 dp->bank_profiles[bank_id].num_users++; 373 spin_unlock_bh(&dp->tx_bank_lock); 374 375 if (configure_register) 376 ath12k_hal_tx_configure_bank_register(ab, 377 bank_config, bank_id); 378 379 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u", 380 bank_id, bank_config, dp->bank_profiles[bank_id].bank_config, 381 dp->bank_profiles[bank_id].num_users); 382 383 return bank_id; 384 } 385 386 void ath12k_dp_tx_put_bank_profile(struct ath12k_dp *dp, u8 bank_id) 387 { 388 spin_lock_bh(&dp->tx_bank_lock); 389 dp->bank_profiles[bank_id].num_users--; 390 spin_unlock_bh(&dp->tx_bank_lock); 391 } 392 393 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab) 394 { 395 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 396 397 kfree(dp->bank_profiles); 398 dp->bank_profiles = NULL; 399 } 400 401 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab) 402 { 403 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 404 u32 num_tcl_banks = ab->hw_params->num_tcl_banks; 405 int i; 406 407 dp->num_bank_profiles = num_tcl_banks; 408 dp->bank_profiles = kmalloc_objs(struct ath12k_dp_tx_bank_profile, 409 num_tcl_banks); 410 if (!dp->bank_profiles) 411 return -ENOMEM; 412 413 spin_lock_init(&dp->tx_bank_lock); 414 415 for (i = 0; i < num_tcl_banks; i++) { 416 dp->bank_profiles[i].is_configured = false; 417 dp->bank_profiles[i].num_users = 0; 418 } 419 420 return 0; 421 } 422 423 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab) 424 { 425 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 426 int i; 427 428 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring); 429 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring); 430 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring); 431 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring); 432 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring); 433 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 434 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring); 435 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring); 436 } 437 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring); 438 } 439 440 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab) 441 { 442 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 443 const struct ath12k_hal_tcl_to_wbm_rbm_map *map; 444 struct hal_srng *srng; 445 int i, ret, tx_comp_ring_num; 446 u32 ring_hash_map; 447 448 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring, 449 HAL_SW2WBM_RELEASE, 0, 0, 450 DP_WBM_RELEASE_RING_SIZE); 451 if (ret) { 452 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n", 453 ret); 454 goto err; 455 } 456 457 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 458 map = ab->hal.tcl_to_wbm_rbm_map; 459 tx_comp_ring_num = map[i].wbm_ring_num; 460 461 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring, 462 HAL_TCL_DATA, i, 0, 463 DP_TCL_DATA_RING_SIZE); 464 if (ret) { 465 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n", 466 i, ret); 467 goto err; 468 } 469 470 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring, 471 HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0, 472 DP_TX_COMP_RING_SIZE(ab)); 473 if (ret) { 474 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n", 475 tx_comp_ring_num, ret); 476 goto err; 477 } 478 } 479 480 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT, 481 0, 0, DP_REO_REINJECT_RING_SIZE); 482 if (ret) { 483 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n", 484 ret); 485 goto err; 486 } 487 488 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE, 489 HAL_WBM2SW_REL_ERR_RING_NUM, 0, 490 DP_RX_RELEASE_RING_SIZE); 491 if (ret) { 492 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret); 493 goto err; 494 } 495 496 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION, 497 0, 0, DP_REO_EXCEPTION_RING_SIZE); 498 if (ret) { 499 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n", 500 ret); 501 goto err; 502 } 503 504 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD, 505 0, 0, DP_REO_CMD_RING_SIZE); 506 if (ret) { 507 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret); 508 goto err; 509 } 510 511 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 512 ath12k_hal_reo_init_cmd_ring(ab, srng); 513 514 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS, 515 0, 0, DP_REO_STATUS_RING_SIZE); 516 if (ret) { 517 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret); 518 goto err; 519 } 520 521 /* When hash based routing of rx packet is enabled, 32 entries to map 522 * the hash values to the ring will be configured. Each hash entry uses 523 * four bits to map to a particular ring. The ring mapping will be 524 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:SW5 525 * 8:SW6, 9:SW7, 10:SW8, 11:Not used. 526 */ 527 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 | 528 HAL_HASH_ROUTING_RING_SW2 << 4 | 529 HAL_HASH_ROUTING_RING_SW3 << 8 | 530 HAL_HASH_ROUTING_RING_SW4 << 12 | 531 HAL_HASH_ROUTING_RING_SW1 << 16 | 532 HAL_HASH_ROUTING_RING_SW2 << 20 | 533 HAL_HASH_ROUTING_RING_SW3 << 24 | 534 HAL_HASH_ROUTING_RING_SW4 << 28; 535 536 ath12k_hal_reo_hw_setup(ab, ring_hash_map); 537 538 return 0; 539 540 err: 541 ath12k_dp_srng_common_cleanup(ab); 542 543 return ret; 544 } 545 546 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab) 547 { 548 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 549 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 550 int i; 551 552 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) { 553 if (!slist[i].vaddr) 554 continue; 555 556 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 557 slist[i].vaddr, slist[i].paddr); 558 slist[i].vaddr = NULL; 559 } 560 } 561 562 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab, 563 int size, 564 u32 n_link_desc_bank, 565 u32 n_link_desc, 566 u32 last_bank_sz) 567 { 568 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 569 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks; 570 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 571 u32 n_entries_per_buf; 572 int num_scatter_buf, scatter_idx; 573 struct hal_wbm_link_desc *scatter_buf; 574 int align_bytes, n_entries; 575 dma_addr_t paddr; 576 int rem_entries; 577 int i; 578 int ret = 0; 579 u32 end_offset, cookie; 580 enum hal_rx_buf_return_buf_manager rbm = dp->idle_link_rbm; 581 582 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 583 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK); 584 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE); 585 586 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX) 587 return -EINVAL; 588 589 for (i = 0; i < num_scatter_buf; i++) { 590 slist[i].vaddr = dma_alloc_coherent(ab->dev, 591 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 592 &slist[i].paddr, GFP_KERNEL); 593 if (!slist[i].vaddr) { 594 ret = -ENOMEM; 595 goto err; 596 } 597 } 598 599 scatter_idx = 0; 600 scatter_buf = slist[scatter_idx].vaddr; 601 rem_entries = n_entries_per_buf; 602 603 for (i = 0; i < n_link_desc_bank; i++) { 604 align_bytes = link_desc_banks[i].vaddr - 605 link_desc_banks[i].vaddr_unaligned; 606 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) / 607 HAL_LINK_DESC_SIZE; 608 paddr = link_desc_banks[i].paddr; 609 while (n_entries) { 610 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); 611 ath12k_hal_set_link_desc_addr(dp->hal, scatter_buf, cookie, 612 paddr, rbm); 613 n_entries--; 614 paddr += HAL_LINK_DESC_SIZE; 615 if (rem_entries) { 616 rem_entries--; 617 scatter_buf++; 618 continue; 619 } 620 621 rem_entries = n_entries_per_buf; 622 scatter_idx++; 623 scatter_buf = slist[scatter_idx].vaddr; 624 } 625 } 626 627 end_offset = (scatter_buf - slist[scatter_idx].vaddr) * 628 sizeof(struct hal_wbm_link_desc); 629 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf, 630 n_link_desc, end_offset); 631 632 return 0; 633 634 err: 635 ath12k_dp_scatter_idle_link_desc_cleanup(ab); 636 637 return ret; 638 } 639 640 static void 641 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab, 642 struct dp_link_desc_bank *link_desc_banks) 643 { 644 int i; 645 646 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) { 647 if (link_desc_banks[i].vaddr_unaligned) { 648 dma_free_coherent(ab->dev, 649 link_desc_banks[i].size, 650 link_desc_banks[i].vaddr_unaligned, 651 link_desc_banks[i].paddr_unaligned); 652 link_desc_banks[i].vaddr_unaligned = NULL; 653 } 654 } 655 } 656 657 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab, 658 struct dp_link_desc_bank *desc_bank, 659 int n_link_desc_bank, 660 int last_bank_sz) 661 { 662 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 663 int i; 664 int ret = 0; 665 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH; 666 667 for (i = 0; i < n_link_desc_bank; i++) { 668 if (i == (n_link_desc_bank - 1) && last_bank_sz) 669 desc_sz = last_bank_sz; 670 671 desc_bank[i].vaddr_unaligned = 672 dma_alloc_coherent(ab->dev, desc_sz, 673 &desc_bank[i].paddr_unaligned, 674 GFP_KERNEL); 675 if (!desc_bank[i].vaddr_unaligned) { 676 ret = -ENOMEM; 677 goto err; 678 } 679 680 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned, 681 HAL_LINK_DESC_ALIGN); 682 desc_bank[i].paddr = desc_bank[i].paddr_unaligned + 683 ((unsigned long)desc_bank[i].vaddr - 684 (unsigned long)desc_bank[i].vaddr_unaligned); 685 desc_bank[i].size = desc_sz; 686 } 687 688 return 0; 689 690 err: 691 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks); 692 693 return ret; 694 } 695 696 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 697 struct dp_link_desc_bank *desc_bank, 698 u32 ring_type, struct dp_srng *ring) 699 { 700 ath12k_dp_link_desc_bank_free(ab, desc_bank); 701 702 if (ring_type != HAL_RXDMA_MONITOR_DESC) { 703 ath12k_dp_srng_cleanup(ab, ring); 704 ath12k_dp_scatter_idle_link_desc_cleanup(ab); 705 } 706 } 707 708 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc) 709 { 710 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 711 u32 n_mpdu_link_desc, n_mpdu_queue_desc; 712 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc; 713 int ret = 0; 714 715 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) / 716 HAL_NUM_MPDUS_PER_LINK_DESC; 717 718 n_mpdu_queue_desc = n_mpdu_link_desc / 719 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC; 720 721 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID * 722 DP_AVG_MSDUS_PER_FLOW) / 723 HAL_NUM_TX_MSDUS_PER_LINK_DESC; 724 725 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX * 726 DP_AVG_MSDUS_PER_MPDU) / 727 HAL_NUM_RX_MSDUS_PER_LINK_DESC; 728 729 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc + 730 n_tx_msdu_link_desc + n_rx_msdu_link_desc; 731 732 if (*n_link_desc & (*n_link_desc - 1)) 733 *n_link_desc = 1 << fls(*n_link_desc); 734 735 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring, 736 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc); 737 if (ret) { 738 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 739 return ret; 740 } 741 return ret; 742 } 743 744 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 745 struct dp_link_desc_bank *link_desc_banks, 746 u32 ring_type, struct hal_srng *srng, 747 u32 n_link_desc) 748 { 749 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 750 u32 tot_mem_sz; 751 u32 n_link_desc_bank, last_bank_sz; 752 u32 entry_sz, align_bytes, n_entries; 753 struct hal_wbm_link_desc *desc; 754 u32 paddr; 755 int i, ret; 756 u32 cookie; 757 enum hal_rx_buf_return_buf_manager rbm = dp->idle_link_rbm; 758 759 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE; 760 tot_mem_sz += HAL_LINK_DESC_ALIGN; 761 762 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) { 763 n_link_desc_bank = 1; 764 last_bank_sz = tot_mem_sz; 765 } else { 766 n_link_desc_bank = tot_mem_sz / 767 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 768 HAL_LINK_DESC_ALIGN); 769 last_bank_sz = tot_mem_sz % 770 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 771 HAL_LINK_DESC_ALIGN); 772 773 if (last_bank_sz) 774 n_link_desc_bank += 1; 775 } 776 777 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX) 778 return -EINVAL; 779 780 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks, 781 n_link_desc_bank, last_bank_sz); 782 if (ret) 783 return ret; 784 785 /* Setup link desc idle list for HW internal usage */ 786 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type); 787 tot_mem_sz = entry_sz * n_link_desc; 788 789 /* Setup scatter desc list when the total memory requirement is more */ 790 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH && 791 ring_type != HAL_RXDMA_MONITOR_DESC) { 792 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz, 793 n_link_desc_bank, 794 n_link_desc, 795 last_bank_sz); 796 if (ret) { 797 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n", 798 ret); 799 goto fail_desc_bank_free; 800 } 801 802 return 0; 803 } 804 805 spin_lock_bh(&srng->lock); 806 807 ath12k_hal_srng_access_begin(ab, srng); 808 809 for (i = 0; i < n_link_desc_bank; i++) { 810 align_bytes = link_desc_banks[i].vaddr - 811 link_desc_banks[i].vaddr_unaligned; 812 n_entries = (link_desc_banks[i].size - align_bytes) / 813 HAL_LINK_DESC_SIZE; 814 paddr = link_desc_banks[i].paddr; 815 while (n_entries && 816 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) { 817 cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); 818 ath12k_hal_set_link_desc_addr(dp->hal, desc, cookie, paddr, 819 rbm); 820 n_entries--; 821 paddr += HAL_LINK_DESC_SIZE; 822 } 823 } 824 825 ath12k_hal_srng_access_end(ab, srng); 826 827 spin_unlock_bh(&srng->lock); 828 829 return 0; 830 831 fail_desc_bank_free: 832 ath12k_dp_link_desc_bank_free(ab, link_desc_banks); 833 834 return ret; 835 } 836 837 void ath12k_dp_pdev_free(struct ath12k_base *ab) 838 { 839 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 840 struct ath12k *ar; 841 int i; 842 843 for (i = 0; i < ab->num_radios; i++) { 844 ar = ab->pdevs[i].ar; 845 rcu_assign_pointer(dp->dp_pdevs[ar->pdev_idx], NULL); 846 } 847 848 synchronize_rcu(); 849 850 for (i = 0; i < ab->num_radios; i++) 851 ath12k_dp_rx_pdev_free(ab, i); 852 } 853 854 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar) 855 { 856 struct ath12k_pdev_dp *dp = &ar->dp; 857 858 dp->mac_id = ar->pdev_idx; 859 atomic_set(&dp->num_tx_pending, 0); 860 init_waitqueue_head(&dp->tx_empty_waitq); 861 /* TODO: Add any RXDMA setup required per pdev */ 862 } 863 864 int ath12k_dp_pdev_alloc(struct ath12k_base *ab) 865 { 866 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 867 struct ath12k_pdev_dp *dp_pdev; 868 struct ath12k *ar; 869 int ret; 870 int i; 871 872 ret = ath12k_dp_rx_htt_setup(ab); 873 if (ret) 874 goto out; 875 876 /* TODO: Per-pdev rx ring unlike tx ring which is mapped to different AC's */ 877 for (i = 0; i < ab->num_radios; i++) { 878 ar = ab->pdevs[i].ar; 879 880 dp_pdev = &ar->dp; 881 882 dp_pdev->hw = ar->ah->hw; 883 dp_pdev->dp = dp; 884 dp_pdev->hw_link_id = ar->hw_link_id; 885 dp_pdev->dp_hw = &ar->ah->dp_hw; 886 887 ret = ath12k_dp_rx_pdev_alloc(ab, i); 888 if (ret) { 889 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n", 890 i); 891 goto err; 892 } 893 ret = ath12k_dp_rx_pdev_mon_attach(ar); 894 if (ret) { 895 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i); 896 goto err; 897 } 898 } 899 900 for (i = 0; i < ab->num_radios; i++) { 901 ar = ab->pdevs[i].ar; 902 rcu_assign_pointer(dp->dp_pdevs[ar->pdev_idx], &ar->dp); 903 } 904 905 return 0; 906 err: 907 ath12k_dp_pdev_free(ab); 908 out: 909 return ret; 910 } 911 912 static void ath12k_dp_update_vdev_search(struct ath12k_link_vif *arvif) 913 { 914 u8 link_id = arvif->link_id; 915 struct ath12k_vif *ahvif = arvif->ahvif; 916 struct ath12k_dp_link_vif *dp_link_vif; 917 918 dp_link_vif = ath12k_dp_vif_to_dp_link_vif(&ahvif->dp_vif, link_id); 919 920 switch (arvif->ahvif->vdev_type) { 921 case WMI_VDEV_TYPE_STA: 922 dp_link_vif->hal_addr_search_flags = HAL_TX_ADDRY_EN; 923 dp_link_vif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 924 break; 925 case WMI_VDEV_TYPE_AP: 926 case WMI_VDEV_TYPE_IBSS: 927 dp_link_vif->hal_addr_search_flags = HAL_TX_ADDRX_EN; 928 dp_link_vif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 929 break; 930 case WMI_VDEV_TYPE_MONITOR: 931 default: 932 return; 933 } 934 } 935 936 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif) 937 { 938 struct ath12k_base *ab = ar->ab; 939 struct ath12k_vif *ahvif = arvif->ahvif; 940 u8 link_id = arvif->link_id; 941 int bank_id; 942 struct ath12k_dp_link_vif *dp_link_vif; 943 944 dp_link_vif = ath12k_dp_vif_to_dp_link_vif(&ahvif->dp_vif, link_id); 945 946 dp_link_vif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) | 947 u32_encode_bits(arvif->vdev_id, 948 HTT_TCL_META_DATA_VDEV_ID) | 949 u32_encode_bits(ar->pdev->pdev_id, 950 HTT_TCL_META_DATA_PDEV_ID); 951 952 /* set HTT extension valid bit to 0 by default */ 953 dp_link_vif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT; 954 955 ath12k_dp_update_vdev_search(arvif); 956 dp_link_vif->vdev_id_check_en = true; 957 bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, ath12k_ab_to_dp(ab)); 958 dp_link_vif->bank_id = bank_id; 959 960 /* TODO: error path for bank id failure */ 961 if (bank_id == DP_INVALID_BANK_ID) { 962 ath12k_err(ar->ab, "Failed to initialize DP TX Banks"); 963 return; 964 } 965 } 966 967 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab) 968 { 969 struct ath12k_rx_desc_info *desc_info; 970 struct ath12k_tx_desc_info *tx_desc_info, *tmp1; 971 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 972 struct ath12k_skb_cb *skb_cb; 973 struct sk_buff *skb; 974 struct ath12k *ar; 975 int i, j; 976 u32 pool_id, tx_spt_page; 977 978 if (!dp->spt_info) 979 return; 980 981 /* RX Descriptor cleanup */ 982 spin_lock_bh(&dp->rx_desc_lock); 983 984 if (dp->rxbaddr) { 985 for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES(ab); i++) { 986 if (!dp->rxbaddr[i]) 987 continue; 988 989 desc_info = dp->rxbaddr[i]; 990 991 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 992 if (!desc_info[j].in_use) { 993 list_del(&desc_info[j].list); 994 continue; 995 } 996 997 skb = desc_info[j].skb; 998 if (!skb) 999 continue; 1000 1001 dma_unmap_single(ab->dev, 1002 ATH12K_SKB_RXCB(skb)->paddr, 1003 skb->len + skb_tailroom(skb), 1004 DMA_FROM_DEVICE); 1005 dev_kfree_skb_any(skb); 1006 } 1007 1008 kfree(dp->rxbaddr[i]); 1009 dp->rxbaddr[i] = NULL; 1010 } 1011 1012 kfree(dp->rxbaddr); 1013 dp->rxbaddr = NULL; 1014 } 1015 1016 spin_unlock_bh(&dp->rx_desc_lock); 1017 1018 /* TX Descriptor cleanup */ 1019 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { 1020 spin_lock_bh(&dp->tx_desc_lock[i]); 1021 1022 list_for_each_entry_safe(tx_desc_info, tmp1, 1023 &dp->tx_desc_used_list[i], list) { 1024 list_del(&tx_desc_info->list); 1025 skb = tx_desc_info->skb; 1026 1027 if (!skb) 1028 continue; 1029 1030 skb_cb = ATH12K_SKB_CB(skb); 1031 if (skb_cb->paddr_ext_desc) { 1032 dma_unmap_single(ab->dev, 1033 skb_cb->paddr_ext_desc, 1034 tx_desc_info->skb_ext_desc->len, 1035 DMA_TO_DEVICE); 1036 dev_kfree_skb_any(tx_desc_info->skb_ext_desc); 1037 } 1038 1039 /* if we are unregistering, hw would've been destroyed and 1040 * ar is no longer valid. 1041 */ 1042 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) { 1043 ar = skb_cb->ar; 1044 1045 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 1046 wake_up(&ar->dp.tx_empty_waitq); 1047 } 1048 1049 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, 1050 skb->len, DMA_TO_DEVICE); 1051 dev_kfree_skb_any(skb); 1052 } 1053 1054 spin_unlock_bh(&dp->tx_desc_lock[i]); 1055 } 1056 1057 if (dp->txbaddr) { 1058 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { 1059 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 1060 1061 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL(ab); i++) { 1062 tx_spt_page = i + pool_id * 1063 ATH12K_TX_SPT_PAGES_PER_POOL(ab); 1064 if (!dp->txbaddr[tx_spt_page]) 1065 continue; 1066 1067 kfree(dp->txbaddr[tx_spt_page]); 1068 dp->txbaddr[tx_spt_page] = NULL; 1069 } 1070 1071 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1072 } 1073 1074 kfree(dp->txbaddr); 1075 dp->txbaddr = NULL; 1076 } 1077 1078 /* unmap SPT pages */ 1079 for (i = 0; i < dp->num_spt_pages; i++) { 1080 if (!dp->spt_info[i].vaddr) 1081 continue; 1082 1083 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE, 1084 dp->spt_info[i].vaddr, dp->spt_info[i].paddr); 1085 dp->spt_info[i].vaddr = NULL; 1086 } 1087 1088 kfree(dp->spt_info); 1089 dp->spt_info = NULL; 1090 } 1091 1092 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab) 1093 { 1094 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1095 1096 if (!ab->hw_params->reoq_lut_support) 1097 return; 1098 1099 if (dp->reoq_lut.vaddr_unaligned) { 1100 ath12k_hal_write_reoq_lut_addr(ab, 0); 1101 dma_free_coherent(ab->dev, dp->reoq_lut.size, 1102 dp->reoq_lut.vaddr_unaligned, 1103 dp->reoq_lut.paddr_unaligned); 1104 dp->reoq_lut.vaddr_unaligned = NULL; 1105 } 1106 1107 if (dp->ml_reoq_lut.vaddr_unaligned) { 1108 ath12k_hal_write_ml_reoq_lut_addr(ab, 0); 1109 dma_free_coherent(ab->dev, dp->ml_reoq_lut.size, 1110 dp->ml_reoq_lut.vaddr_unaligned, 1111 dp->ml_reoq_lut.paddr_unaligned); 1112 dp->ml_reoq_lut.vaddr_unaligned = NULL; 1113 } 1114 } 1115 1116 static void ath12k_dp_cleanup(struct ath12k_base *ab) 1117 { 1118 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1119 int i; 1120 1121 ath12k_dp_link_peer_rhash_tbl_destroy(dp); 1122 1123 if (!dp->ab) 1124 return; 1125 1126 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 1127 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 1128 1129 ath12k_dp_cc_cleanup(ab); 1130 ath12k_dp_reoq_lut_cleanup(ab); 1131 ath12k_dp_deinit_bank_profiles(ab); 1132 ath12k_dp_srng_common_cleanup(ab); 1133 1134 ath12k_dp_rx_reo_cmd_list_cleanup(ab); 1135 1136 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 1137 kfree(dp->tx_ring[i].tx_status); 1138 dp->tx_ring[i].tx_status = NULL; 1139 } 1140 1141 ath12k_dp_rx_free(ab); 1142 /* Deinit any SOC level resource */ 1143 } 1144 1145 static u32 ath12k_dp_cc_cookie_gen(u16 ppt_idx, u16 spt_idx) 1146 { 1147 return (u32)ppt_idx << ATH12K_CC_PPT_SHIFT | spt_idx; 1148 } 1149 1150 static void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_dp *dp, 1151 u16 ppt_idx, u16 spt_idx) 1152 { 1153 return dp->spt_info[ppt_idx].vaddr + spt_idx; 1154 } 1155 1156 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_dp *dp, 1157 u32 cookie) 1158 { 1159 struct ath12k_rx_desc_info **desc_addr_ptr; 1160 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx; 1161 1162 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT); 1163 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT); 1164 1165 start_ppt_idx = dp->rx_ppt_base + ATH12K_RX_SPT_PAGE_OFFSET(dp->ab); 1166 end_ppt_idx = start_ppt_idx + ATH12K_NUM_RX_SPT_PAGES(dp->ab); 1167 1168 if (ppt_idx < start_ppt_idx || 1169 ppt_idx >= end_ppt_idx || 1170 spt_idx > ATH12K_MAX_SPT_ENTRIES) 1171 return NULL; 1172 1173 ppt_idx = ppt_idx - dp->rx_ppt_base; 1174 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(dp, ppt_idx, spt_idx); 1175 1176 return *desc_addr_ptr; 1177 } 1178 EXPORT_SYMBOL(ath12k_dp_get_rx_desc); 1179 1180 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_dp *dp, 1181 u32 cookie) 1182 { 1183 struct ath12k_tx_desc_info **desc_addr_ptr; 1184 u16 start_ppt_idx, end_ppt_idx, ppt_idx, spt_idx; 1185 1186 ppt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT); 1187 spt_idx = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_SPT); 1188 1189 start_ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET; 1190 end_ppt_idx = start_ppt_idx + 1191 (ATH12K_TX_SPT_PAGES_PER_POOL(dp->ab) * ATH12K_HW_MAX_QUEUES); 1192 1193 if (ppt_idx < start_ppt_idx || 1194 ppt_idx >= end_ppt_idx || 1195 spt_idx > ATH12K_MAX_SPT_ENTRIES) 1196 return NULL; 1197 1198 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(dp, ppt_idx, spt_idx); 1199 1200 return *desc_addr_ptr; 1201 } 1202 EXPORT_SYMBOL(ath12k_dp_get_tx_desc); 1203 1204 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab) 1205 { 1206 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1207 struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr; 1208 struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr; 1209 u32 num_rx_spt_pages = ATH12K_NUM_RX_SPT_PAGES(ab); 1210 u32 i, j, pool_id, tx_spt_page; 1211 u32 ppt_idx, cookie_ppt_idx; 1212 1213 spin_lock_bh(&dp->rx_desc_lock); 1214 1215 dp->rxbaddr = kzalloc_objs(struct ath12k_rx_desc_info *, 1216 num_rx_spt_pages, GFP_ATOMIC); 1217 1218 if (!dp->rxbaddr) { 1219 spin_unlock_bh(&dp->rx_desc_lock); 1220 return -ENOMEM; 1221 } 1222 1223 /* First ATH12K_NUM_RX_SPT_PAGES(ab) of allocated SPT pages are used for 1224 * RX 1225 */ 1226 for (i = 0; i < num_rx_spt_pages; i++) { 1227 rx_descs = kzalloc_objs(*rx_descs, ATH12K_MAX_SPT_ENTRIES, 1228 GFP_ATOMIC); 1229 1230 if (!rx_descs) { 1231 spin_unlock_bh(&dp->rx_desc_lock); 1232 return -ENOMEM; 1233 } 1234 1235 ppt_idx = ATH12K_RX_SPT_PAGE_OFFSET(ab) + i; 1236 cookie_ppt_idx = dp->rx_ppt_base + ppt_idx; 1237 dp->rxbaddr[i] = &rx_descs[0]; 1238 1239 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1240 rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(cookie_ppt_idx, j); 1241 rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC; 1242 rx_descs[j].device_id = ab->device_id; 1243 list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list); 1244 1245 /* Update descriptor VA in SPT */ 1246 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(dp, ppt_idx, j); 1247 *rx_desc_addr = &rx_descs[j]; 1248 } 1249 } 1250 1251 spin_unlock_bh(&dp->rx_desc_lock); 1252 1253 dp->txbaddr = kzalloc_objs(struct ath12k_tx_desc_info *, 1254 ATH12K_NUM_TX_SPT_PAGES(ab), GFP_ATOMIC); 1255 1256 if (!dp->txbaddr) 1257 return -ENOMEM; 1258 1259 for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { 1260 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 1261 for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL(ab); i++) { 1262 tx_descs = kzalloc_objs(*tx_descs, 1263 ATH12K_MAX_SPT_ENTRIES, 1264 GFP_ATOMIC); 1265 1266 if (!tx_descs) { 1267 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1268 /* Caller takes care of TX pending and RX desc cleanup */ 1269 return -ENOMEM; 1270 } 1271 1272 tx_spt_page = i + pool_id * 1273 ATH12K_TX_SPT_PAGES_PER_POOL(ab); 1274 ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET + tx_spt_page; 1275 1276 dp->txbaddr[tx_spt_page] = &tx_descs[0]; 1277 1278 for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { 1279 tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j); 1280 tx_descs[j].pool_id = pool_id; 1281 list_add_tail(&tx_descs[j].list, 1282 &dp->tx_desc_free_list[pool_id]); 1283 1284 /* Update descriptor VA in SPT */ 1285 tx_desc_addr = 1286 ath12k_dp_cc_get_desc_addr_ptr(dp, ppt_idx, j); 1287 *tx_desc_addr = &tx_descs[j]; 1288 } 1289 } 1290 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 1291 } 1292 return 0; 1293 } 1294 1295 static int ath12k_dp_cmem_init(struct ath12k_base *ab, 1296 struct ath12k_dp *dp, 1297 enum ath12k_dp_desc_type type) 1298 { 1299 u32 cmem_base; 1300 int i, start, end; 1301 1302 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; 1303 1304 switch (type) { 1305 case ATH12K_DP_TX_DESC: 1306 start = ATH12K_TX_SPT_PAGE_OFFSET; 1307 end = start + ATH12K_NUM_TX_SPT_PAGES(ab); 1308 break; 1309 case ATH12K_DP_RX_DESC: 1310 cmem_base += ATH12K_PPT_ADDR_OFFSET(dp->rx_ppt_base); 1311 start = ATH12K_RX_SPT_PAGE_OFFSET(ab); 1312 end = start + ATH12K_NUM_RX_SPT_PAGES(ab); 1313 break; 1314 default: 1315 ath12k_err(ab, "invalid descriptor type %d in cmem init\n", type); 1316 return -EINVAL; 1317 } 1318 1319 /* Write to PPT in CMEM */ 1320 for (i = start; i < end; i++) 1321 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), 1322 dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); 1323 1324 return 0; 1325 } 1326 1327 void ath12k_dp_partner_cc_init(struct ath12k_base *ab) 1328 { 1329 struct ath12k_hw_group *ag = ab->ag; 1330 int i; 1331 1332 for (i = 0; i < ag->num_devices; i++) { 1333 if (ag->ab[i] == ab) 1334 continue; 1335 1336 ath12k_dp_cmem_init(ab, ath12k_ab_to_dp(ag->ab[i]), ATH12K_DP_RX_DESC); 1337 } 1338 } 1339 1340 static u32 ath12k_dp_get_num_spt_pages(struct ath12k_base *ab) 1341 { 1342 return ATH12K_NUM_RX_SPT_PAGES(ab) + ATH12K_NUM_TX_SPT_PAGES(ab); 1343 } 1344 1345 static int ath12k_dp_cc_init(struct ath12k_base *ab) 1346 { 1347 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1348 int i, ret = 0; 1349 1350 INIT_LIST_HEAD(&dp->rx_desc_free_list); 1351 spin_lock_init(&dp->rx_desc_lock); 1352 1353 for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { 1354 INIT_LIST_HEAD(&dp->tx_desc_free_list[i]); 1355 INIT_LIST_HEAD(&dp->tx_desc_used_list[i]); 1356 spin_lock_init(&dp->tx_desc_lock[i]); 1357 } 1358 1359 dp->num_spt_pages = ath12k_dp_get_num_spt_pages(ab); 1360 if (dp->num_spt_pages > ATH12K_MAX_PPT_ENTRIES) 1361 dp->num_spt_pages = ATH12K_MAX_PPT_ENTRIES; 1362 1363 dp->spt_info = kzalloc_objs(struct ath12k_spt_info, dp->num_spt_pages); 1364 1365 if (!dp->spt_info) { 1366 ath12k_warn(ab, "SPT page allocation failure"); 1367 return -ENOMEM; 1368 } 1369 1370 dp->rx_ppt_base = ab->device_id * ATH12K_NUM_RX_SPT_PAGES(ab); 1371 1372 for (i = 0; i < dp->num_spt_pages; i++) { 1373 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev, 1374 ATH12K_PAGE_SIZE, 1375 &dp->spt_info[i].paddr, 1376 GFP_KERNEL); 1377 1378 if (!dp->spt_info[i].vaddr) { 1379 ret = -ENOMEM; 1380 goto free; 1381 } 1382 1383 if (dp->spt_info[i].paddr & ATH12K_SPT_4K_ALIGN_CHECK) { 1384 ath12k_warn(ab, "SPT allocated memory is not 4K aligned"); 1385 ret = -EINVAL; 1386 goto free; 1387 } 1388 } 1389 1390 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_TX_DESC); 1391 if (ret) { 1392 ath12k_warn(ab, "HW CC Tx cmem init failed %d", ret); 1393 goto free; 1394 } 1395 1396 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_RX_DESC); 1397 if (ret) { 1398 ath12k_warn(ab, "HW CC Rx cmem init failed %d", ret); 1399 goto free; 1400 } 1401 1402 ret = ath12k_dp_cc_desc_init(ab); 1403 if (ret) { 1404 ath12k_warn(ab, "HW CC desc init failed %d", ret); 1405 goto free; 1406 } 1407 1408 return 0; 1409 free: 1410 ath12k_dp_cc_cleanup(ab); 1411 return ret; 1412 } 1413 1414 static int ath12k_dp_alloc_reoq_lut(struct ath12k_base *ab, 1415 struct ath12k_reo_q_addr_lut *lut) 1416 { 1417 lut->size = DP_REOQ_LUT_SIZE + HAL_REO_QLUT_ADDR_ALIGN - 1; 1418 lut->vaddr_unaligned = dma_alloc_coherent(ab->dev, lut->size, 1419 &lut->paddr_unaligned, 1420 GFP_KERNEL | __GFP_ZERO); 1421 if (!lut->vaddr_unaligned) 1422 return -ENOMEM; 1423 1424 lut->vaddr = PTR_ALIGN(lut->vaddr_unaligned, HAL_REO_QLUT_ADDR_ALIGN); 1425 lut->paddr = lut->paddr_unaligned + 1426 ((unsigned long)lut->vaddr - (unsigned long)lut->vaddr_unaligned); 1427 return 0; 1428 } 1429 1430 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab) 1431 { 1432 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 1433 int ret; 1434 1435 if (!ab->hw_params->reoq_lut_support) 1436 return 0; 1437 1438 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->reoq_lut); 1439 if (ret) { 1440 ath12k_warn(ab, "failed to allocate memory for reoq table"); 1441 return ret; 1442 } 1443 1444 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->ml_reoq_lut); 1445 if (ret) { 1446 ath12k_warn(ab, "failed to allocate memory for ML reoq table"); 1447 dma_free_coherent(ab->dev, dp->reoq_lut.size, 1448 dp->reoq_lut.vaddr_unaligned, 1449 dp->reoq_lut.paddr_unaligned); 1450 dp->reoq_lut.vaddr_unaligned = NULL; 1451 return ret; 1452 } 1453 1454 /* Bits in the register have address [39:8] LUT base address to be 1455 * allocated such that LSBs are assumed to be zero. Also, current 1456 * design supports paddr up to 4 GB max hence it fits in 32 bit 1457 * register only 1458 */ 1459 1460 ath12k_hal_write_reoq_lut_addr(ab, dp->reoq_lut.paddr >> 8); 1461 ath12k_hal_write_ml_reoq_lut_addr(ab, dp->ml_reoq_lut.paddr >> 8); 1462 ath12k_hal_reoq_lut_addr_read_enable(ab); 1463 ath12k_hal_reoq_lut_set_max_peerid(ab); 1464 1465 return 0; 1466 } 1467 1468 static int ath12k_dp_setup(struct ath12k_base *ab) 1469 { 1470 struct ath12k_dp *dp; 1471 struct hal_srng *srng = NULL; 1472 size_t size = 0; 1473 u32 n_link_desc = 0; 1474 int ret; 1475 int i; 1476 1477 dp = ath12k_ab_to_dp(ab); 1478 dp->ab = ab; 1479 1480 INIT_LIST_HEAD(&dp->reo_cmd_list); 1481 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list); 1482 INIT_LIST_HEAD(&dp->reo_cmd_update_rx_queue_list); 1483 spin_lock_init(&dp->reo_cmd_lock); 1484 spin_lock_init(&dp->reo_rxq_flush_lock); 1485 1486 spin_lock_init(&dp->dp_lock); 1487 INIT_LIST_HEAD(&dp->peers); 1488 1489 mutex_init(&dp->link_peer_rhash_tbl_lock); 1490 1491 dp->reo_cmd_cache_flush_count = 0; 1492 dp->idle_link_rbm = 1493 ath12k_hal_get_idle_link_rbm(&ab->hal, ab->device_id); 1494 1495 ret = ath12k_dp_link_peer_rhash_tbl_init(dp); 1496 if (ret) { 1497 ath12k_warn(ab, "failed to init link_peer rhash table: %d\n", ret); 1498 return ret; 1499 } 1500 1501 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc); 1502 if (ret) { 1503 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 1504 goto rhash_destroy; 1505 } 1506 1507 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id]; 1508 1509 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks, 1510 HAL_WBM_IDLE_LINK, srng, n_link_desc); 1511 if (ret) { 1512 ath12k_warn(ab, "failed to setup link desc: %d\n", ret); 1513 goto rhash_destroy; 1514 } 1515 1516 ret = ath12k_dp_cc_init(ab); 1517 1518 if (ret) { 1519 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret); 1520 goto fail_link_desc_cleanup; 1521 } 1522 ret = ath12k_dp_init_bank_profiles(ab); 1523 if (ret) { 1524 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret); 1525 goto fail_hw_cc_cleanup; 1526 } 1527 1528 ret = ath12k_dp_srng_common_setup(ab); 1529 if (ret) 1530 goto fail_dp_bank_profiles_cleanup; 1531 1532 size = ab->hal.hal_wbm_release_ring_tx_size * 1533 DP_TX_COMP_RING_SIZE(ab); 1534 1535 ret = ath12k_dp_reoq_lut_setup(ab); 1536 if (ret) { 1537 ath12k_warn(ab, "failed to setup reoq table %d\n", ret); 1538 goto fail_cmn_srng_cleanup; 1539 } 1540 1541 for (i = 0; i < ab->hw_params->max_tx_ring; i++) { 1542 dp->tx_ring[i].tcl_data_ring_id = i; 1543 1544 dp->tx_ring[i].tx_status_head = 0; 1545 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE(ab) - 1; 1546 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL); 1547 if (!dp->tx_ring[i].tx_status) { 1548 ret = -ENOMEM; 1549 /* FIXME: The allocated tx status is not freed 1550 * properly here 1551 */ 1552 goto fail_cmn_reoq_cleanup; 1553 } 1554 } 1555 1556 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++) 1557 ath12k_hal_tx_set_dscp_tid_map(ab, i); 1558 1559 ret = ath12k_dp_rx_alloc(ab); 1560 if (ret) 1561 goto fail_dp_rx_free; 1562 1563 /* Init any SOC level resource for DP */ 1564 1565 return 0; 1566 1567 fail_dp_rx_free: 1568 ath12k_dp_rx_free(ab); 1569 1570 fail_cmn_reoq_cleanup: 1571 ath12k_dp_reoq_lut_cleanup(ab); 1572 1573 fail_cmn_srng_cleanup: 1574 ath12k_dp_srng_common_cleanup(ab); 1575 1576 fail_dp_bank_profiles_cleanup: 1577 ath12k_dp_deinit_bank_profiles(ab); 1578 1579 fail_hw_cc_cleanup: 1580 ath12k_dp_cc_cleanup(ab); 1581 1582 fail_link_desc_cleanup: 1583 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 1584 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 1585 rhash_destroy: 1586 ath12k_dp_link_peer_rhash_tbl_destroy(dp); 1587 1588 return ret; 1589 } 1590 1591 void ath12k_dp_cmn_device_deinit(struct ath12k_dp *dp) 1592 { 1593 ath12k_dp_cleanup(dp->ab); 1594 } 1595 1596 int ath12k_dp_cmn_device_init(struct ath12k_dp *dp) 1597 { 1598 int ret; 1599 1600 ret = ath12k_dp_setup(dp->ab); 1601 if (ret) 1602 return ret; 1603 1604 return 0; 1605 } 1606 1607 void ath12k_dp_cmn_hw_group_unassign(struct ath12k_dp *dp, 1608 struct ath12k_hw_group *ag) 1609 { 1610 struct ath12k_dp_hw_group *dp_hw_grp = &ag->dp_hw_grp; 1611 1612 lockdep_assert_held(&ag->mutex); 1613 1614 dp_hw_grp->dp[dp->device_id] = NULL; 1615 1616 dp->ag = NULL; 1617 dp->device_id = ATH12K_INVALID_DEVICE_ID; 1618 } 1619 1620 void ath12k_dp_cmn_hw_group_assign(struct ath12k_dp *dp, 1621 struct ath12k_hw_group *ag) 1622 { 1623 struct ath12k_base *ab = dp->ab; 1624 struct ath12k_dp_hw_group *dp_hw_grp = &ag->dp_hw_grp; 1625 1626 dp->ag = ag; 1627 dp->device_id = ab->device_id; 1628 dp_hw_grp->dp[dp->device_id] = dp; 1629 } 1630