1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/msi.h>
8 #include <linux/pci.h>
9 #include <linux/firmware.h>
10 #if defined(CONFIG_OF)
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #endif
14 #include <linux/ioport.h>
15 #if defined(__FreeBSD__)
16 #include <linux/delay.h>
17 #endif
18
19 #include "core.h"
20 #include "debug.h"
21 #include "mhi.h"
22 #include "pci.h"
23 #include "pcic.h"
24
25 #define MHI_TIMEOUT_DEFAULT_MS 20000
26 #define RDDM_DUMP_SIZE 0x420000
27 #define MHI_CB_INVALID 0xff
28
29 static const struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
30 {
31 .num = 20,
32 .name = "IPCR",
33 .num_elements = 64,
34 .event_ring = 1,
35 .dir = DMA_TO_DEVICE,
36 .ee_mask = 0x4,
37 .pollcfg = 0,
38 .doorbell = MHI_DB_BRST_DISABLE,
39 .lpm_notify = false,
40 .offload_channel = false,
41 .doorbell_mode_switch = false,
42 .auto_queue = false,
43 },
44 {
45 .num = 21,
46 .name = "IPCR",
47 .num_elements = 64,
48 .event_ring = 1,
49 .dir = DMA_FROM_DEVICE,
50 .ee_mask = 0x4,
51 .pollcfg = 0,
52 .doorbell = MHI_DB_BRST_DISABLE,
53 .lpm_notify = false,
54 .offload_channel = false,
55 .doorbell_mode_switch = false,
56 .auto_queue = true,
57 },
58 };
59
60 static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
61 {
62 .num_elements = 32,
63 .irq_moderation_ms = 0,
64 .irq = 1,
65 .mode = MHI_DB_BRST_DISABLE,
66 .data_type = MHI_ER_CTRL,
67 .hardware_event = false,
68 .client_managed = false,
69 .offload_channel = false,
70 },
71 {
72 .num_elements = 256,
73 .irq_moderation_ms = 1,
74 .irq = 2,
75 .mode = MHI_DB_BRST_DISABLE,
76 .priority = 1,
77 .hardware_event = false,
78 .client_managed = false,
79 .offload_channel = false,
80 },
81 };
82
83 static const struct mhi_controller_config ath11k_mhi_config_qca6390 = {
84 .max_channels = 128,
85 .timeout_ms = 2000,
86 .use_bounce_buf = false,
87 .buf_len = 8192,
88 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
89 .ch_cfg = ath11k_mhi_channels_qca6390,
90 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
91 .event_cfg = ath11k_mhi_events_qca6390,
92 };
93
94 static const struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
95 {
96 .num = 20,
97 .name = "IPCR",
98 .num_elements = 32,
99 .event_ring = 1,
100 .dir = DMA_TO_DEVICE,
101 .ee_mask = 0x14,
102 .pollcfg = 0,
103 .doorbell = MHI_DB_BRST_DISABLE,
104 .lpm_notify = false,
105 .offload_channel = false,
106 .doorbell_mode_switch = false,
107 .auto_queue = false,
108 },
109 {
110 .num = 21,
111 .name = "IPCR",
112 .num_elements = 32,
113 .event_ring = 1,
114 .dir = DMA_FROM_DEVICE,
115 .ee_mask = 0x14,
116 .pollcfg = 0,
117 .doorbell = MHI_DB_BRST_DISABLE,
118 .lpm_notify = false,
119 .offload_channel = false,
120 .doorbell_mode_switch = false,
121 .auto_queue = true,
122 },
123 };
124
125 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
126 {
127 .num_elements = 32,
128 .irq_moderation_ms = 0,
129 .irq = 1,
130 .data_type = MHI_ER_CTRL,
131 .mode = MHI_DB_BRST_DISABLE,
132 .hardware_event = false,
133 .client_managed = false,
134 .offload_channel = false,
135 },
136 {
137 .num_elements = 256,
138 .irq_moderation_ms = 1,
139 .irq = 2,
140 .mode = MHI_DB_BRST_DISABLE,
141 .priority = 1,
142 .hardware_event = false,
143 .client_managed = false,
144 .offload_channel = false,
145 },
146 };
147
148 static const struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
149 .max_channels = 30,
150 .timeout_ms = 10000,
151 .use_bounce_buf = false,
152 .buf_len = 0,
153 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
154 .ch_cfg = ath11k_mhi_channels_qcn9074,
155 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
156 .event_cfg = ath11k_mhi_events_qcn9074,
157 };
158
ath11k_mhi_set_mhictrl_reset(struct ath11k_base * ab)159 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
160 {
161 u32 val;
162
163 val = ath11k_pcic_read32(ab, MHISTATUS);
164
165 ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val);
166
167 /* After SOC_GLOBAL_RESET, MHISTATUS may still have SYSERR bit set
168 * and thus need to set MHICTRL_RESET to clear SYSERR.
169 */
170 ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
171
172 mdelay(10);
173 }
174
ath11k_mhi_reset_txvecdb(struct ath11k_base * ab)175 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab)
176 {
177 ath11k_pcic_write32(ab, PCIE_TXVECDB, 0);
178 }
179
ath11k_mhi_reset_txvecstatus(struct ath11k_base * ab)180 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab)
181 {
182 ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0);
183 }
184
ath11k_mhi_reset_rxvecdb(struct ath11k_base * ab)185 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab)
186 {
187 ath11k_pcic_write32(ab, PCIE_RXVECDB, 0);
188 }
189
ath11k_mhi_reset_rxvecstatus(struct ath11k_base * ab)190 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab)
191 {
192 ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0);
193 }
194
ath11k_mhi_clear_vector(struct ath11k_base * ab)195 void ath11k_mhi_clear_vector(struct ath11k_base *ab)
196 {
197 ath11k_mhi_reset_txvecdb(ab);
198 ath11k_mhi_reset_txvecstatus(ab);
199 ath11k_mhi_reset_rxvecdb(ab);
200 ath11k_mhi_reset_rxvecstatus(ab);
201 }
202
ath11k_mhi_get_msi(struct ath11k_pci * ab_pci)203 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
204 {
205 struct ath11k_base *ab = ab_pci->ab;
206 u32 user_base_data, base_vector;
207 int ret, num_vectors, i;
208 int *irq;
209 unsigned int msi_data;
210
211 ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors,
212 &user_base_data, &base_vector);
213 if (ret)
214 return ret;
215
216 ath11k_dbg(ab, ATH11K_DBG_PCI, "num_vectors %d base_vector %d\n",
217 num_vectors, base_vector);
218
219 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL);
220 if (!irq)
221 return -ENOMEM;
222
223 for (i = 0; i < num_vectors; i++) {
224 msi_data = base_vector;
225
226 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
227 msi_data += i;
228
229 irq[i] = ath11k_pci_get_msi_irq(ab, msi_data);
230 }
231
232 ab_pci->mhi_ctrl->irq = irq;
233 ab_pci->mhi_ctrl->nr_irqs = num_vectors;
234
235 return 0;
236 }
237
ath11k_mhi_op_runtime_get(struct mhi_controller * mhi_cntrl)238 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
239 {
240 return 0;
241 }
242
ath11k_mhi_op_runtime_put(struct mhi_controller * mhi_cntrl)243 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
244 {
245 }
246
ath11k_mhi_op_callback_to_str(enum mhi_callback reason)247 static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason)
248 {
249 switch (reason) {
250 case MHI_CB_IDLE:
251 return "MHI_CB_IDLE";
252 case MHI_CB_PENDING_DATA:
253 return "MHI_CB_PENDING_DATA";
254 case MHI_CB_LPM_ENTER:
255 return "MHI_CB_LPM_ENTER";
256 case MHI_CB_LPM_EXIT:
257 return "MHI_CB_LPM_EXIT";
258 case MHI_CB_EE_RDDM:
259 return "MHI_CB_EE_RDDM";
260 case MHI_CB_EE_MISSION_MODE:
261 return "MHI_CB_EE_MISSION_MODE";
262 case MHI_CB_SYS_ERROR:
263 return "MHI_CB_SYS_ERROR";
264 case MHI_CB_FATAL_ERROR:
265 return "MHI_CB_FATAL_ERROR";
266 case MHI_CB_BW_REQ:
267 return "MHI_CB_BW_REQ";
268 default:
269 return "UNKNOWN";
270 }
271 };
272
ath11k_mhi_op_status_cb(struct mhi_controller * mhi_cntrl,enum mhi_callback cb)273 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
274 enum mhi_callback cb)
275 {
276 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
277 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
278
279 ath11k_dbg(ab, ATH11K_DBG_BOOT, "notify status reason %s\n",
280 ath11k_mhi_op_callback_to_str(cb));
281
282 switch (cb) {
283 case MHI_CB_SYS_ERROR:
284 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
285 break;
286 case MHI_CB_EE_RDDM:
287 ath11k_warn(ab, "firmware crashed: MHI_CB_EE_RDDM\n");
288 if (ab_pci->mhi_pre_cb == MHI_CB_EE_RDDM) {
289 ath11k_dbg(ab, ATH11K_DBG_BOOT,
290 "do not queue again for consecutive RDDM event\n");
291 break;
292 }
293
294 if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags)))
295 queue_work(ab->workqueue_aux, &ab->reset_work);
296
297 break;
298 default:
299 break;
300 }
301
302 ab_pci->mhi_pre_cb = cb;
303 }
304
ath11k_mhi_op_read_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 * out)305 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
306 void __iomem *addr,
307 u32 *out)
308 {
309 *out = readl(addr);
310
311 return 0;
312 }
313
ath11k_mhi_op_write_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 val)314 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
315 void __iomem *addr,
316 u32 val)
317 {
318 writel(val, addr);
319 }
320
ath11k_mhi_read_addr_from_dt(struct mhi_controller * mhi_ctrl)321 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
322 {
323 #if defined(__linux__)
324 struct device_node *np;
325 struct resource res;
326 int ret;
327
328 np = of_find_node_by_type(NULL, "memory");
329 if (!np)
330 return -ENOENT;
331
332 ret = of_address_to_resource(np, 0, &res);
333 of_node_put(np);
334 if (ret)
335 return ret;
336
337 mhi_ctrl->iova_start = res.start + 0x1000000;
338 mhi_ctrl->iova_stop = res.end;
339
340 return 0;
341 #elif defined(__FreeBSD__)
342 return -ENOENT;
343 #endif
344 }
345
ath11k_mhi_register(struct ath11k_pci * ab_pci)346 int ath11k_mhi_register(struct ath11k_pci *ab_pci)
347 {
348 struct ath11k_base *ab = ab_pci->ab;
349 struct mhi_controller *mhi_ctrl;
350 const struct mhi_controller_config *ath11k_mhi_config;
351 int ret;
352
353 mhi_ctrl = mhi_alloc_controller();
354 if (!mhi_ctrl)
355 return -ENOMEM;
356
357 ab_pci->mhi_ctrl = mhi_ctrl;
358 mhi_ctrl->cntrl_dev = ab->dev;
359 mhi_ctrl->regs = ab->mem;
360 mhi_ctrl->reg_len = ab->mem_len;
361
362 if (ab->fw.amss_data && ab->fw.amss_len > 0) {
363 /* use MHI firmware file from firmware-N.bin */
364 mhi_ctrl->fw_data = ab->fw.amss_data;
365 mhi_ctrl->fw_sz = ab->fw.amss_len;
366 } else {
367 /* use the old separate mhi.bin MHI firmware file */
368 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE,
369 ab_pci->amss_path,
370 sizeof(ab_pci->amss_path));
371 mhi_ctrl->fw_image = ab_pci->amss_path;
372 }
373
374 ret = ath11k_mhi_get_msi(ab_pci);
375 if (ret) {
376 ath11k_err(ab, "failed to get msi for mhi\n");
377 goto free_controller;
378 }
379
380 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
381 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
382
383 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) {
384 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl);
385 if (ret < 0)
386 goto free_controller;
387 } else {
388 mhi_ctrl->iova_start = 0;
389 mhi_ctrl->iova_stop = ab_pci->dma_mask;
390 }
391
392 mhi_ctrl->rddm_size = RDDM_DUMP_SIZE;
393 mhi_ctrl->sbl_size = SZ_512K;
394 mhi_ctrl->seg_len = SZ_512K;
395 mhi_ctrl->fbc_download = true;
396 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get;
397 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put;
398 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
399 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
400 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
401
402 switch (ab->hw_rev) {
403 case ATH11K_HW_QCN9074_HW10:
404 ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
405 break;
406 case ATH11K_HW_QCA6390_HW20:
407 case ATH11K_HW_WCN6855_HW20:
408 case ATH11K_HW_WCN6855_HW21:
409 case ATH11K_HW_QCA2066_HW21:
410 case ATH11K_HW_QCA6698AQ_HW21:
411 ath11k_mhi_config = &ath11k_mhi_config_qca6390;
412 break;
413 default:
414 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n",
415 ab->hw_rev);
416 ret = -EINVAL;
417 goto free_controller;
418 }
419
420 ab_pci->mhi_pre_cb = MHI_CB_INVALID;
421 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
422 if (ret) {
423 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
424 goto free_controller;
425 }
426
427 return 0;
428
429 free_controller:
430 mhi_free_controller(mhi_ctrl);
431 ab_pci->mhi_ctrl = NULL;
432 return ret;
433 }
434
ath11k_mhi_unregister(struct ath11k_pci * ab_pci)435 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci)
436 {
437 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
438
439 mhi_unregister_controller(mhi_ctrl);
440 kfree(mhi_ctrl->irq);
441 mhi_free_controller(mhi_ctrl);
442 }
443
ath11k_mhi_start(struct ath11k_pci * ab_pci)444 int ath11k_mhi_start(struct ath11k_pci *ab_pci)
445 {
446 struct ath11k_base *ab = ab_pci->ab;
447 int ret;
448
449 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
450
451 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
452 if (ret) {
453 ath11k_warn(ab, "failed to prepare mhi: %d", ret);
454 return ret;
455 }
456
457 ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
458 if (ret) {
459 ath11k_warn(ab, "failed to power up mhi: %d", ret);
460 return ret;
461 }
462
463 return 0;
464 }
465
ath11k_mhi_stop(struct ath11k_pci * ab_pci,bool is_suspend)466 void ath11k_mhi_stop(struct ath11k_pci *ab_pci, bool is_suspend)
467 {
468 /* During suspend we need to use mhi_power_down_keep_dev()
469 * workaround, otherwise ath11k_core_resume() will timeout
470 * during resume.
471 */
472 if (is_suspend)
473 mhi_power_down_keep_dev(ab_pci->mhi_ctrl, true);
474 else
475 mhi_power_down(ab_pci->mhi_ctrl, true);
476
477 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
478 }
479
ath11k_mhi_suspend(struct ath11k_pci * ab_pci)480 int ath11k_mhi_suspend(struct ath11k_pci *ab_pci)
481 {
482 struct ath11k_base *ab = ab_pci->ab;
483 int ret;
484
485 ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
486 if (ret) {
487 ath11k_warn(ab, "failed to suspend mhi: %d", ret);
488 return ret;
489 }
490
491 return 0;
492 }
493
ath11k_mhi_resume(struct ath11k_pci * ab_pci)494 int ath11k_mhi_resume(struct ath11k_pci *ab_pci)
495 {
496 struct ath11k_base *ab = ab_pci->ab;
497 int ret;
498
499 /* Do force MHI resume as some devices like QCA6390, WCN6855
500 * are not in M3 state but they are functional. So just ignore
501 * the MHI state while resuming.
502 */
503 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl);
504 if (ret) {
505 ath11k_warn(ab, "failed to resume mhi: %d", ret);
506 return ret;
507 }
508
509 return 0;
510 }
511
ath11k_mhi_coredump(struct mhi_controller * mhi_ctrl,bool in_panic)512 void ath11k_mhi_coredump(struct mhi_controller *mhi_ctrl, bool in_panic)
513 {
514 mhi_download_rddm_image(mhi_ctrl, in_panic);
515 }
516