1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 struct hal_rx_desc *desc)
33 {
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 return HAL_ENCRYPT_TYPE_OPEN;
36
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 struct hal_rx_desc *desc)
42 {
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 struct hal_rx_desc *desc)
49 {
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 struct hal_rx_desc *desc)
56 {
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 struct hal_rx_desc *desc)
63 {
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 struct hal_rx_desc *desc)
69 {
70 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 struct sk_buff *skb)
75 {
76 struct ieee80211_hdr *hdr;
77
78 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 return ieee80211_has_morefrags(hdr->frame_control);
80 }
81
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 struct sk_buff *skb)
84 {
85 struct ieee80211_hdr *hdr;
86
87 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 struct hal_rx_desc *desc)
93 {
94 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 struct hal_rx_desc *desc)
99 {
100 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 __le32_to_cpu(attn->info2));
107 }
108
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 __le32_to_cpu(attn->info1));
113 }
114
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 __le32_to_cpu(attn->info1));
119 }
120
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 __le32_to_cpu(attn->info2)) ==
125 RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 u32 info = __le32_to_cpu(attn->info1);
131 u32 errmap = 0;
132
133 if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 errmap |= DP_RX_MPDU_ERR_FCS;
135
136 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 errmap |= DP_RX_MPDU_ERR_DECRYPT;
138
139 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141
142 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144
145 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147
148 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150
151 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153
154 return errmap;
155 }
156
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 struct hal_rx_desc *desc)
159 {
160 struct rx_attention *rx_attention;
161 u32 errmap;
162
163 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165
166 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 struct hal_rx_desc *desc)
171 {
172 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 struct hal_rx_desc *desc)
177 {
178 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 struct hal_rx_desc *desc)
183 {
184 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 struct hal_rx_desc *desc)
189 {
190 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 struct hal_rx_desc *desc)
195 {
196 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 struct hal_rx_desc *desc)
201 {
202 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 struct hal_rx_desc *desc)
207 {
208 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 struct hal_rx_desc *desc)
213 {
214 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 struct hal_rx_desc *desc)
219 {
220 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 struct hal_rx_desc *desc)
225 {
226 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 struct hal_rx_desc *desc)
231 {
232 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 struct hal_rx_desc *desc)
237 {
238 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 struct hal_rx_desc *fdesc,
243 struct hal_rx_desc *ldesc)
244 {
245 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 __le32_to_cpu(attn->info1));
252 }
253
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 struct hal_rx_desc *rx_desc)
256 {
257 u8 *rx_pkt_hdr;
258
259 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260
261 return rx_pkt_hdr;
262 }
263
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 struct hal_rx_desc *rx_desc)
266 {
267 u32 tlv_tag;
268
269 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270
271 return tlv_tag == HAL_RX_MPDU_START;
272 }
273
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 struct hal_rx_desc *rx_desc)
276 {
277 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 struct hal_rx_desc *desc,
282 u16 len)
283 {
284 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 struct hal_rx_desc *desc)
289 {
290 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291
292 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 __le32_to_cpu(attn->info1)));
295 }
296
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 struct hal_rx_desc *desc)
299 {
300 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 struct hal_rx_desc *desc)
305 {
306 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 struct ath11k_base *ab = timer_container_of(ab, t, mon_reap_timer);
312 int i;
313
314 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
315 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316
317 mod_timer(&ab->mon_reap_timer, jiffies +
318 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 int i, reaped = 0;
324 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325
326 do {
327 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
328 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 NULL,
330 DP_MON_SERVICE_BUDGET);
331
332 /* nothing more to reap */
333 if (reaped < DP_MON_SERVICE_BUDGET)
334 return 0;
335
336 } while (time_before(jiffies, timeout));
337
338 ath11k_warn(ab, "dp mon ring purge timeout");
339
340 return -ETIMEDOUT;
341 }
342
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 struct dp_rxdma_ring *rx_ring,
346 int req_entries,
347 enum hal_rx_buf_return_buf_manager mgr)
348 {
349 struct hal_srng *srng;
350 u32 *desc;
351 struct sk_buff *skb;
352 int num_free;
353 int num_remain;
354 int buf_id;
355 u32 cookie;
356 dma_addr_t paddr;
357
358 req_entries = min(req_entries, rx_ring->bufs_max);
359
360 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361
362 spin_lock_bh(&srng->lock);
363
364 ath11k_hal_srng_access_begin(ab, srng);
365
366 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 req_entries = num_free;
369
370 req_entries = min(num_free, req_entries);
371 num_remain = req_entries;
372
373 while (num_remain > 0) {
374 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 DP_RX_BUFFER_ALIGN_SIZE);
376 if (!skb)
377 break;
378
379 if (!IS_ALIGNED((unsigned long)skb->data,
380 DP_RX_BUFFER_ALIGN_SIZE)) {
381 skb_pull(skb,
382 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 skb->data);
384 }
385
386 paddr = dma_map_single(ab->dev, skb->data,
387 skb->len + skb_tailroom(skb),
388 DMA_FROM_DEVICE);
389 if (dma_mapping_error(ab->dev, paddr))
390 goto fail_free_skb;
391
392 spin_lock_bh(&rx_ring->idr_lock);
393 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 spin_unlock_bh(&rx_ring->idr_lock);
396 if (buf_id <= 0)
397 goto fail_dma_unmap;
398
399 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 if (!desc)
401 goto fail_idr_remove;
402
403 ATH11K_SKB_RXCB(skb)->paddr = paddr;
404
405 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407
408 num_remain--;
409
410 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 }
412
413 ath11k_hal_srng_access_end(ab, srng);
414
415 spin_unlock_bh(&srng->lock);
416
417 return req_entries - num_remain;
418
419 fail_idr_remove:
420 spin_lock_bh(&rx_ring->idr_lock);
421 idr_remove(&rx_ring->bufs_idr, buf_id);
422 spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 DMA_FROM_DEVICE);
426 fail_free_skb:
427 dev_kfree_skb_any(skb);
428
429 ath11k_hal_srng_access_end(ab, srng);
430
431 spin_unlock_bh(&srng->lock);
432
433 return req_entries - num_remain;
434 }
435
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring)
438 {
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 return 0;
457 }
458
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 struct ath11k_pdev_dp *dp = &ar->dp;
462 struct ath11k_base *ab = ar->ab;
463 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 int i;
465
466 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467
468 rx_ring = &dp->rxdma_mon_buf_ring;
469 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470
471 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
472 rx_ring = &dp->rx_mon_status_refill_ring[i];
473 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 }
475
476 return 0;
477 }
478
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 struct dp_rxdma_ring *rx_ring,
481 u32 ringtype)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 int num_entries;
485
486 num_entries = rx_ring->refill_buf_ring.size /
487 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488
489 rx_ring->bufs_max = num_entries;
490 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 ar->ab->hw_params.hal_params->rx_buf_rbm);
492 return 0;
493 }
494
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 struct ath11k_pdev_dp *dp = &ar->dp;
498 struct ath11k_base *ab = ar->ab;
499 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 int i;
501
502 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503
504 if (ar->ab->hw_params.rxdma1_enable) {
505 rx_ring = &dp->rxdma_mon_buf_ring;
506 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 }
508
509 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
510 rx_ring = &dp->rx_mon_status_refill_ring[i];
511 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 }
513
514 return 0;
515 }
516
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 int i;
522
523 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524
525 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
526 if (ab->hw_params.rx_mac_buf_ring)
527 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528
529 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 ath11k_dp_srng_cleanup(ab,
531 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 }
533
534 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 struct ath11k_dp *dp = &ab->dp;
540 int i;
541
542 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 struct ath11k_dp *dp = &ab->dp;
549 int ret;
550 int i;
551
552 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 HAL_REO_DST, i, 0,
555 DP_REO_DST_RING_SIZE);
556 if (ret) {
557 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 goto err_reo_cleanup;
559 }
560 }
561
562 return 0;
563
564 err_reo_cleanup:
565 ath11k_dp_pdev_reo_cleanup(ab);
566
567 return ret;
568 }
569
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 struct ath11k_pdev_dp *dp = &ar->dp;
573 struct ath11k_base *ab = ar->ab;
574 struct dp_srng *srng = NULL;
575 int i;
576 int ret;
577
578 ret = ath11k_dp_srng_setup(ar->ab,
579 &dp->rx_refill_buf_ring.refill_buf_ring,
580 HAL_RXDMA_BUF, 0,
581 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 if (ret) {
583 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 return ret;
585 }
586
587 if (ar->ab->hw_params.rx_mac_buf_ring) {
588 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
589 ret = ath11k_dp_srng_setup(ar->ab,
590 &dp->rx_mac_buf_ring[i],
591 HAL_RXDMA_BUF, 1,
592 dp->mac_id + i, 1024);
593 if (ret) {
594 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 i);
596 return ret;
597 }
598 }
599 }
600
601 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
602 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 HAL_RXDMA_DST, 0, dp->mac_id + i,
604 DP_RXDMA_ERR_DST_RING_SIZE);
605 if (ret) {
606 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 return ret;
608 }
609 }
610
611 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
612 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 ret = ath11k_dp_srng_setup(ar->ab,
614 srng,
615 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 DP_RXDMA_MON_STATUS_RING_SIZE);
617 if (ret) {
618 ath11k_warn(ar->ab,
619 "failed to setup rx_mon_status_refill_ring %d\n", i);
620 return ret;
621 }
622 }
623
624 /* if rxdma1_enable is false, then it doesn't need
625 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 * and rxdma_mon_desc_ring.
627 * init reap timer for QCA6390.
628 */
629 if (!ar->ab->hw_params.rxdma1_enable) {
630 //init mon status buffer reap timer
631 timer_setup(&ar->ab->mon_reap_timer,
632 ath11k_dp_service_mon_ring, 0);
633 return 0;
634 }
635
636 ret = ath11k_dp_srng_setup(ar->ab,
637 &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 if (ret) {
641 ath11k_warn(ar->ab,
642 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 return ret;
644 }
645
646 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 DP_RXDMA_MONITOR_DST_RING_SIZE);
649 if (ret) {
650 ath11k_warn(ar->ab,
651 "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 return ret;
653 }
654
655 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 if (ret) {
659 ath11k_warn(ar->ab,
660 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 struct ath11k_dp *dp = &ab->dp;
670 struct dp_reo_cmd *cmd, *tmp;
671 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 struct dp_rx_tid *rx_tid;
673
674 spin_lock_bh(&dp->reo_cmd_lock);
675 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 list_del(&cmd->list);
677 rx_tid = &cmd->data;
678 if (rx_tid->vaddr_unaligned) {
679 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
680 rx_tid->vaddr_unaligned,
681 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
682 rx_tid->vaddr_unaligned = NULL;
683 }
684 kfree(cmd);
685 }
686
687 list_for_each_entry_safe(cmd_cache, tmp_cache,
688 &dp->reo_cmd_cache_flush_list, list) {
689 list_del(&cmd_cache->list);
690 dp->reo_cmd_cache_flush_count--;
691 rx_tid = &cmd_cache->data;
692 if (rx_tid->vaddr_unaligned) {
693 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
694 rx_tid->vaddr_unaligned,
695 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
696 rx_tid->vaddr_unaligned = NULL;
697 }
698 kfree(cmd_cache);
699 }
700 spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 enum hal_reo_cmd_status status)
705 {
706 struct dp_rx_tid *rx_tid = ctx;
707
708 if (status != HAL_REO_CMD_SUCCESS)
709 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 rx_tid->tid, status);
711 if (rx_tid->vaddr_unaligned) {
712 dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
713 rx_tid->vaddr_unaligned,
714 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
715 rx_tid->vaddr_unaligned = NULL;
716 }
717 }
718
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 struct dp_rx_tid *rx_tid)
721 {
722 struct ath11k_hal_reo_cmd cmd = {};
723 unsigned long tot_desc_sz, desc_sz;
724 int ret;
725
726 tot_desc_sz = rx_tid->size;
727 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728
729 while (tot_desc_sz > desc_sz) {
730 tot_desc_sz -= desc_sz;
731 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 NULL);
736 if (ret)
737 ath11k_warn(ab,
738 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 rx_tid->tid, ret);
740 }
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 HAL_REO_CMD_FLUSH_CACHE,
748 &cmd, ath11k_dp_reo_cmd_free);
749 if (ret) {
750 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 rx_tid->tid, ret);
752 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
753 rx_tid->vaddr_unaligned,
754 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
755 rx_tid->vaddr_unaligned = NULL;
756 }
757 }
758
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 enum hal_reo_cmd_status status)
761 {
762 struct ath11k_base *ab = dp->ab;
763 struct dp_rx_tid *rx_tid = ctx;
764 struct dp_reo_cache_flush_elem *elem, *tmp;
765
766 if (status == HAL_REO_CMD_DRAIN) {
767 goto free_desc;
768 } else if (status != HAL_REO_CMD_SUCCESS) {
769 /* Shouldn't happen! Cleanup in case of other failure? */
770 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 rx_tid->tid, status);
772 return;
773 }
774
775 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
776 if (!elem)
777 goto free_desc;
778
779 elem->ts = jiffies;
780 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781
782 spin_lock_bh(&dp->reo_cmd_lock);
783 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 dp->reo_cmd_cache_flush_count++;
785
786 /* Flush and invalidate aged REO desc from HW cache */
787 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 list) {
789 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 time_after(jiffies, elem->ts +
791 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 list_del(&elem->list);
793 dp->reo_cmd_cache_flush_count--;
794 spin_unlock_bh(&dp->reo_cmd_lock);
795
796 ath11k_dp_reo_cache_flush(ab, &elem->data);
797 kfree(elem);
798 spin_lock_bh(&dp->reo_cmd_lock);
799 }
800 }
801 spin_unlock_bh(&dp->reo_cmd_lock);
802
803 return;
804 free_desc:
805 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
806 rx_tid->vaddr_unaligned,
807 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
808 rx_tid->vaddr_unaligned = NULL;
809 }
810
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 struct ath11k_peer *peer, u8 tid)
813 {
814 struct ath11k_hal_reo_cmd cmd = {};
815 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 int ret;
817
818 if (!rx_tid->active)
819 return;
820
821 rx_tid->active = false;
822
823 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 ath11k_dp_rx_tid_del_func);
830 if (ret) {
831 if (ret != -ESHUTDOWN)
832 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 tid, ret);
834 dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
835 rx_tid->vaddr_unaligned,
836 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
837 rx_tid->vaddr_unaligned = NULL;
838 }
839
840 rx_tid->paddr = 0;
841 rx_tid->paddr_unaligned = 0;
842 rx_tid->size = 0;
843 rx_tid->unaligned_size = 0;
844 }
845
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)846 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
847 u32 *link_desc,
848 enum hal_wbm_rel_bm_act action)
849 {
850 struct ath11k_dp *dp = &ab->dp;
851 struct hal_srng *srng;
852 u32 *desc;
853 int ret = 0;
854
855 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
856
857 spin_lock_bh(&srng->lock);
858
859 ath11k_hal_srng_access_begin(ab, srng);
860
861 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
862 if (!desc) {
863 ret = -ENOBUFS;
864 goto exit;
865 }
866
867 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
868 action);
869
870 exit:
871 ath11k_hal_srng_access_end(ab, srng);
872
873 spin_unlock_bh(&srng->lock);
874
875 return ret;
876 }
877
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)878 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
879 {
880 struct ath11k_base *ab = rx_tid->ab;
881
882 lockdep_assert_held(&ab->base_lock);
883
884 if (rx_tid->dst_ring_desc) {
885 if (rel_link_desc)
886 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
887 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
888 kfree(rx_tid->dst_ring_desc);
889 rx_tid->dst_ring_desc = NULL;
890 }
891
892 rx_tid->cur_sn = 0;
893 rx_tid->last_frag_no = 0;
894 rx_tid->rx_frag_bitmap = 0;
895 __skb_queue_purge(&rx_tid->rx_frags);
896 }
897
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)898 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
899 {
900 struct dp_rx_tid *rx_tid;
901 int i;
902
903 lockdep_assert_held(&ar->ab->base_lock);
904
905 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
906 rx_tid = &peer->rx_tid[i];
907
908 spin_unlock_bh(&ar->ab->base_lock);
909 timer_delete_sync(&rx_tid->frag_timer);
910 spin_lock_bh(&ar->ab->base_lock);
911
912 ath11k_dp_rx_frags_cleanup(rx_tid, true);
913 }
914 }
915
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)916 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
917 {
918 struct dp_rx_tid *rx_tid;
919 int i;
920
921 lockdep_assert_held(&ar->ab->base_lock);
922
923 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
924 rx_tid = &peer->rx_tid[i];
925
926 ath11k_peer_rx_tid_delete(ar, peer, i);
927 ath11k_dp_rx_frags_cleanup(rx_tid, true);
928
929 spin_unlock_bh(&ar->ab->base_lock);
930 timer_delete_sync(&rx_tid->frag_timer);
931 spin_lock_bh(&ar->ab->base_lock);
932 }
933 }
934
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)935 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
936 struct ath11k_peer *peer,
937 struct dp_rx_tid *rx_tid,
938 u32 ba_win_sz, u16 ssn,
939 bool update_ssn)
940 {
941 struct ath11k_hal_reo_cmd cmd = {};
942 int ret;
943
944 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
945 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
946 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
947 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
948 cmd.ba_window_size = ba_win_sz;
949
950 if (update_ssn) {
951 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
952 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
953 }
954
955 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
956 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
957 NULL);
958 if (ret) {
959 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
960 rx_tid->tid, ret);
961 return ret;
962 }
963
964 rx_tid->ba_win_sz = ba_win_sz;
965
966 return 0;
967 }
968
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)969 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
970 const u8 *peer_mac, int vdev_id, u8 tid)
971 {
972 struct ath11k_peer *peer;
973 struct dp_rx_tid *rx_tid;
974
975 spin_lock_bh(&ab->base_lock);
976
977 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
978 if (!peer) {
979 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
980 goto unlock_exit;
981 }
982
983 rx_tid = &peer->rx_tid[tid];
984 if (!rx_tid->active)
985 goto unlock_exit;
986
987 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
988 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
989 rx_tid->vaddr_unaligned = NULL;
990
991 rx_tid->active = false;
992
993 unlock_exit:
994 spin_unlock_bh(&ab->base_lock);
995 }
996
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)997 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
998 u8 tid, u32 ba_win_sz, u16 ssn,
999 enum hal_pn_type pn_type)
1000 {
1001 struct ath11k_base *ab = ar->ab;
1002 struct ath11k_peer *peer;
1003 struct dp_rx_tid *rx_tid;
1004 u32 hw_desc_sz, *vaddr;
1005 void *vaddr_unaligned;
1006 dma_addr_t paddr;
1007 int ret;
1008
1009 spin_lock_bh(&ab->base_lock);
1010
1011 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 if (!peer) {
1013 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 peer_mac);
1015 spin_unlock_bh(&ab->base_lock);
1016 return -ENOENT;
1017 }
1018
1019 rx_tid = &peer->rx_tid[tid];
1020 /* Update the tid queue if it is already setup */
1021 if (rx_tid->active) {
1022 paddr = rx_tid->paddr;
1023 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 ba_win_sz, ssn, true);
1025 spin_unlock_bh(&ab->base_lock);
1026 if (ret) {
1027 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 peer_mac, tid, ret);
1029 return ret;
1030 }
1031
1032 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 peer_mac, paddr,
1034 tid, 1, ba_win_sz);
1035 if (ret)
1036 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 peer_mac, tid, ret);
1038 return ret;
1039 }
1040
1041 rx_tid->tid = tid;
1042
1043 rx_tid->ba_win_sz = ba_win_sz;
1044
1045 /* TODO: Optimize the memory allocation for qos tid based on
1046 * the actual BA window size in REO tid update path.
1047 */
1048 if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 else
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052
1053 rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
1054 vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
1055 DMA_BIDIRECTIONAL, GFP_ATOMIC);
1056 if (!vaddr_unaligned) {
1057 spin_unlock_bh(&ab->base_lock);
1058 return -ENOMEM;
1059 }
1060
1061 rx_tid->vaddr_unaligned = vaddr_unaligned;
1062 vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
1063 rx_tid->paddr_unaligned = paddr;
1064 rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
1065 (unsigned long)rx_tid->vaddr_unaligned);
1066 ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
1067 rx_tid->size = hw_desc_sz;
1068 rx_tid->active = true;
1069
1070 /* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
1071 * Since these changes are not reflected in the device, driver now needs to
1072 * explicitly call dma_sync_single_for_device.
1073 */
1074 dma_sync_single_for_device(ab->dev, rx_tid->paddr,
1075 rx_tid->size,
1076 DMA_TO_DEVICE);
1077 spin_unlock_bh(&ab->base_lock);
1078
1079 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
1080 tid, 1, ba_win_sz);
1081 if (ret) {
1082 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1083 peer_mac, tid, ret);
1084 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1085 }
1086
1087 return ret;
1088 }
1089
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 struct ieee80211_ampdu_params *params)
1092 {
1093 struct ath11k_base *ab = ar->ab;
1094 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1095 int vdev_id = arsta->arvif->vdev_id;
1096 int ret;
1097
1098 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 params->tid, params->buf_size,
1100 params->ssn, arsta->pn_type);
1101 if (ret)
1102 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103
1104 return ret;
1105 }
1106
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 struct ieee80211_ampdu_params *params)
1109 {
1110 struct ath11k_base *ab = ar->ab;
1111 struct ath11k_peer *peer;
1112 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1113 int vdev_id = arsta->arvif->vdev_id;
1114 dma_addr_t paddr;
1115 bool active;
1116 int ret;
1117
1118 spin_lock_bh(&ab->base_lock);
1119
1120 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1121 if (!peer) {
1122 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1123 spin_unlock_bh(&ab->base_lock);
1124 return -ENOENT;
1125 }
1126
1127 paddr = peer->rx_tid[params->tid].paddr;
1128 active = peer->rx_tid[params->tid].active;
1129
1130 if (!active) {
1131 spin_unlock_bh(&ab->base_lock);
1132 return 0;
1133 }
1134
1135 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1136 spin_unlock_bh(&ab->base_lock);
1137 if (ret) {
1138 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1139 params->tid, ret);
1140 return ret;
1141 }
1142
1143 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1144 params->sta->addr, paddr,
1145 params->tid, 1, 1);
1146 if (ret)
1147 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1148 ret);
1149
1150 return ret;
1151 }
1152
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1153 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1154 const u8 *peer_addr,
1155 enum set_key_cmd key_cmd,
1156 struct ieee80211_key_conf *key)
1157 {
1158 struct ath11k *ar = arvif->ar;
1159 struct ath11k_base *ab = ar->ab;
1160 struct ath11k_hal_reo_cmd cmd = {};
1161 struct ath11k_peer *peer;
1162 struct dp_rx_tid *rx_tid;
1163 u8 tid;
1164 int ret = 0;
1165
1166 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1167 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1168 * for now.
1169 */
1170 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1171 return 0;
1172
1173 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1174 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1175 HAL_REO_CMD_UPD0_PN_SIZE |
1176 HAL_REO_CMD_UPD0_PN_VALID |
1177 HAL_REO_CMD_UPD0_PN_CHECK |
1178 HAL_REO_CMD_UPD0_SVLD;
1179
1180 switch (key->cipher) {
1181 case WLAN_CIPHER_SUITE_TKIP:
1182 case WLAN_CIPHER_SUITE_CCMP:
1183 case WLAN_CIPHER_SUITE_CCMP_256:
1184 case WLAN_CIPHER_SUITE_GCMP:
1185 case WLAN_CIPHER_SUITE_GCMP_256:
1186 if (key_cmd == SET_KEY) {
1187 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1188 cmd.pn_size = 48;
1189 }
1190 break;
1191 default:
1192 break;
1193 }
1194
1195 spin_lock_bh(&ab->base_lock);
1196
1197 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1198 if (!peer) {
1199 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1200 spin_unlock_bh(&ab->base_lock);
1201 return -ENOENT;
1202 }
1203
1204 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1205 rx_tid = &peer->rx_tid[tid];
1206 if (!rx_tid->active)
1207 continue;
1208 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1209 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1210 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1211 HAL_REO_CMD_UPDATE_RX_QUEUE,
1212 &cmd, NULL);
1213 if (ret) {
1214 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1215 tid, ret);
1216 break;
1217 }
1218 }
1219
1220 spin_unlock_bh(&ab->base_lock);
1221
1222 return ret;
1223 }
1224
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1225 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1226 u16 peer_id)
1227 {
1228 int i;
1229
1230 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1231 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1232 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1233 return i;
1234 } else {
1235 return i;
1236 }
1237 }
1238
1239 return -EINVAL;
1240 }
1241
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1242 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1243 u16 tag, u16 len, const void *ptr,
1244 void *data)
1245 {
1246 struct htt_ppdu_stats_info *ppdu_info;
1247 struct htt_ppdu_user_stats *user_stats;
1248 int cur_user;
1249 u16 peer_id;
1250
1251 ppdu_info = data;
1252
1253 switch (tag) {
1254 case HTT_PPDU_STATS_TAG_COMMON:
1255 if (len < sizeof(struct htt_ppdu_stats_common)) {
1256 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1257 len, tag);
1258 return -EINVAL;
1259 }
1260 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1261 sizeof(struct htt_ppdu_stats_common));
1262 break;
1263 case HTT_PPDU_STATS_TAG_USR_RATE:
1264 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1265 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1266 len, tag);
1267 return -EINVAL;
1268 }
1269
1270 #if defined(__linux__)
1271 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1272 #elif defined(__FreeBSD__)
1273 peer_id = ((const struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1274 #endif
1275 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1276 peer_id);
1277 if (cur_user < 0)
1278 return -EINVAL;
1279 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1280 user_stats->peer_id = peer_id;
1281 user_stats->is_valid_peer_id = true;
1282 memcpy((void *)&user_stats->rate, ptr,
1283 sizeof(struct htt_ppdu_stats_user_rate));
1284 user_stats->tlv_flags |= BIT(tag);
1285 break;
1286 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1287 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1288 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1289 len, tag);
1290 return -EINVAL;
1291 }
1292
1293 #if defined(__linux__)
1294 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1295 #elif defined(__FreeBSD__)
1296 peer_id = ((const struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1297 #endif
1298 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1299 peer_id);
1300 if (cur_user < 0)
1301 return -EINVAL;
1302 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1303 user_stats->peer_id = peer_id;
1304 user_stats->is_valid_peer_id = true;
1305 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1306 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1307 user_stats->tlv_flags |= BIT(tag);
1308 break;
1309 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1310 if (len <
1311 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1312 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1313 len, tag);
1314 return -EINVAL;
1315 }
1316
1317 peer_id =
1318 #if defined(__linux__)
1319 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1320 #elif defined(__FreeBSD__)
1321 ((const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1322 #endif
1323 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1324 peer_id);
1325 if (cur_user < 0)
1326 return -EINVAL;
1327 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1328 user_stats->peer_id = peer_id;
1329 user_stats->is_valid_peer_id = true;
1330 memcpy((void *)&user_stats->ack_ba, ptr,
1331 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1332 user_stats->tlv_flags |= BIT(tag);
1333 break;
1334 }
1335 return 0;
1336 }
1337
1338 #if defined(__linux__)
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1339 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1340 #elif defined(__FreeBSD__)
1341 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const u8 *ptr, size_t len,
1342 #endif
1343 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1344 const void *ptr, void *data),
1345 void *data)
1346 {
1347 const struct htt_tlv *tlv;
1348 #if defined(__linux__)
1349 const void *begin = ptr;
1350 #elif defined(__FreeBSD__)
1351 const u8 *begin = ptr;
1352 #endif
1353 u16 tlv_tag, tlv_len;
1354 int ret = -EINVAL;
1355
1356 while (len > 0) {
1357 if (len < sizeof(*tlv)) {
1358 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1359 ptr - begin, len, sizeof(*tlv));
1360 return -EINVAL;
1361 }
1362 #if defined(__linux__)
1363 tlv = (struct htt_tlv *)ptr;
1364 #elif defined(__FreeBSD__)
1365 tlv = (const struct htt_tlv *)(const void *)ptr;
1366 #endif
1367 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1368 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1369 ptr += sizeof(*tlv);
1370 len -= sizeof(*tlv);
1371
1372 if (tlv_len > len) {
1373 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1374 tlv_tag, ptr - begin, len, tlv_len);
1375 return -EINVAL;
1376 }
1377 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1378 if (ret == -ENOMEM)
1379 return ret;
1380
1381 ptr += tlv_len;
1382 len -= tlv_len;
1383 }
1384 return 0;
1385 }
1386
1387 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1388 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1389 struct htt_ppdu_stats *ppdu_stats, u8 user)
1390 {
1391 struct ath11k_base *ab = ar->ab;
1392 struct ath11k_peer *peer;
1393 struct ieee80211_sta *sta;
1394 struct ath11k_sta *arsta;
1395 struct htt_ppdu_stats_user_rate *user_rate;
1396 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1397 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1398 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1399 int ret;
1400 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1401 u32 succ_bytes = 0;
1402 u16 rate = 0, succ_pkts = 0;
1403 u32 tx_duration = 0;
1404 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1405 bool is_ampdu = false;
1406
1407 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1408 return;
1409
1410 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1411 is_ampdu =
1412 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1413
1414 if (usr_stats->tlv_flags &
1415 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1416 succ_bytes = usr_stats->ack_ba.success_bytes;
1417 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1418 usr_stats->ack_ba.info);
1419 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1420 usr_stats->ack_ba.info);
1421 }
1422
1423 if (common->fes_duration_us)
1424 tx_duration = common->fes_duration_us;
1425
1426 user_rate = &usr_stats->rate;
1427 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1428 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1429 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1430 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1431 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1432 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1433
1434 /* Note: If host configured fixed rates and in some other special
1435 * cases, the broadcast/management frames are sent in different rates.
1436 * Firmware rate's control to be skipped for this?
1437 */
1438
1439 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1440 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1441 return;
1442 }
1443
1444 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1445 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1446 return;
1447 }
1448
1449 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1450 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1451 mcs, nss);
1452 return;
1453 }
1454
1455 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1456 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1457 flags,
1458 &rate_idx,
1459 &rate);
1460 if (ret < 0)
1461 return;
1462 }
1463
1464 rcu_read_lock();
1465 spin_lock_bh(&ab->base_lock);
1466 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1467
1468 if (!peer || !peer->sta) {
1469 spin_unlock_bh(&ab->base_lock);
1470 rcu_read_unlock();
1471 return;
1472 }
1473
1474 sta = peer->sta;
1475 arsta = ath11k_sta_to_arsta(sta);
1476
1477 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1478
1479 switch (flags) {
1480 case WMI_RATE_PREAMBLE_OFDM:
1481 arsta->txrate.legacy = rate;
1482 break;
1483 case WMI_RATE_PREAMBLE_CCK:
1484 arsta->txrate.legacy = rate;
1485 break;
1486 case WMI_RATE_PREAMBLE_HT:
1487 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1488 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1489 if (sgi)
1490 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1491 break;
1492 case WMI_RATE_PREAMBLE_VHT:
1493 arsta->txrate.mcs = mcs;
1494 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1495 if (sgi)
1496 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1497 break;
1498 case WMI_RATE_PREAMBLE_HE:
1499 arsta->txrate.mcs = mcs;
1500 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1501 arsta->txrate.he_dcm = dcm;
1502 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1503 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1504 ((user_rate->ru_end -
1505 user_rate->ru_start) + 1);
1506 break;
1507 }
1508
1509 arsta->txrate.nss = nss;
1510
1511 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1512 arsta->tx_duration += tx_duration;
1513 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1514
1515 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1516 * So skip peer stats update for mgmt packets.
1517 */
1518 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1519 memset(peer_stats, 0, sizeof(*peer_stats));
1520 peer_stats->succ_pkts = succ_pkts;
1521 peer_stats->succ_bytes = succ_bytes;
1522 peer_stats->is_ampdu = is_ampdu;
1523 peer_stats->duration = tx_duration;
1524 peer_stats->ba_fails =
1525 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1526 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1527
1528 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1529 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1530 }
1531
1532 spin_unlock_bh(&ab->base_lock);
1533 rcu_read_unlock();
1534 }
1535
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1536 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1537 struct htt_ppdu_stats *ppdu_stats)
1538 {
1539 u8 user;
1540
1541 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1542 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1543 }
1544
1545 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1546 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1547 u32 ppdu_id)
1548 {
1549 struct htt_ppdu_stats_info *ppdu_info;
1550
1551 lockdep_assert_held(&ar->data_lock);
1552
1553 if (!list_empty(&ar->ppdu_stats_info)) {
1554 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1555 if (ppdu_info->ppdu_id == ppdu_id)
1556 return ppdu_info;
1557 }
1558
1559 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1560 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1561 typeof(*ppdu_info), list);
1562 list_del(&ppdu_info->list);
1563 ar->ppdu_stat_list_depth--;
1564 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1565 kfree(ppdu_info);
1566 }
1567 }
1568
1569 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1570 if (!ppdu_info)
1571 return NULL;
1572
1573 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1574 ar->ppdu_stat_list_depth++;
1575
1576 return ppdu_info;
1577 }
1578
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1579 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1580 struct sk_buff *skb)
1581 {
1582 struct ath11k_htt_ppdu_stats_msg *msg;
1583 struct htt_ppdu_stats_info *ppdu_info;
1584 struct ath11k *ar;
1585 int ret;
1586 u8 pdev_id;
1587 u32 ppdu_id, len;
1588
1589 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1590 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1591 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1592 ppdu_id = msg->ppdu_id;
1593
1594 rcu_read_lock();
1595 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1596 if (!ar) {
1597 ret = -EINVAL;
1598 goto out;
1599 }
1600
1601 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1602 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1603
1604 spin_lock_bh(&ar->data_lock);
1605 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1606 if (!ppdu_info) {
1607 ret = -EINVAL;
1608 goto out_unlock_data;
1609 }
1610
1611 ppdu_info->ppdu_id = ppdu_id;
1612 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1613 ath11k_htt_tlv_ppdu_stats_parse,
1614 (void *)ppdu_info);
1615 if (ret) {
1616 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1617 goto out_unlock_data;
1618 }
1619
1620 out_unlock_data:
1621 spin_unlock_bh(&ar->data_lock);
1622
1623 out:
1624 rcu_read_unlock();
1625
1626 return ret;
1627 }
1628
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1629 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1630 {
1631 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1632 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1633 struct ath11k *ar;
1634 u8 pdev_id;
1635
1636 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1637
1638 rcu_read_lock();
1639
1640 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1641 if (!ar) {
1642 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1643 goto out;
1644 }
1645
1646 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1647 ar->ab->pktlog_defs_checksum);
1648
1649 out:
1650 rcu_read_unlock();
1651 }
1652
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1653 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1654 struct sk_buff *skb)
1655 {
1656 u32 *data = (u32 *)skb->data;
1657 u8 pdev_id, ring_type, ring_id, pdev_idx;
1658 u16 hp, tp;
1659 u32 backpressure_time;
1660 struct ath11k_bp_stats *bp_stats;
1661
1662 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1663 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1664 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1665 ++data;
1666
1667 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1668 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1669 ++data;
1670
1671 backpressure_time = *data;
1672
1673 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1674 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1675
1676 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1677 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1678 return;
1679
1680 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1681 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1682 pdev_idx = DP_HW2SW_MACID(pdev_id);
1683
1684 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1685 return;
1686
1687 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1688 } else {
1689 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1690 ring_type);
1691 return;
1692 }
1693
1694 spin_lock_bh(&ab->base_lock);
1695 bp_stats->hp = hp;
1696 bp_stats->tp = tp;
1697 bp_stats->count++;
1698 bp_stats->jiffies = jiffies;
1699 spin_unlock_bh(&ab->base_lock);
1700 }
1701
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1702 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1703 struct sk_buff *skb)
1704 {
1705 struct ath11k_dp *dp = &ab->dp;
1706 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1707 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1708 u16 peer_id;
1709 u8 vdev_id;
1710 u8 mac_addr[ETH_ALEN];
1711 u16 peer_mac_h16;
1712 u16 ast_hash;
1713 u16 hw_peer_id;
1714
1715 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1716
1717 switch (type) {
1718 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1719 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1720 resp->version_msg.version);
1721 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1722 resp->version_msg.version);
1723 complete(&dp->htt_tgt_version_received);
1724 break;
1725 case HTT_T2H_MSG_TYPE_PEER_MAP:
1726 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1727 resp->peer_map_ev.info);
1728 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1729 resp->peer_map_ev.info);
1730 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1731 resp->peer_map_ev.info1);
1732 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1733 peer_mac_h16, mac_addr);
1734 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1735 break;
1736 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1737 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1738 resp->peer_map_ev.info);
1739 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1740 resp->peer_map_ev.info);
1741 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1742 resp->peer_map_ev.info1);
1743 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1744 peer_mac_h16, mac_addr);
1745 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1746 resp->peer_map_ev.info2);
1747 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1748 resp->peer_map_ev.info1);
1749 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1750 hw_peer_id);
1751 break;
1752 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1753 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1754 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1755 resp->peer_unmap_ev.info);
1756 ath11k_peer_unmap_event(ab, peer_id);
1757 break;
1758 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1759 ath11k_htt_pull_ppdu_stats(ab, skb);
1760 break;
1761 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1762 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1763 break;
1764 case HTT_T2H_MSG_TYPE_PKTLOG:
1765 ath11k_htt_pktlog(ab, skb);
1766 break;
1767 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1768 ath11k_htt_backpressure_event_handler(ab, skb);
1769 break;
1770 default:
1771 ath11k_warn(ab, "htt event %d not handled\n", type);
1772 break;
1773 }
1774
1775 dev_kfree_skb_any(skb);
1776 }
1777
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1778 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1779 struct sk_buff_head *msdu_list,
1780 struct sk_buff *first, struct sk_buff *last,
1781 u8 l3pad_bytes, int msdu_len)
1782 {
1783 struct ath11k_base *ab = ar->ab;
1784 struct sk_buff *skb;
1785 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1786 int buf_first_hdr_len, buf_first_len;
1787 struct hal_rx_desc *ldesc;
1788 int space_extra, rem_len, buf_len;
1789 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1790
1791 /* As the msdu is spread across multiple rx buffers,
1792 * find the offset to the start of msdu for computing
1793 * the length of the msdu in the first buffer.
1794 */
1795 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1796 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1797
1798 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1799 skb_put(first, buf_first_hdr_len + msdu_len);
1800 skb_pull(first, buf_first_hdr_len);
1801 return 0;
1802 }
1803
1804 ldesc = (struct hal_rx_desc *)last->data;
1805 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1806 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1807
1808 /* MSDU spans over multiple buffers because the length of the MSDU
1809 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1810 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1811 */
1812 skb_put(first, DP_RX_BUFFER_SIZE);
1813 skb_pull(first, buf_first_hdr_len);
1814
1815 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1816 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1817 */
1818 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1819
1820 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1821 if (space_extra > 0 &&
1822 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1823 /* Free up all buffers of the MSDU */
1824 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1825 rxcb = ATH11K_SKB_RXCB(skb);
1826 if (!rxcb->is_continuation) {
1827 dev_kfree_skb_any(skb);
1828 break;
1829 }
1830 dev_kfree_skb_any(skb);
1831 }
1832 return -ENOMEM;
1833 }
1834
1835 rem_len = msdu_len - buf_first_len;
1836 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1837 rxcb = ATH11K_SKB_RXCB(skb);
1838 if (rxcb->is_continuation)
1839 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1840 else
1841 buf_len = rem_len;
1842
1843 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1844 WARN_ON_ONCE(1);
1845 dev_kfree_skb_any(skb);
1846 return -EINVAL;
1847 }
1848
1849 skb_put(skb, buf_len + hal_rx_desc_sz);
1850 skb_pull(skb, hal_rx_desc_sz);
1851 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1852 buf_len);
1853 dev_kfree_skb_any(skb);
1854
1855 rem_len -= buf_len;
1856 if (!rxcb->is_continuation)
1857 break;
1858 }
1859
1860 return 0;
1861 }
1862
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1863 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1864 struct sk_buff *first)
1865 {
1866 struct sk_buff *skb;
1867 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1868
1869 if (!rxcb->is_continuation)
1870 return first;
1871
1872 skb_queue_walk(msdu_list, skb) {
1873 rxcb = ATH11K_SKB_RXCB(skb);
1874 if (!rxcb->is_continuation)
1875 return skb;
1876 }
1877
1878 return NULL;
1879 }
1880
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1881 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1882 {
1883 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1884 struct rx_attention *rx_attention;
1885 bool ip_csum_fail, l4_csum_fail;
1886
1887 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1888 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1889 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1890
1891 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1892 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1893 }
1894
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1895 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1896 {
1897 switch (enctype) {
1898 case HAL_ENCRYPT_TYPE_OPEN:
1899 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1900 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1901 return 0;
1902 case HAL_ENCRYPT_TYPE_CCMP_128:
1903 return IEEE80211_CCMP_MIC_LEN;
1904 case HAL_ENCRYPT_TYPE_CCMP_256:
1905 return IEEE80211_CCMP_256_MIC_LEN;
1906 case HAL_ENCRYPT_TYPE_GCMP_128:
1907 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1908 return IEEE80211_GCMP_MIC_LEN;
1909 case HAL_ENCRYPT_TYPE_WEP_40:
1910 case HAL_ENCRYPT_TYPE_WEP_104:
1911 case HAL_ENCRYPT_TYPE_WEP_128:
1912 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1913 case HAL_ENCRYPT_TYPE_WAPI:
1914 break;
1915 }
1916
1917 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1918 return 0;
1919 }
1920
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1921 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1922 enum hal_encrypt_type enctype)
1923 {
1924 switch (enctype) {
1925 case HAL_ENCRYPT_TYPE_OPEN:
1926 return 0;
1927 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1928 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1929 return IEEE80211_TKIP_IV_LEN;
1930 case HAL_ENCRYPT_TYPE_CCMP_128:
1931 return IEEE80211_CCMP_HDR_LEN;
1932 case HAL_ENCRYPT_TYPE_CCMP_256:
1933 return IEEE80211_CCMP_256_HDR_LEN;
1934 case HAL_ENCRYPT_TYPE_GCMP_128:
1935 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1936 return IEEE80211_GCMP_HDR_LEN;
1937 case HAL_ENCRYPT_TYPE_WEP_40:
1938 case HAL_ENCRYPT_TYPE_WEP_104:
1939 case HAL_ENCRYPT_TYPE_WEP_128:
1940 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1941 case HAL_ENCRYPT_TYPE_WAPI:
1942 break;
1943 }
1944
1945 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1946 return 0;
1947 }
1948
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1949 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1950 enum hal_encrypt_type enctype)
1951 {
1952 switch (enctype) {
1953 case HAL_ENCRYPT_TYPE_OPEN:
1954 case HAL_ENCRYPT_TYPE_CCMP_128:
1955 case HAL_ENCRYPT_TYPE_CCMP_256:
1956 case HAL_ENCRYPT_TYPE_GCMP_128:
1957 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1958 return 0;
1959 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1960 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1961 return IEEE80211_TKIP_ICV_LEN;
1962 case HAL_ENCRYPT_TYPE_WEP_40:
1963 case HAL_ENCRYPT_TYPE_WEP_104:
1964 case HAL_ENCRYPT_TYPE_WEP_128:
1965 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1966 case HAL_ENCRYPT_TYPE_WAPI:
1967 break;
1968 }
1969
1970 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1971 return 0;
1972 }
1973
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1974 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1975 struct sk_buff *msdu,
1976 u8 *first_hdr,
1977 enum hal_encrypt_type enctype,
1978 struct ieee80211_rx_status *status)
1979 {
1980 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1981 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1982 struct ieee80211_hdr *hdr;
1983 size_t hdr_len;
1984 u8 da[ETH_ALEN];
1985 u8 sa[ETH_ALEN];
1986 u16 qos_ctl = 0;
1987 u8 *qos;
1988
1989 /* copy SA & DA and pull decapped header */
1990 hdr = (struct ieee80211_hdr *)msdu->data;
1991 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1992 ether_addr_copy(da, ieee80211_get_DA(hdr));
1993 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1994 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1995
1996 if (rxcb->is_first_msdu) {
1997 /* original 802.11 header is valid for the first msdu
1998 * hence we can reuse the same header
1999 */
2000 hdr = (struct ieee80211_hdr *)first_hdr;
2001 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2002
2003 /* Each A-MSDU subframe will be reported as a separate MSDU,
2004 * so strip the A-MSDU bit from QoS Ctl.
2005 */
2006 if (ieee80211_is_data_qos(hdr->frame_control)) {
2007 qos = ieee80211_get_qos_ctl(hdr);
2008 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
2009 }
2010 } else {
2011 /* Rebuild qos header if this is a middle/last msdu */
2012 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
2013
2014 /* Reset the order bit as the HT_Control header is stripped */
2015 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
2016
2017 qos_ctl = rxcb->tid;
2018
2019 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
2020 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
2021
2022 /* TODO Add other QoS ctl fields when required */
2023
2024 /* copy decap header before overwriting for reuse below */
2025 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2026 }
2027
2028 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2029 memcpy(skb_push(msdu,
2030 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2031 #if defined(__linux__)
2032 (void *)hdr + hdr_len,
2033 #elif defined(__FreeBSD__)
2034 (u8 *)hdr + hdr_len,
2035 #endif
2036 ath11k_dp_rx_crypto_param_len(ar, enctype));
2037 }
2038
2039 if (!rxcb->is_first_msdu) {
2040 memcpy(skb_push(msdu,
2041 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2042 IEEE80211_QOS_CTL_LEN);
2043 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2044 return;
2045 }
2046
2047 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2048
2049 /* original 802.11 header has a different DA and in
2050 * case of 4addr it may also have different SA
2051 */
2052 hdr = (struct ieee80211_hdr *)msdu->data;
2053 ether_addr_copy(ieee80211_get_DA(hdr), da);
2054 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2055 }
2056
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2057 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2058 enum hal_encrypt_type enctype,
2059 struct ieee80211_rx_status *status,
2060 bool decrypted)
2061 {
2062 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2063 struct ieee80211_hdr *hdr;
2064 size_t hdr_len;
2065 size_t crypto_len;
2066
2067 if (!rxcb->is_first_msdu ||
2068 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2069 WARN_ON_ONCE(1);
2070 return;
2071 }
2072
2073 skb_trim(msdu, msdu->len - FCS_LEN);
2074
2075 if (!decrypted)
2076 return;
2077
2078 hdr = (void *)msdu->data;
2079
2080 /* Tail */
2081 if (status->flag & RX_FLAG_IV_STRIPPED) {
2082 skb_trim(msdu, msdu->len -
2083 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2084
2085 skb_trim(msdu, msdu->len -
2086 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2087 } else {
2088 /* MIC */
2089 if (status->flag & RX_FLAG_MIC_STRIPPED)
2090 skb_trim(msdu, msdu->len -
2091 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2092
2093 /* ICV */
2094 if (status->flag & RX_FLAG_ICV_STRIPPED)
2095 skb_trim(msdu, msdu->len -
2096 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2097 }
2098
2099 /* MMIC */
2100 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2101 !ieee80211_has_morefrags(hdr->frame_control) &&
2102 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2103 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2104
2105 /* Head */
2106 if (status->flag & RX_FLAG_IV_STRIPPED) {
2107 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2108 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2109
2110 #if defined(__linux__)
2111 memmove((void *)msdu->data + crypto_len,
2112 (void *)msdu->data, hdr_len);
2113 #elif defined(__FreeBSD__)
2114 memmove((u8 *)msdu->data + crypto_len,
2115 (u8 *)msdu->data, hdr_len);
2116 #endif
2117 skb_pull(msdu, crypto_len);
2118 }
2119 }
2120
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2121 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2122 struct sk_buff *msdu,
2123 enum hal_encrypt_type enctype)
2124 {
2125 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2126 struct ieee80211_hdr *hdr;
2127 size_t hdr_len, crypto_len;
2128 #if defined(__linux__)
2129 void *rfc1042;
2130 #elif defined(__FreeBSD__)
2131 u8 *rfc1042;
2132 #endif
2133 bool is_amsdu;
2134
2135 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2136 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2137 #if defined(__linux__)
2138 rfc1042 = hdr;
2139 #elif defined(__FreeBSD__)
2140 rfc1042 = (void *)hdr;
2141 #endif
2142
2143 if (rxcb->is_first_msdu) {
2144 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2145 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2146
2147 rfc1042 += hdr_len + crypto_len;
2148 }
2149
2150 if (is_amsdu)
2151 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2152
2153 return rfc1042;
2154 }
2155
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2156 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2157 struct sk_buff *msdu,
2158 u8 *first_hdr,
2159 enum hal_encrypt_type enctype,
2160 struct ieee80211_rx_status *status)
2161 {
2162 struct ieee80211_hdr *hdr;
2163 struct ethhdr *eth;
2164 size_t hdr_len;
2165 u8 da[ETH_ALEN];
2166 u8 sa[ETH_ALEN];
2167 void *rfc1042;
2168
2169 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2170 if (WARN_ON_ONCE(!rfc1042))
2171 return;
2172
2173 /* pull decapped header and copy SA & DA */
2174 eth = (struct ethhdr *)msdu->data;
2175 ether_addr_copy(da, eth->h_dest);
2176 ether_addr_copy(sa, eth->h_source);
2177 skb_pull(msdu, sizeof(struct ethhdr));
2178
2179 /* push rfc1042/llc/snap */
2180 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2181 sizeof(struct ath11k_dp_rfc1042_hdr));
2182
2183 /* push original 802.11 header */
2184 hdr = (struct ieee80211_hdr *)first_hdr;
2185 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2186
2187 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2188 memcpy(skb_push(msdu,
2189 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2190 #if defined(__linux__)
2191 (void *)hdr + hdr_len,
2192 #elif defined(__FreeBSD__)
2193 (u8 *)hdr + hdr_len,
2194 #endif
2195 ath11k_dp_rx_crypto_param_len(ar, enctype));
2196 }
2197
2198 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2199
2200 /* original 802.11 header has a different DA and in
2201 * case of 4addr it may also have different SA
2202 */
2203 hdr = (struct ieee80211_hdr *)msdu->data;
2204 ether_addr_copy(ieee80211_get_DA(hdr), da);
2205 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2206 }
2207
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2208 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2209 struct hal_rx_desc *rx_desc,
2210 enum hal_encrypt_type enctype,
2211 struct ieee80211_rx_status *status,
2212 bool decrypted)
2213 {
2214 u8 *first_hdr;
2215 u8 decap;
2216 struct ethhdr *ehdr;
2217
2218 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2219 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2220
2221 switch (decap) {
2222 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2223 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2224 enctype, status);
2225 break;
2226 case DP_RX_DECAP_TYPE_RAW:
2227 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2228 decrypted);
2229 break;
2230 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2231 ehdr = (struct ethhdr *)msdu->data;
2232
2233 /* mac80211 allows fast path only for authorized STA */
2234 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2235 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2236 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2237 enctype, status);
2238 break;
2239 }
2240
2241 /* PN for mcast packets will be validated in mac80211;
2242 * remove eth header and add 802.11 header.
2243 */
2244 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2245 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2246 enctype, status);
2247 break;
2248 case DP_RX_DECAP_TYPE_8023:
2249 /* TODO: Handle undecap for these formats */
2250 break;
2251 }
2252 }
2253
2254 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2255 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2256 {
2257 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2258 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2259 struct ath11k_peer *peer = NULL;
2260
2261 lockdep_assert_held(&ab->base_lock);
2262
2263 if (rxcb->peer_id)
2264 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2265
2266 if (peer)
2267 return peer;
2268
2269 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2270 return NULL;
2271
2272 peer = ath11k_peer_find_by_addr(ab,
2273 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2274 return peer;
2275 }
2276
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2277 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2278 struct sk_buff *msdu,
2279 struct hal_rx_desc *rx_desc,
2280 struct ieee80211_rx_status *rx_status)
2281 {
2282 bool fill_crypto_hdr;
2283 enum hal_encrypt_type enctype;
2284 bool is_decrypted = false;
2285 struct ath11k_skb_rxcb *rxcb;
2286 struct ieee80211_hdr *hdr;
2287 struct ath11k_peer *peer;
2288 struct rx_attention *rx_attention;
2289 u32 err_bitmap;
2290
2291 /* PN for multicast packets will be checked in mac80211 */
2292 rxcb = ATH11K_SKB_RXCB(msdu);
2293 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2294 rxcb->is_mcbc = fill_crypto_hdr;
2295
2296 if (rxcb->is_mcbc) {
2297 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2298 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2299 }
2300
2301 spin_lock_bh(&ar->ab->base_lock);
2302 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2303 if (peer) {
2304 if (rxcb->is_mcbc)
2305 enctype = peer->sec_type_grp;
2306 else
2307 enctype = peer->sec_type;
2308 } else {
2309 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2310 }
2311 spin_unlock_bh(&ar->ab->base_lock);
2312
2313 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2314 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2315 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2316 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2317
2318 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2319 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2320 RX_FLAG_MMIC_ERROR |
2321 RX_FLAG_DECRYPTED |
2322 RX_FLAG_IV_STRIPPED |
2323 RX_FLAG_MMIC_STRIPPED);
2324
2325 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2326 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2327 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2328 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2329
2330 if (is_decrypted) {
2331 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2332
2333 if (fill_crypto_hdr)
2334 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2335 RX_FLAG_ICV_STRIPPED;
2336 else
2337 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2338 RX_FLAG_PN_VALIDATED;
2339 }
2340
2341 ath11k_dp_rx_h_csum_offload(ar, msdu);
2342 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2343 enctype, rx_status, is_decrypted);
2344
2345 if (!is_decrypted || fill_crypto_hdr)
2346 return;
2347
2348 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2349 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2350 hdr = (void *)msdu->data;
2351 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2352 }
2353 }
2354
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2355 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2356 struct ieee80211_rx_status *rx_status)
2357 {
2358 struct ieee80211_supported_band *sband;
2359 enum rx_msdu_start_pkt_type pkt_type;
2360 u8 bw;
2361 u8 rate_mcs, nss;
2362 u8 sgi;
2363 bool is_cck, is_ldpc;
2364
2365 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2366 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2367 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2368 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2369 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2370
2371 switch (pkt_type) {
2372 case RX_MSDU_START_PKT_TYPE_11A:
2373 case RX_MSDU_START_PKT_TYPE_11B:
2374 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2375 sband = &ar->mac.sbands[rx_status->band];
2376 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2377 is_cck);
2378 break;
2379 case RX_MSDU_START_PKT_TYPE_11N:
2380 rx_status->encoding = RX_ENC_HT;
2381 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2382 ath11k_warn(ar->ab,
2383 "Received with invalid mcs in HT mode %d\n",
2384 rate_mcs);
2385 break;
2386 }
2387 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2388 if (sgi)
2389 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2390 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2391 break;
2392 case RX_MSDU_START_PKT_TYPE_11AC:
2393 rx_status->encoding = RX_ENC_VHT;
2394 rx_status->rate_idx = rate_mcs;
2395 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2396 ath11k_warn(ar->ab,
2397 "Received with invalid mcs in VHT mode %d\n",
2398 rate_mcs);
2399 break;
2400 }
2401 rx_status->nss = nss;
2402 if (sgi)
2403 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2404 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2405 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2406 if (is_ldpc)
2407 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2408 break;
2409 case RX_MSDU_START_PKT_TYPE_11AX:
2410 rx_status->rate_idx = rate_mcs;
2411 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2412 ath11k_warn(ar->ab,
2413 "Received with invalid mcs in HE mode %d\n",
2414 rate_mcs);
2415 break;
2416 }
2417 rx_status->encoding = RX_ENC_HE;
2418 rx_status->nss = nss;
2419 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2420 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2421 break;
2422 }
2423 }
2424
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2425 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2426 struct ieee80211_rx_status *rx_status)
2427 {
2428 u8 channel_num;
2429 u32 center_freq, meta_data;
2430 struct ieee80211_channel *channel;
2431
2432 rx_status->freq = 0;
2433 rx_status->rate_idx = 0;
2434 rx_status->nss = 0;
2435 rx_status->encoding = RX_ENC_LEGACY;
2436 rx_status->bw = RATE_INFO_BW_20;
2437
2438 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2439
2440 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2441 channel_num = meta_data;
2442 center_freq = meta_data >> 16;
2443
2444 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2445 center_freq <= ATH11K_MAX_6G_FREQ) {
2446 rx_status->band = NL80211_BAND_6GHZ;
2447 rx_status->freq = center_freq;
2448 } else if (channel_num >= 1 && channel_num <= 14) {
2449 rx_status->band = NL80211_BAND_2GHZ;
2450 } else if (channel_num >= 36 && channel_num <= 177) {
2451 rx_status->band = NL80211_BAND_5GHZ;
2452 } else {
2453 spin_lock_bh(&ar->data_lock);
2454 channel = ar->rx_channel;
2455 if (channel) {
2456 rx_status->band = channel->band;
2457 channel_num =
2458 ieee80211_frequency_to_channel(channel->center_freq);
2459 }
2460 spin_unlock_bh(&ar->data_lock);
2461 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2462 rx_desc, sizeof(struct hal_rx_desc));
2463 }
2464
2465 if (rx_status->band != NL80211_BAND_6GHZ)
2466 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2467 rx_status->band);
2468
2469 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2470 }
2471
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2472 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2473 struct sk_buff *msdu,
2474 struct ieee80211_rx_status *status)
2475 {
2476 static const struct ieee80211_radiotap_he known = {
2477 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2478 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2479 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2480 };
2481 struct ieee80211_rx_status *rx_status;
2482 struct ieee80211_radiotap_he *he = NULL;
2483 struct ieee80211_sta *pubsta = NULL;
2484 struct ath11k_peer *peer;
2485 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2486 u8 decap = DP_RX_DECAP_TYPE_RAW;
2487 bool is_mcbc = rxcb->is_mcbc;
2488 bool is_eapol = rxcb->is_eapol;
2489
2490 if (status->encoding == RX_ENC_HE &&
2491 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2492 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2493 he = skb_push(msdu, sizeof(known));
2494 memcpy(he, &known, sizeof(known));
2495 status->flag |= RX_FLAG_RADIOTAP_HE;
2496 }
2497
2498 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2499 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2500
2501 spin_lock_bh(&ar->ab->base_lock);
2502 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2503 if (peer && peer->sta)
2504 pubsta = peer->sta;
2505 spin_unlock_bh(&ar->ab->base_lock);
2506
2507 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2508 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2509 msdu,
2510 msdu->len,
2511 peer ? peer->addr : NULL,
2512 rxcb->tid,
2513 is_mcbc ? "mcast" : "ucast",
2514 rxcb->seq_no,
2515 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2516 (status->encoding == RX_ENC_HT) ? "ht" : "",
2517 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2518 (status->encoding == RX_ENC_HE) ? "he" : "",
2519 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2520 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2521 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2522 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2523 status->rate_idx,
2524 status->nss,
2525 status->freq,
2526 status->band, status->flag,
2527 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2528 !!(status->flag & RX_FLAG_MMIC_ERROR),
2529 !!(status->flag & RX_FLAG_AMSDU_MORE));
2530
2531 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2532 msdu->data, msdu->len);
2533
2534 rx_status = IEEE80211_SKB_RXCB(msdu);
2535 *rx_status = *status;
2536
2537 /* TODO: trace rx packet */
2538
2539 /* PN for multicast packets are not validate in HW,
2540 * so skip 802.3 rx path
2541 * Also, fast_rx expects the STA to be authorized, hence
2542 * eapol packets are sent in slow path.
2543 */
2544 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2545 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2546 rx_status->flag |= RX_FLAG_8023;
2547
2548 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2549 }
2550
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2551 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2552 struct sk_buff *msdu,
2553 struct sk_buff_head *msdu_list,
2554 struct ieee80211_rx_status *rx_status)
2555 {
2556 struct ath11k_base *ab = ar->ab;
2557 struct hal_rx_desc *rx_desc, *lrx_desc;
2558 struct rx_attention *rx_attention;
2559 struct ath11k_skb_rxcb *rxcb;
2560 struct sk_buff *last_buf;
2561 u8 l3_pad_bytes;
2562 u8 *hdr_status;
2563 u16 msdu_len;
2564 int ret;
2565 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2566
2567 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2568 if (!last_buf) {
2569 ath11k_warn(ab,
2570 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2571 ret = -EIO;
2572 goto free_out;
2573 }
2574
2575 rx_desc = (struct hal_rx_desc *)msdu->data;
2576 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2577 ath11k_warn(ar->ab, "msdu len not valid\n");
2578 ret = -EIO;
2579 goto free_out;
2580 }
2581
2582 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2583 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2584 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2585 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2586 ret = -EIO;
2587 goto free_out;
2588 }
2589
2590 rxcb = ATH11K_SKB_RXCB(msdu);
2591 rxcb->rx_desc = rx_desc;
2592 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2593 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2594
2595 if (rxcb->is_frag) {
2596 skb_pull(msdu, hal_rx_desc_sz);
2597 } else if (!rxcb->is_continuation) {
2598 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2599 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2600 ret = -EINVAL;
2601 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2602 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2603 sizeof(struct ieee80211_hdr));
2604 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2605 sizeof(struct hal_rx_desc));
2606 goto free_out;
2607 }
2608 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2609 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2610 } else {
2611 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2612 msdu, last_buf,
2613 l3_pad_bytes, msdu_len);
2614 if (ret) {
2615 ath11k_warn(ab,
2616 "failed to coalesce msdu rx buffer%d\n", ret);
2617 goto free_out;
2618 }
2619 }
2620
2621 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2622 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2623
2624 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2625
2626 return 0;
2627
2628 free_out:
2629 return ret;
2630 }
2631
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2632 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2633 struct napi_struct *napi,
2634 struct sk_buff_head *msdu_list,
2635 int mac_id)
2636 {
2637 struct sk_buff *msdu;
2638 struct ath11k *ar;
2639 struct ieee80211_rx_status rx_status = {};
2640 int ret;
2641
2642 if (skb_queue_empty(msdu_list))
2643 return;
2644
2645 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2646 __skb_queue_purge(msdu_list);
2647 return;
2648 }
2649
2650 ar = ab->pdevs[mac_id].ar;
2651 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2652 __skb_queue_purge(msdu_list);
2653 return;
2654 }
2655
2656 while ((msdu = __skb_dequeue(msdu_list))) {
2657 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2658 if (unlikely(ret)) {
2659 ath11k_dbg(ab, ATH11K_DBG_DATA,
2660 "Unable to process msdu %d", ret);
2661 dev_kfree_skb_any(msdu);
2662 continue;
2663 }
2664
2665 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2666 }
2667 }
2668
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2669 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2670 struct napi_struct *napi, int budget)
2671 {
2672 struct ath11k_dp *dp = &ab->dp;
2673 struct dp_rxdma_ring *rx_ring;
2674 int num_buffs_reaped[MAX_RADIOS] = {};
2675 struct sk_buff_head msdu_list[MAX_RADIOS];
2676 struct ath11k_skb_rxcb *rxcb;
2677 int total_msdu_reaped = 0;
2678 struct hal_srng *srng;
2679 struct sk_buff *msdu;
2680 bool done = false;
2681 int buf_id, mac_id;
2682 struct ath11k *ar;
2683 struct hal_reo_dest_ring *desc;
2684 enum hal_reo_dest_ring_push_reason push_reason;
2685 u32 cookie;
2686 int i;
2687
2688 for (i = 0; i < MAX_RADIOS; i++)
2689 __skb_queue_head_init(&msdu_list[i]);
2690
2691 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2692
2693 spin_lock_bh(&srng->lock);
2694
2695 try_again:
2696 ath11k_hal_srng_access_begin(ab, srng);
2697
2698 while (likely(desc =
2699 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2700 srng))) {
2701 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2702 desc->buf_addr_info.info1);
2703 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2704 cookie);
2705 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2706
2707 if (unlikely(buf_id == 0))
2708 continue;
2709
2710 ar = ab->pdevs[mac_id].ar;
2711 rx_ring = &ar->dp.rx_refill_buf_ring;
2712 spin_lock_bh(&rx_ring->idr_lock);
2713 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2714 if (unlikely(!msdu)) {
2715 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2716 buf_id);
2717 spin_unlock_bh(&rx_ring->idr_lock);
2718 continue;
2719 }
2720
2721 idr_remove(&rx_ring->bufs_idr, buf_id);
2722 spin_unlock_bh(&rx_ring->idr_lock);
2723
2724 rxcb = ATH11K_SKB_RXCB(msdu);
2725 dma_unmap_single(ab->dev, rxcb->paddr,
2726 msdu->len + skb_tailroom(msdu),
2727 DMA_FROM_DEVICE);
2728
2729 num_buffs_reaped[mac_id]++;
2730
2731 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2732 desc->info0);
2733 if (unlikely(push_reason !=
2734 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2735 dev_kfree_skb_any(msdu);
2736 ab->soc_stats.hal_reo_error[ring_id]++;
2737 continue;
2738 }
2739
2740 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2741 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2742 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2743 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2744 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2745 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2746 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2747 desc->rx_mpdu_info.meta_data);
2748 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2749 desc->rx_mpdu_info.info0);
2750 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2751 desc->info0);
2752
2753 rxcb->mac_id = mac_id;
2754 __skb_queue_tail(&msdu_list[mac_id], msdu);
2755
2756 if (rxcb->is_continuation) {
2757 done = false;
2758 } else {
2759 total_msdu_reaped++;
2760 done = true;
2761 }
2762
2763 if (total_msdu_reaped >= budget)
2764 break;
2765 }
2766
2767 /* Hw might have updated the head pointer after we cached it.
2768 * In this case, even though there are entries in the ring we'll
2769 * get rx_desc NULL. Give the read another try with updated cached
2770 * head pointer so that we can reap complete MPDU in the current
2771 * rx processing.
2772 */
2773 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2774 ath11k_hal_srng_access_end(ab, srng);
2775 goto try_again;
2776 }
2777
2778 ath11k_hal_srng_access_end(ab, srng);
2779
2780 spin_unlock_bh(&srng->lock);
2781
2782 if (unlikely(!total_msdu_reaped))
2783 goto exit;
2784
2785 for (i = 0; i < ab->num_radios; i++) {
2786 if (!num_buffs_reaped[i])
2787 continue;
2788
2789 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2790
2791 ar = ab->pdevs[i].ar;
2792 rx_ring = &ar->dp.rx_refill_buf_ring;
2793
2794 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2795 ab->hw_params.hal_params->rx_buf_rbm);
2796 }
2797 exit:
2798 return total_msdu_reaped;
2799 }
2800
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2801 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2802 struct hal_rx_mon_ppdu_info *ppdu_info)
2803 {
2804 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2805 u32 num_msdu;
2806 int i;
2807
2808 if (!rx_stats)
2809 return;
2810
2811 arsta->rssi_comb = ppdu_info->rssi_comb;
2812 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2813
2814 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2815 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2816
2817 rx_stats->num_msdu += num_msdu;
2818 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2819 ppdu_info->tcp_ack_msdu_count;
2820 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2821 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2822
2823 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2824 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2825 ppdu_info->nss = 1;
2826 ppdu_info->mcs = HAL_RX_MAX_MCS;
2827 ppdu_info->tid = IEEE80211_NUM_TIDS;
2828 }
2829
2830 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2831 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2832
2833 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2834 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2835
2836 if (ppdu_info->gi < HAL_RX_GI_MAX)
2837 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2838
2839 if (ppdu_info->bw < HAL_RX_BW_MAX)
2840 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2841
2842 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2843 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2844
2845 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2846 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2847
2848 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2849 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2850
2851 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2852 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2853
2854 if (ppdu_info->is_stbc)
2855 rx_stats->stbc_count += num_msdu;
2856
2857 if (ppdu_info->beamformed)
2858 rx_stats->beamformed_count += num_msdu;
2859
2860 if (ppdu_info->num_mpdu_fcs_ok > 1)
2861 rx_stats->ampdu_msdu_count += num_msdu;
2862 else
2863 rx_stats->non_ampdu_msdu_count += num_msdu;
2864
2865 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2866 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2867 rx_stats->dcm_count += ppdu_info->dcm;
2868 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2869
2870 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2871 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2872
2873 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2874 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2875
2876 rx_stats->rx_duration += ppdu_info->rx_duration;
2877 arsta->rx_duration = rx_stats->rx_duration;
2878 }
2879
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2880 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2881 struct dp_rxdma_ring *rx_ring,
2882 int *buf_id)
2883 {
2884 struct sk_buff *skb;
2885 dma_addr_t paddr;
2886
2887 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2888 DP_RX_BUFFER_ALIGN_SIZE);
2889
2890 if (!skb)
2891 goto fail_alloc_skb;
2892
2893 if (!IS_ALIGNED((unsigned long)skb->data,
2894 DP_RX_BUFFER_ALIGN_SIZE)) {
2895 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2896 skb->data);
2897 }
2898
2899 paddr = dma_map_single(ab->dev, skb->data,
2900 skb->len + skb_tailroom(skb),
2901 DMA_FROM_DEVICE);
2902 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2903 goto fail_free_skb;
2904
2905 spin_lock_bh(&rx_ring->idr_lock);
2906 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2907 rx_ring->bufs_max, GFP_ATOMIC);
2908 spin_unlock_bh(&rx_ring->idr_lock);
2909 if (*buf_id < 0)
2910 goto fail_dma_unmap;
2911
2912 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2913 return skb;
2914
2915 fail_dma_unmap:
2916 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2917 DMA_FROM_DEVICE);
2918 fail_free_skb:
2919 dev_kfree_skb_any(skb);
2920 fail_alloc_skb:
2921 return NULL;
2922 }
2923
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2924 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2925 struct dp_rxdma_ring *rx_ring,
2926 int req_entries,
2927 enum hal_rx_buf_return_buf_manager mgr)
2928 {
2929 struct hal_srng *srng;
2930 u32 *desc;
2931 struct sk_buff *skb;
2932 int num_free;
2933 int num_remain;
2934 int buf_id;
2935 u32 cookie;
2936 dma_addr_t paddr;
2937
2938 req_entries = min(req_entries, rx_ring->bufs_max);
2939
2940 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2941
2942 spin_lock_bh(&srng->lock);
2943
2944 ath11k_hal_srng_access_begin(ab, srng);
2945
2946 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2947
2948 req_entries = min(num_free, req_entries);
2949 num_remain = req_entries;
2950
2951 while (num_remain > 0) {
2952 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2953 &buf_id);
2954 if (!skb)
2955 break;
2956 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2957
2958 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2959 if (!desc)
2960 goto fail_desc_get;
2961
2962 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2963 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2964
2965 num_remain--;
2966
2967 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2968 }
2969
2970 ath11k_hal_srng_access_end(ab, srng);
2971
2972 spin_unlock_bh(&srng->lock);
2973
2974 return req_entries - num_remain;
2975
2976 fail_desc_get:
2977 spin_lock_bh(&rx_ring->idr_lock);
2978 idr_remove(&rx_ring->bufs_idr, buf_id);
2979 spin_unlock_bh(&rx_ring->idr_lock);
2980 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2981 DMA_FROM_DEVICE);
2982 dev_kfree_skb_any(skb);
2983 ath11k_hal_srng_access_end(ab, srng);
2984 spin_unlock_bh(&srng->lock);
2985
2986 return req_entries - num_remain;
2987 }
2988
2989 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2990
2991 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2992 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2993 struct hal_tlv_hdr *tlv)
2994 {
2995 struct hal_rx_ppdu_start *ppdu_start;
2996 u16 ppdu_id_diff, ppdu_id, tlv_len;
2997 u8 *ptr;
2998
2999 /* PPDU id is part of second tlv, move ptr to second tlv */
3000 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
3001 ptr = (u8 *)tlv;
3002 ptr += sizeof(*tlv) + tlv_len;
3003 tlv = (struct hal_tlv_hdr *)ptr;
3004
3005 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
3006 return;
3007
3008 ptr += sizeof(*tlv);
3009 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
3010 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
3011 __le32_to_cpu(ppdu_start->info0));
3012
3013 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
3014 pmon->buf_state = DP_MON_STATUS_LEAD;
3015 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
3016 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
3017 pmon->buf_state = DP_MON_STATUS_LAG;
3018 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
3019 pmon->buf_state = DP_MON_STATUS_LAG;
3020 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
3021 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
3022 pmon->buf_state = DP_MON_STATUS_LEAD;
3023 }
3024 }
3025
3026 static enum dp_mon_status_buf_state
ath11k_dp_rx_mon_buf_done(struct ath11k_base * ab,struct hal_srng * srng,struct dp_rxdma_ring * rx_ring)3027 ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
3028 struct dp_rxdma_ring *rx_ring)
3029 {
3030 struct ath11k_skb_rxcb *rxcb;
3031 struct hal_tlv_hdr *tlv;
3032 struct sk_buff *skb;
3033 void *status_desc;
3034 dma_addr_t paddr;
3035 u32 cookie;
3036 int buf_id;
3037 u8 rbm;
3038
3039 status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
3040 if (!status_desc)
3041 return DP_MON_STATUS_NO_DMA;
3042
3043 ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
3044
3045 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3046
3047 spin_lock_bh(&rx_ring->idr_lock);
3048 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3049 spin_unlock_bh(&rx_ring->idr_lock);
3050
3051 if (!skb)
3052 return DP_MON_STATUS_NO_DMA;
3053
3054 rxcb = ATH11K_SKB_RXCB(skb);
3055 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3056 skb->len + skb_tailroom(skb),
3057 DMA_FROM_DEVICE);
3058
3059 tlv = (struct hal_tlv_hdr *)skb->data;
3060 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
3061 return DP_MON_STATUS_NO_DMA;
3062
3063 return DP_MON_STATUS_REPLINISH;
3064 }
3065
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3066 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3067 int *budget, struct sk_buff_head *skb_list)
3068 {
3069 struct ath11k *ar;
3070 const struct ath11k_hw_hal_params *hal_params;
3071 enum dp_mon_status_buf_state reap_status;
3072 struct ath11k_pdev_dp *dp;
3073 struct dp_rxdma_ring *rx_ring;
3074 struct ath11k_mon_data *pmon;
3075 struct hal_srng *srng;
3076 void *rx_mon_status_desc;
3077 struct sk_buff *skb;
3078 struct ath11k_skb_rxcb *rxcb;
3079 struct hal_tlv_hdr *tlv;
3080 u32 cookie;
3081 int buf_id, srng_id;
3082 dma_addr_t paddr;
3083 u8 rbm;
3084 int num_buffs_reaped = 0;
3085
3086 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3087 dp = &ar->dp;
3088 pmon = &dp->mon_data;
3089 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3090 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3091
3092 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3093
3094 spin_lock_bh(&srng->lock);
3095
3096 ath11k_hal_srng_access_begin(ab, srng);
3097 while (*budget) {
3098 *budget -= 1;
3099 rx_mon_status_desc =
3100 ath11k_hal_srng_src_peek(ab, srng);
3101 if (!rx_mon_status_desc) {
3102 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3103 break;
3104 }
3105
3106 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3107 &cookie, &rbm);
3108 if (paddr) {
3109 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3110
3111 spin_lock_bh(&rx_ring->idr_lock);
3112 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3113 spin_unlock_bh(&rx_ring->idr_lock);
3114
3115 if (!skb) {
3116 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3117 buf_id);
3118 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3119 goto move_next;
3120 }
3121
3122 rxcb = ATH11K_SKB_RXCB(skb);
3123
3124 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3125 skb->len + skb_tailroom(skb),
3126 DMA_FROM_DEVICE);
3127
3128 tlv = (struct hal_tlv_hdr *)skb->data;
3129 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3130 HAL_RX_STATUS_BUFFER_DONE) {
3131 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3132 FIELD_GET(HAL_TLV_HDR_TAG,
3133 tlv->tl), buf_id);
3134 /* RxDMA status done bit might not be set even
3135 * though tp is moved by HW.
3136 */
3137
3138 /* If done status is missing:
3139 * 1. As per MAC team's suggestion,
3140 * when HP + 1 entry is peeked and if DMA
3141 * is not done and if HP + 2 entry's DMA done
3142 * is set. skip HP + 1 entry and
3143 * start processing in next interrupt.
3144 * 2. If HP + 2 entry's DMA done is not set,
3145 * poll onto HP + 1 entry DMA done to be set.
3146 * Check status for same buffer for next time
3147 * dp_rx_mon_status_srng_process
3148 */
3149
3150 reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
3151 rx_ring);
3152 if (reap_status == DP_MON_STATUS_NO_DMA)
3153 continue;
3154
3155 spin_lock_bh(&rx_ring->idr_lock);
3156 idr_remove(&rx_ring->bufs_idr, buf_id);
3157 spin_unlock_bh(&rx_ring->idr_lock);
3158
3159 dma_unmap_single(ab->dev, rxcb->paddr,
3160 skb->len + skb_tailroom(skb),
3161 DMA_FROM_DEVICE);
3162
3163 dev_kfree_skb_any(skb);
3164 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3165 goto move_next;
3166 }
3167
3168 spin_lock_bh(&rx_ring->idr_lock);
3169 idr_remove(&rx_ring->bufs_idr, buf_id);
3170 spin_unlock_bh(&rx_ring->idr_lock);
3171 if (ab->hw_params.full_monitor_mode) {
3172 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3173 if (paddr == pmon->mon_status_paddr)
3174 pmon->buf_state = DP_MON_STATUS_MATCH;
3175 }
3176
3177 dma_unmap_single(ab->dev, rxcb->paddr,
3178 skb->len + skb_tailroom(skb),
3179 DMA_FROM_DEVICE);
3180
3181 __skb_queue_tail(skb_list, skb);
3182 } else {
3183 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3184 }
3185 move_next:
3186 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3187 &buf_id);
3188
3189 if (!skb) {
3190 hal_params = ab->hw_params.hal_params;
3191 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3192 hal_params->rx_buf_rbm);
3193 num_buffs_reaped++;
3194 break;
3195 }
3196 rxcb = ATH11K_SKB_RXCB(skb);
3197
3198 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3199 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3200
3201 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3202 cookie,
3203 ab->hw_params.hal_params->rx_buf_rbm);
3204 ath11k_hal_srng_src_get_next_entry(ab, srng);
3205 num_buffs_reaped++;
3206 }
3207 ath11k_hal_srng_access_end(ab, srng);
3208 spin_unlock_bh(&srng->lock);
3209
3210 return num_buffs_reaped;
3211 }
3212
ath11k_dp_rx_frag_timer(struct timer_list * timer)3213 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3214 {
3215 struct dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer,
3216 frag_timer);
3217
3218 spin_lock_bh(&rx_tid->ab->base_lock);
3219 if (rx_tid->last_frag_no &&
3220 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3221 spin_unlock_bh(&rx_tid->ab->base_lock);
3222 return;
3223 }
3224 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3225 spin_unlock_bh(&rx_tid->ab->base_lock);
3226 }
3227
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3228 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3229 {
3230 struct ath11k_base *ab = ar->ab;
3231 struct crypto_shash *tfm;
3232 struct ath11k_peer *peer;
3233 struct dp_rx_tid *rx_tid;
3234 int i;
3235
3236 tfm = crypto_alloc_shash("michael_mic", 0, 0);
3237 if (IS_ERR(tfm)) {
3238 ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
3239 PTR_ERR(tfm));
3240 return PTR_ERR(tfm);
3241 }
3242
3243 spin_lock_bh(&ab->base_lock);
3244
3245 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3246 if (!peer) {
3247 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3248 spin_unlock_bh(&ab->base_lock);
3249 crypto_free_shash(tfm);
3250 return -ENOENT;
3251 }
3252
3253 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3254 rx_tid = &peer->rx_tid[i];
3255 rx_tid->ab = ab;
3256 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3257 skb_queue_head_init(&rx_tid->rx_frags);
3258 }
3259
3260 peer->tfm_mmic = tfm;
3261 peer->dp_setup_done = true;
3262 spin_unlock_bh(&ab->base_lock);
3263
3264 return 0;
3265 }
3266
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3267 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3268 struct ieee80211_hdr *hdr, u8 *data,
3269 size_t data_len, u8 *mic)
3270 {
3271 SHASH_DESC_ON_STACK(desc, tfm);
3272 u8 mic_hdr[16] = {};
3273 u8 tid = 0;
3274 int ret;
3275
3276 if (!tfm)
3277 return -EINVAL;
3278
3279 desc->tfm = tfm;
3280
3281 ret = crypto_shash_setkey(tfm, key, 8);
3282 if (ret)
3283 goto out;
3284
3285 ret = crypto_shash_init(desc);
3286 if (ret)
3287 goto out;
3288
3289 /* TKIP MIC header */
3290 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3291 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3292 if (ieee80211_is_data_qos(hdr->frame_control))
3293 tid = ieee80211_get_tid(hdr);
3294 mic_hdr[12] = tid;
3295
3296 ret = crypto_shash_update(desc, mic_hdr, 16);
3297 if (ret)
3298 goto out;
3299 ret = crypto_shash_update(desc, data, data_len);
3300 if (ret)
3301 goto out;
3302 ret = crypto_shash_final(desc, mic);
3303 out:
3304 shash_desc_zero(desc);
3305 return ret;
3306 }
3307
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3308 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3309 struct sk_buff *msdu)
3310 {
3311 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3312 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3313 struct ieee80211_key_conf *key_conf;
3314 struct ieee80211_hdr *hdr;
3315 u8 mic[IEEE80211_CCMP_MIC_LEN];
3316 int head_len, tail_len, ret;
3317 size_t data_len;
3318 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3319 u8 *key, *data;
3320 u8 key_idx;
3321
3322 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3323 HAL_ENCRYPT_TYPE_TKIP_MIC)
3324 return 0;
3325
3326 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3327 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3328 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3329 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3330
3331 if (!is_multicast_ether_addr(hdr->addr1))
3332 key_idx = peer->ucast_keyidx;
3333 else
3334 key_idx = peer->mcast_keyidx;
3335
3336 key_conf = peer->keys[key_idx];
3337
3338 data = msdu->data + head_len;
3339 data_len = msdu->len - head_len - tail_len;
3340 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3341
3342 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3343 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3344 goto mic_fail;
3345
3346 return 0;
3347
3348 mic_fail:
3349 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3350 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3351
3352 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3353 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3354 skb_pull(msdu, hal_rx_desc_sz);
3355
3356 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3357 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3358 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3359 ieee80211_rx(ar->hw, msdu);
3360 return -EINVAL;
3361 }
3362
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3363 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3364 enum hal_encrypt_type enctype, u32 flags)
3365 {
3366 struct ieee80211_hdr *hdr;
3367 size_t hdr_len;
3368 size_t crypto_len;
3369 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3370
3371 if (!flags)
3372 return;
3373
3374 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3375
3376 if (flags & RX_FLAG_MIC_STRIPPED)
3377 skb_trim(msdu, msdu->len -
3378 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3379
3380 if (flags & RX_FLAG_ICV_STRIPPED)
3381 skb_trim(msdu, msdu->len -
3382 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3383
3384 if (flags & RX_FLAG_IV_STRIPPED) {
3385 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3386 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3387
3388 #if defined(__linux__)
3389 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3390 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3391 #elif defined(__FreeBSD__)
3392 memmove((u8 *)msdu->data + hal_rx_desc_sz + crypto_len,
3393 (u8 *)msdu->data + hal_rx_desc_sz, hdr_len);
3394 #endif
3395 skb_pull(msdu, crypto_len);
3396 }
3397 }
3398
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3399 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3400 struct ath11k_peer *peer,
3401 struct dp_rx_tid *rx_tid,
3402 struct sk_buff **defrag_skb)
3403 {
3404 struct hal_rx_desc *rx_desc;
3405 struct sk_buff *skb, *first_frag, *last_frag;
3406 struct ieee80211_hdr *hdr;
3407 struct rx_attention *rx_attention;
3408 enum hal_encrypt_type enctype;
3409 bool is_decrypted = false;
3410 int msdu_len = 0;
3411 int extra_space;
3412 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3413
3414 first_frag = skb_peek(&rx_tid->rx_frags);
3415 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3416
3417 skb_queue_walk(&rx_tid->rx_frags, skb) {
3418 flags = 0;
3419 rx_desc = (struct hal_rx_desc *)skb->data;
3420 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3421
3422 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3423 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3424 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3425 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3426 }
3427
3428 if (is_decrypted) {
3429 if (skb != first_frag)
3430 flags |= RX_FLAG_IV_STRIPPED;
3431 if (skb != last_frag)
3432 flags |= RX_FLAG_ICV_STRIPPED |
3433 RX_FLAG_MIC_STRIPPED;
3434 }
3435
3436 /* RX fragments are always raw packets */
3437 if (skb != last_frag)
3438 skb_trim(skb, skb->len - FCS_LEN);
3439 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3440
3441 if (skb != first_frag)
3442 skb_pull(skb, hal_rx_desc_sz +
3443 ieee80211_hdrlen(hdr->frame_control));
3444 msdu_len += skb->len;
3445 }
3446
3447 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3448 if (extra_space > 0 &&
3449 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3450 return -ENOMEM;
3451
3452 __skb_unlink(first_frag, &rx_tid->rx_frags);
3453 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3454 skb_put_data(first_frag, skb->data, skb->len);
3455 dev_kfree_skb_any(skb);
3456 }
3457
3458 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3459 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3460 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3461
3462 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3463 first_frag = NULL;
3464
3465 *defrag_skb = first_frag;
3466 return 0;
3467 }
3468
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3469 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3470 struct sk_buff *defrag_skb)
3471 {
3472 struct ath11k_base *ab = ar->ab;
3473 struct ath11k_pdev_dp *dp = &ar->dp;
3474 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3475 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3476 struct hal_reo_entrance_ring *reo_ent_ring;
3477 struct hal_reo_dest_ring *reo_dest_ring;
3478 struct dp_link_desc_bank *link_desc_banks;
3479 struct hal_rx_msdu_link *msdu_link;
3480 struct hal_rx_msdu_details *msdu0;
3481 struct hal_srng *srng;
3482 dma_addr_t paddr;
3483 u32 desc_bank, msdu_info, mpdu_info;
3484 u32 dst_idx, cookie, hal_rx_desc_sz;
3485 int ret, buf_id;
3486
3487 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3488 link_desc_banks = ab->dp.link_desc_banks;
3489 reo_dest_ring = rx_tid->dst_ring_desc;
3490
3491 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3492 #if defined(__linux__)
3493 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3494 #elif defined(__FreeBSD__)
3495 msdu_link = (struct hal_rx_msdu_link *)((u8 *)link_desc_banks[desc_bank].vaddr +
3496 #endif
3497 (paddr - link_desc_banks[desc_bank].paddr));
3498 msdu0 = &msdu_link->msdu_link[0];
3499 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3500 memset(msdu0, 0, sizeof(*msdu0));
3501
3502 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3503 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3504 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3505 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3506 defrag_skb->len - hal_rx_desc_sz) |
3507 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3508 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3509 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3510 msdu0->rx_msdu_info.info0 = msdu_info;
3511
3512 /* change msdu len in hal rx desc */
3513 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3514
3515 paddr = dma_map_single(ab->dev, defrag_skb->data,
3516 defrag_skb->len + skb_tailroom(defrag_skb),
3517 DMA_TO_DEVICE);
3518 if (dma_mapping_error(ab->dev, paddr))
3519 return -ENOMEM;
3520
3521 spin_lock_bh(&rx_refill_ring->idr_lock);
3522 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3523 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3524 spin_unlock_bh(&rx_refill_ring->idr_lock);
3525 if (buf_id < 0) {
3526 ret = -ENOMEM;
3527 goto err_unmap_dma;
3528 }
3529
3530 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3531 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3532 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3533
3534 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3535 ab->hw_params.hal_params->rx_buf_rbm);
3536
3537 /* Fill mpdu details into reo entrance ring */
3538 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3539
3540 spin_lock_bh(&srng->lock);
3541 ath11k_hal_srng_access_begin(ab, srng);
3542
3543 reo_ent_ring = (struct hal_reo_entrance_ring *)
3544 ath11k_hal_srng_src_get_next_entry(ab, srng);
3545 if (!reo_ent_ring) {
3546 ath11k_hal_srng_access_end(ab, srng);
3547 spin_unlock_bh(&srng->lock);
3548 ret = -ENOSPC;
3549 goto err_free_idr;
3550 }
3551 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3552
3553 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3554 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3555 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3556
3557 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3558 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3559 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3560 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3561 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3562 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3563 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3564
3565 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3566 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3567 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3568 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3569 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3570 reo_dest_ring->info0)) |
3571 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3572 ath11k_hal_srng_access_end(ab, srng);
3573 spin_unlock_bh(&srng->lock);
3574
3575 return 0;
3576
3577 err_free_idr:
3578 spin_lock_bh(&rx_refill_ring->idr_lock);
3579 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3580 spin_unlock_bh(&rx_refill_ring->idr_lock);
3581 err_unmap_dma:
3582 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3583 DMA_TO_DEVICE);
3584 return ret;
3585 }
3586
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3587 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3588 struct sk_buff *a, struct sk_buff *b)
3589 {
3590 int frag1, frag2;
3591
3592 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3593 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3594
3595 return frag1 - frag2;
3596 }
3597
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3598 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3599 struct sk_buff_head *frag_list,
3600 struct sk_buff *cur_frag)
3601 {
3602 struct sk_buff *skb;
3603 int cmp;
3604
3605 skb_queue_walk(frag_list, skb) {
3606 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3607 if (cmp < 0)
3608 continue;
3609 __skb_queue_before(frag_list, skb, cur_frag);
3610 return;
3611 }
3612 __skb_queue_tail(frag_list, cur_frag);
3613 }
3614
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3615 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3616 {
3617 struct ieee80211_hdr *hdr;
3618 u64 pn = 0;
3619 u8 *ehdr;
3620 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3621
3622 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3623 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3624
3625 pn = ehdr[0];
3626 pn |= (u64)ehdr[1] << 8;
3627 pn |= (u64)ehdr[4] << 16;
3628 pn |= (u64)ehdr[5] << 24;
3629 pn |= (u64)ehdr[6] << 32;
3630 pn |= (u64)ehdr[7] << 40;
3631
3632 return pn;
3633 }
3634
3635 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3636 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3637 {
3638 enum hal_encrypt_type encrypt_type;
3639 struct sk_buff *first_frag, *skb;
3640 struct hal_rx_desc *desc;
3641 u64 last_pn;
3642 u64 cur_pn;
3643
3644 first_frag = skb_peek(&rx_tid->rx_frags);
3645 desc = (struct hal_rx_desc *)first_frag->data;
3646
3647 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3648 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3649 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3650 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3651 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3652 return true;
3653
3654 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3655 skb_queue_walk(&rx_tid->rx_frags, skb) {
3656 if (skb == first_frag)
3657 continue;
3658
3659 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3660 if (cur_pn != last_pn + 1)
3661 return false;
3662 last_pn = cur_pn;
3663 }
3664 return true;
3665 }
3666
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3667 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3668 struct sk_buff *msdu,
3669 u32 *ring_desc)
3670 {
3671 struct ath11k_base *ab = ar->ab;
3672 struct hal_rx_desc *rx_desc;
3673 struct ath11k_peer *peer;
3674 struct dp_rx_tid *rx_tid;
3675 struct sk_buff *defrag_skb = NULL;
3676 u32 peer_id;
3677 u16 seqno, frag_no;
3678 u8 tid;
3679 int ret = 0;
3680 bool more_frags;
3681 bool is_mcbc;
3682
3683 rx_desc = (struct hal_rx_desc *)msdu->data;
3684 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3685 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3686 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3687 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3688 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3689 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3690
3691 /* Multicast/Broadcast fragments are not expected */
3692 if (is_mcbc)
3693 return -EINVAL;
3694
3695 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3696 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3697 tid > IEEE80211_NUM_TIDS)
3698 return -EINVAL;
3699
3700 /* received unfragmented packet in reo
3701 * exception ring, this shouldn't happen
3702 * as these packets typically come from
3703 * reo2sw srngs.
3704 */
3705 if (WARN_ON_ONCE(!frag_no && !more_frags))
3706 return -EINVAL;
3707
3708 spin_lock_bh(&ab->base_lock);
3709 peer = ath11k_peer_find_by_id(ab, peer_id);
3710 if (!peer) {
3711 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3712 peer_id);
3713 ret = -ENOENT;
3714 goto out_unlock;
3715 }
3716 if (!peer->dp_setup_done) {
3717 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3718 peer->addr, peer_id);
3719 ret = -ENOENT;
3720 goto out_unlock;
3721 }
3722
3723 rx_tid = &peer->rx_tid[tid];
3724
3725 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3726 skb_queue_empty(&rx_tid->rx_frags)) {
3727 /* Flush stored fragments and start a new sequence */
3728 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3729 rx_tid->cur_sn = seqno;
3730 }
3731
3732 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3733 /* Fragment already present */
3734 ret = -EINVAL;
3735 goto out_unlock;
3736 }
3737
3738 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3739 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3740 else
3741 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3742
3743 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3744 if (!more_frags)
3745 rx_tid->last_frag_no = frag_no;
3746
3747 if (frag_no == 0) {
3748 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3749 sizeof(*rx_tid->dst_ring_desc),
3750 GFP_ATOMIC);
3751 if (!rx_tid->dst_ring_desc) {
3752 ret = -ENOMEM;
3753 goto out_unlock;
3754 }
3755 } else {
3756 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3757 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3758 }
3759
3760 if (!rx_tid->last_frag_no ||
3761 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3762 mod_timer(&rx_tid->frag_timer, jiffies +
3763 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3764 goto out_unlock;
3765 }
3766
3767 spin_unlock_bh(&ab->base_lock);
3768 timer_delete_sync(&rx_tid->frag_timer);
3769 spin_lock_bh(&ab->base_lock);
3770
3771 peer = ath11k_peer_find_by_id(ab, peer_id);
3772 if (!peer)
3773 goto err_frags_cleanup;
3774
3775 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3776 goto err_frags_cleanup;
3777
3778 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3779 goto err_frags_cleanup;
3780
3781 if (!defrag_skb)
3782 goto err_frags_cleanup;
3783
3784 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3785 goto err_frags_cleanup;
3786
3787 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3788 goto out_unlock;
3789
3790 err_frags_cleanup:
3791 dev_kfree_skb_any(defrag_skb);
3792 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3793 out_unlock:
3794 spin_unlock_bh(&ab->base_lock);
3795 return ret;
3796 }
3797
3798 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3799 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3800 {
3801 struct ath11k_pdev_dp *dp = &ar->dp;
3802 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3803 struct sk_buff *msdu;
3804 struct ath11k_skb_rxcb *rxcb;
3805 struct hal_rx_desc *rx_desc;
3806 u8 *hdr_status;
3807 u16 msdu_len;
3808 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3809
3810 spin_lock_bh(&rx_ring->idr_lock);
3811 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3812 if (!msdu) {
3813 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3814 buf_id);
3815 spin_unlock_bh(&rx_ring->idr_lock);
3816 return -EINVAL;
3817 }
3818
3819 idr_remove(&rx_ring->bufs_idr, buf_id);
3820 spin_unlock_bh(&rx_ring->idr_lock);
3821
3822 rxcb = ATH11K_SKB_RXCB(msdu);
3823 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3824 msdu->len + skb_tailroom(msdu),
3825 DMA_FROM_DEVICE);
3826
3827 if (drop) {
3828 dev_kfree_skb_any(msdu);
3829 return 0;
3830 }
3831
3832 rcu_read_lock();
3833 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3834 dev_kfree_skb_any(msdu);
3835 goto exit;
3836 }
3837
3838 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3839 dev_kfree_skb_any(msdu);
3840 goto exit;
3841 }
3842
3843 rx_desc = (struct hal_rx_desc *)msdu->data;
3844 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3845 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3846 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3847 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3848 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3849 sizeof(struct ieee80211_hdr));
3850 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3851 sizeof(struct hal_rx_desc));
3852 dev_kfree_skb_any(msdu);
3853 goto exit;
3854 }
3855
3856 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3857
3858 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3859 dev_kfree_skb_any(msdu);
3860 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3861 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3862 }
3863 exit:
3864 rcu_read_unlock();
3865 return 0;
3866 }
3867
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3868 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3869 int budget)
3870 {
3871 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3872 struct dp_link_desc_bank *link_desc_banks;
3873 enum hal_rx_buf_return_buf_manager rbm;
3874 int tot_n_bufs_reaped, quota, ret, i;
3875 int n_bufs_reaped[MAX_RADIOS] = {};
3876 struct dp_rxdma_ring *rx_ring;
3877 struct dp_srng *reo_except;
3878 u32 desc_bank, num_msdus;
3879 struct hal_srng *srng;
3880 struct ath11k_dp *dp;
3881 void *link_desc_va;
3882 int buf_id, mac_id;
3883 struct ath11k *ar;
3884 dma_addr_t paddr;
3885 u32 *desc;
3886 bool is_frag;
3887 u8 drop = 0;
3888
3889 tot_n_bufs_reaped = 0;
3890 quota = budget;
3891
3892 dp = &ab->dp;
3893 reo_except = &dp->reo_except_ring;
3894 link_desc_banks = dp->link_desc_banks;
3895
3896 srng = &ab->hal.srng_list[reo_except->ring_id];
3897
3898 spin_lock_bh(&srng->lock);
3899
3900 ath11k_hal_srng_access_begin(ab, srng);
3901
3902 while (budget &&
3903 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3904 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3905
3906 ab->soc_stats.err_ring_pkts++;
3907 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3908 &desc_bank);
3909 if (ret) {
3910 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3911 ret);
3912 continue;
3913 }
3914 #if defined(__linux__)
3915 link_desc_va = link_desc_banks[desc_bank].vaddr +
3916 #elif defined(__FreeBSD__)
3917 link_desc_va = (u8 *)link_desc_banks[desc_bank].vaddr +
3918 #endif
3919 (paddr - link_desc_banks[desc_bank].paddr);
3920 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3921 &rbm);
3922 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3923 rbm != HAL_RX_BUF_RBM_SW1_BM &&
3924 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3925 ab->soc_stats.invalid_rbm++;
3926 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3927 ath11k_dp_rx_link_desc_return(ab, desc,
3928 HAL_WBM_REL_BM_ACT_REL_MSDU);
3929 continue;
3930 }
3931
3932 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3933
3934 /* Process only rx fragments with one msdu per link desc below, and drop
3935 * msdu's indicated due to error reasons.
3936 */
3937 if (!is_frag || num_msdus > 1) {
3938 drop = 1;
3939 /* Return the link desc back to wbm idle list */
3940 ath11k_dp_rx_link_desc_return(ab, desc,
3941 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3942 }
3943
3944 for (i = 0; i < num_msdus; i++) {
3945 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3946 msdu_cookies[i]);
3947
3948 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3949 msdu_cookies[i]);
3950
3951 ar = ab->pdevs[mac_id].ar;
3952
3953 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3954 n_bufs_reaped[mac_id]++;
3955 tot_n_bufs_reaped++;
3956 }
3957 }
3958
3959 if (tot_n_bufs_reaped >= quota) {
3960 tot_n_bufs_reaped = quota;
3961 goto exit;
3962 }
3963
3964 budget = quota - tot_n_bufs_reaped;
3965 }
3966
3967 exit:
3968 ath11k_hal_srng_access_end(ab, srng);
3969
3970 spin_unlock_bh(&srng->lock);
3971
3972 for (i = 0; i < ab->num_radios; i++) {
3973 if (!n_bufs_reaped[i])
3974 continue;
3975
3976 ar = ab->pdevs[i].ar;
3977 rx_ring = &ar->dp.rx_refill_buf_ring;
3978
3979 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3980 ab->hw_params.hal_params->rx_buf_rbm);
3981 }
3982
3983 return tot_n_bufs_reaped;
3984 }
3985
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3986 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3987 int msdu_len,
3988 struct sk_buff_head *msdu_list)
3989 {
3990 struct sk_buff *skb, *tmp;
3991 struct ath11k_skb_rxcb *rxcb;
3992 int n_buffs;
3993
3994 n_buffs = DIV_ROUND_UP(msdu_len,
3995 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3996
3997 skb_queue_walk_safe(msdu_list, skb, tmp) {
3998 rxcb = ATH11K_SKB_RXCB(skb);
3999 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
4000 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
4001 if (!n_buffs)
4002 break;
4003 __skb_unlink(skb, msdu_list);
4004 dev_kfree_skb_any(skb);
4005 n_buffs--;
4006 }
4007 }
4008 }
4009
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4010 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
4011 struct ieee80211_rx_status *status,
4012 struct sk_buff_head *msdu_list)
4013 {
4014 u16 msdu_len;
4015 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4016 struct rx_attention *rx_attention;
4017 u8 l3pad_bytes;
4018 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4019 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4020
4021 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4022
4023 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
4024 /* First buffer will be freed by the caller, so deduct it's length */
4025 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
4026 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
4027 return -EINVAL;
4028 }
4029
4030 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
4031 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
4032 ath11k_warn(ar->ab,
4033 "msdu_done bit not set in null_q_des processing\n");
4034 __skb_queue_purge(msdu_list);
4035 return -EIO;
4036 }
4037
4038 /* Handle NULL queue descriptor violations arising out a missing
4039 * REO queue for a given peer or a given TID. This typically
4040 * may happen if a packet is received on a QOS enabled TID before the
4041 * ADDBA negotiation for that TID, when the TID queue is setup. Or
4042 * it may also happen for MC/BC frames if they are not routed to the
4043 * non-QOS TID queue, in the absence of any other default TID queue.
4044 * This error can show up both in a REO destination or WBM release ring.
4045 */
4046
4047 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4048 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4049
4050 if (rxcb->is_frag) {
4051 skb_pull(msdu, hal_rx_desc_sz);
4052 } else {
4053 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4054
4055 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
4056 return -EINVAL;
4057
4058 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4059 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4060 }
4061 ath11k_dp_rx_h_ppdu(ar, desc, status);
4062
4063 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
4064
4065 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
4066
4067 /* Please note that caller will having the access to msdu and completing
4068 * rx with mac80211. Need not worry about cleaning up amsdu_list.
4069 */
4070
4071 return 0;
4072 }
4073
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4074 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
4075 struct ieee80211_rx_status *status,
4076 struct sk_buff_head *msdu_list)
4077 {
4078 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4079 bool drop = false;
4080
4081 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
4082
4083 switch (rxcb->err_code) {
4084 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
4085 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
4086 drop = true;
4087 break;
4088 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
4089 /* TODO: Do not drop PN failed packets in the driver;
4090 * instead, it is good to drop such packets in mac80211
4091 * after incrementing the replay counters.
4092 */
4093 fallthrough;
4094 default:
4095 /* TODO: Review other errors and process them to mac80211
4096 * as appropriate.
4097 */
4098 drop = true;
4099 break;
4100 }
4101
4102 return drop;
4103 }
4104
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4105 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4106 struct ieee80211_rx_status *status)
4107 {
4108 u16 msdu_len;
4109 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4110 u8 l3pad_bytes;
4111 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4112 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4113
4114 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4115 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4116
4117 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4118 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4119 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4120 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4121
4122 ath11k_dp_rx_h_ppdu(ar, desc, status);
4123
4124 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4125 RX_FLAG_DECRYPTED);
4126
4127 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4128 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4129 }
4130
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4131 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4132 struct ieee80211_rx_status *status)
4133 {
4134 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4135 bool drop = false;
4136
4137 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4138
4139 switch (rxcb->err_code) {
4140 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4141 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4142 break;
4143 default:
4144 /* TODO: Review other rxdma error code to check if anything is
4145 * worth reporting to mac80211
4146 */
4147 drop = true;
4148 break;
4149 }
4150
4151 return drop;
4152 }
4153
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4154 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4155 struct napi_struct *napi,
4156 struct sk_buff *msdu,
4157 struct sk_buff_head *msdu_list)
4158 {
4159 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4160 struct ieee80211_rx_status rxs = {};
4161 bool drop = true;
4162
4163 switch (rxcb->err_rel_src) {
4164 case HAL_WBM_REL_SRC_MODULE_REO:
4165 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4166 break;
4167 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4168 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4169 break;
4170 default:
4171 /* msdu will get freed */
4172 break;
4173 }
4174
4175 if (drop) {
4176 dev_kfree_skb_any(msdu);
4177 return;
4178 }
4179
4180 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4181 }
4182
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4183 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4184 struct napi_struct *napi, int budget)
4185 {
4186 struct ath11k *ar;
4187 struct ath11k_dp *dp = &ab->dp;
4188 struct dp_rxdma_ring *rx_ring;
4189 struct hal_rx_wbm_rel_info err_info;
4190 struct hal_srng *srng;
4191 struct sk_buff *msdu;
4192 struct sk_buff_head msdu_list[MAX_RADIOS];
4193 struct ath11k_skb_rxcb *rxcb;
4194 u32 *rx_desc;
4195 int buf_id, mac_id;
4196 int num_buffs_reaped[MAX_RADIOS] = {};
4197 int total_num_buffs_reaped = 0;
4198 int ret, i;
4199
4200 for (i = 0; i < ab->num_radios; i++)
4201 __skb_queue_head_init(&msdu_list[i]);
4202
4203 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4204
4205 spin_lock_bh(&srng->lock);
4206
4207 ath11k_hal_srng_access_begin(ab, srng);
4208
4209 while (budget) {
4210 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4211 if (!rx_desc)
4212 break;
4213
4214 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4215 if (ret) {
4216 ath11k_warn(ab,
4217 "failed to parse rx error in wbm_rel ring desc %d\n",
4218 ret);
4219 continue;
4220 }
4221
4222 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4223 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4224
4225 ar = ab->pdevs[mac_id].ar;
4226 rx_ring = &ar->dp.rx_refill_buf_ring;
4227
4228 spin_lock_bh(&rx_ring->idr_lock);
4229 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4230 if (!msdu) {
4231 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4232 buf_id, mac_id);
4233 spin_unlock_bh(&rx_ring->idr_lock);
4234 continue;
4235 }
4236
4237 idr_remove(&rx_ring->bufs_idr, buf_id);
4238 spin_unlock_bh(&rx_ring->idr_lock);
4239
4240 rxcb = ATH11K_SKB_RXCB(msdu);
4241 dma_unmap_single(ab->dev, rxcb->paddr,
4242 msdu->len + skb_tailroom(msdu),
4243 DMA_FROM_DEVICE);
4244
4245 num_buffs_reaped[mac_id]++;
4246 total_num_buffs_reaped++;
4247 budget--;
4248
4249 if (err_info.push_reason !=
4250 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4251 dev_kfree_skb_any(msdu);
4252 continue;
4253 }
4254
4255 rxcb->err_rel_src = err_info.err_rel_src;
4256 rxcb->err_code = err_info.err_code;
4257 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4258 __skb_queue_tail(&msdu_list[mac_id], msdu);
4259 }
4260
4261 ath11k_hal_srng_access_end(ab, srng);
4262
4263 spin_unlock_bh(&srng->lock);
4264
4265 if (!total_num_buffs_reaped)
4266 goto done;
4267
4268 for (i = 0; i < ab->num_radios; i++) {
4269 if (!num_buffs_reaped[i])
4270 continue;
4271
4272 ar = ab->pdevs[i].ar;
4273 rx_ring = &ar->dp.rx_refill_buf_ring;
4274
4275 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4276 ab->hw_params.hal_params->rx_buf_rbm);
4277 }
4278
4279 rcu_read_lock();
4280 for (i = 0; i < ab->num_radios; i++) {
4281 if (!rcu_dereference(ab->pdevs_active[i])) {
4282 __skb_queue_purge(&msdu_list[i]);
4283 continue;
4284 }
4285
4286 ar = ab->pdevs[i].ar;
4287
4288 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4289 __skb_queue_purge(&msdu_list[i]);
4290 continue;
4291 }
4292
4293 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4294 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4295 }
4296 rcu_read_unlock();
4297 done:
4298 return total_num_buffs_reaped;
4299 }
4300
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4301 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4302 {
4303 struct ath11k *ar;
4304 struct dp_srng *err_ring;
4305 struct dp_rxdma_ring *rx_ring;
4306 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4307 struct hal_srng *srng;
4308 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4309 enum hal_rx_buf_return_buf_manager rbm;
4310 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4311 struct ath11k_skb_rxcb *rxcb;
4312 struct sk_buff *skb;
4313 struct hal_reo_entrance_ring *entr_ring;
4314 void *desc;
4315 int num_buf_freed = 0;
4316 int quota = budget;
4317 dma_addr_t paddr;
4318 u32 desc_bank;
4319 void *link_desc_va;
4320 int num_msdus;
4321 int i;
4322 int buf_id;
4323
4324 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4325 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4326 mac_id)];
4327 rx_ring = &ar->dp.rx_refill_buf_ring;
4328
4329 srng = &ab->hal.srng_list[err_ring->ring_id];
4330
4331 spin_lock_bh(&srng->lock);
4332
4333 ath11k_hal_srng_access_begin(ab, srng);
4334
4335 while (quota-- &&
4336 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4337 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4338
4339 entr_ring = (struct hal_reo_entrance_ring *)desc;
4340 rxdma_err_code =
4341 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4342 entr_ring->info1);
4343 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4344
4345 #if defined(__linux__)
4346 link_desc_va = link_desc_banks[desc_bank].vaddr +
4347 #elif defined(__FreeBSD__)
4348 link_desc_va = (u8 *)link_desc_banks[desc_bank].vaddr +
4349 #endif
4350 (paddr - link_desc_banks[desc_bank].paddr);
4351 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4352 msdu_cookies, &rbm);
4353
4354 for (i = 0; i < num_msdus; i++) {
4355 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4356 msdu_cookies[i]);
4357
4358 spin_lock_bh(&rx_ring->idr_lock);
4359 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4360 if (!skb) {
4361 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4362 buf_id);
4363 spin_unlock_bh(&rx_ring->idr_lock);
4364 continue;
4365 }
4366
4367 idr_remove(&rx_ring->bufs_idr, buf_id);
4368 spin_unlock_bh(&rx_ring->idr_lock);
4369
4370 rxcb = ATH11K_SKB_RXCB(skb);
4371 dma_unmap_single(ab->dev, rxcb->paddr,
4372 skb->len + skb_tailroom(skb),
4373 DMA_FROM_DEVICE);
4374 dev_kfree_skb_any(skb);
4375
4376 num_buf_freed++;
4377 }
4378
4379 ath11k_dp_rx_link_desc_return(ab, desc,
4380 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4381 }
4382
4383 ath11k_hal_srng_access_end(ab, srng);
4384
4385 spin_unlock_bh(&srng->lock);
4386
4387 if (num_buf_freed)
4388 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4389 ab->hw_params.hal_params->rx_buf_rbm);
4390
4391 return budget - quota;
4392 }
4393
ath11k_dp_process_reo_status(struct ath11k_base * ab)4394 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4395 {
4396 struct ath11k_dp *dp = &ab->dp;
4397 struct hal_srng *srng;
4398 struct dp_reo_cmd *cmd, *tmp;
4399 bool found = false;
4400 u32 *reo_desc;
4401 u16 tag;
4402 struct hal_reo_status reo_status;
4403
4404 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4405
4406 memset(&reo_status, 0, sizeof(reo_status));
4407
4408 spin_lock_bh(&srng->lock);
4409
4410 ath11k_hal_srng_access_begin(ab, srng);
4411
4412 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4413 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4414
4415 switch (tag) {
4416 case HAL_REO_GET_QUEUE_STATS_STATUS:
4417 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4418 &reo_status);
4419 break;
4420 case HAL_REO_FLUSH_QUEUE_STATUS:
4421 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4422 &reo_status);
4423 break;
4424 case HAL_REO_FLUSH_CACHE_STATUS:
4425 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4426 &reo_status);
4427 break;
4428 case HAL_REO_UNBLOCK_CACHE_STATUS:
4429 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4430 &reo_status);
4431 break;
4432 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4433 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4434 &reo_status);
4435 break;
4436 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4437 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4438 &reo_status);
4439 break;
4440 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4441 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4442 &reo_status);
4443 break;
4444 default:
4445 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4446 continue;
4447 }
4448
4449 spin_lock_bh(&dp->reo_cmd_lock);
4450 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4451 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4452 found = true;
4453 list_del(&cmd->list);
4454 break;
4455 }
4456 }
4457 spin_unlock_bh(&dp->reo_cmd_lock);
4458
4459 if (found) {
4460 cmd->handler(dp, (void *)&cmd->data,
4461 reo_status.uniform_hdr.cmd_status);
4462 kfree(cmd);
4463 }
4464
4465 found = false;
4466 }
4467
4468 ath11k_hal_srng_access_end(ab, srng);
4469
4470 spin_unlock_bh(&srng->lock);
4471 }
4472
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4473 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4474 {
4475 struct ath11k *ar = ab->pdevs[mac_id].ar;
4476
4477 ath11k_dp_rx_pdev_srng_free(ar);
4478 ath11k_dp_rxdma_pdev_buf_free(ar);
4479 }
4480
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4481 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4482 {
4483 struct ath11k *ar = ab->pdevs[mac_id].ar;
4484 struct ath11k_pdev_dp *dp = &ar->dp;
4485 u32 ring_id;
4486 int i;
4487 int ret;
4488
4489 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4490 if (ret) {
4491 ath11k_warn(ab, "failed to setup rx srngs\n");
4492 return ret;
4493 }
4494
4495 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4496 if (ret) {
4497 ath11k_warn(ab, "failed to setup rxdma ring\n");
4498 return ret;
4499 }
4500
4501 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4502 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4503 if (ret) {
4504 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4505 ret);
4506 return ret;
4507 }
4508
4509 if (ab->hw_params.rx_mac_buf_ring) {
4510 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4511 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4512 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4513 mac_id + i, HAL_RXDMA_BUF);
4514 if (ret) {
4515 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4516 i, ret);
4517 return ret;
4518 }
4519 }
4520 }
4521
4522 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4523 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4524 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4525 mac_id + i, HAL_RXDMA_DST);
4526 if (ret) {
4527 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4528 i, ret);
4529 return ret;
4530 }
4531 }
4532
4533 if (!ab->hw_params.rxdma1_enable)
4534 goto config_refill_ring;
4535
4536 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4537 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4538 mac_id, HAL_RXDMA_MONITOR_BUF);
4539 if (ret) {
4540 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4541 ret);
4542 return ret;
4543 }
4544 ret = ath11k_dp_tx_htt_srng_setup(ab,
4545 dp->rxdma_mon_dst_ring.ring_id,
4546 mac_id, HAL_RXDMA_MONITOR_DST);
4547 if (ret) {
4548 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4549 ret);
4550 return ret;
4551 }
4552 ret = ath11k_dp_tx_htt_srng_setup(ab,
4553 dp->rxdma_mon_desc_ring.ring_id,
4554 mac_id, HAL_RXDMA_MONITOR_DESC);
4555 if (ret) {
4556 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4557 ret);
4558 return ret;
4559 }
4560
4561 config_refill_ring:
4562 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4563 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4564 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4565 HAL_RXDMA_MONITOR_STATUS);
4566 if (ret) {
4567 ath11k_warn(ab,
4568 "failed to configure mon_status_refill_ring%d %d\n",
4569 i, ret);
4570 return ret;
4571 }
4572 }
4573
4574 return 0;
4575 }
4576
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4577 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4578 {
4579 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4580 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4581 *total_len -= *frag_len;
4582 } else {
4583 *frag_len = *total_len;
4584 *total_len = 0;
4585 }
4586 }
4587
4588 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4589 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4590 void *p_last_buf_addr_info,
4591 u8 mac_id)
4592 {
4593 struct ath11k_pdev_dp *dp = &ar->dp;
4594 struct dp_srng *dp_srng;
4595 void *hal_srng;
4596 void *src_srng_desc;
4597 int ret = 0;
4598
4599 if (ar->ab->hw_params.rxdma1_enable) {
4600 dp_srng = &dp->rxdma_mon_desc_ring;
4601 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4602 } else {
4603 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4604 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4605 }
4606
4607 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4608
4609 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4610
4611 if (src_srng_desc) {
4612 struct ath11k_buffer_addr *src_desc = src_srng_desc;
4613
4614 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4615 } else {
4616 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4617 "Monitor Link Desc Ring %d Full", mac_id);
4618 ret = -ENOMEM;
4619 }
4620
4621 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4622 return ret;
4623 }
4624
4625 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4626 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4627 dma_addr_t *paddr, u32 *sw_cookie,
4628 u8 *rbm,
4629 void **pp_buf_addr_info)
4630 {
4631 struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
4632 struct ath11k_buffer_addr *buf_addr_info;
4633
4634 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4635
4636 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4637
4638 *pp_buf_addr_info = (void *)buf_addr_info;
4639 }
4640
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4641 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4642 {
4643 if (skb->len > len) {
4644 skb_trim(skb, len);
4645 } else {
4646 if (skb_tailroom(skb) < len - skb->len) {
4647 if ((pskb_expand_head(skb, 0,
4648 len - skb->len - skb_tailroom(skb),
4649 GFP_ATOMIC))) {
4650 dev_kfree_skb_any(skb);
4651 return -ENOMEM;
4652 }
4653 }
4654 skb_put(skb, (len - skb->len));
4655 }
4656 return 0;
4657 }
4658
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4659 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4660 void *msdu_link_desc,
4661 struct hal_rx_msdu_list *msdu_list,
4662 u16 *num_msdus)
4663 {
4664 struct hal_rx_msdu_details *msdu_details = NULL;
4665 struct rx_msdu_desc *msdu_desc_info = NULL;
4666 struct hal_rx_msdu_link *msdu_link = NULL;
4667 int i;
4668 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4669 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4670 u8 tmp = 0;
4671
4672 msdu_link = msdu_link_desc;
4673 msdu_details = &msdu_link->msdu_link[0];
4674
4675 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4676 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4677 msdu_details[i].buf_addr_info.info0) == 0) {
4678 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4679 msdu_desc_info->info0 |= last;
4680 break;
4681 }
4682 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4683
4684 if (!i)
4685 msdu_desc_info->info0 |= first;
4686 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4687 msdu_desc_info->info0 |= last;
4688 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4689 msdu_list->msdu_info[i].msdu_len =
4690 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4691 msdu_list->sw_cookie[i] =
4692 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4693 msdu_details[i].buf_addr_info.info1);
4694 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4695 msdu_details[i].buf_addr_info.info1);
4696 msdu_list->rbm[i] = tmp;
4697 }
4698 *num_msdus = i;
4699 }
4700
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4701 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4702 u32 *rx_bufs_used)
4703 {
4704 u32 ret = 0;
4705
4706 if ((*ppdu_id < msdu_ppdu_id) &&
4707 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4708 *ppdu_id = msdu_ppdu_id;
4709 ret = msdu_ppdu_id;
4710 } else if ((*ppdu_id > msdu_ppdu_id) &&
4711 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4712 /* mon_dst is behind than mon_status
4713 * skip dst_ring and free it
4714 */
4715 *rx_bufs_used += 1;
4716 *ppdu_id = msdu_ppdu_id;
4717 ret = msdu_ppdu_id;
4718 }
4719 return ret;
4720 }
4721
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4722 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4723 bool *is_frag, u32 *total_len,
4724 u32 *frag_len, u32 *msdu_cnt)
4725 {
4726 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4727 if (!*is_frag) {
4728 *total_len = info->msdu_len;
4729 *is_frag = true;
4730 }
4731 ath11k_dp_mon_set_frag_len(total_len,
4732 frag_len);
4733 } else {
4734 if (*is_frag) {
4735 ath11k_dp_mon_set_frag_len(total_len,
4736 frag_len);
4737 } else {
4738 *frag_len = info->msdu_len;
4739 }
4740 *is_frag = false;
4741 *msdu_cnt -= 1;
4742 }
4743 }
4744
4745 /* clang stack usage explodes if this is inlined */
4746 static noinline_for_stack
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4747 u32 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4748 void *ring_entry, struct sk_buff **head_msdu,
4749 struct sk_buff **tail_msdu, u32 *npackets,
4750 u32 *ppdu_id)
4751 {
4752 struct ath11k_pdev_dp *dp = &ar->dp;
4753 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4754 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4755 struct sk_buff *msdu = NULL, *last = NULL;
4756 struct hal_rx_msdu_list msdu_list;
4757 void *p_buf_addr_info, *p_last_buf_addr_info;
4758 struct hal_rx_desc *rx_desc;
4759 void *rx_msdu_link_desc;
4760 dma_addr_t paddr;
4761 u16 num_msdus = 0;
4762 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4763 u32 rx_bufs_used = 0, i = 0;
4764 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4765 u32 total_len = 0, frag_len = 0;
4766 bool is_frag, is_first_msdu;
4767 bool drop_mpdu = false;
4768 struct ath11k_skb_rxcb *rxcb;
4769 struct hal_reo_entrance_ring *ent_desc = ring_entry;
4770 int buf_id;
4771 u32 rx_link_buf_info[2];
4772 u8 rbm;
4773
4774 if (!ar->ab->hw_params.rxdma1_enable)
4775 rx_ring = &dp->rx_refill_buf_ring;
4776
4777 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4778 &sw_cookie,
4779 &p_last_buf_addr_info, &rbm,
4780 &msdu_cnt);
4781
4782 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4783 ent_desc->info1) ==
4784 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4785 u8 rxdma_err =
4786 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4787 ent_desc->info1);
4788 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4789 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4790 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4791 drop_mpdu = true;
4792 pmon->rx_mon_stats.dest_mpdu_drop++;
4793 }
4794 }
4795
4796 is_frag = false;
4797 is_first_msdu = true;
4798
4799 do {
4800 if (pmon->mon_last_linkdesc_paddr == paddr) {
4801 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4802 return rx_bufs_used;
4803 }
4804
4805 if (ar->ab->hw_params.rxdma1_enable)
4806 rx_msdu_link_desc =
4807 #if defined(__linux__)
4808 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4809 #elif defined(__FreeBSD__)
4810 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
4811 #endif
4812 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4813 else
4814 rx_msdu_link_desc =
4815 #if defined(__linux__)
4816 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4817 #elif defined(__FreeBSD__)
4818 (u8 *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4819 #endif
4820 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4821
4822 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4823 &num_msdus);
4824
4825 for (i = 0; i < num_msdus; i++) {
4826 u32 l2_hdr_offset;
4827
4828 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4829 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4830 "i %d last_cookie %d is same\n",
4831 i, pmon->mon_last_buf_cookie);
4832 drop_mpdu = true;
4833 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4834 continue;
4835 }
4836 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4837 msdu_list.sw_cookie[i]);
4838
4839 spin_lock_bh(&rx_ring->idr_lock);
4840 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4841 spin_unlock_bh(&rx_ring->idr_lock);
4842 if (!msdu) {
4843 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4844 "msdu_pop: invalid buf_id %d\n", buf_id);
4845 goto next_msdu;
4846 }
4847 rxcb = ATH11K_SKB_RXCB(msdu);
4848 if (!rxcb->unmapped) {
4849 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4850 msdu->len +
4851 skb_tailroom(msdu),
4852 DMA_FROM_DEVICE);
4853 rxcb->unmapped = 1;
4854 }
4855 if (drop_mpdu) {
4856 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4857 "i %d drop msdu %p *ppdu_id %x\n",
4858 i, msdu, *ppdu_id);
4859 dev_kfree_skb_any(msdu);
4860 msdu = NULL;
4861 goto next_msdu;
4862 }
4863
4864 rx_desc = (struct hal_rx_desc *)msdu->data;
4865
4866 rx_pkt_offset = sizeof(struct hal_rx_desc);
4867 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4868
4869 if (is_first_msdu) {
4870 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4871 drop_mpdu = true;
4872 dev_kfree_skb_any(msdu);
4873 msdu = NULL;
4874 pmon->mon_last_linkdesc_paddr = paddr;
4875 goto next_msdu;
4876 }
4877
4878 msdu_ppdu_id =
4879 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4880
4881 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4882 ppdu_id,
4883 &rx_bufs_used)) {
4884 if (rx_bufs_used) {
4885 drop_mpdu = true;
4886 dev_kfree_skb_any(msdu);
4887 msdu = NULL;
4888 goto next_msdu;
4889 }
4890 return rx_bufs_used;
4891 }
4892 pmon->mon_last_linkdesc_paddr = paddr;
4893 is_first_msdu = false;
4894 }
4895 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4896 &is_frag, &total_len,
4897 &frag_len, &msdu_cnt);
4898 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4899
4900 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4901
4902 if (!(*head_msdu))
4903 *head_msdu = msdu;
4904 else if (last)
4905 last->next = msdu;
4906
4907 last = msdu;
4908 next_msdu:
4909 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4910 rx_bufs_used++;
4911 spin_lock_bh(&rx_ring->idr_lock);
4912 idr_remove(&rx_ring->bufs_idr, buf_id);
4913 spin_unlock_bh(&rx_ring->idr_lock);
4914 }
4915
4916 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4917
4918 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4919 &sw_cookie, &rbm,
4920 &p_buf_addr_info);
4921
4922 if (ar->ab->hw_params.rxdma1_enable) {
4923 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4924 p_last_buf_addr_info,
4925 dp->mac_id))
4926 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4927 "dp_rx_monitor_link_desc_return failed");
4928 } else {
4929 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4930 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4931 }
4932
4933 p_last_buf_addr_info = p_buf_addr_info;
4934
4935 } while (paddr && msdu_cnt);
4936
4937 if (last)
4938 last->next = NULL;
4939
4940 *tail_msdu = msdu;
4941
4942 if (msdu_cnt == 0)
4943 *npackets = 1;
4944
4945 return rx_bufs_used;
4946 }
4947
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4948 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4949 {
4950 u32 rx_pkt_offset, l2_hdr_offset;
4951
4952 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4953 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4954 (struct hal_rx_desc *)msdu->data);
4955 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4956 }
4957
4958 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4959 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4960 u32 mac_id, struct sk_buff *head_msdu,
4961 struct sk_buff *last_msdu,
4962 struct ieee80211_rx_status *rxs, bool *fcs_err)
4963 {
4964 struct ath11k_base *ab = ar->ab;
4965 struct sk_buff *msdu, *prev_buf;
4966 struct hal_rx_desc *rx_desc;
4967 char *hdr_desc;
4968 u8 *dest, decap_format;
4969 struct ieee80211_hdr_3addr *wh;
4970 struct rx_attention *rx_attention;
4971 u32 err_bitmap;
4972
4973 if (!head_msdu)
4974 goto err_merge_fail;
4975
4976 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4977 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4978 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4979
4980 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4981 *fcs_err = true;
4982
4983 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4984 return NULL;
4985
4986 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4987
4988 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4989
4990 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4991 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4992
4993 prev_buf = head_msdu;
4994 msdu = head_msdu->next;
4995
4996 while (msdu) {
4997 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4998
4999 prev_buf = msdu;
5000 msdu = msdu->next;
5001 }
5002
5003 prev_buf->next = NULL;
5004
5005 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
5006 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
5007 u8 qos_pkt = 0;
5008
5009 rx_desc = (struct hal_rx_desc *)head_msdu->data;
5010 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
5011
5012 /* Base size */
5013 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
5014
5015 if (ieee80211_is_data_qos(wh->frame_control))
5016 qos_pkt = 1;
5017
5018 msdu = head_msdu;
5019
5020 while (msdu) {
5021 ath11k_dp_rx_msdus_set_payload(ar, msdu);
5022 if (qos_pkt) {
5023 dest = skb_push(msdu, sizeof(__le16));
5024 if (!dest)
5025 goto err_merge_fail;
5026 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
5027 }
5028 prev_buf = msdu;
5029 msdu = msdu->next;
5030 }
5031 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
5032 if (!dest)
5033 goto err_merge_fail;
5034
5035 ath11k_dbg(ab, ATH11K_DBG_DATA,
5036 "mpdu_buf %p mpdu_buf->len %u",
5037 prev_buf, prev_buf->len);
5038 } else {
5039 ath11k_dbg(ab, ATH11K_DBG_DATA,
5040 "decap format %d is not supported!\n",
5041 decap_format);
5042 goto err_merge_fail;
5043 }
5044
5045 return head_msdu;
5046
5047 err_merge_fail:
5048 return NULL;
5049 }
5050
5051 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5052 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
5053 u8 *rtap_buf)
5054 {
5055 u32 rtap_len = 0;
5056
5057 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
5058 rtap_len += 2;
5059
5060 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
5061 rtap_len += 2;
5062
5063 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
5064 rtap_len += 2;
5065
5066 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
5067 rtap_len += 2;
5068
5069 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
5070 rtap_len += 2;
5071
5072 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
5073 }
5074
5075 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5076 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
5077 u8 *rtap_buf)
5078 {
5079 u32 rtap_len = 0;
5080
5081 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
5082 rtap_len += 2;
5083
5084 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
5085 rtap_len += 2;
5086
5087 rtap_buf[rtap_len] = rx_status->he_RU[0];
5088 rtap_len += 1;
5089
5090 rtap_buf[rtap_len] = rx_status->he_RU[1];
5091 rtap_len += 1;
5092
5093 rtap_buf[rtap_len] = rx_status->he_RU[2];
5094 rtap_len += 1;
5095
5096 rtap_buf[rtap_len] = rx_status->he_RU[3];
5097 }
5098
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)5099 static void ath11k_update_radiotap(struct ath11k *ar,
5100 struct hal_rx_mon_ppdu_info *ppduinfo,
5101 struct sk_buff *mon_skb,
5102 struct ieee80211_rx_status *rxs)
5103 {
5104 struct ieee80211_supported_band *sband;
5105 u8 *ptr = NULL;
5106
5107 rxs->flag |= RX_FLAG_MACTIME_START;
5108 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
5109
5110 if (ppduinfo->nss)
5111 rxs->nss = ppduinfo->nss;
5112
5113 if (ppduinfo->he_mu_flags) {
5114 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
5115 rxs->encoding = RX_ENC_HE;
5116 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5117 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5118 } else if (ppduinfo->he_flags) {
5119 rxs->flag |= RX_FLAG_RADIOTAP_HE;
5120 rxs->encoding = RX_ENC_HE;
5121 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5122 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5123 rxs->rate_idx = ppduinfo->rate;
5124 } else if (ppduinfo->vht_flags) {
5125 rxs->encoding = RX_ENC_VHT;
5126 rxs->rate_idx = ppduinfo->rate;
5127 } else if (ppduinfo->ht_flags) {
5128 rxs->encoding = RX_ENC_HT;
5129 rxs->rate_idx = ppduinfo->rate;
5130 } else {
5131 rxs->encoding = RX_ENC_LEGACY;
5132 sband = &ar->mac.sbands[rxs->band];
5133 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5134 ppduinfo->cck_flag);
5135 }
5136
5137 rxs->mactime = ppduinfo->tsft;
5138 }
5139
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5140 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5141 struct sk_buff *head_msdu,
5142 struct hal_rx_mon_ppdu_info *ppduinfo,
5143 struct sk_buff *tail_msdu,
5144 struct napi_struct *napi)
5145 {
5146 struct ath11k_pdev_dp *dp = &ar->dp;
5147 struct sk_buff *mon_skb, *skb_next, *header;
5148 struct ieee80211_rx_status *rxs = &dp->rx_status;
5149 bool fcs_err = false;
5150
5151 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5152 tail_msdu, rxs, &fcs_err);
5153
5154 if (!mon_skb)
5155 goto mon_deliver_fail;
5156
5157 header = mon_skb;
5158
5159 rxs->flag = 0;
5160
5161 if (fcs_err)
5162 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5163
5164 do {
5165 skb_next = mon_skb->next;
5166 if (!skb_next)
5167 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5168 else
5169 rxs->flag |= RX_FLAG_AMSDU_MORE;
5170
5171 if (mon_skb == header) {
5172 header = NULL;
5173 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5174 } else {
5175 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5176 }
5177 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5178 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5179
5180 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5181 mon_skb = skb_next;
5182 } while (mon_skb);
5183 rxs->flag = 0;
5184
5185 return 0;
5186
5187 mon_deliver_fail:
5188 mon_skb = head_msdu;
5189 while (mon_skb) {
5190 skb_next = mon_skb->next;
5191 dev_kfree_skb_any(mon_skb);
5192 mon_skb = skb_next;
5193 }
5194 return -EINVAL;
5195 }
5196
5197 /* The destination ring processing is stuck if the destination is not
5198 * moving while status ring moves 16 PPDU. The destination ring processing
5199 * skips this destination ring PPDU as a workaround.
5200 */
5201 #define MON_DEST_RING_STUCK_MAX_CNT 16
5202
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5203 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5204 u32 quota, struct napi_struct *napi)
5205 {
5206 struct ath11k_pdev_dp *dp = &ar->dp;
5207 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5208 const struct ath11k_hw_hal_params *hal_params;
5209 void *ring_entry;
5210 struct hal_srng *mon_dst_srng;
5211 u32 ppdu_id;
5212 u32 rx_bufs_used;
5213 u32 ring_id;
5214 struct ath11k_pdev_mon_stats *rx_mon_stats;
5215 u32 npackets = 0;
5216 u32 mpdu_rx_bufs_used;
5217
5218 if (ar->ab->hw_params.rxdma1_enable)
5219 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5220 else
5221 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5222
5223 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5224
5225 spin_lock_bh(&pmon->mon_lock);
5226
5227 spin_lock_bh(&mon_dst_srng->lock);
5228 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5229
5230 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5231 rx_bufs_used = 0;
5232 rx_mon_stats = &pmon->rx_mon_stats;
5233
5234 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5235 struct sk_buff *head_msdu, *tail_msdu;
5236
5237 head_msdu = NULL;
5238 tail_msdu = NULL;
5239
5240 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5241 &head_msdu,
5242 &tail_msdu,
5243 &npackets, &ppdu_id);
5244
5245 rx_bufs_used += mpdu_rx_bufs_used;
5246
5247 if (mpdu_rx_bufs_used) {
5248 dp->mon_dest_ring_stuck_cnt = 0;
5249 } else {
5250 dp->mon_dest_ring_stuck_cnt++;
5251 rx_mon_stats->dest_mon_not_reaped++;
5252 }
5253
5254 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5255 rx_mon_stats->dest_mon_stuck++;
5256 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5257 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5258 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5259 dp->mon_dest_ring_stuck_cnt,
5260 rx_mon_stats->dest_mon_not_reaped,
5261 rx_mon_stats->dest_mon_stuck);
5262 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5263 continue;
5264 }
5265
5266 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5267 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5268 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5269 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5270 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5271 rx_mon_stats->dest_mon_not_reaped,
5272 rx_mon_stats->dest_mon_stuck);
5273 break;
5274 }
5275 if (head_msdu && tail_msdu) {
5276 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5277 &pmon->mon_ppdu_info,
5278 tail_msdu, napi);
5279 rx_mon_stats->dest_mpdu_done++;
5280 }
5281
5282 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5283 mon_dst_srng);
5284 }
5285 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5286 spin_unlock_bh(&mon_dst_srng->lock);
5287
5288 spin_unlock_bh(&pmon->mon_lock);
5289
5290 if (rx_bufs_used) {
5291 rx_mon_stats->dest_ppdu_done++;
5292 hal_params = ar->ab->hw_params.hal_params;
5293
5294 if (ar->ab->hw_params.rxdma1_enable)
5295 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5296 &dp->rxdma_mon_buf_ring,
5297 rx_bufs_used,
5298 hal_params->rx_buf_rbm);
5299 else
5300 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5301 &dp->rx_refill_buf_ring,
5302 rx_bufs_used,
5303 hal_params->rx_buf_rbm);
5304 }
5305 }
5306
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5307 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5308 struct napi_struct *napi, int budget)
5309 {
5310 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5311 enum hal_rx_mon_status hal_status;
5312 struct sk_buff *skb;
5313 struct sk_buff_head skb_list;
5314 struct ath11k_peer *peer;
5315 struct ath11k_sta *arsta;
5316 int num_buffs_reaped = 0;
5317 u32 rx_buf_sz;
5318 u16 log_type;
5319 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5320 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5321 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5322
5323 __skb_queue_head_init(&skb_list);
5324
5325 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5326 &skb_list);
5327 if (!num_buffs_reaped)
5328 goto exit;
5329
5330 memset(ppdu_info, 0, sizeof(*ppdu_info));
5331 ppdu_info->peer_id = HAL_INVALID_PEERID;
5332
5333 while ((skb = __skb_dequeue(&skb_list))) {
5334 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5335 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5336 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5337 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5338 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5339 rx_buf_sz = DP_RX_BUFFER_SIZE;
5340 } else {
5341 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5342 rx_buf_sz = 0;
5343 }
5344
5345 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5346 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5347
5348 memset(ppdu_info, 0, sizeof(*ppdu_info));
5349 ppdu_info->peer_id = HAL_INVALID_PEERID;
5350 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5351
5352 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5353 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5354 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5355 rx_mon_stats->status_ppdu_done++;
5356 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5357 if (!ab->hw_params.full_monitor_mode) {
5358 ath11k_dp_rx_mon_dest_process(ar, mac_id,
5359 budget, napi);
5360 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5361 }
5362 }
5363
5364 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5365 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5366 dev_kfree_skb_any(skb);
5367 continue;
5368 }
5369
5370 rcu_read_lock();
5371 spin_lock_bh(&ab->base_lock);
5372 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5373
5374 if (!peer || !peer->sta) {
5375 ath11k_dbg(ab, ATH11K_DBG_DATA,
5376 "failed to find the peer with peer_id %d\n",
5377 ppdu_info->peer_id);
5378 goto next_skb;
5379 }
5380
5381 arsta = ath11k_sta_to_arsta(peer->sta);
5382 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5383
5384 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5385 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5386
5387 next_skb:
5388 spin_unlock_bh(&ab->base_lock);
5389 rcu_read_unlock();
5390
5391 dev_kfree_skb_any(skb);
5392 memset(ppdu_info, 0, sizeof(*ppdu_info));
5393 ppdu_info->peer_id = HAL_INVALID_PEERID;
5394 }
5395 exit:
5396 return num_buffs_reaped;
5397 }
5398
5399 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5400 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5401 void *ring_entry, struct sk_buff **head_msdu,
5402 struct sk_buff **tail_msdu,
5403 struct hal_sw_mon_ring_entries *sw_mon_entries)
5404 {
5405 struct ath11k_pdev_dp *dp = &ar->dp;
5406 struct ath11k_mon_data *pmon = &dp->mon_data;
5407 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5408 struct sk_buff *msdu = NULL, *last = NULL;
5409 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5410 struct hal_rx_msdu_list msdu_list;
5411 struct hal_rx_desc *rx_desc;
5412 struct ath11k_skb_rxcb *rxcb;
5413 void *rx_msdu_link_desc;
5414 void *p_buf_addr_info, *p_last_buf_addr_info;
5415 int buf_id, i = 0;
5416 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5417 u32 rx_bufs_used = 0, msdu_cnt = 0;
5418 u32 total_len = 0, frag_len = 0, sw_cookie;
5419 u16 num_msdus = 0;
5420 u8 rxdma_err, rbm;
5421 bool is_frag, is_first_msdu;
5422 bool drop_mpdu = false;
5423
5424 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5425
5426 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5427 sw_mon_entries->end_of_ppdu = false;
5428 sw_mon_entries->drop_ppdu = false;
5429 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5430 msdu_cnt = sw_mon_entries->msdu_cnt;
5431
5432 sw_mon_entries->end_of_ppdu =
5433 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5434 if (sw_mon_entries->end_of_ppdu)
5435 return rx_bufs_used;
5436
5437 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5438 sw_desc->info0) ==
5439 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5440 rxdma_err =
5441 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5442 sw_desc->info0);
5443 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5444 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5445 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5446 pmon->rx_mon_stats.dest_mpdu_drop++;
5447 drop_mpdu = true;
5448 }
5449 }
5450
5451 is_frag = false;
5452 is_first_msdu = true;
5453
5454 do {
5455 rx_msdu_link_desc =
5456 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5457 (sw_mon_entries->mon_dst_paddr -
5458 pmon->link_desc_banks[sw_cookie].paddr);
5459
5460 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5461 &num_msdus);
5462
5463 for (i = 0; i < num_msdus; i++) {
5464 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5465 msdu_list.sw_cookie[i]);
5466
5467 spin_lock_bh(&rx_ring->idr_lock);
5468 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5469 if (!msdu) {
5470 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5471 "full mon msdu_pop: invalid buf_id %d\n",
5472 buf_id);
5473 spin_unlock_bh(&rx_ring->idr_lock);
5474 goto next_msdu;
5475 }
5476 idr_remove(&rx_ring->bufs_idr, buf_id);
5477 spin_unlock_bh(&rx_ring->idr_lock);
5478
5479 rxcb = ATH11K_SKB_RXCB(msdu);
5480 if (!rxcb->unmapped) {
5481 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5482 msdu->len +
5483 skb_tailroom(msdu),
5484 DMA_FROM_DEVICE);
5485 rxcb->unmapped = 1;
5486 }
5487 if (drop_mpdu) {
5488 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5489 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5490 i, msdu, sw_mon_entries->ppdu_id);
5491 dev_kfree_skb_any(msdu);
5492 msdu_cnt--;
5493 goto next_msdu;
5494 }
5495
5496 rx_desc = (struct hal_rx_desc *)msdu->data;
5497
5498 rx_pkt_offset = sizeof(struct hal_rx_desc);
5499 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5500
5501 if (is_first_msdu) {
5502 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5503 drop_mpdu = true;
5504 dev_kfree_skb_any(msdu);
5505 msdu = NULL;
5506 goto next_msdu;
5507 }
5508 is_first_msdu = false;
5509 }
5510
5511 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5512 &is_frag, &total_len,
5513 &frag_len, &msdu_cnt);
5514
5515 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5516
5517 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5518
5519 if (!(*head_msdu))
5520 *head_msdu = msdu;
5521 else if (last)
5522 last->next = msdu;
5523
5524 last = msdu;
5525 next_msdu:
5526 rx_bufs_used++;
5527 }
5528
5529 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5530 &sw_mon_entries->mon_dst_paddr,
5531 &sw_mon_entries->mon_dst_sw_cookie,
5532 &rbm,
5533 &p_buf_addr_info);
5534
5535 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5536 p_last_buf_addr_info,
5537 dp->mac_id))
5538 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5539 "full mon: dp_rx_monitor_link_desc_return failed\n");
5540
5541 p_last_buf_addr_info = p_buf_addr_info;
5542
5543 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5544
5545 if (last)
5546 last->next = NULL;
5547
5548 *tail_msdu = msdu;
5549
5550 return rx_bufs_used;
5551 }
5552
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5553 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5554 struct dp_full_mon_mpdu *mon_mpdu,
5555 struct sk_buff *head,
5556 struct sk_buff *tail)
5557 {
5558 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5559 if (!mon_mpdu)
5560 return -ENOMEM;
5561
5562 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5563 mon_mpdu->head = head;
5564 mon_mpdu->tail = tail;
5565
5566 return 0;
5567 }
5568
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5569 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5570 struct dp_full_mon_mpdu *mon_mpdu)
5571 {
5572 struct dp_full_mon_mpdu *tmp;
5573 struct sk_buff *tmp_msdu, *skb_next;
5574
5575 if (list_empty(&dp->dp_full_mon_mpdu_list))
5576 return;
5577
5578 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5579 list_del(&mon_mpdu->list);
5580
5581 tmp_msdu = mon_mpdu->head;
5582 while (tmp_msdu) {
5583 skb_next = tmp_msdu->next;
5584 dev_kfree_skb_any(tmp_msdu);
5585 tmp_msdu = skb_next;
5586 }
5587
5588 kfree(mon_mpdu);
5589 }
5590 }
5591
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5592 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5593 int mac_id,
5594 struct ath11k_mon_data *pmon,
5595 struct napi_struct *napi)
5596 {
5597 struct ath11k_pdev_mon_stats *rx_mon_stats;
5598 struct dp_full_mon_mpdu *tmp;
5599 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5600 struct sk_buff *head_msdu, *tail_msdu;
5601 struct ath11k_base *ab = ar->ab;
5602 struct ath11k_dp *dp = &ab->dp;
5603 int ret;
5604
5605 rx_mon_stats = &pmon->rx_mon_stats;
5606
5607 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5608 list_del(&mon_mpdu->list);
5609 head_msdu = mon_mpdu->head;
5610 tail_msdu = mon_mpdu->tail;
5611 if (head_msdu && tail_msdu) {
5612 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5613 &pmon->mon_ppdu_info,
5614 tail_msdu, napi);
5615 rx_mon_stats->dest_mpdu_done++;
5616 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5617 }
5618 kfree(mon_mpdu);
5619 }
5620
5621 return ret;
5622 }
5623
5624 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5625 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5626 struct napi_struct *napi, int budget)
5627 {
5628 struct ath11k *ar = ab->pdevs[mac_id].ar;
5629 struct ath11k_pdev_dp *dp = &ar->dp;
5630 struct ath11k_mon_data *pmon = &dp->mon_data;
5631 struct hal_sw_mon_ring_entries *sw_mon_entries;
5632 int quota = 0, work = 0, count;
5633
5634 sw_mon_entries = &pmon->sw_mon_entries;
5635
5636 while (pmon->hold_mon_dst_ring) {
5637 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5638 napi, 1);
5639 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5640 count = sw_mon_entries->status_buf_count;
5641 if (count > 1) {
5642 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5643 napi, count);
5644 }
5645
5646 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5647 pmon, napi);
5648 pmon->hold_mon_dst_ring = false;
5649 } else if (!pmon->mon_status_paddr ||
5650 pmon->buf_state == DP_MON_STATUS_LEAD) {
5651 sw_mon_entries->drop_ppdu = true;
5652 pmon->hold_mon_dst_ring = false;
5653 }
5654
5655 if (!quota)
5656 break;
5657
5658 work += quota;
5659 }
5660
5661 if (sw_mon_entries->drop_ppdu)
5662 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5663
5664 return work;
5665 }
5666
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5667 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5668 struct napi_struct *napi, int budget)
5669 {
5670 struct ath11k *ar = ab->pdevs[mac_id].ar;
5671 struct ath11k_pdev_dp *dp = &ar->dp;
5672 struct ath11k_mon_data *pmon = &dp->mon_data;
5673 struct hal_sw_mon_ring_entries *sw_mon_entries;
5674 struct ath11k_pdev_mon_stats *rx_mon_stats;
5675 struct sk_buff *head_msdu, *tail_msdu;
5676 struct hal_srng *mon_dst_srng;
5677 void *ring_entry;
5678 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5679 int quota = 0, ret;
5680 bool break_dst_ring = false;
5681
5682 spin_lock_bh(&pmon->mon_lock);
5683
5684 sw_mon_entries = &pmon->sw_mon_entries;
5685 rx_mon_stats = &pmon->rx_mon_stats;
5686
5687 if (pmon->hold_mon_dst_ring) {
5688 spin_unlock_bh(&pmon->mon_lock);
5689 goto reap_status_ring;
5690 }
5691
5692 mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5693 spin_lock_bh(&mon_dst_srng->lock);
5694
5695 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5696 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5697 head_msdu = NULL;
5698 tail_msdu = NULL;
5699
5700 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5701 &head_msdu,
5702 &tail_msdu,
5703 sw_mon_entries);
5704 rx_bufs_used += mpdu_rx_bufs_used;
5705
5706 if (!sw_mon_entries->end_of_ppdu) {
5707 if (head_msdu) {
5708 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5709 pmon->mon_mpdu,
5710 head_msdu,
5711 tail_msdu);
5712 if (ret)
5713 break_dst_ring = true;
5714 }
5715
5716 goto next_entry;
5717 } else {
5718 if (!sw_mon_entries->ppdu_id &&
5719 !sw_mon_entries->mon_status_paddr) {
5720 break_dst_ring = true;
5721 goto next_entry;
5722 }
5723 }
5724
5725 rx_mon_stats->dest_ppdu_done++;
5726 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5727 pmon->buf_state = DP_MON_STATUS_LAG;
5728 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5729 pmon->hold_mon_dst_ring = true;
5730 next_entry:
5731 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5732 mon_dst_srng);
5733 if (break_dst_ring)
5734 break;
5735 }
5736
5737 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5738 spin_unlock_bh(&mon_dst_srng->lock);
5739 spin_unlock_bh(&pmon->mon_lock);
5740
5741 if (rx_bufs_used) {
5742 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5743 &dp->rxdma_mon_buf_ring,
5744 rx_bufs_used,
5745 HAL_RX_BUF_RBM_SW3_BM);
5746 }
5747
5748 reap_status_ring:
5749 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5750 napi, budget);
5751
5752 return quota;
5753 }
5754
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5755 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5756 struct napi_struct *napi, int budget)
5757 {
5758 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5759 int ret = 0;
5760
5761 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5762 ab->hw_params.full_monitor_mode)
5763 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5764 else
5765 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5766
5767 return ret;
5768 }
5769
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5770 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5771 {
5772 struct ath11k_pdev_dp *dp = &ar->dp;
5773 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5774
5775 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5776
5777 memset(&pmon->rx_mon_stats, 0,
5778 sizeof(pmon->rx_mon_stats));
5779 return 0;
5780 }
5781
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5782 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5783 {
5784 struct ath11k_pdev_dp *dp = &ar->dp;
5785 struct ath11k_mon_data *pmon = &dp->mon_data;
5786 struct hal_srng *mon_desc_srng = NULL;
5787 struct dp_srng *dp_srng;
5788 int ret = 0;
5789 u32 n_link_desc = 0;
5790
5791 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5792 if (ret) {
5793 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5794 return ret;
5795 }
5796
5797 /* if rxdma1_enable is false, no need to setup
5798 * rxdma_mon_desc_ring.
5799 */
5800 if (!ar->ab->hw_params.rxdma1_enable)
5801 return 0;
5802
5803 dp_srng = &dp->rxdma_mon_desc_ring;
5804 n_link_desc = dp_srng->size /
5805 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5806 mon_desc_srng =
5807 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5808
5809 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5810 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5811 n_link_desc);
5812 if (ret) {
5813 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5814 return ret;
5815 }
5816 pmon->mon_last_linkdesc_paddr = 0;
5817 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5818 spin_lock_init(&pmon->mon_lock);
5819
5820 return 0;
5821 }
5822
ath11k_dp_mon_link_free(struct ath11k * ar)5823 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5824 {
5825 struct ath11k_pdev_dp *dp = &ar->dp;
5826 struct ath11k_mon_data *pmon = &dp->mon_data;
5827
5828 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5829 HAL_RXDMA_MONITOR_DESC,
5830 &dp->rxdma_mon_desc_ring);
5831 return 0;
5832 }
5833
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5834 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5835 {
5836 ath11k_dp_mon_link_free(ar);
5837 return 0;
5838 }
5839
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5840 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5841 {
5842 /* start reap timer */
5843 mod_timer(&ab->mon_reap_timer,
5844 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5845
5846 return 0;
5847 }
5848
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5849 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5850 {
5851 int ret;
5852
5853 if (stop_timer)
5854 timer_delete_sync(&ab->mon_reap_timer);
5855
5856 /* reap all the monitor related rings */
5857 ret = ath11k_dp_purge_mon_ring(ab);
5858 if (ret) {
5859 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5860 return ret;
5861 }
5862
5863 return 0;
5864 }
5865