1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 struct hal_rx_desc *desc)
33 {
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 return HAL_ENCRYPT_TYPE_OPEN;
36
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 struct hal_rx_desc *desc)
42 {
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 struct hal_rx_desc *desc)
49 {
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 struct hal_rx_desc *desc)
56 {
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 struct hal_rx_desc *desc)
63 {
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 struct hal_rx_desc *desc)
69 {
70 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 struct sk_buff *skb)
75 {
76 struct ieee80211_hdr *hdr;
77
78 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 return ieee80211_has_morefrags(hdr->frame_control);
80 }
81
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 struct sk_buff *skb)
84 {
85 struct ieee80211_hdr *hdr;
86
87 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 struct hal_rx_desc *desc)
93 {
94 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 struct hal_rx_desc *desc)
99 {
100 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 __le32_to_cpu(attn->info2));
107 }
108
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 __le32_to_cpu(attn->info1));
113 }
114
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 __le32_to_cpu(attn->info1));
119 }
120
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 __le32_to_cpu(attn->info2)) ==
125 RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 u32 info = __le32_to_cpu(attn->info1);
131 u32 errmap = 0;
132
133 if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 errmap |= DP_RX_MPDU_ERR_FCS;
135
136 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 errmap |= DP_RX_MPDU_ERR_DECRYPT;
138
139 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141
142 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144
145 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147
148 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150
151 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153
154 return errmap;
155 }
156
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 struct hal_rx_desc *desc)
159 {
160 struct rx_attention *rx_attention;
161 u32 errmap;
162
163 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165
166 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 struct hal_rx_desc *desc)
171 {
172 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 struct hal_rx_desc *desc)
177 {
178 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 struct hal_rx_desc *desc)
183 {
184 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 struct hal_rx_desc *desc)
189 {
190 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 struct hal_rx_desc *desc)
195 {
196 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 struct hal_rx_desc *desc)
201 {
202 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 struct hal_rx_desc *desc)
207 {
208 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 struct hal_rx_desc *desc)
213 {
214 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 struct hal_rx_desc *desc)
219 {
220 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 struct hal_rx_desc *desc)
225 {
226 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 struct hal_rx_desc *desc)
231 {
232 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 struct hal_rx_desc *desc)
237 {
238 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 struct hal_rx_desc *fdesc,
243 struct hal_rx_desc *ldesc)
244 {
245 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 __le32_to_cpu(attn->info1));
252 }
253
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 struct hal_rx_desc *rx_desc)
256 {
257 u8 *rx_pkt_hdr;
258
259 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260
261 return rx_pkt_hdr;
262 }
263
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 struct hal_rx_desc *rx_desc)
266 {
267 u32 tlv_tag;
268
269 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270
271 return tlv_tag == HAL_RX_MPDU_START;
272 }
273
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 struct hal_rx_desc *rx_desc)
276 {
277 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 struct hal_rx_desc *desc,
282 u16 len)
283 {
284 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 struct hal_rx_desc *desc)
289 {
290 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291
292 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 __le32_to_cpu(attn->info1)));
295 }
296
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 struct hal_rx_desc *desc)
299 {
300 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 struct hal_rx_desc *desc)
305 {
306 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
312 int i;
313
314 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
315 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316
317 mod_timer(&ab->mon_reap_timer, jiffies +
318 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 int i, reaped = 0;
324 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325
326 do {
327 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
328 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 NULL,
330 DP_MON_SERVICE_BUDGET);
331
332 /* nothing more to reap */
333 if (reaped < DP_MON_SERVICE_BUDGET)
334 return 0;
335
336 } while (time_before(jiffies, timeout));
337
338 ath11k_warn(ab, "dp mon ring purge timeout");
339
340 return -ETIMEDOUT;
341 }
342
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 struct dp_rxdma_ring *rx_ring,
346 int req_entries,
347 enum hal_rx_buf_return_buf_manager mgr)
348 {
349 struct hal_srng *srng;
350 u32 *desc;
351 struct sk_buff *skb;
352 int num_free;
353 int num_remain;
354 int buf_id;
355 u32 cookie;
356 dma_addr_t paddr;
357
358 req_entries = min(req_entries, rx_ring->bufs_max);
359
360 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361
362 spin_lock_bh(&srng->lock);
363
364 ath11k_hal_srng_access_begin(ab, srng);
365
366 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 req_entries = num_free;
369
370 req_entries = min(num_free, req_entries);
371 num_remain = req_entries;
372
373 while (num_remain > 0) {
374 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 DP_RX_BUFFER_ALIGN_SIZE);
376 if (!skb)
377 break;
378
379 if (!IS_ALIGNED((unsigned long)skb->data,
380 DP_RX_BUFFER_ALIGN_SIZE)) {
381 skb_pull(skb,
382 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 skb->data);
384 }
385
386 paddr = dma_map_single(ab->dev, skb->data,
387 skb->len + skb_tailroom(skb),
388 DMA_FROM_DEVICE);
389 if (dma_mapping_error(ab->dev, paddr))
390 goto fail_free_skb;
391
392 spin_lock_bh(&rx_ring->idr_lock);
393 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 spin_unlock_bh(&rx_ring->idr_lock);
396 if (buf_id <= 0)
397 goto fail_dma_unmap;
398
399 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 if (!desc)
401 goto fail_idr_remove;
402
403 ATH11K_SKB_RXCB(skb)->paddr = paddr;
404
405 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407
408 num_remain--;
409
410 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 }
412
413 ath11k_hal_srng_access_end(ab, srng);
414
415 spin_unlock_bh(&srng->lock);
416
417 return req_entries - num_remain;
418
419 fail_idr_remove:
420 spin_lock_bh(&rx_ring->idr_lock);
421 idr_remove(&rx_ring->bufs_idr, buf_id);
422 spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 DMA_FROM_DEVICE);
426 fail_free_skb:
427 dev_kfree_skb_any(skb);
428
429 ath11k_hal_srng_access_end(ab, srng);
430
431 spin_unlock_bh(&srng->lock);
432
433 return req_entries - num_remain;
434 }
435
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring)
438 {
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 return 0;
457 }
458
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 struct ath11k_pdev_dp *dp = &ar->dp;
462 struct ath11k_base *ab = ar->ab;
463 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 int i;
465
466 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467
468 rx_ring = &dp->rxdma_mon_buf_ring;
469 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470
471 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
472 rx_ring = &dp->rx_mon_status_refill_ring[i];
473 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 }
475
476 return 0;
477 }
478
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 struct dp_rxdma_ring *rx_ring,
481 u32 ringtype)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 int num_entries;
485
486 num_entries = rx_ring->refill_buf_ring.size /
487 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488
489 rx_ring->bufs_max = num_entries;
490 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 ar->ab->hw_params.hal_params->rx_buf_rbm);
492 return 0;
493 }
494
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 struct ath11k_pdev_dp *dp = &ar->dp;
498 struct ath11k_base *ab = ar->ab;
499 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 int i;
501
502 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503
504 if (ar->ab->hw_params.rxdma1_enable) {
505 rx_ring = &dp->rxdma_mon_buf_ring;
506 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 }
508
509 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
510 rx_ring = &dp->rx_mon_status_refill_ring[i];
511 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 }
513
514 return 0;
515 }
516
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 int i;
522
523 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524
525 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
526 if (ab->hw_params.rx_mac_buf_ring)
527 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528
529 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 ath11k_dp_srng_cleanup(ab,
531 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 }
533
534 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 struct ath11k_dp *dp = &ab->dp;
540 int i;
541
542 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 struct ath11k_dp *dp = &ab->dp;
549 int ret;
550 int i;
551
552 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 HAL_REO_DST, i, 0,
555 DP_REO_DST_RING_SIZE);
556 if (ret) {
557 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 goto err_reo_cleanup;
559 }
560 }
561
562 return 0;
563
564 err_reo_cleanup:
565 ath11k_dp_pdev_reo_cleanup(ab);
566
567 return ret;
568 }
569
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 struct ath11k_pdev_dp *dp = &ar->dp;
573 struct ath11k_base *ab = ar->ab;
574 struct dp_srng *srng = NULL;
575 int i;
576 int ret;
577
578 ret = ath11k_dp_srng_setup(ar->ab,
579 &dp->rx_refill_buf_ring.refill_buf_ring,
580 HAL_RXDMA_BUF, 0,
581 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 if (ret) {
583 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 return ret;
585 }
586
587 if (ar->ab->hw_params.rx_mac_buf_ring) {
588 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
589 ret = ath11k_dp_srng_setup(ar->ab,
590 &dp->rx_mac_buf_ring[i],
591 HAL_RXDMA_BUF, 1,
592 dp->mac_id + i, 1024);
593 if (ret) {
594 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 i);
596 return ret;
597 }
598 }
599 }
600
601 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
602 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 HAL_RXDMA_DST, 0, dp->mac_id + i,
604 DP_RXDMA_ERR_DST_RING_SIZE);
605 if (ret) {
606 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 return ret;
608 }
609 }
610
611 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
612 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 ret = ath11k_dp_srng_setup(ar->ab,
614 srng,
615 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 DP_RXDMA_MON_STATUS_RING_SIZE);
617 if (ret) {
618 ath11k_warn(ar->ab,
619 "failed to setup rx_mon_status_refill_ring %d\n", i);
620 return ret;
621 }
622 }
623
624 /* if rxdma1_enable is false, then it doesn't need
625 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 * and rxdma_mon_desc_ring.
627 * init reap timer for QCA6390.
628 */
629 if (!ar->ab->hw_params.rxdma1_enable) {
630 //init mon status buffer reap timer
631 timer_setup(&ar->ab->mon_reap_timer,
632 ath11k_dp_service_mon_ring, 0);
633 return 0;
634 }
635
636 ret = ath11k_dp_srng_setup(ar->ab,
637 &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 if (ret) {
641 ath11k_warn(ar->ab,
642 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 return ret;
644 }
645
646 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 DP_RXDMA_MONITOR_DST_RING_SIZE);
649 if (ret) {
650 ath11k_warn(ar->ab,
651 "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 return ret;
653 }
654
655 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 if (ret) {
659 ath11k_warn(ar->ab,
660 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 struct ath11k_dp *dp = &ab->dp;
670 struct dp_reo_cmd *cmd, *tmp;
671 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 struct dp_rx_tid *rx_tid;
673
674 spin_lock_bh(&dp->reo_cmd_lock);
675 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 list_del(&cmd->list);
677 rx_tid = &cmd->data;
678 if (rx_tid->vaddr_unaligned) {
679 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
680 rx_tid->vaddr_unaligned,
681 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
682 rx_tid->vaddr_unaligned = NULL;
683 }
684 kfree(cmd);
685 }
686
687 list_for_each_entry_safe(cmd_cache, tmp_cache,
688 &dp->reo_cmd_cache_flush_list, list) {
689 list_del(&cmd_cache->list);
690 dp->reo_cmd_cache_flush_count--;
691 rx_tid = &cmd_cache->data;
692 if (rx_tid->vaddr_unaligned) {
693 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
694 rx_tid->vaddr_unaligned,
695 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
696 rx_tid->vaddr_unaligned = NULL;
697 }
698 kfree(cmd_cache);
699 }
700 spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 enum hal_reo_cmd_status status)
705 {
706 struct dp_rx_tid *rx_tid = ctx;
707
708 if (status != HAL_REO_CMD_SUCCESS)
709 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 rx_tid->tid, status);
711 if (rx_tid->vaddr_unaligned) {
712 dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
713 rx_tid->vaddr_unaligned,
714 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
715 rx_tid->vaddr_unaligned = NULL;
716 }
717 }
718
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 struct dp_rx_tid *rx_tid)
721 {
722 struct ath11k_hal_reo_cmd cmd = {0};
723 unsigned long tot_desc_sz, desc_sz;
724 int ret;
725
726 tot_desc_sz = rx_tid->size;
727 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728
729 while (tot_desc_sz > desc_sz) {
730 tot_desc_sz -= desc_sz;
731 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 NULL);
736 if (ret)
737 ath11k_warn(ab,
738 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 rx_tid->tid, ret);
740 }
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 HAL_REO_CMD_FLUSH_CACHE,
748 &cmd, ath11k_dp_reo_cmd_free);
749 if (ret) {
750 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 rx_tid->tid, ret);
752 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
753 rx_tid->vaddr_unaligned,
754 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
755 rx_tid->vaddr_unaligned = NULL;
756 }
757 }
758
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 enum hal_reo_cmd_status status)
761 {
762 struct ath11k_base *ab = dp->ab;
763 struct dp_rx_tid *rx_tid = ctx;
764 struct dp_reo_cache_flush_elem *elem, *tmp;
765
766 if (status == HAL_REO_CMD_DRAIN) {
767 goto free_desc;
768 } else if (status != HAL_REO_CMD_SUCCESS) {
769 /* Shouldn't happen! Cleanup in case of other failure? */
770 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 rx_tid->tid, status);
772 return;
773 }
774
775 elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
776 if (!elem)
777 goto free_desc;
778
779 elem->ts = jiffies;
780 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781
782 spin_lock_bh(&dp->reo_cmd_lock);
783 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 dp->reo_cmd_cache_flush_count++;
785
786 /* Flush and invalidate aged REO desc from HW cache */
787 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 list) {
789 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 time_after(jiffies, elem->ts +
791 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 list_del(&elem->list);
793 dp->reo_cmd_cache_flush_count--;
794 spin_unlock_bh(&dp->reo_cmd_lock);
795
796 ath11k_dp_reo_cache_flush(ab, &elem->data);
797 kfree(elem);
798 spin_lock_bh(&dp->reo_cmd_lock);
799 }
800 }
801 spin_unlock_bh(&dp->reo_cmd_lock);
802
803 return;
804 free_desc:
805 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
806 rx_tid->vaddr_unaligned,
807 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
808 rx_tid->vaddr_unaligned = NULL;
809 }
810
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 struct ath11k_peer *peer, u8 tid)
813 {
814 struct ath11k_hal_reo_cmd cmd = {0};
815 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 int ret;
817
818 if (!rx_tid->active)
819 return;
820
821 rx_tid->active = false;
822
823 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 ath11k_dp_rx_tid_del_func);
830 if (ret) {
831 if (ret != -ESHUTDOWN)
832 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 tid, ret);
834 dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
835 rx_tid->vaddr_unaligned,
836 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
837 rx_tid->vaddr_unaligned = NULL;
838 }
839
840 rx_tid->paddr = 0;
841 rx_tid->paddr_unaligned = 0;
842 rx_tid->size = 0;
843 rx_tid->unaligned_size = 0;
844 }
845
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)846 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
847 u32 *link_desc,
848 enum hal_wbm_rel_bm_act action)
849 {
850 struct ath11k_dp *dp = &ab->dp;
851 struct hal_srng *srng;
852 u32 *desc;
853 int ret = 0;
854
855 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
856
857 spin_lock_bh(&srng->lock);
858
859 ath11k_hal_srng_access_begin(ab, srng);
860
861 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
862 if (!desc) {
863 ret = -ENOBUFS;
864 goto exit;
865 }
866
867 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
868 action);
869
870 exit:
871 ath11k_hal_srng_access_end(ab, srng);
872
873 spin_unlock_bh(&srng->lock);
874
875 return ret;
876 }
877
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)878 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
879 {
880 struct ath11k_base *ab = rx_tid->ab;
881
882 lockdep_assert_held(&ab->base_lock);
883
884 if (rx_tid->dst_ring_desc) {
885 if (rel_link_desc)
886 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
887 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
888 kfree(rx_tid->dst_ring_desc);
889 rx_tid->dst_ring_desc = NULL;
890 }
891
892 rx_tid->cur_sn = 0;
893 rx_tid->last_frag_no = 0;
894 rx_tid->rx_frag_bitmap = 0;
895 __skb_queue_purge(&rx_tid->rx_frags);
896 }
897
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)898 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
899 {
900 struct dp_rx_tid *rx_tid;
901 int i;
902
903 lockdep_assert_held(&ar->ab->base_lock);
904
905 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
906 rx_tid = &peer->rx_tid[i];
907
908 spin_unlock_bh(&ar->ab->base_lock);
909 del_timer_sync(&rx_tid->frag_timer);
910 spin_lock_bh(&ar->ab->base_lock);
911
912 ath11k_dp_rx_frags_cleanup(rx_tid, true);
913 }
914 }
915
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)916 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
917 {
918 struct dp_rx_tid *rx_tid;
919 int i;
920
921 lockdep_assert_held(&ar->ab->base_lock);
922
923 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
924 rx_tid = &peer->rx_tid[i];
925
926 ath11k_peer_rx_tid_delete(ar, peer, i);
927 ath11k_dp_rx_frags_cleanup(rx_tid, true);
928
929 spin_unlock_bh(&ar->ab->base_lock);
930 del_timer_sync(&rx_tid->frag_timer);
931 spin_lock_bh(&ar->ab->base_lock);
932 }
933 }
934
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)935 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
936 struct ath11k_peer *peer,
937 struct dp_rx_tid *rx_tid,
938 u32 ba_win_sz, u16 ssn,
939 bool update_ssn)
940 {
941 struct ath11k_hal_reo_cmd cmd = {0};
942 int ret;
943
944 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
945 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
946 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
947 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
948 cmd.ba_window_size = ba_win_sz;
949
950 if (update_ssn) {
951 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
952 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
953 }
954
955 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
956 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
957 NULL);
958 if (ret) {
959 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
960 rx_tid->tid, ret);
961 return ret;
962 }
963
964 rx_tid->ba_win_sz = ba_win_sz;
965
966 return 0;
967 }
968
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)969 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
970 const u8 *peer_mac, int vdev_id, u8 tid)
971 {
972 struct ath11k_peer *peer;
973 struct dp_rx_tid *rx_tid;
974
975 spin_lock_bh(&ab->base_lock);
976
977 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
978 if (!peer) {
979 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
980 goto unlock_exit;
981 }
982
983 rx_tid = &peer->rx_tid[tid];
984 if (!rx_tid->active)
985 goto unlock_exit;
986
987 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
988 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
989 rx_tid->vaddr_unaligned = NULL;
990
991 rx_tid->active = false;
992
993 unlock_exit:
994 spin_unlock_bh(&ab->base_lock);
995 }
996
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)997 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
998 u8 tid, u32 ba_win_sz, u16 ssn,
999 enum hal_pn_type pn_type)
1000 {
1001 struct ath11k_base *ab = ar->ab;
1002 struct ath11k_peer *peer;
1003 struct dp_rx_tid *rx_tid;
1004 u32 hw_desc_sz, *vaddr;
1005 void *vaddr_unaligned;
1006 dma_addr_t paddr;
1007 int ret;
1008
1009 spin_lock_bh(&ab->base_lock);
1010
1011 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 if (!peer) {
1013 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 peer_mac);
1015 spin_unlock_bh(&ab->base_lock);
1016 return -ENOENT;
1017 }
1018
1019 rx_tid = &peer->rx_tid[tid];
1020 /* Update the tid queue if it is already setup */
1021 if (rx_tid->active) {
1022 paddr = rx_tid->paddr;
1023 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 ba_win_sz, ssn, true);
1025 spin_unlock_bh(&ab->base_lock);
1026 if (ret) {
1027 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 peer_mac, tid, ret);
1029 return ret;
1030 }
1031
1032 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 peer_mac, paddr,
1034 tid, 1, ba_win_sz);
1035 if (ret)
1036 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 peer_mac, tid, ret);
1038 return ret;
1039 }
1040
1041 rx_tid->tid = tid;
1042
1043 rx_tid->ba_win_sz = ba_win_sz;
1044
1045 /* TODO: Optimize the memory allocation for qos tid based on
1046 * the actual BA window size in REO tid update path.
1047 */
1048 if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 else
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052
1053 rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
1054 vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
1055 DMA_BIDIRECTIONAL, GFP_ATOMIC);
1056 if (!vaddr_unaligned) {
1057 spin_unlock_bh(&ab->base_lock);
1058 return -ENOMEM;
1059 }
1060
1061 rx_tid->vaddr_unaligned = vaddr_unaligned;
1062 vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
1063 rx_tid->paddr_unaligned = paddr;
1064 rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
1065 (unsigned long)rx_tid->vaddr_unaligned);
1066 ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
1067 rx_tid->size = hw_desc_sz;
1068 rx_tid->active = true;
1069
1070 /* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
1071 * Since these changes are not reflected in the device, driver now needs to
1072 * explicitly call dma_sync_single_for_device.
1073 */
1074 dma_sync_single_for_device(ab->dev, rx_tid->paddr,
1075 rx_tid->size,
1076 DMA_TO_DEVICE);
1077 spin_unlock_bh(&ab->base_lock);
1078
1079 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
1080 tid, 1, ba_win_sz);
1081 if (ret) {
1082 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1083 peer_mac, tid, ret);
1084 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1085 }
1086
1087 return ret;
1088 }
1089
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 struct ieee80211_ampdu_params *params)
1092 {
1093 struct ath11k_base *ab = ar->ab;
1094 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1095 int vdev_id = arsta->arvif->vdev_id;
1096 int ret;
1097
1098 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 params->tid, params->buf_size,
1100 params->ssn, arsta->pn_type);
1101 if (ret)
1102 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103
1104 return ret;
1105 }
1106
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 struct ieee80211_ampdu_params *params)
1109 {
1110 struct ath11k_base *ab = ar->ab;
1111 struct ath11k_peer *peer;
1112 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1113 int vdev_id = arsta->arvif->vdev_id;
1114 dma_addr_t paddr;
1115 bool active;
1116 int ret;
1117
1118 spin_lock_bh(&ab->base_lock);
1119
1120 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1121 if (!peer) {
1122 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1123 spin_unlock_bh(&ab->base_lock);
1124 return -ENOENT;
1125 }
1126
1127 paddr = peer->rx_tid[params->tid].paddr;
1128 active = peer->rx_tid[params->tid].active;
1129
1130 if (!active) {
1131 spin_unlock_bh(&ab->base_lock);
1132 return 0;
1133 }
1134
1135 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1136 spin_unlock_bh(&ab->base_lock);
1137 if (ret) {
1138 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1139 params->tid, ret);
1140 return ret;
1141 }
1142
1143 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1144 params->sta->addr, paddr,
1145 params->tid, 1, 1);
1146 if (ret)
1147 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1148 ret);
1149
1150 return ret;
1151 }
1152
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1153 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1154 const u8 *peer_addr,
1155 enum set_key_cmd key_cmd,
1156 struct ieee80211_key_conf *key)
1157 {
1158 struct ath11k *ar = arvif->ar;
1159 struct ath11k_base *ab = ar->ab;
1160 struct ath11k_hal_reo_cmd cmd = {0};
1161 struct ath11k_peer *peer;
1162 struct dp_rx_tid *rx_tid;
1163 u8 tid;
1164 int ret = 0;
1165
1166 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1167 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1168 * for now.
1169 */
1170 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1171 return 0;
1172
1173 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1174 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1175 HAL_REO_CMD_UPD0_PN_SIZE |
1176 HAL_REO_CMD_UPD0_PN_VALID |
1177 HAL_REO_CMD_UPD0_PN_CHECK |
1178 HAL_REO_CMD_UPD0_SVLD;
1179
1180 switch (key->cipher) {
1181 case WLAN_CIPHER_SUITE_TKIP:
1182 case WLAN_CIPHER_SUITE_CCMP:
1183 case WLAN_CIPHER_SUITE_CCMP_256:
1184 case WLAN_CIPHER_SUITE_GCMP:
1185 case WLAN_CIPHER_SUITE_GCMP_256:
1186 if (key_cmd == SET_KEY) {
1187 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1188 cmd.pn_size = 48;
1189 }
1190 break;
1191 default:
1192 break;
1193 }
1194
1195 spin_lock_bh(&ab->base_lock);
1196
1197 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1198 if (!peer) {
1199 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1200 spin_unlock_bh(&ab->base_lock);
1201 return -ENOENT;
1202 }
1203
1204 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1205 rx_tid = &peer->rx_tid[tid];
1206 if (!rx_tid->active)
1207 continue;
1208 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1209 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1210 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1211 HAL_REO_CMD_UPDATE_RX_QUEUE,
1212 &cmd, NULL);
1213 if (ret) {
1214 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1215 tid, ret);
1216 break;
1217 }
1218 }
1219
1220 spin_unlock_bh(&ab->base_lock);
1221
1222 return ret;
1223 }
1224
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1225 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1226 u16 peer_id)
1227 {
1228 int i;
1229
1230 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1231 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1232 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1233 return i;
1234 } else {
1235 return i;
1236 }
1237 }
1238
1239 return -EINVAL;
1240 }
1241
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1242 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1243 u16 tag, u16 len, const void *ptr,
1244 void *data)
1245 {
1246 struct htt_ppdu_stats_info *ppdu_info;
1247 struct htt_ppdu_user_stats *user_stats;
1248 int cur_user;
1249 u16 peer_id;
1250
1251 ppdu_info = data;
1252
1253 switch (tag) {
1254 case HTT_PPDU_STATS_TAG_COMMON:
1255 if (len < sizeof(struct htt_ppdu_stats_common)) {
1256 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1257 len, tag);
1258 return -EINVAL;
1259 }
1260 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1261 sizeof(struct htt_ppdu_stats_common));
1262 break;
1263 case HTT_PPDU_STATS_TAG_USR_RATE:
1264 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1265 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1266 len, tag);
1267 return -EINVAL;
1268 }
1269
1270 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1271 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1272 peer_id);
1273 if (cur_user < 0)
1274 return -EINVAL;
1275 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1276 user_stats->peer_id = peer_id;
1277 user_stats->is_valid_peer_id = true;
1278 memcpy((void *)&user_stats->rate, ptr,
1279 sizeof(struct htt_ppdu_stats_user_rate));
1280 user_stats->tlv_flags |= BIT(tag);
1281 break;
1282 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1283 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1284 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1285 len, tag);
1286 return -EINVAL;
1287 }
1288
1289 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1290 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1291 peer_id);
1292 if (cur_user < 0)
1293 return -EINVAL;
1294 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1295 user_stats->peer_id = peer_id;
1296 user_stats->is_valid_peer_id = true;
1297 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1298 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1299 user_stats->tlv_flags |= BIT(tag);
1300 break;
1301 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1302 if (len <
1303 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1304 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1305 len, tag);
1306 return -EINVAL;
1307 }
1308
1309 peer_id =
1310 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1311 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1312 peer_id);
1313 if (cur_user < 0)
1314 return -EINVAL;
1315 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1316 user_stats->peer_id = peer_id;
1317 user_stats->is_valid_peer_id = true;
1318 memcpy((void *)&user_stats->ack_ba, ptr,
1319 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1320 user_stats->tlv_flags |= BIT(tag);
1321 break;
1322 }
1323 return 0;
1324 }
1325
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1326 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1327 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1328 const void *ptr, void *data),
1329 void *data)
1330 {
1331 const struct htt_tlv *tlv;
1332 const void *begin = ptr;
1333 u16 tlv_tag, tlv_len;
1334 int ret = -EINVAL;
1335
1336 while (len > 0) {
1337 if (len < sizeof(*tlv)) {
1338 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1339 ptr - begin, len, sizeof(*tlv));
1340 return -EINVAL;
1341 }
1342 tlv = (struct htt_tlv *)ptr;
1343 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1344 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1345 ptr += sizeof(*tlv);
1346 len -= sizeof(*tlv);
1347
1348 if (tlv_len > len) {
1349 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1350 tlv_tag, ptr - begin, len, tlv_len);
1351 return -EINVAL;
1352 }
1353 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1354 if (ret == -ENOMEM)
1355 return ret;
1356
1357 ptr += tlv_len;
1358 len -= tlv_len;
1359 }
1360 return 0;
1361 }
1362
1363 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1364 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1365 struct htt_ppdu_stats *ppdu_stats, u8 user)
1366 {
1367 struct ath11k_base *ab = ar->ab;
1368 struct ath11k_peer *peer;
1369 struct ieee80211_sta *sta;
1370 struct ath11k_sta *arsta;
1371 struct htt_ppdu_stats_user_rate *user_rate;
1372 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1373 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1374 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1375 int ret;
1376 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1377 u32 succ_bytes = 0;
1378 u16 rate = 0, succ_pkts = 0;
1379 u32 tx_duration = 0;
1380 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1381 bool is_ampdu = false;
1382
1383 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1384 return;
1385
1386 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1387 is_ampdu =
1388 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1389
1390 if (usr_stats->tlv_flags &
1391 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1392 succ_bytes = usr_stats->ack_ba.success_bytes;
1393 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1394 usr_stats->ack_ba.info);
1395 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1396 usr_stats->ack_ba.info);
1397 }
1398
1399 if (common->fes_duration_us)
1400 tx_duration = common->fes_duration_us;
1401
1402 user_rate = &usr_stats->rate;
1403 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1404 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1405 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1406 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1407 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1408 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1409
1410 /* Note: If host configured fixed rates and in some other special
1411 * cases, the broadcast/management frames are sent in different rates.
1412 * Firmware rate's control to be skipped for this?
1413 */
1414
1415 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1416 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1417 return;
1418 }
1419
1420 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1421 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1422 return;
1423 }
1424
1425 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1426 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1427 mcs, nss);
1428 return;
1429 }
1430
1431 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1432 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1433 flags,
1434 &rate_idx,
1435 &rate);
1436 if (ret < 0)
1437 return;
1438 }
1439
1440 rcu_read_lock();
1441 spin_lock_bh(&ab->base_lock);
1442 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1443
1444 if (!peer || !peer->sta) {
1445 spin_unlock_bh(&ab->base_lock);
1446 rcu_read_unlock();
1447 return;
1448 }
1449
1450 sta = peer->sta;
1451 arsta = ath11k_sta_to_arsta(sta);
1452
1453 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1454
1455 switch (flags) {
1456 case WMI_RATE_PREAMBLE_OFDM:
1457 arsta->txrate.legacy = rate;
1458 break;
1459 case WMI_RATE_PREAMBLE_CCK:
1460 arsta->txrate.legacy = rate;
1461 break;
1462 case WMI_RATE_PREAMBLE_HT:
1463 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1464 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1465 if (sgi)
1466 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1467 break;
1468 case WMI_RATE_PREAMBLE_VHT:
1469 arsta->txrate.mcs = mcs;
1470 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1471 if (sgi)
1472 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1473 break;
1474 case WMI_RATE_PREAMBLE_HE:
1475 arsta->txrate.mcs = mcs;
1476 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1477 arsta->txrate.he_dcm = dcm;
1478 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1479 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1480 ((user_rate->ru_end -
1481 user_rate->ru_start) + 1);
1482 break;
1483 }
1484
1485 arsta->txrate.nss = nss;
1486
1487 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1488 arsta->tx_duration += tx_duration;
1489 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1490
1491 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1492 * So skip peer stats update for mgmt packets.
1493 */
1494 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1495 memset(peer_stats, 0, sizeof(*peer_stats));
1496 peer_stats->succ_pkts = succ_pkts;
1497 peer_stats->succ_bytes = succ_bytes;
1498 peer_stats->is_ampdu = is_ampdu;
1499 peer_stats->duration = tx_duration;
1500 peer_stats->ba_fails =
1501 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1502 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1503
1504 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1505 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1506 }
1507
1508 spin_unlock_bh(&ab->base_lock);
1509 rcu_read_unlock();
1510 }
1511
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1512 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1513 struct htt_ppdu_stats *ppdu_stats)
1514 {
1515 u8 user;
1516
1517 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1518 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1519 }
1520
1521 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1522 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1523 u32 ppdu_id)
1524 {
1525 struct htt_ppdu_stats_info *ppdu_info;
1526
1527 lockdep_assert_held(&ar->data_lock);
1528
1529 if (!list_empty(&ar->ppdu_stats_info)) {
1530 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1531 if (ppdu_info->ppdu_id == ppdu_id)
1532 return ppdu_info;
1533 }
1534
1535 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1536 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1537 typeof(*ppdu_info), list);
1538 list_del(&ppdu_info->list);
1539 ar->ppdu_stat_list_depth--;
1540 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1541 kfree(ppdu_info);
1542 }
1543 }
1544
1545 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1546 if (!ppdu_info)
1547 return NULL;
1548
1549 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1550 ar->ppdu_stat_list_depth++;
1551
1552 return ppdu_info;
1553 }
1554
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1555 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1556 struct sk_buff *skb)
1557 {
1558 struct ath11k_htt_ppdu_stats_msg *msg;
1559 struct htt_ppdu_stats_info *ppdu_info;
1560 struct ath11k *ar;
1561 int ret;
1562 u8 pdev_id;
1563 u32 ppdu_id, len;
1564
1565 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1566 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1567 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1568 ppdu_id = msg->ppdu_id;
1569
1570 rcu_read_lock();
1571 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1572 if (!ar) {
1573 ret = -EINVAL;
1574 goto out;
1575 }
1576
1577 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1578 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1579
1580 spin_lock_bh(&ar->data_lock);
1581 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1582 if (!ppdu_info) {
1583 ret = -EINVAL;
1584 goto out_unlock_data;
1585 }
1586
1587 ppdu_info->ppdu_id = ppdu_id;
1588 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1589 ath11k_htt_tlv_ppdu_stats_parse,
1590 (void *)ppdu_info);
1591 if (ret) {
1592 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1593 goto out_unlock_data;
1594 }
1595
1596 out_unlock_data:
1597 spin_unlock_bh(&ar->data_lock);
1598
1599 out:
1600 rcu_read_unlock();
1601
1602 return ret;
1603 }
1604
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1605 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1606 {
1607 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1608 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1609 struct ath11k *ar;
1610 u8 pdev_id;
1611
1612 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1613
1614 rcu_read_lock();
1615
1616 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1617 if (!ar) {
1618 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1619 goto out;
1620 }
1621
1622 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1623 ar->ab->pktlog_defs_checksum);
1624
1625 out:
1626 rcu_read_unlock();
1627 }
1628
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1629 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1630 struct sk_buff *skb)
1631 {
1632 u32 *data = (u32 *)skb->data;
1633 u8 pdev_id, ring_type, ring_id, pdev_idx;
1634 u16 hp, tp;
1635 u32 backpressure_time;
1636 struct ath11k_bp_stats *bp_stats;
1637
1638 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1639 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1640 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1641 ++data;
1642
1643 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1644 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1645 ++data;
1646
1647 backpressure_time = *data;
1648
1649 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1650 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1651
1652 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1653 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1654 return;
1655
1656 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1657 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1658 pdev_idx = DP_HW2SW_MACID(pdev_id);
1659
1660 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1661 return;
1662
1663 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1664 } else {
1665 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1666 ring_type);
1667 return;
1668 }
1669
1670 spin_lock_bh(&ab->base_lock);
1671 bp_stats->hp = hp;
1672 bp_stats->tp = tp;
1673 bp_stats->count++;
1674 bp_stats->jiffies = jiffies;
1675 spin_unlock_bh(&ab->base_lock);
1676 }
1677
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1678 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1679 struct sk_buff *skb)
1680 {
1681 struct ath11k_dp *dp = &ab->dp;
1682 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1683 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1684 u16 peer_id;
1685 u8 vdev_id;
1686 u8 mac_addr[ETH_ALEN];
1687 u16 peer_mac_h16;
1688 u16 ast_hash;
1689 u16 hw_peer_id;
1690
1691 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1692
1693 switch (type) {
1694 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1695 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1696 resp->version_msg.version);
1697 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1698 resp->version_msg.version);
1699 complete(&dp->htt_tgt_version_received);
1700 break;
1701 case HTT_T2H_MSG_TYPE_PEER_MAP:
1702 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1703 resp->peer_map_ev.info);
1704 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1705 resp->peer_map_ev.info);
1706 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1707 resp->peer_map_ev.info1);
1708 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1709 peer_mac_h16, mac_addr);
1710 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1711 break;
1712 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1713 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1714 resp->peer_map_ev.info);
1715 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1716 resp->peer_map_ev.info);
1717 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1718 resp->peer_map_ev.info1);
1719 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1720 peer_mac_h16, mac_addr);
1721 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1722 resp->peer_map_ev.info2);
1723 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1724 resp->peer_map_ev.info1);
1725 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1726 hw_peer_id);
1727 break;
1728 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1729 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1730 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1731 resp->peer_unmap_ev.info);
1732 ath11k_peer_unmap_event(ab, peer_id);
1733 break;
1734 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1735 ath11k_htt_pull_ppdu_stats(ab, skb);
1736 break;
1737 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1738 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1739 break;
1740 case HTT_T2H_MSG_TYPE_PKTLOG:
1741 ath11k_htt_pktlog(ab, skb);
1742 break;
1743 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1744 ath11k_htt_backpressure_event_handler(ab, skb);
1745 break;
1746 default:
1747 ath11k_warn(ab, "htt event %d not handled\n", type);
1748 break;
1749 }
1750
1751 dev_kfree_skb_any(skb);
1752 }
1753
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1754 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1755 struct sk_buff_head *msdu_list,
1756 struct sk_buff *first, struct sk_buff *last,
1757 u8 l3pad_bytes, int msdu_len)
1758 {
1759 struct ath11k_base *ab = ar->ab;
1760 struct sk_buff *skb;
1761 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1762 int buf_first_hdr_len, buf_first_len;
1763 struct hal_rx_desc *ldesc;
1764 int space_extra, rem_len, buf_len;
1765 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1766
1767 /* As the msdu is spread across multiple rx buffers,
1768 * find the offset to the start of msdu for computing
1769 * the length of the msdu in the first buffer.
1770 */
1771 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1772 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1773
1774 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1775 skb_put(first, buf_first_hdr_len + msdu_len);
1776 skb_pull(first, buf_first_hdr_len);
1777 return 0;
1778 }
1779
1780 ldesc = (struct hal_rx_desc *)last->data;
1781 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1782 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1783
1784 /* MSDU spans over multiple buffers because the length of the MSDU
1785 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1786 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1787 */
1788 skb_put(first, DP_RX_BUFFER_SIZE);
1789 skb_pull(first, buf_first_hdr_len);
1790
1791 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1792 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1793 */
1794 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1795
1796 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1797 if (space_extra > 0 &&
1798 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1799 /* Free up all buffers of the MSDU */
1800 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1801 rxcb = ATH11K_SKB_RXCB(skb);
1802 if (!rxcb->is_continuation) {
1803 dev_kfree_skb_any(skb);
1804 break;
1805 }
1806 dev_kfree_skb_any(skb);
1807 }
1808 return -ENOMEM;
1809 }
1810
1811 rem_len = msdu_len - buf_first_len;
1812 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1813 rxcb = ATH11K_SKB_RXCB(skb);
1814 if (rxcb->is_continuation)
1815 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1816 else
1817 buf_len = rem_len;
1818
1819 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1820 WARN_ON_ONCE(1);
1821 dev_kfree_skb_any(skb);
1822 return -EINVAL;
1823 }
1824
1825 skb_put(skb, buf_len + hal_rx_desc_sz);
1826 skb_pull(skb, hal_rx_desc_sz);
1827 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1828 buf_len);
1829 dev_kfree_skb_any(skb);
1830
1831 rem_len -= buf_len;
1832 if (!rxcb->is_continuation)
1833 break;
1834 }
1835
1836 return 0;
1837 }
1838
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1839 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1840 struct sk_buff *first)
1841 {
1842 struct sk_buff *skb;
1843 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1844
1845 if (!rxcb->is_continuation)
1846 return first;
1847
1848 skb_queue_walk(msdu_list, skb) {
1849 rxcb = ATH11K_SKB_RXCB(skb);
1850 if (!rxcb->is_continuation)
1851 return skb;
1852 }
1853
1854 return NULL;
1855 }
1856
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1857 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1858 {
1859 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1860 struct rx_attention *rx_attention;
1861 bool ip_csum_fail, l4_csum_fail;
1862
1863 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1864 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1865 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1866
1867 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1868 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1869 }
1870
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1871 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1872 {
1873 switch (enctype) {
1874 case HAL_ENCRYPT_TYPE_OPEN:
1875 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1876 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1877 return 0;
1878 case HAL_ENCRYPT_TYPE_CCMP_128:
1879 return IEEE80211_CCMP_MIC_LEN;
1880 case HAL_ENCRYPT_TYPE_CCMP_256:
1881 return IEEE80211_CCMP_256_MIC_LEN;
1882 case HAL_ENCRYPT_TYPE_GCMP_128:
1883 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1884 return IEEE80211_GCMP_MIC_LEN;
1885 case HAL_ENCRYPT_TYPE_WEP_40:
1886 case HAL_ENCRYPT_TYPE_WEP_104:
1887 case HAL_ENCRYPT_TYPE_WEP_128:
1888 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1889 case HAL_ENCRYPT_TYPE_WAPI:
1890 break;
1891 }
1892
1893 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1894 return 0;
1895 }
1896
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1897 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1898 enum hal_encrypt_type enctype)
1899 {
1900 switch (enctype) {
1901 case HAL_ENCRYPT_TYPE_OPEN:
1902 return 0;
1903 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1904 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1905 return IEEE80211_TKIP_IV_LEN;
1906 case HAL_ENCRYPT_TYPE_CCMP_128:
1907 return IEEE80211_CCMP_HDR_LEN;
1908 case HAL_ENCRYPT_TYPE_CCMP_256:
1909 return IEEE80211_CCMP_256_HDR_LEN;
1910 case HAL_ENCRYPT_TYPE_GCMP_128:
1911 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1912 return IEEE80211_GCMP_HDR_LEN;
1913 case HAL_ENCRYPT_TYPE_WEP_40:
1914 case HAL_ENCRYPT_TYPE_WEP_104:
1915 case HAL_ENCRYPT_TYPE_WEP_128:
1916 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1917 case HAL_ENCRYPT_TYPE_WAPI:
1918 break;
1919 }
1920
1921 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1922 return 0;
1923 }
1924
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1925 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1926 enum hal_encrypt_type enctype)
1927 {
1928 switch (enctype) {
1929 case HAL_ENCRYPT_TYPE_OPEN:
1930 case HAL_ENCRYPT_TYPE_CCMP_128:
1931 case HAL_ENCRYPT_TYPE_CCMP_256:
1932 case HAL_ENCRYPT_TYPE_GCMP_128:
1933 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1934 return 0;
1935 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1936 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1937 return IEEE80211_TKIP_ICV_LEN;
1938 case HAL_ENCRYPT_TYPE_WEP_40:
1939 case HAL_ENCRYPT_TYPE_WEP_104:
1940 case HAL_ENCRYPT_TYPE_WEP_128:
1941 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1942 case HAL_ENCRYPT_TYPE_WAPI:
1943 break;
1944 }
1945
1946 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1947 return 0;
1948 }
1949
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1950 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1951 struct sk_buff *msdu,
1952 u8 *first_hdr,
1953 enum hal_encrypt_type enctype,
1954 struct ieee80211_rx_status *status)
1955 {
1956 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1957 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1958 struct ieee80211_hdr *hdr;
1959 size_t hdr_len;
1960 u8 da[ETH_ALEN];
1961 u8 sa[ETH_ALEN];
1962 u16 qos_ctl = 0;
1963 u8 *qos;
1964
1965 /* copy SA & DA and pull decapped header */
1966 hdr = (struct ieee80211_hdr *)msdu->data;
1967 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1968 ether_addr_copy(da, ieee80211_get_DA(hdr));
1969 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1970 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1971
1972 if (rxcb->is_first_msdu) {
1973 /* original 802.11 header is valid for the first msdu
1974 * hence we can reuse the same header
1975 */
1976 hdr = (struct ieee80211_hdr *)first_hdr;
1977 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1978
1979 /* Each A-MSDU subframe will be reported as a separate MSDU,
1980 * so strip the A-MSDU bit from QoS Ctl.
1981 */
1982 if (ieee80211_is_data_qos(hdr->frame_control)) {
1983 qos = ieee80211_get_qos_ctl(hdr);
1984 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1985 }
1986 } else {
1987 /* Rebuild qos header if this is a middle/last msdu */
1988 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1989
1990 /* Reset the order bit as the HT_Control header is stripped */
1991 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1992
1993 qos_ctl = rxcb->tid;
1994
1995 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
1996 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1997
1998 /* TODO Add other QoS ctl fields when required */
1999
2000 /* copy decap header before overwriting for reuse below */
2001 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2002 }
2003
2004 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2005 memcpy(skb_push(msdu,
2006 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2007 (void *)hdr + hdr_len,
2008 ath11k_dp_rx_crypto_param_len(ar, enctype));
2009 }
2010
2011 if (!rxcb->is_first_msdu) {
2012 memcpy(skb_push(msdu,
2013 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2014 IEEE80211_QOS_CTL_LEN);
2015 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2016 return;
2017 }
2018
2019 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2020
2021 /* original 802.11 header has a different DA and in
2022 * case of 4addr it may also have different SA
2023 */
2024 hdr = (struct ieee80211_hdr *)msdu->data;
2025 ether_addr_copy(ieee80211_get_DA(hdr), da);
2026 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2027 }
2028
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2029 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2030 enum hal_encrypt_type enctype,
2031 struct ieee80211_rx_status *status,
2032 bool decrypted)
2033 {
2034 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2035 struct ieee80211_hdr *hdr;
2036 size_t hdr_len;
2037 size_t crypto_len;
2038
2039 if (!rxcb->is_first_msdu ||
2040 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2041 WARN_ON_ONCE(1);
2042 return;
2043 }
2044
2045 skb_trim(msdu, msdu->len - FCS_LEN);
2046
2047 if (!decrypted)
2048 return;
2049
2050 hdr = (void *)msdu->data;
2051
2052 /* Tail */
2053 if (status->flag & RX_FLAG_IV_STRIPPED) {
2054 skb_trim(msdu, msdu->len -
2055 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2056
2057 skb_trim(msdu, msdu->len -
2058 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2059 } else {
2060 /* MIC */
2061 if (status->flag & RX_FLAG_MIC_STRIPPED)
2062 skb_trim(msdu, msdu->len -
2063 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2064
2065 /* ICV */
2066 if (status->flag & RX_FLAG_ICV_STRIPPED)
2067 skb_trim(msdu, msdu->len -
2068 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2069 }
2070
2071 /* MMIC */
2072 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2073 !ieee80211_has_morefrags(hdr->frame_control) &&
2074 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2075 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2076
2077 /* Head */
2078 if (status->flag & RX_FLAG_IV_STRIPPED) {
2079 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2080 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2081
2082 memmove((void *)msdu->data + crypto_len,
2083 (void *)msdu->data, hdr_len);
2084 skb_pull(msdu, crypto_len);
2085 }
2086 }
2087
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2088 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2089 struct sk_buff *msdu,
2090 enum hal_encrypt_type enctype)
2091 {
2092 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2093 struct ieee80211_hdr *hdr;
2094 size_t hdr_len, crypto_len;
2095 void *rfc1042;
2096 bool is_amsdu;
2097
2098 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2099 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2100 rfc1042 = hdr;
2101
2102 if (rxcb->is_first_msdu) {
2103 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2104 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2105
2106 rfc1042 += hdr_len + crypto_len;
2107 }
2108
2109 if (is_amsdu)
2110 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2111
2112 return rfc1042;
2113 }
2114
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2115 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2116 struct sk_buff *msdu,
2117 u8 *first_hdr,
2118 enum hal_encrypt_type enctype,
2119 struct ieee80211_rx_status *status)
2120 {
2121 struct ieee80211_hdr *hdr;
2122 struct ethhdr *eth;
2123 size_t hdr_len;
2124 u8 da[ETH_ALEN];
2125 u8 sa[ETH_ALEN];
2126 void *rfc1042;
2127
2128 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2129 if (WARN_ON_ONCE(!rfc1042))
2130 return;
2131
2132 /* pull decapped header and copy SA & DA */
2133 eth = (struct ethhdr *)msdu->data;
2134 ether_addr_copy(da, eth->h_dest);
2135 ether_addr_copy(sa, eth->h_source);
2136 skb_pull(msdu, sizeof(struct ethhdr));
2137
2138 /* push rfc1042/llc/snap */
2139 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2140 sizeof(struct ath11k_dp_rfc1042_hdr));
2141
2142 /* push original 802.11 header */
2143 hdr = (struct ieee80211_hdr *)first_hdr;
2144 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2145
2146 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2147 memcpy(skb_push(msdu,
2148 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2149 (void *)hdr + hdr_len,
2150 ath11k_dp_rx_crypto_param_len(ar, enctype));
2151 }
2152
2153 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2154
2155 /* original 802.11 header has a different DA and in
2156 * case of 4addr it may also have different SA
2157 */
2158 hdr = (struct ieee80211_hdr *)msdu->data;
2159 ether_addr_copy(ieee80211_get_DA(hdr), da);
2160 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2161 }
2162
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2163 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2164 struct hal_rx_desc *rx_desc,
2165 enum hal_encrypt_type enctype,
2166 struct ieee80211_rx_status *status,
2167 bool decrypted)
2168 {
2169 u8 *first_hdr;
2170 u8 decap;
2171 struct ethhdr *ehdr;
2172
2173 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2174 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2175
2176 switch (decap) {
2177 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2178 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2179 enctype, status);
2180 break;
2181 case DP_RX_DECAP_TYPE_RAW:
2182 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2183 decrypted);
2184 break;
2185 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2186 ehdr = (struct ethhdr *)msdu->data;
2187
2188 /* mac80211 allows fast path only for authorized STA */
2189 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2190 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2191 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2192 enctype, status);
2193 break;
2194 }
2195
2196 /* PN for mcast packets will be validated in mac80211;
2197 * remove eth header and add 802.11 header.
2198 */
2199 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2200 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2201 enctype, status);
2202 break;
2203 case DP_RX_DECAP_TYPE_8023:
2204 /* TODO: Handle undecap for these formats */
2205 break;
2206 }
2207 }
2208
2209 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2210 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2211 {
2212 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2213 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2214 struct ath11k_peer *peer = NULL;
2215
2216 lockdep_assert_held(&ab->base_lock);
2217
2218 if (rxcb->peer_id)
2219 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2220
2221 if (peer)
2222 return peer;
2223
2224 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2225 return NULL;
2226
2227 peer = ath11k_peer_find_by_addr(ab,
2228 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2229 return peer;
2230 }
2231
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2232 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2233 struct sk_buff *msdu,
2234 struct hal_rx_desc *rx_desc,
2235 struct ieee80211_rx_status *rx_status)
2236 {
2237 bool fill_crypto_hdr;
2238 enum hal_encrypt_type enctype;
2239 bool is_decrypted = false;
2240 struct ath11k_skb_rxcb *rxcb;
2241 struct ieee80211_hdr *hdr;
2242 struct ath11k_peer *peer;
2243 struct rx_attention *rx_attention;
2244 u32 err_bitmap;
2245
2246 /* PN for multicast packets will be checked in mac80211 */
2247 rxcb = ATH11K_SKB_RXCB(msdu);
2248 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2249 rxcb->is_mcbc = fill_crypto_hdr;
2250
2251 if (rxcb->is_mcbc) {
2252 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2253 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2254 }
2255
2256 spin_lock_bh(&ar->ab->base_lock);
2257 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2258 if (peer) {
2259 if (rxcb->is_mcbc)
2260 enctype = peer->sec_type_grp;
2261 else
2262 enctype = peer->sec_type;
2263 } else {
2264 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2265 }
2266 spin_unlock_bh(&ar->ab->base_lock);
2267
2268 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2269 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2270 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2271 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2272
2273 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2274 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2275 RX_FLAG_MMIC_ERROR |
2276 RX_FLAG_DECRYPTED |
2277 RX_FLAG_IV_STRIPPED |
2278 RX_FLAG_MMIC_STRIPPED);
2279
2280 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2281 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2282 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2283 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2284
2285 if (is_decrypted) {
2286 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2287
2288 if (fill_crypto_hdr)
2289 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2290 RX_FLAG_ICV_STRIPPED;
2291 else
2292 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2293 RX_FLAG_PN_VALIDATED;
2294 }
2295
2296 ath11k_dp_rx_h_csum_offload(ar, msdu);
2297 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2298 enctype, rx_status, is_decrypted);
2299
2300 if (!is_decrypted || fill_crypto_hdr)
2301 return;
2302
2303 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2304 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2305 hdr = (void *)msdu->data;
2306 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2307 }
2308 }
2309
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2310 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2311 struct ieee80211_rx_status *rx_status)
2312 {
2313 struct ieee80211_supported_band *sband;
2314 enum rx_msdu_start_pkt_type pkt_type;
2315 u8 bw;
2316 u8 rate_mcs, nss;
2317 u8 sgi;
2318 bool is_cck, is_ldpc;
2319
2320 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2321 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2322 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2323 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2324 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2325
2326 switch (pkt_type) {
2327 case RX_MSDU_START_PKT_TYPE_11A:
2328 case RX_MSDU_START_PKT_TYPE_11B:
2329 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2330 sband = &ar->mac.sbands[rx_status->band];
2331 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2332 is_cck);
2333 break;
2334 case RX_MSDU_START_PKT_TYPE_11N:
2335 rx_status->encoding = RX_ENC_HT;
2336 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2337 ath11k_warn(ar->ab,
2338 "Received with invalid mcs in HT mode %d\n",
2339 rate_mcs);
2340 break;
2341 }
2342 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2343 if (sgi)
2344 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2345 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2346 break;
2347 case RX_MSDU_START_PKT_TYPE_11AC:
2348 rx_status->encoding = RX_ENC_VHT;
2349 rx_status->rate_idx = rate_mcs;
2350 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2351 ath11k_warn(ar->ab,
2352 "Received with invalid mcs in VHT mode %d\n",
2353 rate_mcs);
2354 break;
2355 }
2356 rx_status->nss = nss;
2357 if (sgi)
2358 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2359 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2360 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2361 if (is_ldpc)
2362 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2363 break;
2364 case RX_MSDU_START_PKT_TYPE_11AX:
2365 rx_status->rate_idx = rate_mcs;
2366 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2367 ath11k_warn(ar->ab,
2368 "Received with invalid mcs in HE mode %d\n",
2369 rate_mcs);
2370 break;
2371 }
2372 rx_status->encoding = RX_ENC_HE;
2373 rx_status->nss = nss;
2374 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2375 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2376 break;
2377 }
2378 }
2379
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2380 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2381 struct ieee80211_rx_status *rx_status)
2382 {
2383 u8 channel_num;
2384 u32 center_freq, meta_data;
2385 struct ieee80211_channel *channel;
2386
2387 rx_status->freq = 0;
2388 rx_status->rate_idx = 0;
2389 rx_status->nss = 0;
2390 rx_status->encoding = RX_ENC_LEGACY;
2391 rx_status->bw = RATE_INFO_BW_20;
2392
2393 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2394
2395 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2396 channel_num = meta_data;
2397 center_freq = meta_data >> 16;
2398
2399 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2400 center_freq <= ATH11K_MAX_6G_FREQ) {
2401 rx_status->band = NL80211_BAND_6GHZ;
2402 rx_status->freq = center_freq;
2403 } else if (channel_num >= 1 && channel_num <= 14) {
2404 rx_status->band = NL80211_BAND_2GHZ;
2405 } else if (channel_num >= 36 && channel_num <= 177) {
2406 rx_status->band = NL80211_BAND_5GHZ;
2407 } else {
2408 spin_lock_bh(&ar->data_lock);
2409 channel = ar->rx_channel;
2410 if (channel) {
2411 rx_status->band = channel->band;
2412 channel_num =
2413 ieee80211_frequency_to_channel(channel->center_freq);
2414 }
2415 spin_unlock_bh(&ar->data_lock);
2416 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2417 rx_desc, sizeof(struct hal_rx_desc));
2418 }
2419
2420 if (rx_status->band != NL80211_BAND_6GHZ)
2421 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2422 rx_status->band);
2423
2424 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2425 }
2426
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2427 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2428 struct sk_buff *msdu,
2429 struct ieee80211_rx_status *status)
2430 {
2431 static const struct ieee80211_radiotap_he known = {
2432 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2433 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2434 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2435 };
2436 struct ieee80211_rx_status *rx_status;
2437 struct ieee80211_radiotap_he *he = NULL;
2438 struct ieee80211_sta *pubsta = NULL;
2439 struct ath11k_peer *peer;
2440 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2441 u8 decap = DP_RX_DECAP_TYPE_RAW;
2442 bool is_mcbc = rxcb->is_mcbc;
2443 bool is_eapol = rxcb->is_eapol;
2444
2445 if (status->encoding == RX_ENC_HE &&
2446 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2447 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2448 he = skb_push(msdu, sizeof(known));
2449 memcpy(he, &known, sizeof(known));
2450 status->flag |= RX_FLAG_RADIOTAP_HE;
2451 }
2452
2453 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2454 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2455
2456 spin_lock_bh(&ar->ab->base_lock);
2457 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2458 if (peer && peer->sta)
2459 pubsta = peer->sta;
2460 spin_unlock_bh(&ar->ab->base_lock);
2461
2462 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2463 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2464 msdu,
2465 msdu->len,
2466 peer ? peer->addr : NULL,
2467 rxcb->tid,
2468 is_mcbc ? "mcast" : "ucast",
2469 rxcb->seq_no,
2470 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2471 (status->encoding == RX_ENC_HT) ? "ht" : "",
2472 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2473 (status->encoding == RX_ENC_HE) ? "he" : "",
2474 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2475 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2476 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2477 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2478 status->rate_idx,
2479 status->nss,
2480 status->freq,
2481 status->band, status->flag,
2482 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2483 !!(status->flag & RX_FLAG_MMIC_ERROR),
2484 !!(status->flag & RX_FLAG_AMSDU_MORE));
2485
2486 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2487 msdu->data, msdu->len);
2488
2489 rx_status = IEEE80211_SKB_RXCB(msdu);
2490 *rx_status = *status;
2491
2492 /* TODO: trace rx packet */
2493
2494 /* PN for multicast packets are not validate in HW,
2495 * so skip 802.3 rx path
2496 * Also, fast_rx expects the STA to be authorized, hence
2497 * eapol packets are sent in slow path.
2498 */
2499 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2500 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2501 rx_status->flag |= RX_FLAG_8023;
2502
2503 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2504 }
2505
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2506 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2507 struct sk_buff *msdu,
2508 struct sk_buff_head *msdu_list,
2509 struct ieee80211_rx_status *rx_status)
2510 {
2511 struct ath11k_base *ab = ar->ab;
2512 struct hal_rx_desc *rx_desc, *lrx_desc;
2513 struct rx_attention *rx_attention;
2514 struct ath11k_skb_rxcb *rxcb;
2515 struct sk_buff *last_buf;
2516 u8 l3_pad_bytes;
2517 u8 *hdr_status;
2518 u16 msdu_len;
2519 int ret;
2520 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2521
2522 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2523 if (!last_buf) {
2524 ath11k_warn(ab,
2525 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2526 ret = -EIO;
2527 goto free_out;
2528 }
2529
2530 rx_desc = (struct hal_rx_desc *)msdu->data;
2531 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2532 ath11k_warn(ar->ab, "msdu len not valid\n");
2533 ret = -EIO;
2534 goto free_out;
2535 }
2536
2537 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2538 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2539 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2540 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2541 ret = -EIO;
2542 goto free_out;
2543 }
2544
2545 rxcb = ATH11K_SKB_RXCB(msdu);
2546 rxcb->rx_desc = rx_desc;
2547 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2548 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2549
2550 if (rxcb->is_frag) {
2551 skb_pull(msdu, hal_rx_desc_sz);
2552 } else if (!rxcb->is_continuation) {
2553 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2554 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2555 ret = -EINVAL;
2556 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2557 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2558 sizeof(struct ieee80211_hdr));
2559 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2560 sizeof(struct hal_rx_desc));
2561 goto free_out;
2562 }
2563 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2564 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2565 } else {
2566 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2567 msdu, last_buf,
2568 l3_pad_bytes, msdu_len);
2569 if (ret) {
2570 ath11k_warn(ab,
2571 "failed to coalesce msdu rx buffer%d\n", ret);
2572 goto free_out;
2573 }
2574 }
2575
2576 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2577 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2578
2579 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2580
2581 return 0;
2582
2583 free_out:
2584 return ret;
2585 }
2586
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2587 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2588 struct napi_struct *napi,
2589 struct sk_buff_head *msdu_list,
2590 int mac_id)
2591 {
2592 struct sk_buff *msdu;
2593 struct ath11k *ar;
2594 struct ieee80211_rx_status rx_status = {0};
2595 int ret;
2596
2597 if (skb_queue_empty(msdu_list))
2598 return;
2599
2600 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2601 __skb_queue_purge(msdu_list);
2602 return;
2603 }
2604
2605 ar = ab->pdevs[mac_id].ar;
2606 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2607 __skb_queue_purge(msdu_list);
2608 return;
2609 }
2610
2611 while ((msdu = __skb_dequeue(msdu_list))) {
2612 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2613 if (unlikely(ret)) {
2614 ath11k_dbg(ab, ATH11K_DBG_DATA,
2615 "Unable to process msdu %d", ret);
2616 dev_kfree_skb_any(msdu);
2617 continue;
2618 }
2619
2620 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2621 }
2622 }
2623
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2624 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2625 struct napi_struct *napi, int budget)
2626 {
2627 struct ath11k_dp *dp = &ab->dp;
2628 struct dp_rxdma_ring *rx_ring;
2629 int num_buffs_reaped[MAX_RADIOS] = {0};
2630 struct sk_buff_head msdu_list[MAX_RADIOS];
2631 struct ath11k_skb_rxcb *rxcb;
2632 int total_msdu_reaped = 0;
2633 struct hal_srng *srng;
2634 struct sk_buff *msdu;
2635 bool done = false;
2636 int buf_id, mac_id;
2637 struct ath11k *ar;
2638 struct hal_reo_dest_ring *desc;
2639 enum hal_reo_dest_ring_push_reason push_reason;
2640 u32 cookie;
2641 int i;
2642
2643 for (i = 0; i < MAX_RADIOS; i++)
2644 __skb_queue_head_init(&msdu_list[i]);
2645
2646 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2647
2648 spin_lock_bh(&srng->lock);
2649
2650 try_again:
2651 ath11k_hal_srng_access_begin(ab, srng);
2652
2653 while (likely(desc =
2654 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2655 srng))) {
2656 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2657 desc->buf_addr_info.info1);
2658 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2659 cookie);
2660 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2661
2662 if (unlikely(buf_id == 0))
2663 continue;
2664
2665 ar = ab->pdevs[mac_id].ar;
2666 rx_ring = &ar->dp.rx_refill_buf_ring;
2667 spin_lock_bh(&rx_ring->idr_lock);
2668 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2669 if (unlikely(!msdu)) {
2670 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2671 buf_id);
2672 spin_unlock_bh(&rx_ring->idr_lock);
2673 continue;
2674 }
2675
2676 idr_remove(&rx_ring->bufs_idr, buf_id);
2677 spin_unlock_bh(&rx_ring->idr_lock);
2678
2679 rxcb = ATH11K_SKB_RXCB(msdu);
2680 dma_unmap_single(ab->dev, rxcb->paddr,
2681 msdu->len + skb_tailroom(msdu),
2682 DMA_FROM_DEVICE);
2683
2684 num_buffs_reaped[mac_id]++;
2685
2686 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2687 desc->info0);
2688 if (unlikely(push_reason !=
2689 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2690 dev_kfree_skb_any(msdu);
2691 ab->soc_stats.hal_reo_error[ring_id]++;
2692 continue;
2693 }
2694
2695 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2696 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2697 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2698 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2699 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2700 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2701 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2702 desc->rx_mpdu_info.meta_data);
2703 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2704 desc->rx_mpdu_info.info0);
2705 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2706 desc->info0);
2707
2708 rxcb->mac_id = mac_id;
2709 __skb_queue_tail(&msdu_list[mac_id], msdu);
2710
2711 if (rxcb->is_continuation) {
2712 done = false;
2713 } else {
2714 total_msdu_reaped++;
2715 done = true;
2716 }
2717
2718 if (total_msdu_reaped >= budget)
2719 break;
2720 }
2721
2722 /* Hw might have updated the head pointer after we cached it.
2723 * In this case, even though there are entries in the ring we'll
2724 * get rx_desc NULL. Give the read another try with updated cached
2725 * head pointer so that we can reap complete MPDU in the current
2726 * rx processing.
2727 */
2728 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2729 ath11k_hal_srng_access_end(ab, srng);
2730 goto try_again;
2731 }
2732
2733 ath11k_hal_srng_access_end(ab, srng);
2734
2735 spin_unlock_bh(&srng->lock);
2736
2737 if (unlikely(!total_msdu_reaped))
2738 goto exit;
2739
2740 for (i = 0; i < ab->num_radios; i++) {
2741 if (!num_buffs_reaped[i])
2742 continue;
2743
2744 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2745
2746 ar = ab->pdevs[i].ar;
2747 rx_ring = &ar->dp.rx_refill_buf_ring;
2748
2749 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2750 ab->hw_params.hal_params->rx_buf_rbm);
2751 }
2752 exit:
2753 return total_msdu_reaped;
2754 }
2755
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2756 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2757 struct hal_rx_mon_ppdu_info *ppdu_info)
2758 {
2759 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2760 u32 num_msdu;
2761 int i;
2762
2763 if (!rx_stats)
2764 return;
2765
2766 arsta->rssi_comb = ppdu_info->rssi_comb;
2767 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2768
2769 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2770 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2771
2772 rx_stats->num_msdu += num_msdu;
2773 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2774 ppdu_info->tcp_ack_msdu_count;
2775 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2776 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2777
2778 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2779 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2780 ppdu_info->nss = 1;
2781 ppdu_info->mcs = HAL_RX_MAX_MCS;
2782 ppdu_info->tid = IEEE80211_NUM_TIDS;
2783 }
2784
2785 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2786 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2787
2788 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2789 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2790
2791 if (ppdu_info->gi < HAL_RX_GI_MAX)
2792 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2793
2794 if (ppdu_info->bw < HAL_RX_BW_MAX)
2795 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2796
2797 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2798 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2799
2800 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2801 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2802
2803 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2804 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2805
2806 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2807 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2808
2809 if (ppdu_info->is_stbc)
2810 rx_stats->stbc_count += num_msdu;
2811
2812 if (ppdu_info->beamformed)
2813 rx_stats->beamformed_count += num_msdu;
2814
2815 if (ppdu_info->num_mpdu_fcs_ok > 1)
2816 rx_stats->ampdu_msdu_count += num_msdu;
2817 else
2818 rx_stats->non_ampdu_msdu_count += num_msdu;
2819
2820 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2821 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2822 rx_stats->dcm_count += ppdu_info->dcm;
2823 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2824
2825 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2826 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2827
2828 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2829 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2830
2831 rx_stats->rx_duration += ppdu_info->rx_duration;
2832 arsta->rx_duration = rx_stats->rx_duration;
2833 }
2834
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2835 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2836 struct dp_rxdma_ring *rx_ring,
2837 int *buf_id)
2838 {
2839 struct sk_buff *skb;
2840 dma_addr_t paddr;
2841
2842 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2843 DP_RX_BUFFER_ALIGN_SIZE);
2844
2845 if (!skb)
2846 goto fail_alloc_skb;
2847
2848 if (!IS_ALIGNED((unsigned long)skb->data,
2849 DP_RX_BUFFER_ALIGN_SIZE)) {
2850 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2851 skb->data);
2852 }
2853
2854 paddr = dma_map_single(ab->dev, skb->data,
2855 skb->len + skb_tailroom(skb),
2856 DMA_FROM_DEVICE);
2857 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2858 goto fail_free_skb;
2859
2860 spin_lock_bh(&rx_ring->idr_lock);
2861 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2862 rx_ring->bufs_max, GFP_ATOMIC);
2863 spin_unlock_bh(&rx_ring->idr_lock);
2864 if (*buf_id < 0)
2865 goto fail_dma_unmap;
2866
2867 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2868 return skb;
2869
2870 fail_dma_unmap:
2871 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2872 DMA_FROM_DEVICE);
2873 fail_free_skb:
2874 dev_kfree_skb_any(skb);
2875 fail_alloc_skb:
2876 return NULL;
2877 }
2878
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2879 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2880 struct dp_rxdma_ring *rx_ring,
2881 int req_entries,
2882 enum hal_rx_buf_return_buf_manager mgr)
2883 {
2884 struct hal_srng *srng;
2885 u32 *desc;
2886 struct sk_buff *skb;
2887 int num_free;
2888 int num_remain;
2889 int buf_id;
2890 u32 cookie;
2891 dma_addr_t paddr;
2892
2893 req_entries = min(req_entries, rx_ring->bufs_max);
2894
2895 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2896
2897 spin_lock_bh(&srng->lock);
2898
2899 ath11k_hal_srng_access_begin(ab, srng);
2900
2901 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2902
2903 req_entries = min(num_free, req_entries);
2904 num_remain = req_entries;
2905
2906 while (num_remain > 0) {
2907 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2908 &buf_id);
2909 if (!skb)
2910 break;
2911 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2912
2913 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2914 if (!desc)
2915 goto fail_desc_get;
2916
2917 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2918 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2919
2920 num_remain--;
2921
2922 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2923 }
2924
2925 ath11k_hal_srng_access_end(ab, srng);
2926
2927 spin_unlock_bh(&srng->lock);
2928
2929 return req_entries - num_remain;
2930
2931 fail_desc_get:
2932 spin_lock_bh(&rx_ring->idr_lock);
2933 idr_remove(&rx_ring->bufs_idr, buf_id);
2934 spin_unlock_bh(&rx_ring->idr_lock);
2935 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2936 DMA_FROM_DEVICE);
2937 dev_kfree_skb_any(skb);
2938 ath11k_hal_srng_access_end(ab, srng);
2939 spin_unlock_bh(&srng->lock);
2940
2941 return req_entries - num_remain;
2942 }
2943
2944 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2945
2946 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2947 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2948 struct hal_tlv_hdr *tlv)
2949 {
2950 struct hal_rx_ppdu_start *ppdu_start;
2951 u16 ppdu_id_diff, ppdu_id, tlv_len;
2952 u8 *ptr;
2953
2954 /* PPDU id is part of second tlv, move ptr to second tlv */
2955 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2956 ptr = (u8 *)tlv;
2957 ptr += sizeof(*tlv) + tlv_len;
2958 tlv = (struct hal_tlv_hdr *)ptr;
2959
2960 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2961 return;
2962
2963 ptr += sizeof(*tlv);
2964 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2965 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2966 __le32_to_cpu(ppdu_start->info0));
2967
2968 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2969 pmon->buf_state = DP_MON_STATUS_LEAD;
2970 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2971 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2972 pmon->buf_state = DP_MON_STATUS_LAG;
2973 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2974 pmon->buf_state = DP_MON_STATUS_LAG;
2975 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2976 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2977 pmon->buf_state = DP_MON_STATUS_LEAD;
2978 }
2979 }
2980
2981 static enum dp_mon_status_buf_state
ath11k_dp_rx_mon_buf_done(struct ath11k_base * ab,struct hal_srng * srng,struct dp_rxdma_ring * rx_ring)2982 ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
2983 struct dp_rxdma_ring *rx_ring)
2984 {
2985 struct ath11k_skb_rxcb *rxcb;
2986 struct hal_tlv_hdr *tlv;
2987 struct sk_buff *skb;
2988 void *status_desc;
2989 dma_addr_t paddr;
2990 u32 cookie;
2991 int buf_id;
2992 u8 rbm;
2993
2994 status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
2995 if (!status_desc)
2996 return DP_MON_STATUS_NO_DMA;
2997
2998 ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
2999
3000 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3001
3002 spin_lock_bh(&rx_ring->idr_lock);
3003 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3004 spin_unlock_bh(&rx_ring->idr_lock);
3005
3006 if (!skb)
3007 return DP_MON_STATUS_NO_DMA;
3008
3009 rxcb = ATH11K_SKB_RXCB(skb);
3010 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3011 skb->len + skb_tailroom(skb),
3012 DMA_FROM_DEVICE);
3013
3014 tlv = (struct hal_tlv_hdr *)skb->data;
3015 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
3016 return DP_MON_STATUS_NO_DMA;
3017
3018 return DP_MON_STATUS_REPLINISH;
3019 }
3020
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3021 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3022 int *budget, struct sk_buff_head *skb_list)
3023 {
3024 struct ath11k *ar;
3025 const struct ath11k_hw_hal_params *hal_params;
3026 enum dp_mon_status_buf_state reap_status;
3027 struct ath11k_pdev_dp *dp;
3028 struct dp_rxdma_ring *rx_ring;
3029 struct ath11k_mon_data *pmon;
3030 struct hal_srng *srng;
3031 void *rx_mon_status_desc;
3032 struct sk_buff *skb;
3033 struct ath11k_skb_rxcb *rxcb;
3034 struct hal_tlv_hdr *tlv;
3035 u32 cookie;
3036 int buf_id, srng_id;
3037 dma_addr_t paddr;
3038 u8 rbm;
3039 int num_buffs_reaped = 0;
3040
3041 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3042 dp = &ar->dp;
3043 pmon = &dp->mon_data;
3044 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3045 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3046
3047 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3048
3049 spin_lock_bh(&srng->lock);
3050
3051 ath11k_hal_srng_access_begin(ab, srng);
3052 while (*budget) {
3053 *budget -= 1;
3054 rx_mon_status_desc =
3055 ath11k_hal_srng_src_peek(ab, srng);
3056 if (!rx_mon_status_desc) {
3057 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3058 break;
3059 }
3060
3061 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3062 &cookie, &rbm);
3063 if (paddr) {
3064 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3065
3066 spin_lock_bh(&rx_ring->idr_lock);
3067 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3068 spin_unlock_bh(&rx_ring->idr_lock);
3069
3070 if (!skb) {
3071 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3072 buf_id);
3073 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3074 goto move_next;
3075 }
3076
3077 rxcb = ATH11K_SKB_RXCB(skb);
3078
3079 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3080 skb->len + skb_tailroom(skb),
3081 DMA_FROM_DEVICE);
3082
3083 tlv = (struct hal_tlv_hdr *)skb->data;
3084 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3085 HAL_RX_STATUS_BUFFER_DONE) {
3086 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3087 FIELD_GET(HAL_TLV_HDR_TAG,
3088 tlv->tl), buf_id);
3089 /* RxDMA status done bit might not be set even
3090 * though tp is moved by HW.
3091 */
3092
3093 /* If done status is missing:
3094 * 1. As per MAC team's suggestion,
3095 * when HP + 1 entry is peeked and if DMA
3096 * is not done and if HP + 2 entry's DMA done
3097 * is set. skip HP + 1 entry and
3098 * start processing in next interrupt.
3099 * 2. If HP + 2 entry's DMA done is not set,
3100 * poll onto HP + 1 entry DMA done to be set.
3101 * Check status for same buffer for next time
3102 * dp_rx_mon_status_srng_process
3103 */
3104
3105 reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
3106 rx_ring);
3107 if (reap_status == DP_MON_STATUS_NO_DMA)
3108 continue;
3109
3110 spin_lock_bh(&rx_ring->idr_lock);
3111 idr_remove(&rx_ring->bufs_idr, buf_id);
3112 spin_unlock_bh(&rx_ring->idr_lock);
3113
3114 dma_unmap_single(ab->dev, rxcb->paddr,
3115 skb->len + skb_tailroom(skb),
3116 DMA_FROM_DEVICE);
3117
3118 dev_kfree_skb_any(skb);
3119 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3120 goto move_next;
3121 }
3122
3123 spin_lock_bh(&rx_ring->idr_lock);
3124 idr_remove(&rx_ring->bufs_idr, buf_id);
3125 spin_unlock_bh(&rx_ring->idr_lock);
3126 if (ab->hw_params.full_monitor_mode) {
3127 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3128 if (paddr == pmon->mon_status_paddr)
3129 pmon->buf_state = DP_MON_STATUS_MATCH;
3130 }
3131
3132 dma_unmap_single(ab->dev, rxcb->paddr,
3133 skb->len + skb_tailroom(skb),
3134 DMA_FROM_DEVICE);
3135
3136 __skb_queue_tail(skb_list, skb);
3137 } else {
3138 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3139 }
3140 move_next:
3141 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3142 &buf_id);
3143
3144 if (!skb) {
3145 hal_params = ab->hw_params.hal_params;
3146 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3147 hal_params->rx_buf_rbm);
3148 num_buffs_reaped++;
3149 break;
3150 }
3151 rxcb = ATH11K_SKB_RXCB(skb);
3152
3153 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3154 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3155
3156 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3157 cookie,
3158 ab->hw_params.hal_params->rx_buf_rbm);
3159 ath11k_hal_srng_src_get_next_entry(ab, srng);
3160 num_buffs_reaped++;
3161 }
3162 ath11k_hal_srng_access_end(ab, srng);
3163 spin_unlock_bh(&srng->lock);
3164
3165 return num_buffs_reaped;
3166 }
3167
ath11k_dp_rx_frag_timer(struct timer_list * timer)3168 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3169 {
3170 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3171
3172 spin_lock_bh(&rx_tid->ab->base_lock);
3173 if (rx_tid->last_frag_no &&
3174 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3175 spin_unlock_bh(&rx_tid->ab->base_lock);
3176 return;
3177 }
3178 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3179 spin_unlock_bh(&rx_tid->ab->base_lock);
3180 }
3181
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3182 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3183 {
3184 struct ath11k_base *ab = ar->ab;
3185 struct crypto_shash *tfm;
3186 struct ath11k_peer *peer;
3187 struct dp_rx_tid *rx_tid;
3188 int i;
3189
3190 tfm = crypto_alloc_shash("michael_mic", 0, 0);
3191 if (IS_ERR(tfm)) {
3192 ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
3193 PTR_ERR(tfm));
3194 return PTR_ERR(tfm);
3195 }
3196
3197 spin_lock_bh(&ab->base_lock);
3198
3199 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3200 if (!peer) {
3201 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3202 spin_unlock_bh(&ab->base_lock);
3203 crypto_free_shash(tfm);
3204 return -ENOENT;
3205 }
3206
3207 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3208 rx_tid = &peer->rx_tid[i];
3209 rx_tid->ab = ab;
3210 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3211 skb_queue_head_init(&rx_tid->rx_frags);
3212 }
3213
3214 peer->tfm_mmic = tfm;
3215 peer->dp_setup_done = true;
3216 spin_unlock_bh(&ab->base_lock);
3217
3218 return 0;
3219 }
3220
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3221 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3222 struct ieee80211_hdr *hdr, u8 *data,
3223 size_t data_len, u8 *mic)
3224 {
3225 SHASH_DESC_ON_STACK(desc, tfm);
3226 u8 mic_hdr[16] = {0};
3227 u8 tid = 0;
3228 int ret;
3229
3230 if (!tfm)
3231 return -EINVAL;
3232
3233 desc->tfm = tfm;
3234
3235 ret = crypto_shash_setkey(tfm, key, 8);
3236 if (ret)
3237 goto out;
3238
3239 ret = crypto_shash_init(desc);
3240 if (ret)
3241 goto out;
3242
3243 /* TKIP MIC header */
3244 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3245 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3246 if (ieee80211_is_data_qos(hdr->frame_control))
3247 tid = ieee80211_get_tid(hdr);
3248 mic_hdr[12] = tid;
3249
3250 ret = crypto_shash_update(desc, mic_hdr, 16);
3251 if (ret)
3252 goto out;
3253 ret = crypto_shash_update(desc, data, data_len);
3254 if (ret)
3255 goto out;
3256 ret = crypto_shash_final(desc, mic);
3257 out:
3258 shash_desc_zero(desc);
3259 return ret;
3260 }
3261
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3262 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3263 struct sk_buff *msdu)
3264 {
3265 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3266 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3267 struct ieee80211_key_conf *key_conf;
3268 struct ieee80211_hdr *hdr;
3269 u8 mic[IEEE80211_CCMP_MIC_LEN];
3270 int head_len, tail_len, ret;
3271 size_t data_len;
3272 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3273 u8 *key, *data;
3274 u8 key_idx;
3275
3276 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3277 HAL_ENCRYPT_TYPE_TKIP_MIC)
3278 return 0;
3279
3280 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3281 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3282 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3283 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3284
3285 if (!is_multicast_ether_addr(hdr->addr1))
3286 key_idx = peer->ucast_keyidx;
3287 else
3288 key_idx = peer->mcast_keyidx;
3289
3290 key_conf = peer->keys[key_idx];
3291
3292 data = msdu->data + head_len;
3293 data_len = msdu->len - head_len - tail_len;
3294 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3295
3296 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3297 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3298 goto mic_fail;
3299
3300 return 0;
3301
3302 mic_fail:
3303 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3304 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3305
3306 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3307 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3308 skb_pull(msdu, hal_rx_desc_sz);
3309
3310 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3311 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3312 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3313 ieee80211_rx(ar->hw, msdu);
3314 return -EINVAL;
3315 }
3316
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3317 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3318 enum hal_encrypt_type enctype, u32 flags)
3319 {
3320 struct ieee80211_hdr *hdr;
3321 size_t hdr_len;
3322 size_t crypto_len;
3323 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3324
3325 if (!flags)
3326 return;
3327
3328 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3329
3330 if (flags & RX_FLAG_MIC_STRIPPED)
3331 skb_trim(msdu, msdu->len -
3332 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3333
3334 if (flags & RX_FLAG_ICV_STRIPPED)
3335 skb_trim(msdu, msdu->len -
3336 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3337
3338 if (flags & RX_FLAG_IV_STRIPPED) {
3339 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3340 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3341
3342 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3343 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3344 skb_pull(msdu, crypto_len);
3345 }
3346 }
3347
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3348 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3349 struct ath11k_peer *peer,
3350 struct dp_rx_tid *rx_tid,
3351 struct sk_buff **defrag_skb)
3352 {
3353 struct hal_rx_desc *rx_desc;
3354 struct sk_buff *skb, *first_frag, *last_frag;
3355 struct ieee80211_hdr *hdr;
3356 struct rx_attention *rx_attention;
3357 enum hal_encrypt_type enctype;
3358 bool is_decrypted = false;
3359 int msdu_len = 0;
3360 int extra_space;
3361 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3362
3363 first_frag = skb_peek(&rx_tid->rx_frags);
3364 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3365
3366 skb_queue_walk(&rx_tid->rx_frags, skb) {
3367 flags = 0;
3368 rx_desc = (struct hal_rx_desc *)skb->data;
3369 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3370
3371 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3372 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3373 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3374 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3375 }
3376
3377 if (is_decrypted) {
3378 if (skb != first_frag)
3379 flags |= RX_FLAG_IV_STRIPPED;
3380 if (skb != last_frag)
3381 flags |= RX_FLAG_ICV_STRIPPED |
3382 RX_FLAG_MIC_STRIPPED;
3383 }
3384
3385 /* RX fragments are always raw packets */
3386 if (skb != last_frag)
3387 skb_trim(skb, skb->len - FCS_LEN);
3388 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3389
3390 if (skb != first_frag)
3391 skb_pull(skb, hal_rx_desc_sz +
3392 ieee80211_hdrlen(hdr->frame_control));
3393 msdu_len += skb->len;
3394 }
3395
3396 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3397 if (extra_space > 0 &&
3398 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3399 return -ENOMEM;
3400
3401 __skb_unlink(first_frag, &rx_tid->rx_frags);
3402 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3403 skb_put_data(first_frag, skb->data, skb->len);
3404 dev_kfree_skb_any(skb);
3405 }
3406
3407 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3408 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3409 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3410
3411 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3412 first_frag = NULL;
3413
3414 *defrag_skb = first_frag;
3415 return 0;
3416 }
3417
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3418 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3419 struct sk_buff *defrag_skb)
3420 {
3421 struct ath11k_base *ab = ar->ab;
3422 struct ath11k_pdev_dp *dp = &ar->dp;
3423 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3424 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3425 struct hal_reo_entrance_ring *reo_ent_ring;
3426 struct hal_reo_dest_ring *reo_dest_ring;
3427 struct dp_link_desc_bank *link_desc_banks;
3428 struct hal_rx_msdu_link *msdu_link;
3429 struct hal_rx_msdu_details *msdu0;
3430 struct hal_srng *srng;
3431 dma_addr_t paddr;
3432 u32 desc_bank, msdu_info, mpdu_info;
3433 u32 dst_idx, cookie, hal_rx_desc_sz;
3434 int ret, buf_id;
3435
3436 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3437 link_desc_banks = ab->dp.link_desc_banks;
3438 reo_dest_ring = rx_tid->dst_ring_desc;
3439
3440 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3441 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3442 (paddr - link_desc_banks[desc_bank].paddr));
3443 msdu0 = &msdu_link->msdu_link[0];
3444 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3445 memset(msdu0, 0, sizeof(*msdu0));
3446
3447 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3448 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3449 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3450 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3451 defrag_skb->len - hal_rx_desc_sz) |
3452 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3453 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3454 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3455 msdu0->rx_msdu_info.info0 = msdu_info;
3456
3457 /* change msdu len in hal rx desc */
3458 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3459
3460 paddr = dma_map_single(ab->dev, defrag_skb->data,
3461 defrag_skb->len + skb_tailroom(defrag_skb),
3462 DMA_TO_DEVICE);
3463 if (dma_mapping_error(ab->dev, paddr))
3464 return -ENOMEM;
3465
3466 spin_lock_bh(&rx_refill_ring->idr_lock);
3467 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3468 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3469 spin_unlock_bh(&rx_refill_ring->idr_lock);
3470 if (buf_id < 0) {
3471 ret = -ENOMEM;
3472 goto err_unmap_dma;
3473 }
3474
3475 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3476 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3477 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3478
3479 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3480 ab->hw_params.hal_params->rx_buf_rbm);
3481
3482 /* Fill mpdu details into reo entrance ring */
3483 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3484
3485 spin_lock_bh(&srng->lock);
3486 ath11k_hal_srng_access_begin(ab, srng);
3487
3488 reo_ent_ring = (struct hal_reo_entrance_ring *)
3489 ath11k_hal_srng_src_get_next_entry(ab, srng);
3490 if (!reo_ent_ring) {
3491 ath11k_hal_srng_access_end(ab, srng);
3492 spin_unlock_bh(&srng->lock);
3493 ret = -ENOSPC;
3494 goto err_free_idr;
3495 }
3496 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3497
3498 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3499 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3500 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3501
3502 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3503 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3504 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3505 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3506 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3507 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3508 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3509
3510 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3511 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3512 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3513 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3514 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3515 reo_dest_ring->info0)) |
3516 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3517 ath11k_hal_srng_access_end(ab, srng);
3518 spin_unlock_bh(&srng->lock);
3519
3520 return 0;
3521
3522 err_free_idr:
3523 spin_lock_bh(&rx_refill_ring->idr_lock);
3524 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3525 spin_unlock_bh(&rx_refill_ring->idr_lock);
3526 err_unmap_dma:
3527 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3528 DMA_TO_DEVICE);
3529 return ret;
3530 }
3531
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3532 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3533 struct sk_buff *a, struct sk_buff *b)
3534 {
3535 int frag1, frag2;
3536
3537 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3538 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3539
3540 return frag1 - frag2;
3541 }
3542
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3543 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3544 struct sk_buff_head *frag_list,
3545 struct sk_buff *cur_frag)
3546 {
3547 struct sk_buff *skb;
3548 int cmp;
3549
3550 skb_queue_walk(frag_list, skb) {
3551 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3552 if (cmp < 0)
3553 continue;
3554 __skb_queue_before(frag_list, skb, cur_frag);
3555 return;
3556 }
3557 __skb_queue_tail(frag_list, cur_frag);
3558 }
3559
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3560 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3561 {
3562 struct ieee80211_hdr *hdr;
3563 u64 pn = 0;
3564 u8 *ehdr;
3565 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3566
3567 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3568 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3569
3570 pn = ehdr[0];
3571 pn |= (u64)ehdr[1] << 8;
3572 pn |= (u64)ehdr[4] << 16;
3573 pn |= (u64)ehdr[5] << 24;
3574 pn |= (u64)ehdr[6] << 32;
3575 pn |= (u64)ehdr[7] << 40;
3576
3577 return pn;
3578 }
3579
3580 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3581 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3582 {
3583 enum hal_encrypt_type encrypt_type;
3584 struct sk_buff *first_frag, *skb;
3585 struct hal_rx_desc *desc;
3586 u64 last_pn;
3587 u64 cur_pn;
3588
3589 first_frag = skb_peek(&rx_tid->rx_frags);
3590 desc = (struct hal_rx_desc *)first_frag->data;
3591
3592 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3593 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3594 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3595 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3596 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3597 return true;
3598
3599 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3600 skb_queue_walk(&rx_tid->rx_frags, skb) {
3601 if (skb == first_frag)
3602 continue;
3603
3604 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3605 if (cur_pn != last_pn + 1)
3606 return false;
3607 last_pn = cur_pn;
3608 }
3609 return true;
3610 }
3611
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3612 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3613 struct sk_buff *msdu,
3614 u32 *ring_desc)
3615 {
3616 struct ath11k_base *ab = ar->ab;
3617 struct hal_rx_desc *rx_desc;
3618 struct ath11k_peer *peer;
3619 struct dp_rx_tid *rx_tid;
3620 struct sk_buff *defrag_skb = NULL;
3621 u32 peer_id;
3622 u16 seqno, frag_no;
3623 u8 tid;
3624 int ret = 0;
3625 bool more_frags;
3626 bool is_mcbc;
3627
3628 rx_desc = (struct hal_rx_desc *)msdu->data;
3629 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3630 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3631 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3632 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3633 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3634 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3635
3636 /* Multicast/Broadcast fragments are not expected */
3637 if (is_mcbc)
3638 return -EINVAL;
3639
3640 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3641 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3642 tid > IEEE80211_NUM_TIDS)
3643 return -EINVAL;
3644
3645 /* received unfragmented packet in reo
3646 * exception ring, this shouldn't happen
3647 * as these packets typically come from
3648 * reo2sw srngs.
3649 */
3650 if (WARN_ON_ONCE(!frag_no && !more_frags))
3651 return -EINVAL;
3652
3653 spin_lock_bh(&ab->base_lock);
3654 peer = ath11k_peer_find_by_id(ab, peer_id);
3655 if (!peer) {
3656 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3657 peer_id);
3658 ret = -ENOENT;
3659 goto out_unlock;
3660 }
3661 if (!peer->dp_setup_done) {
3662 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3663 peer->addr, peer_id);
3664 ret = -ENOENT;
3665 goto out_unlock;
3666 }
3667
3668 rx_tid = &peer->rx_tid[tid];
3669
3670 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3671 skb_queue_empty(&rx_tid->rx_frags)) {
3672 /* Flush stored fragments and start a new sequence */
3673 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3674 rx_tid->cur_sn = seqno;
3675 }
3676
3677 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3678 /* Fragment already present */
3679 ret = -EINVAL;
3680 goto out_unlock;
3681 }
3682
3683 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3684 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3685 else
3686 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3687
3688 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3689 if (!more_frags)
3690 rx_tid->last_frag_no = frag_no;
3691
3692 if (frag_no == 0) {
3693 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3694 sizeof(*rx_tid->dst_ring_desc),
3695 GFP_ATOMIC);
3696 if (!rx_tid->dst_ring_desc) {
3697 ret = -ENOMEM;
3698 goto out_unlock;
3699 }
3700 } else {
3701 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3702 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3703 }
3704
3705 if (!rx_tid->last_frag_no ||
3706 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3707 mod_timer(&rx_tid->frag_timer, jiffies +
3708 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3709 goto out_unlock;
3710 }
3711
3712 spin_unlock_bh(&ab->base_lock);
3713 del_timer_sync(&rx_tid->frag_timer);
3714 spin_lock_bh(&ab->base_lock);
3715
3716 peer = ath11k_peer_find_by_id(ab, peer_id);
3717 if (!peer)
3718 goto err_frags_cleanup;
3719
3720 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3721 goto err_frags_cleanup;
3722
3723 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3724 goto err_frags_cleanup;
3725
3726 if (!defrag_skb)
3727 goto err_frags_cleanup;
3728
3729 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3730 goto err_frags_cleanup;
3731
3732 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3733 goto out_unlock;
3734
3735 err_frags_cleanup:
3736 dev_kfree_skb_any(defrag_skb);
3737 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3738 out_unlock:
3739 spin_unlock_bh(&ab->base_lock);
3740 return ret;
3741 }
3742
3743 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3744 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3745 {
3746 struct ath11k_pdev_dp *dp = &ar->dp;
3747 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3748 struct sk_buff *msdu;
3749 struct ath11k_skb_rxcb *rxcb;
3750 struct hal_rx_desc *rx_desc;
3751 u8 *hdr_status;
3752 u16 msdu_len;
3753 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3754
3755 spin_lock_bh(&rx_ring->idr_lock);
3756 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3757 if (!msdu) {
3758 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3759 buf_id);
3760 spin_unlock_bh(&rx_ring->idr_lock);
3761 return -EINVAL;
3762 }
3763
3764 idr_remove(&rx_ring->bufs_idr, buf_id);
3765 spin_unlock_bh(&rx_ring->idr_lock);
3766
3767 rxcb = ATH11K_SKB_RXCB(msdu);
3768 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3769 msdu->len + skb_tailroom(msdu),
3770 DMA_FROM_DEVICE);
3771
3772 if (drop) {
3773 dev_kfree_skb_any(msdu);
3774 return 0;
3775 }
3776
3777 rcu_read_lock();
3778 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3779 dev_kfree_skb_any(msdu);
3780 goto exit;
3781 }
3782
3783 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3784 dev_kfree_skb_any(msdu);
3785 goto exit;
3786 }
3787
3788 rx_desc = (struct hal_rx_desc *)msdu->data;
3789 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3790 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3791 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3792 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3793 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3794 sizeof(struct ieee80211_hdr));
3795 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3796 sizeof(struct hal_rx_desc));
3797 dev_kfree_skb_any(msdu);
3798 goto exit;
3799 }
3800
3801 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3802
3803 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3804 dev_kfree_skb_any(msdu);
3805 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3806 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3807 }
3808 exit:
3809 rcu_read_unlock();
3810 return 0;
3811 }
3812
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3813 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3814 int budget)
3815 {
3816 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3817 struct dp_link_desc_bank *link_desc_banks;
3818 enum hal_rx_buf_return_buf_manager rbm;
3819 int tot_n_bufs_reaped, quota, ret, i;
3820 int n_bufs_reaped[MAX_RADIOS] = {0};
3821 struct dp_rxdma_ring *rx_ring;
3822 struct dp_srng *reo_except;
3823 u32 desc_bank, num_msdus;
3824 struct hal_srng *srng;
3825 struct ath11k_dp *dp;
3826 void *link_desc_va;
3827 int buf_id, mac_id;
3828 struct ath11k *ar;
3829 dma_addr_t paddr;
3830 u32 *desc;
3831 bool is_frag;
3832 u8 drop = 0;
3833
3834 tot_n_bufs_reaped = 0;
3835 quota = budget;
3836
3837 dp = &ab->dp;
3838 reo_except = &dp->reo_except_ring;
3839 link_desc_banks = dp->link_desc_banks;
3840
3841 srng = &ab->hal.srng_list[reo_except->ring_id];
3842
3843 spin_lock_bh(&srng->lock);
3844
3845 ath11k_hal_srng_access_begin(ab, srng);
3846
3847 while (budget &&
3848 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3849 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3850
3851 ab->soc_stats.err_ring_pkts++;
3852 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3853 &desc_bank);
3854 if (ret) {
3855 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3856 ret);
3857 continue;
3858 }
3859 link_desc_va = link_desc_banks[desc_bank].vaddr +
3860 (paddr - link_desc_banks[desc_bank].paddr);
3861 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3862 &rbm);
3863 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3864 rbm != HAL_RX_BUF_RBM_SW1_BM &&
3865 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3866 ab->soc_stats.invalid_rbm++;
3867 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3868 ath11k_dp_rx_link_desc_return(ab, desc,
3869 HAL_WBM_REL_BM_ACT_REL_MSDU);
3870 continue;
3871 }
3872
3873 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3874
3875 /* Process only rx fragments with one msdu per link desc below, and drop
3876 * msdu's indicated due to error reasons.
3877 */
3878 if (!is_frag || num_msdus > 1) {
3879 drop = 1;
3880 /* Return the link desc back to wbm idle list */
3881 ath11k_dp_rx_link_desc_return(ab, desc,
3882 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3883 }
3884
3885 for (i = 0; i < num_msdus; i++) {
3886 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3887 msdu_cookies[i]);
3888
3889 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3890 msdu_cookies[i]);
3891
3892 ar = ab->pdevs[mac_id].ar;
3893
3894 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3895 n_bufs_reaped[mac_id]++;
3896 tot_n_bufs_reaped++;
3897 }
3898 }
3899
3900 if (tot_n_bufs_reaped >= quota) {
3901 tot_n_bufs_reaped = quota;
3902 goto exit;
3903 }
3904
3905 budget = quota - tot_n_bufs_reaped;
3906 }
3907
3908 exit:
3909 ath11k_hal_srng_access_end(ab, srng);
3910
3911 spin_unlock_bh(&srng->lock);
3912
3913 for (i = 0; i < ab->num_radios; i++) {
3914 if (!n_bufs_reaped[i])
3915 continue;
3916
3917 ar = ab->pdevs[i].ar;
3918 rx_ring = &ar->dp.rx_refill_buf_ring;
3919
3920 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3921 ab->hw_params.hal_params->rx_buf_rbm);
3922 }
3923
3924 return tot_n_bufs_reaped;
3925 }
3926
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3927 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3928 int msdu_len,
3929 struct sk_buff_head *msdu_list)
3930 {
3931 struct sk_buff *skb, *tmp;
3932 struct ath11k_skb_rxcb *rxcb;
3933 int n_buffs;
3934
3935 n_buffs = DIV_ROUND_UP(msdu_len,
3936 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3937
3938 skb_queue_walk_safe(msdu_list, skb, tmp) {
3939 rxcb = ATH11K_SKB_RXCB(skb);
3940 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3941 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3942 if (!n_buffs)
3943 break;
3944 __skb_unlink(skb, msdu_list);
3945 dev_kfree_skb_any(skb);
3946 n_buffs--;
3947 }
3948 }
3949 }
3950
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3951 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3952 struct ieee80211_rx_status *status,
3953 struct sk_buff_head *msdu_list)
3954 {
3955 u16 msdu_len;
3956 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3957 struct rx_attention *rx_attention;
3958 u8 l3pad_bytes;
3959 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3960 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3961
3962 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3963
3964 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3965 /* First buffer will be freed by the caller, so deduct it's length */
3966 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3967 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3968 return -EINVAL;
3969 }
3970
3971 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3972 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3973 ath11k_warn(ar->ab,
3974 "msdu_done bit not set in null_q_des processing\n");
3975 __skb_queue_purge(msdu_list);
3976 return -EIO;
3977 }
3978
3979 /* Handle NULL queue descriptor violations arising out a missing
3980 * REO queue for a given peer or a given TID. This typically
3981 * may happen if a packet is received on a QOS enabled TID before the
3982 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3983 * it may also happen for MC/BC frames if they are not routed to the
3984 * non-QOS TID queue, in the absence of any other default TID queue.
3985 * This error can show up both in a REO destination or WBM release ring.
3986 */
3987
3988 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3989 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3990
3991 if (rxcb->is_frag) {
3992 skb_pull(msdu, hal_rx_desc_sz);
3993 } else {
3994 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3995
3996 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3997 return -EINVAL;
3998
3999 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4000 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4001 }
4002 ath11k_dp_rx_h_ppdu(ar, desc, status);
4003
4004 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
4005
4006 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
4007
4008 /* Please note that caller will having the access to msdu and completing
4009 * rx with mac80211. Need not worry about cleaning up amsdu_list.
4010 */
4011
4012 return 0;
4013 }
4014
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4015 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
4016 struct ieee80211_rx_status *status,
4017 struct sk_buff_head *msdu_list)
4018 {
4019 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4020 bool drop = false;
4021
4022 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
4023
4024 switch (rxcb->err_code) {
4025 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
4026 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
4027 drop = true;
4028 break;
4029 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
4030 /* TODO: Do not drop PN failed packets in the driver;
4031 * instead, it is good to drop such packets in mac80211
4032 * after incrementing the replay counters.
4033 */
4034 fallthrough;
4035 default:
4036 /* TODO: Review other errors and process them to mac80211
4037 * as appropriate.
4038 */
4039 drop = true;
4040 break;
4041 }
4042
4043 return drop;
4044 }
4045
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4046 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4047 struct ieee80211_rx_status *status)
4048 {
4049 u16 msdu_len;
4050 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4051 u8 l3pad_bytes;
4052 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4053 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4054
4055 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4056 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4057
4058 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4059 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4060 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4061 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4062
4063 ath11k_dp_rx_h_ppdu(ar, desc, status);
4064
4065 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4066 RX_FLAG_DECRYPTED);
4067
4068 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4069 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4070 }
4071
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4072 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4073 struct ieee80211_rx_status *status)
4074 {
4075 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4076 bool drop = false;
4077
4078 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4079
4080 switch (rxcb->err_code) {
4081 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4082 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4083 break;
4084 default:
4085 /* TODO: Review other rxdma error code to check if anything is
4086 * worth reporting to mac80211
4087 */
4088 drop = true;
4089 break;
4090 }
4091
4092 return drop;
4093 }
4094
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4095 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4096 struct napi_struct *napi,
4097 struct sk_buff *msdu,
4098 struct sk_buff_head *msdu_list)
4099 {
4100 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4101 struct ieee80211_rx_status rxs = {0};
4102 bool drop = true;
4103
4104 switch (rxcb->err_rel_src) {
4105 case HAL_WBM_REL_SRC_MODULE_REO:
4106 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4107 break;
4108 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4109 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4110 break;
4111 default:
4112 /* msdu will get freed */
4113 break;
4114 }
4115
4116 if (drop) {
4117 dev_kfree_skb_any(msdu);
4118 return;
4119 }
4120
4121 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4122 }
4123
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4124 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4125 struct napi_struct *napi, int budget)
4126 {
4127 struct ath11k *ar;
4128 struct ath11k_dp *dp = &ab->dp;
4129 struct dp_rxdma_ring *rx_ring;
4130 struct hal_rx_wbm_rel_info err_info;
4131 struct hal_srng *srng;
4132 struct sk_buff *msdu;
4133 struct sk_buff_head msdu_list[MAX_RADIOS];
4134 struct ath11k_skb_rxcb *rxcb;
4135 u32 *rx_desc;
4136 int buf_id, mac_id;
4137 int num_buffs_reaped[MAX_RADIOS] = {0};
4138 int total_num_buffs_reaped = 0;
4139 int ret, i;
4140
4141 for (i = 0; i < ab->num_radios; i++)
4142 __skb_queue_head_init(&msdu_list[i]);
4143
4144 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4145
4146 spin_lock_bh(&srng->lock);
4147
4148 ath11k_hal_srng_access_begin(ab, srng);
4149
4150 while (budget) {
4151 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4152 if (!rx_desc)
4153 break;
4154
4155 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4156 if (ret) {
4157 ath11k_warn(ab,
4158 "failed to parse rx error in wbm_rel ring desc %d\n",
4159 ret);
4160 continue;
4161 }
4162
4163 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4164 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4165
4166 ar = ab->pdevs[mac_id].ar;
4167 rx_ring = &ar->dp.rx_refill_buf_ring;
4168
4169 spin_lock_bh(&rx_ring->idr_lock);
4170 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4171 if (!msdu) {
4172 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4173 buf_id, mac_id);
4174 spin_unlock_bh(&rx_ring->idr_lock);
4175 continue;
4176 }
4177
4178 idr_remove(&rx_ring->bufs_idr, buf_id);
4179 spin_unlock_bh(&rx_ring->idr_lock);
4180
4181 rxcb = ATH11K_SKB_RXCB(msdu);
4182 dma_unmap_single(ab->dev, rxcb->paddr,
4183 msdu->len + skb_tailroom(msdu),
4184 DMA_FROM_DEVICE);
4185
4186 num_buffs_reaped[mac_id]++;
4187 total_num_buffs_reaped++;
4188 budget--;
4189
4190 if (err_info.push_reason !=
4191 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4192 dev_kfree_skb_any(msdu);
4193 continue;
4194 }
4195
4196 rxcb->err_rel_src = err_info.err_rel_src;
4197 rxcb->err_code = err_info.err_code;
4198 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4199 __skb_queue_tail(&msdu_list[mac_id], msdu);
4200 }
4201
4202 ath11k_hal_srng_access_end(ab, srng);
4203
4204 spin_unlock_bh(&srng->lock);
4205
4206 if (!total_num_buffs_reaped)
4207 goto done;
4208
4209 for (i = 0; i < ab->num_radios; i++) {
4210 if (!num_buffs_reaped[i])
4211 continue;
4212
4213 ar = ab->pdevs[i].ar;
4214 rx_ring = &ar->dp.rx_refill_buf_ring;
4215
4216 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4217 ab->hw_params.hal_params->rx_buf_rbm);
4218 }
4219
4220 rcu_read_lock();
4221 for (i = 0; i < ab->num_radios; i++) {
4222 if (!rcu_dereference(ab->pdevs_active[i])) {
4223 __skb_queue_purge(&msdu_list[i]);
4224 continue;
4225 }
4226
4227 ar = ab->pdevs[i].ar;
4228
4229 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4230 __skb_queue_purge(&msdu_list[i]);
4231 continue;
4232 }
4233
4234 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4235 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4236 }
4237 rcu_read_unlock();
4238 done:
4239 return total_num_buffs_reaped;
4240 }
4241
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4242 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4243 {
4244 struct ath11k *ar;
4245 struct dp_srng *err_ring;
4246 struct dp_rxdma_ring *rx_ring;
4247 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4248 struct hal_srng *srng;
4249 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4250 enum hal_rx_buf_return_buf_manager rbm;
4251 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4252 struct ath11k_skb_rxcb *rxcb;
4253 struct sk_buff *skb;
4254 struct hal_reo_entrance_ring *entr_ring;
4255 void *desc;
4256 int num_buf_freed = 0;
4257 int quota = budget;
4258 dma_addr_t paddr;
4259 u32 desc_bank;
4260 void *link_desc_va;
4261 int num_msdus;
4262 int i;
4263 int buf_id;
4264
4265 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4266 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4267 mac_id)];
4268 rx_ring = &ar->dp.rx_refill_buf_ring;
4269
4270 srng = &ab->hal.srng_list[err_ring->ring_id];
4271
4272 spin_lock_bh(&srng->lock);
4273
4274 ath11k_hal_srng_access_begin(ab, srng);
4275
4276 while (quota-- &&
4277 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4278 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4279
4280 entr_ring = (struct hal_reo_entrance_ring *)desc;
4281 rxdma_err_code =
4282 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4283 entr_ring->info1);
4284 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4285
4286 link_desc_va = link_desc_banks[desc_bank].vaddr +
4287 (paddr - link_desc_banks[desc_bank].paddr);
4288 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4289 msdu_cookies, &rbm);
4290
4291 for (i = 0; i < num_msdus; i++) {
4292 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4293 msdu_cookies[i]);
4294
4295 spin_lock_bh(&rx_ring->idr_lock);
4296 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4297 if (!skb) {
4298 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4299 buf_id);
4300 spin_unlock_bh(&rx_ring->idr_lock);
4301 continue;
4302 }
4303
4304 idr_remove(&rx_ring->bufs_idr, buf_id);
4305 spin_unlock_bh(&rx_ring->idr_lock);
4306
4307 rxcb = ATH11K_SKB_RXCB(skb);
4308 dma_unmap_single(ab->dev, rxcb->paddr,
4309 skb->len + skb_tailroom(skb),
4310 DMA_FROM_DEVICE);
4311 dev_kfree_skb_any(skb);
4312
4313 num_buf_freed++;
4314 }
4315
4316 ath11k_dp_rx_link_desc_return(ab, desc,
4317 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4318 }
4319
4320 ath11k_hal_srng_access_end(ab, srng);
4321
4322 spin_unlock_bh(&srng->lock);
4323
4324 if (num_buf_freed)
4325 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4326 ab->hw_params.hal_params->rx_buf_rbm);
4327
4328 return budget - quota;
4329 }
4330
ath11k_dp_process_reo_status(struct ath11k_base * ab)4331 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4332 {
4333 struct ath11k_dp *dp = &ab->dp;
4334 struct hal_srng *srng;
4335 struct dp_reo_cmd *cmd, *tmp;
4336 bool found = false;
4337 u32 *reo_desc;
4338 u16 tag;
4339 struct hal_reo_status reo_status;
4340
4341 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4342
4343 memset(&reo_status, 0, sizeof(reo_status));
4344
4345 spin_lock_bh(&srng->lock);
4346
4347 ath11k_hal_srng_access_begin(ab, srng);
4348
4349 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4350 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4351
4352 switch (tag) {
4353 case HAL_REO_GET_QUEUE_STATS_STATUS:
4354 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4355 &reo_status);
4356 break;
4357 case HAL_REO_FLUSH_QUEUE_STATUS:
4358 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4359 &reo_status);
4360 break;
4361 case HAL_REO_FLUSH_CACHE_STATUS:
4362 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4363 &reo_status);
4364 break;
4365 case HAL_REO_UNBLOCK_CACHE_STATUS:
4366 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4367 &reo_status);
4368 break;
4369 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4370 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4371 &reo_status);
4372 break;
4373 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4374 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4375 &reo_status);
4376 break;
4377 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4378 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4379 &reo_status);
4380 break;
4381 default:
4382 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4383 continue;
4384 }
4385
4386 spin_lock_bh(&dp->reo_cmd_lock);
4387 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4388 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4389 found = true;
4390 list_del(&cmd->list);
4391 break;
4392 }
4393 }
4394 spin_unlock_bh(&dp->reo_cmd_lock);
4395
4396 if (found) {
4397 cmd->handler(dp, (void *)&cmd->data,
4398 reo_status.uniform_hdr.cmd_status);
4399 kfree(cmd);
4400 }
4401
4402 found = false;
4403 }
4404
4405 ath11k_hal_srng_access_end(ab, srng);
4406
4407 spin_unlock_bh(&srng->lock);
4408 }
4409
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4410 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4411 {
4412 struct ath11k *ar = ab->pdevs[mac_id].ar;
4413
4414 ath11k_dp_rx_pdev_srng_free(ar);
4415 ath11k_dp_rxdma_pdev_buf_free(ar);
4416 }
4417
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4418 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4419 {
4420 struct ath11k *ar = ab->pdevs[mac_id].ar;
4421 struct ath11k_pdev_dp *dp = &ar->dp;
4422 u32 ring_id;
4423 int i;
4424 int ret;
4425
4426 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4427 if (ret) {
4428 ath11k_warn(ab, "failed to setup rx srngs\n");
4429 return ret;
4430 }
4431
4432 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4433 if (ret) {
4434 ath11k_warn(ab, "failed to setup rxdma ring\n");
4435 return ret;
4436 }
4437
4438 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4439 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4440 if (ret) {
4441 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4442 ret);
4443 return ret;
4444 }
4445
4446 if (ab->hw_params.rx_mac_buf_ring) {
4447 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4448 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4449 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4450 mac_id + i, HAL_RXDMA_BUF);
4451 if (ret) {
4452 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4453 i, ret);
4454 return ret;
4455 }
4456 }
4457 }
4458
4459 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4460 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4461 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4462 mac_id + i, HAL_RXDMA_DST);
4463 if (ret) {
4464 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4465 i, ret);
4466 return ret;
4467 }
4468 }
4469
4470 if (!ab->hw_params.rxdma1_enable)
4471 goto config_refill_ring;
4472
4473 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4474 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4475 mac_id, HAL_RXDMA_MONITOR_BUF);
4476 if (ret) {
4477 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4478 ret);
4479 return ret;
4480 }
4481 ret = ath11k_dp_tx_htt_srng_setup(ab,
4482 dp->rxdma_mon_dst_ring.ring_id,
4483 mac_id, HAL_RXDMA_MONITOR_DST);
4484 if (ret) {
4485 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4486 ret);
4487 return ret;
4488 }
4489 ret = ath11k_dp_tx_htt_srng_setup(ab,
4490 dp->rxdma_mon_desc_ring.ring_id,
4491 mac_id, HAL_RXDMA_MONITOR_DESC);
4492 if (ret) {
4493 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4494 ret);
4495 return ret;
4496 }
4497
4498 config_refill_ring:
4499 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4500 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4501 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4502 HAL_RXDMA_MONITOR_STATUS);
4503 if (ret) {
4504 ath11k_warn(ab,
4505 "failed to configure mon_status_refill_ring%d %d\n",
4506 i, ret);
4507 return ret;
4508 }
4509 }
4510
4511 return 0;
4512 }
4513
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4514 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4515 {
4516 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4517 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4518 *total_len -= *frag_len;
4519 } else {
4520 *frag_len = *total_len;
4521 *total_len = 0;
4522 }
4523 }
4524
4525 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4526 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4527 void *p_last_buf_addr_info,
4528 u8 mac_id)
4529 {
4530 struct ath11k_pdev_dp *dp = &ar->dp;
4531 struct dp_srng *dp_srng;
4532 void *hal_srng;
4533 void *src_srng_desc;
4534 int ret = 0;
4535
4536 if (ar->ab->hw_params.rxdma1_enable) {
4537 dp_srng = &dp->rxdma_mon_desc_ring;
4538 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4539 } else {
4540 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4541 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4542 }
4543
4544 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4545
4546 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4547
4548 if (src_srng_desc) {
4549 struct ath11k_buffer_addr *src_desc = src_srng_desc;
4550
4551 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4552 } else {
4553 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4554 "Monitor Link Desc Ring %d Full", mac_id);
4555 ret = -ENOMEM;
4556 }
4557
4558 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4559 return ret;
4560 }
4561
4562 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4563 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4564 dma_addr_t *paddr, u32 *sw_cookie,
4565 u8 *rbm,
4566 void **pp_buf_addr_info)
4567 {
4568 struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
4569 struct ath11k_buffer_addr *buf_addr_info;
4570
4571 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4572
4573 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4574
4575 *pp_buf_addr_info = (void *)buf_addr_info;
4576 }
4577
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4578 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4579 {
4580 if (skb->len > len) {
4581 skb_trim(skb, len);
4582 } else {
4583 if (skb_tailroom(skb) < len - skb->len) {
4584 if ((pskb_expand_head(skb, 0,
4585 len - skb->len - skb_tailroom(skb),
4586 GFP_ATOMIC))) {
4587 dev_kfree_skb_any(skb);
4588 return -ENOMEM;
4589 }
4590 }
4591 skb_put(skb, (len - skb->len));
4592 }
4593 return 0;
4594 }
4595
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4596 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4597 void *msdu_link_desc,
4598 struct hal_rx_msdu_list *msdu_list,
4599 u16 *num_msdus)
4600 {
4601 struct hal_rx_msdu_details *msdu_details = NULL;
4602 struct rx_msdu_desc *msdu_desc_info = NULL;
4603 struct hal_rx_msdu_link *msdu_link = NULL;
4604 int i;
4605 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4606 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4607 u8 tmp = 0;
4608
4609 msdu_link = msdu_link_desc;
4610 msdu_details = &msdu_link->msdu_link[0];
4611
4612 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4613 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4614 msdu_details[i].buf_addr_info.info0) == 0) {
4615 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4616 msdu_desc_info->info0 |= last;
4617 ;
4618 break;
4619 }
4620 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4621
4622 if (!i)
4623 msdu_desc_info->info0 |= first;
4624 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4625 msdu_desc_info->info0 |= last;
4626 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4627 msdu_list->msdu_info[i].msdu_len =
4628 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4629 msdu_list->sw_cookie[i] =
4630 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4631 msdu_details[i].buf_addr_info.info1);
4632 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4633 msdu_details[i].buf_addr_info.info1);
4634 msdu_list->rbm[i] = tmp;
4635 }
4636 *num_msdus = i;
4637 }
4638
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4639 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4640 u32 *rx_bufs_used)
4641 {
4642 u32 ret = 0;
4643
4644 if ((*ppdu_id < msdu_ppdu_id) &&
4645 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4646 *ppdu_id = msdu_ppdu_id;
4647 ret = msdu_ppdu_id;
4648 } else if ((*ppdu_id > msdu_ppdu_id) &&
4649 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4650 /* mon_dst is behind than mon_status
4651 * skip dst_ring and free it
4652 */
4653 *rx_bufs_used += 1;
4654 *ppdu_id = msdu_ppdu_id;
4655 ret = msdu_ppdu_id;
4656 }
4657 return ret;
4658 }
4659
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4660 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4661 bool *is_frag, u32 *total_len,
4662 u32 *frag_len, u32 *msdu_cnt)
4663 {
4664 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4665 if (!*is_frag) {
4666 *total_len = info->msdu_len;
4667 *is_frag = true;
4668 }
4669 ath11k_dp_mon_set_frag_len(total_len,
4670 frag_len);
4671 } else {
4672 if (*is_frag) {
4673 ath11k_dp_mon_set_frag_len(total_len,
4674 frag_len);
4675 } else {
4676 *frag_len = info->msdu_len;
4677 }
4678 *is_frag = false;
4679 *msdu_cnt -= 1;
4680 }
4681 }
4682
4683 /* clang stack usage explodes if this is inlined */
4684 static noinline_for_stack
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4685 u32 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4686 void *ring_entry, struct sk_buff **head_msdu,
4687 struct sk_buff **tail_msdu, u32 *npackets,
4688 u32 *ppdu_id)
4689 {
4690 struct ath11k_pdev_dp *dp = &ar->dp;
4691 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4692 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4693 struct sk_buff *msdu = NULL, *last = NULL;
4694 struct hal_rx_msdu_list msdu_list;
4695 void *p_buf_addr_info, *p_last_buf_addr_info;
4696 struct hal_rx_desc *rx_desc;
4697 void *rx_msdu_link_desc;
4698 dma_addr_t paddr;
4699 u16 num_msdus = 0;
4700 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4701 u32 rx_bufs_used = 0, i = 0;
4702 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4703 u32 total_len = 0, frag_len = 0;
4704 bool is_frag, is_first_msdu;
4705 bool drop_mpdu = false;
4706 struct ath11k_skb_rxcb *rxcb;
4707 struct hal_reo_entrance_ring *ent_desc = ring_entry;
4708 int buf_id;
4709 u32 rx_link_buf_info[2];
4710 u8 rbm;
4711
4712 if (!ar->ab->hw_params.rxdma1_enable)
4713 rx_ring = &dp->rx_refill_buf_ring;
4714
4715 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4716 &sw_cookie,
4717 &p_last_buf_addr_info, &rbm,
4718 &msdu_cnt);
4719
4720 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4721 ent_desc->info1) ==
4722 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4723 u8 rxdma_err =
4724 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4725 ent_desc->info1);
4726 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4727 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4728 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4729 drop_mpdu = true;
4730 pmon->rx_mon_stats.dest_mpdu_drop++;
4731 }
4732 }
4733
4734 is_frag = false;
4735 is_first_msdu = true;
4736
4737 do {
4738 if (pmon->mon_last_linkdesc_paddr == paddr) {
4739 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4740 return rx_bufs_used;
4741 }
4742
4743 if (ar->ab->hw_params.rxdma1_enable)
4744 rx_msdu_link_desc =
4745 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4746 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4747 else
4748 rx_msdu_link_desc =
4749 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4750 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4751
4752 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4753 &num_msdus);
4754
4755 for (i = 0; i < num_msdus; i++) {
4756 u32 l2_hdr_offset;
4757
4758 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4759 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4760 "i %d last_cookie %d is same\n",
4761 i, pmon->mon_last_buf_cookie);
4762 drop_mpdu = true;
4763 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4764 continue;
4765 }
4766 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4767 msdu_list.sw_cookie[i]);
4768
4769 spin_lock_bh(&rx_ring->idr_lock);
4770 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4771 spin_unlock_bh(&rx_ring->idr_lock);
4772 if (!msdu) {
4773 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4774 "msdu_pop: invalid buf_id %d\n", buf_id);
4775 goto next_msdu;
4776 }
4777 rxcb = ATH11K_SKB_RXCB(msdu);
4778 if (!rxcb->unmapped) {
4779 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4780 msdu->len +
4781 skb_tailroom(msdu),
4782 DMA_FROM_DEVICE);
4783 rxcb->unmapped = 1;
4784 }
4785 if (drop_mpdu) {
4786 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4787 "i %d drop msdu %p *ppdu_id %x\n",
4788 i, msdu, *ppdu_id);
4789 dev_kfree_skb_any(msdu);
4790 msdu = NULL;
4791 goto next_msdu;
4792 }
4793
4794 rx_desc = (struct hal_rx_desc *)msdu->data;
4795
4796 rx_pkt_offset = sizeof(struct hal_rx_desc);
4797 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4798
4799 if (is_first_msdu) {
4800 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4801 drop_mpdu = true;
4802 dev_kfree_skb_any(msdu);
4803 msdu = NULL;
4804 pmon->mon_last_linkdesc_paddr = paddr;
4805 goto next_msdu;
4806 }
4807
4808 msdu_ppdu_id =
4809 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4810
4811 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4812 ppdu_id,
4813 &rx_bufs_used)) {
4814 if (rx_bufs_used) {
4815 drop_mpdu = true;
4816 dev_kfree_skb_any(msdu);
4817 msdu = NULL;
4818 goto next_msdu;
4819 }
4820 return rx_bufs_used;
4821 }
4822 pmon->mon_last_linkdesc_paddr = paddr;
4823 is_first_msdu = false;
4824 }
4825 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4826 &is_frag, &total_len,
4827 &frag_len, &msdu_cnt);
4828 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4829
4830 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4831
4832 if (!(*head_msdu))
4833 *head_msdu = msdu;
4834 else if (last)
4835 last->next = msdu;
4836
4837 last = msdu;
4838 next_msdu:
4839 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4840 rx_bufs_used++;
4841 spin_lock_bh(&rx_ring->idr_lock);
4842 idr_remove(&rx_ring->bufs_idr, buf_id);
4843 spin_unlock_bh(&rx_ring->idr_lock);
4844 }
4845
4846 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4847
4848 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4849 &sw_cookie, &rbm,
4850 &p_buf_addr_info);
4851
4852 if (ar->ab->hw_params.rxdma1_enable) {
4853 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4854 p_last_buf_addr_info,
4855 dp->mac_id))
4856 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4857 "dp_rx_monitor_link_desc_return failed");
4858 } else {
4859 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4860 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4861 }
4862
4863 p_last_buf_addr_info = p_buf_addr_info;
4864
4865 } while (paddr && msdu_cnt);
4866
4867 if (last)
4868 last->next = NULL;
4869
4870 *tail_msdu = msdu;
4871
4872 if (msdu_cnt == 0)
4873 *npackets = 1;
4874
4875 return rx_bufs_used;
4876 }
4877
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4878 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4879 {
4880 u32 rx_pkt_offset, l2_hdr_offset;
4881
4882 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4883 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4884 (struct hal_rx_desc *)msdu->data);
4885 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4886 }
4887
4888 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4889 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4890 u32 mac_id, struct sk_buff *head_msdu,
4891 struct sk_buff *last_msdu,
4892 struct ieee80211_rx_status *rxs, bool *fcs_err)
4893 {
4894 struct ath11k_base *ab = ar->ab;
4895 struct sk_buff *msdu, *prev_buf;
4896 struct hal_rx_desc *rx_desc;
4897 char *hdr_desc;
4898 u8 *dest, decap_format;
4899 struct ieee80211_hdr_3addr *wh;
4900 struct rx_attention *rx_attention;
4901 u32 err_bitmap;
4902
4903 if (!head_msdu)
4904 goto err_merge_fail;
4905
4906 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4907 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4908 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4909
4910 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4911 *fcs_err = true;
4912
4913 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4914 return NULL;
4915
4916 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4917
4918 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4919
4920 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4921 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4922
4923 prev_buf = head_msdu;
4924 msdu = head_msdu->next;
4925
4926 while (msdu) {
4927 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4928
4929 prev_buf = msdu;
4930 msdu = msdu->next;
4931 }
4932
4933 prev_buf->next = NULL;
4934
4935 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4936 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4937 u8 qos_pkt = 0;
4938
4939 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4940 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4941
4942 /* Base size */
4943 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4944
4945 if (ieee80211_is_data_qos(wh->frame_control))
4946 qos_pkt = 1;
4947
4948 msdu = head_msdu;
4949
4950 while (msdu) {
4951 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4952 if (qos_pkt) {
4953 dest = skb_push(msdu, sizeof(__le16));
4954 if (!dest)
4955 goto err_merge_fail;
4956 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4957 }
4958 prev_buf = msdu;
4959 msdu = msdu->next;
4960 }
4961 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4962 if (!dest)
4963 goto err_merge_fail;
4964
4965 ath11k_dbg(ab, ATH11K_DBG_DATA,
4966 "mpdu_buf %p mpdu_buf->len %u",
4967 prev_buf, prev_buf->len);
4968 } else {
4969 ath11k_dbg(ab, ATH11K_DBG_DATA,
4970 "decap format %d is not supported!\n",
4971 decap_format);
4972 goto err_merge_fail;
4973 }
4974
4975 return head_msdu;
4976
4977 err_merge_fail:
4978 return NULL;
4979 }
4980
4981 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4982 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4983 u8 *rtap_buf)
4984 {
4985 u32 rtap_len = 0;
4986
4987 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4988 rtap_len += 2;
4989
4990 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
4991 rtap_len += 2;
4992
4993 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
4994 rtap_len += 2;
4995
4996 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
4997 rtap_len += 2;
4998
4999 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
5000 rtap_len += 2;
5001
5002 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
5003 }
5004
5005 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5006 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
5007 u8 *rtap_buf)
5008 {
5009 u32 rtap_len = 0;
5010
5011 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
5012 rtap_len += 2;
5013
5014 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
5015 rtap_len += 2;
5016
5017 rtap_buf[rtap_len] = rx_status->he_RU[0];
5018 rtap_len += 1;
5019
5020 rtap_buf[rtap_len] = rx_status->he_RU[1];
5021 rtap_len += 1;
5022
5023 rtap_buf[rtap_len] = rx_status->he_RU[2];
5024 rtap_len += 1;
5025
5026 rtap_buf[rtap_len] = rx_status->he_RU[3];
5027 }
5028
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)5029 static void ath11k_update_radiotap(struct ath11k *ar,
5030 struct hal_rx_mon_ppdu_info *ppduinfo,
5031 struct sk_buff *mon_skb,
5032 struct ieee80211_rx_status *rxs)
5033 {
5034 struct ieee80211_supported_band *sband;
5035 u8 *ptr = NULL;
5036
5037 rxs->flag |= RX_FLAG_MACTIME_START;
5038 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
5039
5040 if (ppduinfo->nss)
5041 rxs->nss = ppduinfo->nss;
5042
5043 if (ppduinfo->he_mu_flags) {
5044 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
5045 rxs->encoding = RX_ENC_HE;
5046 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5047 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5048 } else if (ppduinfo->he_flags) {
5049 rxs->flag |= RX_FLAG_RADIOTAP_HE;
5050 rxs->encoding = RX_ENC_HE;
5051 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5052 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5053 rxs->rate_idx = ppduinfo->rate;
5054 } else if (ppduinfo->vht_flags) {
5055 rxs->encoding = RX_ENC_VHT;
5056 rxs->rate_idx = ppduinfo->rate;
5057 } else if (ppduinfo->ht_flags) {
5058 rxs->encoding = RX_ENC_HT;
5059 rxs->rate_idx = ppduinfo->rate;
5060 } else {
5061 rxs->encoding = RX_ENC_LEGACY;
5062 sband = &ar->mac.sbands[rxs->band];
5063 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5064 ppduinfo->cck_flag);
5065 }
5066
5067 rxs->mactime = ppduinfo->tsft;
5068 }
5069
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5070 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5071 struct sk_buff *head_msdu,
5072 struct hal_rx_mon_ppdu_info *ppduinfo,
5073 struct sk_buff *tail_msdu,
5074 struct napi_struct *napi)
5075 {
5076 struct ath11k_pdev_dp *dp = &ar->dp;
5077 struct sk_buff *mon_skb, *skb_next, *header;
5078 struct ieee80211_rx_status *rxs = &dp->rx_status;
5079 bool fcs_err = false;
5080
5081 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5082 tail_msdu, rxs, &fcs_err);
5083
5084 if (!mon_skb)
5085 goto mon_deliver_fail;
5086
5087 header = mon_skb;
5088
5089 rxs->flag = 0;
5090
5091 if (fcs_err)
5092 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5093
5094 do {
5095 skb_next = mon_skb->next;
5096 if (!skb_next)
5097 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5098 else
5099 rxs->flag |= RX_FLAG_AMSDU_MORE;
5100
5101 if (mon_skb == header) {
5102 header = NULL;
5103 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5104 } else {
5105 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5106 }
5107 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5108 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5109
5110 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5111 mon_skb = skb_next;
5112 } while (mon_skb);
5113 rxs->flag = 0;
5114
5115 return 0;
5116
5117 mon_deliver_fail:
5118 mon_skb = head_msdu;
5119 while (mon_skb) {
5120 skb_next = mon_skb->next;
5121 dev_kfree_skb_any(mon_skb);
5122 mon_skb = skb_next;
5123 }
5124 return -EINVAL;
5125 }
5126
5127 /* The destination ring processing is stuck if the destination is not
5128 * moving while status ring moves 16 PPDU. The destination ring processing
5129 * skips this destination ring PPDU as a workaround.
5130 */
5131 #define MON_DEST_RING_STUCK_MAX_CNT 16
5132
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5133 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5134 u32 quota, struct napi_struct *napi)
5135 {
5136 struct ath11k_pdev_dp *dp = &ar->dp;
5137 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5138 const struct ath11k_hw_hal_params *hal_params;
5139 void *ring_entry;
5140 struct hal_srng *mon_dst_srng;
5141 u32 ppdu_id;
5142 u32 rx_bufs_used;
5143 u32 ring_id;
5144 struct ath11k_pdev_mon_stats *rx_mon_stats;
5145 u32 npackets = 0;
5146 u32 mpdu_rx_bufs_used;
5147
5148 if (ar->ab->hw_params.rxdma1_enable)
5149 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5150 else
5151 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5152
5153 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5154
5155 spin_lock_bh(&pmon->mon_lock);
5156
5157 spin_lock_bh(&mon_dst_srng->lock);
5158 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5159
5160 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5161 rx_bufs_used = 0;
5162 rx_mon_stats = &pmon->rx_mon_stats;
5163
5164 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5165 struct sk_buff *head_msdu, *tail_msdu;
5166
5167 head_msdu = NULL;
5168 tail_msdu = NULL;
5169
5170 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5171 &head_msdu,
5172 &tail_msdu,
5173 &npackets, &ppdu_id);
5174
5175 rx_bufs_used += mpdu_rx_bufs_used;
5176
5177 if (mpdu_rx_bufs_used) {
5178 dp->mon_dest_ring_stuck_cnt = 0;
5179 } else {
5180 dp->mon_dest_ring_stuck_cnt++;
5181 rx_mon_stats->dest_mon_not_reaped++;
5182 }
5183
5184 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5185 rx_mon_stats->dest_mon_stuck++;
5186 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5187 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5188 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5189 dp->mon_dest_ring_stuck_cnt,
5190 rx_mon_stats->dest_mon_not_reaped,
5191 rx_mon_stats->dest_mon_stuck);
5192 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5193 continue;
5194 }
5195
5196 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5197 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5198 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5199 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5200 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5201 rx_mon_stats->dest_mon_not_reaped,
5202 rx_mon_stats->dest_mon_stuck);
5203 break;
5204 }
5205 if (head_msdu && tail_msdu) {
5206 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5207 &pmon->mon_ppdu_info,
5208 tail_msdu, napi);
5209 rx_mon_stats->dest_mpdu_done++;
5210 }
5211
5212 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5213 mon_dst_srng);
5214 }
5215 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5216 spin_unlock_bh(&mon_dst_srng->lock);
5217
5218 spin_unlock_bh(&pmon->mon_lock);
5219
5220 if (rx_bufs_used) {
5221 rx_mon_stats->dest_ppdu_done++;
5222 hal_params = ar->ab->hw_params.hal_params;
5223
5224 if (ar->ab->hw_params.rxdma1_enable)
5225 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5226 &dp->rxdma_mon_buf_ring,
5227 rx_bufs_used,
5228 hal_params->rx_buf_rbm);
5229 else
5230 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5231 &dp->rx_refill_buf_ring,
5232 rx_bufs_used,
5233 hal_params->rx_buf_rbm);
5234 }
5235 }
5236
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5237 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5238 struct napi_struct *napi, int budget)
5239 {
5240 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5241 enum hal_rx_mon_status hal_status;
5242 struct sk_buff *skb;
5243 struct sk_buff_head skb_list;
5244 struct ath11k_peer *peer;
5245 struct ath11k_sta *arsta;
5246 int num_buffs_reaped = 0;
5247 u32 rx_buf_sz;
5248 u16 log_type;
5249 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5250 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5251 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5252
5253 __skb_queue_head_init(&skb_list);
5254
5255 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5256 &skb_list);
5257 if (!num_buffs_reaped)
5258 goto exit;
5259
5260 memset(ppdu_info, 0, sizeof(*ppdu_info));
5261 ppdu_info->peer_id = HAL_INVALID_PEERID;
5262
5263 while ((skb = __skb_dequeue(&skb_list))) {
5264 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5265 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5266 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5267 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5268 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5269 rx_buf_sz = DP_RX_BUFFER_SIZE;
5270 } else {
5271 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5272 rx_buf_sz = 0;
5273 }
5274
5275 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5276 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5277
5278 memset(ppdu_info, 0, sizeof(*ppdu_info));
5279 ppdu_info->peer_id = HAL_INVALID_PEERID;
5280 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5281
5282 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5283 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5284 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5285 rx_mon_stats->status_ppdu_done++;
5286 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5287 if (!ab->hw_params.full_monitor_mode) {
5288 ath11k_dp_rx_mon_dest_process(ar, mac_id,
5289 budget, napi);
5290 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5291 }
5292 }
5293
5294 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5295 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5296 dev_kfree_skb_any(skb);
5297 continue;
5298 }
5299
5300 rcu_read_lock();
5301 spin_lock_bh(&ab->base_lock);
5302 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5303
5304 if (!peer || !peer->sta) {
5305 ath11k_dbg(ab, ATH11K_DBG_DATA,
5306 "failed to find the peer with peer_id %d\n",
5307 ppdu_info->peer_id);
5308 goto next_skb;
5309 }
5310
5311 arsta = ath11k_sta_to_arsta(peer->sta);
5312 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5313
5314 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5315 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5316
5317 next_skb:
5318 spin_unlock_bh(&ab->base_lock);
5319 rcu_read_unlock();
5320
5321 dev_kfree_skb_any(skb);
5322 memset(ppdu_info, 0, sizeof(*ppdu_info));
5323 ppdu_info->peer_id = HAL_INVALID_PEERID;
5324 }
5325 exit:
5326 return num_buffs_reaped;
5327 }
5328
5329 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5330 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5331 void *ring_entry, struct sk_buff **head_msdu,
5332 struct sk_buff **tail_msdu,
5333 struct hal_sw_mon_ring_entries *sw_mon_entries)
5334 {
5335 struct ath11k_pdev_dp *dp = &ar->dp;
5336 struct ath11k_mon_data *pmon = &dp->mon_data;
5337 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5338 struct sk_buff *msdu = NULL, *last = NULL;
5339 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5340 struct hal_rx_msdu_list msdu_list;
5341 struct hal_rx_desc *rx_desc;
5342 struct ath11k_skb_rxcb *rxcb;
5343 void *rx_msdu_link_desc;
5344 void *p_buf_addr_info, *p_last_buf_addr_info;
5345 int buf_id, i = 0;
5346 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5347 u32 rx_bufs_used = 0, msdu_cnt = 0;
5348 u32 total_len = 0, frag_len = 0, sw_cookie;
5349 u16 num_msdus = 0;
5350 u8 rxdma_err, rbm;
5351 bool is_frag, is_first_msdu;
5352 bool drop_mpdu = false;
5353
5354 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5355
5356 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5357 sw_mon_entries->end_of_ppdu = false;
5358 sw_mon_entries->drop_ppdu = false;
5359 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5360 msdu_cnt = sw_mon_entries->msdu_cnt;
5361
5362 sw_mon_entries->end_of_ppdu =
5363 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5364 if (sw_mon_entries->end_of_ppdu)
5365 return rx_bufs_used;
5366
5367 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5368 sw_desc->info0) ==
5369 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5370 rxdma_err =
5371 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5372 sw_desc->info0);
5373 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5374 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5375 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5376 pmon->rx_mon_stats.dest_mpdu_drop++;
5377 drop_mpdu = true;
5378 }
5379 }
5380
5381 is_frag = false;
5382 is_first_msdu = true;
5383
5384 do {
5385 rx_msdu_link_desc =
5386 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5387 (sw_mon_entries->mon_dst_paddr -
5388 pmon->link_desc_banks[sw_cookie].paddr);
5389
5390 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5391 &num_msdus);
5392
5393 for (i = 0; i < num_msdus; i++) {
5394 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5395 msdu_list.sw_cookie[i]);
5396
5397 spin_lock_bh(&rx_ring->idr_lock);
5398 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5399 if (!msdu) {
5400 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5401 "full mon msdu_pop: invalid buf_id %d\n",
5402 buf_id);
5403 spin_unlock_bh(&rx_ring->idr_lock);
5404 goto next_msdu;
5405 }
5406 idr_remove(&rx_ring->bufs_idr, buf_id);
5407 spin_unlock_bh(&rx_ring->idr_lock);
5408
5409 rxcb = ATH11K_SKB_RXCB(msdu);
5410 if (!rxcb->unmapped) {
5411 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5412 msdu->len +
5413 skb_tailroom(msdu),
5414 DMA_FROM_DEVICE);
5415 rxcb->unmapped = 1;
5416 }
5417 if (drop_mpdu) {
5418 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5419 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5420 i, msdu, sw_mon_entries->ppdu_id);
5421 dev_kfree_skb_any(msdu);
5422 msdu_cnt--;
5423 goto next_msdu;
5424 }
5425
5426 rx_desc = (struct hal_rx_desc *)msdu->data;
5427
5428 rx_pkt_offset = sizeof(struct hal_rx_desc);
5429 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5430
5431 if (is_first_msdu) {
5432 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5433 drop_mpdu = true;
5434 dev_kfree_skb_any(msdu);
5435 msdu = NULL;
5436 goto next_msdu;
5437 }
5438 is_first_msdu = false;
5439 }
5440
5441 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5442 &is_frag, &total_len,
5443 &frag_len, &msdu_cnt);
5444
5445 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5446
5447 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5448
5449 if (!(*head_msdu))
5450 *head_msdu = msdu;
5451 else if (last)
5452 last->next = msdu;
5453
5454 last = msdu;
5455 next_msdu:
5456 rx_bufs_used++;
5457 }
5458
5459 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5460 &sw_mon_entries->mon_dst_paddr,
5461 &sw_mon_entries->mon_dst_sw_cookie,
5462 &rbm,
5463 &p_buf_addr_info);
5464
5465 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5466 p_last_buf_addr_info,
5467 dp->mac_id))
5468 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5469 "full mon: dp_rx_monitor_link_desc_return failed\n");
5470
5471 p_last_buf_addr_info = p_buf_addr_info;
5472
5473 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5474
5475 if (last)
5476 last->next = NULL;
5477
5478 *tail_msdu = msdu;
5479
5480 return rx_bufs_used;
5481 }
5482
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5483 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5484 struct dp_full_mon_mpdu *mon_mpdu,
5485 struct sk_buff *head,
5486 struct sk_buff *tail)
5487 {
5488 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5489 if (!mon_mpdu)
5490 return -ENOMEM;
5491
5492 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5493 mon_mpdu->head = head;
5494 mon_mpdu->tail = tail;
5495
5496 return 0;
5497 }
5498
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5499 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5500 struct dp_full_mon_mpdu *mon_mpdu)
5501 {
5502 struct dp_full_mon_mpdu *tmp;
5503 struct sk_buff *tmp_msdu, *skb_next;
5504
5505 if (list_empty(&dp->dp_full_mon_mpdu_list))
5506 return;
5507
5508 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5509 list_del(&mon_mpdu->list);
5510
5511 tmp_msdu = mon_mpdu->head;
5512 while (tmp_msdu) {
5513 skb_next = tmp_msdu->next;
5514 dev_kfree_skb_any(tmp_msdu);
5515 tmp_msdu = skb_next;
5516 }
5517
5518 kfree(mon_mpdu);
5519 }
5520 }
5521
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5522 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5523 int mac_id,
5524 struct ath11k_mon_data *pmon,
5525 struct napi_struct *napi)
5526 {
5527 struct ath11k_pdev_mon_stats *rx_mon_stats;
5528 struct dp_full_mon_mpdu *tmp;
5529 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5530 struct sk_buff *head_msdu, *tail_msdu;
5531 struct ath11k_base *ab = ar->ab;
5532 struct ath11k_dp *dp = &ab->dp;
5533 int ret;
5534
5535 rx_mon_stats = &pmon->rx_mon_stats;
5536
5537 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5538 list_del(&mon_mpdu->list);
5539 head_msdu = mon_mpdu->head;
5540 tail_msdu = mon_mpdu->tail;
5541 if (head_msdu && tail_msdu) {
5542 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5543 &pmon->mon_ppdu_info,
5544 tail_msdu, napi);
5545 rx_mon_stats->dest_mpdu_done++;
5546 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5547 }
5548 kfree(mon_mpdu);
5549 }
5550
5551 return ret;
5552 }
5553
5554 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5555 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5556 struct napi_struct *napi, int budget)
5557 {
5558 struct ath11k *ar = ab->pdevs[mac_id].ar;
5559 struct ath11k_pdev_dp *dp = &ar->dp;
5560 struct ath11k_mon_data *pmon = &dp->mon_data;
5561 struct hal_sw_mon_ring_entries *sw_mon_entries;
5562 int quota = 0, work = 0, count;
5563
5564 sw_mon_entries = &pmon->sw_mon_entries;
5565
5566 while (pmon->hold_mon_dst_ring) {
5567 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5568 napi, 1);
5569 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5570 count = sw_mon_entries->status_buf_count;
5571 if (count > 1) {
5572 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5573 napi, count);
5574 }
5575
5576 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5577 pmon, napi);
5578 pmon->hold_mon_dst_ring = false;
5579 } else if (!pmon->mon_status_paddr ||
5580 pmon->buf_state == DP_MON_STATUS_LEAD) {
5581 sw_mon_entries->drop_ppdu = true;
5582 pmon->hold_mon_dst_ring = false;
5583 }
5584
5585 if (!quota)
5586 break;
5587
5588 work += quota;
5589 }
5590
5591 if (sw_mon_entries->drop_ppdu)
5592 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5593
5594 return work;
5595 }
5596
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5597 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5598 struct napi_struct *napi, int budget)
5599 {
5600 struct ath11k *ar = ab->pdevs[mac_id].ar;
5601 struct ath11k_pdev_dp *dp = &ar->dp;
5602 struct ath11k_mon_data *pmon = &dp->mon_data;
5603 struct hal_sw_mon_ring_entries *sw_mon_entries;
5604 struct ath11k_pdev_mon_stats *rx_mon_stats;
5605 struct sk_buff *head_msdu, *tail_msdu;
5606 struct hal_srng *mon_dst_srng;
5607 void *ring_entry;
5608 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5609 int quota = 0, ret;
5610 bool break_dst_ring = false;
5611
5612 spin_lock_bh(&pmon->mon_lock);
5613
5614 sw_mon_entries = &pmon->sw_mon_entries;
5615 rx_mon_stats = &pmon->rx_mon_stats;
5616
5617 if (pmon->hold_mon_dst_ring) {
5618 spin_unlock_bh(&pmon->mon_lock);
5619 goto reap_status_ring;
5620 }
5621
5622 mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5623 spin_lock_bh(&mon_dst_srng->lock);
5624
5625 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5626 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5627 head_msdu = NULL;
5628 tail_msdu = NULL;
5629
5630 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5631 &head_msdu,
5632 &tail_msdu,
5633 sw_mon_entries);
5634 rx_bufs_used += mpdu_rx_bufs_used;
5635
5636 if (!sw_mon_entries->end_of_ppdu) {
5637 if (head_msdu) {
5638 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5639 pmon->mon_mpdu,
5640 head_msdu,
5641 tail_msdu);
5642 if (ret)
5643 break_dst_ring = true;
5644 }
5645
5646 goto next_entry;
5647 } else {
5648 if (!sw_mon_entries->ppdu_id &&
5649 !sw_mon_entries->mon_status_paddr) {
5650 break_dst_ring = true;
5651 goto next_entry;
5652 }
5653 }
5654
5655 rx_mon_stats->dest_ppdu_done++;
5656 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5657 pmon->buf_state = DP_MON_STATUS_LAG;
5658 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5659 pmon->hold_mon_dst_ring = true;
5660 next_entry:
5661 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5662 mon_dst_srng);
5663 if (break_dst_ring)
5664 break;
5665 }
5666
5667 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5668 spin_unlock_bh(&mon_dst_srng->lock);
5669 spin_unlock_bh(&pmon->mon_lock);
5670
5671 if (rx_bufs_used) {
5672 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5673 &dp->rxdma_mon_buf_ring,
5674 rx_bufs_used,
5675 HAL_RX_BUF_RBM_SW3_BM);
5676 }
5677
5678 reap_status_ring:
5679 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5680 napi, budget);
5681
5682 return quota;
5683 }
5684
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5685 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5686 struct napi_struct *napi, int budget)
5687 {
5688 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5689 int ret = 0;
5690
5691 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5692 ab->hw_params.full_monitor_mode)
5693 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5694 else
5695 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5696
5697 return ret;
5698 }
5699
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5700 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5701 {
5702 struct ath11k_pdev_dp *dp = &ar->dp;
5703 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5704
5705 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5706
5707 memset(&pmon->rx_mon_stats, 0,
5708 sizeof(pmon->rx_mon_stats));
5709 return 0;
5710 }
5711
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5712 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5713 {
5714 struct ath11k_pdev_dp *dp = &ar->dp;
5715 struct ath11k_mon_data *pmon = &dp->mon_data;
5716 struct hal_srng *mon_desc_srng = NULL;
5717 struct dp_srng *dp_srng;
5718 int ret = 0;
5719 u32 n_link_desc = 0;
5720
5721 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5722 if (ret) {
5723 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5724 return ret;
5725 }
5726
5727 /* if rxdma1_enable is false, no need to setup
5728 * rxdma_mon_desc_ring.
5729 */
5730 if (!ar->ab->hw_params.rxdma1_enable)
5731 return 0;
5732
5733 dp_srng = &dp->rxdma_mon_desc_ring;
5734 n_link_desc = dp_srng->size /
5735 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5736 mon_desc_srng =
5737 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5738
5739 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5740 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5741 n_link_desc);
5742 if (ret) {
5743 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5744 return ret;
5745 }
5746 pmon->mon_last_linkdesc_paddr = 0;
5747 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5748 spin_lock_init(&pmon->mon_lock);
5749
5750 return 0;
5751 }
5752
ath11k_dp_mon_link_free(struct ath11k * ar)5753 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5754 {
5755 struct ath11k_pdev_dp *dp = &ar->dp;
5756 struct ath11k_mon_data *pmon = &dp->mon_data;
5757
5758 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5759 HAL_RXDMA_MONITOR_DESC,
5760 &dp->rxdma_mon_desc_ring);
5761 return 0;
5762 }
5763
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5764 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5765 {
5766 ath11k_dp_mon_link_free(ar);
5767 return 0;
5768 }
5769
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5770 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5771 {
5772 /* start reap timer */
5773 mod_timer(&ab->mon_reap_timer,
5774 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5775
5776 return 0;
5777 }
5778
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5779 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5780 {
5781 int ret;
5782
5783 if (stop_timer)
5784 del_timer_sync(&ab->mon_reap_timer);
5785
5786 /* reap all the monitor related rings */
5787 ret = ath11k_dp_purge_mon_ring(ab);
5788 if (ret) {
5789 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5790 return ret;
5791 }
5792
5793 return 0;
5794 }
5795