1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 // 7 // Author: Nicolin Chen <nicoleotsuka@gmail.com> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <linux/dma/imx-dma.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 19 #include "fsl_asrc.h" 20 21 #define IDEAL_RATIO_DECIMAL_DEPTH 26 22 #define DIVIDER_NUM 64 23 #define INIT_RETRY_NUM 50 24 25 #define pair_err(fmt, ...) \ 26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 27 28 #define pair_dbg(fmt, ...) \ 29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 30 31 #define pair_warn(fmt, ...) \ 32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 33 34 /* Corresponding to process_option */ 35 static unsigned int supported_asrc_rate[] = { 36 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 37 64000, 88200, 96000, 128000, 176400, 192000, 38 }; 39 40 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { 41 .count = ARRAY_SIZE(supported_asrc_rate), 42 .list = supported_asrc_rate, 43 }; 44 45 /* 46 * The following tables map the relationship between asrc_inclk/asrc_outclk in 47 * fsl_asrc.h and the registers of ASRCSR 48 */ 49 static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 50 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 51 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 52 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 53 }; 54 55 static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 56 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 57 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 58 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 59 }; 60 61 /* i.MX53 uses the same map for input and output */ 62 static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 63 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 64 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 65 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 66 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 67 }; 68 69 static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 70 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 71 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 72 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 73 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 74 }; 75 76 /* 77 * i.MX8QM/i.MX8QXP uses the same map for input and output. 78 * clk_map_imx8qm[0] is for i.MX8QM asrc0 79 * clk_map_imx8qm[1] is for i.MX8QM asrc1 80 * clk_map_imx8qxp[0] is for i.MX8QXP asrc0 81 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1 82 */ 83 static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = { 84 { 85 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 86 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 87 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 88 }, 89 { 90 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 91 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 92 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 93 }, 94 }; 95 96 static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = { 97 { 98 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 99 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf, 100 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 101 }, 102 { 103 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 104 0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 105 0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 106 }, 107 }; 108 109 /* 110 * According to RM, the divider range is 1 ~ 8, 111 * prescaler is power of 2 from 1 ~ 128. 112 */ 113 static int asrc_clk_divider[DIVIDER_NUM] = { 114 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */ 115 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */ 116 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */ 117 4, 8, 16, 32, 64, 128, 256, 512, /* divider = 4 */ 118 5, 10, 20, 40, 80, 160, 320, 640, /* divider = 5 */ 119 6, 12, 24, 48, 96, 192, 384, 768, /* divider = 6 */ 120 7, 14, 28, 56, 112, 224, 448, 896, /* divider = 7 */ 121 8, 16, 32, 64, 128, 256, 512, 1024, /* divider = 8 */ 122 }; 123 124 /* 125 * Check if the divider is available for internal ratio mode 126 */ 127 static bool fsl_asrc_divider_avail(int clk_rate, int rate, int *div) 128 { 129 u32 rem, i; 130 u64 n; 131 132 if (div) 133 *div = 0; 134 135 if (clk_rate == 0 || rate == 0) 136 return false; 137 138 n = clk_rate; 139 rem = do_div(n, rate); 140 141 if (div) 142 *div = n; 143 144 if (rem != 0) 145 return false; 146 147 for (i = 0; i < DIVIDER_NUM; i++) { 148 if (n == asrc_clk_divider[i]) 149 break; 150 } 151 152 if (i == DIVIDER_NUM) 153 return false; 154 155 return true; 156 } 157 158 /** 159 * fsl_asrc_sel_proc - Select the pre-processing and post-processing options 160 * @inrate: input sample rate 161 * @outrate: output sample rate 162 * @pre_proc: return value for pre-processing option 163 * @post_proc: return value for post-processing option 164 * 165 * Make sure to exclude following unsupported cases before 166 * calling this function: 167 * 1) inrate > 8.125 * outrate 168 * 2) inrate > 16.125 * outrate 169 * 170 */ 171 static void fsl_asrc_sel_proc(int inrate, int outrate, 172 int *pre_proc, int *post_proc) 173 { 174 bool post_proc_cond2; 175 bool post_proc_cond0; 176 177 /* select pre_proc between [0, 2] */ 178 if (inrate * 8 > 33 * outrate) 179 *pre_proc = 2; 180 else if (inrate * 8 > 15 * outrate) { 181 if (inrate > 152000) 182 *pre_proc = 2; 183 else 184 *pre_proc = 1; 185 } else if (inrate < 76000) 186 *pre_proc = 0; 187 else if (inrate > 152000) 188 *pre_proc = 2; 189 else 190 *pre_proc = 1; 191 192 /* Condition for selection of post-processing */ 193 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) || 194 (inrate > 56000 && outrate < 56000); 195 post_proc_cond0 = inrate * 23 < outrate * 8; 196 197 if (post_proc_cond2) 198 *post_proc = 2; 199 else if (post_proc_cond0) 200 *post_proc = 0; 201 else 202 *post_proc = 1; 203 } 204 205 /** 206 * fsl_asrc_request_pair - Request ASRC pair 207 * @channels: number of channels 208 * @pair: pointer to pair 209 * 210 * It assigns pair by the order of A->C->B because allocation of pair B, 211 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 212 * while pair A and pair C are comparatively independent. 213 */ 214 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 215 { 216 enum asrc_pair_index index = ASRC_INVALID_PAIR; 217 struct fsl_asrc *asrc = pair->asrc; 218 struct device *dev = &asrc->pdev->dev; 219 unsigned long lock_flags; 220 int i, ret = 0; 221 222 spin_lock_irqsave(&asrc->lock, lock_flags); 223 224 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 225 if (asrc->pair[i] != NULL) 226 continue; 227 228 index = i; 229 230 if (i != ASRC_PAIR_B) 231 break; 232 } 233 234 if (index == ASRC_INVALID_PAIR) { 235 dev_err(dev, "all pairs are busy now\n"); 236 ret = -EBUSY; 237 } else if (asrc->channel_avail < channels) { 238 dev_err(dev, "can't afford required channels: %d\n", channels); 239 ret = -EINVAL; 240 } else { 241 asrc->channel_avail -= channels; 242 asrc->pair[index] = pair; 243 pair->channels = channels; 244 pair->index = index; 245 } 246 247 spin_unlock_irqrestore(&asrc->lock, lock_flags); 248 249 return ret; 250 } 251 252 /** 253 * fsl_asrc_release_pair - Release ASRC pair 254 * @pair: pair to release 255 * 256 * It clears the resource from asrc and releases the occupied channels. 257 */ 258 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 259 { 260 struct fsl_asrc *asrc = pair->asrc; 261 enum asrc_pair_index index = pair->index; 262 unsigned long lock_flags; 263 264 /* Make sure the pair is disabled */ 265 regmap_update_bits(asrc->regmap, REG_ASRCTR, 266 ASRCTR_ASRCEi_MASK(index), 0); 267 268 spin_lock_irqsave(&asrc->lock, lock_flags); 269 270 asrc->channel_avail += pair->channels; 271 asrc->pair[index] = NULL; 272 pair->error = 0; 273 274 spin_unlock_irqrestore(&asrc->lock, lock_flags); 275 } 276 277 /** 278 * fsl_asrc_set_watermarks- configure input and output thresholds 279 * @pair: pointer to pair 280 * @in: input threshold 281 * @out: output threshold 282 */ 283 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 284 { 285 struct fsl_asrc *asrc = pair->asrc; 286 enum asrc_pair_index index = pair->index; 287 288 regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 289 ASRMCRi_EXTTHRSHi_MASK | 290 ASRMCRi_INFIFO_THRESHOLD_MASK | 291 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 292 ASRMCRi_EXTTHRSHi | 293 ASRMCRi_INFIFO_THRESHOLD(in) | 294 ASRMCRi_OUTFIFO_THRESHOLD(out)); 295 } 296 297 /** 298 * fsl_asrc_cal_asrck_divisor - Calculate the total divisor between asrck clock rate and sample rate 299 * @pair: pointer to pair 300 * @div: divider 301 * 302 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 303 */ 304 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 305 { 306 u32 ps; 307 308 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 309 for (ps = 0; div > 8; ps++) 310 div >>= 1; 311 312 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 313 } 314 315 /** 316 * fsl_asrc_set_ideal_ratio - Calculate and set the ratio for Ideal Ratio mode only 317 * @pair: pointer to pair 318 * @inrate: input rate 319 * @outrate: output rate 320 * 321 * The ratio is a 32-bit fixed point value with 26 fractional bits. 322 */ 323 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 324 int inrate, int outrate) 325 { 326 struct fsl_asrc *asrc = pair->asrc; 327 enum asrc_pair_index index = pair->index; 328 unsigned long ratio; 329 int i; 330 331 if (!outrate) { 332 pair_err("output rate should not be zero\n"); 333 return -EINVAL; 334 } 335 336 /* Calculate the intergal part of the ratio */ 337 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 338 339 /* ... and then the 26 depth decimal part */ 340 inrate %= outrate; 341 342 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 343 inrate <<= 1; 344 345 if (inrate < outrate) 346 continue; 347 348 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 349 inrate -= outrate; 350 351 if (!inrate) 352 break; 353 } 354 355 regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio); 356 regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24); 357 358 return 0; 359 } 360 361 /** 362 * fsl_asrc_config_pair - Configure the assigned ASRC pair 363 * @pair: pointer to pair 364 * @use_ideal_rate: boolean configuration 365 * 366 * It configures those ASRC registers according to a configuration instance 367 * of struct asrc_config which includes in/output sample rate, width, channel 368 * and clock settings. 369 * 370 * Note: 371 * The ideal ratio configuration can work with a flexible clock rate setting. 372 * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC. 373 * For a regular audio playback, the clock rate should not be slower than an 374 * clock rate aligning with the output sample rate; For a use case requiring 375 * faster conversion, set use_ideal_rate to have the faster speed. 376 */ 377 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate) 378 { 379 struct fsl_asrc_pair_priv *pair_priv = pair->private; 380 struct asrc_config *config = pair_priv->config; 381 struct fsl_asrc *asrc = pair->asrc; 382 struct fsl_asrc_priv *asrc_priv = asrc->private; 383 enum asrc_pair_index index = pair->index; 384 enum asrc_word_width input_word_width; 385 enum asrc_word_width output_word_width; 386 u32 inrate, outrate, indiv, outdiv; 387 u32 clk_index[2], div[2]; 388 u64 clk_rate; 389 int in, out, channels; 390 int pre_proc, post_proc; 391 struct clk *clk; 392 bool ideal, div_avail; 393 394 if (!config) { 395 pair_err("invalid pair config\n"); 396 return -EINVAL; 397 } 398 399 /* Validate channels */ 400 if (config->channel_num < 1 || config->channel_num > 10) { 401 pair_err("does not support %d channels\n", config->channel_num); 402 return -EINVAL; 403 } 404 405 switch (snd_pcm_format_width(config->input_format)) { 406 case 8: 407 input_word_width = ASRC_WIDTH_8_BIT; 408 break; 409 case 16: 410 input_word_width = ASRC_WIDTH_16_BIT; 411 break; 412 case 24: 413 input_word_width = ASRC_WIDTH_24_BIT; 414 break; 415 default: 416 pair_err("does not support this input format, %d\n", 417 config->input_format); 418 return -EINVAL; 419 } 420 421 switch (snd_pcm_format_width(config->output_format)) { 422 case 16: 423 output_word_width = ASRC_WIDTH_16_BIT; 424 break; 425 case 24: 426 output_word_width = ASRC_WIDTH_24_BIT; 427 break; 428 default: 429 pair_err("does not support this output format, %d\n", 430 config->output_format); 431 return -EINVAL; 432 } 433 434 inrate = config->input_sample_rate; 435 outrate = config->output_sample_rate; 436 ideal = config->inclk == INCLK_NONE; 437 438 /* Validate input and output sample rates */ 439 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++) 440 if (inrate == supported_asrc_rate[in]) 441 break; 442 443 if (in == ARRAY_SIZE(supported_asrc_rate)) { 444 pair_err("unsupported input sample rate: %dHz\n", inrate); 445 return -EINVAL; 446 } 447 448 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 449 if (outrate == supported_asrc_rate[out]) 450 break; 451 452 if (out == ARRAY_SIZE(supported_asrc_rate)) { 453 pair_err("unsupported output sample rate: %dHz\n", outrate); 454 return -EINVAL; 455 } 456 457 if ((outrate >= 5512 && outrate <= 30000) && 458 (outrate > 24 * inrate || inrate > 8 * outrate)) { 459 pair_err("exceed supported ratio range [1/24, 8] for \ 460 inrate/outrate: %d/%d\n", inrate, outrate); 461 return -EINVAL; 462 } 463 464 /* Validate input and output clock sources */ 465 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk]; 466 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk]; 467 468 /* We only have output clock for ideal ratio mode */ 469 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 470 471 clk_rate = clk_get_rate(clk); 472 div_avail = fsl_asrc_divider_avail(clk_rate, inrate, &div[IN]); 473 474 /* 475 * The divider range is [1, 1024], defined by the hardware. For non- 476 * ideal ratio configuration, clock rate has to be strictly aligned 477 * with the sample rate. For ideal ratio configuration, clock rates 478 * only result in different converting speeds. So remainder does not 479 * matter, as long as we keep the divider within its valid range. 480 */ 481 if (div[IN] == 0 || (!ideal && !div_avail)) { 482 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 483 inrate, clk_index[ideal ? OUT : IN]); 484 return -EINVAL; 485 } 486 487 div[IN] = min_t(u32, 1024, div[IN]); 488 489 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 490 clk_rate = clk_get_rate(clk); 491 if (ideal && use_ideal_rate) 492 div_avail = fsl_asrc_divider_avail(clk_rate, IDEAL_RATIO_RATE, &div[OUT]); 493 else 494 div_avail = fsl_asrc_divider_avail(clk_rate, outrate, &div[OUT]); 495 496 /* Output divider has the same limitation as the input one */ 497 if (div[OUT] == 0 || (!ideal && !div_avail)) { 498 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 499 outrate, clk_index[OUT]); 500 return -EINVAL; 501 } 502 503 div[OUT] = min_t(u32, 1024, div[OUT]); 504 505 /* Set the channel number */ 506 channels = config->channel_num; 507 508 if (asrc_priv->soc->channel_bits < 4) 509 channels /= 2; 510 511 /* Update channels for current pair */ 512 regmap_update_bits(asrc->regmap, REG_ASRCNCR, 513 ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits), 514 ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits)); 515 516 /* Default setting: Automatic selection for processing mode */ 517 regmap_update_bits(asrc->regmap, REG_ASRCTR, 518 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 519 regmap_update_bits(asrc->regmap, REG_ASRCTR, 520 ASRCTR_USRi_MASK(index), 0); 521 522 /* Set the input and output clock sources */ 523 regmap_update_bits(asrc->regmap, REG_ASRCSR, 524 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 525 ASRCSR_AICS(index, clk_index[IN]) | 526 ASRCSR_AOCS(index, clk_index[OUT])); 527 528 /* Calculate the input clock divisors */ 529 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 530 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 531 532 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 533 regmap_update_bits(asrc->regmap, REG_ASRCDR(index), 534 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 535 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 536 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 537 538 /* Implement word_width configurations */ 539 regmap_update_bits(asrc->regmap, REG_ASRMCR1(index), 540 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 541 ASRMCR1i_OW16(output_word_width) | 542 ASRMCR1i_IWD(input_word_width)); 543 544 /* Enable BUFFER STALL */ 545 regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 546 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 547 548 /* Set default thresholds for input and output FIFO */ 549 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 550 ASRC_INPUTFIFO_THRESHOLD); 551 552 /* Configure the following only for Ideal Ratio mode */ 553 if (!ideal) 554 return 0; 555 556 /* Clear ASTSx bit to use Ideal Ratio mode */ 557 regmap_update_bits(asrc->regmap, REG_ASRCTR, 558 ASRCTR_ATSi_MASK(index), 0); 559 560 /* Enable Ideal Ratio mode */ 561 regmap_update_bits(asrc->regmap, REG_ASRCTR, 562 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 563 ASRCTR_IDR(index) | ASRCTR_USR(index)); 564 565 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc); 566 567 /* Apply configurations for pre- and post-processing */ 568 regmap_update_bits(asrc->regmap, REG_ASRCFG, 569 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 570 ASRCFG_PREMOD(index, pre_proc) | 571 ASRCFG_POSTMOD(index, post_proc)); 572 573 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 574 } 575 576 /** 577 * fsl_asrc_start_pair - Start the assigned ASRC pair 578 * @pair: pointer to pair 579 * 580 * It enables the assigned pair and makes it stopped at the stall level. 581 */ 582 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 583 { 584 struct fsl_asrc *asrc = pair->asrc; 585 enum asrc_pair_index index = pair->index; 586 int reg, retry = INIT_RETRY_NUM, i; 587 588 /* Enable the current pair */ 589 regmap_update_bits(asrc->regmap, REG_ASRCTR, 590 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 591 592 /* Wait for status of initialization */ 593 do { 594 udelay(5); 595 regmap_read(asrc->regmap, REG_ASRCFG, ®); 596 reg &= ASRCFG_INIRQi_MASK(index); 597 } while (!reg && --retry); 598 599 /* NOTE: Doesn't treat initialization timeout as an error */ 600 if (!retry) 601 pair_warn("initialization isn't finished\n"); 602 603 /* Make the input fifo to ASRC STALL level */ 604 regmap_read(asrc->regmap, REG_ASRCNCR, ®); 605 for (i = 0; i < pair->channels * 4; i++) 606 regmap_write(asrc->regmap, REG_ASRDI(index), 0); 607 608 /* Enable overload interrupt */ 609 regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE); 610 } 611 612 /** 613 * fsl_asrc_stop_pair - Stop the assigned ASRC pair 614 * @pair: pointer to pair 615 */ 616 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 617 { 618 struct fsl_asrc *asrc = pair->asrc; 619 enum asrc_pair_index index = pair->index; 620 621 /* Stop the current pair */ 622 regmap_update_bits(asrc->regmap, REG_ASRCTR, 623 ASRCTR_ASRCEi_MASK(index), 0); 624 } 625 626 /** 627 * fsl_asrc_get_dma_channel- Get DMA channel according to the pair and direction. 628 * @pair: pointer to pair 629 * @dir: DMA direction 630 */ 631 static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, 632 bool dir) 633 { 634 struct fsl_asrc *asrc = pair->asrc; 635 enum asrc_pair_index index = pair->index; 636 char name[4]; 637 638 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 639 640 return dma_request_slave_channel(&asrc->pdev->dev, name); 641 } 642 643 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, 644 struct snd_soc_dai *dai) 645 { 646 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 647 struct fsl_asrc_priv *asrc_priv = asrc->private; 648 649 /* Odd channel number is not valid for older ASRC (channel_bits==3) */ 650 if (asrc_priv->soc->channel_bits == 3) 651 snd_pcm_hw_constraint_step(substream->runtime, 0, 652 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 653 654 655 return snd_pcm_hw_constraint_list(substream->runtime, 0, 656 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints); 657 } 658 659 /* Select proper clock source for internal ratio mode */ 660 static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv, 661 struct fsl_asrc_pair *pair, 662 int in_rate, 663 int out_rate) 664 { 665 struct fsl_asrc_pair_priv *pair_priv = pair->private; 666 struct asrc_config *config = pair_priv->config; 667 int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */ 668 int clk_rate, clk_index; 669 int i, j; 670 671 rate[IN] = in_rate; 672 rate[OUT] = out_rate; 673 674 /* Select proper clock source for internal ratio mode */ 675 for (j = 0; j < 2; j++) { 676 for (i = 0; i < ASRC_CLK_MAP_LEN; i++) { 677 clk_index = asrc_priv->clk_map[j][i]; 678 clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]); 679 /* Only match a perfect clock source with no remainder */ 680 if (fsl_asrc_divider_avail(clk_rate, rate[j], NULL)) 681 break; 682 } 683 684 select_clk[j] = i; 685 } 686 687 /* Switch to ideal ratio mode if there is no proper clock source */ 688 if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) { 689 select_clk[IN] = INCLK_NONE; 690 select_clk[OUT] = OUTCLK_ASRCK1_CLK; 691 } 692 693 config->inclk = select_clk[IN]; 694 config->outclk = select_clk[OUT]; 695 } 696 697 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 698 struct snd_pcm_hw_params *params, 699 struct snd_soc_dai *dai) 700 { 701 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 702 struct fsl_asrc_priv *asrc_priv = asrc->private; 703 struct snd_pcm_runtime *runtime = substream->runtime; 704 struct fsl_asrc_pair *pair = runtime->private_data; 705 struct fsl_asrc_pair_priv *pair_priv = pair->private; 706 unsigned int channels = params_channels(params); 707 unsigned int rate = params_rate(params); 708 struct asrc_config config; 709 int ret; 710 711 ret = fsl_asrc_request_pair(channels, pair); 712 if (ret) { 713 dev_err(dai->dev, "fail to request asrc pair\n"); 714 return ret; 715 } 716 717 pair_priv->config = &config; 718 719 config.pair = pair->index; 720 config.channel_num = channels; 721 722 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 723 config.input_format = params_format(params); 724 config.output_format = asrc->asrc_format; 725 config.input_sample_rate = rate; 726 config.output_sample_rate = asrc->asrc_rate; 727 } else { 728 config.input_format = asrc->asrc_format; 729 config.output_format = params_format(params); 730 config.input_sample_rate = asrc->asrc_rate; 731 config.output_sample_rate = rate; 732 } 733 734 fsl_asrc_select_clk(asrc_priv, pair, 735 config.input_sample_rate, 736 config.output_sample_rate); 737 738 ret = fsl_asrc_config_pair(pair, false); 739 if (ret) { 740 dev_err(dai->dev, "fail to config asrc pair\n"); 741 return ret; 742 } 743 744 return 0; 745 } 746 747 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 748 struct snd_soc_dai *dai) 749 { 750 struct snd_pcm_runtime *runtime = substream->runtime; 751 struct fsl_asrc_pair *pair = runtime->private_data; 752 753 if (pair) 754 fsl_asrc_release_pair(pair); 755 756 return 0; 757 } 758 759 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 760 struct snd_soc_dai *dai) 761 { 762 struct snd_pcm_runtime *runtime = substream->runtime; 763 struct fsl_asrc_pair *pair = runtime->private_data; 764 765 switch (cmd) { 766 case SNDRV_PCM_TRIGGER_START: 767 case SNDRV_PCM_TRIGGER_RESUME: 768 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 769 fsl_asrc_start_pair(pair); 770 break; 771 case SNDRV_PCM_TRIGGER_STOP: 772 case SNDRV_PCM_TRIGGER_SUSPEND: 773 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 774 fsl_asrc_stop_pair(pair); 775 break; 776 default: 777 return -EINVAL; 778 } 779 780 return 0; 781 } 782 783 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 784 { 785 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 786 787 snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx, 788 &asrc->dma_params_rx); 789 790 return 0; 791 } 792 793 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = { 794 .probe = fsl_asrc_dai_probe, 795 .startup = fsl_asrc_dai_startup, 796 .hw_params = fsl_asrc_dai_hw_params, 797 .hw_free = fsl_asrc_dai_hw_free, 798 .trigger = fsl_asrc_dai_trigger, 799 }; 800 801 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 802 SNDRV_PCM_FMTBIT_S16_LE | \ 803 SNDRV_PCM_FMTBIT_S24_3LE) 804 805 static struct snd_soc_dai_driver fsl_asrc_dai = { 806 .playback = { 807 .stream_name = "ASRC-Playback", 808 .channels_min = 1, 809 .channels_max = 10, 810 .rate_min = 5512, 811 .rate_max = 192000, 812 .rates = SNDRV_PCM_RATE_KNOT, 813 .formats = FSL_ASRC_FORMATS | 814 SNDRV_PCM_FMTBIT_S8, 815 }, 816 .capture = { 817 .stream_name = "ASRC-Capture", 818 .channels_min = 1, 819 .channels_max = 10, 820 .rate_min = 5512, 821 .rate_max = 192000, 822 .rates = SNDRV_PCM_RATE_KNOT, 823 .formats = FSL_ASRC_FORMATS, 824 }, 825 .ops = &fsl_asrc_dai_ops, 826 }; 827 828 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 829 { 830 switch (reg) { 831 case REG_ASRCTR: 832 case REG_ASRIER: 833 case REG_ASRCNCR: 834 case REG_ASRCFG: 835 case REG_ASRCSR: 836 case REG_ASRCDR1: 837 case REG_ASRCDR2: 838 case REG_ASRSTR: 839 case REG_ASRPM1: 840 case REG_ASRPM2: 841 case REG_ASRPM3: 842 case REG_ASRPM4: 843 case REG_ASRPM5: 844 case REG_ASRTFR1: 845 case REG_ASRCCR: 846 case REG_ASRDOA: 847 case REG_ASRDOB: 848 case REG_ASRDOC: 849 case REG_ASRIDRHA: 850 case REG_ASRIDRLA: 851 case REG_ASRIDRHB: 852 case REG_ASRIDRLB: 853 case REG_ASRIDRHC: 854 case REG_ASRIDRLC: 855 case REG_ASR76K: 856 case REG_ASR56K: 857 case REG_ASRMCRA: 858 case REG_ASRFSTA: 859 case REG_ASRMCRB: 860 case REG_ASRFSTB: 861 case REG_ASRMCRC: 862 case REG_ASRFSTC: 863 case REG_ASRMCR1A: 864 case REG_ASRMCR1B: 865 case REG_ASRMCR1C: 866 return true; 867 default: 868 return false; 869 } 870 } 871 872 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 873 { 874 switch (reg) { 875 case REG_ASRSTR: 876 case REG_ASRDIA: 877 case REG_ASRDIB: 878 case REG_ASRDIC: 879 case REG_ASRDOA: 880 case REG_ASRDOB: 881 case REG_ASRDOC: 882 case REG_ASRFSTA: 883 case REG_ASRFSTB: 884 case REG_ASRFSTC: 885 case REG_ASRCFG: 886 return true; 887 default: 888 return false; 889 } 890 } 891 892 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 893 { 894 switch (reg) { 895 case REG_ASRCTR: 896 case REG_ASRIER: 897 case REG_ASRCNCR: 898 case REG_ASRCFG: 899 case REG_ASRCSR: 900 case REG_ASRCDR1: 901 case REG_ASRCDR2: 902 case REG_ASRSTR: 903 case REG_ASRPM1: 904 case REG_ASRPM2: 905 case REG_ASRPM3: 906 case REG_ASRPM4: 907 case REG_ASRPM5: 908 case REG_ASRTFR1: 909 case REG_ASRCCR: 910 case REG_ASRDIA: 911 case REG_ASRDIB: 912 case REG_ASRDIC: 913 case REG_ASRIDRHA: 914 case REG_ASRIDRLA: 915 case REG_ASRIDRHB: 916 case REG_ASRIDRLB: 917 case REG_ASRIDRHC: 918 case REG_ASRIDRLC: 919 case REG_ASR76K: 920 case REG_ASR56K: 921 case REG_ASRMCRA: 922 case REG_ASRMCRB: 923 case REG_ASRMCRC: 924 case REG_ASRMCR1A: 925 case REG_ASRMCR1B: 926 case REG_ASRMCR1C: 927 return true; 928 default: 929 return false; 930 } 931 } 932 933 static struct reg_default fsl_asrc_reg[] = { 934 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 935 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 936 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 937 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 938 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 939 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 940 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 941 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 942 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 943 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 944 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 945 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 946 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 947 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 948 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 949 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 950 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 951 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 952 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 953 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 954 { REG_ASRMCR1C, 0x0000 }, 955 }; 956 957 static const struct regmap_config fsl_asrc_regmap_config = { 958 .reg_bits = 32, 959 .reg_stride = 4, 960 .val_bits = 32, 961 962 .max_register = REG_ASRMCR1C, 963 .reg_defaults = fsl_asrc_reg, 964 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 965 .readable_reg = fsl_asrc_readable_reg, 966 .volatile_reg = fsl_asrc_volatile_reg, 967 .writeable_reg = fsl_asrc_writeable_reg, 968 .cache_type = REGCACHE_FLAT, 969 }; 970 971 /** 972 * fsl_asrc_init - Initialize ASRC registers with a default configuration 973 * @asrc: ASRC context 974 */ 975 static int fsl_asrc_init(struct fsl_asrc *asrc) 976 { 977 unsigned long ipg_rate; 978 979 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 980 regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 981 982 /* Disable interrupt by default */ 983 regmap_write(asrc->regmap, REG_ASRIER, 0x0); 984 985 /* Apply recommended settings for parameters from Reference Manual */ 986 regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff); 987 regmap_write(asrc->regmap, REG_ASRPM2, 0x255555); 988 regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280); 989 regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280); 990 regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280); 991 992 /* Base address for task queue FIFO. Set to 0x7C */ 993 regmap_update_bits(asrc->regmap, REG_ASRTFR1, 994 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 995 996 /* 997 * Set the period of the 76KHz and 56KHz sampling clocks based on 998 * the ASRC processing clock. 999 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947 1000 */ 1001 ipg_rate = clk_get_rate(asrc->ipg_clk); 1002 regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000); 1003 return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000); 1004 } 1005 1006 /** 1007 * fsl_asrc_isr- Interrupt handler for ASRC 1008 * @irq: irq number 1009 * @dev_id: ASRC context 1010 */ 1011 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 1012 { 1013 struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id; 1014 struct device *dev = &asrc->pdev->dev; 1015 enum asrc_pair_index index; 1016 u32 status; 1017 1018 regmap_read(asrc->regmap, REG_ASRSTR, &status); 1019 1020 /* Clean overload error */ 1021 regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE); 1022 1023 /* 1024 * We here use dev_dbg() for all exceptions because ASRC itself does 1025 * not care if FIFO overflowed or underrun while a warning in the 1026 * interrupt would result a ridged conversion. 1027 */ 1028 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 1029 if (!asrc->pair[index]) 1030 continue; 1031 1032 if (status & ASRSTR_ATQOL) { 1033 asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 1034 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 1035 } 1036 1037 if (status & ASRSTR_AOOL(index)) { 1038 asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 1039 pair_dbg("Output Task Overload\n"); 1040 } 1041 1042 if (status & ASRSTR_AIOL(index)) { 1043 asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 1044 pair_dbg("Input Task Overload\n"); 1045 } 1046 1047 if (status & ASRSTR_AODO(index)) { 1048 asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 1049 pair_dbg("Output Data Buffer has overflowed\n"); 1050 } 1051 1052 if (status & ASRSTR_AIDU(index)) { 1053 asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 1054 pair_dbg("Input Data Buffer has underflowed\n"); 1055 } 1056 } 1057 1058 return IRQ_HANDLED; 1059 } 1060 1061 static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index) 1062 { 1063 return REG_ASRDx(dir, index); 1064 } 1065 1066 /* Get sample numbers in FIFO */ 1067 static unsigned int fsl_asrc_get_output_fifo_size(struct fsl_asrc_pair *pair) 1068 { 1069 struct fsl_asrc *asrc = pair->asrc; 1070 enum asrc_pair_index index = pair->index; 1071 u32 val; 1072 1073 regmap_read(asrc->regmap, REG_ASRFST(index), &val); 1074 1075 val &= ASRFSTi_OUTPUT_FIFO_MASK; 1076 1077 return val >> ASRFSTi_OUTPUT_FIFO_SHIFT; 1078 } 1079 1080 static int fsl_asrc_m2m_prepare(struct fsl_asrc_pair *pair) 1081 { 1082 struct fsl_asrc_pair_priv *pair_priv = pair->private; 1083 struct fsl_asrc *asrc = pair->asrc; 1084 struct device *dev = &asrc->pdev->dev; 1085 struct asrc_config config; 1086 int ret; 1087 1088 /* fill config */ 1089 config.pair = pair->index; 1090 config.channel_num = pair->channels; 1091 config.input_sample_rate = pair->rate[IN]; 1092 config.output_sample_rate = pair->rate[OUT]; 1093 config.input_format = pair->sample_format[IN]; 1094 config.output_format = pair->sample_format[OUT]; 1095 config.inclk = INCLK_NONE; 1096 config.outclk = OUTCLK_ASRCK1_CLK; 1097 1098 pair_priv->config = &config; 1099 ret = fsl_asrc_config_pair(pair, true); 1100 if (ret) { 1101 dev_err(dev, "failed to config pair: %d\n", ret); 1102 return ret; 1103 } 1104 1105 pair->first_convert = 1; 1106 1107 return 0; 1108 } 1109 1110 static int fsl_asrc_m2m_start(struct fsl_asrc_pair *pair) 1111 { 1112 if (pair->first_convert) { 1113 fsl_asrc_start_pair(pair); 1114 pair->first_convert = 0; 1115 } 1116 /* 1117 * Clear DMA request during the stall state of ASRC: 1118 * During STALL state, the remaining in input fifo would never be 1119 * smaller than the input threshold while the output fifo would not 1120 * be bigger than output one. Thus the DMA request would be cleared. 1121 */ 1122 fsl_asrc_set_watermarks(pair, ASRC_FIFO_THRESHOLD_MIN, 1123 ASRC_FIFO_THRESHOLD_MAX); 1124 1125 /* Update the real input threshold to raise DMA request */ 1126 fsl_asrc_set_watermarks(pair, ASRC_M2M_INPUTFIFO_WML, 1127 ASRC_M2M_OUTPUTFIFO_WML); 1128 1129 return 0; 1130 } 1131 1132 static int fsl_asrc_m2m_stop(struct fsl_asrc_pair *pair) 1133 { 1134 if (!pair->first_convert) { 1135 fsl_asrc_stop_pair(pair); 1136 pair->first_convert = 1; 1137 } 1138 1139 return 0; 1140 } 1141 1142 /* calculate capture data length according to output data length and sample rate */ 1143 static int fsl_asrc_m2m_calc_out_len(struct fsl_asrc_pair *pair, int input_buffer_length) 1144 { 1145 unsigned int in_width, out_width; 1146 unsigned int channels = pair->channels; 1147 unsigned int in_samples, out_samples; 1148 unsigned int out_length; 1149 1150 in_width = snd_pcm_format_physical_width(pair->sample_format[IN]) / 8; 1151 out_width = snd_pcm_format_physical_width(pair->sample_format[OUT]) / 8; 1152 1153 in_samples = input_buffer_length / in_width / channels; 1154 out_samples = pair->rate[OUT] * in_samples / pair->rate[IN]; 1155 out_length = (out_samples - ASRC_OUTPUT_LAST_SAMPLE) * out_width * channels; 1156 1157 return out_length; 1158 } 1159 1160 static int fsl_asrc_m2m_get_maxburst(u8 dir, struct fsl_asrc_pair *pair) 1161 { 1162 struct fsl_asrc *asrc = pair->asrc; 1163 struct fsl_asrc_priv *asrc_priv = asrc->private; 1164 int wml = (dir == IN) ? ASRC_M2M_INPUTFIFO_WML : ASRC_M2M_OUTPUTFIFO_WML; 1165 1166 if (!asrc_priv->soc->use_edma) 1167 return wml * pair->channels; 1168 else 1169 return 1; 1170 } 1171 1172 static int fsl_asrc_m2m_get_cap(struct fsl_asrc_m2m_cap *cap) 1173 { 1174 cap->fmt_in = FSL_ASRC_FORMATS; 1175 cap->fmt_out = FSL_ASRC_FORMATS | SNDRV_PCM_FMTBIT_S8; 1176 1177 cap->rate_in = supported_asrc_rate; 1178 cap->rate_in_count = ARRAY_SIZE(supported_asrc_rate); 1179 cap->rate_out = supported_asrc_rate; 1180 cap->rate_out_count = ARRAY_SIZE(supported_asrc_rate); 1181 cap->chan_min = 1; 1182 cap->chan_max = 10; 1183 1184 return 0; 1185 } 1186 1187 static int fsl_asrc_m2m_pair_resume(struct fsl_asrc_pair *pair) 1188 { 1189 struct fsl_asrc *asrc = pair->asrc; 1190 int i; 1191 1192 for (i = 0; i < pair->channels * 4; i++) 1193 regmap_write(asrc->regmap, REG_ASRDI(pair->index), 0); 1194 1195 pair->first_convert = 1; 1196 return 0; 1197 } 1198 1199 static int fsl_asrc_runtime_resume(struct device *dev); 1200 static int fsl_asrc_runtime_suspend(struct device *dev); 1201 1202 static int fsl_asrc_probe(struct platform_device *pdev) 1203 { 1204 struct device_node *np = pdev->dev.of_node; 1205 struct fsl_asrc_priv *asrc_priv; 1206 struct fsl_asrc *asrc; 1207 struct resource *res; 1208 void __iomem *regs; 1209 int irq, ret, i; 1210 u32 asrc_fmt = 0; 1211 u32 map_idx; 1212 char tmp[16]; 1213 u32 width; 1214 1215 asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL); 1216 if (!asrc) 1217 return -ENOMEM; 1218 1219 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 1220 if (!asrc_priv) 1221 return -ENOMEM; 1222 1223 asrc->pdev = pdev; 1224 asrc->private = asrc_priv; 1225 1226 /* Get the addresses and IRQ */ 1227 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1228 if (IS_ERR(regs)) 1229 return PTR_ERR(regs); 1230 1231 asrc->paddr = res->start; 1232 1233 asrc->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_asrc_regmap_config); 1234 if (IS_ERR(asrc->regmap)) { 1235 dev_err(&pdev->dev, "failed to init regmap\n"); 1236 return PTR_ERR(asrc->regmap); 1237 } 1238 1239 irq = platform_get_irq(pdev, 0); 1240 if (irq < 0) 1241 return irq; 1242 1243 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 1244 dev_name(&pdev->dev), asrc); 1245 if (ret) { 1246 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 1247 return ret; 1248 } 1249 1250 asrc->mem_clk = devm_clk_get(&pdev->dev, "mem"); 1251 if (IS_ERR(asrc->mem_clk)) { 1252 dev_err(&pdev->dev, "failed to get mem clock\n"); 1253 return PTR_ERR(asrc->mem_clk); 1254 } 1255 1256 asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 1257 if (IS_ERR(asrc->ipg_clk)) { 1258 dev_err(&pdev->dev, "failed to get ipg clock\n"); 1259 return PTR_ERR(asrc->ipg_clk); 1260 } 1261 1262 asrc->spba_clk = devm_clk_get(&pdev->dev, "spba"); 1263 if (IS_ERR(asrc->spba_clk)) 1264 dev_warn(&pdev->dev, "failed to get spba clock\n"); 1265 1266 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1267 sprintf(tmp, "asrck_%x", i); 1268 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 1269 if (IS_ERR(asrc_priv->asrck_clk[i])) { 1270 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 1271 return PTR_ERR(asrc_priv->asrck_clk[i]); 1272 } 1273 } 1274 1275 asrc_priv->soc = of_device_get_match_data(&pdev->dev); 1276 asrc->use_edma = asrc_priv->soc->use_edma; 1277 asrc->get_dma_channel = fsl_asrc_get_dma_channel; 1278 asrc->request_pair = fsl_asrc_request_pair; 1279 asrc->release_pair = fsl_asrc_release_pair; 1280 asrc->get_fifo_addr = fsl_asrc_get_fifo_addr; 1281 asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv); 1282 1283 asrc->m2m_prepare = fsl_asrc_m2m_prepare; 1284 asrc->m2m_start = fsl_asrc_m2m_start; 1285 asrc->m2m_stop = fsl_asrc_m2m_stop; 1286 asrc->get_output_fifo_size = fsl_asrc_get_output_fifo_size; 1287 asrc->m2m_calc_out_len = fsl_asrc_m2m_calc_out_len; 1288 asrc->m2m_get_maxburst = fsl_asrc_m2m_get_maxburst; 1289 asrc->m2m_pair_resume = fsl_asrc_m2m_pair_resume; 1290 asrc->m2m_get_cap = fsl_asrc_m2m_get_cap; 1291 1292 if (of_device_is_compatible(np, "fsl,imx35-asrc")) { 1293 asrc_priv->clk_map[IN] = input_clk_map_imx35; 1294 asrc_priv->clk_map[OUT] = output_clk_map_imx35; 1295 } else if (of_device_is_compatible(np, "fsl,imx53-asrc")) { 1296 asrc_priv->clk_map[IN] = input_clk_map_imx53; 1297 asrc_priv->clk_map[OUT] = output_clk_map_imx53; 1298 } else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") || 1299 of_device_is_compatible(np, "fsl,imx8qxp-asrc")) { 1300 ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx); 1301 if (ret) { 1302 dev_err(&pdev->dev, "failed to get clk map index\n"); 1303 return ret; 1304 } 1305 1306 if (map_idx > 1) { 1307 dev_err(&pdev->dev, "unsupported clk map index\n"); 1308 return -EINVAL; 1309 } 1310 if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) { 1311 asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx]; 1312 asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx]; 1313 } else { 1314 asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx]; 1315 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx]; 1316 } 1317 } 1318 1319 asrc->channel_avail = 10; 1320 1321 ret = of_property_read_u32(np, "fsl,asrc-rate", 1322 &asrc->asrc_rate); 1323 if (ret) { 1324 dev_err(&pdev->dev, "failed to get output rate\n"); 1325 return ret; 1326 } 1327 1328 ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt); 1329 asrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt; 1330 if (ret) { 1331 ret = of_property_read_u32(np, "fsl,asrc-width", &width); 1332 if (ret) { 1333 dev_err(&pdev->dev, "failed to decide output format\n"); 1334 return ret; 1335 } 1336 1337 switch (width) { 1338 case 16: 1339 asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE; 1340 break; 1341 case 24: 1342 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1343 break; 1344 default: 1345 dev_warn(&pdev->dev, 1346 "unsupported width, use default S24_LE\n"); 1347 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1348 break; 1349 } 1350 } 1351 1352 if (!(FSL_ASRC_FORMATS & pcm_format_to_bits(asrc->asrc_format))) { 1353 dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n"); 1354 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1355 } 1356 1357 platform_set_drvdata(pdev, asrc); 1358 spin_lock_init(&asrc->lock); 1359 pm_runtime_enable(&pdev->dev); 1360 if (!pm_runtime_enabled(&pdev->dev)) { 1361 ret = fsl_asrc_runtime_resume(&pdev->dev); 1362 if (ret) 1363 goto err_pm_disable; 1364 } 1365 1366 ret = pm_runtime_resume_and_get(&pdev->dev); 1367 if (ret < 0) 1368 goto err_pm_get_sync; 1369 1370 ret = fsl_asrc_init(asrc); 1371 if (ret) { 1372 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 1373 goto err_pm_get_sync; 1374 } 1375 1376 ret = pm_runtime_put_sync(&pdev->dev); 1377 if (ret < 0 && ret != -ENOSYS) 1378 goto err_pm_get_sync; 1379 1380 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 1381 &fsl_asrc_dai, 1); 1382 if (ret) { 1383 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 1384 goto err_pm_get_sync; 1385 } 1386 1387 ret = fsl_asrc_m2m_init(asrc); 1388 if (ret) { 1389 dev_err(&pdev->dev, "failed to init m2m device %d\n", ret); 1390 return ret; 1391 } 1392 1393 return 0; 1394 1395 err_pm_get_sync: 1396 if (!pm_runtime_status_suspended(&pdev->dev)) 1397 fsl_asrc_runtime_suspend(&pdev->dev); 1398 err_pm_disable: 1399 pm_runtime_disable(&pdev->dev); 1400 return ret; 1401 } 1402 1403 static void fsl_asrc_remove(struct platform_device *pdev) 1404 { 1405 struct fsl_asrc *asrc = dev_get_drvdata(&pdev->dev); 1406 1407 fsl_asrc_m2m_exit(asrc); 1408 1409 pm_runtime_disable(&pdev->dev); 1410 if (!pm_runtime_status_suspended(&pdev->dev)) 1411 fsl_asrc_runtime_suspend(&pdev->dev); 1412 } 1413 1414 static int fsl_asrc_runtime_resume(struct device *dev) 1415 { 1416 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1417 struct fsl_asrc_priv *asrc_priv = asrc->private; 1418 int reg, retry = INIT_RETRY_NUM; 1419 int i, ret; 1420 u32 asrctr; 1421 1422 ret = clk_prepare_enable(asrc->mem_clk); 1423 if (ret) 1424 return ret; 1425 ret = clk_prepare_enable(asrc->ipg_clk); 1426 if (ret) 1427 goto disable_mem_clk; 1428 if (!IS_ERR(asrc->spba_clk)) { 1429 ret = clk_prepare_enable(asrc->spba_clk); 1430 if (ret) 1431 goto disable_ipg_clk; 1432 } 1433 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1434 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]); 1435 if (ret) 1436 goto disable_asrck_clk; 1437 } 1438 1439 /* Stop all pairs provisionally */ 1440 regmap_read(asrc->regmap, REG_ASRCTR, &asrctr); 1441 regmap_update_bits(asrc->regmap, REG_ASRCTR, 1442 ASRCTR_ASRCEi_ALL_MASK, 0); 1443 1444 /* Restore all registers */ 1445 regcache_cache_only(asrc->regmap, false); 1446 regcache_mark_dirty(asrc->regmap); 1447 regcache_sync(asrc->regmap); 1448 1449 regmap_update_bits(asrc->regmap, REG_ASRCFG, 1450 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK | 1451 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg); 1452 1453 /* Restart enabled pairs */ 1454 regmap_update_bits(asrc->regmap, REG_ASRCTR, 1455 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1456 1457 /* Wait for status of initialization for all enabled pairs */ 1458 do { 1459 udelay(5); 1460 regmap_read(asrc->regmap, REG_ASRCFG, ®); 1461 reg = (reg >> ASRCFG_INIRQi_SHIFT(0)) & 0x7; 1462 } while ((reg != ((asrctr >> ASRCTR_ASRCEi_SHIFT(0)) & 0x7)) && --retry); 1463 1464 /* 1465 * NOTE: Doesn't treat initialization timeout as an error 1466 * Some of the pairs may success, then still can continue. 1467 */ 1468 if (!retry) { 1469 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 1470 if ((asrctr & ASRCTR_ASRCEi_MASK(i)) && !(reg & (1 << i))) 1471 dev_warn(dev, "Pair %c initialization isn't finished\n", 'A' + i); 1472 } 1473 } 1474 1475 return 0; 1476 1477 disable_asrck_clk: 1478 for (i--; i >= 0; i--) 1479 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1480 if (!IS_ERR(asrc->spba_clk)) 1481 clk_disable_unprepare(asrc->spba_clk); 1482 disable_ipg_clk: 1483 clk_disable_unprepare(asrc->ipg_clk); 1484 disable_mem_clk: 1485 clk_disable_unprepare(asrc->mem_clk); 1486 return ret; 1487 } 1488 1489 static int fsl_asrc_runtime_suspend(struct device *dev) 1490 { 1491 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1492 struct fsl_asrc_priv *asrc_priv = asrc->private; 1493 int i; 1494 1495 regmap_read(asrc->regmap, REG_ASRCFG, 1496 &asrc_priv->regcache_cfg); 1497 1498 regcache_cache_only(asrc->regmap, true); 1499 1500 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 1501 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1502 if (!IS_ERR(asrc->spba_clk)) 1503 clk_disable_unprepare(asrc->spba_clk); 1504 clk_disable_unprepare(asrc->ipg_clk); 1505 clk_disable_unprepare(asrc->mem_clk); 1506 1507 return 0; 1508 } 1509 1510 static int fsl_asrc_suspend(struct device *dev) 1511 { 1512 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1513 int ret; 1514 1515 fsl_asrc_m2m_suspend(asrc); 1516 ret = pm_runtime_force_suspend(dev); 1517 return ret; 1518 } 1519 1520 static int fsl_asrc_resume(struct device *dev) 1521 { 1522 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1523 int ret; 1524 1525 ret = pm_runtime_force_resume(dev); 1526 fsl_asrc_m2m_resume(asrc); 1527 return ret; 1528 } 1529 1530 static const struct dev_pm_ops fsl_asrc_pm = { 1531 RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 1532 SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) 1533 }; 1534 1535 static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = { 1536 .use_edma = false, 1537 .channel_bits = 3, 1538 }; 1539 1540 static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = { 1541 .use_edma = false, 1542 .channel_bits = 4, 1543 }; 1544 1545 static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = { 1546 .use_edma = true, 1547 .channel_bits = 4, 1548 }; 1549 1550 static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = { 1551 .use_edma = true, 1552 .channel_bits = 4, 1553 }; 1554 1555 static const struct of_device_id fsl_asrc_ids[] = { 1556 { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data }, 1557 { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data }, 1558 { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data }, 1559 { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data }, 1560 {} 1561 }; 1562 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1563 1564 static struct platform_driver fsl_asrc_driver = { 1565 .probe = fsl_asrc_probe, 1566 .remove = fsl_asrc_remove, 1567 .driver = { 1568 .name = "fsl-asrc", 1569 .of_match_table = fsl_asrc_ids, 1570 .pm = pm_ptr(&fsl_asrc_pm), 1571 }, 1572 }; 1573 module_platform_driver(fsl_asrc_driver); 1574 1575 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1576 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1577 MODULE_ALIAS("platform:fsl-asrc"); 1578 MODULE_LICENSE("GPL v2"); 1579