1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_DEVICE_TYPES_H_ 7 #define _XE_DEVICE_TYPES_H_ 8 9 #include <linux/pci.h> 10 11 #include <drm/drm_device.h> 12 #include <drm/drm_file.h> 13 #include <drm/ttm/ttm_device.h> 14 15 #include "xe_devcoredump_types.h" 16 #include "xe_heci_gsc.h" 17 #include "xe_gt_types.h" 18 #include "xe_lmtt_types.h" 19 #include "xe_memirq_types.h" 20 #include "xe_oa.h" 21 #include "xe_platform_types.h" 22 #include "xe_pt_types.h" 23 #include "xe_sriov_types.h" 24 #include "xe_step_types.h" 25 26 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 27 #include "soc/intel_pch.h" 28 #include "intel_display_core.h" 29 #include "intel_display_device.h" 30 #endif 31 32 struct xe_ggtt; 33 struct xe_pat_ops; 34 35 #define XE_BO_INVALID_OFFSET LONG_MAX 36 37 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100) 38 #define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100) 39 #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100) 40 #define MEDIA_VERx100(xe) ((xe)->info.media_verx100) 41 #define IS_DGFX(xe) ((xe)->info.is_dgfx) 42 #define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi) 43 44 #define XE_VRAM_FLAGS_NEED64K BIT(0) 45 46 #define XE_GT0 0 47 #define XE_GT1 1 48 #define XE_MAX_TILES_PER_DEVICE (XE_GT1 + 1) 49 50 #define XE_MAX_ASID (BIT(20)) 51 52 #define IS_PLATFORM_STEP(_xe, _platform, min_step, max_step) \ 53 ((_xe)->info.platform == (_platform) && \ 54 (_xe)->info.step.graphics >= (min_step) && \ 55 (_xe)->info.step.graphics < (max_step)) 56 #define IS_SUBPLATFORM_STEP(_xe, _platform, sub, min_step, max_step) \ 57 ((_xe)->info.platform == (_platform) && \ 58 (_xe)->info.subplatform == (sub) && \ 59 (_xe)->info.step.graphics >= (min_step) && \ 60 (_xe)->info.step.graphics < (max_step)) 61 62 #define tile_to_xe(tile__) \ 63 _Generic(tile__, \ 64 const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \ 65 struct xe_tile * : (tile__)->xe) 66 67 /** 68 * struct xe_mem_region - memory region structure 69 * This is used to describe a memory region in xe 70 * device, such as HBM memory or CXL extension memory. 71 */ 72 struct xe_mem_region { 73 /** @io_start: IO start address of this VRAM instance */ 74 resource_size_t io_start; 75 /** 76 * @io_size: IO size of this VRAM instance 77 * 78 * This represents how much of this VRAM we can access 79 * via the CPU through the VRAM BAR. This can be smaller 80 * than @usable_size, in which case only part of VRAM is CPU 81 * accessible (typically the first 256M). This 82 * configuration is known as small-bar. 83 */ 84 resource_size_t io_size; 85 /** @dpa_base: This memory regions's DPA (device physical address) base */ 86 resource_size_t dpa_base; 87 /** 88 * @usable_size: usable size of VRAM 89 * 90 * Usable size of VRAM excluding reserved portions 91 * (e.g stolen mem) 92 */ 93 resource_size_t usable_size; 94 /** 95 * @actual_physical_size: Actual VRAM size 96 * 97 * Actual VRAM size including reserved portions 98 * (e.g stolen mem) 99 */ 100 resource_size_t actual_physical_size; 101 /** @mapping: pointer to VRAM mappable space */ 102 void __iomem *mapping; 103 }; 104 105 /** 106 * struct xe_tile - hardware tile structure 107 * 108 * From a driver perspective, a "tile" is effectively a complete GPU, containing 109 * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM. 110 * 111 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI 112 * device and designate one "root" tile as being responsible for external PCI 113 * communication. PCI BAR0 exposes the GGTT and MMIO register space for each 114 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated 115 * with each tile similarly. Device-wide interrupts can be enabled/disabled 116 * at the root tile, and the MSTR_TILE_INTR register will report which tiles 117 * have interrupts that need servicing. 118 */ 119 struct xe_tile { 120 /** @xe: Backpointer to tile's PCI device */ 121 struct xe_device *xe; 122 123 /** @id: ID of the tile */ 124 u8 id; 125 126 /** 127 * @primary_gt: Primary GT 128 */ 129 struct xe_gt *primary_gt; 130 131 /** 132 * @media_gt: Media GT 133 * 134 * Only present on devices with media version >= 13. 135 */ 136 struct xe_gt *media_gt; 137 138 /** 139 * @mmio: MMIO info for a tile. 140 * 141 * Each tile has its own 16MB space in BAR0, laid out as: 142 * * 0-4MB: registers 143 * * 4MB-8MB: reserved 144 * * 8MB-16MB: global GTT 145 */ 146 struct { 147 /** @mmio.size: size of tile's MMIO space */ 148 size_t size; 149 150 /** @mmio.regs: pointer to tile's MMIO space (starting with registers) */ 151 void __iomem *regs; 152 } mmio; 153 154 /** 155 * @mmio_ext: MMIO-extension info for a tile. 156 * 157 * Each tile has its own additional 256MB (28-bit) MMIO-extension space. 158 */ 159 struct { 160 /** @mmio_ext.size: size of tile's additional MMIO-extension space */ 161 size_t size; 162 163 /** @mmio_ext.regs: pointer to tile's additional MMIO-extension space */ 164 void __iomem *regs; 165 } mmio_ext; 166 167 /** @mem: memory management info for tile */ 168 struct { 169 /** 170 * @mem.vram: VRAM info for tile. 171 * 172 * Although VRAM is associated with a specific tile, it can 173 * still be accessed by all tiles' GTs. 174 */ 175 struct xe_mem_region vram; 176 177 /** @mem.vram_mgr: VRAM TTM manager */ 178 struct xe_ttm_vram_mgr *vram_mgr; 179 180 /** @mem.ggtt: Global graphics translation table */ 181 struct xe_ggtt *ggtt; 182 183 /** 184 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated. 185 * 186 * Media GT shares a pool with its primary GT. 187 */ 188 struct xe_sa_manager *kernel_bb_pool; 189 } mem; 190 191 /** @sriov: tile level virtualization data */ 192 union { 193 struct { 194 /** @sriov.pf.lmtt: Local Memory Translation Table. */ 195 struct xe_lmtt lmtt; 196 } pf; 197 struct { 198 /** @sriov.vf.memirq: Memory Based Interrupts. */ 199 struct xe_memirq memirq; 200 201 /** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */ 202 struct drm_mm_node ggtt_balloon[2]; 203 } vf; 204 } sriov; 205 206 /** @migrate: Migration helper for vram blits and clearing */ 207 struct xe_migrate *migrate; 208 209 /** @sysfs: sysfs' kobj used by xe_tile_sysfs */ 210 struct kobject *sysfs; 211 }; 212 213 /** 214 * struct xe_device - Top level struct of XE device 215 */ 216 struct xe_device { 217 /** @drm: drm device */ 218 struct drm_device drm; 219 220 /** @devcoredump: device coredump */ 221 struct xe_devcoredump devcoredump; 222 223 /** @info: device info */ 224 struct intel_device_info { 225 /** @info.platform_name: platform name */ 226 const char *platform_name; 227 /** @info.graphics_name: graphics IP name */ 228 const char *graphics_name; 229 /** @info.media_name: media IP name */ 230 const char *media_name; 231 /** @info.tile_mmio_ext_size: size of MMIO extension space, per-tile */ 232 u32 tile_mmio_ext_size; 233 /** @info.graphics_verx100: graphics IP version */ 234 u32 graphics_verx100; 235 /** @info.media_verx100: media IP version */ 236 u32 media_verx100; 237 /** @info.mem_region_mask: mask of valid memory regions */ 238 u32 mem_region_mask; 239 /** @info.platform: XE platform enum */ 240 enum xe_platform platform; 241 /** @info.subplatform: XE subplatform enum */ 242 enum xe_subplatform subplatform; 243 /** @info.devid: device ID */ 244 u16 devid; 245 /** @info.revid: device revision */ 246 u8 revid; 247 /** @info.step: stepping information for each IP */ 248 struct xe_step_info step; 249 /** @info.dma_mask_size: DMA address bits */ 250 u8 dma_mask_size; 251 /** @info.vram_flags: Vram flags */ 252 u8 vram_flags; 253 /** @info.tile_count: Number of tiles */ 254 u8 tile_count; 255 /** @info.gt_count: Total number of GTs for entire device */ 256 u8 gt_count; 257 /** @info.vm_max_level: Max VM level */ 258 u8 vm_max_level; 259 /** @info.va_bits: Maximum bits of a virtual address */ 260 u8 va_bits; 261 262 /** @info.is_dgfx: is discrete device */ 263 u8 is_dgfx:1; 264 /** @info.has_asid: Has address space ID */ 265 u8 has_asid:1; 266 /** @info.force_execlist: Forced execlist submission */ 267 u8 force_execlist:1; 268 /** @info.has_flat_ccs: Whether flat CCS metadata is used */ 269 u8 has_flat_ccs:1; 270 /** @info.has_llc: Device has a shared CPU+GPU last level cache */ 271 u8 has_llc:1; 272 /** @info.has_mmio_ext: Device has extra MMIO address range */ 273 u8 has_mmio_ext:1; 274 /** @info.has_range_tlb_invalidation: Has range based TLB invalidations */ 275 u8 has_range_tlb_invalidation:1; 276 /** @info.has_sriov: Supports SR-IOV */ 277 u8 has_sriov:1; 278 /** @info.has_usm: Device has unified shared memory support */ 279 u8 has_usm:1; 280 /** @info.enable_display: display enabled */ 281 u8 enable_display:1; 282 /** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */ 283 u8 skip_mtcfg:1; 284 /** @info.skip_pcode: skip access to PCODE uC */ 285 u8 skip_pcode:1; 286 /** @info.has_heci_gscfi: device has heci gscfi */ 287 u8 has_heci_gscfi:1; 288 /** @info.skip_guc_pc: Skip GuC based PM feature init */ 289 u8 skip_guc_pc:1; 290 /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ 291 u8 has_atomic_enable_pte_bit:1; 292 /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ 293 u8 has_device_atomics_on_smem:1; 294 295 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 296 struct { 297 u32 rawclk_freq; 298 } i915_runtime; 299 #endif 300 } info; 301 302 /** @irq: device interrupt state */ 303 struct { 304 /** @irq.lock: lock for processing irq's on this device */ 305 spinlock_t lock; 306 307 /** @irq.enabled: interrupts enabled on this device */ 308 bool enabled; 309 } irq; 310 311 /** @ttm: ttm device */ 312 struct ttm_device ttm; 313 314 /** @mmio: mmio info for device */ 315 struct { 316 /** @mmio.size: size of MMIO space for device */ 317 size_t size; 318 /** @mmio.regs: pointer to MMIO space for device */ 319 void __iomem *regs; 320 } mmio; 321 322 /** @mem: memory info for device */ 323 struct { 324 /** @mem.vram: VRAM info for device */ 325 struct xe_mem_region vram; 326 /** @mem.sys_mgr: system TTM manager */ 327 struct ttm_resource_manager sys_mgr; 328 } mem; 329 330 /** @sriov: device level virtualization data */ 331 struct { 332 /** @sriov.__mode: SR-IOV mode (Don't access directly!) */ 333 enum xe_sriov_mode __mode; 334 335 /** @sriov.pf: PF specific data */ 336 struct xe_device_pf pf; 337 338 /** @sriov.wq: workqueue used by the virtualization workers */ 339 struct workqueue_struct *wq; 340 } sriov; 341 342 /** @clients: drm clients info */ 343 struct { 344 /** @clients.lock: Protects drm clients info */ 345 spinlock_t lock; 346 347 /** @clients.count: number of drm clients */ 348 u64 count; 349 } clients; 350 351 /** @usm: unified memory state */ 352 struct { 353 /** @usm.asid: convert a ASID to VM */ 354 struct xarray asid_to_vm; 355 /** @usm.next_asid: next ASID, used to cyclical alloc asids */ 356 u32 next_asid; 357 /** @usm.num_vm_in_fault_mode: number of VM in fault mode */ 358 u32 num_vm_in_fault_mode; 359 /** @usm.num_vm_in_non_fault_mode: number of VM in non-fault mode */ 360 u32 num_vm_in_non_fault_mode; 361 /** @usm.lock: protects UM state */ 362 struct mutex lock; 363 } usm; 364 365 /** @pinned: pinned BO state */ 366 struct { 367 /** @pinned.lock: protected pinned BO list state */ 368 spinlock_t lock; 369 /** @pinned.kernel_bo_present: pinned kernel BO that are present */ 370 struct list_head kernel_bo_present; 371 /** @pinned.evicted: pinned BO that have been evicted */ 372 struct list_head evicted; 373 /** @pinned.external_vram: pinned external BO in vram*/ 374 struct list_head external_vram; 375 } pinned; 376 377 /** @ufence_wq: user fence wait queue */ 378 wait_queue_head_t ufence_wq; 379 380 /** @preempt_fence_wq: used to serialize preempt fences */ 381 struct workqueue_struct *preempt_fence_wq; 382 383 /** @ordered_wq: used to serialize compute mode resume */ 384 struct workqueue_struct *ordered_wq; 385 386 /** @unordered_wq: used to serialize unordered work, mostly display */ 387 struct workqueue_struct *unordered_wq; 388 389 /** @tiles: device tiles */ 390 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; 391 392 /** 393 * @mem_access: keep track of memory access in the device, possibly 394 * triggering additional actions when they occur. 395 */ 396 struct { 397 /** 398 * @mem_access.vram_userfault: Encapsulate vram_userfault 399 * related stuff 400 */ 401 struct { 402 /** 403 * @mem_access.vram_userfault.lock: Protects access to 404 * @vram_usefault.list Using mutex instead of spinlock 405 * as lock is applied to entire list operation which 406 * may sleep 407 */ 408 struct mutex lock; 409 410 /** 411 * @mem_access.vram_userfault.list: Keep list of userfaulted 412 * vram bo, which require to release their mmap mappings 413 * at runtime suspend path 414 */ 415 struct list_head list; 416 } vram_userfault; 417 } mem_access; 418 419 /** 420 * @pat: Encapsulate PAT related stuff 421 */ 422 struct { 423 /** @pat.ops: Internal operations to abstract platforms */ 424 const struct xe_pat_ops *ops; 425 /** @pat.table: PAT table to program in the HW */ 426 const struct xe_pat_table_entry *table; 427 /** @pat.n_entries: Number of PAT entries */ 428 int n_entries; 429 u32 idx[__XE_CACHE_LEVEL_COUNT]; 430 } pat; 431 432 /** @d3cold: Encapsulate d3cold related stuff */ 433 struct { 434 /** @d3cold.capable: Indicates if root port is d3cold capable */ 435 bool capable; 436 437 /** @d3cold.allowed: Indicates if d3cold is a valid device state */ 438 bool allowed; 439 440 /** 441 * @d3cold.vram_threshold: 442 * 443 * This represents the permissible threshold(in megabytes) 444 * for vram save/restore. d3cold will be disallowed, 445 * when vram_usages is above or equals the threshold value 446 * to avoid the vram save/restore latency. 447 * Default threshold value is 300mb. 448 */ 449 u32 vram_threshold; 450 /** @d3cold.lock: protect vram_threshold */ 451 struct mutex lock; 452 } d3cold; 453 454 /** 455 * @pm_callback_task: Track the active task that is running in either 456 * the runtime_suspend or runtime_resume callbacks. 457 */ 458 struct task_struct *pm_callback_task; 459 460 /** @hwmon: hwmon subsystem integration */ 461 struct xe_hwmon *hwmon; 462 463 /** @heci_gsc: graphics security controller */ 464 struct xe_heci_gsc heci_gsc; 465 466 /** @oa: oa observation subsystem */ 467 struct xe_oa oa; 468 469 /** @needs_flr_on_fini: requests function-reset on fini */ 470 bool needs_flr_on_fini; 471 472 /** @wedged: Struct to control Wedged States and mode */ 473 struct { 474 /** @wedged.flag: Xe device faced a critical error and is now blocked. */ 475 atomic_t flag; 476 /** @wedged.mode: Mode controlled by kernel parameter and debugfs */ 477 int mode; 478 } wedged; 479 480 /* private: */ 481 482 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 483 /* 484 * Any fields below this point are the ones used by display. 485 * They are temporarily added here so xe_device can be desguised as 486 * drm_i915_private during build. After cleanup these should go away, 487 * migrating to the right sub-structs 488 */ 489 struct intel_display display; 490 enum intel_pch pch_type; 491 u16 pch_id; 492 493 struct dram_info { 494 bool wm_lv_0_adjust_needed; 495 u8 num_channels; 496 bool symmetric_memory; 497 enum intel_dram_type { 498 INTEL_DRAM_UNKNOWN, 499 INTEL_DRAM_DDR3, 500 INTEL_DRAM_DDR4, 501 INTEL_DRAM_LPDDR3, 502 INTEL_DRAM_LPDDR4, 503 INTEL_DRAM_DDR5, 504 INTEL_DRAM_LPDDR5, 505 INTEL_DRAM_GDDR, 506 } type; 507 u8 num_qgv_points; 508 u8 num_psf_gv_points; 509 } dram_info; 510 511 /* 512 * edram size in MB. 513 * Cannot be determined by PCIID. You must always read a register. 514 */ 515 u32 edram_size_mb; 516 517 /* To shut up runtime pm macros.. */ 518 struct xe_runtime_pm {} runtime_pm; 519 520 /* only to allow build, not used functionally */ 521 u32 irq_mask; 522 523 struct intel_uncore { 524 spinlock_t lock; 525 } uncore; 526 527 /* only to allow build, not used functionally */ 528 struct { 529 unsigned int hpll_freq; 530 unsigned int czclk_freq; 531 unsigned int fsb_freq, mem_freq, is_ddr3; 532 }; 533 534 void *pxp; 535 #endif 536 }; 537 538 /** 539 * struct xe_file - file handle for XE driver 540 */ 541 struct xe_file { 542 /** @xe: xe DEVICE **/ 543 struct xe_device *xe; 544 545 /** @drm: base DRM file */ 546 struct drm_file *drm; 547 548 /** @vm: VM state for file */ 549 struct { 550 /** @vm.xe: xarray to store VMs */ 551 struct xarray xa; 552 /** @vm.lock: protects file VM state */ 553 struct mutex lock; 554 } vm; 555 556 /** @exec_queue: Submission exec queue state for file */ 557 struct { 558 /** @exec_queue.xe: xarray to store engines */ 559 struct xarray xa; 560 /** @exec_queue.lock: protects file engine state */ 561 struct mutex lock; 562 } exec_queue; 563 564 /** @run_ticks: hw engine class run time in ticks for this drm client */ 565 u64 run_ticks[XE_ENGINE_CLASS_MAX]; 566 567 /** @client: drm client */ 568 struct xe_drm_client *client; 569 570 /** @refcount: ref count of this xe file */ 571 struct kref refcount; 572 }; 573 574 #endif 575