1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2011 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * Developed by Ben Gray <ben.r.gray@gmail.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the company nor the name of the author may be used to
18 * endorse or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /**
35 * The ARM Cortex-A9 core can support a global timer plus a private and
36 * watchdog timer per core. This driver reserves memory and interrupt
37 * resources for accessing both timer register sets, these resources are
38 * stored globally and used to setup the timecount and eventtimer.
39 *
40 * The timecount timer uses the global 64-bit counter, whereas the
41 * per-CPU eventtimer uses the private 32-bit counters.
42 *
43 *
44 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
45 */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/bus.h>
50 #include <sys/kernel.h>
51 #include <sys/module.h>
52 #include <sys/malloc.h>
53 #include <sys/rman.h>
54 #include <sys/timeet.h>
55 #include <sys/timetc.h>
56 #include <sys/watchdog.h>
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
60
61 #include <machine/machdep.h> /* For arm_set_delay */
62
63 #include <dev/ofw/openfirm.h>
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
66
67 #include <machine/bus.h>
68
69 #include <arm/arm/mpcore_timervar.h>
70
71 /* Private (per-CPU) timer register map */
72 #define PRV_TIMER_LOAD 0x0000
73 #define PRV_TIMER_COUNT 0x0004
74 #define PRV_TIMER_CTRL 0x0008
75 #define PRV_TIMER_INTR 0x000C
76
77 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8
78 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
79 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1)
80 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
81
82 #define PRV_TIMER_INTR_EVENT (1UL << 0)
83
84 /* Global timer register map */
85 #define GBL_TIMER_COUNT_LOW 0x0000
86 #define GBL_TIMER_COUNT_HIGH 0x0004
87 #define GBL_TIMER_CTRL 0x0008
88 #define GBL_TIMER_INTR 0x000C
89
90 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8
91 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3)
92 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
93 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1)
94 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
95
96 #define GBL_TIMER_INTR_EVENT (1UL << 0)
97
98 struct arm_tmr_softc {
99 device_t dev;
100 int irqrid;
101 int memrid;
102 struct resource * gbl_mem;
103 struct resource * prv_mem;
104 struct resource * prv_irq;
105 uint64_t clkfreq;
106 struct eventtimer et;
107 };
108
109 static struct eventtimer *arm_tmr_et;
110 static struct timecounter *arm_tmr_tc;
111 static uint64_t arm_tmr_freq;
112 static boolean_t arm_tmr_freq_varies;
113
114 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
115 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)
116 #define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)
117 #define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val)
118
119 static void arm_tmr_delay(int, void *);
120
121 static timecounter_get_t arm_tmr_get_timecount;
122
123 static struct timecounter arm_tmr_timecount = {
124 .tc_name = "MPCore",
125 .tc_get_timecount = arm_tmr_get_timecount,
126 .tc_poll_pps = NULL,
127 .tc_counter_mask = ~0u,
128 .tc_frequency = 0,
129 .tc_quality = 800,
130 };
131
132 #define TMR_GBL 0x01
133 #define TMR_PRV 0x02
134 #define TMR_BOTH (TMR_GBL | TMR_PRV)
135 #define TMR_NONE 0
136
137 static struct ofw_compat_data compat_data[] = {
138 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */
139 {"arm,cortex-a9-global-timer", TMR_GBL},
140 {"arm,cortex-a5-global-timer", TMR_GBL},
141 {"arm,cortex-a9-twd-timer", TMR_PRV},
142 {"arm,cortex-a5-twd-timer", TMR_PRV},
143 {"arm,arm11mp-twd-timer", TMR_PRV},
144 {NULL, TMR_NONE}
145 };
146
147 /**
148 * arm_tmr_get_timecount - reads the timecount (global) timer
149 * @tc: pointer to arm_tmr_timecount struct
150 *
151 * We only read the lower 32-bits, the timecount stuff only uses 32-bits
152 * so (for now?) ignore the upper 32-bits.
153 *
154 * RETURNS
155 * The lower 32-bits of the counter.
156 */
157 static unsigned
arm_tmr_get_timecount(struct timecounter * tc)158 arm_tmr_get_timecount(struct timecounter *tc)
159 {
160 struct arm_tmr_softc *sc;
161
162 sc = tc->tc_priv;
163 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW));
164 }
165
166 /**
167 * arm_tmr_start - starts the eventtimer (private) timer
168 * @et: pointer to eventtimer struct
169 * @first: the number of seconds and fractional sections to trigger in
170 * @period: the period (in seconds and fractional sections) to set
171 *
172 * If the eventtimer is required to be in oneshot mode, period will be
173 * NULL and first will point to the time to trigger. If in periodic mode
174 * period will contain the time period and first may optionally contain
175 * the time for the first period.
176 *
177 * RETURNS
178 * Always returns 0
179 */
180 static int
arm_tmr_start(struct eventtimer * et,sbintime_t first,sbintime_t period)181 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
182 {
183 struct arm_tmr_softc *sc;
184 uint32_t load, count;
185 uint32_t ctrl;
186
187 sc = et->et_priv;
188 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
189 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
190
191 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
192
193 if (period != 0) {
194 load = ((uint32_t)et->et_frequency * period) >> 32;
195 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;
196 } else
197 load = 0;
198
199 if (first != 0)
200 count = (uint32_t)((et->et_frequency * first) >> 32);
201 else
202 count = load;
203
204 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load);
205 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count);
206 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl);
207
208 return (0);
209 }
210
211 /**
212 * arm_tmr_stop - stops the eventtimer (private) timer
213 * @et: pointer to eventtimer struct
214 *
215 * Simply stops the private timer by clearing all bits in the ctrl register.
216 *
217 * RETURNS
218 * Always returns 0
219 */
220 static int
arm_tmr_stop(struct eventtimer * et)221 arm_tmr_stop(struct eventtimer *et)
222 {
223 struct arm_tmr_softc *sc;
224
225 sc = et->et_priv;
226 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
227 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
228 return (0);
229 }
230
231 /**
232 * arm_tmr_intr - ISR for the eventtimer (private) timer
233 * @arg: pointer to arm_tmr_softc struct
234 *
235 * Clears the event register and then calls the eventtimer callback.
236 *
237 * RETURNS
238 * Always returns FILTER_HANDLED
239 */
240 static int
arm_tmr_intr(void * arg)241 arm_tmr_intr(void *arg)
242 {
243 struct arm_tmr_softc *sc;
244
245 sc = arg;
246 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
247 if (sc->et.et_active)
248 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
249 return (FILTER_HANDLED);
250 }
251
252 /**
253 * arm_tmr_probe - timer probe routine
254 * @dev: new device
255 *
256 * The probe function returns success when probed with the fdt compatible
257 * string set to "arm,mpcore-timers".
258 *
259 * RETURNS
260 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO.
261 */
262 static int
arm_tmr_probe(device_t dev)263 arm_tmr_probe(device_t dev)
264 {
265
266 if (!ofw_bus_status_okay(dev))
267 return (ENXIO);
268
269 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE)
270 return (ENXIO);
271
272 device_set_desc(dev, "ARM MPCore Timers");
273 return (BUS_PROBE_DEFAULT);
274 }
275
276 static int
attach_tc(struct arm_tmr_softc * sc)277 attach_tc(struct arm_tmr_softc *sc)
278 {
279 int rid;
280
281 if (arm_tmr_tc != NULL)
282 return (EBUSY);
283
284 rid = sc->memrid;
285 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
286 RF_ACTIVE);
287 if (sc->gbl_mem == NULL) {
288 device_printf(sc->dev, "could not allocate gbl mem resources\n");
289 return (ENXIO);
290 }
291 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000);
292
293 arm_tmr_timecount.tc_frequency = sc->clkfreq;
294 arm_tmr_timecount.tc_priv = sc;
295 tc_init(&arm_tmr_timecount);
296 arm_tmr_tc = &arm_tmr_timecount;
297
298 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
299
300 return (0);
301 }
302
303 static int
attach_et(struct arm_tmr_softc * sc)304 attach_et(struct arm_tmr_softc *sc)
305 {
306 void *ihl;
307 int irid, mrid;
308
309 if (arm_tmr_et != NULL)
310 return (EBUSY);
311
312 mrid = sc->memrid;
313 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid,
314 RF_ACTIVE);
315 if (sc->prv_mem == NULL) {
316 device_printf(sc->dev, "could not allocate prv mem resources\n");
317 return (ENXIO);
318 }
319 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000);
320
321 irid = sc->irqrid;
322 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE);
323 if (sc->prv_irq == NULL) {
324 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
325 device_printf(sc->dev, "could not allocate prv irq resources\n");
326 return (ENXIO);
327 }
328
329 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr,
330 NULL, sc, &ihl) != 0) {
331 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
332 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq);
333 device_printf(sc->dev, "unable to setup the et irq handler.\n");
334 return (ENXIO);
335 }
336
337 /*
338 * Setup and register the eventtimer. Most event timers set their min
339 * and max period values to some value calculated from the clock
340 * frequency. We might not know yet what our runtime clock frequency
341 * will be, so we just use some safe values. A max of 2 seconds ensures
342 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
343 * we won't overflow our 32-bit timer count register. A min of 20
344 * nanoseconds is pretty much completely arbitrary.
345 */
346 sc->et.et_name = "MPCore";
347 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
348 sc->et.et_quality = 1000;
349 sc->et.et_frequency = sc->clkfreq;
350 sc->et.et_min_period = nstosbt(20);
351 sc->et.et_max_period = 2 * SBT_1S;
352 sc->et.et_start = arm_tmr_start;
353 sc->et.et_stop = arm_tmr_stop;
354 sc->et.et_priv = sc;
355 et_register(&sc->et);
356 arm_tmr_et = &sc->et;
357
358 return (0);
359 }
360
361 /**
362 * arm_tmr_attach - attaches the timer to the simplebus
363 * @dev: new device
364 *
365 * Reserves memory and interrupt resources, stores the softc structure
366 * globally and registers both the timecount and eventtimer objects.
367 *
368 * RETURNS
369 * Zero on success or ENXIO if an error occuried.
370 */
371 static int
arm_tmr_attach(device_t dev)372 arm_tmr_attach(device_t dev)
373 {
374 struct arm_tmr_softc *sc;
375 phandle_t node;
376 pcell_t clock;
377 int et_err, tc_err, tmrtype;
378
379 sc = device_get_softc(dev);
380 sc->dev = dev;
381
382 if (arm_tmr_freq_varies) {
383 sc->clkfreq = arm_tmr_freq;
384 } else {
385 if (arm_tmr_freq != 0) {
386 sc->clkfreq = arm_tmr_freq;
387 } else {
388 /* Get the base clock frequency */
389 node = ofw_bus_get_node(dev);
390 if ((OF_getencprop(node, "clock-frequency", &clock,
391 sizeof(clock))) <= 0) {
392 device_printf(dev, "missing clock-frequency "
393 "attribute in FDT\n");
394 return (ENXIO);
395 }
396 sc->clkfreq = clock;
397 }
398 }
399
400 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
401 tc_err = ENXIO;
402 et_err = ENXIO;
403
404 /*
405 * If we're handling the global timer and it is fixed-frequency, set it
406 * up to use as a timecounter. If it's variable frequency it won't work
407 * as a timecounter. We also can't use it for DELAY(), so hopefully the
408 * platform provides its own implementation. If it doesn't, ours will
409 * get used, but since the frequency isn't set, it will only use the
410 * bogus loop counter.
411 */
412 if (tmrtype & TMR_GBL) {
413 if (!arm_tmr_freq_varies)
414 tc_err = attach_tc(sc);
415 else if (bootverbose)
416 device_printf(sc->dev,
417 "not using variable-frequency device as timecounter\n");
418 sc->memrid++;
419 sc->irqrid++;
420 }
421
422 /* If we are handling the private timer, set it up as an eventtimer. */
423 if (tmrtype & TMR_PRV) {
424 et_err = attach_et(sc);
425 }
426
427 /*
428 * If we didn't successfully set up a timecounter or eventtimer then we
429 * didn't actually attach at all, return error.
430 */
431 if (tc_err != 0 && et_err != 0) {
432 return (ENXIO);
433 }
434
435 #ifdef PLATFORM
436 /*
437 * We can register as the DELAY() implementation only if we successfully
438 * set up the global timer.
439 */
440 if (tc_err == 0)
441 arm_set_delay(arm_tmr_delay, sc);
442 #endif
443
444 return (0);
445 }
446
447 static device_method_t arm_tmr_methods[] = {
448 DEVMETHOD(device_probe, arm_tmr_probe),
449 DEVMETHOD(device_attach, arm_tmr_attach),
450 { 0, 0 }
451 };
452
453 static driver_t arm_tmr_driver = {
454 "mp_tmr",
455 arm_tmr_methods,
456 sizeof(struct arm_tmr_softc),
457 };
458
459 EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, 0, 0,
460 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
461 EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, 0, 0,
462 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
463
464 /*
465 * Handle a change in clock frequency. The mpcore timer runs at half the CPU
466 * frequency. When the CPU frequency changes due to power-saving or thermal
467 * management, the platform-specific code that causes the frequency change calls
468 * this routine to inform the clock driver, and we in turn inform the event
469 * timer system, which actually updates the value in et->frequency for us and
470 * reschedules the current event(s) in a way that's atomic with respect to
471 * start/stop/intr code that may be running on various CPUs at the time of the
472 * call.
473 *
474 * This routine can also be called by a platform's early init code. If the
475 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code
476 * to register as an eventtimer, but not a timecounter. If the value passed in
477 * is any other non-zero value it is used as the fixed frequency for the timer.
478 */
479 void
arm_tmr_change_frequency(uint64_t newfreq)480 arm_tmr_change_frequency(uint64_t newfreq)
481 {
482
483 if (newfreq == ARM_TMR_FREQUENCY_VARIES) {
484 arm_tmr_freq_varies = true;
485 return;
486 }
487
488 arm_tmr_freq = newfreq;
489 if (arm_tmr_et != NULL)
490 et_change_frequency(arm_tmr_et, newfreq);
491 }
492
493 static void
arm_tmr_delay(int usec,void * arg)494 arm_tmr_delay(int usec, void *arg)
495 {
496 struct arm_tmr_softc *sc = arg;
497 int32_t counts_per_usec;
498 int32_t counts;
499 uint32_t first, last;
500
501 /* Get the number of times to count */
502 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
503
504 /*
505 * Clamp the timeout at a maximum value (about 32 seconds with
506 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
507 * near that length of time and if they are, they should be hung
508 * out to dry.
509 */
510 if (usec >= (0x80000000U / counts_per_usec))
511 counts = (0x80000000U / counts_per_usec) - 1;
512 else
513 counts = usec * counts_per_usec;
514
515 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
516
517 while (counts > 0) {
518 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
519 counts -= (int32_t)(last - first);
520 first = last;
521 }
522 }
523
524 #ifndef PLATFORM
525 /**
526 * DELAY - Delay for at least usec microseconds.
527 * @usec: number of microseconds to delay by
528 *
529 * This function is called all over the kernel and is suppose to provide a
530 * consistent delay. This function may also be called before the console
531 * is setup so no printf's can be called here.
532 *
533 * RETURNS:
534 * nothing
535 */
536 void
DELAY(int usec)537 DELAY(int usec)
538 {
539 struct arm_tmr_softc *sc;
540 int32_t counts;
541
542 TSENTER();
543 /* Check the timers are setup, if not just use a for loop for the meantime */
544 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) {
545 for (; usec > 0; usec--)
546 for (counts = 200; counts > 0; counts--)
547 cpufunc_nullop(); /* Prevent gcc from optimizing
548 * out the loop
549 */
550 } else {
551 sc = arm_tmr_tc->tc_priv;
552 arm_tmr_delay(usec, sc);
553 }
554 TSEXIT();
555 }
556 #endif
557