1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/pmc.h> 33 #include <sys/pmckern.h> 34 35 #include <machine/pmc_mdep.h> 36 #include <machine/cpu.h> 37 #include <machine/machdep.h> 38 39 #include "opt_acpi.h" 40 41 static int arm64_npmcs; 42 43 struct arm64_event_code_map { 44 enum pmc_event pe_ev; 45 uint8_t pe_code; 46 }; 47 48 /* 49 * Per-processor information. 50 */ 51 struct arm64_cpu { 52 struct pmc_hw *pc_arm64pmcs; 53 }; 54 55 static struct arm64_cpu **arm64_pcpu; 56 57 /* 58 * Interrupt Enable Set Register 59 */ 60 static __inline void 61 arm64_interrupt_enable(uint32_t pmc) 62 { 63 uint32_t reg; 64 65 reg = (1 << pmc); 66 WRITE_SPECIALREG(pmintenset_el1, reg); 67 68 isb(); 69 } 70 71 /* 72 * Interrupt Clear Set Register 73 */ 74 static __inline void 75 arm64_interrupt_disable(uint32_t pmc) 76 { 77 uint32_t reg; 78 79 reg = (1 << pmc); 80 WRITE_SPECIALREG(pmintenclr_el1, reg); 81 82 isb(); 83 } 84 85 /* 86 * Counter Set Enable Register 87 */ 88 static __inline void 89 arm64_counter_enable(unsigned int pmc) 90 { 91 uint32_t reg; 92 93 reg = (1 << pmc); 94 WRITE_SPECIALREG(pmcntenset_el0, reg); 95 96 isb(); 97 } 98 99 /* 100 * Counter Clear Enable Register 101 */ 102 static __inline void 103 arm64_counter_disable(unsigned int pmc) 104 { 105 uint32_t reg; 106 107 reg = (1 << pmc); 108 WRITE_SPECIALREG(pmcntenclr_el0, reg); 109 110 isb(); 111 } 112 113 /* 114 * Performance Monitors Control Register 115 */ 116 static uint32_t 117 arm64_pmcr_read(void) 118 { 119 uint32_t reg; 120 121 reg = READ_SPECIALREG(pmcr_el0); 122 123 return (reg); 124 } 125 126 static void 127 arm64_pmcr_write(uint32_t reg) 128 { 129 130 WRITE_SPECIALREG(pmcr_el0, reg); 131 132 isb(); 133 } 134 135 /* 136 * Performance Count Register N 137 */ 138 static uint32_t 139 arm64_pmcn_read(unsigned int pmc) 140 { 141 142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 143 144 WRITE_SPECIALREG(pmselr_el0, pmc); 145 146 isb(); 147 148 return (READ_SPECIALREG(pmxevcntr_el0)); 149 } 150 151 static void 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 153 { 154 155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 156 157 WRITE_SPECIALREG(pmselr_el0, pmc); 158 WRITE_SPECIALREG(pmxevcntr_el0, reg); 159 160 isb(); 161 } 162 163 static int 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 165 const struct pmc_op_pmcallocate *a) 166 { 167 uint64_t config; 168 enum pmc_event pe; 169 170 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 171 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 172 KASSERT(ri >= 0 && ri < arm64_npmcs, 173 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 174 175 if (a->pm_class != PMC_CLASS_ARMV8) { 176 return (EINVAL); 177 } 178 pe = a->pm_ev; 179 180 if ((a->pm_flags & PMC_F_EV_PMU) != 0) { 181 config = a->pm_md.pm_md_config; 182 } else { 183 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 184 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 185 return (EINVAL); 186 } 187 188 switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) { 189 case PMC_CAP_SYSTEM: 190 /* Exclude EL0 */ 191 config |= PMEVTYPER_U; 192 if (in_vhe()) { 193 /* If in VHE we need to include EL2 and exclude EL1 */ 194 config |= PMEVTYPER_NSH | PMEVTYPER_P; 195 } 196 break; 197 case PMC_CAP_USER: 198 /* Exclude EL1 */ 199 config |= PMEVTYPER_P; 200 /* Exclude EL2 */ 201 config &= ~PMEVTYPER_NSH; 202 break; 203 default: 204 /* 205 * Trace both USER and SYSTEM if none are specified 206 * (default setting) or if both flags are specified 207 * (user explicitly requested both qualifiers). 208 */ 209 if (in_vhe()) { 210 /* If in VHE we need to include EL2 */ 211 config |= PMEVTYPER_NSH; 212 } 213 break; 214 } 215 216 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 217 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%lx", ri, 218 config); 219 220 return (0); 221 } 222 223 224 static int 225 arm64_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 226 { 227 pmc_value_t tmp; 228 register_t s; 229 int reg; 230 231 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 232 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 233 KASSERT(ri >= 0 && ri < arm64_npmcs, 234 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 235 236 /* 237 * Ensure we don't get interrupted while updating the overflow count. 238 */ 239 s = intr_disable(); 240 tmp = arm64_pmcn_read(ri); 241 reg = (1 << ri); 242 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 243 /* Clear Overflow Flag */ 244 WRITE_SPECIALREG(pmovsclr_el0, reg); 245 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 246 247 /* Reread counter in case we raced. */ 248 tmp = arm64_pmcn_read(ri); 249 } 250 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 251 intr_restore(s); 252 253 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 254 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 255 /* 256 * Clamp value to 0 if the counter just overflowed, 257 * otherwise the returned reload count would wrap to a 258 * huge value. 259 */ 260 if ((tmp & (1ull << 63)) == 0) 261 tmp = 0; 262 else 263 tmp = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 264 } 265 *v = tmp; 266 267 return (0); 268 } 269 270 static int 271 arm64_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 272 { 273 274 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 275 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 276 KASSERT(ri >= 0 && ri < arm64_npmcs, 277 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 278 279 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 280 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 281 282 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 283 284 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 285 arm64_pmcn_write(ri, v); 286 287 return (0); 288 } 289 290 static int 291 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 292 { 293 struct pmc_hw *phw; 294 295 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 296 297 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 298 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 299 KASSERT(ri >= 0 && ri < arm64_npmcs, 300 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 301 302 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 303 304 KASSERT(pm == NULL || phw->phw_pmc == NULL, 305 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 306 __LINE__, pm, phw->phw_pmc)); 307 308 phw->phw_pmc = pm; 309 310 return (0); 311 } 312 313 static int 314 arm64_start_pmc(int cpu, int ri, struct pmc *pm) 315 { 316 uint64_t config; 317 318 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 319 320 /* 321 * Configure the event selection. 322 */ 323 WRITE_SPECIALREG(pmselr_el0, ri); 324 WRITE_SPECIALREG(pmxevtyper_el0, config); 325 326 isb(); 327 328 /* 329 * Enable the PMC. 330 */ 331 arm64_interrupt_enable(ri); 332 arm64_counter_enable(ri); 333 334 return (0); 335 } 336 337 static int 338 arm64_stop_pmc(int cpu, int ri, struct pmc *pm __unused) 339 { 340 /* 341 * Disable the PMCs. 342 */ 343 arm64_counter_disable(ri); 344 arm64_interrupt_disable(ri); 345 346 return (0); 347 } 348 349 static int 350 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 351 { 352 struct pmc_hw *phw __diagused; 353 354 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 355 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 356 KASSERT(ri >= 0 && ri < arm64_npmcs, 357 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 358 359 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 360 KASSERT(phw->phw_pmc == NULL, 361 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 362 363 return (0); 364 } 365 366 static int 367 arm64_intr(struct trapframe *tf) 368 { 369 int retval, ri; 370 struct pmc *pm; 371 int error; 372 int reg, cpu; 373 374 cpu = curcpu; 375 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 376 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 377 378 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 379 TRAPF_USERMODE(tf)); 380 381 retval = 0; 382 383 for (ri = 0; ri < arm64_npmcs; ri++) { 384 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 385 if (pm == NULL) 386 continue; 387 /* Check if counter is overflowed */ 388 reg = (1 << ri); 389 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 390 continue; 391 /* Clear Overflow Flag */ 392 WRITE_SPECIALREG(pmovsclr_el0, reg); 393 394 isb(); 395 396 retval = 1; /* Found an interrupting PMC. */ 397 398 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 399 400 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 401 continue; 402 403 if (pm->pm_state != PMC_STATE_RUNNING) 404 continue; 405 406 error = pmc_process_interrupt(PMC_HR, pm, tf); 407 if (error) 408 arm64_stop_pmc(cpu, ri, pm); 409 410 /* Reload sampling count */ 411 arm64_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount); 412 } 413 414 return (retval); 415 } 416 417 static int 418 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 419 { 420 struct pmc_hw *phw; 421 422 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 423 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 424 KASSERT(ri >= 0 && ri < arm64_npmcs, 425 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 426 427 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 428 429 snprintf(pi->pm_name, sizeof(pi->pm_name), "ARMV8-%d", ri); 430 pi->pm_class = PMC_CLASS_ARMV8; 431 432 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 433 pi->pm_enabled = TRUE; 434 *ppmc = phw->phw_pmc; 435 } else { 436 pi->pm_enabled = FALSE; 437 *ppmc = NULL; 438 } 439 440 return (0); 441 } 442 443 static int 444 arm64_get_config(int cpu, int ri, struct pmc **ppm) 445 { 446 447 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 448 449 return (0); 450 } 451 452 static int 453 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 454 { 455 struct arm64_cpu *pac; 456 struct pmc_hw *phw; 457 struct pmc_cpu *pc; 458 uint64_t pmcr; 459 int first_ri; 460 int i; 461 462 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 463 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 464 PMCDBG0(MDP, INI, 1, "arm64-pcpu-init"); 465 466 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 467 M_WAITOK | M_ZERO); 468 469 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 470 M_PMC, M_WAITOK | M_ZERO); 471 pc = pmc_pcpu[cpu]; 472 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 473 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 474 475 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 476 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 477 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 478 phw->phw_pmc = NULL; 479 pc->pc_hwpmcs[i + first_ri] = phw; 480 } 481 482 /* 483 * Disable all counters and overflow interrupts. Upon reset they are in 484 * an undefined state. 485 * 486 * Don't issue an isb here, just wait for the one in arm64_pmcr_write() 487 * to make the writes visible. 488 */ 489 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); 490 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); 491 492 /* Enable unit */ 493 pmcr = arm64_pmcr_read(); 494 pmcr |= PMCR_E; 495 arm64_pmcr_write(pmcr); 496 497 return (0); 498 } 499 500 static int 501 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 502 { 503 uint32_t pmcr; 504 505 PMCDBG0(MDP, INI, 1, "arm64-pcpu-fini"); 506 507 pmcr = arm64_pmcr_read(); 508 pmcr &= ~PMCR_E; 509 arm64_pmcr_write(pmcr); 510 511 free(arm64_pcpu[cpu]->pc_arm64pmcs, M_PMC); 512 free(arm64_pcpu[cpu], M_PMC); 513 arm64_pcpu[cpu] = NULL; 514 515 return (0); 516 } 517 518 struct pmc_mdep * 519 pmc_arm64_initialize(void) 520 { 521 struct pmc_mdep *pmc_mdep; 522 struct pmc_classdep *pcd; 523 int classes, idcode, impcode; 524 int reg; 525 uint64_t midr; 526 527 reg = arm64_pmcr_read(); 528 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 529 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 530 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 531 532 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 533 534 /* 535 * Write the CPU model to kern.hwpmc.cpuid. 536 * 537 * We zero the variant and revision fields. 538 * 539 * TODO: how to handle differences between cores due to big.LITTLE? 540 * For now, just use MIDR from CPU 0. 541 */ 542 midr = (uint64_t)(pcpu_find(0)->pc_midr); 543 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 544 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 545 546 /* 547 * Allocate space for pointers to PMC HW descriptors and for 548 * the MDEP structure used by MI code. 549 */ 550 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 551 M_PMC, M_WAITOK | M_ZERO); 552 553 /* One AArch64 CPU class */ 554 classes = 1; 555 556 #ifdef DEV_ACPI 557 /* Query presence of optional classes and set max class. */ 558 if (pmc_cmn600_nclasses() > 0) 559 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_CMN600); 560 if (pmc_dmc620_nclasses() > 0) 561 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_DMC620_C); 562 #endif 563 564 pmc_mdep = pmc_mdep_alloc(classes); 565 566 switch(impcode) { 567 case PMCR_IMP_ARM: 568 switch (idcode) { 569 case PMCR_IDCODE_CORTEX_A76: 570 case PMCR_IDCODE_NEOVERSE_N1: 571 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 572 break; 573 case PMCR_IDCODE_CORTEX_A57: 574 case PMCR_IDCODE_CORTEX_A72: 575 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 576 break; 577 default: 578 case PMCR_IDCODE_CORTEX_A53: 579 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 580 break; 581 } 582 break; 583 default: 584 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 585 break; 586 } 587 588 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 589 pcd->pcd_caps = ARMV8_PMC_CAPS; 590 pcd->pcd_class = PMC_CLASS_ARMV8; 591 pcd->pcd_num = arm64_npmcs; 592 pcd->pcd_ri = pmc_mdep->pmd_npmc; 593 pcd->pcd_width = 32; 594 595 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 596 pcd->pcd_config_pmc = arm64_config_pmc; 597 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 598 pcd->pcd_pcpu_init = arm64_pcpu_init; 599 pcd->pcd_describe = arm64_describe; 600 pcd->pcd_get_config = arm64_get_config; 601 pcd->pcd_read_pmc = arm64_read_pmc; 602 pcd->pcd_release_pmc = arm64_release_pmc; 603 pcd->pcd_start_pmc = arm64_start_pmc; 604 pcd->pcd_stop_pmc = arm64_stop_pmc; 605 pcd->pcd_write_pmc = arm64_write_pmc; 606 607 pmc_mdep->pmd_intr = arm64_intr; 608 pmc_mdep->pmd_npmc += arm64_npmcs; 609 610 #ifdef DEV_ACPI 611 if (pmc_cmn600_nclasses() > 0) 612 pmc_cmn600_initialize(pmc_mdep); 613 if (pmc_dmc620_nclasses() > 0) { 614 pmc_dmc620_initialize_cd2(pmc_mdep); 615 pmc_dmc620_initialize_c(pmc_mdep); 616 } 617 #endif 618 619 return (pmc_mdep); 620 } 621 622 void 623 pmc_arm64_finalize(struct pmc_mdep *md) 624 { 625 PMCDBG0(MDP, INI, 1, "arm64-finalize"); 626 627 for (int i = 0; i < pmc_cpu_max(); i++) 628 KASSERT(arm64_pcpu[i] == NULL, 629 ("[arm64,%d] non-null pcpu cpu %d", __LINE__, i)); 630 631 free(arm64_pcpu, M_PMC); 632 } 633