1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_dpm.h"
29 #include "amdgpu_smu.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_atombios.h"
33 #include "smu_v11_0.h"
34 #include "smu11_driver_if_arcturus.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "arcturus_ppt.h"
38 #include "smu_v11_0_pptable.h"
39 #include "arcturus_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/i2c.h>
46 #include <linux/pci.h>
47 #include "amdgpu_ras.h"
48 #include "smu_cmn.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
61 [smu_feature] = {1, (arcturus_feature)}
62
63 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
64 #define SMU_FEATURES_LOW_SHIFT 0
65 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
66 #define SMU_FEATURES_HIGH_SHIFT 32
67
68 static const struct smu_feature_bits arcturus_dpm_features = {
69 .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
70 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
71 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
72 SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
73 SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT),
74 SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
75 SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT) }
76 };
77
78 #define smnPCIE_ESM_CTRL 0x111003D0
79
80 #define mmCG_FDO_CTRL0_ARCT 0x8B
81 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0
82
83 #define mmCG_FDO_CTRL1_ARCT 0x8C
84 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0
85
86 #define mmCG_FDO_CTRL2_ARCT 0x8D
87 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0
88
89 #define mmCG_TACH_CTRL_ARCT 0x8E
90 #define mmCG_TACH_CTRL_ARCT_BASE_IDX 0
91
92 #define mmCG_TACH_STATUS_ARCT 0x8F
93 #define mmCG_TACH_STATUS_ARCT_BASE_IDX 0
94
95 #define mmCG_THERMAL_STATUS_ARCT 0x90
96 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0
97
98 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
99 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
100 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
101 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
102 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
103 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
104 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
105 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
106 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
107 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
108 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
109 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
110 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0),
111 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0),
112 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
113 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
114 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
115 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
116 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
117 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
118 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
119 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
120 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
121 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
122 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
123 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
124 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
132 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
133 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0),
134 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
135 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
136 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
137 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
138 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0),
139 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0),
140 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0),
141 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0),
142 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
143 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
144 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
145 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0),
146 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0),
147 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
148 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
149 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
150 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
151 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
152 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
153 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0),
154 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
155 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
156 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
157 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1),
158 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1),
159 MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0),
160 };
161
162 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
163 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
164 CLK_MAP(SCLK, PPCLK_GFXCLK),
165 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
166 CLK_MAP(FCLK, PPCLK_FCLK),
167 CLK_MAP(UCLK, PPCLK_UCLK),
168 CLK_MAP(MCLK, PPCLK_UCLK),
169 CLK_MAP(DCLK, PPCLK_DCLK),
170 CLK_MAP(VCLK, PPCLK_VCLK),
171 };
172
173 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
174 FEA_MAP(DPM_PREFETCHER),
175 FEA_MAP(DPM_GFXCLK),
176 FEA_MAP(DPM_UCLK),
177 FEA_MAP(DPM_SOCCLK),
178 FEA_MAP(DPM_FCLK),
179 FEA_MAP(DPM_MP0CLK),
180 FEA_MAP(DPM_XGMI),
181 FEA_MAP(DS_GFXCLK),
182 FEA_MAP(DS_SOCCLK),
183 FEA_MAP(DS_LCLK),
184 FEA_MAP(DS_FCLK),
185 FEA_MAP(DS_UCLK),
186 FEA_MAP(GFX_ULV),
187 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
188 FEA_MAP(RSMU_SMN_CG),
189 FEA_MAP(WAFL_CG),
190 FEA_MAP(PPT),
191 FEA_MAP(TDC),
192 FEA_MAP(APCC_PLUS),
193 FEA_MAP(VR0HOT),
194 FEA_MAP(VR1HOT),
195 FEA_MAP(FW_CTF),
196 FEA_MAP(FAN_CONTROL),
197 FEA_MAP(THERMAL),
198 FEA_MAP(OUT_OF_BAND_MONITOR),
199 FEA_MAP(TEMP_DEPENDENT_VMIN),
200 };
201
202 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
203 TAB_MAP(PPTABLE),
204 TAB_MAP(AVFS),
205 TAB_MAP(AVFS_PSM_DEBUG),
206 TAB_MAP(AVFS_FUSE_OVERRIDE),
207 TAB_MAP(PMSTATUSLOG),
208 TAB_MAP(SMU_METRICS),
209 TAB_MAP(DRIVER_SMU_CONFIG),
210 TAB_MAP(OVERDRIVE),
211 TAB_MAP(I2C_COMMANDS),
212 TAB_MAP(ACTIVITY_MONITOR_COEFF),
213 };
214
215 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
216 PWR_MAP(AC),
217 PWR_MAP(DC),
218 };
219
220 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
224 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
226 };
227
228 static const uint8_t arcturus_throttler_map[] = {
229 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
230 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
231 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
232 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
233 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
234 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
235 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
236 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
237 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
238 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
239 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
240 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
241 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
242 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
243 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
244 [THROTTLER_VRHOT0_BIT] = (SMU_THROTTLER_VRHOT0_BIT),
245 [THROTTLER_VRHOT1_BIT] = (SMU_THROTTLER_VRHOT1_BIT),
246 };
247
arcturus_tables_init(struct smu_context * smu)248 static int arcturus_tables_init(struct smu_context *smu)
249 {
250 struct smu_table_context *smu_table = &smu->smu_table;
251 struct smu_table *tables = smu_table->tables;
252 int ret;
253
254 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
255 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
256
257 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
258 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
259
260 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
261 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
262
263 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
264 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
265
266 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
267 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
268 AMDGPU_GEM_DOMAIN_VRAM);
269
270 smu_table->metrics_table = kzalloc_obj(SmuMetrics_t);
271 if (!smu_table->metrics_table)
272 return -ENOMEM;
273 smu_table->metrics_time = 0;
274
275 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
276 sizeof(struct gpu_metrics_v1_3),
277 SMU_GPU_METRICS_CACHE_INTERVAL);
278 if (ret) {
279 kfree(smu_table->metrics_table);
280 return ret;
281 }
282
283 return 0;
284 }
285
arcturus_select_plpd_policy(struct smu_context * smu,int level)286 static int arcturus_select_plpd_policy(struct smu_context *smu, int level)
287 {
288 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
289 if (smu->smc_fw_version < 0x00361700) {
290 dev_err(smu->adev->dev,
291 "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
292 return -EINVAL;
293 }
294
295 if (level == XGMI_PLPD_DEFAULT)
296 return smu_cmn_send_smc_msg_with_param(
297 smu, SMU_MSG_GmiPwrDnControl, 1, NULL);
298 else if (level == XGMI_PLPD_DISALLOW)
299 return smu_cmn_send_smc_msg_with_param(
300 smu, SMU_MSG_GmiPwrDnControl, 0, NULL);
301 else
302 return -EINVAL;
303 }
304
arcturus_allocate_dpm_context(struct smu_context * smu)305 static int arcturus_allocate_dpm_context(struct smu_context *smu)
306 {
307 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
308 struct smu_dpm_policy *policy;
309
310 smu_dpm->dpm_context = kzalloc_obj(struct smu_11_0_dpm_context);
311 if (!smu_dpm->dpm_context)
312 return -ENOMEM;
313 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
314
315 smu_dpm->dpm_policies =
316 kzalloc_obj(struct smu_dpm_policy_ctxt);
317
318 if (!smu_dpm->dpm_policies)
319 return -ENOMEM;
320
321 policy = &(smu_dpm->dpm_policies->policies[0]);
322 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
323 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT);
324 policy->current_level = XGMI_PLPD_DEFAULT;
325 policy->set_policy = arcturus_select_plpd_policy;
326 smu_cmn_generic_plpd_policy_desc(policy);
327 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
328
329 return 0;
330 }
331
arcturus_init_smc_tables(struct smu_context * smu)332 static int arcturus_init_smc_tables(struct smu_context *smu)
333 {
334 int ret = 0;
335
336 ret = arcturus_tables_init(smu);
337 if (ret)
338 return ret;
339
340 ret = arcturus_allocate_dpm_context(smu);
341 if (ret)
342 return ret;
343
344 return smu_v11_0_init_smc_tables(smu);
345 }
346
347 static int
arcturus_init_allowed_features(struct smu_context * smu)348 arcturus_init_allowed_features(struct smu_context *smu)
349 {
350 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
351
352 return 0;
353 }
354
arcturus_set_default_dpm_table(struct smu_context * smu)355 static int arcturus_set_default_dpm_table(struct smu_context *smu)
356 {
357 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
358 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
359 struct smu_dpm_table *dpm_table = NULL;
360 int ret = 0;
361
362 /* socclk dpm table setup */
363 dpm_table = &dpm_context->dpm_tables.soc_table;
364 dpm_table->clk_type = SMU_SOCCLK;
365 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
366 ret = smu_v11_0_set_single_dpm_table(smu,
367 SMU_SOCCLK,
368 dpm_table);
369 if (ret)
370 return ret;
371 if (!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete)
372 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
373 } else {
374 dpm_table->count = 1;
375 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
376 dpm_table->dpm_levels[0].enabled = true;
377 }
378
379 /* gfxclk dpm table setup */
380 dpm_table = &dpm_context->dpm_tables.gfx_table;
381 dpm_table->clk_type = SMU_GFXCLK;
382 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
383 ret = smu_v11_0_set_single_dpm_table(smu,
384 SMU_GFXCLK,
385 dpm_table);
386 if (ret)
387 return ret;
388 if (!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete)
389 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
390 } else {
391 dpm_table->count = 1;
392 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
393 dpm_table->dpm_levels[0].enabled = true;
394 }
395
396 /* memclk dpm table setup */
397 dpm_table = &dpm_context->dpm_tables.uclk_table;
398 dpm_table->clk_type = SMU_UCLK;
399 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
400 ret = smu_v11_0_set_single_dpm_table(smu,
401 SMU_UCLK,
402 dpm_table);
403 if (ret)
404 return ret;
405 if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete)
406 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
407 } else {
408 dpm_table->count = 1;
409 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
410 dpm_table->dpm_levels[0].enabled = true;
411 }
412
413 /* fclk dpm table setup */
414 dpm_table = &dpm_context->dpm_tables.fclk_table;
415 dpm_table->clk_type = SMU_FCLK;
416 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
417 ret = smu_v11_0_set_single_dpm_table(smu,
418 SMU_FCLK,
419 dpm_table);
420 if (ret)
421 return ret;
422 if (!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete)
423 dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
424 } else {
425 dpm_table->count = 1;
426 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
427 dpm_table->dpm_levels[0].enabled = true;
428 }
429
430 /* XGMI PLPD is supported by 54.23.0 and onwards */
431 if (smu->smc_fw_version < 0x00361700) {
432 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
433
434 smu_dpm->dpm_policies->policy_mask &=
435 ~BIT(PP_PM_POLICY_XGMI_PLPD);
436 }
437
438 return 0;
439 }
440
arcturus_check_bxco_support(struct smu_context * smu)441 static void arcturus_check_bxco_support(struct smu_context *smu)
442 {
443 struct smu_table_context *table_context = &smu->smu_table;
444 struct smu_11_0_powerplay_table *powerplay_table =
445 table_context->power_play_table;
446 struct smu_baco_context *smu_baco = &smu->smu_baco;
447 struct amdgpu_device *adev = smu->adev;
448 uint32_t val;
449
450 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
451 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
452 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
453 smu_baco->platform_support =
454 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
455 false;
456 }
457 }
458
arcturus_check_fan_support(struct smu_context * smu)459 static void arcturus_check_fan_support(struct smu_context *smu)
460 {
461 struct smu_table_context *table_context = &smu->smu_table;
462 PPTable_t *pptable = table_context->driver_pptable;
463
464 /* No sort of fan control possible if PPTable has it disabled */
465 smu->adev->pm.no_fan =
466 !(pptable->FeaturesToRun[0] & FEATURE_FAN_CONTROL_MASK);
467 if (smu->adev->pm.no_fan)
468 dev_info_once(smu->adev->dev,
469 "PMFW based fan control disabled");
470 }
471
arcturus_check_powerplay_table(struct smu_context * smu)472 static int arcturus_check_powerplay_table(struct smu_context *smu)
473 {
474 struct smu_table_context *table_context = &smu->smu_table;
475 struct smu_11_0_powerplay_table *powerplay_table =
476 table_context->power_play_table;
477
478 arcturus_check_bxco_support(smu);
479 arcturus_check_fan_support(smu);
480
481 table_context->thermal_controller_type =
482 powerplay_table->thermal_controller_type;
483
484 return 0;
485 }
486
arcturus_store_powerplay_table(struct smu_context * smu)487 static int arcturus_store_powerplay_table(struct smu_context *smu)
488 {
489 struct smu_table_context *table_context = &smu->smu_table;
490 struct smu_11_0_powerplay_table *powerplay_table =
491 table_context->power_play_table;
492
493 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
494 sizeof(PPTable_t));
495
496 return 0;
497 }
498
arcturus_append_powerplay_table(struct smu_context * smu)499 static int arcturus_append_powerplay_table(struct smu_context *smu)
500 {
501 struct smu_table_context *table_context = &smu->smu_table;
502 PPTable_t *smc_pptable = table_context->driver_pptable;
503 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
504 int index, ret;
505
506 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
507 smc_dpm_info);
508
509 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
510 (uint8_t **)&smc_dpm_table);
511 if (ret)
512 return ret;
513
514 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
515 smc_dpm_table->table_header.format_revision,
516 smc_dpm_table->table_header.content_revision);
517
518 if ((smc_dpm_table->table_header.format_revision == 4) &&
519 (smc_dpm_table->table_header.content_revision == 6))
520 smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
521 smc_dpm_table, maxvoltagestepgfx);
522 return 0;
523 }
524
arcturus_setup_pptable(struct smu_context * smu)525 static int arcturus_setup_pptable(struct smu_context *smu)
526 {
527 int ret = 0;
528
529 ret = smu_v11_0_setup_pptable(smu);
530 if (ret)
531 return ret;
532
533 ret = arcturus_store_powerplay_table(smu);
534 if (ret)
535 return ret;
536
537 ret = arcturus_append_powerplay_table(smu);
538 if (ret)
539 return ret;
540
541 ret = arcturus_check_powerplay_table(smu);
542 if (ret)
543 return ret;
544
545 return ret;
546 }
547
arcturus_run_btc(struct smu_context * smu)548 static int arcturus_run_btc(struct smu_context *smu)
549 {
550 int ret = 0;
551
552 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
553 if (ret) {
554 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
555 return ret;
556 }
557
558 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
559 }
560
arcturus_populate_umd_state_clk(struct smu_context * smu)561 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
562 {
563 struct smu_11_0_dpm_context *dpm_context =
564 smu->smu_dpm.dpm_context;
565 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
566 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
567 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
568 struct smu_umd_pstate_table *pstate_table =
569 &smu->pstate_table;
570
571 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
572 pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);
573
574 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);
575 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);
576
577 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);
578 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);
579
580 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
581 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
582 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
583 pstate_table->gfxclk_pstate.standard =
584 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
585 pstate_table->uclk_pstate.standard =
586 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
587 pstate_table->socclk_pstate.standard =
588 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
589 } else {
590 pstate_table->gfxclk_pstate.standard =
591 pstate_table->gfxclk_pstate.min;
592 pstate_table->uclk_pstate.standard =
593 pstate_table->uclk_pstate.min;
594 pstate_table->socclk_pstate.standard =
595 pstate_table->socclk_pstate.min;
596 }
597
598 return 0;
599 }
600
arcturus_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)601 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
602 MetricsMember_t member,
603 uint32_t *value)
604 {
605 struct smu_table_context *smu_table = &smu->smu_table;
606 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
607 int ret = 0;
608
609 ret = smu_cmn_get_metrics_table(smu,
610 NULL,
611 false);
612 if (ret)
613 return ret;
614
615 switch (member) {
616 case METRICS_CURR_GFXCLK:
617 *value = metrics->CurrClock[PPCLK_GFXCLK];
618 break;
619 case METRICS_CURR_SOCCLK:
620 *value = metrics->CurrClock[PPCLK_SOCCLK];
621 break;
622 case METRICS_CURR_UCLK:
623 *value = metrics->CurrClock[PPCLK_UCLK];
624 break;
625 case METRICS_CURR_VCLK:
626 *value = metrics->CurrClock[PPCLK_VCLK];
627 break;
628 case METRICS_CURR_DCLK:
629 *value = metrics->CurrClock[PPCLK_DCLK];
630 break;
631 case METRICS_CURR_FCLK:
632 *value = metrics->CurrClock[PPCLK_FCLK];
633 break;
634 case METRICS_AVERAGE_GFXCLK:
635 *value = metrics->AverageGfxclkFrequency;
636 break;
637 case METRICS_AVERAGE_SOCCLK:
638 *value = metrics->AverageSocclkFrequency;
639 break;
640 case METRICS_AVERAGE_UCLK:
641 *value = metrics->AverageUclkFrequency;
642 break;
643 case METRICS_AVERAGE_VCLK:
644 *value = metrics->AverageVclkFrequency;
645 break;
646 case METRICS_AVERAGE_DCLK:
647 *value = metrics->AverageDclkFrequency;
648 break;
649 case METRICS_AVERAGE_GFXACTIVITY:
650 *value = metrics->AverageGfxActivity;
651 break;
652 case METRICS_AVERAGE_MEMACTIVITY:
653 *value = metrics->AverageUclkActivity;
654 break;
655 case METRICS_AVERAGE_VCNACTIVITY:
656 *value = metrics->VcnActivityPercentage;
657 break;
658 case METRICS_AVERAGE_SOCKETPOWER:
659 *value = metrics->AverageSocketPower << 8;
660 break;
661 case METRICS_TEMPERATURE_EDGE:
662 *value = metrics->TemperatureEdge *
663 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
664 break;
665 case METRICS_TEMPERATURE_HOTSPOT:
666 *value = metrics->TemperatureHotspot *
667 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
668 break;
669 case METRICS_TEMPERATURE_MEM:
670 *value = metrics->TemperatureHBM *
671 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
672 break;
673 case METRICS_TEMPERATURE_VRGFX:
674 *value = metrics->TemperatureVrGfx *
675 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
676 break;
677 case METRICS_TEMPERATURE_VRSOC:
678 *value = metrics->TemperatureVrSoc *
679 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
680 break;
681 case METRICS_TEMPERATURE_VRMEM:
682 *value = metrics->TemperatureVrMem *
683 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
684 break;
685 case METRICS_THROTTLER_STATUS:
686 *value = metrics->ThrottlerStatus;
687 break;
688 case METRICS_CURR_FANSPEED:
689 *value = metrics->CurrFanSpeed;
690 break;
691 default:
692 *value = UINT_MAX;
693 break;
694 }
695
696 return ret;
697 }
698
arcturus_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)699 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
700 enum smu_clk_type clk_type,
701 uint32_t *value)
702 {
703 MetricsMember_t member_type;
704 int clk_id = 0;
705
706 if (!value)
707 return -EINVAL;
708
709 clk_id = smu_cmn_to_asic_specific_index(smu,
710 CMN2ASIC_MAPPING_CLK,
711 clk_type);
712 if (clk_id < 0)
713 return -EINVAL;
714
715 switch (clk_id) {
716 case PPCLK_GFXCLK:
717 /*
718 * CurrClock[clk_id] can provide accurate
719 * output only when the dpm feature is enabled.
720 * We can use Average_* for dpm disabled case.
721 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
722 */
723 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
724 member_type = METRICS_CURR_GFXCLK;
725 else
726 member_type = METRICS_AVERAGE_GFXCLK;
727 break;
728 case PPCLK_UCLK:
729 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
730 member_type = METRICS_CURR_UCLK;
731 else
732 member_type = METRICS_AVERAGE_UCLK;
733 break;
734 case PPCLK_SOCCLK:
735 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
736 member_type = METRICS_CURR_SOCCLK;
737 else
738 member_type = METRICS_AVERAGE_SOCCLK;
739 break;
740 case PPCLK_VCLK:
741 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
742 member_type = METRICS_CURR_VCLK;
743 else
744 member_type = METRICS_AVERAGE_VCLK;
745 break;
746 case PPCLK_DCLK:
747 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
748 member_type = METRICS_CURR_DCLK;
749 else
750 member_type = METRICS_AVERAGE_DCLK;
751 break;
752 case PPCLK_FCLK:
753 member_type = METRICS_CURR_FCLK;
754 break;
755 default:
756 return -EINVAL;
757 }
758
759 return arcturus_get_smu_metrics_data(smu,
760 member_type,
761 value);
762 }
763
arcturus_emit_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf,int * offset)764 static int arcturus_emit_clk_levels(struct smu_context *smu,
765 enum smu_clk_type type, char *buf, int *offset)
766 {
767 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
768 struct smu_dpm_table *single_dpm_table;
769 struct smu_pcie_table *pcie_table;
770 uint32_t gen_speed, lane_width;
771 uint32_t cur_value = 0;
772 int ret = 0;
773 static const char attempt_string[] = "Attempt to get current";
774
775 if (amdgpu_ras_intr_triggered()) {
776 *offset += sysfs_emit_at(buf, *offset, "unavailable\n");
777 return -EBUSY;
778 }
779
780 switch (type) {
781 case SMU_SCLK:
782 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value);
783 if (ret) {
784 dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string);
785 return ret;
786 }
787 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
788 ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
789 cur_value, buf, offset);
790 if (ret < 0)
791 return ret;
792 break;
793
794 case SMU_MCLK:
795 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value);
796 if (ret) {
797 dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string);
798 return ret;
799 }
800 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
801 ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
802 cur_value, buf, offset);
803 if (ret < 0)
804 return ret;
805 break;
806
807 case SMU_SOCCLK:
808 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value);
809 if (ret) {
810 dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
811 return ret;
812 }
813 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
814 ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
815 cur_value, buf, offset);
816 if (ret < 0)
817 return ret;
818 break;
819
820 case SMU_FCLK:
821 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value);
822 if (ret) {
823 dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string);
824 return ret;
825 }
826 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
827 ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
828 cur_value, buf, offset);
829 if (ret < 0)
830 return ret;
831 break;
832
833 case SMU_VCLK:
834 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value);
835 if (ret) {
836 dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string);
837 return ret;
838 }
839 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
840 ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
841 cur_value, buf, offset);
842 if (ret < 0)
843 return ret;
844 break;
845
846 case SMU_DCLK:
847 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value);
848 if (ret) {
849 dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string);
850 return ret;
851 }
852 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
853 ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
854 cur_value, buf, offset);
855 if (ret < 0)
856 return ret;
857 break;
858
859 case SMU_PCIE:
860 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
861 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
862 pcie_table = &(dpm_context->dpm_tables.pcie_table);
863 /* Populate with current state - arcturus only has boot level lclk */
864 pcie_table->lclk_levels = 1;
865 pcie_table->pcie_gen[0] = gen_speed;
866 pcie_table->pcie_lane[0] = lane_width;
867 pcie_table->lclk_freq[0] =
868 smu->smu_table.boot_values.lclk / 100;
869 ret = smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed,
870 lane_width, buf, offset);
871 if (ret < 0)
872 return ret;
873 break;
874
875 default:
876 return -EINVAL;
877 }
878
879 return 0;
880 }
881
arcturus_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)882 static int arcturus_upload_dpm_level(struct smu_context *smu,
883 bool max,
884 uint32_t feature_mask,
885 uint32_t level)
886 {
887 struct smu_11_0_dpm_context *dpm_context =
888 smu->smu_dpm.dpm_context;
889 uint32_t freq;
890 int ret = 0;
891
892 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
893 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
894 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
895 ret = smu_cmn_send_smc_msg_with_param(smu,
896 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
897 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
898 NULL);
899 if (ret) {
900 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
901 max ? "max" : "min");
902 return ret;
903 }
904 }
905
906 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
907 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
908 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
909 ret = smu_cmn_send_smc_msg_with_param(smu,
910 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
911 (PPCLK_UCLK << 16) | (freq & 0xffff),
912 NULL);
913 if (ret) {
914 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
915 max ? "max" : "min");
916 return ret;
917 }
918 }
919
920 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
921 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
922 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
923 ret = smu_cmn_send_smc_msg_with_param(smu,
924 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
925 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
926 NULL);
927 if (ret) {
928 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
929 max ? "max" : "min");
930 return ret;
931 }
932 }
933
934 return ret;
935 }
936
arcturus_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)937 static int arcturus_force_clk_levels(struct smu_context *smu,
938 enum smu_clk_type type, uint32_t mask)
939 {
940 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
941 struct smu_dpm_table *single_dpm_table = NULL;
942 uint32_t soft_min_level, soft_max_level;
943 int ret = 0;
944
945 if ((smu->smc_fw_version >= 0x361200) &&
946 (smu->smc_fw_version <= 0x361a00)) {
947 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
948 "54.18 - 54.26(included) SMU firmwares\n");
949 return -EOPNOTSUPP;
950 }
951
952 soft_min_level = mask ? (ffs(mask) - 1) : 0;
953 soft_max_level = mask ? (fls(mask) - 1) : 0;
954
955 switch (type) {
956 case SMU_SCLK:
957 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
958 if (soft_max_level >= single_dpm_table->count) {
959 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
960 soft_max_level, single_dpm_table->count - 1);
961 ret = -EINVAL;
962 break;
963 }
964
965 ret = arcturus_upload_dpm_level(smu,
966 false,
967 FEATURE_DPM_GFXCLK_MASK,
968 soft_min_level);
969 if (ret) {
970 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
971 break;
972 }
973
974 ret = arcturus_upload_dpm_level(smu,
975 true,
976 FEATURE_DPM_GFXCLK_MASK,
977 soft_max_level);
978 if (ret)
979 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
980
981 break;
982
983 case SMU_MCLK:
984 case SMU_SOCCLK:
985 case SMU_FCLK:
986 /*
987 * Should not arrive here since Arcturus does not
988 * support mclk/socclk/fclk softmin/softmax settings
989 */
990 ret = -EINVAL;
991 break;
992
993 default:
994 break;
995 }
996
997 return ret;
998 }
999
arcturus_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1000 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1001 struct smu_temperature_range *range)
1002 {
1003 struct smu_table_context *table_context = &smu->smu_table;
1004 struct smu_11_0_powerplay_table *powerplay_table =
1005 table_context->power_play_table;
1006 PPTable_t *pptable = smu->smu_table.driver_pptable;
1007
1008 if (!range)
1009 return -EINVAL;
1010
1011 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1012
1013 range->max = pptable->TedgeLimit *
1014 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1015 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1016 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1017 range->hotspot_crit_max = pptable->ThotspotLimit *
1018 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1019 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1020 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1021 range->mem_crit_max = pptable->TmemLimit *
1022 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1023 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1024 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1025 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1026
1027 return 0;
1028 }
1029
arcturus_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1030 static int arcturus_read_sensor(struct smu_context *smu,
1031 enum amd_pp_sensors sensor,
1032 void *data, uint32_t *size)
1033 {
1034 struct smu_table_context *table_context = &smu->smu_table;
1035 PPTable_t *pptable = table_context->driver_pptable;
1036 int ret = 0;
1037
1038 if (amdgpu_ras_intr_triggered())
1039 return 0;
1040
1041 if (!data || !size)
1042 return -EINVAL;
1043
1044 switch (sensor) {
1045 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1046 *(uint32_t *)data = pptable->FanMaximumRpm;
1047 *size = 4;
1048 break;
1049 case AMDGPU_PP_SENSOR_MEM_LOAD:
1050 ret = arcturus_get_smu_metrics_data(smu,
1051 METRICS_AVERAGE_MEMACTIVITY,
1052 (uint32_t *)data);
1053 *size = 4;
1054 break;
1055 case AMDGPU_PP_SENSOR_GPU_LOAD:
1056 ret = arcturus_get_smu_metrics_data(smu,
1057 METRICS_AVERAGE_GFXACTIVITY,
1058 (uint32_t *)data);
1059 *size = 4;
1060 break;
1061 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1062 ret = arcturus_get_smu_metrics_data(smu,
1063 METRICS_AVERAGE_SOCKETPOWER,
1064 (uint32_t *)data);
1065 *size = 4;
1066 break;
1067 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1068 ret = arcturus_get_smu_metrics_data(smu,
1069 METRICS_TEMPERATURE_HOTSPOT,
1070 (uint32_t *)data);
1071 *size = 4;
1072 break;
1073 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1074 ret = arcturus_get_smu_metrics_data(smu,
1075 METRICS_TEMPERATURE_EDGE,
1076 (uint32_t *)data);
1077 *size = 4;
1078 break;
1079 case AMDGPU_PP_SENSOR_MEM_TEMP:
1080 ret = arcturus_get_smu_metrics_data(smu,
1081 METRICS_TEMPERATURE_MEM,
1082 (uint32_t *)data);
1083 *size = 4;
1084 break;
1085 case AMDGPU_PP_SENSOR_GFX_MCLK:
1086 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1087 /* the output clock frequency in 10K unit */
1088 *(uint32_t *)data *= 100;
1089 *size = 4;
1090 break;
1091 case AMDGPU_PP_SENSOR_GFX_SCLK:
1092 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1093 *(uint32_t *)data *= 100;
1094 *size = 4;
1095 break;
1096 case AMDGPU_PP_SENSOR_VDDGFX:
1097 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1098 *size = 4;
1099 break;
1100 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1101 default:
1102 ret = -EOPNOTSUPP;
1103 break;
1104 }
1105
1106 return ret;
1107 }
1108
arcturus_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1109 static int arcturus_set_fan_static_mode(struct smu_context *smu,
1110 uint32_t mode)
1111 {
1112 struct amdgpu_device *adev = smu->adev;
1113
1114 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1115 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1116 CG_FDO_CTRL2, TMIN, 0));
1117 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1118 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1119 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1120
1121 return 0;
1122 }
1123
arcturus_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1124 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1125 uint32_t *speed)
1126 {
1127 struct amdgpu_device *adev = smu->adev;
1128 uint32_t crystal_clock_freq = 2500;
1129 uint32_t tach_status;
1130 uint64_t tmp64;
1131 int ret = 0;
1132
1133 if (!speed)
1134 return -EINVAL;
1135
1136 switch (smu_v11_0_get_fan_control_mode(smu)) {
1137 case AMD_FAN_CTRL_AUTO:
1138 ret = arcturus_get_smu_metrics_data(smu,
1139 METRICS_CURR_FANSPEED,
1140 speed);
1141 break;
1142 default:
1143 /*
1144 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1145 * detected via register retrieving. To workaround this, we will
1146 * report the fan speed as 0 RPM if user just requested such.
1147 */
1148 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1149 && !smu->user_dpm_profile.fan_speed_rpm) {
1150 *speed = 0;
1151 return 0;
1152 }
1153
1154 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1155 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1156 if (tach_status) {
1157 do_div(tmp64, tach_status);
1158 *speed = (uint32_t)tmp64;
1159 } else {
1160 *speed = 0;
1161 }
1162
1163 break;
1164 }
1165
1166 return ret;
1167 }
1168
arcturus_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1169 static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1170 uint32_t speed)
1171 {
1172 struct amdgpu_device *adev = smu->adev;
1173 uint32_t duty100, duty;
1174 uint64_t tmp64;
1175
1176 speed = min_t(uint32_t, speed, 255);
1177
1178 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1179 CG_FDO_CTRL1, FMAX_DUTY100);
1180 if (!duty100)
1181 return -EINVAL;
1182
1183 tmp64 = (uint64_t)speed * duty100;
1184 do_div(tmp64, 255);
1185 duty = (uint32_t)tmp64;
1186
1187 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1188 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1189 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1190
1191 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1192 }
1193
arcturus_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1194 static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1195 uint32_t speed)
1196 {
1197 struct amdgpu_device *adev = smu->adev;
1198 /*
1199 * crystal_clock_freq used for fan speed rpm calculation is
1200 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1201 */
1202 uint32_t crystal_clock_freq = 2500;
1203 uint32_t tach_period;
1204
1205 if (!speed || speed > UINT_MAX/8)
1206 return -EINVAL;
1207
1208 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1209 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1210 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1211 CG_TACH_CTRL, TARGET_PERIOD,
1212 tach_period));
1213
1214 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1215 }
1216
arcturus_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1217 static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1218 uint32_t *speed)
1219 {
1220 struct amdgpu_device *adev = smu->adev;
1221 uint32_t duty100, duty;
1222 uint64_t tmp64;
1223
1224 /*
1225 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1226 * detected via register retrieving. To workaround this, we will
1227 * report the fan speed as 0 PWM if user just requested such.
1228 */
1229 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1230 && !smu->user_dpm_profile.fan_speed_pwm) {
1231 *speed = 0;
1232 return 0;
1233 }
1234
1235 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1236 CG_FDO_CTRL1, FMAX_DUTY100);
1237 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1238 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1239
1240 if (duty100) {
1241 tmp64 = (uint64_t)duty * 255;
1242 do_div(tmp64, duty100);
1243 *speed = min_t(uint32_t, tmp64, 255);
1244 } else {
1245 *speed = 0;
1246 }
1247
1248 return 0;
1249 }
1250
arcturus_get_fan_parameters(struct smu_context * smu)1251 static int arcturus_get_fan_parameters(struct smu_context *smu)
1252 {
1253 PPTable_t *pptable = smu->smu_table.driver_pptable;
1254
1255 smu->fan_max_rpm = pptable->FanMaximumRpm;
1256
1257 return 0;
1258 }
1259
arcturus_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1260 static int arcturus_get_power_limit(struct smu_context *smu,
1261 uint32_t *current_power_limit,
1262 uint32_t *default_power_limit,
1263 uint32_t *max_power_limit,
1264 uint32_t *min_power_limit)
1265 {
1266 PPTable_t *pptable = smu->smu_table.driver_pptable;
1267 uint32_t power_limit;
1268
1269 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1270 /* the last hope to figure out the ppt limit */
1271 if (!pptable) {
1272 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1273 return -EINVAL;
1274 }
1275 power_limit =
1276 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1277 }
1278
1279 if (current_power_limit)
1280 *current_power_limit = power_limit;
1281 if (default_power_limit)
1282 *default_power_limit = power_limit;
1283 if (max_power_limit)
1284 *max_power_limit = power_limit;
1285 /*
1286 * No lower bound is imposed on the limit. Any unreasonable limit set
1287 * will result in frequent throttling.
1288 */
1289 if (min_power_limit)
1290 *min_power_limit = 0;
1291
1292 return 0;
1293 }
1294
arcturus_get_power_profile_mode(struct smu_context * smu,char * buf)1295 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1296 char *buf)
1297 {
1298 DpmActivityMonitorCoeffInt_t activity_monitor;
1299 static const char *title[] = {
1300 "PROFILE_INDEX(NAME)",
1301 "CLOCK_TYPE(NAME)",
1302 "FPS",
1303 "UseRlcBusy",
1304 "MinActiveFreqType",
1305 "MinActiveFreq",
1306 "BoosterFreqType",
1307 "BoosterFreq",
1308 "PD_Data_limit_c",
1309 "PD_Data_error_coeff",
1310 "PD_Data_error_rate_coeff"};
1311 uint32_t i, size = 0;
1312 int16_t workload_type = 0;
1313 int result = 0;
1314
1315 if (!buf)
1316 return -EINVAL;
1317
1318 if (smu->smc_fw_version >= 0x360d00)
1319 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1320 title[0], title[1], title[2], title[3], title[4], title[5],
1321 title[6], title[7], title[8], title[9], title[10]);
1322 else
1323 size += sysfs_emit_at(buf, size, "%16s\n",
1324 title[0]);
1325
1326 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1327 /*
1328 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1329 * Not all profile modes are supported on arcturus.
1330 */
1331 workload_type = smu_cmn_to_asic_specific_index(smu,
1332 CMN2ASIC_MAPPING_WORKLOAD,
1333 i);
1334 if (workload_type < 0)
1335 continue;
1336
1337 if (smu->smc_fw_version >= 0x360d00) {
1338 result = smu_cmn_update_table(smu,
1339 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1340 workload_type,
1341 (void *)(&activity_monitor),
1342 false);
1343 if (result) {
1344 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1345 return result;
1346 }
1347 }
1348
1349 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1350 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1351
1352 if (smu->smc_fw_version >= 0x360d00) {
1353 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1354 " ",
1355 0,
1356 "GFXCLK",
1357 activity_monitor.Gfx_FPS,
1358 activity_monitor.Gfx_UseRlcBusy,
1359 activity_monitor.Gfx_MinActiveFreqType,
1360 activity_monitor.Gfx_MinActiveFreq,
1361 activity_monitor.Gfx_BoosterFreqType,
1362 activity_monitor.Gfx_BoosterFreq,
1363 activity_monitor.Gfx_PD_Data_limit_c,
1364 activity_monitor.Gfx_PD_Data_error_coeff,
1365 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1366
1367 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1368 " ",
1369 1,
1370 "UCLK",
1371 activity_monitor.Mem_FPS,
1372 activity_monitor.Mem_UseRlcBusy,
1373 activity_monitor.Mem_MinActiveFreqType,
1374 activity_monitor.Mem_MinActiveFreq,
1375 activity_monitor.Mem_BoosterFreqType,
1376 activity_monitor.Mem_BoosterFreq,
1377 activity_monitor.Mem_PD_Data_limit_c,
1378 activity_monitor.Mem_PD_Data_error_coeff,
1379 activity_monitor.Mem_PD_Data_error_rate_coeff);
1380 }
1381 }
1382
1383 return size;
1384 }
1385
1386 #define ARCTURUS_CUSTOM_PARAMS_COUNT 10
1387 #define ARCTURUS_CUSTOM_PARAMS_CLOCK_COUNT 2
1388 #define ARCTURUS_CUSTOM_PARAMS_SIZE (ARCTURUS_CUSTOM_PARAMS_CLOCK_COUNT * ARCTURUS_CUSTOM_PARAMS_COUNT * sizeof(long))
1389
arcturus_set_power_profile_mode_coeff(struct smu_context * smu,long * input)1390 static int arcturus_set_power_profile_mode_coeff(struct smu_context *smu,
1391 long *input)
1392 {
1393 DpmActivityMonitorCoeffInt_t activity_monitor;
1394 int ret, idx;
1395
1396 ret = smu_cmn_update_table(smu,
1397 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1398 WORKLOAD_PPLIB_CUSTOM_BIT,
1399 (void *)(&activity_monitor),
1400 false);
1401 if (ret) {
1402 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1403 return ret;
1404 }
1405
1406 idx = 0 * ARCTURUS_CUSTOM_PARAMS_COUNT;
1407 if (input[idx]) {
1408 /* Gfxclk */
1409 activity_monitor.Gfx_FPS = input[idx + 1];
1410 activity_monitor.Gfx_UseRlcBusy = input[idx + 2];
1411 activity_monitor.Gfx_MinActiveFreqType = input[idx + 3];
1412 activity_monitor.Gfx_MinActiveFreq = input[idx + 4];
1413 activity_monitor.Gfx_BoosterFreqType = input[idx + 5];
1414 activity_monitor.Gfx_BoosterFreq = input[idx + 6];
1415 activity_monitor.Gfx_PD_Data_limit_c = input[idx + 7];
1416 activity_monitor.Gfx_PD_Data_error_coeff = input[idx + 8];
1417 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[idx + 9];
1418 }
1419 idx = 1 * ARCTURUS_CUSTOM_PARAMS_COUNT;
1420 if (input[idx]) {
1421 /* Uclk */
1422 activity_monitor.Mem_FPS = input[idx + 1];
1423 activity_monitor.Mem_UseRlcBusy = input[idx + 2];
1424 activity_monitor.Mem_MinActiveFreqType = input[idx + 3];
1425 activity_monitor.Mem_MinActiveFreq = input[idx + 4];
1426 activity_monitor.Mem_BoosterFreqType = input[idx + 5];
1427 activity_monitor.Mem_BoosterFreq = input[idx + 6];
1428 activity_monitor.Mem_PD_Data_limit_c = input[idx + 7];
1429 activity_monitor.Mem_PD_Data_error_coeff = input[idx + 8];
1430 activity_monitor.Mem_PD_Data_error_rate_coeff = input[idx + 9];
1431 }
1432
1433 ret = smu_cmn_update_table(smu,
1434 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1435 WORKLOAD_PPLIB_CUSTOM_BIT,
1436 (void *)(&activity_monitor),
1437 true);
1438 if (ret) {
1439 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1440 return ret;
1441 }
1442
1443 return ret;
1444 }
1445
arcturus_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1446 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1447 u32 workload_mask,
1448 long *custom_params,
1449 u32 custom_params_max_idx)
1450 {
1451 u32 backend_workload_mask = 0;
1452 int ret, idx = -1, i;
1453
1454 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1455 &backend_workload_mask);
1456
1457 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
1458 if (smu->smc_fw_version < 0x360d00)
1459 return -EINVAL;
1460 if (!smu->custom_profile_params) {
1461 smu->custom_profile_params =
1462 kzalloc(ARCTURUS_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
1463 if (!smu->custom_profile_params)
1464 return -ENOMEM;
1465 }
1466 if (custom_params && custom_params_max_idx) {
1467 if (custom_params_max_idx != ARCTURUS_CUSTOM_PARAMS_COUNT)
1468 return -EINVAL;
1469 if (custom_params[0] >= ARCTURUS_CUSTOM_PARAMS_CLOCK_COUNT)
1470 return -EINVAL;
1471 idx = custom_params[0] * ARCTURUS_CUSTOM_PARAMS_COUNT;
1472 smu->custom_profile_params[idx] = 1;
1473 for (i = 1; i < custom_params_max_idx; i++)
1474 smu->custom_profile_params[idx + i] = custom_params[i];
1475 }
1476 ret = arcturus_set_power_profile_mode_coeff(smu,
1477 smu->custom_profile_params);
1478 if (ret) {
1479 if (idx != -1)
1480 smu->custom_profile_params[idx] = 0;
1481 return ret;
1482 }
1483 } else if (smu->custom_profile_params) {
1484 memset(smu->custom_profile_params, 0, ARCTURUS_CUSTOM_PARAMS_SIZE);
1485 }
1486
1487 ret = smu_cmn_send_smc_msg_with_param(smu,
1488 SMU_MSG_SetWorkloadMask,
1489 backend_workload_mask,
1490 NULL);
1491 if (ret) {
1492 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
1493 workload_mask);
1494 if (idx != -1)
1495 smu->custom_profile_params[idx] = 0;
1496 return ret;
1497 }
1498
1499 return ret;
1500 }
1501
arcturus_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1502 static int arcturus_set_performance_level(struct smu_context *smu,
1503 enum amd_dpm_forced_level level)
1504 {
1505 switch (level) {
1506 case AMD_DPM_FORCED_LEVEL_HIGH:
1507 case AMD_DPM_FORCED_LEVEL_LOW:
1508 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1509 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1510 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1511 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1512 if ((smu->smc_fw_version >= 0x361200) &&
1513 (smu->smc_fw_version <= 0x361a00)) {
1514 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1515 "54.18 - 54.26(included) SMU firmwares\n");
1516 return -EOPNOTSUPP;
1517 }
1518 break;
1519 default:
1520 break;
1521 }
1522
1523 return smu_v11_0_set_performance_level(smu, level);
1524 }
1525
arcturus_is_dpm_running(struct smu_context * smu)1526 static bool arcturus_is_dpm_running(struct smu_context *smu)
1527 {
1528 int ret = 0;
1529 struct smu_feature_bits feature_enabled;
1530
1531 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1532 if (ret)
1533 return false;
1534
1535 return smu_feature_bits_test_mask(&feature_enabled,
1536 arcturus_dpm_features.bits);
1537 }
1538
arcturus_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)1539 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,
1540 bool enable,
1541 int inst)
1542 {
1543 int ret = 0;
1544
1545 if (enable) {
1546 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1547 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
1548 if (ret) {
1549 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1550 return ret;
1551 }
1552 }
1553 } else {
1554 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1555 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
1556 if (ret) {
1557 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1558 return ret;
1559 }
1560 }
1561 }
1562
1563 return ret;
1564 }
1565
arcturus_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)1566 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1567 struct i2c_msg *msg, int num_msgs)
1568 {
1569 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1570 struct amdgpu_device *adev = smu_i2c->adev;
1571 struct smu_context *smu = adev->powerplay.pp_handle;
1572 struct smu_table_context *smu_table = &smu->smu_table;
1573 struct smu_table *table = &smu_table->driver_table;
1574 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1575 int i, j, r, c;
1576 u16 dir;
1577
1578 if (!adev->pm.dpm_enabled)
1579 return -EBUSY;
1580
1581 req = kzalloc_obj(*req);
1582 if (!req)
1583 return -ENOMEM;
1584
1585 req->I2CcontrollerPort = smu_i2c->port;
1586 req->I2CSpeed = I2C_SPEED_FAST_400K;
1587 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1588 dir = msg[0].flags & I2C_M_RD;
1589
1590 for (c = i = 0; i < num_msgs; i++) {
1591 for (j = 0; j < msg[i].len; j++, c++) {
1592 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1593
1594 if (!(msg[i].flags & I2C_M_RD)) {
1595 /* write */
1596 cmd->Cmd = I2C_CMD_WRITE;
1597 cmd->RegisterAddr = msg[i].buf[j];
1598 }
1599
1600 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1601 /* The direction changes.
1602 */
1603 dir = msg[i].flags & I2C_M_RD;
1604 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1605 }
1606
1607 req->NumCmds++;
1608
1609 /*
1610 * Insert STOP if we are at the last byte of either last
1611 * message for the transaction or the client explicitly
1612 * requires a STOP at this particular message.
1613 */
1614 if ((j == msg[i].len - 1) &&
1615 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1616 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1617 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1618 }
1619 }
1620 }
1621 mutex_lock(&adev->pm.mutex);
1622 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1623 if (r)
1624 goto fail;
1625
1626 for (c = i = 0; i < num_msgs; i++) {
1627 if (!(msg[i].flags & I2C_M_RD)) {
1628 c += msg[i].len;
1629 continue;
1630 }
1631 for (j = 0; j < msg[i].len; j++, c++) {
1632 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1633
1634 msg[i].buf[j] = cmd->Data;
1635 }
1636 }
1637 r = num_msgs;
1638 fail:
1639 mutex_unlock(&adev->pm.mutex);
1640 kfree(req);
1641 return r;
1642 }
1643
arcturus_i2c_func(struct i2c_adapter * adap)1644 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
1645 {
1646 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1647 }
1648
1649
1650 static const struct i2c_algorithm arcturus_i2c_algo = {
1651 .master_xfer = arcturus_i2c_xfer,
1652 .functionality = arcturus_i2c_func,
1653 };
1654
1655
1656 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
1657 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1658 .max_read_len = MAX_SW_I2C_COMMANDS,
1659 .max_write_len = MAX_SW_I2C_COMMANDS,
1660 .max_comb_1st_msg_len = 2,
1661 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1662 };
1663
arcturus_i2c_control_init(struct smu_context * smu)1664 static int arcturus_i2c_control_init(struct smu_context *smu)
1665 {
1666 struct amdgpu_device *adev = smu->adev;
1667 int res, i;
1668
1669 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1670 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1671 struct i2c_adapter *control = &smu_i2c->adapter;
1672
1673 smu_i2c->adev = adev;
1674 smu_i2c->port = i;
1675 mutex_init(&smu_i2c->mutex);
1676 control->owner = THIS_MODULE;
1677 control->class = I2C_CLASS_HWMON;
1678 control->dev.parent = &adev->pdev->dev;
1679 control->algo = &arcturus_i2c_algo;
1680 control->quirks = &arcturus_i2c_control_quirks;
1681 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
1682 i2c_set_adapdata(control, smu_i2c);
1683
1684 res = devm_i2c_add_adapter(adev->dev, control);
1685 if (res) {
1686 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1687 return res;
1688 }
1689 }
1690
1691 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1692 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
1693
1694 return 0;
1695 }
1696
arcturus_i2c_control_fini(struct smu_context * smu)1697 static void arcturus_i2c_control_fini(struct smu_context *smu)
1698 {
1699 struct amdgpu_device *adev = smu->adev;
1700
1701 adev->pm.ras_eeprom_i2c_bus = NULL;
1702 adev->pm.fru_eeprom_i2c_bus = NULL;
1703 }
1704
arcturus_get_unique_id(struct smu_context * smu)1705 static void arcturus_get_unique_id(struct smu_context *smu)
1706 {
1707 struct amdgpu_device *adev = smu->adev;
1708 uint32_t top32 = 0, bottom32 = 0;
1709 uint64_t id;
1710
1711 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
1712 if (smu->smc_fw_version < 0x361700) {
1713 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
1714 return;
1715 }
1716
1717 /* Get the SN to turn into a Unique ID */
1718 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
1719 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
1720
1721 id = ((uint64_t)bottom32 << 32) | top32;
1722 adev->unique_id = id;
1723 }
1724
arcturus_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)1725 static int arcturus_set_df_cstate(struct smu_context *smu,
1726 enum pp_df_cstate state)
1727 {
1728 struct amdgpu_device *adev = smu->adev;
1729
1730 /*
1731 * Arcturus does not need the cstate disablement
1732 * prerequisite for gpu reset.
1733 */
1734 if (amdgpu_in_reset(adev) || adev->in_suspend)
1735 return 0;
1736
1737 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
1738 if (smu->smc_fw_version < 0x360F00) {
1739 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
1740 return -EINVAL;
1741 }
1742
1743 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1744 }
1745
1746 static const struct throttling_logging_label {
1747 uint32_t feature_mask;
1748 const char *label;
1749 } logging_label[] = {
1750 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
1751 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1752 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1753 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1754 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1755 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
1756 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
1757 };
arcturus_log_thermal_throttling_event(struct smu_context * smu)1758 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
1759 {
1760 int ret;
1761 int throttler_idx, throttling_events = 0, buf_idx = 0;
1762 struct amdgpu_device *adev = smu->adev;
1763 uint32_t throttler_status;
1764 char log_buf[256];
1765
1766 ret = arcturus_get_smu_metrics_data(smu,
1767 METRICS_THROTTLER_STATUS,
1768 &throttler_status);
1769 if (ret)
1770 return;
1771
1772 memset(log_buf, 0, sizeof(log_buf));
1773 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1774 throttler_idx++) {
1775 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1776 throttling_events++;
1777 buf_idx += snprintf(log_buf + buf_idx,
1778 sizeof(log_buf) - buf_idx,
1779 "%s%s",
1780 throttling_events > 1 ? " and " : "",
1781 logging_label[throttler_idx].label);
1782 if (buf_idx >= sizeof(log_buf)) {
1783 dev_err(adev->dev, "buffer overflow!\n");
1784 log_buf[sizeof(log_buf) - 1] = '\0';
1785 break;
1786 }
1787 }
1788 }
1789
1790 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1791 log_buf);
1792 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1793 smu_cmn_get_indep_throttler_status(throttler_status,
1794 arcturus_throttler_map));
1795 }
1796
arcturus_get_current_pcie_link_speed(struct smu_context * smu)1797 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
1798 {
1799 struct amdgpu_device *adev = smu->adev;
1800 uint32_t esm_ctrl;
1801
1802 /* TODO: confirm this on real target */
1803 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1804 if ((esm_ctrl >> 15) & 0x1)
1805 return (uint16_t)(((esm_ctrl >> 8) & 0x7F) + 128);
1806
1807 return smu_v11_0_get_current_pcie_link_speed(smu);
1808 }
1809
arcturus_get_gpu_metrics(struct smu_context * smu,void ** table)1810 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
1811 void **table)
1812 {
1813 struct gpu_metrics_v1_3 *gpu_metrics =
1814 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr(
1815 smu, SMU_DRIVER_TABLE_GPU_METRICS);
1816 SmuMetrics_t metrics;
1817 int ret = 0;
1818
1819 ret = smu_cmn_get_metrics_table(smu,
1820 &metrics,
1821 false);
1822 if (ret)
1823 return ret;
1824
1825 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1826
1827 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1828 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1829 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1830 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1831 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1832 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1833
1834 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1835 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1836 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
1837
1838 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1839 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
1840
1841 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1842 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1843 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1844 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
1845 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
1846
1847 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1848 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1849 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1850 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1851 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1852
1853 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1854 gpu_metrics->indep_throttle_status =
1855 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1856 arcturus_throttler_map);
1857
1858 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
1859
1860 gpu_metrics->pcie_link_width =
1861 smu_v11_0_get_current_pcie_link_width(smu);
1862 gpu_metrics->pcie_link_speed =
1863 arcturus_get_current_pcie_link_speed(smu);
1864
1865 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1866
1867 *table = (void *)gpu_metrics;
1868
1869 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
1870
1871 return sizeof(struct gpu_metrics_v1_3);
1872 }
1873
1874 static const struct pptable_funcs arcturus_ppt_funcs = {
1875 /* init dpm */
1876 .init_allowed_features = arcturus_init_allowed_features,
1877 /* btc */
1878 .run_btc = arcturus_run_btc,
1879 /* dpm/clk tables */
1880 .set_default_dpm_table = arcturus_set_default_dpm_table,
1881 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
1882 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1883 .emit_clk_levels = arcturus_emit_clk_levels,
1884 .force_clk_levels = arcturus_force_clk_levels,
1885 .read_sensor = arcturus_read_sensor,
1886 .get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
1887 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1888 .get_power_profile_mode = arcturus_get_power_profile_mode,
1889 .set_power_profile_mode = arcturus_set_power_profile_mode,
1890 .set_performance_level = arcturus_set_performance_level,
1891 .get_power_limit = arcturus_get_power_limit,
1892 .is_dpm_running = arcturus_is_dpm_running,
1893 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
1894 .i2c_init = arcturus_i2c_control_init,
1895 .i2c_fini = arcturus_i2c_control_fini,
1896 .get_unique_id = arcturus_get_unique_id,
1897 .init_microcode = smu_v11_0_init_microcode,
1898 .load_microcode = smu_v11_0_load_microcode,
1899 .fini_microcode = smu_v11_0_fini_microcode,
1900 .init_smc_tables = arcturus_init_smc_tables,
1901 .fini_smc_tables = smu_v11_0_fini_smc_tables,
1902 .init_power = smu_v11_0_init_power,
1903 .fini_power = smu_v11_0_fini_power,
1904 .check_fw_status = smu_v11_0_check_fw_status,
1905 /* pptable related */
1906 .setup_pptable = arcturus_setup_pptable,
1907 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1908 .check_fw_version = smu_v11_0_check_fw_version,
1909 .write_pptable = smu_cmn_write_pptable,
1910 .set_driver_table_location = smu_v11_0_set_driver_table_location,
1911 .set_tool_table_location = smu_v11_0_set_tool_table_location,
1912 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1913 .system_features_control = smu_v11_0_system_features_control,
1914 .init_display_count = NULL,
1915 .set_allowed_mask = smu_v11_0_set_allowed_mask,
1916 .get_enabled_mask = smu_cmn_get_enabled_mask,
1917 .feature_is_enabled = smu_cmn_feature_is_enabled,
1918 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1919 .notify_display_change = NULL,
1920 .set_power_limit = smu_v11_0_set_power_limit,
1921 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1922 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
1923 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
1924 .set_min_dcef_deep_sleep = NULL,
1925 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1926 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1927 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1928 .set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
1929 .set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
1930 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1931 .gfx_off_control = smu_v11_0_gfx_off_control,
1932 .register_irq_handler = smu_v11_0_register_irq_handler,
1933 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1934 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1935 .get_bamaco_support = smu_v11_0_get_bamaco_support,
1936 .baco_enter = smu_v11_0_baco_enter,
1937 .baco_exit = smu_v11_0_baco_exit,
1938 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
1939 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
1940 .set_df_cstate = arcturus_set_df_cstate,
1941 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
1942 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1943 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1944 .get_gpu_metrics = arcturus_get_gpu_metrics,
1945 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
1946 .deep_sleep_control = smu_v11_0_deep_sleep_control,
1947 .get_fan_parameters = arcturus_get_fan_parameters,
1948 .interrupt_work = smu_v11_0_interrupt_work,
1949 .smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr,
1950 .set_mp1_state = smu_cmn_set_mp1_state,
1951 };
1952
arcturus_set_ppt_funcs(struct smu_context * smu)1953 void arcturus_set_ppt_funcs(struct smu_context *smu)
1954 {
1955 smu->ppt_funcs = &arcturus_ppt_funcs;
1956 smu->clock_map = arcturus_clk_map;
1957 smu->feature_map = arcturus_feature_mask_map;
1958 smu->table_map = arcturus_table_map;
1959 smu->pwr_src_map = arcturus_pwr_src_map;
1960 smu->workload_map = arcturus_workload_map;
1961 smu_v11_0_init_msg_ctl(smu, arcturus_message_map);
1962 }
1963