1 /*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "opt_ah.h"
18
19 #include "ah.h"
20 #include "ah_internal.h"
21 #include "ah_devid.h"
22 #ifdef AH_DEBUG
23 #include "ah_desc.h" /* NB: for HAL_PHYERR* */
24 #endif
25
26 #include "ar9300/ar9300.h"
27 #include "ar9300/ar9300reg.h"
28 #include "ar9300/ar9300phy.h"
29 #include "ar9300/ar9300desc.h"
30
31 static u_int32_t ar9300_read_loc_timer(struct ath_hal *ah);
32
33 void
ar9300_get_hw_hangs(struct ath_hal * ah,hal_hw_hangs_t * hangs)34 ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs)
35 {
36 struct ath_hal_9300 *ahp = AH9300(ah);
37 *hangs = 0;
38
39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) {
40 *hangs |= HAL_RIFS_BB_HANG_WAR;
41 }
42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) {
43 *hangs |= HAL_DFS_BB_HANG_WAR;
44 }
45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL)
46 == HAL_OK)
47 {
48 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR;
49 }
50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) {
51 *hangs |= HAL_MAC_HANG_WAR;
52 }
53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
54 == HAL_OK)
55 {
56 *hangs |= HAL_PHYRESTART_CLR_WAR;
57 }
58
59 ahp->ah_hang_wars = *hangs;
60 }
61
62 /*
63 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
64 * HT20, HT40, fast-clock, turbo mode, etc.
65 */
66 static u_int
ar9300_mac_to_usec(struct ath_hal * ah,u_int clks)67 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
68 {
69 #if 0
70 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
71
72 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
73 return (ath_hal_mac_usec(ah, clks) / 2);
74 } else {
75 return (ath_hal_mac_usec(ah, clks));
76 }
77 #endif
78 return (ath_hal_mac_usec(ah, clks));
79 }
80
81 u_int
ar9300_mac_to_clks(struct ath_hal * ah,u_int usecs)82 ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
83 {
84 #if 0
85 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
86
87 if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
88 return (ath_hal_mac_clks(ah, usecs) * 2);
89 } else {
90 return (ath_hal_mac_clks(ah, usecs));
91 }
92 #endif
93 return (ath_hal_mac_clks(ah, usecs));
94 }
95
96 void
ar9300_get_mac_address(struct ath_hal * ah,u_int8_t * mac)97 ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
98 {
99 struct ath_hal_9300 *ahp = AH9300(ah);
100
101 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
102 }
103
104 HAL_BOOL
ar9300_set_mac_address(struct ath_hal * ah,const u_int8_t * mac)105 ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac)
106 {
107 struct ath_hal_9300 *ahp = AH9300(ah);
108
109 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
110 return AH_TRUE;
111 }
112
113 void
ar9300_get_bss_id_mask(struct ath_hal * ah,u_int8_t * mask)114 ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask)
115 {
116 struct ath_hal_9300 *ahp = AH9300(ah);
117
118 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN);
119 }
120
121 HAL_BOOL
ar9300_set_bss_id_mask(struct ath_hal * ah,const u_int8_t * mask)122 ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask)
123 {
124 struct ath_hal_9300 *ahp = AH9300(ah);
125
126 /* save it since it must be rewritten on reset */
127 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN);
128
129 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
130 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
131 return AH_TRUE;
132 }
133
134 /*
135 * Attempt to change the cards operating regulatory domain to the given value
136 * Returns: A_EINVAL for an unsupported regulatory domain.
137 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
138 */
139 HAL_BOOL
ar9300_set_regulatory_domain(struct ath_hal * ah,u_int16_t reg_domain,HAL_STATUS * status)140 ar9300_set_regulatory_domain(struct ath_hal *ah,
141 u_int16_t reg_domain, HAL_STATUS *status)
142 {
143 HAL_STATUS ecode;
144
145 if (AH_PRIVATE(ah)->ah_currentRD == 0) {
146 AH_PRIVATE(ah)->ah_currentRD = reg_domain;
147 return AH_TRUE;
148 }
149 ecode = HAL_EIO;
150
151 #if 0
152 bad:
153 #endif
154 if (status) {
155 *status = ecode;
156 }
157 return AH_FALSE;
158 }
159
160 /*
161 * Return the wireless modes (a,b,g,t) supported by hardware.
162 *
163 * This value is what is actually supported by the hardware
164 * and is unaffected by regulatory/country code settings.
165 *
166 */
167 u_int
ar9300_get_wireless_modes(struct ath_hal * ah)168 ar9300_get_wireless_modes(struct ath_hal *ah)
169 {
170 return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
171 }
172
173 /*
174 * Set the interrupt and GPIO values so the ISR can disable RF
175 * on a switch signal. Assumes GPIO port and interrupt polarity
176 * are set prior to call.
177 */
178 void
ar9300_enable_rf_kill(struct ath_hal * ah)179 ar9300_enable_rf_kill(struct ath_hal *ah)
180 {
181 /* TODO - can this really be above the hal on the GPIO interface for
182 * TODO - the client only?
183 */
184 struct ath_hal_9300 *ahp = AH9300(ah);
185
186 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
187 /* Check RF kill GPIO before set/clear RFSILENT bits. */
188 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) {
189 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
190 AR_RFSILENT_FORCE);
191 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
192 }
193 else {
194 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
195 AR_RFSILENT_FORCE);
196 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
197 }
198 }
199 else {
200 /* Connect rfsilent_bb_l to baseband */
201 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
202 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
203
204 /* Set input mux for rfsilent_bb_l to GPIO #0 */
205 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206 AR_GPIO_INPUT_MUX2_RFSILENT);
207 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
208 (ahp->ah_gpio_select & 0x0f) << 4);
209
210 /*
211 * Configure the desired GPIO port for input and
212 * enable baseband rf silence
213 */
214 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
215 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
216 }
217
218 /*
219 * If radio disable switch connection to GPIO bit x is enabled
220 * program GPIO interrupt.
221 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
222 * verified that it is a later version of eeprom, it has a place for
223 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
224 * connection is present.
225 */
226 /*
227 * RFKill uses polling not interrupt,
228 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue
229 */
230 if (ath_hal_hasrfkill_int(ah)) {
231 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) {
232 /* switch already closed, set to interrupt upon open */
233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit);
234 } else {
235 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit);
236 }
237 }
238 }
239
240 /*
241 * Change the LED blinking pattern to correspond to the connectivity
242 */
243 void
ar9300_set_led_state(struct ath_hal * ah,HAL_LED_STATE state)244 ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state)
245 {
246 static const u_int32_t ledbits[8] = {
247 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */
248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */
249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */
250 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */
251 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */
252 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */
253 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
254 AR_CFG_LED_ASSOC_NONE,
255 };
256
257 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]);
258 }
259
260 /*
261 * Sets the Power LED on the cardbus without affecting the Network LED.
262 */
263 void
ar9300_set_power_led_state(struct ath_hal * ah,u_int8_t enabled)264 ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled)
265 {
266 u_int32_t val;
267
268 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF;
269 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val);
270 }
271
272 /*
273 * Sets the Network LED on the cardbus without affecting the Power LED.
274 */
275 void
ar9300_set_network_led_state(struct ath_hal * ah,u_int8_t enabled)276 ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled)
277 {
278 u_int32_t val;
279
280 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF;
281 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val);
282 }
283
284 /*
285 * Change association related fields programmed into the hardware.
286 * Writing a valid BSSID to the hardware effectively enables the hardware
287 * to synchronize its TSF to the correct beacons and receive frames coming
288 * from that BSSID. It is called by the SME JOIN operation.
289 */
290 void
ar9300_write_associd(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)291 ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
292 u_int16_t assoc_id)
293 {
294 struct ath_hal_9300 *ahp = AH9300(ah);
295
296 /* save bssid and assoc_id for restore on reset */
297 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
298 ahp->ah_assoc_id = assoc_id;
299
300 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
301 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
302 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
303 }
304
305 /*
306 * Get the current hardware tsf for stamlme
307 */
308 u_int64_t
ar9300_get_tsf64(struct ath_hal * ah)309 ar9300_get_tsf64(struct ath_hal *ah)
310 {
311 u_int64_t tsf;
312
313 /* XXX sync multi-word read? */
314 tsf = OS_REG_READ(ah, AR_TSF_U32);
315 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
316 return tsf;
317 }
318
319 void
ar9300_set_tsf64(struct ath_hal * ah,u_int64_t tsf)320 ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf)
321 {
322 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff));
323 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff));
324 }
325
326 /*
327 * Get the current hardware tsf for stamlme
328 */
329 u_int32_t
ar9300_get_tsf32(struct ath_hal * ah)330 ar9300_get_tsf32(struct ath_hal *ah)
331 {
332 return OS_REG_READ(ah, AR_TSF_L32);
333 }
334
335 u_int32_t
ar9300_get_tsf2_32(struct ath_hal * ah)336 ar9300_get_tsf2_32(struct ath_hal *ah)
337 {
338 return OS_REG_READ(ah, AR_TSF2_L32);
339 }
340
341 /*
342 * Reset the current hardware tsf for stamlme.
343 */
344 void
ar9300_reset_tsf(struct ath_hal * ah)345 ar9300_reset_tsf(struct ath_hal *ah)
346 {
347 int count;
348
349 count = 0;
350 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
351 count++;
352 if (count > 10) {
353 HALDEBUG(ah, HAL_DEBUG_RESET,
354 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__);
355 break;
356 }
357 OS_DELAY(10);
358 }
359 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
360 }
361
362 /*
363 * Set or clear hardware basic rate bit
364 * Set hardware basic rate set if basic rate is found
365 * and basic rate is equal or less than 2Mbps
366 */
367 void
ar9300_set_basic_rate(struct ath_hal * ah,HAL_RATE_SET * rs)368 ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
369 {
370 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
371 u_int32_t reg;
372 u_int8_t xset;
373 int i;
374
375 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
376 return;
377 }
378 xset = 0;
379 for (i = 0; i < rs->rs_count; i++) {
380 u_int8_t rset = rs->rs_rates[i];
381 /* Basic rate defined? */
382 if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
383 xset = rset;
384 }
385 }
386 /*
387 * Set the h/w bit to reflect whether or not the basic
388 * rate is found to be equal or less than 2Mbps.
389 */
390 reg = OS_REG_READ(ah, AR_STA_ID1);
391 if (xset && xset / 2 <= 2) {
392 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
393 } else {
394 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
395 }
396 }
397
398 /*
399 * Grab a semi-random value from hardware registers - may not
400 * change often
401 */
402 u_int32_t
ar9300_get_random_seed(struct ath_hal * ah)403 ar9300_get_random_seed(struct ath_hal *ah)
404 {
405 u_int32_t nf;
406
407 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
408 if (nf & 0x100) {
409 nf = 0 - ((nf ^ 0x1ff) + 1);
410 }
411 return (OS_REG_READ(ah, AR_TSF_U32) ^
412 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
413 }
414
415 /*
416 * Detect if our card is present
417 */
418 HAL_BOOL
ar9300_detect_card_present(struct ath_hal * ah)419 ar9300_detect_card_present(struct ath_hal *ah)
420 {
421 u_int16_t mac_version, mac_rev;
422 u_int32_t v;
423
424 /*
425 * Read the Silicon Revision register and compare that
426 * to what we read at attach time. If the same, we say
427 * a card/device is present.
428 */
429 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID;
430 if (v == 0xFF) {
431 /* new SREV format */
432 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
433 /*
434 * Include 6-bit Chip Type (masked to 0) to differentiate
435 * from pre-Sowl versions
436 */
437 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
438 mac_rev = MS(v, AR_SREV_REVISION2);
439 } else {
440 mac_version = MS(v, AR_SREV_VERSION);
441 mac_rev = v & AR_SREV_REVISION;
442 }
443 return (AH_PRIVATE(ah)->ah_macVersion == mac_version &&
444 AH_PRIVATE(ah)->ah_macRev == mac_rev);
445 }
446
447 /*
448 * Update MIB Counters
449 */
450 void
ar9300_update_mib_mac_stats(struct ath_hal * ah)451 ar9300_update_mib_mac_stats(struct ath_hal *ah)
452 {
453 struct ath_hal_9300 *ahp = AH9300(ah);
454 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats;
455
456 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
457 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
458 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
459 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
460 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
461 }
462
463 void
ar9300_get_mib_mac_stats(struct ath_hal * ah,HAL_MIB_STATS * stats)464 ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats)
465 {
466 struct ath_hal_9300 *ahp = AH9300(ah);
467 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats;
468
469 stats->ackrcv_bad = istats->ackrcv_bad;
470 stats->rts_bad = istats->rts_bad;
471 stats->fcs_bad = istats->fcs_bad;
472 stats->rts_good = istats->rts_good;
473 stats->beacons = istats->beacons;
474 }
475
476 /*
477 * Detect if the HW supports spreading a CCK signal on channel 14
478 */
479 HAL_BOOL
ar9300_is_japan_channel_spread_supported(struct ath_hal * ah)480 ar9300_is_japan_channel_spread_supported(struct ath_hal *ah)
481 {
482 return AH_TRUE;
483 }
484
485 /*
486 * Get the rssi of frame curently being received.
487 */
488 u_int32_t
ar9300_get_cur_rssi(struct ath_hal * ah)489 ar9300_get_cur_rssi(struct ath_hal *ah)
490 {
491 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */
492 /* get combined RSSI */
493 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff);
494 }
495
496 #if ATH_GEN_RANDOMNESS
497 /*
498 * Get the rssi value from BB on ctl chain0.
499 */
500 u_int32_t
ar9300_get_rssi_chain0(struct ath_hal * ah)501 ar9300_get_rssi_chain0(struct ath_hal *ah)
502 {
503 /* get ctl chain0 RSSI */
504 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff;
505 }
506 #endif
507
508 u_int
ar9300_get_def_antenna(struct ath_hal * ah)509 ar9300_get_def_antenna(struct ath_hal *ah)
510 {
511 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
512 }
513
514 /* Setup coverage class */
515 void
ar9300_set_coverage_class(struct ath_hal * ah,u_int8_t coverageclass,int now)516 ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now)
517 {
518 }
519
520 void
ar9300_set_def_antenna(struct ath_hal * ah,u_int antenna)521 ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
522 {
523 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
524 }
525
526 HAL_BOOL
ar9300_set_antenna_switch(struct ath_hal * ah,HAL_ANT_SETTING settings,const struct ieee80211_channel * chan,u_int8_t * tx_chainmask,u_int8_t * rx_chainmask,u_int8_t * antenna_cfgd)527 ar9300_set_antenna_switch(struct ath_hal *ah,
528 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
529 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
530 {
531 struct ath_hal_9300 *ahp = AH9300(ah);
532
533 /*
534 * Owl does not support diversity or changing antennas.
535 *
536 * Instead this API and function are defined differently for AR9300.
537 * To support Tablet PC's, this interface allows the system
538 * to dramatically reduce the TX power on a particular chain.
539 *
540 * Based on the value of (redefined) diversity_control, the
541 * reset code will decrease power on chain 0 or chain 1/2.
542 *
543 * Based on the value of bit 0 of antenna_switch_swap,
544 * the mapping between OID call and chain is defined as:
545 * 0: map A -> 0, B -> 1;
546 * 1: map A -> 1, B -> 0;
547 *
548 * NOTE:
549 * The devices that use this OID should use a tx_chain_mask and
550 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is
551 * used in order to ensure an active transmit antenna. This
552 * API will allow the host to turn off the only transmitting
553 * antenna to ensure the antenna closest to the user's body is
554 * powered-down.
555 */
556 /*
557 * Set antenna control for use during reset sequence by
558 * ar9300_decrease_chain_power()
559 */
560 ahp->ah_diversity_control = settings;
561
562 return AH_TRUE;
563 }
564
565 HAL_BOOL
ar9300_is_sleep_after_beacon_broken(struct ath_hal * ah)566 ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah)
567 {
568 return AH_TRUE;
569 }
570
571 HAL_BOOL
ar9300_set_slot_time(struct ath_hal * ah,u_int us)572 ar9300_set_slot_time(struct ath_hal *ah, u_int us)
573 {
574 struct ath_hal_9300 *ahp = AH9300(ah);
575 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) {
576 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us);
577 ahp->ah_slot_time = (u_int) -1; /* restore default handling */
578 return AH_FALSE;
579 } else {
580 /* convert to system clocks */
581 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us));
582 ahp->ah_slot_time = us;
583 return AH_TRUE;
584 }
585 }
586
587 HAL_BOOL
ar9300_set_ack_timeout(struct ath_hal * ah,u_int us)588 ar9300_set_ack_timeout(struct ath_hal *ah, u_int us)
589 {
590 struct ath_hal_9300 *ahp = AH9300(ah);
591
592 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
593 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us);
594 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */
595 return AH_FALSE;
596 } else {
597 /* convert to system clocks */
598 OS_REG_RMW_FIELD(ah,
599 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us));
600 ahp->ah_ack_timeout = us;
601 return AH_TRUE;
602 }
603 }
604
605 u_int
ar9300_get_ack_timeout(struct ath_hal * ah)606 ar9300_get_ack_timeout(struct ath_hal *ah)
607 {
608 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
609 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
610 }
611
612 HAL_STATUS
ar9300_set_quiet(struct ath_hal * ah,u_int32_t period,u_int32_t duration,u_int32_t next_start,HAL_QUIET_FLAG flag)613 ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
614 u_int32_t next_start, HAL_QUIET_FLAG flag)
615 {
616 #define TU_TO_USEC(_tu) ((_tu) << 10)
617 HAL_STATUS status = HAL_EIO;
618 u_int32_t tsf = 0, j, next_start_us = 0;
619 if (flag & HAL_QUIET_ENABLE) {
620 for (j = 0; j < 2; j++) {
621 next_start_us = TU_TO_USEC(next_start);
622 tsf = OS_REG_READ(ah, AR_TSF_L32);
623 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
624 next_start_us += tsf;
625 }
626 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
627 next_start_us +=
628 ah->ah_config.ah_sw_beacon_response_time;
629 }
630 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
631 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
632 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
633 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
634 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
635 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
636 status = HAL_OK;
637 break;
638 }
639 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved "
640 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf);
641 /* TSF shouldn't count twice or reg access is taking forever */
642 HALASSERT(j < 1);
643 }
644 } else {
645 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
646 status = HAL_OK;
647 }
648
649 return status;
650 #undef TU_TO_USEC
651 }
652
653 //#ifdef ATH_SUPPORT_DFS
654 void
ar9300_cac_tx_quiet(struct ath_hal * ah,HAL_BOOL enable)655 ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
656 {
657 uint32_t reg1, reg2;
658
659 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
660 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1));
661 AH9300(ah)->ah_cac_quiet_enabled = enable;
662
663 if (enable) {
664 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
665 reg1 | AR_PCU_FORCE_QUIET_COLL);
666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
667 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE);
668 } else {
669 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
670 reg1 & ~AR_PCU_FORCE_QUIET_COLL);
671 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
672 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE);
673 }
674 }
675 //#endif /* ATH_SUPPORT_DFS */
676
677 void
ar9300_set_pcu_config(struct ath_hal * ah)678 ar9300_set_pcu_config(struct ath_hal *ah)
679 {
680 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode);
681 }
682
683 HAL_STATUS
ar9300_get_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t * result)684 ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
685 u_int32_t capability, u_int32_t *result)
686 {
687 struct ath_hal_9300 *ahp = AH9300(ah);
688 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
689 struct ar9300_ani_state *ani;
690
691 switch (type) {
692 case HAL_CAP_CIPHER: /* cipher handled in hardware */
693 switch (capability) {
694 case HAL_CIPHER_AES_CCM:
695 case HAL_CIPHER_AES_OCB:
696 case HAL_CIPHER_TKIP:
697 case HAL_CIPHER_WEP:
698 case HAL_CIPHER_MIC:
699 case HAL_CIPHER_CLR:
700 return HAL_OK;
701 default:
702 return HAL_ENOTSUPP;
703 }
704 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
705 switch (capability) {
706 case 0: /* hardware capability */
707 return HAL_OK;
708 case 1:
709 return (ahp->ah_sta_id1_defaults &
710 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
711 default:
712 return HAL_ENOTSUPP;
713 }
714 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
715 switch (capability) {
716 case 0: /* hardware capability */
717 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
718 case 1: /* current setting */
719 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
720 HAL_ENXIO : HAL_OK;
721 default:
722 return HAL_ENOTSUPP;
723 }
724 case HAL_CAP_WME_TKIPMIC:
725 /* hardware can do TKIP MIC when WMM is turned on */
726 return HAL_OK;
727 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
728 return HAL_OK;
729 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
730 switch (capability) {
731 case 0: /* hardware capability */
732 return HAL_OK;
733 case 1: /* current setting */
734 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) &
735 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
736 HAL_OK : HAL_ENXIO;
737 }
738 return HAL_EINVAL;
739 case HAL_CAP_TPC:
740 switch (capability) {
741 case 0: /* hardware capability */
742 return HAL_OK;
743 case 1:
744 return ah->ah_config.ath_hal_desc_tpc ?
745 HAL_OK : HAL_ENXIO;
746 }
747 return HAL_OK;
748 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
749 return HAL_OK;
750 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
751 switch (capability) {
752 case 0: /* hardware capability */
753 return HAL_OK;
754 case 1:
755 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
756 /*
757 * Owl and Merlin have problems in mcast key search.
758 * Disable this cap. in Ad-hoc mode. see Bug 25776 and
759 * 26802
760 */
761 return HAL_ENXIO;
762 } else {
763 return (ahp->ah_sta_id1_defaults &
764 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
765 }
766 }
767 return HAL_EINVAL;
768 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
769 switch (capability) {
770 case 0: /* hardware capability */
771 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
772 case 1:
773 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
774 HAL_OK : HAL_ENXIO;
775 }
776 return HAL_EINVAL;
777 case HAL_CAP_RFSILENT: /* rfsilent support */
778 if (capability == 3) { /* rfkill interrupt */
779 /*
780 * XXX: Interrupt-based notification of RF Kill state
781 * changes not working yet. Report that this feature
782 * is not supported so that polling is used instead.
783 */
784 return (HAL_ENOTSUPP);
785 }
786 return ath_hal_getcapability(ah, type, capability, result);
787 case HAL_CAP_4ADDR_AGGR:
788 return HAL_OK;
789 case HAL_CAP_BB_RIFS_HANG:
790 return HAL_ENOTSUPP;
791 case HAL_CAP_BB_DFS_HANG:
792 return HAL_ENOTSUPP;
793 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG:
794 /* Track chips that are known to have BB hangs related
795 * to rx_clear stuck low.
796 */
797 return HAL_ENOTSUPP;
798 case HAL_CAP_MAC_HANG:
799 /* Track chips that are known to have MAC hangs.
800 */
801 return HAL_OK;
802 case HAL_CAP_RIFS_RX_ENABLED:
803 /* Is RIFS RX currently enabled */
804 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
805 #if 0
806 case HAL_CAP_ANT_CFG_2GHZ:
807 *result = p_cap->halNumAntCfg2Ghz;
808 return HAL_OK;
809 case HAL_CAP_ANT_CFG_5GHZ:
810 *result = p_cap->halNumAntCfg5Ghz;
811 return HAL_OK;
812 case HAL_CAP_RX_STBC:
813 *result = p_cap->hal_rx_stbc_support;
814 return HAL_OK;
815 case HAL_CAP_TX_STBC:
816 *result = p_cap->hal_tx_stbc_support;
817 return HAL_OK;
818 #endif
819 case HAL_CAP_LDPC:
820 *result = p_cap->halLDPCSupport;
821 return HAL_OK;
822 case HAL_CAP_DYNAMIC_SMPS:
823 return HAL_OK;
824 case HAL_CAP_DS:
825 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
826 (p_cap->halTxChainMask & 0x3) != 0x3 ||
827 (p_cap->halRxChainMask & 0x3) != 0x3) ?
828 HAL_ENOTSUPP : HAL_OK;
829 case HAL_CAP_TS:
830 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
831 (p_cap->halTxChainMask & 0x7) != 0x7 ||
832 (p_cap->halRxChainMask & 0x7) != 0x7) ?
833 HAL_ENOTSUPP : HAL_OK;
834 case HAL_CAP_OL_PWRCTRL:
835 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
836 HAL_OK : HAL_ENOTSUPP;
837 case HAL_CAP_CRDC:
838 #if ATH_SUPPORT_CRDC
839 return (AR_SREV_WASP(ah) &&
840 ah->ah_config.ath_hal_crdc_enable) ?
841 HAL_OK : HAL_ENOTSUPP;
842 #else
843 return HAL_ENOTSUPP;
844 #endif
845 #if 0
846 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
847 *result = (u_int32_t)(-1);
848 return HAL_OK;
849 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
850 *result = (u_int32_t)(-1);
851 return HAL_OK;
852 #endif
853 case HAL_CAP_BB_PANIC_WATCHDOG:
854 return HAL_OK;
855 case HAL_CAP_PHYRESTART_CLR_WAR:
856 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
857 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
858 {
859 return HAL_OK;
860 }
861 else
862 {
863 return HAL_ENOTSUPP;
864 }
865 case HAL_CAP_ENTERPRISE_MODE:
866 *result = ahp->ah_enterprise_mode >> 16;
867 /*
868 * WAR for EV 77658 - Add delimiters to first sub-frame when using
869 * RTS/CTS with aggregation and non-enterprise Osprey.
870 *
871 * Bug fixed in AR9580/Peacock, Wasp1.1 and later
872 */
873 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
874 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
875 AR_SREV_WASP_10(ah))) {
876 *result |= AH_ENT_RTSCTS_DELIM_WAR;
877 }
878 return HAL_OK;
879 case HAL_CAP_LDPCWAR:
880 /* WAR for RIFS+LDPC issue is required for all chips currently
881 * supported by ar9300 HAL.
882 */
883 return HAL_OK;
884 case HAL_CAP_ENABLE_APM:
885 *result = p_cap->halApmEnable;
886 return HAL_OK;
887 case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
888 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
889 case HAL_CAP_PCIE_LCR_OFFSET:
890 *result = p_cap->hal_pcie_lcr_offset;
891 return HAL_OK;
892 case HAL_CAP_SMARTANTENNA:
893 /* FIXME A request is pending with h/w team to add feature bit in
894 * caldata to detect if board has smart antenna or not, once added
895 * we need to fix his piece of code to read and return value without
896 * any compile flags
897 */
898 #if UMAC_SUPPORT_SMARTANTENNA
899 /* enable smart antenna for Peacock, Wasp and scorpion
900 for future chips need to modify */
901 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) {
902 return HAL_OK;
903 } else {
904 return HAL_ENOTSUPP;
905 }
906 #else
907 return HAL_ENOTSUPP;
908 #endif
909
910 #ifdef ATH_TRAFFIC_FAST_RECOVER
911 case HAL_CAP_TRAFFIC_FAST_RECOVER:
912 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) {
913 return HAL_OK;
914 } else {
915 return HAL_ENOTSUPP;
916 }
917 #endif
918
919 /* FreeBSD ANI */
920 case HAL_CAP_INTMIT: /* interference mitigation */
921 switch (capability) {
922 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */
923 return HAL_OK;
924 case HAL_CAP_INTMIT_ENABLE:
925 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ?
926 HAL_OK : HAL_ENXIO;
927 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL:
928 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL:
929 // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR:
930 case HAL_CAP_INTMIT_FIRSTEP_LEVEL:
931 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL:
932 ani = ar9300_ani_get_current_state(ah);
933 if (ani == AH_NULL)
934 return HAL_ENXIO;
935 switch (capability) {
936 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */
937 case 2: *result = ani->ofdm_noise_immunity_level; break;
938 case 3: *result = !ani->ofdm_weak_sig_detect_off; break;
939 // case 4: *result = ani->cck_weak_sig_threshold; break;
940 case 5: *result = ani->firstep_level; break;
941 case 6: *result = ani->spur_immunity_level; break;
942 }
943 return HAL_OK;
944 }
945 return HAL_EINVAL;
946 case HAL_CAP_ENFORCE_TXOP:
947 if (capability == 0)
948 return (HAL_OK);
949 if (capability != 1)
950 return (HAL_ENOTSUPP);
951 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA);
952 return (HAL_OK);
953 case HAL_CAP_TOA_LOCATIONING:
954 if (capability == 0)
955 return HAL_OK;
956 if (capability == 2) {
957 *result = ar9300_read_loc_timer(ah);
958 return (HAL_OK);
959 }
960 return HAL_ENOTSUPP;
961 default:
962 return ath_hal_getcapability(ah, type, capability, result);
963 }
964 }
965
966 HAL_BOOL
ar9300_set_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t setting,HAL_STATUS * status)967 ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
968 u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
969 {
970 struct ath_hal_9300 *ahp = AH9300(ah);
971 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
972 u_int32_t v;
973
974 switch (type) {
975 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
976 if (! p_cap->halTkipMicTxRxKeySupport)
977 return AH_FALSE;
978
979 if (setting)
980 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
981 else
982 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
983
984 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
985 return AH_TRUE;
986
987 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
988 if (setting) {
989 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
990 } else {
991 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
992 }
993 return AH_TRUE;
994 case HAL_CAP_DIVERSITY:
995 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
996 if (setting) {
997 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
998 } else {
999 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1000 }
1001 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1002 return AH_TRUE;
1003 case HAL_CAP_DIAG: /* hardware diagnostic support */
1004 /*
1005 * NB: could split this up into virtual capabilities,
1006 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
1007 * seems worth the additional complexity.
1008 */
1009 #ifdef AH_DEBUG
1010 AH_PRIVATE(ah)->ah_diagreg = setting;
1011 #else
1012 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
1013 #endif
1014 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
1015 return AH_TRUE;
1016 case HAL_CAP_TPC:
1017 ah->ah_config.ath_hal_desc_tpc = (setting != 0);
1018 return AH_TRUE;
1019 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
1020 if (setting) {
1021 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
1022 } else {
1023 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1024 }
1025 return AH_TRUE;
1026 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
1027 if (p_cap->halTsfAddSupport) {
1028 if (setting) {
1029 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
1030 } else {
1031 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
1032 }
1033 return AH_TRUE;
1034 }
1035 return AH_FALSE;
1036
1037 /* FreeBSD interrupt mitigation / ANI */
1038 case HAL_CAP_INTMIT: { /* interference mitigation */
1039 /* This maps the public ANI commands to the internal ANI commands */
1040 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */
1041 static const HAL_ANI_CMD cmds[] = {
1042 HAL_ANI_PRESENT,
1043 HAL_ANI_MODE,
1044 HAL_ANI_NOISE_IMMUNITY_LEVEL,
1045 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
1046 HAL_ANI_CCK_WEAK_SIGNAL_THR,
1047 HAL_ANI_FIRSTEP_LEVEL,
1048 HAL_ANI_SPUR_IMMUNITY_LEVEL,
1049 };
1050 #define N(a) (sizeof(a) / sizeof(a[0]))
1051 return capability < N(cmds) ?
1052 ar9300_ani_control(ah, cmds[capability], setting) :
1053 AH_FALSE;
1054 #undef N
1055 }
1056
1057 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */
1058 ahp->rx_buf_size = setting & AR_DATABUF_MASK;
1059 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
1060 return AH_TRUE;
1061
1062 case HAL_CAP_ENFORCE_TXOP:
1063 if (capability != 1)
1064 return AH_FALSE;
1065 if (setting) {
1066 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA;
1067 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1068 } else {
1069 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA;
1070 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1071 }
1072 return AH_TRUE;
1073
1074 case HAL_CAP_TOA_LOCATIONING:
1075 if (capability == 0)
1076 return AH_TRUE;
1077 if (capability == 1) {
1078 ar9300_update_loc_ctl_reg(ah, setting);
1079 return AH_TRUE;
1080 }
1081 return AH_FALSE;
1082 /* fall thru... */
1083 default:
1084 return ath_hal_setcapability(ah, type, capability, setting, status);
1085 }
1086 }
1087
1088 #ifdef AH_DEBUG
1089 static void
ar9300_print_reg(struct ath_hal * ah,u_int32_t args)1090 ar9300_print_reg(struct ath_hal *ah, u_int32_t args)
1091 {
1092 u_int32_t i = 0;
1093
1094 /* Read 0x80d0 to trigger pcie analyzer */
1095 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1096 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0));
1097
1098 if (args & HAL_DIAG_PRINT_REG_COUNTER) {
1099 struct ath_hal_9300 *ahp = AH9300(ah);
1100 u_int32_t tf, rf, rc, cc;
1101
1102 tf = OS_REG_READ(ah, AR_TFCNT);
1103 rf = OS_REG_READ(ah, AR_RFCNT);
1104 rc = OS_REG_READ(ah, AR_RCCNT);
1105 cc = OS_REG_READ(ah, AR_CCCNT);
1106
1107 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1108 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf);
1109 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1110 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf);
1111 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1112 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc);
1113 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1114 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc);
1115
1116 ahp->last_tf = tf;
1117 ahp->last_rf = rf;
1118 ahp->last_rc = rc;
1119 ahp->last_cc = cc;
1120
1121 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1122 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0));
1123 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1124 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1));
1125 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1126 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2));
1127 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1128 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3));
1129 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1130 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4));
1131 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1132 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5));
1133 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1134 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6));
1135 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1136 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7));
1137 }
1138
1139 if (args & HAL_DIAG_PRINT_REG_ALL) {
1140 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) {
1141 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1142 i, OS_REG_READ(ah, i));
1143 }
1144
1145 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) {
1146 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1147 i, OS_REG_READ(ah, i));
1148 }
1149
1150 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1151 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i));
1152
1153 HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1154 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i));
1155
1156 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) {
1157 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1158 i, OS_REG_READ(ah, i));
1159 }
1160
1161 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) {
1162 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1163 i, OS_REG_READ(ah, i));
1164 }
1165
1166 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) {
1167 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1168 i, OS_REG_READ(ah, i));
1169 }
1170
1171 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) {
1172 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1173 i, OS_REG_READ(ah, i));
1174 }
1175
1176 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) {
1177 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1178 i, OS_REG_READ(ah, i));
1179 }
1180
1181 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) {
1182 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1183 i, OS_REG_READ(ah, i));
1184 }
1185
1186 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) {
1187 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1188 i, OS_REG_READ(ah, i));
1189 }
1190
1191 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) {
1192 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1193 i, OS_REG_READ(ah, i));
1194 }
1195
1196 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) {
1197 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1198 i, OS_REG_READ(ah, i));
1199 }
1200
1201 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) {
1202 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1203 i, OS_REG_READ(ah, i));
1204 }
1205
1206 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) {
1207 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1208 i, OS_REG_READ(ah, i));
1209 }
1210 }
1211 }
1212 #endif
1213
1214 HAL_BOOL
ar9300_get_diag_state(struct ath_hal * ah,int request,const void * args,u_int32_t argsize,void ** result,u_int32_t * resultsize)1215 ar9300_get_diag_state(struct ath_hal *ah, int request,
1216 const void *args, u_int32_t argsize,
1217 void **result, u_int32_t *resultsize)
1218 {
1219 struct ath_hal_9300 *ahp = AH9300(ah);
1220 struct ar9300_ani_state *ani;
1221
1222 (void) ahp;
1223 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) {
1224 return AH_TRUE;
1225 }
1226 switch (request) {
1227 #ifdef AH_PRIVATE_DIAG
1228 case HAL_DIAG_EEPROM:
1229 *result = &ahp->ah_eeprom;
1230 *resultsize = sizeof(ar9300_eeprom_t);
1231 return AH_TRUE;
1232
1233 #if 0 /* XXX - TODO */
1234 case HAL_DIAG_EEPROM_EXP_11A:
1235 case HAL_DIAG_EEPROM_EXP_11B:
1236 case HAL_DIAG_EEPROM_EXP_11G:
1237 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A];
1238 *result = pe->p_channels;
1239 *resultsize = (*result == AH_NULL) ? 0 :
1240 roundup(sizeof(u_int16_t) * pe->num_channels,
1241 sizeof(u_int32_t)) +
1242 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels;
1243 return AH_TRUE;
1244 #endif
1245 case HAL_DIAG_RFGAIN:
1246 *result = &ahp->ah_gain_values;
1247 *resultsize = sizeof(GAIN_VALUES);
1248 return AH_TRUE;
1249 case HAL_DIAG_RFGAIN_CURSTEP:
1250 *result = (void *) ahp->ah_gain_values.curr_step;
1251 *resultsize = (*result == AH_NULL) ?
1252 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1253 return AH_TRUE;
1254 #if 0 /* XXX - TODO */
1255 case HAL_DIAG_PCDAC:
1256 *result = ahp->ah_pcdac_table;
1257 *resultsize = ahp->ah_pcdac_table_size;
1258 return AH_TRUE;
1259 #endif
1260 case HAL_DIAG_ANI_CURRENT:
1261
1262 ani = ar9300_ani_get_current_state(ah);
1263 if (ani == AH_NULL)
1264 return AH_FALSE;
1265 /* Convert ar9300 HAL to FreeBSD HAL ANI state */
1266 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state));
1267 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level;
1268 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level;
1269 ahp->ext_ani_state.firstepLevel = ani->firstep_level;
1270 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off;
1271 ahp->ext_ani_state.mrcCck = !! ani->mrc_cck_off;
1272 ahp->ext_ani_state.cckNoiseImmunityLevel = ani->cck_noise_immunity_level;
1273
1274 ahp->ext_ani_state.listenTime = ani->listen_time;
1275
1276 *result = &ahp->ext_ani_state;
1277 *resultsize = sizeof(ahp->ext_ani_state);
1278 #if 0
1279 *result = ar9300_ani_get_current_state(ah);
1280 *resultsize = (*result == AH_NULL) ?
1281 0 : sizeof(struct ar9300_ani_state);
1282 #endif
1283 return AH_TRUE;
1284 case HAL_DIAG_ANI_STATS:
1285 *result = ar9300_ani_get_current_stats(ah);
1286 *resultsize = (*result == AH_NULL) ?
1287 0 : sizeof(HAL_ANI_STATS);
1288 return AH_TRUE;
1289 case HAL_DIAG_ANI_CMD:
1290 {
1291 HAL_ANI_CMD savefunc = ahp->ah_ani_function;
1292 if (argsize != 2*sizeof(u_int32_t)) {
1293 return AH_FALSE;
1294 }
1295 /* temporarly allow all functions so we can override */
1296 ahp->ah_ani_function = HAL_ANI_ALL;
1297 ar9300_ani_control(
1298 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1299 ahp->ah_ani_function = savefunc;
1300 return AH_TRUE;
1301 }
1302 #if 0
1303 case HAL_DIAG_TXCONT:
1304 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1305 return AH_TRUE;
1306 #endif /* 0 */
1307 #endif /* AH_PRIVATE_DIAG */
1308 case HAL_DIAG_CHANNELS:
1309 #if 0
1310 *result = &(ahp->ah_priv.ah_channels[0]);
1311 *resultsize =
1312 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1313 #endif
1314 return AH_TRUE;
1315 #ifdef AH_DEBUG
1316 case HAL_DIAG_PRINT_REG:
1317 ar9300_print_reg(ah, *((const u_int32_t *)args));
1318 return AH_TRUE;
1319 #endif
1320 default:
1321 break;
1322 }
1323
1324 return AH_FALSE;
1325 }
1326
1327 void
ar9300_dma_reg_dump(struct ath_hal * ah)1328 ar9300_dma_reg_dump(struct ath_hal *ah)
1329 {
1330 #ifdef AH_DEBUG
1331 #define NUM_DMA_DEBUG_REGS 8
1332 #define NUM_QUEUES 10
1333
1334 u_int32_t val[NUM_DMA_DEBUG_REGS];
1335 int qcu_offset = 0, dcu_offset = 0;
1336 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1337 int i, j, k;
1338 int16_t nfarray[HAL_NUM_NF_READINGS];
1339 #ifdef ATH_NF_PER_CHAN
1340 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1341 #endif /* ATH_NF_PER_CHAN */
1342 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1343
1344 /* selecting DMA OBS 8 */
1345 OS_REG_WRITE(ah, AR_MACMISC,
1346 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1347 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1348
1349 ath_hal_printf(ah, "Raw DMA Debug values:\n");
1350 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
1351 if (i % 4 == 0) {
1352 ath_hal_printf(ah, "\n");
1353 }
1354
1355 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1356 ath_hal_printf(ah, "%d: %08x ", i, val[i]);
1357 }
1358
1359 ath_hal_printf(ah, "\n\n");
1360 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1361
1362 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) {
1363 if (i == 8) {
1364 /* only 8 QCU entries in val[0] */
1365 qcu_offset = 0;
1366 qcu_base++;
1367 }
1368
1369 if (i == 6) {
1370 /* only 6 DCU entries in val[4] */
1371 dcu_offset = 0;
1372 dcu_base++;
1373 }
1374
1375 ath_hal_printf(ah,
1376 "%2d %2x %1x %2x %2x\n",
1377 i,
1378 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset,
1379 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3),
1380 val[2] & (0x7 << (i * 3)) >> (i * 3),
1381 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset);
1382 }
1383
1384 ath_hal_printf(ah, "\n");
1385 ath_hal_printf(ah,
1386 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1387 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1388 ath_hal_printf(ah,
1389 "qcu_complete state: %2x dcu_complete state: %2x\n",
1390 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1391 ath_hal_printf(ah,
1392 "dcu_arb state: %2x dcu_fp state: %2x\n",
1393 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1394 ath_hal_printf(ah,
1395 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1396 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1397 ath_hal_printf(ah,
1398 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1399 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1400 ath_hal_printf(ah,
1401 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1402 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1403 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1));
1404 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR));
1405
1406 ar9300_upload_noise_floor(ah, 1, nfarray);
1407 ath_hal_printf(ah, "2G:\n");
1408 ath_hal_printf(ah, "Min CCA Out:\n");
1409 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1410 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1411 nfarray[0], nfarray[1], nfarray[2]);
1412 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1413 nfarray[3], nfarray[4], nfarray[5]);
1414
1415 ar9300_upload_noise_floor(ah, 0, nfarray);
1416 ath_hal_printf(ah, "5G:\n");
1417 ath_hal_printf(ah, "Min CCA Out:\n");
1418 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1419 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1420 nfarray[0], nfarray[1], nfarray[2]);
1421 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1422 nfarray[3], nfarray[4], nfarray[5]);
1423
1424 for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1425 ath_hal_printf(ah, "%s Chain %d NF History:\n",
1426 ((i < 3) ? "Control " : "Extension "), i%3);
1427 for (j = 0, k = h->base.curr_index;
1428 j < HAL_NF_CAL_HIST_LEN_FULL;
1429 j++, k++) {
1430 ath_hal_printf(ah, "Element %d: %d\n",
1431 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1432 }
1433 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]);
1434 }
1435
1436 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1437 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n",
1438 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1439 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1440 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ);
1441 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n",
1442 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES),
1443 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES));
1444 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n",
1445 MS(reg, AR_PHY_DESIRED_SZ_ADC),
1446 MS(reg, AR_PHY_DESIRED_SZ_ADC));
1447 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG);
1448 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n",
1449 MS(reg, AR_PHY_FIND_SIG_FIRSTEP),
1450 MS(reg, AR_PHY_FIND_SIG_FIRSTEP));
1451 reg = OS_REG_READ(ah, AR_PHY_AGC);
1452 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n",
1453 MS(reg, AR_PHY_AGC_COARSE_HIGH),
1454 MS(reg, AR_PHY_AGC_COARSE_HIGH));
1455 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n",
1456 MS(reg, AR_PHY_AGC_COARSE_LOW),
1457 MS(reg, AR_PHY_AGC_COARSE_LOW));
1458 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n",
1459 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST),
1460 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST));
1461 reg = OS_REG_READ(ah, AR_PHY_TIMING5);
1462 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n",
1463 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE));
1464 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n",
1465 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1),
1466 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1));
1467 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n",
1468 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A),
1469 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A));
1470 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK);
1471 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n",
1472 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR));
1473 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n",
1474 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR),
1475 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR));
1476
1477
1478 /* Step 1a: Set bit 23 of register 0xa360 to 0 */
1479 reg = OS_REG_READ(ah, 0xa360);
1480 reg &= ~0x00800000;
1481 OS_REG_WRITE(ah, 0xa360, reg);
1482
1483 /* Step 2a: Set register 0xa364 to 0x1000 */
1484 reg = 0x1000;
1485 OS_REG_WRITE(ah, 0xa364, reg);
1486
1487 /* Step 3a: Read bits 17:0 of register 0x9c20 */
1488 reg = OS_REG_READ(ah, 0x9c20);
1489 reg &= 0x0003ffff;
1490 ath_hal_printf(ah,
1491 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n",
1492 __func__, reg);
1493
1494 /* Step 1b: Set bit 23 of register 0xa360 to 0 */
1495 reg = OS_REG_READ(ah, 0xa360);
1496 reg &= ~0x00800000;
1497 OS_REG_WRITE(ah, 0xa360, reg);
1498
1499 /* Step 2b: Set register 0xa364 to 0x1400 */
1500 reg = 0x1400;
1501 OS_REG_WRITE(ah, 0xa364, reg);
1502
1503 /* Step 3b: Read bits 17:0 of register 0x9c20 */
1504 reg = OS_REG_READ(ah, 0x9c20);
1505 reg &= 0x0003ffff;
1506 ath_hal_printf(ah,
1507 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n",
1508 __func__, reg);
1509
1510 /* Step 1c: Set bit 23 of register 0xa360 to 0 */
1511 reg = OS_REG_READ(ah, 0xa360);
1512 reg &= ~0x00800000;
1513 OS_REG_WRITE(ah, 0xa360, reg);
1514
1515 /* Step 2c: Set register 0xa364 to 0x3C00 */
1516 reg = 0x3c00;
1517 OS_REG_WRITE(ah, 0xa364, reg);
1518
1519 /* Step 3c: Read bits 17:0 of register 0x9c20 */
1520 reg = OS_REG_READ(ah, 0x9c20);
1521 reg &= 0x0003ffff;
1522 ath_hal_printf(ah,
1523 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n",
1524 __func__, reg);
1525
1526 /* Step 1d: Set bit 24 of register 0xa360 to 0 */
1527 reg = OS_REG_READ(ah, 0xa360);
1528 reg &= ~0x001040000;
1529 OS_REG_WRITE(ah, 0xa360, reg);
1530
1531 /* Step 2d: Set register 0xa364 to 0x5005D */
1532 reg = 0x5005D;
1533 OS_REG_WRITE(ah, 0xa364, reg);
1534
1535 /* Step 3d: Read bits 17:0 of register 0xa368 */
1536 reg = OS_REG_READ(ah, 0xa368);
1537 reg &= 0x0003ffff;
1538 ath_hal_printf(ah,
1539 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n",
1540 __func__, reg);
1541
1542 /* Step 1e: Set bit 24 of register 0xa360 to 0 */
1543 reg = OS_REG_READ(ah, 0xa360);
1544 reg &= ~0x001040000;
1545 OS_REG_WRITE(ah, 0xa360, reg);
1546
1547 /* Step 2e: Set register 0xa364 to 0x7005D */
1548 reg = 0x7005D;
1549 OS_REG_WRITE(ah, 0xa364, reg);
1550
1551 /* Step 3e: Read bits 17:0 of register 0xa368 */
1552 reg = OS_REG_READ(ah, 0xa368);
1553 reg &= 0x0003ffff;
1554 ath_hal_printf(ah,
1555 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n",
1556 __func__, reg);
1557
1558 /* Step 1f: Set bit 24 of register 0xa360 to 0 */
1559 reg = OS_REG_READ(ah, 0xa360);
1560 reg &= ~0x001000000;
1561 reg |= 0x40000;
1562 OS_REG_WRITE(ah, 0xa360, reg);
1563
1564 /* Step 2f: Set register 0xa364 to 0x3005D */
1565 reg = 0x3005D;
1566 OS_REG_WRITE(ah, 0xa364, reg);
1567
1568 /* Step 3f: Read bits 17:0 of register 0xa368 */
1569 reg = OS_REG_READ(ah, 0xa368);
1570 reg &= 0x0003ffff;
1571 ath_hal_printf(ah,
1572 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n",
1573 __func__, reg);
1574
1575 /* Step 1g: Set bit 24 of register 0xa360 to 0 */
1576 reg = OS_REG_READ(ah, 0xa360);
1577 reg &= ~0x001000000;
1578 reg |= 0x40000;
1579 OS_REG_WRITE(ah, 0xa360, reg);
1580
1581 /* Step 2g: Set register 0xa364 to 0x6005D */
1582 reg = 0x6005D;
1583 OS_REG_WRITE(ah, 0xa364, reg);
1584
1585 /* Step 3g: Read bits 17:0 of register 0xa368 */
1586 reg = OS_REG_READ(ah, 0xa368);
1587 reg &= 0x0003ffff;
1588 ath_hal_printf(ah,
1589 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n",
1590 __func__, reg);
1591 #endif /* AH_DEBUG */
1592 }
1593
1594 /*
1595 * Return the busy for rx_frame, rx_clear, and tx_frame
1596 */
1597 u_int32_t
ar9300_get_mib_cycle_counts_pct(struct ath_hal * ah,u_int32_t * rxc_pcnt,u_int32_t * rxf_pcnt,u_int32_t * txf_pcnt)1598 ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt,
1599 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt)
1600 {
1601 struct ath_hal_9300 *ahp = AH9300(ah);
1602 u_int32_t good = 1;
1603
1604 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT);
1605 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT);
1606 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT);
1607 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1608
1609 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) {
1610 /*
1611 * Cycle counter wrap (or initial call); it's not possible
1612 * to accurately calculate a value because the registers
1613 * right shift rather than wrap--so punt and return 0.
1614 */
1615 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1616 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1617 good = 0;
1618 } else {
1619 u_int32_t cc_d = cc - ahp->ah_cycles;
1620 u_int32_t rc_d = rc - ahp->ah_rx_clear;
1621 u_int32_t rf_d = rf - ahp->ah_rx_frame;
1622 u_int32_t tf_d = tf - ahp->ah_tx_frame;
1623
1624 if (cc_d != 0) {
1625 *rxc_pcnt = rc_d * 100 / cc_d;
1626 *rxf_pcnt = rf_d * 100 / cc_d;
1627 *txf_pcnt = tf_d * 100 / cc_d;
1628 } else {
1629 good = 0;
1630 }
1631 }
1632
1633 ahp->ah_cycles = cc;
1634 ahp->ah_rx_frame = rf;
1635 ahp->ah_rx_clear = rc;
1636 ahp->ah_tx_frame = tf;
1637
1638 return good;
1639 }
1640
1641 /*
1642 * Return approximation of extension channel busy over an time interval
1643 * 0% (clear) -> 100% (busy)
1644 * -1 for invalid estimate
1645 */
1646 uint32_t
ar9300_get_11n_ext_busy(struct ath_hal * ah)1647 ar9300_get_11n_ext_busy(struct ath_hal *ah)
1648 {
1649 /*
1650 * Overflow condition to check before multiplying to get %
1651 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1652 */
1653 #define OVERFLOW_LIMIT 0x28F5C28
1654 #define ERROR_CODE -1
1655
1656 struct ath_hal_9300 *ahp = AH9300(ah);
1657 u_int32_t busy = 0; /* percentage */
1658 int8_t busyper = 0;
1659 u_int32_t cycle_count, ctl_busy, ext_busy;
1660
1661 /* cycle_count will always be the first to wrap; therefore, read it last
1662 * This sequence of reads is not atomic, and MIB counter wrap
1663 * could happen during it ?
1664 */
1665 ctl_busy = OS_REG_READ(ah, AR_RCCNT);
1666 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT);
1667 cycle_count = OS_REG_READ(ah, AR_CCCNT);
1668
1669 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) ||
1670 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy))
1671 {
1672 /*
1673 * Cycle counter wrap (or initial call); it's not possible
1674 * to accurately calculate a value because the registers
1675 * right shift rather than wrap--so punt and return 0.
1676 */
1677 busyper = ERROR_CODE;
1678 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1679 "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1680 } else {
1681 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count;
1682 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy;
1683
1684 /*
1685 * Compute extension channel busy percentage
1686 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100
1687 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0
1688 * Will never happen, since (ext_busy_delta < cycle_delta) always,
1689 * and shift necessitated by large ext_busy_delta.
1690 * Due to timing difference to read the registers and counter overflow,
1691 * it may still happen that cycle_delta >> 7 = 0.
1692 *
1693 */
1694 if (cycle_delta) {
1695 if (ext_busy_delta > OVERFLOW_LIMIT) {
1696 if (cycle_delta >> 7) {
1697 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7);
1698 } else {
1699 busyper = ERROR_CODE;
1700 }
1701 } else {
1702 busy = (ext_busy_delta * 100) / cycle_delta;
1703 }
1704 } else {
1705 busyper = ERROR_CODE;
1706 }
1707
1708 if (busy > 100) {
1709 busy = 100;
1710 }
1711 if ( busyper != ERROR_CODE ) {
1712 busyper = busy;
1713 }
1714 }
1715
1716 ahp->ah_cycle_count = cycle_count;
1717 ahp->ah_ctl_busy = ctl_busy;
1718 ahp->ah_ext_busy = ext_busy;
1719
1720 return busyper;
1721 #undef OVERFLOW_LIMIT
1722 #undef ERROR_CODE
1723 }
1724
1725 /* BB Panic Watchdog declarations */
1726 #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1727 #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1728
1729 void
ar9300_config_bb_panic_watchdog(struct ath_hal * ah)1730 ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1731 {
1732 #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1733 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1734 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1735 u_int32_t val, idle_count;
1736
1737 if (idle_tmo_ms != 0) {
1738 /* enable IRQ, disable chip-reset for BB panic */
1739 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1740 AR_PHY_BB_PANIC_CNTL2_MASK;
1741 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1742 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1743 /* bound limit to 10 secs */
1744 if (idle_tmo_ms > 10000) {
1745 idle_tmo_ms = 10000;
1746 }
1747 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1748 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1749 } else {
1750 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1751 }
1752 /*
1753 * enable panic in non-IDLE mode,
1754 * disable in IDLE mode,
1755 * set idle time-out
1756 */
1757
1758 // EV92527 : Enable IDLE mode panic
1759
1760 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1761 AR_PHY_BB_PANIC_NON_IDLE_ENABLE |
1762 AR_PHY_BB_PANIC_IDLE_ENABLE |
1763 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) |
1764 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2)));
1765 } else {
1766 /* disable IRQ, disable chip-reset for BB panic */
1767 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1768 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1769 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1770 /* disable panic in non-IDLE mode, disable in IDLE mode */
1771 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1772 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1773 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1774 }
1775
1776 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1777 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1778 #undef HAL_BB_PANIC_IDLE_TIME_OUT
1779 }
1780
1781
1782 void
ar9300_handle_bb_panic(struct ath_hal * ah)1783 ar9300_handle_bb_panic(struct ath_hal *ah)
1784 {
1785 u_int32_t status;
1786 /*
1787 * we want to avoid printing in ISR context so we save
1788 * panic watchdog status to be printed later in DPC context
1789 */
1790 AH9300(ah)->ah_bb_panic_last_status = status =
1791 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1792 /*
1793 * panic watchdog timer should reset on status read
1794 * but to make sure we write 0 to the watchdog status bit
1795 */
1796 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1797 }
1798
1799 int
ar9300_get_bb_panic_info(struct ath_hal * ah,struct hal_bb_panic_info * bb_panic)1800 ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1801 {
1802 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1803
1804 /*
1805 * For signature 04000539 do not print anything.
1806 * This is a very common occurence as a compromise between
1807 * BB Panic and AH_FALSE detects (EV71009). It indicates
1808 * radar hang, which can be cleared by reprogramming
1809 * radar related register and does not requre a chip reset
1810 */
1811
1812 /* Suppress BB Status mesg following signature */
1813 switch (bb_panic->status) {
1814 case 0x04000539:
1815 case 0x04008009:
1816 case 0x04000b09:
1817 case 0x1300000a:
1818 return -1;
1819 }
1820
1821 bb_panic->tsf = ar9300_get_tsf32(ah);
1822 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS);
1823 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG);
1824 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM);
1825 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM);
1826 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM);
1827 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM);
1828 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM);
1829 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM);
1830 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM);
1831 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1);
1832 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1833 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1834 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1835 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1836 &bb_panic->rxc_pcnt,
1837 &bb_panic->rxf_pcnt,
1838 &bb_panic->txf_pcnt);
1839
1840 if (ah->ah_config.ath_hal_show_bb_panic) {
1841 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1842 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1843 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1844 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1845 bb_panic->wd, bb_panic->det, bb_panic->rdar,
1846 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1847 bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1848 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1849 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2);
1850 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n",
1851 bb_panic->phy_gen_ctrl);
1852 if (bb_panic->cycles) {
1853 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, "
1854 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt,
1855 bb_panic->rxf_pcnt, bb_panic->txf_pcnt);
1856 }
1857 ath_hal_printf(ah, "==== BB update: done ====\n\n");
1858 }
1859
1860 return 0; //The returned data will be stored for athstats to retrieve it
1861 }
1862
1863 /* set the reason for HAL reset */
1864 void
ar9300_set_hal_reset_reason(struct ath_hal * ah,u_int8_t resetreason)1865 ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1866 {
1867 AH9300(ah)->ah_reset_reason = resetreason;
1868 }
1869
1870 /*
1871 * Configure 20/40 operation
1872 *
1873 * 20/40 = joint rx clear (control and extension)
1874 * 20 = rx clear (control)
1875 *
1876 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1877 * when changing from 20/40 => 20 only
1878 */
1879 void
ar9300_set_11n_mac2040(struct ath_hal * ah,HAL_HT_MACMODE mode)1880 ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1881 {
1882 u_int32_t macmode;
1883
1884 /* Configure MAC for 20/40 operation */
1885 if (mode == HAL_HT_MACMODE_2040 &&
1886 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1887 macmode = AR_2040_JOINED_RX_CLEAR;
1888 } else {
1889 macmode = 0;
1890 }
1891 OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1892 }
1893
1894 /*
1895 * Get Rx clear (control/extension channel)
1896 *
1897 * Returns active low (busy) for ctrl/ext channel
1898 * Owl 2.0
1899 */
1900 HAL_HT_RXCLEAR
ar9300_get_11n_rx_clear(struct ath_hal * ah)1901 ar9300_get_11n_rx_clear(struct ath_hal *ah)
1902 {
1903 HAL_HT_RXCLEAR rxclear = 0;
1904 u_int32_t val;
1905
1906 val = OS_REG_READ(ah, AR_DIAG_SW);
1907
1908 /* control channel */
1909 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) {
1910 rxclear |= HAL_RX_CLEAR_CTL_LOW;
1911 }
1912 /* extension channel */
1913 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) {
1914 rxclear |= HAL_RX_CLEAR_EXT_LOW;
1915 }
1916 return rxclear;
1917 }
1918
1919 /*
1920 * Set Rx clear (control/extension channel)
1921 *
1922 * Useful for forcing the channel to appear busy for
1923 * debugging/diagnostics
1924 * Owl 2.0
1925 */
1926 void
ar9300_set_11n_rx_clear(struct ath_hal * ah,HAL_HT_RXCLEAR rxclear)1927 ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
1928 {
1929 /* control channel */
1930 if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
1931 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1932 } else {
1933 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1934 }
1935 /* extension channel */
1936 if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
1937 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1938 } else {
1939 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1940 }
1941 }
1942
1943
1944 /*
1945 * HAL support code for force ppm tracking workaround.
1946 */
1947
1948 u_int32_t
ar9300_ppm_get_rssi_dump(struct ath_hal * ah)1949 ar9300_ppm_get_rssi_dump(struct ath_hal *ah)
1950 {
1951 u_int32_t retval;
1952 u_int32_t off1;
1953 u_int32_t off2;
1954
1955 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1956 off1 = 0x2000;
1957 off2 = 0x1000;
1958 } else {
1959 off1 = 0x1000;
1960 off2 = 0x2000;
1961 }
1962
1963 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) |
1964 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) |
1965 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16);
1966
1967 return retval;
1968 }
1969
1970 u_int32_t
ar9300_ppm_force(struct ath_hal * ah)1971 ar9300_ppm_force(struct ath_hal *ah)
1972 {
1973 u_int32_t data_fine;
1974 u_int32_t data4;
1975 //u_int32_t off1;
1976 //u_int32_t off2;
1977 HAL_BOOL signed_val = AH_FALSE;
1978
1979 // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1980 // off1 = 0x2000;
1981 // off2 = 0x1000;
1982 // } else {
1983 // off1 = 0x1000;
1984 // off2 = 0x2000;
1985 // }
1986 data_fine =
1987 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK &
1988 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF);
1989
1990 /*
1991 * bit [11-0] is new ppm value. bit 11 is the signed bit.
1992 * So check value from bit[10:0].
1993 * Now get the abs val of the ppm value read in bit[0:11].
1994 * After that do bound check on abs value.
1995 * if value is off limit, CAP the value and and restore signed bit.
1996 */
1997 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1998 {
1999 /* get the positive value */
2000 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
2001 signed_val = AH_TRUE;
2002 }
2003 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
2004 {
2005 HALDEBUG(ah, HAL_DEBUG_REGIO,
2006 "%s Correcting ppm out of range %x\n",
2007 __func__, (data_fine & 0x7ff));
2008 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
2009 }
2010 /*
2011 * Restore signed value if changed above.
2012 * Use typecast to avoid compilation errors
2013 */
2014 if (signed_val) {
2015 data_fine = (-(int32_t)data_fine) &
2016 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
2017 }
2018
2019 /* write value */
2020 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) &
2021 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
2022 OS_REG_WRITE(ah, AR_PHY_TIMING2,
2023 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM);
2024
2025 return data_fine;
2026 }
2027
2028 void
ar9300_ppm_un_force(struct ath_hal * ah)2029 ar9300_ppm_un_force(struct ath_hal *ah)
2030 {
2031 u_int32_t data4;
2032
2033 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM;
2034 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4);
2035 }
2036
2037 u_int32_t
ar9300_ppm_arm_trigger(struct ath_hal * ah)2038 ar9300_ppm_arm_trigger(struct ath_hal *ah)
2039 {
2040 u_int32_t val;
2041 u_int32_t ret;
2042
2043 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY);
2044 ret = OS_REG_READ(ah, AR_TSF_L32);
2045 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY,
2046 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK);
2047
2048 /* return low word of TSF at arm time */
2049 return ret;
2050 }
2051
2052 int
ar9300_ppm_get_trigger(struct ath_hal * ah)2053 ar9300_ppm_get_trigger(struct ath_hal *ah)
2054 {
2055 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) &
2056 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK)
2057 {
2058 /* has not triggered yet, return AH_FALSE */
2059 return 0;
2060 }
2061
2062 /* else triggered, return AH_TRUE */
2063 return 1;
2064 }
2065
2066 void
ar9300_mark_phy_inactive(struct ath_hal * ah)2067 ar9300_mark_phy_inactive(struct ath_hal *ah)
2068 {
2069 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2070 }
2071
2072 /* DEBUG */
2073 u_int32_t
ar9300_ppm_get_force_state(struct ath_hal * ah)2074 ar9300_ppm_get_force_state(struct ath_hal *ah)
2075 {
2076 return
2077 OS_REG_READ(ah, AR_PHY_TIMING2) &
2078 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
2079 }
2080
2081 /*
2082 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
2083 */
2084 HAL_BOOL
ar9300_get_mib_cycle_counts(struct ath_hal * ah,HAL_SURVEY_SAMPLE * hs)2085 ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
2086 {
2087 /*
2088 * XXX FreeBSD todo: reimplement this
2089 */
2090 #if 0
2091 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2092 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
2093 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
2094 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2095 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
2096 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
2097 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
2098 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
2099 #endif
2100 return AH_FALSE;
2101 }
2102
2103 void
ar9300_clear_mib_counters(struct ath_hal * ah)2104 ar9300_clear_mib_counters(struct ath_hal *ah)
2105 {
2106 u_int32_t reg_val;
2107
2108 reg_val = OS_REG_READ(ah, AR_MIBC);
2109 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
2110 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
2111 }
2112
2113
2114 /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
2115 HAL_BOOL
ar9300_set_rifs_delay(struct ath_hal * ah,HAL_BOOL enable)2116 ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2117 {
2118 struct ath_hal_9300 *ahp = AH9300(ah);
2119 HAL_CHANNEL_INTERNAL *ichan =
2120 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2121 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2122 u_int32_t tmp = 0;
2123
2124 if (enable) {
2125 if (ahp->ah_rifs_enabled == AH_TRUE) {
2126 return AH_TRUE;
2127 }
2128
2129 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2130 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2131 ahp->ah_rifs_reg[1]);
2132
2133 ahp->ah_rifs_enabled = AH_TRUE;
2134 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg));
2135 } else {
2136 if (ahp->ah_rifs_enabled == AH_TRUE) {
2137 ahp->ah_rifs_reg[0] = OS_REG_READ(ah,
2138 AR_PHY_SEARCH_START_DELAY);
2139 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2140 }
2141 /* Change rifs init delay to 0 */
2142 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2143 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2144 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2145 if (is_chan_2g) {
2146 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2147 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2148 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2149 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2150 }
2151 } else {
2152 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2153 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2154 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2155 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2156 }
2157 }
2158
2159 ahp->ah_rifs_enabled = AH_FALSE;
2160 }
2161 return AH_TRUE;
2162
2163 } /* ar9300_set_rifs_delay () */
2164
2165 /* Set the current RIFS Rx setting */
2166 HAL_BOOL
ar9300_set_11n_rx_rifs(struct ath_hal * ah,HAL_BOOL enable)2167 ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable)
2168 {
2169 /* Non-Owl 11n chips */
2170 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) {
2171 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) {
2172 return ar9300_set_rifs_delay(ah, enable);
2173 }
2174 return AH_FALSE;
2175 }
2176
2177 return AH_TRUE;
2178 } /* ar9300_set_11n_rx_rifs () */
2179
2180 static hal_mac_hangs_t
ar9300_compare_dbg_hang(struct ath_hal * ah,mac_dbg_regs_t mac_dbg,hal_mac_hang_check_t hang_check,hal_mac_hangs_t hangs,u_int8_t * dcu_chain)2181 ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg,
2182 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain)
2183 {
2184 int i = 0;
2185 hal_mac_hangs_t found_hangs = 0;
2186
2187 if (hangs & dcu_chain_state) {
2188 for (i = 0; i < 6; i++) {
2189 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) ==
2190 hang_check.dcu_chain_state)
2191 {
2192 found_hangs |= dcu_chain_state;
2193 *dcu_chain = i;
2194 }
2195 }
2196 for (i = 0; i < 4; i++) {
2197 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) ==
2198 hang_check.dcu_chain_state)
2199 {
2200 found_hangs |= dcu_chain_state;
2201 *dcu_chain = i + 6;
2202 }
2203 }
2204 }
2205
2206 if (hangs & dcu_complete_state) {
2207 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) {
2208 found_hangs |= dcu_complete_state;
2209 }
2210 }
2211
2212 return found_hangs;
2213
2214 } /* end - ar9300_compare_dbg_hang */
2215
2216 #define NUM_STATUS_READS 50
2217 HAL_BOOL
ar9300_detect_mac_hang(struct ath_hal * ah)2218 ar9300_detect_mac_hang(struct ath_hal *ah)
2219 {
2220 struct ath_hal_9300 *ahp = AH9300(ah);
2221 mac_dbg_regs_t mac_dbg;
2222 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0};
2223 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state);
2224 int i = 0;
2225 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val;
2226
2227 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) {
2228 return AH_FALSE;
2229 }
2230
2231 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg));
2232
2233 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2234 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2235 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2236
2237 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n",
2238 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
2239 mac_dbg.dma_dbg_6);
2240
2241 if (hang_sig1 !=
2242 ar9300_compare_dbg_hang(ah, mac_dbg,
2243 hang_sig1_val, hang_sig1, &dcu_chain))
2244 {
2245 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n");
2246 return AH_FALSE;
2247 }
2248
2249 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain);
2250 shift_val *= 5;
2251
2252 for (i = 1; i <= NUM_STATUS_READS; i++) {
2253 if (dcu_chain < 6) {
2254 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2255 current_dcu_chain_state =
2256 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f);
2257 } else {
2258 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2259 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f);
2260 }
2261 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2262
2263 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state)
2264 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) {
2265 return AH_FALSE;
2266 }
2267 }
2268 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__,
2269 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]);
2270 ahp->ah_hang[MAC_HANG_SIG1]++;
2271 return AH_TRUE;
2272
2273 } /* end - ar9300_detect_mac_hang */
2274
2275 /* Determine if the baseband is hung by reading the Observation Bus Register */
2276 HAL_BOOL
ar9300_detect_bb_hang(struct ath_hal * ah)2277 ar9300_detect_bb_hang(struct ath_hal *ah)
2278 {
2279 #define N(a) (sizeof(a) / sizeof(a[0]))
2280 struct ath_hal_9300 *ahp = AH9300(ah);
2281 u_int32_t hang_sig = 0;
2282 int i = 0;
2283 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times
2284 *
2285 * 4 known BB hang signatures -
2286 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
2287 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52
2288 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18
2289 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
2290 * Rx State (bits 20-24) is 0x7.
2291 */
2292 hal_hw_hang_check_t hang_list [] =
2293 {
2294 /* Offset Reg Value Reg Mask Hang Offset */
2295 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1},
2296 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2},
2297 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3},
2298 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4}
2299 };
2300
2301 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR |
2302 HAL_DFS_BB_HANG_WAR |
2303 HAL_RX_STUCK_LOW_BB_HANG_WAR))) {
2304 return AH_FALSE;
2305 }
2306
2307 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1);
2308 for (i = 1; i <= NUM_STATUS_READS; i++) {
2309 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) {
2310 return AH_FALSE;
2311 }
2312 }
2313
2314 for (i = 0; i < N(hang_list); i++) {
2315 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) {
2316 ahp->ah_hang[hang_list[i].hang_offset]++;
2317 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d "
2318 "sig3count=%d sig4count=%d\n", __func__,
2319 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2],
2320 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]);
2321 return AH_TRUE;
2322 }
2323 }
2324
2325 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! "
2326 "<0x806c>=0x%x\n", __func__, hang_sig);
2327
2328 return AH_FALSE;
2329
2330 #undef N
2331 } /* end - ar9300_detect_bb_hang () */
2332
2333 #undef NUM_STATUS_READS
2334
2335 HAL_STATUS
ar9300_select_ant_config(struct ath_hal * ah,u_int32_t cfg)2336 ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2337 {
2338 struct ath_hal_9300 *ahp = AH9300(ah);
2339 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2340 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2341 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2342 u_int16_t ant_config;
2343 u_int32_t hal_num_ant_config;
2344
2345 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2346 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2347
2348 if (cfg < hal_num_ant_config) {
2349 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2350 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2351 return HAL_OK;
2352 }
2353 }
2354
2355 return HAL_EINVAL;
2356 }
2357
2358 /*
2359 * Functions to get/set DCS mode
2360 */
2361 void
ar9300_set_dcs_mode(struct ath_hal * ah,u_int32_t mode)2362 ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2363 {
2364 AH9300(ah)->ah_dcs_enable = mode;
2365 }
2366
2367 u_int32_t
ar9300_get_dcs_mode(struct ath_hal * ah)2368 ar9300_get_dcs_mode(struct ath_hal *ah)
2369 {
2370 return AH9300(ah)->ah_dcs_enable;
2371 }
2372
2373 #if ATH_BT_COEX
2374 void
ar9300_set_bt_coex_info(struct ath_hal * ah,HAL_BT_COEX_INFO * btinfo)2375 ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2376 {
2377 struct ath_hal_9300 *ahp = AH9300(ah);
2378
2379 ahp->ah_bt_module = btinfo->bt_module;
2380 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2381 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
2382 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority;
2383 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active;
2384 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity;
2385 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant;
2386 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation;
2387 }
2388
2389 void
ar9300_bt_coex_config(struct ath_hal * ah,HAL_BT_COEX_CONFIG * btconf)2390 ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf)
2391 {
2392 struct ath_hal_9300 *ahp = AH9300(ah);
2393 HAL_BOOL rx_clear_polarity;
2394
2395 /*
2396 * For Kiwi and Osprey, the polarity of rx_clear is active high.
2397 * The bt_rxclear_polarity flag from ath_dev needs to be inverted.
2398 */
2399 rx_clear_polarity = !btconf->bt_rxclear_polarity;
2400
2401 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) |
2402 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) |
2403 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
2404 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
2405 SM(btconf->bt_mode, AR_BT_MODE) |
2406 SM(btconf->bt_quiet_collision, AR_BT_QUIET) |
2407 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) |
2408 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) |
2409 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME);
2410
2411 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR);
2412
2413 if (ahp->ah_bt_coex_single_ant == AH_FALSE) {
2414 /* Enable ACK to go out even though BT has higher priority. */
2415 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
2416 }
2417 }
2418
2419 void
ar9300_bt_coex_set_qcu_thresh(struct ath_hal * ah,int qnum)2420 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum)
2421 {
2422 struct ath_hal_9300 *ahp = AH9300(ah);
2423
2424 /* clear the old value, then set the new value */
2425 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH;
2426 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH);
2427 }
2428
2429 void
ar9300_bt_coex_set_weights(struct ath_hal * ah,u_int32_t stomp_type)2430 ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
2431 {
2432 struct ath_hal_9300 *ahp = AH9300(ah);
2433
2434 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT;
2435 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT;
2436 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT;
2437 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT;
2438
2439 switch (stomp_type) {
2440 case HAL_BT_COEX_STOMP_ALL:
2441 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
2442 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
2443 break;
2444 case HAL_BT_COEX_STOMP_LOW:
2445 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
2446 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
2447 break;
2448 case HAL_BT_COEX_STOMP_ALL_FORCE:
2449 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0;
2450 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1;
2451 break;
2452 case HAL_BT_COEX_STOMP_LOW_FORCE:
2453 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0;
2454 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1;
2455 break;
2456 case HAL_BT_COEX_STOMP_NONE:
2457 case HAL_BT_COEX_NO_STOMP:
2458 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
2459 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
2460 break;
2461 default:
2462 /* There is a force_weight from registry */
2463 ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
2464 ahp->ah_bt_coex_wlan_weight[1] = stomp_type;
2465 break;
2466 }
2467 }
2468
2469 void
ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal * ah,u_int32_t thresh)2470 ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh)
2471 {
2472 struct ath_hal_9300 *ahp = AH9300(ah);
2473
2474 /* clear the old value, then set the new value */
2475 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH;
2476 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2477 }
2478
2479 static void
ar9300_bt_coex_antenna_diversity(struct ath_hal * ah,u_int32_t value)2480 ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2481 {
2482 struct ath_hal_9300 *ahp = AH9300(ah);
2483 #if ATH_ANT_DIV_COMB
2484 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2485 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2486 #endif
2487
2488 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called, value=%d\n", __func__, value);
2489
2490 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2491 {
2492 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2493 {
2494 /* Config antenna diversity */
2495 #if ATH_ANT_DIV_COMB
2496 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan);
2497 #endif
2498 }
2499 }
2500 }
2501
2502
2503 void
ar9300_bt_coex_set_parameter(struct ath_hal * ah,u_int32_t type,u_int32_t value)2504 ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
2505 u_int32_t value)
2506 {
2507 struct ath_hal_9300 *ahp = AH9300(ah);
2508 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2509
2510 switch (type) {
2511 case HAL_BT_COEX_SET_ACK_PWR:
2512 if (value) {
2513 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2514 } else {
2515 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2516 }
2517 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2518 ahpriv->ah_extraTxPow, 0);
2519 break;
2520
2521 case HAL_BT_COEX_ANTENNA_DIVERSITY:
2522 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
2523 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2524 if (value) {
2525 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2526 }
2527 else {
2528 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2529 }
2530 ar9300_bt_coex_antenna_diversity(ah, value);
2531 }
2532 break;
2533 case HAL_BT_COEX_LOWER_TX_PWR:
2534 if (value) {
2535 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2536 }
2537 else {
2538 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2539 }
2540 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2541 ahpriv->ah_extraTxPow, 0);
2542 break;
2543 #if ATH_SUPPORT_MCI
2544 case HAL_BT_COEX_MCI_MAX_TX_PWR:
2545 if ((ah->ah_config.ath_hal_mci_config &
2546 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2547 {
2548 if (value) {
2549 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2550 ahp->ah_mci_concur_tx_en = AH_TRUE;
2551 }
2552 else {
2553 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2554 ahp->ah_mci_concur_tx_en = AH_FALSE;
2555 }
2556 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2557 ahpriv->ah_extraTxPow, 0);
2558 }
2559 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2560 ahp->ah_mci_concur_tx_en);
2561 break;
2562 case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2563 if (value) {
2564 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2565 }
2566 else {
2567 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2568 }
2569 break;
2570 #endif
2571 default:
2572 break;
2573 }
2574 }
2575
2576 void
ar9300_bt_coex_disable(struct ath_hal * ah)2577 ar9300_bt_coex_disable(struct ath_hal *ah)
2578 {
2579 struct ath_hal_9300 *ahp = AH9300(ah);
2580
2581 /* Always drive rx_clear_external output as 0 */
2582 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2583 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2584
2585 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2586 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2587 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2588 }
2589
2590 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
2591 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
2592 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
2593 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
2594 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
2595 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
2596 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
2597 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
2598
2599 ahp->ah_bt_coex_enabled = AH_FALSE;
2600 }
2601
2602 int
ar9300_bt_coex_enable(struct ath_hal * ah)2603 ar9300_bt_coex_enable(struct ath_hal *ah)
2604 {
2605 struct ath_hal_9300 *ahp = AH9300(ah);
2606
2607 /* Program coex mode and weight registers to actually enable coex */
2608 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode);
2609 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2);
2610 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
2611 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
2612 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]);
2613 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]);
2614 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]);
2615 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]);
2616
2617 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) {
2618 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);
2619 } else {
2620 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);
2621 }
2622
2623 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2624 if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2625 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2626 } else {
2627 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2628 }
2629
2630 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2631 /* For 3-wire, configure the desired GPIO port for rx_clear */
2632 ath_hal_gpioCfgOutput(ah,
2633 ahp->ah_wlan_active_gpio_select,
2634 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2635 }
2636 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2637 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2638 {
2639 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2640 ath_hal_gpioCfgOutput(ah,
2641 ahp->ah_wlan_active_gpio_select,
2642 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2643 }
2644
2645 /*
2646 * Enable a weak pull down on BT_ACTIVE.
2647 * When BT device is disabled, BT_ACTIVE might be floating.
2648 */
2649 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU),
2650 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)),
2651 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2)));
2652
2653 ahp->ah_bt_coex_enabled = AH_TRUE;
2654
2655 return 0;
2656 }
2657
ar9300_get_bt_active_gpio(struct ath_hal * ah,u_int32_t reg)2658 u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg)
2659 {
2660 return 0;
2661 }
2662
ar9300_get_wlan_active_gpio(struct ath_hal * ah,u_int32_t reg,u_int32_t bOn)2663 u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn)
2664 {
2665 return bOn;
2666 }
2667
2668 void
ar9300_init_bt_coex(struct ath_hal * ah)2669 ar9300_init_bt_coex(struct ath_hal *ah)
2670 {
2671 struct ath_hal_9300 *ahp = AH9300(ah);
2672
2673 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2674 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2675 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
2676 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
2677
2678 /*
2679 * Set input mux for bt_prority_async and
2680 * bt_active_async to GPIO pins
2681 */
2682 OS_REG_RMW_FIELD(ah,
2683 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2684 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2685 ahp->ah_bt_active_gpio_select);
2686 OS_REG_RMW_FIELD(ah,
2687 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2688 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2689 ahp->ah_bt_priority_gpio_select);
2690
2691 /* Configure the desired GPIO ports for input */
2692 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2693 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2694
2695 if (ahp->ah_bt_coex_enabled) {
2696 ar9300_bt_coex_enable(ah);
2697 } else {
2698 ar9300_bt_coex_disable(ah);
2699 }
2700 }
2701 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2702 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2703 {
2704 /* 2-wire */
2705 if (ahp->ah_bt_coex_enabled) {
2706 /* Connect bt_active_async to baseband */
2707 OS_REG_CLR_BIT(ah,
2708 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2709 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
2710 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
2711 OS_REG_SET_BIT(ah,
2712 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2713 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
2714
2715 /*
2716 * Set input mux for bt_prority_async and
2717 * bt_active_async to GPIO pins
2718 */
2719 OS_REG_RMW_FIELD(ah,
2720 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2721 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2722 ahp->ah_bt_active_gpio_select);
2723
2724 /* Configure the desired GPIO ports for input */
2725 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2726
2727 /* Enable coexistence on initialization */
2728 ar9300_bt_coex_enable(ah);
2729 }
2730 }
2731 #if ATH_SUPPORT_MCI
2732 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2733 if (ahp->ah_bt_coex_enabled) {
2734 ar9300_mci_bt_coex_enable(ah);
2735 }
2736 else {
2737 ar9300_mci_bt_coex_disable(ah);
2738 }
2739 }
2740 #endif /* ATH_SUPPORT_MCI */
2741 }
2742
2743 #endif /* ATH_BT_COEX */
2744
ar9300_set_proxy_sta(struct ath_hal * ah,HAL_BOOL enable)2745 HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable)
2746 {
2747 u_int32_t val;
2748 int wasp_mm_rev;
2749
2750 #define AR_SOC_RST_REVISION_ID 0xB8060090
2751 #define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
2752 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) &
2753 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >>
2754 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT;
2755 #undef AR_SOC_RST_REVISION_ID
2756 #undef REG_READ
2757
2758 /*
2759 * Azimuth (ProxySTA) Mode is only supported correctly by
2760 * Peacock or WASP 1.3.0.1 or later (hopefully) chips.
2761 *
2762 * Enable this feature for Scorpion at this time. The silicon
2763 * still needs to be validated.
2764 */
2765 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) &&
2766 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) &&
2767 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) &&
2768 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) ||
2769 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 &&
2770 wasp_mm_rev >= 0 /* 1 */))))
2771 {
2772 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, "
2773 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n",
2774 __func__, AH_PRIVATE((ah))->ah_macVersion,
2775 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev);
2776 return HAL_ENOTSUPP;
2777 }
2778
2779 OS_REG_WRITE(ah,
2780 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996);
2781
2782 /* turn on mode bit[24] for proxy sta */
2783 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2,
2784 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA);
2785
2786 val = OS_REG_READ(ah, AR_AZIMUTH_MODE);
2787 if (enable) {
2788 val |= AR_AZIMUTH_KEY_SEARCH_AD1 |
2789 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2790 AR_AZIMUTH_BA_USES_AD1;
2791 /* turn off filter pass hold (bit 9) */
2792 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD;
2793 } else {
2794 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 |
2795 AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2796 AR_AZIMUTH_BA_USES_AD1);
2797 }
2798 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val);
2799
2800 /* enable promiscous mode */
2801 OS_REG_WRITE(ah, AR_RX_FILTER,
2802 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM);
2803 /* enable promiscous in azimuth mode */
2804 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE);
2805 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE);
2806
2807 /* turn on filter pass hold (bit 9) */
2808 OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2809 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2810
2811 return HAL_OK;
2812 }
2813
2814 #if 0
2815 void ar9300_mat_enable(struct ath_hal *ah, int enable)
2816 {
2817 /*
2818 * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2819 * mitigation and turn on key search always for better performance.
2820 */
2821 struct ath_hal_9300 *ahp = AH9300(ah);
2822 struct ath_hal_private *ap = AH_PRIVATE(ah);
2823
2824 ahp->ah_intr_mitigation_rx = !enable;
2825 if (ahp->ah_intr_mitigation_rx) {
2826 /*
2827 * Enable Interrupt Mitigation for Rx.
2828 * If no build-specific limits for the rx interrupt mitigation
2829 * timer have been specified, use conservative defaults.
2830 */
2831 #ifndef AH_RIMT_VAL_LAST
2832 #define AH_RIMT_LAST_MICROSEC 500
2833 #endif
2834 #ifndef AH_RIMT_VAL_FIRST
2835 #define AH_RIMT_FIRST_MICROSEC 2000
2836 #endif
2837 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2838 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2839 } else {
2840 OS_REG_WRITE(ah, AR_RIMT, 0);
2841 }
2842
2843 ahp->ah_enable_keysearch_always = !!enable;
2844 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2845 }
2846 #endif
2847
ar9300_enable_tpc(struct ath_hal * ah)2848 void ar9300_enable_tpc(struct ath_hal *ah)
2849 {
2850 u_int32_t val = 0;
2851
2852 ah->ah_config.ath_hal_desc_tpc = 1;
2853
2854 /* Enable TPC */
2855 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2856
2857 /*
2858 * Disable per chain power reduction since we are already
2859 * accounting for this in our calculations
2860 */
2861 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB);
2862 if (AR_SREV_WASP(ah)) {
2863 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2864 val & AR_PHY_POWER_TX_SUB_2_DISABLE);
2865 } else {
2866 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2867 val & AR_PHY_POWER_TX_SUB_3_DISABLE);
2868 }
2869 }
2870
2871
2872 /*
2873 * ar9300_force_tsf_sync
2874 * This function forces the TSF sync to the given bssid, this is implemented
2875 * as a temp hack to get the AoW demo, and is primarily used in the WDS client
2876 * mode of operation, where we sync the TSF to RootAP TSF values
2877 */
2878 void
ar9300_force_tsf_sync(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)2879 ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid,
2880 u_int16_t assoc_id)
2881 {
2882 ar9300_set_operating_mode(ah, HAL_M_STA);
2883 ar9300_write_associd(ah, bssid, assoc_id);
2884 }
2885
ar9300_chk_rssi_update_tx_pwr(struct ath_hal * ah,int rssi)2886 void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
2887 {
2888 struct ath_hal_9300 *ahp = AH9300(ah);
2889 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val;
2890 u_int32_t temp_powertx_rate9_reg_val;
2891 int8_t olpc_power_offset = 0;
2892 int8_t tmp_olpc_val = 0;
2893 HAL_RSSI_TX_POWER old_greentx_status;
2894 u_int8_t target_power_val_t[ar9300_rate_size];
2895 int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2896
2897 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2898 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2899 return;
2900 }
2901
2902 old_greentx_status = AH9300(ah)->green_tx_status;
2903 if (ahp->ah_hw_green_tx_enable) {
2904 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2905 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2906 } else {
2907 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2908 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2909 }
2910
2911 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2912 && (rssi > tmp_rss1_thr1))
2913 {
2914 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2915 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2916 }
2917 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2918 && (rssi > tmp_rss1_thr2))
2919 {
2920 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2921 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2922 }
2923 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2924 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2925 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2926 }
2927 }
2928
2929 /* If status is not change, don't do anything */
2930 if (old_greentx_status == AH9300(ah)->green_tx_status) {
2931 return;
2932 }
2933
2934 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2935 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2936 && AR_SREV_POSEIDON(ah))
2937 {
2938 if (ahp->ah_hw_green_tx_enable) {
2939 switch (AH9300(ah)->green_tx_status) {
2940 case HAL_RSSI_TX_POWER_SHORT:
2941 /* 1. TxPower Config */
2942 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2943 sizeof(target_power_val_t));
2944 /* 1.1 Store OLPC Delta Calibration Offset*/
2945 olpc_power_offset = 0;
2946 /* 2. Store OB/DB */
2947 /* 3. Store TPC settting */
2948 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2949 SM(14, AR_TPC_CTS) |
2950 SM(14, AR_TPC_CHIRP) |
2951 SM(14, AR_TPC_RPT));
2952 /* 4. Store BB_powertx_rate9 value */
2953 temp_powertx_rate9_reg_val =
2954 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE;
2955 break;
2956 case HAL_RSSI_TX_POWER_MIDDLE:
2957 /* 1. TxPower Config */
2958 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle,
2959 sizeof(target_power_val_t));
2960 /* 1.1 Store OLPC Delta Calibration Offset*/
2961 olpc_power_offset = 0;
2962 /* 2. Store OB/DB */
2963 /* 3. Store TPC settting */
2964 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) |
2965 SM(18, AR_TPC_CTS) |
2966 SM(18, AR_TPC_CHIRP) |
2967 SM(18, AR_TPC_RPT));
2968 /* 4. Store BB_powertx_rate9 value */
2969 temp_powertx_rate9_reg_val =
2970 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE;
2971 break;
2972 case HAL_RSSI_TX_POWER_LONG:
2973 default:
2974 /* 1. TxPower Config */
2975 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2976 sizeof(target_power_val_t));
2977 /* 1.1 Store OLPC Delta Calibration Offset*/
2978 olpc_power_offset = 0;
2979 /* 2. Store OB/DB1/DB2 */
2980 /* 3. Store TPC settting */
2981 temp_tcp_reg_val =
2982 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2983 /* 4. Store BB_powertx_rate9 value */
2984 temp_powertx_rate9_reg_val =
2985 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2986 break;
2987 }
2988 } else {
2989 switch (AH9300(ah)->green_tx_status) {
2990 case HAL_RSSI_TX_POWER_SHORT:
2991 /* 1. TxPower Config */
2992 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2993 sizeof(target_power_val_t));
2994 /* 1.1 Store OLPC Delta Calibration Offset*/
2995 olpc_power_offset =
2996 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2997 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2998 /* 2. Store OB/DB */
2999 temp_obdb_reg_val =
3000 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3001 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
3002 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
3003 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
3004 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
3005 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
3006 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
3007 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
3008 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
3009 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
3010 SM(WB225_OB_GREEN_TX_SHORT_VALUE,
3011 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
3012 /* 3. Store TPC settting */
3013 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) |
3014 SM(6, AR_TPC_CTS) |
3015 SM(6, AR_TPC_CHIRP) |
3016 SM(6, AR_TPC_RPT));
3017 /* 4. Store BB_powertx_rate9 value */
3018 temp_powertx_rate9_reg_val =
3019 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE;
3020 break;
3021 case HAL_RSSI_TX_POWER_MIDDLE:
3022 /* 1. TxPower Config */
3023 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
3024 sizeof(target_power_val_t));
3025 /* 1.1 Store OLPC Delta Calibration Offset*/
3026 olpc_power_offset =
3027 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
3028 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3029 /* 2. Store OB/DB */
3030 temp_obdb_reg_val =
3031 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3032 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
3033 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
3034 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
3035 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
3036 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
3037 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3038 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
3039 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3040 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
3041 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3042 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
3043 /* 3. Store TPC settting */
3044 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
3045 SM(14, AR_TPC_CTS) |
3046 SM(14, AR_TPC_CHIRP) |
3047 SM(14, AR_TPC_RPT));
3048 /* 4. Store BB_powertx_rate9 value */
3049 temp_powertx_rate9_reg_val =
3050 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE;
3051 break;
3052 case HAL_RSSI_TX_POWER_LONG:
3053 default:
3054 /* 1. TxPower Config */
3055 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
3056 sizeof(target_power_val_t));
3057 /* 1.1 Store OLPC Delta Calibration Offset*/
3058 olpc_power_offset =
3059 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
3060 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3061 /* 2. Store OB/DB1/DB2 */
3062 temp_obdb_reg_val =
3063 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3064 /* 3. Store TPC settting */
3065 temp_tcp_reg_val =
3066 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
3067 /* 4. Store BB_powertx_rate9 value */
3068 temp_powertx_rate9_reg_val =
3069 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
3070 break;
3071 }
3072 }
3073 /* 1.1 Do OLPC Delta Calibration Offset */
3074 tmp_olpc_val =
3075 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
3076 tmp_olpc_val += olpc_power_offset;
3077 OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
3078 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3079 AR_PHY_TPC_OLPC_GAIN_DELTA);
3080
3081 /* 1.2 TxPower Config */
3082 ar9300_transmit_power_reg_write(ah, target_power_val_t);
3083 /* 2. Config OB/DB */
3084 if (!ahp->ah_hw_green_tx_enable) {
3085 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
3086 }
3087 /* 3. config TPC settting */
3088 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
3089 /* 4. config BB_powertx_rate9 value */
3090 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
3091 }
3092 }
3093
3094 #if 0
3095 void
3096 ar9300_get_vow_stats(
3097 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
3098 {
3099 if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
3100 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
3101 }
3102 if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
3103 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
3104 }
3105 if (vow_reg_flags & AR_REG_RX_CLR_CNT) {
3106 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
3107 }
3108 if (vow_reg_flags & AR_REG_CYCLE_CNT) {
3109 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
3110 }
3111 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
3112 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
3113 }
3114 }
3115 #endif
3116
3117 /*
3118 * ar9300_is_skip_paprd_by_greentx
3119 *
3120 * This function check if we need to skip PAPRD tuning
3121 * when GreenTx in specific state.
3122 */
3123 HAL_BOOL
ar9300_is_skip_paprd_by_greentx(struct ath_hal * ah)3124 ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3125 {
3126 if (AR_SREV_POSEIDON(ah) &&
3127 ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3128 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3129 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3130 {
3131 return AH_TRUE;
3132 }
3133 return AH_FALSE;
3134 }
3135
3136 void
ar9300_control_signals_for_green_tx_mode(struct ath_hal * ah)3137 ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
3138 {
3139 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3]
3140 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3]
3141 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3]
3142 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3]
3143 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3]
3144 struct ath_hal_9300 *ahp = AH9300(ah);
3145
3146 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3147 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3148 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0);
3149 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3150 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0);
3151 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3152 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0);
3153 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3154 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0);
3155 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3156 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0);
3157 }
3158 }
3159
ar9300_hwgreentx_set_pal_spare(struct ath_hal * ah,int value)3160 void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value)
3161 {
3162 struct ath_hal_9300 *ahp = AH9300(ah);
3163
3164 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3165 if ((value == 0) || (value == 1)) {
3166 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
3167 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value);
3168 }
3169 }
3170 }
3171
ar9300_reset_hw_beacon_proc_crc(struct ath_hal * ah)3172 void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah)
3173 {
3174 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC);
3175 }
3176
ar9300_get_hw_beacon_rssi(struct ath_hal * ah)3177 int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah)
3178 {
3179 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL);
3180
3181 /* RSSI format is 8.4. Ignore lowest four bits */
3182 val = val >> 4;
3183 return val;
3184 }
3185
ar9300_set_hw_beacon_rssi_threshold(struct ath_hal * ah,u_int32_t rssi_threshold)3186 void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
3187 u_int32_t rssi_threshold)
3188 {
3189 struct ath_hal_9300 *ahp = AH9300(ah);
3190
3191 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold);
3192
3193 /* save value for restoring after chip reset */
3194 ahp->ah_beacon_rssi_threshold = rssi_threshold;
3195 }
3196
ar9300_reset_hw_beacon_rssi(struct ath_hal * ah)3197 void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah)
3198 {
3199 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST);
3200 }
3201
ar9300_set_hw_beacon_proc(struct ath_hal * ah,HAL_BOOL on)3202 void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on)
3203 {
3204 if (on) {
3205 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3206 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3207 }
3208 else {
3209 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3210 AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3211 }
3212 }
3213 /*
3214 * Gets the contents of the specified key cache entry.
3215 */
3216 HAL_BOOL
ar9300_print_keycache(struct ath_hal * ah)3217 ar9300_print_keycache(struct ath_hal *ah)
3218 {
3219
3220 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3221 u_int32_t key0, key1, key2, key3, key4;
3222 u_int32_t mac_hi, mac_lo;
3223 u_int16_t entry = 0;
3224 u_int32_t valid = 0;
3225 u_int32_t key_type;
3226
3227 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3228
3229 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3230 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3231 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3232 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3233 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3234 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3235
3236 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3237
3238 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry));
3239 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
3240
3241 if (mac_hi & AR_KEYTABLE_VALID) {
3242 valid = 1;
3243 } else {
3244 valid = 0;
3245 }
3246
3247 if ((mac_hi != 0) && (mac_lo != 0)) {
3248 mac_hi &= ~0x8000;
3249 mac_hi <<= 1;
3250 mac_hi |= ((mac_lo & (1 << 31) )) >> 31;
3251 mac_lo <<= 1;
3252 }
3253
3254 ath_hal_printf(ah,
3255 "%03d "
3256 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
3257 " %02d %02d "
3258 "%02x:%02x:%02x:%02x:%02x:%02x \n",
3259 entry,
3260 (key0 << 24) >> 24, (key0 << 16) >> 24,
3261 (key0 << 8) >> 24, key0 >> 24,
3262 (key1 << 24) >> 24, (key1 << 16) >> 24,
3263 //(key1 << 8) >> 24, key1 >> 24,
3264 (key2 << 24) >> 24, (key2 << 16) >> 24,
3265 (key2 << 8) >> 24, key2 >> 24,
3266 (key3 << 24) >> 24, (key3 << 16) >> 24,
3267 //(key3 << 8) >> 24, key3 >> 24,
3268 (key4 << 24) >> 24, (key4 << 16) >> 24,
3269 (key4 << 8) >> 24, key4 >> 24,
3270 valid, key_type,
3271 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3272 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3273 }
3274
3275 return AH_TRUE;
3276 }
3277
3278 /* enable/disable smart antenna mode */
3279 HAL_BOOL
ar9300_set_smart_antenna(struct ath_hal * ah,HAL_BOOL enable)3280 ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3281 {
3282 struct ath_hal_9300 *ahp = AH9300(ah);
3283
3284 if (enable) {
3285 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3286 } else {
3287 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3288 }
3289
3290 /* if scropion and smart antenna is enabled, write swcom1 with 0x440
3291 * and swcom2 with 0
3292 * FIXME Ideally these registers need to be made read from caldata.
3293 * Until the calibration team gets them, keep them along with board
3294 * configuration.
3295 */
3296 if (enable && AR_SREV_SCORPION(ah) &&
3297 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) {
3298
3299 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440);
3300 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0);
3301 }
3302
3303 ahp->ah_smartantenna_enable = enable;
3304 return 1;
3305 }
3306
3307 #ifdef ATH_TX99_DIAG
3308 #ifndef ATH_SUPPORT_HTC
3309 void
ar9300_tx99_channel_pwr_update(struct ath_hal * ah,HAL_CHANNEL * c,u_int32_t txpower)3310 ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3311 u_int32_t txpower)
3312 {
3313 #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3314 static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3315 int32_t i;
3316
3317 /* The max power is limited to 63 */
3318 if (txpower <= AR9300_MAX_RATE_POWER) {
3319 for (i = 0; i < ar9300_rate_size; i++) {
3320 p_pwr_array[i] = txpower;
3321 }
3322 } else {
3323 for (i = 0; i < ar9300_rate_size; i++) {
3324 p_pwr_array[i] = AR9300_MAX_RATE_POWER;
3325 }
3326 }
3327
3328 OS_REG_WRITE(ah, 0xa458, 0);
3329
3330 /* Write the OFDM power per rate set */
3331 /* 6 (LSB), 9, 12, 18 (MSB) */
3332 OS_REG_WRITE(ah, 0xa3c0,
3333 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24)
3334 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16)
3335 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8)
3336 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3337 );
3338 /* 24 (LSB), 36, 48, 54 (MSB) */
3339 OS_REG_WRITE(ah, 0xa3c4,
3340 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24)
3341 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16)
3342 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8)
3343 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3344 );
3345
3346 /* Write the CCK power per rate set */
3347 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3348 OS_REG_WRITE(ah, 0xa3c8,
3349 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24)
3350 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16)
3351 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */
3352 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3353 );
3354 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3355 OS_REG_WRITE(ah, 0xa3cc,
3356 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24)
3357 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16)
3358 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8)
3359 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3360 );
3361
3362 /* Write the HT20 power per rate set */
3363 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3364 OS_REG_WRITE(ah, 0xa3d0,
3365 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24)
3366 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16)
3367 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)
3368 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)
3369 );
3370
3371 /* 6 (LSB), 7, 12, 13 (MSB) */
3372 OS_REG_WRITE(ah, 0xa3d4,
3373 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24)
3374 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16)
3375 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8)
3376 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0)
3377 );
3378
3379 /* 14 (LSB), 15, 20, 21 */
3380 OS_REG_WRITE(ah, 0xa3e4,
3381 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24)
3382 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16)
3383 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8)
3384 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0)
3385 );
3386
3387 /* Mixed HT20 and HT40 rates */
3388 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3389 OS_REG_WRITE(ah, 0xa3e8,
3390 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24)
3391 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16)
3392 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8)
3393 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0)
3394 );
3395
3396 /* Write the HT40 power per rate set */
3397 /* correct PAR difference between HT40 and HT20/LEGACY */
3398 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3399 OS_REG_WRITE(ah, 0xa3d8,
3400 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24)
3401 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16)
3402 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8)
3403 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)
3404 );
3405
3406 /* 6 (LSB), 7, 12, 13 (MSB) */
3407 OS_REG_WRITE(ah, 0xa3dc,
3408 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24)
3409 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16)
3410 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8)
3411 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0)
3412 );
3413
3414 /* 14 (LSB), 15, 20, 21 */
3415 OS_REG_WRITE(ah, 0xa3ec,
3416 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24)
3417 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16)
3418 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8)
3419 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0)
3420 );
3421 #undef PWR_MAS
3422 }
3423
3424 void
ar9300_tx99_chainmsk_setup(struct ath_hal * ah,int tx_chainmask)3425 ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
3426 {
3427 if (tx_chainmask == 0x5) {
3428 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3429 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3430 }
3431 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
3432 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
3433
3434 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3435 if (tx_chainmask == 0x5) {
3436 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3437 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3438 }
3439 }
3440
3441 void
ar9300_tx99_set_single_carrier(struct ath_hal * ah,int tx_chain_mask,int chtype)3442 ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask,
3443 int chtype)
3444 {
3445 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff);
3446 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1));
3447 OS_REG_WRITE(ah, 0xa350,
3448 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13));
3449
3450 /* 11G mode */
3451 if (!chtype) {
3452 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3453 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2));
3454 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3455 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3456 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3457 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3458 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3459 | (0x1 << 26) | (0x7 << 24))
3460 & ~(0x1 << 22));
3461 } else {
3462 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3463 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3464 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3465 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3466 | (0x1 << 26) | (0x7 << 24))
3467 & ~(0x1 << 22));
3468 }
3469
3470 /* chain zero */
3471 if ((tx_chain_mask & 0x01) == 0x01) {
3472 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3473 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3474 | (0x1 << 31) | (0x5 << 15)
3475 | (0x3 << 9)) & ~(0x1 << 27)
3476 & ~(0x1 << 12));
3477 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3478 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3479 | (0x1 << 12) | (0x1 << 10)
3480 | (0x1 << 9) | (0x1 << 8)
3481 | (0x1 << 7)) & ~(0x1 << 11));
3482 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3483 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3484 | (0x1 << 29) | (0x1 << 25)
3485 | (0x1 << 23) | (0x1 << 19)
3486 | (0x1 << 10) | (0x1 << 9)
3487 | (0x1 << 8) | (0x1 << 3))
3488 & ~(0x1 << 28)& ~(0x1 << 24)
3489 & ~(0x1 << 22)& ~(0x1 << 7));
3490 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3491 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3492 | (0x1 << 23))& ~(0x1 << 21));
3493 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3494 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3495 | (0x1 << 12) | (0x1 << 10)
3496 | (0x1 << 9) | (0x1 << 8)
3497 | (0x1 << 6) | (0x1 << 5)
3498 | (0x1 << 4) | (0x1 << 3)
3499 | (0x1 << 2));
3500 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3501 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3502 }
3503 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3504 /* chain one */
3505 if ((tx_chain_mask & 0x02) == 0x02 ) {
3506 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3507 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3508 | (0x1 << 31) | (0x5 << 15)
3509 | (0x3 << 9)) & ~(0x1 << 27)
3510 & ~(0x1 << 12));
3511 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3512 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3513 | (0x1 << 12) | (0x1 << 10)
3514 | (0x1 << 9) | (0x1 << 8)
3515 | (0x1 << 7)) & ~(0x1 << 11));
3516 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3517 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3518 | (0x1 << 29) | (0x1 << 25)
3519 | (0x1 << 23) | (0x1 << 19)
3520 | (0x1 << 10) | (0x1 << 9)
3521 | (0x1 << 8) | (0x1 << 3))
3522 & ~(0x1 << 28)& ~(0x1 << 24)
3523 & ~(0x1 << 22)& ~(0x1 << 7));
3524 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3525 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3526 | (0x1 << 23))& ~(0x1 << 21));
3527 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3528 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3529 | (0x1 << 12) | (0x1 << 10)
3530 | (0x1 << 9) | (0x1 << 8)
3531 | (0x1 << 6) | (0x1 << 5)
3532 | (0x1 << 4) | (0x1 << 3)
3533 | (0x1 << 2));
3534 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3535 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3536 }
3537 }
3538 if (AR_SREV_OSPREY(ah)) {
3539 /* chain two */
3540 if ((tx_chain_mask & 0x04) == 0x04 ) {
3541 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3542 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3543 | (0x1 << 31) | (0x5 << 15)
3544 | (0x3 << 9)) & ~(0x1 << 27)
3545 & ~(0x1 << 12));
3546 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3547 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3548 | (0x1 << 12) | (0x1 << 10)
3549 | (0x1 << 9) | (0x1 << 8)
3550 | (0x1 << 7)) & ~(0x1 << 11));
3551 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3552 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3553 | (0x1 << 29) | (0x1 << 25)
3554 | (0x1 << 23) | (0x1 << 19)
3555 | (0x1 << 10) | (0x1 << 9)
3556 | (0x1 << 8) | (0x1 << 3))
3557 & ~(0x1 << 28)& ~(0x1 << 24)
3558 & ~(0x1 << 22)& ~(0x1 << 7));
3559 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3560 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3561 | (0x1 << 23))& ~(0x1 << 21));
3562 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3563 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3564 | (0x1 << 12) | (0x1 << 10)
3565 | (0x1 << 9) | (0x1 << 8)
3566 | (0x1 << 6) | (0x1 << 5)
3567 | (0x1 << 4) | (0x1 << 3)
3568 | (0x1 << 2));
3569 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3570 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3571 }
3572 }
3573
3574 OS_REG_WRITE(ah, 0xa28c, 0x11111);
3575 OS_REG_WRITE(ah, 0xa288, 0x111);
3576 } else {
3577 /* chain zero */
3578 if ((tx_chain_mask & 0x01) == 0x01) {
3579 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3580 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3581 | (0x1 << 31) | (0x1 << 27)
3582 | (0x3 << 23) | (0x1 << 19)
3583 | (0x1 << 15) | (0x3 << 9))
3584 & ~(0x1 << 12));
3585 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3586 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3587 | (0x1 << 12) | (0x1 << 10)
3588 | (0x1 << 9) | (0x1 << 8)
3589 | (0x1 << 7) | (0x1 << 3)
3590 | (0x1 << 2) | (0x1 << 1))
3591 & ~(0x1 << 11)& ~(0x1 << 0));
3592 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3593 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3594 | (0x1 << 29) | (0x1 << 25)
3595 | (0x1 << 23) | (0x1 << 19)
3596 | (0x1 << 10) | (0x1 << 9)
3597 | (0x1 << 8) | (0x1 << 3))
3598 & ~(0x1 << 28)& ~(0x1 << 24)
3599 & ~(0x1 << 22)& ~(0x1 << 7));
3600 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3601 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3602 | (0x1 << 23))& ~(0x1 << 21));
3603 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2,
3604 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
3605 | (0x3 << 3) | (0x3 << 0));
3606 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3,
3607 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
3608 | (0x3 << 29) | (0x3 << 26)
3609 | (0x2 << 23) | (0x2 << 20)
3610 | (0x2 << 17))& ~(0x1 << 14));
3611 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3612 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3613 | (0x1 << 12) | (0x1 << 10)
3614 | (0x1 << 9) | (0x1 << 8)
3615 | (0x1 << 6) | (0x1 << 5)
3616 | (0x1 << 4) | (0x1 << 3)
3617 | (0x1 << 2));
3618 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3619 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3620 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3621 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3622 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3623 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3624 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3625 | (0x1 << 26) | (0x7 << 24)
3626 | (0x3 << 22));
3627 } else {
3628 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3629 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3630 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3631 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3632 | (0x1 << 26) | (0x7 << 24)
3633 | (0x3 << 22));
3634 }
3635
3636 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3637 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3638 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3639 | (0x1 << 3) | (0x1 << 2)
3640 | (0x1 << 1)) & ~(0x1 << 0));
3641 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3642 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3643 | (0x1 << 19) | (0x1 << 3));
3644 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3645 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3646 }
3647 if (AR_SREV_OSPREY(ah)) {
3648 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3649 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3650 | (0x1 << 3) | (0x1 << 2)
3651 | (0x1 << 1)) & ~(0x1 << 0));
3652 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3653 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3654 | (0x1 << 19) | (0x1 << 3));
3655 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3656 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3657 }
3658 }
3659 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3660 /* chain one */
3661 if ((tx_chain_mask & 0x02) == 0x02 ) {
3662 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3663 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3664 | (0x1 << 3) | (0x1 << 2)
3665 | (0x1 << 1)) & ~(0x1 << 0));
3666 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3667 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3668 | (0x1 << 19) | (0x1 << 3));
3669 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3670 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3671 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3672 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3673 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3674 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3675 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3676 | (0x1 << 26) | (0x7 << 24)
3677 | (0x3 << 22));
3678 } else {
3679 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3680 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3681 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3682 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3683 | (0x1 << 26) | (0x7 << 24)
3684 | (0x3 << 22));
3685 }
3686
3687 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3688 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3689 | (0x1 << 31) | (0x1 << 27)
3690 | (0x3 << 23) | (0x1 << 19)
3691 | (0x1 << 15) | (0x3 << 9))
3692 & ~(0x1 << 12));
3693 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3694 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3695 | (0x1 << 12) | (0x1 << 10)
3696 | (0x1 << 9) | (0x1 << 8)
3697 | (0x1 << 7) | (0x1 << 3)
3698 | (0x1 << 2) | (0x1 << 1))
3699 & ~(0x1 << 11)& ~(0x1 << 0));
3700 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3701 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3702 | (0x1 << 29) | (0x1 << 25)
3703 | (0x1 << 23) | (0x1 << 19)
3704 | (0x1 << 10) | (0x1 << 9)
3705 | (0x1 << 8) | (0x1 << 3))
3706 & ~(0x1 << 28)& ~(0x1 << 24)
3707 & ~(0x1 << 22)& ~(0x1 << 7));
3708 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3709 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3710 | (0x1 << 23))& ~(0x1 << 21));
3711 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2,
3712 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
3713 | (0x3 << 3) | (0x3 << 0));
3714 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3,
3715 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
3716 | (0x3 << 29) | (0x3 << 26)
3717 | (0x2 << 23) | (0x2 << 20)
3718 | (0x2 << 17))& ~(0x1 << 14));
3719 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3720 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3721 | (0x1 << 12) | (0x1 << 10)
3722 | (0x1 << 9) | (0x1 << 8)
3723 | (0x1 << 6) | (0x1 << 5)
3724 | (0x1 << 4) | (0x1 << 3)
3725 | (0x1 << 2));
3726 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3727 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3728
3729 if (AR_SREV_OSPREY(ah)) {
3730 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3731 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3732 | (0x1 << 3) | (0x1 << 2)
3733 | (0x1 << 1)) & ~(0x1 << 0));
3734 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3735 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3736 | (0x1 << 19) | (0x1 << 3));
3737 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3738 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3739 }
3740 }
3741 }
3742 if (AR_SREV_OSPREY(ah)) {
3743 /* chain two */
3744 if ((tx_chain_mask & 0x04) == 0x04 ) {
3745 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3746 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3747 | (0x1 << 3) | (0x1 << 2)
3748 | (0x1 << 1)) & ~(0x1 << 0));
3749 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3750 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3751 | (0x1 << 19) | (0x1 << 3));
3752 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3753 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3754 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3755 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3756 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3757 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3758 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3759 | (0x1 << 26) | (0x7 << 24)
3760 | (0x3 << 22));
3761 } else {
3762 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3763 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3764 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3765 OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3766 | (0x1 << 26) | (0x7 << 24)
3767 | (0x3 << 22));
3768 }
3769
3770 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3771 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3772 | (0x1 << 3) | (0x1 << 2)
3773 | (0x1 << 1)) & ~(0x1 << 0));
3774 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3775 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3776 | (0x1 << 19) | (0x1 << 3));
3777 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3778 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3779
3780 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3781 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3782 | (0x1 << 31) | (0x1 << 27)
3783 | (0x3 << 23) | (0x1 << 19)
3784 | (0x1 << 15) | (0x3 << 9))
3785 & ~(0x1 << 12));
3786 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3787 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3788 | (0x1 << 12) | (0x1 << 10)
3789 | (0x1 << 9) | (0x1 << 8)
3790 | (0x1 << 7) | (0x1 << 3)
3791 | (0x1 << 2) | (0x1 << 1))
3792 & ~(0x1 << 11)& ~(0x1 << 0));
3793 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3794 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3795 | (0x1 << 29) | (0x1 << 25)
3796 | (0x1 << 23) | (0x1 << 19)
3797 | (0x1 << 10) | (0x1 << 9)
3798 | (0x1 << 8) | (0x1 << 3))
3799 & ~(0x1 << 28)& ~(0x1 << 24)
3800 & ~(0x1 << 22)& ~(0x1 << 7));
3801 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3802 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3803 | (0x1 << 23))& ~(0x1 << 21));
3804 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2,
3805 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
3806 | (0x3 << 3) | (0x3 << 0));
3807 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3,
3808 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
3809 | (0x3 << 29) | (0x3 << 26)
3810 | (0x2 << 23) | (0x2 << 20)
3811 | (0x2 << 17))& ~(0x1 << 14));
3812 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3813 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3814 | (0x1 << 12) | (0x1 << 10)
3815 | (0x1 << 9) | (0x1 << 8)
3816 | (0x1 << 6) | (0x1 << 5)
3817 | (0x1 << 4) | (0x1 << 3)
3818 | (0x1 << 2));
3819 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3820 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3821 }
3822 }
3823
3824 OS_REG_WRITE(ah, 0xa28c, 0x22222);
3825 OS_REG_WRITE(ah, 0xa288, 0x222);
3826 }
3827 }
3828
3829 void
ar9300_tx99_start(struct ath_hal * ah,u_int8_t * data)3830 ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data)
3831 {
3832 u_int32_t val;
3833 u_int32_t qnum = (u_int32_t)data;
3834
3835 /* Disable AGC to A2 */
3836 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR));
3837 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
3838
3839 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */
3840 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */
3841 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
3842 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
3843 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
3844 /* 200 ok for HT20, 400 ok for HT40 */
3845 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
3846 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
3847
3848 /* set QCU modes to early termination */
3849 val = OS_REG_READ(ah, AR_QMISC(qnum));
3850 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
3851 }
3852
3853 void
ar9300_tx99_stop(struct ath_hal * ah)3854 ar9300_tx99_stop(struct ath_hal *ah)
3855 {
3856 /* this should follow the setting of start */
3857 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR);
3858 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
3859 }
3860 #endif /* ATH_TX99_DIAG */
3861 #endif /* ATH_SUPPORT_HTC */
3862
3863 HAL_BOOL
ar9300Get3StreamSignature(struct ath_hal * ah)3864 ar9300Get3StreamSignature(struct ath_hal *ah)
3865 {
3866 return AH_FALSE;
3867 }
3868
3869 HAL_BOOL
ar9300ForceVCS(struct ath_hal * ah)3870 ar9300ForceVCS(struct ath_hal *ah)
3871 {
3872 return AH_FALSE;
3873 }
3874
3875 HAL_BOOL
ar9300SetDfs3StreamFix(struct ath_hal * ah,u_int32_t val)3876 ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3877 {
3878 return AH_FALSE;
3879 }
3880
3881 static u_int32_t
ar9300_read_loc_timer(struct ath_hal * ah)3882 ar9300_read_loc_timer(struct ath_hal *ah)
3883 {
3884
3885 return OS_REG_READ(ah, AR_LOC_TIMER_REG);
3886 }
3887
3888 HAL_BOOL
ar9300_set_ctl_pwr(struct ath_hal * ah,u_int8_t * ctl_array)3889 ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array)
3890 {
3891 struct ath_hal_9300 *ahp = AH9300(ah);
3892 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom;
3893 u_int8_t *ctl_index;
3894 u_int32_t offset = 0;
3895
3896 if (!ctl_array)
3897 return AH_FALSE;
3898
3899 /* copy 2G ctl freqbin and power data */
3900 ctl_index = p_eep_data->ctl_index_2g;
3901 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array,
3902 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */
3903 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */
3904 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) +
3905 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G));
3906
3907
3908 /* copy 2G ctl freqbin and power data */
3909 ctl_index = p_eep_data->ctl_index_5g;
3910 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset,
3911 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */
3912 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */
3913
3914 return AH_FALSE;
3915 }
3916
3917 void
ar9300_set_txchainmaskopt(struct ath_hal * ah,u_int8_t mask)3918 ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask)
3919 {
3920 struct ath_hal_9300 *ahp = AH9300(ah);
3921
3922 /* optional txchainmask should be subset of primary txchainmask */
3923 if ((mask & ahp->ah_tx_chainmask) != mask) {
3924 ahp->ah_tx_chainmaskopt = 0;
3925 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask);
3926 return;
3927 }
3928
3929 ahp->ah_tx_chainmaskopt = mask;
3930 }
3931