xref: /freebsd/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2004 Atheros Communications, Inc.
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 #include "opt_ah.h"
20 
21 #include "ah.h"
22 #include "ah_internal.h"
23 #include "ah_desc.h"
24 
25 #include "ar5210/ar5210.h"
26 #include "ar5210/ar5210reg.h"
27 #include "ar5210/ar5210desc.h"
28 
29 /*
30  * Get the RXDP.
31  */
32 uint32_t
ar5210GetRxDP(struct ath_hal * ah,HAL_RX_QUEUE qtype)33 ar5210GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)
34 {
35 
36 	HALASSERT(qtype == HAL_RX_QUEUE_HP);
37 	return OS_REG_READ(ah, AR_RXDP);
38 }
39 
40 /*
41  * Set the RxDP.
42  */
43 void
ar5210SetRxDP(struct ath_hal * ah,uint32_t rxdp,HAL_RX_QUEUE qtype)44 ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
45 {
46 
47 	HALASSERT(qtype == HAL_RX_QUEUE_HP);
48 	OS_REG_WRITE(ah, AR_RXDP, rxdp);
49 }
50 
51 /*
52  * Set Receive Enable bits.
53  */
54 void
ar5210EnableReceive(struct ath_hal * ah)55 ar5210EnableReceive(struct ath_hal *ah)
56 {
57 	OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
58 }
59 
60 /*
61  * Stop Receive at the DMA engine
62  */
63 HAL_BOOL
ar5210StopDmaReceive(struct ath_hal * ah)64 ar5210StopDmaReceive(struct ath_hal *ah)
65 {
66 	int i;
67 
68 	OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);	/* Set receive disable bit */
69 	for (i = 0; i < 1000; i++) {
70 		if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
71 			return AH_TRUE;
72 		OS_DELAY(10);
73 	}
74 #ifdef AH_DEBUG
75 	ath_hal_printf(ah, "ar5210: dma receive failed to stop in 10ms\n");
76 	ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
77 	ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW));
78 #endif
79 	return AH_FALSE;
80 }
81 
82 /*
83  * Start Transmit at the PCU engine (unpause receive)
84  */
85 void
ar5210StartPcuReceive(struct ath_hal * ah,HAL_BOOL is_scanning)86 ar5210StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning)
87 {
88 	ar5210UpdateDiagReg(ah,
89 		OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
90 }
91 
92 /*
93  * Stop Transmit at the PCU engine (pause receive)
94  */
95 void
ar5210StopPcuReceive(struct ath_hal * ah)96 ar5210StopPcuReceive(struct ath_hal *ah)
97 {
98 	ar5210UpdateDiagReg(ah,
99 		OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
100 }
101 
102 /*
103  * Set multicast filter 0 (lower 32-bits)
104  *			   filter 1 (upper 32-bits)
105  */
106 void
ar5210SetMulticastFilter(struct ath_hal * ah,uint32_t filter0,uint32_t filter1)107 ar5210SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
108 {
109 	OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
110 	OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
111 }
112 
113 /*
114  * Clear multicast filter by index
115  */
116 HAL_BOOL
ar5210ClrMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)117 ar5210ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
118 {
119 	uint32_t val;
120 
121 	if (ix >= 64)
122 		return AH_FALSE;
123 	if (ix >= 32) {
124 		val = OS_REG_READ(ah, AR_MCAST_FIL1);
125 		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
126 	} else {
127 		val = OS_REG_READ(ah, AR_MCAST_FIL0);
128 		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
129 	}
130 	return AH_TRUE;
131 }
132 
133 /*
134  * Set multicast filter by index
135  */
136 HAL_BOOL
ar5210SetMulticastFilterIndex(struct ath_hal * ah,uint32_t ix)137 ar5210SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
138 {
139 	uint32_t val;
140 
141 	if (ix >= 64)
142 		return AH_FALSE;
143 	if (ix >= 32) {
144 		val = OS_REG_READ(ah, AR_MCAST_FIL1);
145 		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
146 	} else {
147 		val = OS_REG_READ(ah, AR_MCAST_FIL0);
148 		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
149 	}
150 	return AH_TRUE;
151 }
152 
153 /*
154  * Return the receive packet filter.
155  */
156 uint32_t
ar5210GetRxFilter(struct ath_hal * ah)157 ar5210GetRxFilter(struct ath_hal *ah)
158 {
159 	/* XXX can't be sure if promiscuous mode is set because of PHYRADAR */
160 	return OS_REG_READ(ah, AR_RX_FILTER);
161 }
162 
163 /*
164  * Turn off/on bits in the receive packet filter.
165  */
166 void
ar5210SetRxFilter(struct ath_hal * ah,uint32_t bits)167 ar5210SetRxFilter(struct ath_hal *ah, uint32_t bits)
168 {
169 	if (bits & HAL_RX_FILTER_PHYRADAR) {
170 		/* must enable promiscuous mode to get radar */
171 		bits = (bits &~ HAL_RX_FILTER_PHYRADAR) | AR_RX_FILTER_PROMISCUOUS;
172 	}
173 	OS_REG_WRITE(ah, AR_RX_FILTER, bits);
174 }
175 
176 /*
177  * Initialize RX descriptor, by clearing the status and clearing
178  * the size.  This is not strictly HW dependent, but we want the
179  * control and status words to be opaque above the hal.
180  */
181 HAL_BOOL
ar5210SetupRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t size,u_int flags)182 ar5210SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
183 	uint32_t size, u_int flags)
184 {
185 	struct ar5210_desc *ads = AR5210DESC(ds);
186 
187 	(void) flags;
188 
189 	ads->ds_ctl0 = 0;
190 	ads->ds_ctl1 = size & AR_BufLen;
191 	if (ads->ds_ctl1 != size) {
192 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
193 		    __func__, size);
194 		return AH_FALSE;
195 	}
196 	if (flags & HAL_RXDESC_INTREQ)
197 		ads->ds_ctl1 |= AR_RxInterReq;
198 	ads->ds_status0 = ads->ds_status1 = 0;
199 
200 	return AH_TRUE;
201 }
202 
203 /*
204  * Process an RX descriptor, and return the status to the caller.
205  * Copy some hardware specific items into the software portion
206  * of the descriptor.
207  *
208  * NB: the caller is responsible for validating the memory contents
209  *     of the descriptor (e.g. flushing any cached copy).
210  */
211 HAL_STATUS
ar5210ProcRxDesc(struct ath_hal * ah,struct ath_desc * ds,uint32_t pa,struct ath_desc * nds,uint64_t tsf,struct ath_rx_status * rs)212 ar5210ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
213 	uint32_t pa, struct ath_desc *nds, uint64_t tsf,
214 	struct ath_rx_status *rs)
215 {
216 	struct ar5210_desc *ads = AR5210DESC(ds);
217 	struct ar5210_desc *ands = AR5210DESC(nds);
218 	uint32_t now, rstamp;
219 
220 	if ((ads->ds_status1 & AR_Done) == 0)
221 		return HAL_EINPROGRESS;
222 	/*
223 	 * Given the use of a self-linked tail be very sure that the hw is
224 	 * done with this descriptor; the hw may have done this descriptor
225 	 * once and picked it up again...make sure the hw has moved on.
226 	 */
227 	if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
228 		return HAL_EINPROGRESS;
229 
230 	rs->rs_datalen = ads->ds_status0 & AR_DataLen;
231 	rstamp = MS(ads->ds_status1, AR_RcvTimestamp);
232 	/*
233 	 * Convert timestamp.  The value in the
234 	 * descriptor is bits [10..22] of the TSF.
235 	 */
236 	now = (OS_REG_READ(ah, AR_TSF_L32) >> 10) & 0xffff;
237 	if ((now & 0x1fff) < rstamp)
238 		rstamp |= (now - 0x2000) & 0xffff;
239 	else
240 		rstamp |= now;
241 	/* NB: keep only 15 bits for consistency w/ other chips */
242 	rs->rs_tstamp = rstamp & 0x7fff;
243 	rs->rs_status = 0;
244 	if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
245 		if (ads->ds_status1 & AR_CRCErr)
246 			rs->rs_status |= HAL_RXERR_CRC;
247 		else if (ads->ds_status1 & AR_DecryptCRCErr)
248 			rs->rs_status |= HAL_RXERR_DECRYPT;
249 		else if (ads->ds_status1 & AR_FIFOOverrun)
250 			rs->rs_status |= HAL_RXERR_FIFO;
251 		else {
252 			rs->rs_status |= HAL_RXERR_PHY;
253 			rs->rs_phyerr =
254 				(ads->ds_status1 & AR_PHYErr) >> AR_PHYErr_S;
255 		}
256 	}
257 	/* XXX what about KeyCacheMiss? */
258 	rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
259 	if (ads->ds_status1 & AR_KeyIdxValid)
260 		rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
261 	else
262 		rs->rs_keyix = HAL_RXKEYIX_INVALID;
263 	/* NB: caller expected to do rate table mapping */
264 	rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
265 	rs->rs_antenna  = (ads->ds_status0 & AR_RcvAntenna) ? 1 : 0;
266 	rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;
267 
268 	return HAL_OK;
269 }
270