1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/bus.h>
30 #include <sys/errno.h>
31 #include <sys/kernel.h>
32 #include <sys/malloc.h>
33 #include <sys/module.h>
34 #include <sys/socket.h>
35 #include <sys/sockio.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
38
39 #include <net/if.h>
40 #include <net/if_var.h>
41 #include <net/if_arp.h>
42 #include <net/ethernet.h>
43 #include <net/if_dl.h>
44 #include <net/if_media.h>
45 #include <net/if_types.h>
46
47 #include <machine/bus.h>
48 #include <dev/iicbus/iic.h>
49 #include <dev/iicbus/iiconf.h>
50 #include <dev/iicbus/iicbus.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53 #include <dev/mdio/mdio.h>
54 #include <dev/clk/clk.h>
55 #include <dev/hwreset/hwreset.h>
56
57 #include <dev/fdt/fdt_common.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
60
61 #include <dev/etherswitch/etherswitch.h>
62
63 #include <dev/etherswitch/ar40xx/ar40xx_var.h>
64 #include <dev/etherswitch/ar40xx/ar40xx_reg.h>
65 #include <dev/etherswitch/ar40xx/ar40xx_hw.h>
66 #include <dev/etherswitch/ar40xx/ar40xx_hw_mib.h>
67
68 #include "mdio_if.h"
69 #include "miibus_if.h"
70 #include "etherswitch_if.h"
71
72
73 #define MIB_DESC(_s , _o, _n) \
74 { \
75 .size = (_s), \
76 .offset = (_o), \
77 .name = (_n), \
78 }
79
80 static const struct ar40xx_mib_desc ar40xx_mibs[] = {
81 MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"),
82 MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"),
83 MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"),
84 MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"),
85 MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"),
86 MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"),
87 MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"),
88 MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"),
89 MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"),
90 MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"),
91 MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"),
92 MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"),
93 MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"),
94 MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"),
95 MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"),
96 MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"),
97 MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"),
98 MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"),
99 MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"),
100 MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"),
101 MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"),
102 MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"),
103 MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"),
104 MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"),
105 MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"),
106 MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"),
107 MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"),
108 MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"),
109 MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"),
110 MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"),
111 MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"),
112 MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"),
113 MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"),
114 MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"),
115 MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"),
116 MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"),
117 MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"),
118 MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"),
119 MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"),
120 };
121
122
123 int
ar40xx_hw_mib_op(struct ar40xx_softc * sc,uint32_t op)124 ar40xx_hw_mib_op(struct ar40xx_softc *sc, uint32_t op)
125 {
126 uint32_t reg;
127 int ret;
128
129 AR40XX_LOCK_ASSERT(sc);
130
131 /* Trigger capturing statistics on all ports */
132 AR40XX_REG_BARRIER_READ(sc);
133 reg = AR40XX_REG_READ(sc, AR40XX_REG_MIB_FUNC);
134 reg &= ~AR40XX_MIB_FUNC;
135 reg |= (op << AR40XX_MIB_FUNC_S);
136 AR40XX_REG_WRITE(sc, AR40XX_REG_MIB_FUNC, reg);
137 AR40XX_REG_BARRIER_WRITE(sc);
138
139 /* Now wait */
140 ret = ar40xx_hw_wait_bit(sc, AR40XX_REG_MIB_FUNC,
141 AR40XX_MIB_BUSY, 0);
142 if (ret != 0) {
143 device_printf(sc->sc_dev,
144 "%s: ERROR: timeout waiting for MIB load\n",
145 __func__);
146 }
147
148 return ret;
149 }
150
151 int
ar40xx_hw_mib_capture(struct ar40xx_softc * sc)152 ar40xx_hw_mib_capture(struct ar40xx_softc *sc)
153 {
154 int ret;
155
156 ret = ar40xx_hw_mib_op(sc, AR40XX_MIB_FUNC_CAPTURE);
157 return (ret);
158 }
159
160 int
ar40xx_hw_mib_flush(struct ar40xx_softc * sc)161 ar40xx_hw_mib_flush(struct ar40xx_softc *sc)
162 {
163 int ret;
164
165 ret = ar40xx_hw_mib_op(sc, AR40XX_MIB_FUNC_FLUSH);
166 return (ret);
167 }
168
169 int
ar40xx_hw_mib_fetch(struct ar40xx_softc * sc,int port)170 ar40xx_hw_mib_fetch(struct ar40xx_softc *sc, int port)
171 {
172 uint64_t val;
173 uint32_t base, reg;
174 int i;
175
176 base = AR40XX_REG_PORT_STATS_START
177 + (AR40XX_REG_PORT_STATS_LEN * port);
178
179 /* For now just print them out, we'll store them later */
180 AR40XX_REG_BARRIER_READ(sc);
181 for (i = 0; i < nitems(ar40xx_mibs); i++) {
182 val = 0;
183
184 val = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset);
185 if (ar40xx_mibs[i].size == 2) {
186 reg = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset + 4);
187 val |= ((uint64_t) reg << 32);
188 }
189
190 device_printf(sc->sc_dev, "%s[%d] = %llu\n", ar40xx_mibs[i].name, port, val);
191 }
192
193 return (0);
194 }
195