xref: /illumos-gate/usr/src/uts/i86pc/io/apix/apix.c (revision 62ce774c77b225680545e57fc633daa60f3ff300)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 /*
26  * Copyright (c) 2010, Intel Corporation.
27  * All rights reserved.
28  * Copyright 2018 Joyent, Inc.
29  */
30 
31 /*
32  * To understand how the apix module interacts with the interrupt subsystem read
33  * the theory statement in uts/i86pc/os/intr.c.
34  */
35 
36 /*
37  * PSMI 1.1 extensions are supported only in 2.6 and later versions.
38  * PSMI 1.2 extensions are supported only in 2.7 and later versions.
39  * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
40  * PSMI 1.5 extensions are supported in Solaris Nevada.
41  * PSMI 1.6 extensions are supported in Solaris Nevada.
42  * PSMI 1.7 extensions are supported in Solaris Nevada.
43  */
44 #define	PSMI_1_7
45 
46 #include <sys/processor.h>
47 #include <sys/time.h>
48 #include <sys/psm.h>
49 #include <sys/smp_impldefs.h>
50 #include <sys/cram.h>
51 #include <sys/acpi/acpi.h>
52 #include <sys/acpica.h>
53 #include <sys/psm_common.h>
54 #include <sys/pit.h>
55 #include <sys/ddi.h>
56 #include <sys/sunddi.h>
57 #include <sys/ddi_impldefs.h>
58 #include <sys/pci.h>
59 #include <sys/promif.h>
60 #include <sys/x86_archext.h>
61 #include <sys/cpc_impl.h>
62 #include <sys/uadmin.h>
63 #include <sys/panic.h>
64 #include <sys/debug.h>
65 #include <sys/archsystm.h>
66 #include <sys/trap.h>
67 #include <sys/machsystm.h>
68 #include <sys/sysmacros.h>
69 #include <sys/cpuvar.h>
70 #include <sys/rm_platter.h>
71 #include <sys/privregs.h>
72 #include <sys/note.h>
73 #include <sys/pci_intr_lib.h>
74 #include <sys/spl.h>
75 #include <sys/clock.h>
76 #include <sys/cyclic.h>
77 #include <sys/dditypes.h>
78 #include <sys/sunddi.h>
79 #include <sys/x_call.h>
80 #include <sys/reboot.h>
81 #include <sys/mach_intr.h>
82 #include <sys/apix.h>
83 #include <sys/apix_irm_impl.h>
84 
85 static int apix_probe();
86 static void apix_init();
87 static void apix_picinit(void);
88 static int apix_intr_enter(int, int *);
89 static void apix_intr_exit(int, int);
90 static void apix_setspl(int);
91 static int apix_disable_intr(processorid_t);
92 static void apix_enable_intr(processorid_t);
93 static int apix_get_clkvect(int);
94 static int apix_get_ipivect(int, int);
95 static void apix_post_cyclic_setup(void *);
96 static int apix_post_cpu_start();
97 static int apix_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *,
98     psm_intr_op_t, int *);
99 
100 /*
101  * Helper functions for apix_intr_ops()
102  */
103 static void apix_redistribute_compute(void);
104 static int apix_get_pending(apix_vector_t *);
105 static apix_vector_t *apix_get_req_vector(ddi_intr_handle_impl_t *, ushort_t);
106 static int apix_get_intr_info(ddi_intr_handle_impl_t *, apic_get_intr_t *);
107 static char *apix_get_apic_type(void);
108 static int apix_intx_get_pending(int);
109 static void apix_intx_set_mask(int irqno);
110 static void apix_intx_clear_mask(int irqno);
111 static int apix_intx_get_shared(int irqno);
112 static void apix_intx_set_shared(int irqno, int delta);
113 static apix_vector_t *apix_intx_xlate_vector(dev_info_t *, int,
114     struct intrspec *);
115 static int apix_intx_alloc_vector(dev_info_t *, int, struct intrspec *);
116 
117 extern int apic_clkinit(int);
118 
119 /* IRM initialization for APIX PSM module */
120 extern void apix_irm_init(void);
121 
122 extern int irm_enable;
123 
124 /*
125  *	Local static data
126  */
127 static struct	psm_ops apix_ops = {
128 	apix_probe,
129 
130 	apix_init,
131 	apix_picinit,
132 	apix_intr_enter,
133 	apix_intr_exit,
134 	apix_setspl,
135 	apix_addspl,
136 	apix_delspl,
137 	apix_disable_intr,
138 	apix_enable_intr,
139 	NULL,			/* psm_softlvl_to_irq */
140 	NULL,			/* psm_set_softintr */
141 
142 	apic_set_idlecpu,
143 	apic_unset_idlecpu,
144 
145 	apic_clkinit,
146 	apix_get_clkvect,
147 	NULL,			/* psm_hrtimeinit */
148 	apic_gethrtime,
149 
150 	apic_get_next_processorid,
151 	apic_cpu_start,
152 	apix_post_cpu_start,
153 	apic_shutdown,
154 	apix_get_ipivect,
155 	apic_send_ipi,
156 
157 	NULL,			/* psm_translate_irq */
158 	NULL,			/* psm_notify_error */
159 	NULL,			/* psm_notify_func */
160 	apic_timer_reprogram,
161 	apic_timer_enable,
162 	apic_timer_disable,
163 	apix_post_cyclic_setup,
164 	apic_preshutdown,
165 	apix_intr_ops,		/* Advanced DDI Interrupt framework */
166 	apic_state,		/* save, restore apic state for S3 */
167 	apic_cpu_ops,		/* CPU control interface. */
168 
169 	apic_get_pir_ipivect,
170 	apic_send_pir_ipi,
171 	apic_cmci_setup
172 };
173 
174 struct psm_ops *psmops = &apix_ops;
175 
176 static struct	psm_info apix_psm_info = {
177 	PSM_INFO_VER01_7,			/* version */
178 	PSM_OWN_EXCLUSIVE,			/* ownership */
179 	&apix_ops,				/* operation */
180 	APIX_NAME,				/* machine name */
181 	"apix MPv1.4 compatible",
182 };
183 
184 static void *apix_hdlp;
185 
186 static int apix_is_enabled = 0;
187 
188 /*
189  * apix_lock is used for cpu selection and vector re-binding
190  */
191 lock_t apix_lock;
192 apix_impl_t *apixs[NCPU];
193 /*
194  * Mapping between device interrupt and the allocated vector. Indexed
195  * by major number.
196  */
197 apix_dev_vector_t **apix_dev_vector;
198 /*
199  * Mapping between device major number and cpu id. It gets used
200  * when interrupt binding policy round robin with affinity is
201  * applied. With that policy, devices with the same major number
202  * will be bound to the same CPU.
203  */
204 processorid_t *apix_major_to_cpu;	/* major to cpu mapping */
205 kmutex_t apix_mutex;	/* for apix_dev_vector & apix_major_to_cpu */
206 
207 int apix_nipis = 16;	/* Maximum number of IPIs */
208 /*
209  * Maximum number of vectors in a CPU that can be used for interrupt
210  * allocation (including IPIs and the reserved vectors).
211  */
212 int apix_cpu_nvectors = APIX_NVECTOR;
213 
214 /* number of CPUs in power-on transition state */
215 static int apic_poweron_cnt = 0;
216 
217 /* gcpu.h */
218 
219 extern void apic_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
220 extern void apic_change_eoi();
221 
222 /*
223  *	This is the loadable module wrapper
224  */
225 
226 int
_init(void)227 _init(void)
228 {
229 	if (apic_coarse_hrtime)
230 		apix_ops.psm_gethrtime = &apic_gettime;
231 	return (psm_mod_init(&apix_hdlp, &apix_psm_info));
232 }
233 
234 int
_fini(void)235 _fini(void)
236 {
237 	return (psm_mod_fini(&apix_hdlp, &apix_psm_info));
238 }
239 
240 int
_info(struct modinfo * modinfop)241 _info(struct modinfo *modinfop)
242 {
243 	return (psm_mod_info(&apix_hdlp, &apix_psm_info, modinfop));
244 }
245 
246 static int
apix_probe()247 apix_probe()
248 {
249 	int rval;
250 
251 	if (apix_enable == 0)
252 		return (PSM_FAILURE);
253 
254 	/*
255 	 * FIXME Temporarily disable apix module on Xen HVM platform due to
256 	 * known hang during boot (see #3605).
257 	 *
258 	 * Please remove when/if the issue is resolved.
259 	 */
260 	if (get_hwenv() & HW_XEN_HVM)
261 		return (PSM_FAILURE);
262 
263 	if (apic_local_mode() == LOCAL_X2APIC) {
264 		/* x2APIC mode activated by BIOS, switch ops */
265 		apic_mode = LOCAL_X2APIC;
266 		apic_change_ops();
267 	}
268 
269 	rval = apic_probe_common(apix_psm_info.p_mach_idstring);
270 	if (rval == PSM_SUCCESS)
271 		apix_is_enabled = 1;
272 	else
273 		apix_is_enabled = 0;
274 	return (rval);
275 }
276 
277 /*
278  * Initialize the data structures needed by pcplusmpx module.
279  * Specifically, the data structures used by addspl() and delspl()
280  * routines.
281  */
282 static void
apix_softinit()283 apix_softinit()
284 {
285 	int i, *iptr;
286 	apix_impl_t *hdlp;
287 	int nproc;
288 
289 	nproc = max(apic_nproc, apic_max_nproc);
290 
291 	hdlp = kmem_zalloc(nproc * sizeof (apix_impl_t), KM_SLEEP);
292 	for (i = 0; i < nproc; i++) {
293 		apixs[i] = &hdlp[i];
294 		apixs[i]->x_cpuid = i;
295 		LOCK_INIT_CLEAR(&apixs[i]->x_lock);
296 	}
297 
298 	/* cpu 0 is always up (for now) */
299 	apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE;
300 
301 	iptr = (int *)&apic_irq_table[0];
302 	for (i = 0; i <= APIC_MAX_VECTOR; i++) {
303 		apic_level_intr[i] = 0;
304 		*iptr++ = 0;
305 	}
306 	mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL);
307 
308 	apix_dev_vector = kmem_zalloc(sizeof (apix_dev_vector_t *) * devcnt,
309 	    KM_SLEEP);
310 
311 	if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) {
312 		apix_major_to_cpu = kmem_zalloc(sizeof (int) * devcnt,
313 		    KM_SLEEP);
314 		for (i = 0; i < devcnt; i++)
315 			apix_major_to_cpu[i] = IRQ_UNINIT;
316 	}
317 
318 	mutex_init(&apix_mutex, NULL, MUTEX_DEFAULT, NULL);
319 }
320 
321 static int
apix_get_pending_spl(void)322 apix_get_pending_spl(void)
323 {
324 	int cpuid = CPU->cpu_id;
325 
326 	return (bsrw_insn(apixs[cpuid]->x_intr_pending));
327 }
328 
329 static uintptr_t
apix_get_intr_handler(int cpu,short vec)330 apix_get_intr_handler(int cpu, short vec)
331 {
332 	apix_vector_t *apix_vector;
333 
334 	ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR);
335 	if (cpu >= apic_nproc || vec >= APIX_NVECTOR)
336 		return (0);
337 
338 	apix_vector = apixs[cpu]->x_vectbl[vec];
339 
340 	return ((uintptr_t)(apix_vector->v_autovect));
341 }
342 
343 static void
apix_init()344 apix_init()
345 {
346 	extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
347 
348 	APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n"));
349 
350 	do_interrupt_common = apix_do_interrupt;
351 	addintr = apix_add_avintr;
352 	remintr = apix_rem_avintr;
353 	get_pending_spl = apix_get_pending_spl;
354 	get_intr_handler = apix_get_intr_handler;
355 	psm_get_localapicid = apic_get_localapicid;
356 	psm_get_ioapicid = apic_get_ioapicid;
357 
358 	apix_softinit();
359 
360 	apic_pir_vect = apix_get_ipivect(XC_CPUPOKE_PIL, -1);
361 
362 	/*
363 	 * Initialize IRM pool parameters
364 	 */
365 	if (irm_enable) {
366 		int	i;
367 		int	lowest_irq;
368 		int	highest_irq;
369 
370 		/* number of CPUs present */
371 		apix_irminfo.apix_ncpus = apic_nproc;
372 		/* total number of entries in all of the IOAPICs present */
373 		lowest_irq = apic_io_vectbase[0];
374 		highest_irq = apic_io_vectend[0];
375 		for (i = 1; i < apic_io_max; i++) {
376 			if (apic_io_vectbase[i] < lowest_irq)
377 				lowest_irq = apic_io_vectbase[i];
378 			if (apic_io_vectend[i] > highest_irq)
379 				highest_irq = apic_io_vectend[i];
380 		}
381 		apix_irminfo.apix_ioapic_max_vectors =
382 		    highest_irq - lowest_irq + 1;
383 		/*
384 		 * Number of available per-CPU vectors excluding
385 		 * reserved vectors for Dtrace, int80, system-call,
386 		 * fast-trap, etc.
387 		 */
388 		apix_irminfo.apix_per_cpu_vectors = APIX_NAVINTR -
389 		    APIX_SW_RESERVED_VECTORS;
390 
391 		/* Number of vectors (pre) allocated (SCI and HPET) */
392 		apix_irminfo.apix_vectors_allocated = 0;
393 		if (apic_hpet_vect != -1)
394 			apix_irminfo.apix_vectors_allocated++;
395 		if (apic_sci_vect != -1)
396 			apix_irminfo.apix_vectors_allocated++;
397 	}
398 }
399 
400 static void
apix_init_intr()401 apix_init_intr()
402 {
403 	processorid_t	cpun = psm_get_cpu_id();
404 	uint_t nlvt;
405 	uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
406 	extern void cmi_cmci_trap(void);
407 
408 	apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
409 
410 	if (apic_mode == LOCAL_APIC) {
411 		/*
412 		 * We are running APIC in MMIO mode.
413 		 */
414 		if (apic_flat_model) {
415 			apic_reg_ops->apic_write(APIC_FORMAT_REG,
416 			    APIC_FLAT_MODEL);
417 		} else {
418 			apic_reg_ops->apic_write(APIC_FORMAT_REG,
419 			    APIC_CLUSTER_MODEL);
420 		}
421 
422 		apic_reg_ops->apic_write(APIC_DEST_REG,
423 		    AV_HIGH_ORDER >> cpun);
424 	}
425 
426 	if (apic_directed_EOI_supported()) {
427 		/*
428 		 * Setting the 12th bit in the Spurious Interrupt Vector
429 		 * Register suppresses broadcast EOIs generated by the local
430 		 * APIC. The suppression of broadcast EOIs happens only when
431 		 * interrupts are level-triggered.
432 		 */
433 		svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
434 	}
435 
436 	/* need to enable APIC before unmasking NMI */
437 	apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
438 
439 	/*
440 	 * Presence of an invalid vector with delivery mode AV_FIXED can
441 	 * cause an error interrupt, even if the entry is masked...so
442 	 * write a valid vector to LVT entries along with the mask bit
443 	 */
444 
445 	/* All APICs have timer and LINT0/1 */
446 	apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
447 	apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
448 	apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI);	/* enable NMI */
449 
450 	/*
451 	 * On integrated APICs, the number of LVT entries is
452 	 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
453 	 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
454 	 */
455 
456 	if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
457 		nlvt = 3;
458 	} else {
459 		nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
460 		    0xFF) + 1;
461 	}
462 
463 	if (nlvt >= 5) {
464 		/* Enable performance counter overflow interrupt */
465 
466 		if (!is_x86_feature(x86_featureset, X86FSET_MSR))
467 			apic_enable_cpcovf_intr = 0;
468 		if (apic_enable_cpcovf_intr) {
469 			if (apic_cpcovf_vect == 0) {
470 				int ipl = APIC_PCINT_IPL;
471 
472 				apic_cpcovf_vect = apix_get_ipivect(ipl, -1);
473 				ASSERT(apic_cpcovf_vect);
474 
475 				(void) add_avintr(NULL, ipl,
476 				    (avfunc)kcpc_hw_overflow_intr,
477 				    "apic pcint", apic_cpcovf_vect,
478 				    NULL, NULL, NULL, NULL);
479 				kcpc_hw_overflow_intr_installed = 1;
480 				kcpc_hw_enable_cpc_intr =
481 				    apic_cpcovf_mask_clear;
482 			}
483 			apic_reg_ops->apic_write(APIC_PCINT_VECT,
484 			    apic_cpcovf_vect);
485 		}
486 	}
487 
488 	if (nlvt >= 6) {
489 		/* Only mask TM intr if the BIOS apparently doesn't use it */
490 
491 		uint32_t lvtval;
492 
493 		lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
494 		if (((lvtval & AV_MASK) == AV_MASK) ||
495 		    ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
496 			apic_reg_ops->apic_write(APIC_THERM_VECT,
497 			    AV_MASK|APIC_RESV_IRQ);
498 		}
499 	}
500 
501 	/* Enable error interrupt */
502 
503 	if (nlvt >= 4 && apic_enable_error_intr) {
504 		if (apic_errvect == 0) {
505 			int ipl = 0xf;	/* get highest priority intr */
506 			apic_errvect = apix_get_ipivect(ipl, -1);
507 			ASSERT(apic_errvect);
508 			/*
509 			 * Not PSMI compliant, but we are going to merge
510 			 * with ON anyway
511 			 */
512 			(void) add_avintr(NULL, ipl,
513 			    (avfunc)apic_error_intr, "apic error intr",
514 			    apic_errvect, NULL, NULL, NULL, NULL);
515 		}
516 		apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
517 		apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
518 		apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
519 	}
520 
521 	/*
522 	 * Ensure a CMCI interrupt is allocated, regardless of whether it is
523 	 * enabled or not.
524 	 */
525 	if (apic_cmci_vect == 0) {
526 		const int ipl = 0x2;
527 		apic_cmci_vect = apix_get_ipivect(ipl, -1);
528 		ASSERT(apic_cmci_vect);
529 
530 		(void) add_avintr(NULL, ipl,
531 		    (avfunc)cmi_cmci_trap, "apic cmci intr",
532 		    apic_cmci_vect, NULL, NULL, NULL, NULL);
533 	}
534 
535 	apic_reg_ops->apic_write_task_reg(0);
536 }
537 
538 static void
apix_picinit(void)539 apix_picinit(void)
540 {
541 	int i, j;
542 	uint_t isr;
543 
544 	APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_picinit\n"));
545 
546 	/*
547 	 * initialize interrupt remapping before apic
548 	 * hardware initialization
549 	 */
550 	apic_intrmap_init(apic_mode);
551 	if (apic_vt_ops == psm_vt_ops)
552 		apix_mul_ioapic_method = APIC_MUL_IOAPIC_IIR;
553 
554 	/*
555 	 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
556 	 * bit on without clearing it with EOI.  Since softint
557 	 * uses vector 0x20 to interrupt itself, so softint will
558 	 * not work on this machine.  In order to fix this problem
559 	 * a check is made to verify all the isr bits are clear.
560 	 * If not, EOIs are issued to clear the bits.
561 	 */
562 	for (i = 7; i >= 1; i--) {
563 		isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
564 		if (isr != 0)
565 			for (j = 0; ((j < 32) && (isr != 0)); j++)
566 				if (isr & (1 << j)) {
567 					apic_reg_ops->apic_write(
568 					    APIC_EOI_REG, 0);
569 					isr &= ~(1 << j);
570 					apic_error |= APIC_ERR_BOOT_EOI;
571 				}
572 	}
573 
574 	/* set a flag so we know we have run apic_picinit() */
575 	apic_picinit_called = 1;
576 	LOCK_INIT_CLEAR(&apic_gethrtime_lock);
577 	LOCK_INIT_CLEAR(&apic_ioapic_lock);
578 	LOCK_INIT_CLEAR(&apic_error_lock);
579 	LOCK_INIT_CLEAR(&apic_mode_switch_lock);
580 
581 	picsetup();	 /* initialise the 8259 */
582 
583 	/* add nmi handler - least priority nmi handler */
584 	LOCK_INIT_CLEAR(&apic_nmi_lock);
585 
586 	if (!psm_add_nmintr(0, apic_nmi_intr,
587 	    "apix NMI handler", (caddr_t)NULL))
588 		cmn_err(CE_WARN, "apix: Unable to add nmi handler");
589 
590 	apix_init_intr();
591 
592 	/* enable apic mode if imcr present */
593 	if (apic_imcrp) {
594 		outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
595 		outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
596 	}
597 
598 	ioapix_init_intr(IOAPIC_MASK);
599 
600 	/* setup global IRM pool if applicable */
601 	if (irm_enable)
602 		apix_irm_init();
603 }
604 
605 static __inline__ void
apix_send_eoi(void)606 apix_send_eoi(void)
607 {
608 	if (apic_mode == LOCAL_APIC)
609 		LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
610 	else
611 		X2APIC_WRITE(APIC_EOI_REG, 0);
612 }
613 
614 /*
615  * platform_intr_enter
616  *
617  *	Called at the beginning of the interrupt service routine, but unlike
618  *	pcplusmp, does not mask interrupts. An EOI is given to the interrupt
619  *	controller to enable other HW interrupts but interrupts are still
620  *	masked by the IF flag.
621  *
622  *	Return -1 for spurious interrupts
623  *
624  */
625 static int
apix_intr_enter(int ipl,int * vectorp)626 apix_intr_enter(int ipl, int *vectorp)
627 {
628 	struct cpu *cpu = CPU;
629 	uint32_t cpuid = CPU->cpu_id;
630 	apic_cpus_info_t *cpu_infop;
631 	uchar_t vector;
632 	apix_vector_t *vecp;
633 	int nipl = -1;
634 
635 	/*
636 	 * The real vector delivered is (*vectorp + 0x20), but our caller
637 	 * subtracts 0x20 from the vector before passing it to us.
638 	 * (That's why APIC_BASE_VECT is 0x20.)
639 	 */
640 	vector = *vectorp = (uchar_t)*vectorp + APIC_BASE_VECT;
641 
642 	cpu_infop = &apic_cpus[cpuid];
643 	if (vector == APIC_SPUR_INTR) {
644 		cpu_infop->aci_spur_cnt++;
645 		return (APIC_INT_SPURIOUS);
646 	}
647 
648 	vecp = xv_vector(cpuid, vector);
649 	if (vecp == NULL) {
650 		if (APIX_IS_FAKE_INTR(vector))
651 			nipl = apix_rebindinfo.i_pri;
652 		apix_send_eoi();
653 		return (nipl);
654 	}
655 	nipl = vecp->v_pri;
656 
657 	/* if interrupted by the clock, increment apic_nsec_since_boot */
658 	if (vector == (apic_clkvect + APIC_BASE_VECT)) {
659 		if (!apic_oneshot) {
660 			/* NOTE: this is not MT aware */
661 			apic_hrtime_stamp++;
662 			apic_nsec_since_boot += apic_nsec_per_intr;
663 			apic_hrtime_stamp++;
664 			last_count_read = apic_hertz_count;
665 			apix_redistribute_compute();
666 		}
667 
668 		apix_send_eoi();
669 
670 		return (nipl);
671 	}
672 
673 	ASSERT(vecp->v_state != APIX_STATE_OBSOLETED);
674 
675 	/* pre-EOI handling for level-triggered interrupts */
676 	if (!APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method) &&
677 	    (vecp->v_type & APIX_TYPE_FIXED) && apic_level_intr[vecp->v_inum])
678 		apix_level_intr_pre_eoi(vecp->v_inum);
679 
680 	/* send back EOI */
681 	apix_send_eoi();
682 
683 	cpu_infop->aci_current[nipl] = vector;
684 	if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) {
685 		cpu_infop->aci_curipl = (uchar_t)nipl;
686 		cpu_infop->aci_ISR_in_progress |= 1 << nipl;
687 	}
688 
689 #ifdef	DEBUG
690 	if (vector >= APIX_IPI_MIN)
691 		return (nipl);	/* skip IPI */
692 
693 	APIC_DEBUG_BUF_PUT(vector);
694 	APIC_DEBUG_BUF_PUT(vecp->v_inum);
695 	APIC_DEBUG_BUF_PUT(nipl);
696 	APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
697 	if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
698 		drv_usecwait(apic_stretch_interrupts);
699 #endif /* DEBUG */
700 
701 	return (nipl);
702 }
703 
704 /*
705  * Any changes made to this function must also change X2APIC
706  * version of intr_exit.
707  */
708 static void
apix_intr_exit(int prev_ipl,int arg2)709 apix_intr_exit(int prev_ipl, int arg2)
710 {
711 	int cpuid = psm_get_cpu_id();
712 	apic_cpus_info_t *cpu_infop = &apic_cpus[cpuid];
713 	apix_impl_t *apixp = apixs[cpuid];
714 
715 	UNREFERENCED_1PARAMETER(arg2);
716 
717 	cpu_infop->aci_curipl = (uchar_t)prev_ipl;
718 	/* ISR above current pri could not be in progress */
719 	cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
720 
721 	if (apixp->x_obsoletes != NULL) {
722 		if (APIX_CPU_LOCK_HELD(cpuid))
723 			return;
724 
725 		APIX_ENTER_CPU_LOCK(cpuid);
726 		(void) apix_obsolete_vector(apixp->x_obsoletes);
727 		APIX_LEAVE_CPU_LOCK(cpuid);
728 	}
729 }
730 
731 /*
732  * The pcplusmp setspl code uses the TPR to mask all interrupts at or below the
733  * given ipl, but apix never uses the TPR and we never mask a subset of the
734  * interrupts. They are either all blocked by the IF flag or all can come in.
735  *
736  * For setspl, we mask all interrupts for XC_HI_PIL (15), otherwise, interrupts
737  * can come in if currently enabled by the IF flag. This table shows the state
738  * of the IF flag when we leave this function.
739  *
740  *    curr IF |	ipl == 15	ipl != 15
741  *    --------+---------------------------
742  *       0    |    0		    0
743  *       1    |    0		    1
744  */
745 static void
apix_setspl(int ipl)746 apix_setspl(int ipl)
747 {
748 	/*
749 	 * Interrupts at ipl above this cannot be in progress, so the following
750 	 * mask is ok.
751 	 */
752 	apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
753 
754 	if (ipl == XC_HI_PIL)
755 		cli();
756 }
757 
758 int
apix_addspl(int virtvec,int ipl,int min_ipl,int max_ipl)759 apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl)
760 {
761 	uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
762 	uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
763 	apix_vector_t *vecp = xv_vector(cpuid, vector);
764 
765 	UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
766 	ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
767 
768 	if (vecp->v_type == APIX_TYPE_FIXED)
769 		apix_intx_set_shared(vecp->v_inum, 1);
770 
771 	/* There are more interrupts, so it's already been enabled */
772 	if (vecp->v_share > 1)
773 		return (PSM_SUCCESS);
774 
775 	/* return if it is not hardware interrupt */
776 	if (vecp->v_type == APIX_TYPE_IPI)
777 		return (PSM_SUCCESS);
778 
779 	/*
780 	 * if apix_picinit() has not been called yet, just return.
781 	 * At the end of apic_picinit(), we will call setup_io_intr().
782 	 */
783 	if (!apic_picinit_called)
784 		return (PSM_SUCCESS);
785 
786 	(void) apix_setup_io_intr(vecp);
787 
788 	return (PSM_SUCCESS);
789 }
790 
791 int
apix_delspl(int virtvec,int ipl,int min_ipl,int max_ipl)792 apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl)
793 {
794 	uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
795 	uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
796 	apix_vector_t *vecp = xv_vector(cpuid, vector);
797 
798 	UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
799 	ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
800 
801 	if (vecp->v_type == APIX_TYPE_FIXED)
802 		apix_intx_set_shared(vecp->v_inum, -1);
803 
804 	/* There are more interrupts */
805 	if (vecp->v_share > 1)
806 		return (PSM_SUCCESS);
807 
808 	/* return if it is not hardware interrupt */
809 	if (vecp->v_type == APIX_TYPE_IPI)
810 		return (PSM_SUCCESS);
811 
812 	if (!apic_picinit_called) {
813 		cmn_err(CE_WARN, "apix: delete 0x%x before apic init",
814 		    virtvec);
815 		return (PSM_SUCCESS);
816 	}
817 
818 	apix_disable_vector(vecp);
819 
820 	return (PSM_SUCCESS);
821 }
822 
823 /*
824  * Try and disable all interrupts. We just assign interrupts to other
825  * processors based on policy. If any were bound by user request, we
826  * let them continue and return failure. We do not bother to check
827  * for cache affinity while rebinding.
828  */
829 static int
apix_disable_intr(processorid_t cpun)830 apix_disable_intr(processorid_t cpun)
831 {
832 	apix_impl_t *apixp = apixs[cpun];
833 	apix_vector_t *vecp, *newp;
834 	int bindcpu, i, hardbound = 0, errbound = 0, ret, loop, type;
835 
836 	lock_set(&apix_lock);
837 
838 	apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
839 	apic_cpus[cpun].aci_curipl = 0;
840 
841 	/* if this is for SUSPEND operation, skip rebinding */
842 	if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
843 		for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
844 			vecp = apixp->x_vectbl[i];
845 			if (!IS_VECT_ENABLED(vecp))
846 				continue;
847 
848 			apix_disable_vector(vecp);
849 		}
850 		lock_clear(&apix_lock);
851 		return (PSM_SUCCESS);
852 	}
853 
854 	for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
855 		vecp = apixp->x_vectbl[i];
856 		if (!IS_VECT_ENABLED(vecp))
857 			continue;
858 
859 		if (vecp->v_flags & APIX_VECT_USER_BOUND) {
860 			hardbound++;
861 			continue;
862 		}
863 		type = vecp->v_type;
864 
865 		/*
866 		 * If there are bound interrupts on this cpu, then
867 		 * rebind them to other processors.
868 		 */
869 		loop = 0;
870 		do {
871 			bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE);
872 
873 			if (type != APIX_TYPE_MSI)
874 				newp = apix_set_cpu(vecp, bindcpu, &ret);
875 			else
876 				newp = apix_grp_set_cpu(vecp, bindcpu, &ret);
877 		} while ((newp == NULL) && (loop++ < apic_nproc));
878 
879 		if (loop >= apic_nproc) {
880 			errbound++;
881 			cmn_err(CE_WARN, "apix: failed to rebind vector %x/%x",
882 			    vecp->v_cpuid, vecp->v_vector);
883 		}
884 	}
885 
886 	lock_clear(&apix_lock);
887 
888 	if (hardbound || errbound) {
889 		cmn_err(CE_WARN, "Could not disable interrupts on %d"
890 		    "due to user bound interrupts or failed operation",
891 		    cpun);
892 		return (PSM_FAILURE);
893 	}
894 
895 	return (PSM_SUCCESS);
896 }
897 
898 /*
899  * Bind interrupts to specified CPU
900  */
901 static void
apix_enable_intr(processorid_t cpun)902 apix_enable_intr(processorid_t cpun)
903 {
904 	apix_vector_t *vecp;
905 	int i, ret;
906 	processorid_t n;
907 
908 	lock_set(&apix_lock);
909 
910 	apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
911 
912 	/* interrupt enabling for system resume */
913 	if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
914 		for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
915 			vecp = xv_vector(cpun, i);
916 			if (!IS_VECT_ENABLED(vecp))
917 				continue;
918 
919 			apix_enable_vector(vecp);
920 		}
921 		apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
922 	}
923 
924 	for (n = 0; n < apic_nproc; n++) {
925 		if (!apic_cpu_in_range(n) || n == cpun ||
926 		    (apic_cpus[n].aci_status & APIC_CPU_INTR_ENABLE) == 0)
927 			continue;
928 
929 		for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
930 			vecp = xv_vector(n, i);
931 			if (!IS_VECT_ENABLED(vecp) ||
932 			    vecp->v_bound_cpuid != cpun)
933 				continue;
934 
935 			if (vecp->v_type != APIX_TYPE_MSI)
936 				(void) apix_set_cpu(vecp, cpun, &ret);
937 			else
938 				(void) apix_grp_set_cpu(vecp, cpun, &ret);
939 		}
940 	}
941 
942 	lock_clear(&apix_lock);
943 }
944 
945 /*
946  * Allocate vector for IPI
947  * type == -1 indicates it is an internal request. Do not change
948  * resv_vector for these requests.
949  */
950 static int
apix_get_ipivect(int ipl,int type)951 apix_get_ipivect(int ipl, int type)
952 {
953 	uchar_t vector;
954 
955 	if ((vector = apix_alloc_ipi(ipl)) > 0) {
956 		if (type != -1)
957 			apic_resv_vector[ipl] = vector;
958 		return (vector);
959 	}
960 	apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
961 	return (-1);	/* shouldn't happen */
962 }
963 
964 static int
apix_get_clkvect(int ipl)965 apix_get_clkvect(int ipl)
966 {
967 	int vector;
968 
969 	if ((vector = apix_get_ipivect(ipl, -1)) == -1)
970 		return (-1);
971 
972 	apic_clkvect = vector - APIC_BASE_VECT;
973 	APIC_VERBOSE(IPI, (CE_CONT, "apix: clock vector = %x\n",
974 	    apic_clkvect));
975 	return (vector);
976 }
977 
978 static int
apix_post_cpu_start()979 apix_post_cpu_start()
980 {
981 	int cpun;
982 	static int cpus_started = 1;
983 
984 	/* We know this CPU + BSP  started successfully. */
985 	cpus_started++;
986 
987 	/*
988 	 * On BSP we would have enabled X2APIC, if supported by processor,
989 	 * in acpi_probe(), but on AP we do it here.
990 	 *
991 	 * We enable X2APIC mode only if BSP is running in X2APIC & the
992 	 * local APIC mode of the current CPU is MMIO (xAPIC).
993 	 */
994 	if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
995 	    apic_local_mode() == LOCAL_APIC) {
996 		apic_enable_x2apic();
997 	}
998 
999 	/*
1000 	 * Switch back to x2apic IPI sending method for performance when target
1001 	 * CPU has entered x2apic mode.
1002 	 */
1003 	if (apic_mode == LOCAL_X2APIC) {
1004 		apic_switch_ipi_callback(B_FALSE);
1005 	}
1006 
1007 	splx(ipltospl(LOCK_LEVEL));
1008 	apix_init_intr();
1009 
1010 #ifdef	DEBUG
1011 	APIC_AV_PENDING_SET();
1012 #else
1013 	if (apic_mode == LOCAL_APIC)
1014 		APIC_AV_PENDING_SET();
1015 #endif	/* DEBUG */
1016 
1017 	/*
1018 	 * We may be booting, or resuming from suspend; aci_status will
1019 	 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
1020 	 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
1021 	 */
1022 	cpun = psm_get_cpu_id();
1023 	apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
1024 
1025 	apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
1026 
1027 	return (PSM_SUCCESS);
1028 }
1029 
1030 /*
1031  * If this module needs a periodic handler for the interrupt distribution, it
1032  * can be added here. The argument to the periodic handler is not currently
1033  * used, but is reserved for future.
1034  */
1035 static void
apix_post_cyclic_setup(void * arg)1036 apix_post_cyclic_setup(void *arg)
1037 {
1038 	UNREFERENCED_1PARAMETER(arg);
1039 
1040 	cyc_handler_t cyh;
1041 	cyc_time_t cyt;
1042 
1043 	/* cpu_lock is held */
1044 	/* set up a periodic handler for intr redistribution */
1045 
1046 	/*
1047 	 * In peridoc mode intr redistribution processing is done in
1048 	 * apic_intr_enter during clk intr processing
1049 	 */
1050 	if (!apic_oneshot)
1051 		return;
1052 
1053 	/*
1054 	 * Register a periodical handler for the redistribution processing.
1055 	 * Though we would generally prefer to use the DDI interface for
1056 	 * periodic handler invocation, ddi_periodic_add(9F), we are
1057 	 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1058 	 * attempt to take for us.  Thus, we add our own cyclic directly:
1059 	 */
1060 	cyh.cyh_func = (void (*)(void *))apix_redistribute_compute;
1061 	cyh.cyh_arg = NULL;
1062 	cyh.cyh_level = CY_LOW_LEVEL;
1063 
1064 	cyt.cyt_when = 0;
1065 	cyt.cyt_interval = apic_redistribute_sample_interval;
1066 
1067 	apic_cyclic_id = cyclic_add(&cyh, &cyt);
1068 }
1069 
1070 /*
1071  * Called the first time we enable x2apic mode on this cpu.
1072  * Update some of the function pointers to use x2apic routines.
1073  */
1074 void
x2apic_update_psm()1075 x2apic_update_psm()
1076 {
1077 	struct psm_ops *pops = &apix_ops;
1078 
1079 	ASSERT(pops != NULL);
1080 
1081 	/*
1082 	 * The pcplusmp module's version of x2apic_update_psm makes additional
1083 	 * changes that we do not have to make here. It needs to make those
1084 	 * changes because pcplusmp relies on the TPR register and the means of
1085 	 * addressing that changes when using the local apic versus the x2apic.
1086 	 * It's also worth noting that the apix driver specific function end up
1087 	 * being apix_foo as opposed to apic_foo and x2apic_foo.
1088 	 */
1089 	pops->psm_send_ipi = x2apic_send_ipi;
1090 	send_dirintf = pops->psm_send_ipi;
1091 
1092 	pops->psm_send_pir_ipi = x2apic_send_pir_ipi;
1093 	psm_send_pir_ipi = pops->psm_send_pir_ipi;
1094 
1095 	apic_mode = LOCAL_X2APIC;
1096 	apic_change_ops();
1097 }
1098 
1099 /*
1100  * This function provides external interface to the nexus for all
1101  * functionalities related to the new DDI interrupt framework.
1102  *
1103  * Input:
1104  * dip     - pointer to the dev_info structure of the requested device
1105  * hdlp    - pointer to the internal interrupt handle structure for the
1106  *	     requested interrupt
1107  * intr_op - opcode for this call
1108  * result  - pointer to the integer that will hold the result to be
1109  *	     passed back if return value is PSM_SUCCESS
1110  *
1111  * Output:
1112  * return value is either PSM_SUCCESS or PSM_FAILURE
1113  */
1114 static int
apix_intr_ops(dev_info_t * dip,ddi_intr_handle_impl_t * hdlp,psm_intr_op_t intr_op,int * result)1115 apix_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
1116     psm_intr_op_t intr_op, int *result)
1117 {
1118 	int		cap;
1119 	apix_vector_t	*vecp, *newvecp;
1120 	struct intrspec *ispec, intr_spec;
1121 	processorid_t target;
1122 
1123 	ispec = &intr_spec;
1124 	ispec->intrspec_pri = hdlp->ih_pri;
1125 	ispec->intrspec_vec = hdlp->ih_inum;
1126 	ispec->intrspec_func = hdlp->ih_cb_func;
1127 
1128 	switch (intr_op) {
1129 	case PSM_INTR_OP_ALLOC_VECTORS:
1130 		switch (hdlp->ih_type) {
1131 		case DDI_INTR_TYPE_MSI:
1132 			/* allocate MSI vectors */
1133 			*result = apix_alloc_msi(dip, hdlp->ih_inum,
1134 			    hdlp->ih_scratch1,
1135 			    (int)(uintptr_t)hdlp->ih_scratch2);
1136 			break;
1137 		case DDI_INTR_TYPE_MSIX:
1138 			/* allocate MSI-X vectors */
1139 			*result = apix_alloc_msix(dip, hdlp->ih_inum,
1140 			    hdlp->ih_scratch1,
1141 			    (int)(uintptr_t)hdlp->ih_scratch2);
1142 			break;
1143 		case DDI_INTR_TYPE_FIXED:
1144 			/* allocate or share vector for fixed */
1145 			if ((ihdl_plat_t *)hdlp->ih_private == NULL) {
1146 				return (PSM_FAILURE);
1147 			}
1148 			ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp;
1149 			*result = apix_intx_alloc_vector(dip, hdlp->ih_inum,
1150 			    ispec);
1151 			break;
1152 		default:
1153 			return (PSM_FAILURE);
1154 		}
1155 		break;
1156 	case PSM_INTR_OP_FREE_VECTORS:
1157 		apix_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1,
1158 		    hdlp->ih_type);
1159 		break;
1160 	case PSM_INTR_OP_XLATE_VECTOR:
1161 		/*
1162 		 * Vectors are allocated by ALLOC and freed by FREE.
1163 		 * XLATE finds and returns APIX_VIRTVEC_VECTOR(cpu, vector).
1164 		 */
1165 		*result = APIX_INVALID_VECT;
1166 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1167 		if (vecp != NULL) {
1168 			*result = APIX_VIRTVECTOR(vecp->v_cpuid,
1169 			    vecp->v_vector);
1170 			break;
1171 		}
1172 
1173 		/*
1174 		 * No vector to device mapping exists. If this is FIXED type
1175 		 * then check if this IRQ is already mapped for another device
1176 		 * then return the vector number for it (i.e. shared IRQ case).
1177 		 * Otherwise, return PSM_FAILURE.
1178 		 */
1179 		if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
1180 			vecp = apix_intx_xlate_vector(dip, hdlp->ih_inum,
1181 			    ispec);
1182 			*result = (vecp == NULL) ? APIX_INVALID_VECT :
1183 			    APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector);
1184 		}
1185 		if (*result == APIX_INVALID_VECT)
1186 			return (PSM_FAILURE);
1187 		break;
1188 	case PSM_INTR_OP_GET_PENDING:
1189 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1190 		if (vecp == NULL)
1191 			return (PSM_FAILURE);
1192 
1193 		*result = apix_get_pending(vecp);
1194 		break;
1195 	case PSM_INTR_OP_CLEAR_MASK:
1196 		if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1197 			return (PSM_FAILURE);
1198 
1199 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1200 		if (vecp == NULL)
1201 			return (PSM_FAILURE);
1202 
1203 		apix_intx_clear_mask(vecp->v_inum);
1204 		break;
1205 	case PSM_INTR_OP_SET_MASK:
1206 		if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1207 			return (PSM_FAILURE);
1208 
1209 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1210 		if (vecp == NULL)
1211 			return (PSM_FAILURE);
1212 
1213 		apix_intx_set_mask(vecp->v_inum);
1214 		break;
1215 	case PSM_INTR_OP_GET_SHARED:
1216 		if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1217 			return (PSM_FAILURE);
1218 
1219 		vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1220 		if (vecp == NULL)
1221 			return (PSM_FAILURE);
1222 
1223 		*result = apix_intx_get_shared(vecp->v_inum);
1224 		break;
1225 	case PSM_INTR_OP_SET_PRI:
1226 		/*
1227 		 * Called prior to adding the interrupt handler or when
1228 		 * an interrupt handler is unassigned.
1229 		 */
1230 		if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1231 			return (PSM_SUCCESS);
1232 
1233 		if (apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type) == NULL)
1234 			return (PSM_FAILURE);
1235 
1236 		break;
1237 	case PSM_INTR_OP_SET_CPU:
1238 	case PSM_INTR_OP_GRP_SET_CPU:
1239 		/*
1240 		 * The interrupt handle given here has been allocated
1241 		 * specifically for this command, and ih_private carries
1242 		 * a CPU value.
1243 		 */
1244 		*result = EINVAL;
1245 		target = (int)(intptr_t)hdlp->ih_private;
1246 		if (!apic_cpu_in_range(target)) {
1247 			DDI_INTR_IMPLDBG((CE_WARN,
1248 			    "[grp_]set_cpu: cpu out of range: %d\n", target));
1249 			return (PSM_FAILURE);
1250 		}
1251 
1252 		lock_set(&apix_lock);
1253 
1254 		vecp = apix_get_req_vector(hdlp, hdlp->ih_flags);
1255 		if (!IS_VECT_ENABLED(vecp)) {
1256 			DDI_INTR_IMPLDBG((CE_WARN,
1257 			    "[grp]_set_cpu: invalid vector 0x%x\n",
1258 			    hdlp->ih_vector));
1259 			lock_clear(&apix_lock);
1260 			return (PSM_FAILURE);
1261 		}
1262 
1263 		*result = 0;
1264 
1265 		if (intr_op == PSM_INTR_OP_SET_CPU)
1266 			newvecp = apix_set_cpu(vecp, target, result);
1267 		else
1268 			newvecp = apix_grp_set_cpu(vecp, target, result);
1269 
1270 		lock_clear(&apix_lock);
1271 
1272 		if (newvecp == NULL) {
1273 			*result = EIO;
1274 			return (PSM_FAILURE);
1275 		}
1276 		newvecp->v_bound_cpuid = target;
1277 		hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid,
1278 		    newvecp->v_vector);
1279 		break;
1280 
1281 	case PSM_INTR_OP_GET_INTR:
1282 		/*
1283 		 * The interrupt handle given here has been allocated
1284 		 * specifically for this command, and ih_private carries
1285 		 * a pointer to a apic_get_intr_t.
1286 		 */
1287 		if (apix_get_intr_info(hdlp, hdlp->ih_private) != PSM_SUCCESS)
1288 			return (PSM_FAILURE);
1289 		break;
1290 
1291 	case PSM_INTR_OP_CHECK_MSI:
1292 		/*
1293 		 * Check MSI/X is supported or not at APIC level and
1294 		 * masked off the MSI/X bits in hdlp->ih_type if not
1295 		 * supported before return.  If MSI/X is supported,
1296 		 * leave the ih_type unchanged and return.
1297 		 *
1298 		 * hdlp->ih_type passed in from the nexus has all the
1299 		 * interrupt types supported by the device.
1300 		 */
1301 		if (apic_support_msi == 0) {	/* uninitialized */
1302 			/*
1303 			 * if apic_support_msi is not set, call
1304 			 * apic_check_msi_support() to check whether msi
1305 			 * is supported first
1306 			 */
1307 			if (apic_check_msi_support() == PSM_SUCCESS)
1308 				apic_support_msi = 1;	/* supported */
1309 			else
1310 				apic_support_msi = -1;	/* not-supported */
1311 		}
1312 		if (apic_support_msi == 1) {
1313 			if (apic_msix_enable)
1314 				*result = hdlp->ih_type;
1315 			else
1316 				*result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX;
1317 		} else
1318 			*result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI |
1319 			    DDI_INTR_TYPE_MSIX);
1320 		break;
1321 	case PSM_INTR_OP_GET_CAP:
1322 		cap = DDI_INTR_FLAG_PENDING;
1323 		if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1324 			cap |= DDI_INTR_FLAG_MASKABLE;
1325 		*result = cap;
1326 		break;
1327 	case PSM_INTR_OP_APIC_TYPE:
1328 		((apic_get_type_t *)(hdlp->ih_private))->avgi_type =
1329 		    apix_get_apic_type();
1330 		((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr =
1331 		    APIX_IPI_MIN;
1332 		((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu =
1333 		    apic_nproc;
1334 		hdlp->ih_ver = apic_get_apic_version();
1335 		break;
1336 	case PSM_INTR_OP_SET_CAP:
1337 	default:
1338 		return (PSM_FAILURE);
1339 	}
1340 
1341 	return (PSM_SUCCESS);
1342 }
1343 
1344 static void
apix_cleanup_busy(void)1345 apix_cleanup_busy(void)
1346 {
1347 	int i, j;
1348 	apix_vector_t *vecp;
1349 
1350 	for (i = 0; i < apic_nproc; i++) {
1351 		if (!apic_cpu_in_range(i))
1352 			continue;
1353 		apic_cpus[i].aci_busy = 0;
1354 		for (j = APIX_AVINTR_MIN; j < APIX_AVINTR_MAX; j++) {
1355 			if ((vecp = xv_vector(i, j)) != NULL)
1356 				vecp->v_busy = 0;
1357 		}
1358 	}
1359 }
1360 
1361 static void
apix_redistribute_compute(void)1362 apix_redistribute_compute(void)
1363 {
1364 	int	i, j, max_busy;
1365 
1366 	if (!apic_enable_dynamic_migration)
1367 		return;
1368 
1369 	if (++apic_nticks == apic_sample_factor_redistribution) {
1370 		/*
1371 		 * Time to call apic_intr_redistribute().
1372 		 * reset apic_nticks. This will cause max_busy
1373 		 * to be calculated below and if it is more than
1374 		 * apic_int_busy, we will do the whole thing
1375 		 */
1376 		apic_nticks = 0;
1377 	}
1378 	max_busy = 0;
1379 	for (i = 0; i < apic_nproc; i++) {
1380 		if (!apic_cpu_in_range(i))
1381 			continue;
1382 		/*
1383 		 * Check if curipl is non zero & if ISR is in
1384 		 * progress
1385 		 */
1386 		if (((j = apic_cpus[i].aci_curipl) != 0) &&
1387 		    (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1388 
1389 			int	vect;
1390 			apic_cpus[i].aci_busy++;
1391 			vect = apic_cpus[i].aci_current[j];
1392 			apixs[i]->x_vectbl[vect]->v_busy++;
1393 		}
1394 
1395 		if (!apic_nticks &&
1396 		    (apic_cpus[i].aci_busy > max_busy))
1397 			max_busy = apic_cpus[i].aci_busy;
1398 	}
1399 	if (!apic_nticks) {
1400 		if (max_busy > apic_int_busy_mark) {
1401 		/*
1402 		 * We could make the following check be
1403 		 * skipped > 1 in which case, we get a
1404 		 * redistribution at half the busy mark (due to
1405 		 * double interval). Need to be able to collect
1406 		 * more empirical data to decide if that is a
1407 		 * good strategy. Punt for now.
1408 		 */
1409 			apix_cleanup_busy();
1410 			apic_skipped_redistribute = 0;
1411 		} else
1412 			apic_skipped_redistribute++;
1413 	}
1414 }
1415 
1416 /*
1417  * intr_ops() service routines
1418  */
1419 
1420 static int
apix_get_pending(apix_vector_t * vecp)1421 apix_get_pending(apix_vector_t *vecp)
1422 {
1423 	int bit, index, irr, pending;
1424 
1425 	/* need to get on the bound cpu */
1426 	mutex_enter(&cpu_lock);
1427 	affinity_set(vecp->v_cpuid);
1428 
1429 	index = vecp->v_vector / 32;
1430 	bit = vecp->v_vector % 32;
1431 	irr = apic_reg_ops->apic_read(APIC_IRR_REG + index);
1432 
1433 	affinity_clear();
1434 	mutex_exit(&cpu_lock);
1435 
1436 	pending = (irr & (1 << bit)) ? 1 : 0;
1437 	if (!pending && vecp->v_type == APIX_TYPE_FIXED)
1438 		pending = apix_intx_get_pending(vecp->v_inum);
1439 
1440 	return (pending);
1441 }
1442 
1443 static apix_vector_t *
apix_get_req_vector(ddi_intr_handle_impl_t * hdlp,ushort_t flags)1444 apix_get_req_vector(ddi_intr_handle_impl_t *hdlp, ushort_t flags)
1445 {
1446 	apix_vector_t *vecp;
1447 	processorid_t cpuid;
1448 	int32_t virt_vec = 0;
1449 
1450 	switch (flags & PSMGI_INTRBY_FLAGS) {
1451 	case PSMGI_INTRBY_IRQ:
1452 		return (apix_intx_get_vector(hdlp->ih_vector));
1453 	case PSMGI_INTRBY_VEC:
1454 		virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec;
1455 
1456 		cpuid = APIX_VIRTVEC_CPU(virt_vec);
1457 		if (!apic_cpu_in_range(cpuid))
1458 			return (NULL);
1459 
1460 		vecp = xv_vector(cpuid, APIX_VIRTVEC_VECTOR(virt_vec));
1461 		break;
1462 	case PSMGI_INTRBY_DEFAULT:
1463 		vecp = apix_get_dev_map(hdlp->ih_dip, hdlp->ih_inum,
1464 		    hdlp->ih_type);
1465 		break;
1466 	default:
1467 		return (NULL);
1468 	}
1469 
1470 	return (vecp);
1471 }
1472 
1473 static int
apix_get_intr_info(ddi_intr_handle_impl_t * hdlp,apic_get_intr_t * intr_params_p)1474 apix_get_intr_info(ddi_intr_handle_impl_t *hdlp,
1475     apic_get_intr_t *intr_params_p)
1476 {
1477 	apix_vector_t *vecp;
1478 	struct autovec *av_dev;
1479 	int i;
1480 
1481 	vecp = apix_get_req_vector(hdlp, intr_params_p->avgi_req_flags);
1482 	if (IS_VECT_FREE(vecp)) {
1483 		intr_params_p->avgi_num_devs = 0;
1484 		intr_params_p->avgi_cpu_id = 0;
1485 		intr_params_p->avgi_req_flags = 0;
1486 		return (PSM_SUCCESS);
1487 	}
1488 
1489 	if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) {
1490 		intr_params_p->avgi_cpu_id = vecp->v_cpuid;
1491 
1492 		/* Return user bound info for intrd. */
1493 		if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) {
1494 			intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND;
1495 			intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND;
1496 		}
1497 	}
1498 
1499 	if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR)
1500 		intr_params_p->avgi_vector = vecp->v_vector;
1501 
1502 	if (intr_params_p->avgi_req_flags &
1503 	    (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS))
1504 		/* Get number of devices from apic_irq table shared field. */
1505 		intr_params_p->avgi_num_devs = vecp->v_share;
1506 
1507 	if (intr_params_p->avgi_req_flags &  PSMGI_REQ_GET_DEVS) {
1508 
1509 		intr_params_p->avgi_req_flags  |= PSMGI_REQ_NUM_DEVS;
1510 
1511 		/* Some devices have NULL dip.  Don't count these. */
1512 		if (intr_params_p->avgi_num_devs > 0) {
1513 			for (i = 0, av_dev = vecp->v_autovect; av_dev;
1514 			    av_dev = av_dev->av_link) {
1515 				if (av_dev->av_vector && av_dev->av_dip)
1516 					i++;
1517 			}
1518 			intr_params_p->avgi_num_devs =
1519 			    (uint8_t)MIN(intr_params_p->avgi_num_devs, i);
1520 		}
1521 
1522 		/* There are no viable dips to return. */
1523 		if (intr_params_p->avgi_num_devs == 0) {
1524 			intr_params_p->avgi_dip_list = NULL;
1525 
1526 		} else {	/* Return list of dips */
1527 
1528 			/* Allocate space in array for that number of devs. */
1529 			intr_params_p->avgi_dip_list = kmem_zalloc(
1530 			    intr_params_p->avgi_num_devs *
1531 			    sizeof (dev_info_t *),
1532 			    KM_NOSLEEP);
1533 			if (intr_params_p->avgi_dip_list == NULL) {
1534 				DDI_INTR_IMPLDBG((CE_WARN,
1535 				    "apix_get_vector_intr_info: no memory"));
1536 				return (PSM_FAILURE);
1537 			}
1538 
1539 			/*
1540 			 * Loop through the device list of the autovec table
1541 			 * filling in the dip array.
1542 			 *
1543 			 * Note that the autovect table may have some special
1544 			 * entries which contain NULL dips.  These will be
1545 			 * ignored.
1546 			 */
1547 			for (i = 0, av_dev = vecp->v_autovect; av_dev;
1548 			    av_dev = av_dev->av_link) {
1549 				if (av_dev->av_vector && av_dev->av_dip)
1550 					intr_params_p->avgi_dip_list[i++] =
1551 					    av_dev->av_dip;
1552 			}
1553 		}
1554 	}
1555 
1556 	return (PSM_SUCCESS);
1557 }
1558 
1559 static char *
apix_get_apic_type(void)1560 apix_get_apic_type(void)
1561 {
1562 	return (apix_psm_info.p_mach_idstring);
1563 }
1564 
1565 apix_vector_t *
apix_set_cpu(apix_vector_t * vecp,int new_cpu,int * result)1566 apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1567 {
1568 	apix_vector_t *newp = NULL;
1569 	dev_info_t *dip;
1570 	int inum, cap_ptr;
1571 	ddi_acc_handle_t handle;
1572 	ddi_intr_msix_t *msix_p = NULL;
1573 	ushort_t msix_ctrl;
1574 	uintptr_t off = 0;
1575 	uint32_t mask = 0;
1576 
1577 	ASSERT(LOCK_HELD(&apix_lock));
1578 	*result = ENXIO;
1579 
1580 	/* Fail if this is an MSI intr and is part of a group. */
1581 	if (vecp->v_type == APIX_TYPE_MSI) {
1582 		if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1)
1583 			return (NULL);
1584 		else
1585 			return (apix_grp_set_cpu(vecp, new_cpu, result));
1586 	}
1587 
1588 	/*
1589 	 * Mask MSI-X. It's unmasked when MSI-X gets enabled.
1590 	 */
1591 	if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) {
1592 		if ((dip = APIX_GET_DIP(vecp)) == NULL)
1593 			return (NULL);
1594 		inum = vecp->v_devp->dv_inum;
1595 
1596 		handle = i_ddi_get_pci_config_handle(dip);
1597 		cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1598 		msix_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
1599 		if ((msix_ctrl & PCI_MSIX_FUNCTION_MASK) == 0) {
1600 			/*
1601 			 * Function is not masked, then mask "inum"th
1602 			 * entry in the MSI-X table
1603 			 */
1604 			msix_p = i_ddi_get_msix(dip);
1605 			off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
1606 			    PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
1607 			mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
1608 			ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off,
1609 			    mask | 1);
1610 		}
1611 	}
1612 
1613 	*result = 0;
1614 	if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL)
1615 		*result = EIO;
1616 
1617 	/* Restore mask bit */
1618 	if (msix_p != NULL)
1619 		ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask);
1620 
1621 	return (newp);
1622 }
1623 
1624 /*
1625  * Set cpu for MSIs
1626  */
1627 apix_vector_t *
apix_grp_set_cpu(apix_vector_t * vecp,int new_cpu,int * result)1628 apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1629 {
1630 	apix_vector_t *newp, *vp;
1631 	uint32_t orig_cpu = vecp->v_cpuid;
1632 	int orig_vect = vecp->v_vector;
1633 	int i, num_vectors, cap_ptr, msi_mask_off = 0;
1634 	uint32_t msi_pvm = 0;
1635 	ushort_t msi_ctrl;
1636 	ddi_acc_handle_t handle;
1637 	dev_info_t *dip;
1638 
1639 	APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x,"
1640 	    " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu));
1641 
1642 	ASSERT(LOCK_HELD(&apix_lock));
1643 
1644 	*result = ENXIO;
1645 
1646 	if (vecp->v_type != APIX_TYPE_MSI) {
1647 		DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n"));
1648 		return (NULL);
1649 	}
1650 
1651 	if ((dip = APIX_GET_DIP(vecp)) == NULL)
1652 		return (NULL);
1653 
1654 	num_vectors = i_ddi_intr_get_current_nintrs(dip);
1655 	if ((num_vectors < 1) || ((num_vectors - 1) & orig_vect)) {
1656 		APIC_VERBOSE(INTR, (CE_WARN,
1657 		    "set_grp: base vec not part of a grp or not aligned: "
1658 		    "vec:0x%x, num_vec:0x%x\n", orig_vect, num_vectors));
1659 		return (NULL);
1660 	}
1661 
1662 	if (vecp->v_inum != apix_get_min_dev_inum(dip, vecp->v_type))
1663 		return (NULL);
1664 
1665 	*result = EIO;
1666 	for (i = 1; i < num_vectors; i++) {
1667 		if ((vp = xv_vector(orig_cpu, orig_vect + i)) == NULL)
1668 			return (NULL);
1669 #ifdef DEBUG
1670 		/*
1671 		 * Sanity check: CPU and dip is the same for all entries.
1672 		 * May be called when first msi to be enabled, at this time
1673 		 * add_avintr() is not called for other msi
1674 		 */
1675 		if ((vp->v_share != 0) &&
1676 		    ((APIX_GET_DIP(vp) != dip) ||
1677 		    (vp->v_cpuid != vecp->v_cpuid))) {
1678 			APIC_VERBOSE(INTR, (CE_WARN,
1679 			    "set_grp: cpu or dip for vec 0x%x difft than for "
1680 			    "vec 0x%x\n", orig_vect, orig_vect + i));
1681 			APIC_VERBOSE(INTR, (CE_WARN,
1682 			    "  cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu,
1683 			    vp->v_cpuid, (void *)dip,
1684 			    (void *)APIX_GET_DIP(vp)));
1685 			return (NULL);
1686 		}
1687 #endif /* DEBUG */
1688 	}
1689 
1690 	cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1691 	handle = i_ddi_get_pci_config_handle(dip);
1692 	msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
1693 
1694 	/* MSI Per vector masking is supported. */
1695 	if (msi_ctrl & PCI_MSI_PVM_MASK) {
1696 		if (msi_ctrl &  PCI_MSI_64BIT_MASK)
1697 			msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS;
1698 		else
1699 			msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK;
1700 		msi_pvm = pci_config_get32(handle, msi_mask_off);
1701 		pci_config_put32(handle, msi_mask_off, (uint32_t)-1);
1702 		APIC_VERBOSE(INTR, (CE_CONT,
1703 		    "set_grp: pvm supported.  Mask set to 0x%x\n",
1704 		    pci_config_get32(handle, msi_mask_off)));
1705 	}
1706 
1707 	if ((newp = apix_rebind(vecp, new_cpu, num_vectors)) != NULL)
1708 		*result = 0;
1709 
1710 	/* Reenable vectors if per vector masking is supported. */
1711 	if (msi_ctrl & PCI_MSI_PVM_MASK) {
1712 		pci_config_put32(handle, msi_mask_off, msi_pvm);
1713 		APIC_VERBOSE(INTR, (CE_CONT,
1714 		    "set_grp: pvm supported.  Mask restored to 0x%x\n",
1715 		    pci_config_get32(handle, msi_mask_off)));
1716 	}
1717 
1718 	return (newp);
1719 }
1720 
1721 void
apix_intx_set_vector(int irqno,uint32_t cpuid,uchar_t vector)1722 apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector)
1723 {
1724 	apic_irq_t *irqp;
1725 
1726 	mutex_enter(&airq_mutex);
1727 	irqp = apic_irq_table[irqno];
1728 	irqp->airq_cpu = cpuid;
1729 	irqp->airq_vector = vector;
1730 	apic_record_rdt_entry(irqp, irqno);
1731 	mutex_exit(&airq_mutex);
1732 }
1733 
1734 apix_vector_t *
apix_intx_get_vector(int irqno)1735 apix_intx_get_vector(int irqno)
1736 {
1737 	apic_irq_t *irqp;
1738 	uint32_t cpuid;
1739 	uchar_t vector;
1740 
1741 	mutex_enter(&airq_mutex);
1742 	irqp = apic_irq_table[irqno & 0xff];
1743 	if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
1744 		mutex_exit(&airq_mutex);
1745 		return (NULL);
1746 	}
1747 	cpuid = irqp->airq_cpu;
1748 	vector = irqp->airq_vector;
1749 	mutex_exit(&airq_mutex);
1750 
1751 	return (xv_vector(cpuid, vector));
1752 }
1753 
1754 /*
1755  * Must called with interrupts disabled and apic_ioapic_lock held
1756  */
1757 void
apix_intx_enable(int irqno)1758 apix_intx_enable(int irqno)
1759 {
1760 	uchar_t ioapicindex, intin;
1761 	apic_irq_t *irqp = apic_irq_table[irqno];
1762 	ioapic_rdt_t irdt;
1763 	apic_cpus_info_t *cpu_infop;
1764 	apix_vector_t *vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector);
1765 
1766 	ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1767 
1768 	ioapicindex = irqp->airq_ioapicindex;
1769 	intin = irqp->airq_intin_no;
1770 	cpu_infop =  &apic_cpus[irqp->airq_cpu];
1771 
1772 	irdt.ir_lo = AV_PDEST | AV_FIXED | irqp->airq_rdt_entry;
1773 	irdt.ir_hi = cpu_infop->aci_local_id;
1774 
1775 	apic_vt_ops->apic_intrmap_alloc_entry(&vecp->v_intrmap_private, NULL,
1776 	    vecp->v_type, 1, ioapicindex);
1777 	apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private,
1778 	    (void *)&irdt, vecp->v_type, 1);
1779 	apic_vt_ops->apic_intrmap_record_rdt(vecp->v_intrmap_private, &irdt);
1780 
1781 	/* write RDT entry high dword - destination */
1782 	WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin,
1783 	    irdt.ir_hi);
1784 
1785 	/* Write the vector, trigger, and polarity portion of the RDT */
1786 	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin, irdt.ir_lo);
1787 
1788 	vecp->v_state = APIX_STATE_ENABLED;
1789 
1790 	APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_enable: ioapic 0x%x"
1791 	    " intin 0x%x rdt_low 0x%x rdt_high 0x%x\n",
1792 	    ioapicindex, intin, irdt.ir_lo, irdt.ir_hi));
1793 }
1794 
1795 /*
1796  * Must called with interrupts disabled and apic_ioapic_lock held
1797  */
1798 void
apix_intx_disable(int irqno)1799 apix_intx_disable(int irqno)
1800 {
1801 	apic_irq_t *irqp = apic_irq_table[irqno];
1802 	int ioapicindex, intin;
1803 
1804 	ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1805 	/*
1806 	 * The assumption here is that this is safe, even for
1807 	 * systems with IOAPICs that suffer from the hardware
1808 	 * erratum because all devices have been quiesced before
1809 	 * they unregister their interrupt handlers.  If that
1810 	 * assumption turns out to be false, this mask operation
1811 	 * can induce the same erratum result we're trying to
1812 	 * avoid.
1813 	 */
1814 	ioapicindex = irqp->airq_ioapicindex;
1815 	intin = irqp->airq_intin_no;
1816 	ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK);
1817 
1818 	APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_disable: ioapic 0x%x"
1819 	    " intin 0x%x\n", ioapicindex, intin));
1820 }
1821 
1822 void
apix_intx_free(int irqno)1823 apix_intx_free(int irqno)
1824 {
1825 	apic_irq_t *irqp;
1826 
1827 	mutex_enter(&airq_mutex);
1828 	irqp = apic_irq_table[irqno];
1829 
1830 	if (IS_IRQ_FREE(irqp)) {
1831 		mutex_exit(&airq_mutex);
1832 		return;
1833 	}
1834 
1835 	irqp->airq_mps_intr_index = FREE_INDEX;
1836 	irqp->airq_cpu = IRQ_UNINIT;
1837 	irqp->airq_vector = APIX_INVALID_VECT;
1838 	mutex_exit(&airq_mutex);
1839 }
1840 
1841 #ifdef DEBUG
1842 int apix_intr_deliver_timeouts = 0;
1843 int apix_intr_rirr_timeouts = 0;
1844 int apix_intr_rirr_reset_failure = 0;
1845 #endif
1846 int apix_max_reps_irr_pending = 10;
1847 
1848 #define	GET_RDT_BITS(ioapic, intin, bits)	\
1849 	(READ_IOAPIC_RDT_ENTRY_LOW_DWORD((ioapic), (intin)) & (bits))
1850 #define	APIX_CHECK_IRR_DELAY	drv_usectohz(5000)
1851 
1852 int
apix_intx_rebind(int irqno,processorid_t cpuid,uchar_t vector)1853 apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector)
1854 {
1855 	apic_irq_t *irqp = apic_irq_table[irqno];
1856 	ulong_t iflag;
1857 	int waited, ioapic_ix, intin_no, level, repeats, rdt_entry, masked;
1858 
1859 	ASSERT(irqp != NULL);
1860 
1861 	iflag = intr_clear();
1862 	lock_set(&apic_ioapic_lock);
1863 
1864 	ioapic_ix = irqp->airq_ioapicindex;
1865 	intin_no = irqp->airq_intin_no;
1866 	level = apic_level_intr[irqno];
1867 
1868 	/*
1869 	 * Wait for the delivery status bit to be cleared. This should
1870 	 * be a very small amount of time.
1871 	 */
1872 	repeats = 0;
1873 	do {
1874 		repeats++;
1875 
1876 		for (waited = 0; waited < apic_max_reps_clear_pending;
1877 		    waited++) {
1878 			if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) == 0)
1879 				break;
1880 		}
1881 		if (!level)
1882 			break;
1883 
1884 		/*
1885 		 * Mask the RDT entry for level-triggered interrupts.
1886 		 */
1887 		irqp->airq_rdt_entry |= AV_MASK;
1888 		rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1889 		    intin_no);
1890 		if ((masked = (rdt_entry & AV_MASK)) == 0) {
1891 			/* Mask it */
1892 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no,
1893 			    AV_MASK | rdt_entry);
1894 		}
1895 
1896 		/*
1897 		 * If there was a race and an interrupt was injected
1898 		 * just before we masked, check for that case here.
1899 		 * Then, unmask the RDT entry and try again.  If we're
1900 		 * on our last try, don't unmask (because we want the
1901 		 * RDT entry to remain masked for the rest of the
1902 		 * function).
1903 		 */
1904 		rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1905 		    intin_no);
1906 		if ((masked == 0) && ((rdt_entry & AV_PENDING) != 0) &&
1907 		    (repeats < apic_max_reps_clear_pending)) {
1908 			/* Unmask it */
1909 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1910 			    intin_no, rdt_entry & ~AV_MASK);
1911 			irqp->airq_rdt_entry &= ~AV_MASK;
1912 		}
1913 	} while ((rdt_entry & AV_PENDING) &&
1914 	    (repeats < apic_max_reps_clear_pending));
1915 
1916 #ifdef DEBUG
1917 	if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) != 0)
1918 		apix_intr_deliver_timeouts++;
1919 #endif
1920 
1921 	if (!level || !APIX_IS_MASK_RDT(apix_mul_ioapic_method))
1922 		goto done;
1923 
1924 	/*
1925 	 * wait for remote IRR to be cleared for level-triggered
1926 	 * interrupts
1927 	 */
1928 	repeats = 0;
1929 	do {
1930 		repeats++;
1931 
1932 		for (waited = 0; waited < apic_max_reps_clear_pending;
1933 		    waited++) {
1934 			if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR)
1935 			    == 0)
1936 				break;
1937 		}
1938 
1939 		if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1940 			lock_clear(&apic_ioapic_lock);
1941 			intr_restore(iflag);
1942 
1943 			delay(APIX_CHECK_IRR_DELAY);
1944 
1945 			iflag = intr_clear();
1946 			lock_set(&apic_ioapic_lock);
1947 		}
1948 	} while (repeats < apix_max_reps_irr_pending);
1949 
1950 	if (repeats >= apix_max_reps_irr_pending) {
1951 #ifdef DEBUG
1952 		apix_intr_rirr_timeouts++;
1953 #endif
1954 
1955 		/*
1956 		 * If we waited and the Remote IRR bit is still not cleared,
1957 		 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
1958 		 * times for this interrupt, try the last-ditch workaround:
1959 		 */
1960 		if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1961 			/*
1962 			 * Trying to clear the bit through normal
1963 			 * channels has failed.  So as a last-ditch
1964 			 * effort, try to set the trigger mode to
1965 			 * edge, then to level.  This has been
1966 			 * observed to work on many systems.
1967 			 */
1968 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1969 			    intin_no,
1970 			    READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1971 			    intin_no) & ~AV_LEVEL);
1972 			WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1973 			    intin_no,
1974 			    READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1975 			    intin_no) | AV_LEVEL);
1976 		}
1977 
1978 		if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1979 #ifdef DEBUG
1980 			apix_intr_rirr_reset_failure++;
1981 #endif
1982 			lock_clear(&apic_ioapic_lock);
1983 			intr_restore(iflag);
1984 			prom_printf("apix: Remote IRR still "
1985 			    "not clear for IOAPIC %d intin %d.\n"
1986 			    "\tInterrupts to this pin may cease "
1987 			    "functioning.\n", ioapic_ix, intin_no);
1988 			return (1);	/* return failure */
1989 		}
1990 	}
1991 
1992 done:
1993 	/* change apic_irq_table */
1994 	lock_clear(&apic_ioapic_lock);
1995 	intr_restore(iflag);
1996 	apix_intx_set_vector(irqno, cpuid, vector);
1997 	iflag = intr_clear();
1998 	lock_set(&apic_ioapic_lock);
1999 
2000 	/* reprogramme IO-APIC RDT entry */
2001 	apix_intx_enable(irqno);
2002 
2003 	lock_clear(&apic_ioapic_lock);
2004 	intr_restore(iflag);
2005 
2006 	return (0);
2007 }
2008 
2009 static int
apix_intx_get_pending(int irqno)2010 apix_intx_get_pending(int irqno)
2011 {
2012 	apic_irq_t *irqp;
2013 	int intin, ioapicindex, pending;
2014 	ulong_t iflag;
2015 
2016 	mutex_enter(&airq_mutex);
2017 	irqp = apic_irq_table[irqno];
2018 	if (IS_IRQ_FREE(irqp)) {
2019 		mutex_exit(&airq_mutex);
2020 		return (0);
2021 	}
2022 
2023 	/* check IO-APIC delivery status */
2024 	intin = irqp->airq_intin_no;
2025 	ioapicindex = irqp->airq_ioapicindex;
2026 	mutex_exit(&airq_mutex);
2027 
2028 	iflag = intr_clear();
2029 	lock_set(&apic_ioapic_lock);
2030 
2031 	pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin) &
2032 	    AV_PENDING) ? 1 : 0;
2033 
2034 	lock_clear(&apic_ioapic_lock);
2035 	intr_restore(iflag);
2036 
2037 	return (pending);
2038 }
2039 
2040 /*
2041  * This function will mask the interrupt on the I/O APIC
2042  */
2043 static void
apix_intx_set_mask(int irqno)2044 apix_intx_set_mask(int irqno)
2045 {
2046 	int intin, ioapixindex, rdt_entry;
2047 	ulong_t iflag;
2048 	apic_irq_t *irqp;
2049 
2050 	mutex_enter(&airq_mutex);
2051 	irqp = apic_irq_table[irqno];
2052 
2053 	ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2054 
2055 	intin = irqp->airq_intin_no;
2056 	ioapixindex = irqp->airq_ioapicindex;
2057 	mutex_exit(&airq_mutex);
2058 
2059 	iflag = intr_clear();
2060 	lock_set(&apic_ioapic_lock);
2061 
2062 	rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2063 
2064 	/* clear mask */
2065 	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2066 	    (AV_MASK | rdt_entry));
2067 
2068 	lock_clear(&apic_ioapic_lock);
2069 	intr_restore(iflag);
2070 }
2071 
2072 /*
2073  * This function will clear the mask for the interrupt on the I/O APIC
2074  */
2075 static void
apix_intx_clear_mask(int irqno)2076 apix_intx_clear_mask(int irqno)
2077 {
2078 	int intin, ioapixindex, rdt_entry;
2079 	ulong_t iflag;
2080 	apic_irq_t *irqp;
2081 
2082 	mutex_enter(&airq_mutex);
2083 	irqp = apic_irq_table[irqno];
2084 
2085 	ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2086 
2087 	intin = irqp->airq_intin_no;
2088 	ioapixindex = irqp->airq_ioapicindex;
2089 	mutex_exit(&airq_mutex);
2090 
2091 	iflag = intr_clear();
2092 	lock_set(&apic_ioapic_lock);
2093 
2094 	rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2095 
2096 	/* clear mask */
2097 	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2098 	    ((~AV_MASK) & rdt_entry));
2099 
2100 	lock_clear(&apic_ioapic_lock);
2101 	intr_restore(iflag);
2102 }
2103 
2104 /*
2105  * For level-triggered interrupt, mask the IRQ line. Mask means
2106  * new interrupts will not be delivered. The interrupt already
2107  * accepted by a local APIC is not affected
2108  */
2109 void
apix_level_intr_pre_eoi(int irq)2110 apix_level_intr_pre_eoi(int irq)
2111 {
2112 	apic_irq_t *irqp = apic_irq_table[irq];
2113 	int apic_ix, intin_ix;
2114 
2115 	if (irqp == NULL)
2116 		return;
2117 
2118 	ASSERT(apic_level_intr[irq] == TRIGGER_MODE_LEVEL);
2119 
2120 	lock_set(&apic_ioapic_lock);
2121 
2122 	intin_ix = irqp->airq_intin_no;
2123 	apic_ix = irqp->airq_ioapicindex;
2124 
2125 	if (irqp->airq_cpu != CPU->cpu_id) {
2126 		if (!APIX_IS_MASK_RDT(apix_mul_ioapic_method))
2127 			ioapic_write_eoi(apic_ix, irqp->airq_vector);
2128 		lock_clear(&apic_ioapic_lock);
2129 		return;
2130 	}
2131 
2132 	if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) {
2133 		/*
2134 		 * This is a IOxAPIC and there is EOI register:
2135 		 *	Change the vector to reserved unused vector, so that
2136 		 *	the EOI	from Local APIC won't clear the Remote IRR for
2137 		 *	this level trigger interrupt. Instead, we'll manually
2138 		 *	clear it in apix_post_hardint() after ISR handling.
2139 		 */
2140 		WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2141 		    (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR);
2142 	} else {
2143 		WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2144 		    AV_MASK | irqp->airq_rdt_entry);
2145 	}
2146 
2147 	lock_clear(&apic_ioapic_lock);
2148 }
2149 
2150 /*
2151  * For level-triggered interrupt, unmask the IRQ line
2152  * or restore the original vector number.
2153  */
2154 void
apix_level_intr_post_dispatch(int irq)2155 apix_level_intr_post_dispatch(int irq)
2156 {
2157 	apic_irq_t *irqp = apic_irq_table[irq];
2158 	int apic_ix, intin_ix;
2159 
2160 	if (irqp == NULL)
2161 		return;
2162 
2163 	lock_set(&apic_ioapic_lock);
2164 
2165 	intin_ix = irqp->airq_intin_no;
2166 	apic_ix = irqp->airq_ioapicindex;
2167 
2168 	if (APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method)) {
2169 		/*
2170 		 * Already sent EOI back to Local APIC.
2171 		 * Send EOI to IO-APIC
2172 		 */
2173 		ioapic_write_eoi(apic_ix, irqp->airq_vector);
2174 	} else {
2175 		/* clear the mask or restore the vector */
2176 		WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2177 		    irqp->airq_rdt_entry);
2178 
2179 		/* send EOI to IOxAPIC */
2180 		if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC)
2181 			ioapic_write_eoi(apic_ix, irqp->airq_vector);
2182 	}
2183 
2184 	lock_clear(&apic_ioapic_lock);
2185 }
2186 
2187 static int
apix_intx_get_shared(int irqno)2188 apix_intx_get_shared(int irqno)
2189 {
2190 	apic_irq_t *irqp;
2191 	int share;
2192 
2193 	mutex_enter(&airq_mutex);
2194 	irqp = apic_irq_table[irqno];
2195 	if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
2196 		mutex_exit(&airq_mutex);
2197 		return (0);
2198 	}
2199 	share = irqp->airq_share;
2200 	mutex_exit(&airq_mutex);
2201 
2202 	return (share);
2203 }
2204 
2205 static void
apix_intx_set_shared(int irqno,int delta)2206 apix_intx_set_shared(int irqno, int delta)
2207 {
2208 	apic_irq_t *irqp;
2209 
2210 	mutex_enter(&airq_mutex);
2211 	irqp = apic_irq_table[irqno];
2212 	if (IS_IRQ_FREE(irqp)) {
2213 		mutex_exit(&airq_mutex);
2214 		return;
2215 	}
2216 	irqp->airq_share += delta;
2217 	mutex_exit(&airq_mutex);
2218 }
2219 
2220 /*
2221  * Setup IRQ table. Return IRQ no or -1 on failure
2222  */
2223 static int
apix_intx_setup(dev_info_t * dip,int inum,int irqno,struct apic_io_intr * intrp,struct intrspec * ispec,iflag_t * iflagp)2224 apix_intx_setup(dev_info_t *dip, int inum, int irqno,
2225     struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *iflagp)
2226 {
2227 	int origirq = ispec->intrspec_vec;
2228 	int newirq;
2229 	short intr_index;
2230 	uchar_t ipin, ioapic, ioapicindex;
2231 	apic_irq_t *irqp;
2232 
2233 	UNREFERENCED_1PARAMETER(inum);
2234 
2235 	if (intrp != NULL) {
2236 		intr_index = (short)(intrp - apic_io_intrp);
2237 		ioapic = intrp->intr_destid;
2238 		ipin = intrp->intr_destintin;
2239 
2240 		/* Find ioapicindex. If destid was ALL, we will exit with 0. */
2241 		for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--)
2242 			if (apic_io_id[ioapicindex] == ioapic)
2243 				break;
2244 		ASSERT((ioapic == apic_io_id[ioapicindex]) ||
2245 		    (ioapic == INTR_ALL_APIC));
2246 
2247 		/* check whether this intin# has been used by another irqno */
2248 		if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1)
2249 			return (newirq);
2250 
2251 	} else if (iflagp != NULL) {	/* ACPI */
2252 		intr_index = ACPI_INDEX;
2253 		ioapicindex = acpi_find_ioapic(irqno);
2254 		ASSERT(ioapicindex != 0xFF);
2255 		ioapic = apic_io_id[ioapicindex];
2256 		ipin = irqno - apic_io_vectbase[ioapicindex];
2257 
2258 		if (apic_irq_table[irqno] &&
2259 		    apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) {
2260 			ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin &&
2261 			    apic_irq_table[irqno]->airq_ioapicindex ==
2262 			    ioapicindex);
2263 			return (irqno);
2264 		}
2265 
2266 	} else {	/* default configuration */
2267 		intr_index = DEFAULT_INDEX;
2268 		ioapicindex = 0;
2269 		ioapic = apic_io_id[ioapicindex];
2270 		ipin = (uchar_t)irqno;
2271 	}
2272 
2273 	/* allocate a new IRQ no */
2274 	if ((irqp = apic_irq_table[irqno]) == NULL) {
2275 		irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP);
2276 		apic_irq_table[irqno] = irqp;
2277 	} else {
2278 		if (irqp->airq_mps_intr_index != FREE_INDEX) {
2279 			newirq = apic_allocate_irq(apic_first_avail_irq);
2280 			if (newirq == -1) {
2281 				return (-1);
2282 			}
2283 			irqno = newirq;
2284 			irqp = apic_irq_table[irqno];
2285 			ASSERT(irqp != NULL);
2286 		}
2287 	}
2288 	apic_max_device_irq = max(irqno, apic_max_device_irq);
2289 	apic_min_device_irq = min(irqno, apic_min_device_irq);
2290 
2291 	irqp->airq_mps_intr_index = intr_index;
2292 	irqp->airq_ioapicindex = ioapicindex;
2293 	irqp->airq_intin_no = ipin;
2294 	irqp->airq_dip = dip;
2295 	irqp->airq_origirq = (uchar_t)origirq;
2296 	if (iflagp != NULL)
2297 		irqp->airq_iflag = *iflagp;
2298 	irqp->airq_cpu = IRQ_UNINIT;
2299 	irqp->airq_vector = 0;
2300 
2301 	return (irqno);
2302 }
2303 
2304 /*
2305  * Setup IRQ table for non-pci devices. Return IRQ no or -1 on error
2306  */
2307 static int
apix_intx_setup_nonpci(dev_info_t * dip,int inum,int bustype,struct intrspec * ispec)2308 apix_intx_setup_nonpci(dev_info_t *dip, int inum, int bustype,
2309     struct intrspec *ispec)
2310 {
2311 	int irqno = ispec->intrspec_vec;
2312 	int newirq, i;
2313 	iflag_t intr_flag;
2314 	ACPI_SUBTABLE_HEADER	*hp;
2315 	ACPI_MADT_INTERRUPT_OVERRIDE *isop;
2316 	struct apic_io_intr *intrp;
2317 
2318 	if (!apic_enable_acpi || apic_use_acpi_madt_only) {
2319 		int busid;
2320 
2321 		if (bustype == 0)
2322 			bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA;
2323 
2324 		/* loop checking BUS_ISA/BUS_EISA */
2325 		for (i = 0; i < 2; i++) {
2326 			if (((busid = apic_find_bus_id(bustype)) != -1) &&
2327 			    ((intrp = apic_find_io_intr_w_busid(irqno, busid))
2328 			    != NULL)) {
2329 				return (apix_intx_setup(dip, inum, irqno,
2330 				    intrp, ispec, NULL));
2331 			}
2332 			bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA;
2333 		}
2334 
2335 		/* fall back to default configuration */
2336 		return (-1);
2337 	}
2338 
2339 	/* search iso entries first */
2340 	if (acpi_iso_cnt != 0) {
2341 		hp = (ACPI_SUBTABLE_HEADER *)acpi_isop;
2342 		i = 0;
2343 		while (i < acpi_iso_cnt) {
2344 			if (hp->Type == ACPI_MADT_TYPE_INTERRUPT_OVERRIDE) {
2345 				isop = (ACPI_MADT_INTERRUPT_OVERRIDE *) hp;
2346 				if (isop->Bus == 0 &&
2347 				    isop->SourceIrq == irqno) {
2348 					newirq = isop->GlobalIrq;
2349 					intr_flag.intr_po = isop->IntiFlags &
2350 					    ACPI_MADT_POLARITY_MASK;
2351 					intr_flag.intr_el = (isop->IntiFlags &
2352 					    ACPI_MADT_TRIGGER_MASK) >> 2;
2353 					intr_flag.bustype = BUS_ISA;
2354 
2355 					return (apix_intx_setup(dip, inum,
2356 					    newirq, NULL, ispec, &intr_flag));
2357 				}
2358 				i++;
2359 			}
2360 			hp = (ACPI_SUBTABLE_HEADER *)(((char *)hp) +
2361 			    hp->Length);
2362 		}
2363 	}
2364 	intr_flag.intr_po = INTR_PO_ACTIVE_HIGH;
2365 	intr_flag.intr_el = INTR_EL_EDGE;
2366 	intr_flag.bustype = BUS_ISA;
2367 	return (apix_intx_setup(dip, inum, irqno, NULL, ispec, &intr_flag));
2368 }
2369 
2370 
2371 /*
2372  * Setup IRQ table for pci devices. Return IRQ no or -1 on error
2373  */
2374 static int
apix_intx_setup_pci(dev_info_t * dip,int inum,int bustype,struct intrspec * ispec)2375 apix_intx_setup_pci(dev_info_t *dip, int inum, int bustype,
2376     struct intrspec *ispec)
2377 {
2378 	int busid, devid, pci_irq;
2379 	ddi_acc_handle_t cfg_handle;
2380 	uchar_t ipin;
2381 	iflag_t intr_flag;
2382 	struct apic_io_intr *intrp;
2383 
2384 	if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0)
2385 		return (-1);
2386 
2387 	if (busid == 0 && apic_pci_bus_total == 1)
2388 		busid = (int)apic_single_pci_busid;
2389 
2390 	if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS)
2391 		return (-1);
2392 	ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA;
2393 	pci_config_teardown(&cfg_handle);
2394 
2395 	if (apic_enable_acpi && !apic_use_acpi_madt_only) {	/* ACPI */
2396 		if (apic_acpi_translate_pci_irq(dip, busid, devid,
2397 		    ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS)
2398 			return (-1);
2399 
2400 		intr_flag.bustype = (uchar_t)bustype;
2401 		return (apix_intx_setup(dip, inum, pci_irq, NULL, ispec,
2402 		    &intr_flag));
2403 	}
2404 
2405 	/* MP configuration table */
2406 	pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3);
2407 	if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) == NULL) {
2408 		pci_irq = apic_handle_pci_pci_bridge(dip, devid, ipin, &intrp);
2409 		if (pci_irq == -1)
2410 			return (-1);
2411 	}
2412 
2413 	return (apix_intx_setup(dip, inum, pci_irq, intrp, ispec, NULL));
2414 }
2415 
2416 /*
2417  * Translate and return IRQ no
2418  */
2419 static int
apix_intx_xlate_irq(dev_info_t * dip,int inum,struct intrspec * ispec)2420 apix_intx_xlate_irq(dev_info_t *dip, int inum, struct intrspec *ispec)
2421 {
2422 	int newirq, irqno = ispec->intrspec_vec;
2423 	int parent_is_pci_or_pciex = 0, child_is_pciex = 0;
2424 	int bustype = 0, dev_len;
2425 	char dev_type[16];
2426 
2427 	if (apic_defconf) {
2428 		mutex_enter(&airq_mutex);
2429 		goto defconf;
2430 	}
2431 
2432 	if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) {
2433 		mutex_enter(&airq_mutex);
2434 		goto nonpci;
2435 	}
2436 
2437 	/*
2438 	 * use ddi_getlongprop_buf() instead of ddi_prop_lookup_string()
2439 	 * to avoid extra buffer allocation.
2440 	 */
2441 	dev_len = sizeof (dev_type);
2442 	if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip),
2443 	    DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
2444 	    &dev_len) == DDI_PROP_SUCCESS) {
2445 		if ((strcmp(dev_type, "pci") == 0) ||
2446 		    (strcmp(dev_type, "pciex") == 0))
2447 			parent_is_pci_or_pciex = 1;
2448 	}
2449 
2450 	if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip,
2451 	    DDI_PROP_DONTPASS, "compatible", (caddr_t)dev_type,
2452 	    &dev_len) == DDI_PROP_SUCCESS) {
2453 		if (strstr(dev_type, "pciex"))
2454 			child_is_pciex = 1;
2455 	}
2456 
2457 	mutex_enter(&airq_mutex);
2458 
2459 	if (parent_is_pci_or_pciex) {
2460 		bustype = child_is_pciex ? BUS_PCIE : BUS_PCI;
2461 		newirq = apix_intx_setup_pci(dip, inum, bustype, ispec);
2462 		if (newirq != -1)
2463 			goto done;
2464 		bustype = 0;
2465 	} else if (strcmp(dev_type, "isa") == 0)
2466 		bustype = BUS_ISA;
2467 	else if (strcmp(dev_type, "eisa") == 0)
2468 		bustype = BUS_EISA;
2469 
2470 nonpci:
2471 	newirq = apix_intx_setup_nonpci(dip, inum, bustype, ispec);
2472 	if (newirq != -1)
2473 		goto done;
2474 
2475 defconf:
2476 	newirq = apix_intx_setup(dip, inum, irqno, NULL, ispec, NULL);
2477 	if (newirq == -1) {
2478 		mutex_exit(&airq_mutex);
2479 		return (-1);
2480 	}
2481 done:
2482 	ASSERT(apic_irq_table[newirq]);
2483 	mutex_exit(&airq_mutex);
2484 	return (newirq);
2485 }
2486 
2487 static int
apix_intx_alloc_vector(dev_info_t * dip,int inum,struct intrspec * ispec)2488 apix_intx_alloc_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2489 {
2490 	int irqno;
2491 	apix_vector_t *vecp;
2492 
2493 	if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2494 		return (0);
2495 
2496 	if ((vecp = apix_alloc_intx(dip, inum, irqno)) == NULL)
2497 		return (0);
2498 
2499 	DDI_INTR_IMPLDBG((CE_CONT, "apix_intx_alloc_vector: dip=0x%p name=%s "
2500 	    "irqno=0x%x cpuid=%d vector=0x%x\n",
2501 	    (void *)dip, ddi_driver_name(dip), irqno,
2502 	    vecp->v_cpuid, vecp->v_vector));
2503 
2504 	return (1);
2505 }
2506 
2507 /*
2508  * Return the vector number if the translated IRQ for this device
2509  * has a vector mapping setup. If no IRQ setup exists or no vector is
2510  * allocated to it then return 0.
2511  */
2512 static apix_vector_t *
apix_intx_xlate_vector(dev_info_t * dip,int inum,struct intrspec * ispec)2513 apix_intx_xlate_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2514 {
2515 	int irqno;
2516 	apix_vector_t *vecp;
2517 
2518 	/* get the IRQ number */
2519 	if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2520 		return (NULL);
2521 
2522 	/* get the vector number if a vector is allocated to this irqno */
2523 	vecp = apix_intx_get_vector(irqno);
2524 
2525 	return (vecp);
2526 }
2527 
2528 /*
2529  * Switch between safe and x2APIC IPI sending method.
2530  * The CPU may power on in xapic mode or x2apic mode. If the CPU needs to send
2531  * an IPI to other CPUs before entering x2APIC mode, it still needs to use the
2532  * xAPIC method. Before sending a StartIPI to the target CPU, psm_send_ipi will
2533  * be changed to apic_common_send_ipi, which detects current local APIC mode and
2534  * use the right method to send an IPI. If some CPUs fail to start up,
2535  * apic_poweron_cnt won't return to zero, so apic_common_send_ipi will always be
2536  * used. psm_send_ipi can't be simply changed back to x2apic_send_ipi if some
2537  * CPUs failed to start up because those failed CPUs may recover itself later at
2538  * unpredictable time.
2539  */
2540 void
apic_switch_ipi_callback(boolean_t enter)2541 apic_switch_ipi_callback(boolean_t enter)
2542 {
2543 	ulong_t iflag;
2544 	struct psm_ops *pops = psmops;
2545 
2546 	iflag = intr_clear();
2547 	lock_set(&apic_mode_switch_lock);
2548 	if (enter) {
2549 		ASSERT(apic_poweron_cnt >= 0);
2550 		if (apic_poweron_cnt == 0) {
2551 			pops->psm_send_ipi = apic_common_send_ipi;
2552 			send_dirintf = pops->psm_send_ipi;
2553 			pops->psm_send_pir_ipi = apic_common_send_pir_ipi;
2554 			psm_send_pir_ipi = pops->psm_send_pir_ipi;
2555 		}
2556 		apic_poweron_cnt++;
2557 	} else {
2558 		ASSERT(apic_poweron_cnt > 0);
2559 		apic_poweron_cnt--;
2560 		if (apic_poweron_cnt == 0) {
2561 			pops->psm_send_ipi = x2apic_send_ipi;
2562 			send_dirintf = pops->psm_send_ipi;
2563 			pops->psm_send_pir_ipi = x2apic_send_pir_ipi;
2564 			psm_send_pir_ipi = pops->psm_send_pir_ipi;
2565 		}
2566 	}
2567 	lock_clear(&apic_mode_switch_lock);
2568 	intr_restore(iflag);
2569 }
2570 
2571 /* stub function */
2572 int
apix_loaded(void)2573 apix_loaded(void)
2574 {
2575 	return (apix_is_enabled);
2576 }
2577